E2E @ su/alter - manual dispatch #185

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shrikanthup wants to merge 2 commits from refs/pull/185/head into main

pull from: refs/pull/185/head

merge into: NoIndexTests:main

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Conversation 2 Commits 2 Changes 7 +504 -81

shrikanthup commented 2026-05-15 21:43:29 +00:00 (Migrated from staging.allspice.dev)

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Source: manual dispatch
Ref: su/alternate-formats
Mode: e2e
Cache: enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache)
Cleanup: auto-closed after 7 days

Resolved config

{
  "dump_analysis_dir": "debug_dump",
  "libraries": [
    {
      "ipn_column": "IPN",
      "mpn_column": "MPN",
      "path": ".allspice/library.csv",
      "type": "csv"
    },
    {
      "digikey_client_id_env": "DIGIKEY_CLIENT_ID",
      "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET",
      "type": "digikey"
    }
  ]
}

Triggered at 2026-05-15T21:43:26.496802Z. Branch 4e527de7 will be deleted on cleanup.

**Source:** manual dispatch **Ref:** [`su/alternate-formats`](https://github.com/AllSpiceIO/connections-checker/tree/su/alternate-formats) **Mode:** e2e **Cache:** enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache) **Cleanup:** auto-closed after 7 days <details> <summary>Resolved config</summary> ```json { "dump_analysis_dir": "debug_dump", "libraries": [ { "ipn_column": "IPN", "mpn_column": "MPN", "path": ".allspice/library.csv", "type": "csv" }, { "digikey_client_id_env": "DIGIKEY_CLIENT_ID", "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET", "type": "digikey" } ] } ``` </details> Triggered at 2026-05-15T21:43:26.496802Z. Branch `4e527de7` will be deleted on cleanup.

AllSpiceAlice commented 2026-05-15 21:50:36 +00:00 (Migrated from staging.allspice.dev)

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DRCY has reviewed this Design Review, and there should be a review posted below.

DRCY has reviewed this Design Review, and there should be a review posted below.

AllSpiceAlice (Migrated from staging.allspice.dev) reviewed 2026-05-16 00:04:44 +00:00

AllSpiceAlice (Migrated from staging.allspice.dev) left a comment

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DRCY Connections Checker Review

DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 448 component(s) to review, and found 12 potential issue(s) in 12 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
AK12	DDI0_RCOMP_P	DDI_RCOMP_N	❌	DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P, positive) is connected to DDI_RCOMP_N net, and pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅, negative) is connected to DDI_RCOMP_P net. These connections should be reversed. Pin AK12 is named DDI0_RCOMP_P (positive) in the datasheet (from datasheet 140-0004628) Pin AK13 is named DDI_RCOMP_N (negative) in the datasheet, shown with overline in schematic as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (from datasheet 140-0004628) Pin AK12 connects to net DDI_RCOMP_N in the schematic (from schematic) Pin AK13 connects to net DDI_RCOMP_P in the schematic (from schematic) Compensation resistor R217 (402 ohms) connects between DDI_RCOMP_N and DDI_RCOMP_P nets (from schematic) For differential compensation resistors, the positive pin should connect to the positive side and negative pin to the negative side (reasoning) The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning) The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning) The pins are swapped and should be corrected: AK12 should connect to DDI_RCOMP_P and AK13 should connect to DDI_RCOMP_N (reasoning)
AK13	~DDI0_RCOMP	DDI_RCOMP_P	❌	DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P, positive) is connected to DDI_RCOMP_N net, and pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅, negative) is connected to DDI_RCOMP_P net. These connections should be reversed. Pin AK12 is named DDI0_RCOMP_P (positive) in the datasheet (from datasheet 140-0004628) Pin AK13 is named DDI_RCOMP_N (negative) in the datasheet, shown with overline in schematic as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (from datasheet 140-0004628) Pin AK12 connects to net DDI_RCOMP_N in the schematic (from schematic) Pin AK13 connects to net DDI_RCOMP_P in the schematic (from schematic) Compensation resistor R217 (402 ohms) connects between DDI_RCOMP_N and DDI_RCOMP_P nets (from schematic) For differential compensation resistors, the positive pin should connect to the positive side and negative pin to the negative side (reasoning) The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning) The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning) The pins are swapped and should be corrected: AK12 should connect to DDI_RCOMP_P and AK13 should connect to DDI_RCOMP_N (reasoning)
A29	RESERVED_A29	GPIO_NC13	✅	RESERVED_A29 pin connected to GPIO_NC13 net with 10K pull-down resistor R102 to ground. This configuration is correct for an unused/reserved GPIO pin.
B26	DDI0_BKLTCTL		✅	DDI0 control pins (BKLTCTL, VDDEN, BKLTEN) are unconnected. This may be acceptable if backlight and panel power control are handled externally or not needed for HDMI.
B28	DDI0_VDDEN		✅	DDI0 control pins (BKLTCTL, VDDEN, BKLTEN) are unconnected. This may be acceptable if backlight and panel power control are handled externally or not needed for HDMI.
C27	DDI0_BKLTEN		✅	DDI0 control pins (BKLTCTL, VDDEN, BKLTEN) are unconnected. This may be acceptable if backlight and panel power control are handled externally or not needed for HDMI.
B30	GPIO_S0_NC12	$3N566	✅	GPIO_S0_NC12 pin connected to test point TP15 (DNI). This is correct for a test point on a GPIO pin.
C26	DDI0_DDCDATA	HDMI_DDCDAT	✅	DDI0 DDC pins (DDCDATA, DDCCLK) connected to HDMI DDC signals (HDMI_DDCDAT, HDMI_DDCCLK). This is correct for HDMI DDC/EDID communication.
C28	DDI0_DDCCLK	HDMI_DDCCLK	✅	DDI0 DDC pins (DDCDATA, DDCCLK) connected to HDMI DDC signals (HDMI_DDCDAT, HDMI_DDCCLK). This is correct for HDMI DDC/EDID communication.
D27	DDI0_HPD	HDMI_HPD_B	✅	DDI0_HPD pin connected to HDMI_HPD_B (inverted hot plug detect signal from U39). This is correct.
G30	DDI1_DDCCLK	GND	✅	DDI1 control pins. DDCCLK and HPD are tied to ground, DDCDATA has 2.2K pull-down through R257. This correctly disables the DDI1 interface.
K30	DDI1_HPD	GND	✅	DDI1 control pins. DDCCLK and HPD are tied to ground, DDCDATA has 2.2K pull-down through R257. This correctly disables the DDI1 interface.
P30	DDI1_DDCDATA	DDI1_DDCDAT	✅	DDI1 control pins. DDCCLK and HPD are tied to ground, DDCDATA has 2.2K pull-down through R257. This correctly disables the DDI1 interface.
J30	DDI1_BKLTEN		✅	DDI1 control pins (BKLTEN, BKLTCTL, VDDEN) are unconnected. This is correct as DDI1 interface is disabled.
M30	DDI1_BKLTCTL		✅	DDI1 control pins (BKLTEN, BKLTCTL, VDDEN) are unconnected. This is correct as DDI1 interface is disabled.
N30	DDI1_VDDEN		✅	DDI1 control pins (BKLTEN, BKLTCTL, VDDEN) are unconnected. This is correct as DDI1 interface is disabled.
P14	RESERVED_P14	MCSI_RCOMP	✅	MCSI_RCOMP pin connected through 150-ohm resistor R213 to ground. This provides compensation for the MIPI camera interface and is correct.
AB2	RESERVED_AB2		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AB3	RESERVED_AB3		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AB7	RESERVED_AB7		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AB9	RESERVED_AB9		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AB12	RESERVED_AB12		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AB13	RESERVED_AB13		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AB14	RESERVED_AB14		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AD4	RESERVED_AD4		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AD6	RESERVED_AD6		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AF13	RESERVED_AF13		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AF14	RESERVED_AF14		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AH13	RESERVED_AH13		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AH14	RESERVED_AH14		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AM13	RESERVED_AM13		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AM14	RESERVED_AM14		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
C29	RESERVED_C29		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
C30	RESERVED_C30		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
D28	RESERVED_D28		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
D32	RESERVED_D32		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
D34	RESERVED_D34		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
F28	RESERVED_F28		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
F32	RESERVED_F32		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
F34	RESERVED_F34		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
J28	RESERVED_J28		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
J34	RESERVED_J34		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
K28	RESERVED_K28		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
K34	RESERVED_K34		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
M32	RESERVED_M32		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
N32	RESERVED_N32		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
R1	RESERVED_R1		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
R3	RESERVED_R3		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T2	RESERVED_T2		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T3	RESERVED_T3		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T4	RESERVED_T4		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T6	RESERVED_T6		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T7	RESERVED_T7		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T9	RESERVED_T9		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T10	RESERVED_T10		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T12	RESERVED_T12		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T13	RESERVED_T13		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
T14	RESERVED_T14		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V2	RESERVED_V2		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V3	RESERVED_V3		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V4	RESERVED_V4		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V6	RESERVED_V6		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V9	RESERVED_V9		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V10	RESERVED_V10		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V13	RESERVED_V13		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
V14	RESERVED_V14		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
W1	RESERVED_W1		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
W3	RESERVED_W3		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
Y2	RESERVED_Y2		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
Y3	RESERVED_Y3		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
Y4	RESERVED_Y4		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
Y6	RESERVED_Y6		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
Y12	RESERVED_Y12		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
Y13	RESERVED_Y13		✅	Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected.
AC1	DDI1_TXN_3		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AC3	DDI1_TXP_3		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AD2	DDI1_TXN_2		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AD3	DDI1_TXP_2		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AF2	DDI1_TXN_1		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AF3	DDI1_TXP_1		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AG1	DDI1_TXN_0		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AG3	DDI1_TXP_0		✅	DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'.
AH2	RESERVED_VSS3	$3N554	✅	Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct.
AH3	RESERVED_VSS2	$3N552	✅	Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct.
AM2	RESERVED_VSS1	$3N589	✅	Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct.
AM3	RESERVED_VSS0	$3N579	✅	Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct.
AK2	DDI1_AUXN		✅	DDI1 auxiliary pins (DDI1_AUXN, DDI1_AUXP) are left unconnected. This is correct as DDI1 interface is disabled.
AK3	DDI1_AUXP		✅	DDI1 auxiliary pins (DDI1_AUXN, DDI1_AUXP) are left unconnected. This is correct as DDI1 interface is disabled.
AL1	DDI0_AUXN		✅	DDI0 auxiliary pins (DDI0_AUXN, DDI0_AUXP) are left unconnected. This is acceptable as HDMI does not use auxiliary channel (used for DisplayPort).
AL3	DDI0_AUXP		✅	DDI0 auxiliary pins (DDI0_AUXN, DDI0_AUXP) are left unconnected. This is acceptable as HDMI does not use auxiliary channel (used for DisplayPort).
AP2	DDI0_TXN_3	HDMI_CLK_DN	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AP3	DDI0_TXP_3	HDMI_CLK_DP	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AR1	DDI0_TXN_2	HDMI_TX0_DN	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AR3	DDI0_TXP_2	HDMI_TX0_DP	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AT2	DDI0_TXP_1	HDMI_TX1_DP	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AT3	DDI0_TXN_1	HDMI_TX1_DN	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AV2	DDI0_TXN_0	HDMI_TX2_DN	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AV3	DDI0_TXP_0	HDMI_TX2_DP	✅	DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note.
AW1	VGA_IREF	$3N548	✅	VGA_IREF pin connected through 357-ohm resistor R40 to ground. This sets the VGA DAC reference current and is correct.
AY2	VGA_BLUE		✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.
AY3	VGA_IRTN	GND	✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.
BA1	VGA_GREEN		✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.
BA3	VGA_RED		✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.
BC1	VGA_DDCCLK	CRT_CLK	✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.
BC2	VGA_DDCDATA	CRT_DAT	✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.
BD2	VGA_HSYNC		✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.
BF2	VGA_VSYNC		✅	VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable.

U39 - SN74LVC1G14DCKR ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin is left unconnected in the schematic. This is acceptable per the datasheet which states the pin has no internal connection.
2	A	HDMI_HPD	✅	Input pin A is correctly connected to HDMI_HPD signal for Schmitt-trigger conditioning of the HDMI Hot Plug Detect signal.
3	GND	GND	✅	Ground pin is correctly connected to the GND net.
4	Y	HDMI_HPD_B	✅	Output pin Y is correctly connected to HDMI_HPD_B which drives the CPU's DDI0_HPD input, providing an inverted and conditioned HDMI Hot Plug Detect signal.
5	VCC	+V1P8S	✅	VCC power pin is correctly connected to +V1P8S (1.8V supply), which is within the specified 1.65V to 5.5V operating range. A 0.1uF bypass capacitor (C375) is present on this power rail.

R38 - 110-0002631 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_DAT	❌	Pin 1 connects to CRT_DAT (VGA_DDCDATA from CPU1 pin BC2), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation. Pin 1 is connected to net CRT_DAT (from schematic) Net CRT_DAT connects to CPU1 pin BC2, which is labeled VGA_DDCDATA (from schematic) Pin 2 connects to GND, creating a 150Ω pull-down configuration (from schematic) VGA_DDCDATA is the I2C SDA (data) line for the VGA Display Data Channel (DDC) interface (reasoning) DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground (reasoning) Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements (reasoning) A 150Ω pull-down resistor would pull the DDC data line low and prevent proper I2C communication by fighting against the required pull-up (reasoning) This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional (reasoning) The same issue affects R39 on the CRT_CLK line, indicating a systematic problem with the VGA DDC interface design (reasoning)
2	2	GND	❌	Connected to GND, creating a 150 ohm pull-down on the VGA DDC data line. This is incorrect for I2C/DDC operation which requires pull-up resistors. Pin 2 is connected to GND (from schematic) This creates a 150 ohm pull-down resistor on the VGA_DDCDATA signal (reasoning) I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors (reasoning) A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication (reasoning) This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled (reasoning)

R39 - 110-0002631 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_CLK	❌	Pin 1 connects to CRT_CLK (VGA_DDCCLK from CPU1 pin BC1), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation. Pin 1 is connected to net CRT_CLK (from schematic) Net CRT_CLK connects to CPU1 pin BC1, which is labeled VGA_DDCCLK (from schematic) Pin 2 connects to GND, creating a 150Ω pull-down configuration (from schematic) VGA_DDCCLK is the I2C SCL (clock) line for the VGA Display Data Channel (DDC) interface (reasoning) DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground (reasoning) Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements (reasoning) A 150Ω pull-down resistor would pull the DDC clock line low and prevent proper I2C communication by fighting against the required pull-up (reasoning) This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional (reasoning) The same issue affects R38 on the CRT_DAT line, indicating a systematic problem with the VGA DDC interface design (reasoning)
2	2	GND	❌	Connected to GND, creating a 150 ohm pull-down on the VGA DDC clock line. This is incorrect for I2C/DDC operation which requires pull-up resistors. Pin 2 is connected to GND (from schematic) This creates a 150 ohm pull-down resistor on the VGA_DDCCLK signal (reasoning) I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors (reasoning) A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication (reasoning) This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled (reasoning)

R213 - 110-0002631 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCSI_RCOMP	✅	Connected to MCSI_RCOMP net, which connects to CPU1 pin P14 (marked as RESERVED_P14 but used for MCSI compensation on Bay Trail-I variant).
2	2	GND	✅	Connected to GND, forming a compensation resistor configuration where MCSI_RCOMP is terminated to ground through 150 ohms.

R217 - 110-0004476 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI_RCOMP_N	✅	402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming a compensation resistor for the DDI0 interface. The net naming appears swapped relative to CPU pin naming conventions, but this does not affect electrical functionality.
2	2	DDI_RCOMP_P	✅	402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming a compensation resistor for the DDI0 interface. The net naming appears swapped relative to CPU pin naming conventions, but this does not affect electrical functionality.

R46 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$3N552	✅	Pin 1 connects to CPU1 pin AH3 (RESERVED_VSS2) through net $3N552. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor.
2	2	GND	✅	Pin 2 connects to GND, completing the connection from CPU1 RESERVED_VSS2 pin to ground.

R43 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$3N554	✅	Pin 1 connects to CPU1 pin AH2 (RESERVED_VSS3) through net $3N554. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor.
2	2	GND	✅	Pin 2 connects to GND, completing the connection from CPU1 RESERVED_VSS3 pin to ground.

R42 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This is one side of a 0-ohm resistor connecting CPU1 RESERVED_VSS0 pin to ground.
2	2	$3N579	✅	Pin 2 connects to CPU1 pin AM3 (RESERVED_VSS0) through net $3N579. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor.

R41 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This is one side of a 0-ohm resistor connecting CPU1 RESERVED_VSS1 pin to ground.
2	2	$3N589	✅	Pin 2 connects to CPU1 pin AM2 (RESERVED_VSS1) through net $3N589. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor.

R102 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	10K ohm pull-down resistor on GPIO_NC13 (CPU1 pin A29). Provides a defined logic low level for this reserved GPIO pin.
2	2	GPIO_NC13	✅	10K ohm pull-down resistor on GPIO_NC13 (CPU1 pin A29). Provides a defined logic low level for this reserved GPIO pin.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
C24	~PROCHOT	VR_HOT_L	✅	PROCHOT# is connected with 73.2 ohm resistor R255 to +V1P0S for thermal management.
BA12	SATA_GP0	SATA_GP0	✅	SATA_GP0 is connected with 10K pull-down resistor R220 to ground.
BA16	SATA_RXN_1	SATA1_RXN	✅	SATA_RXN_1 is connected through AC coupling capacitor C177 from mSATA interface.
BA26	SD3_D3	SD3_D3	✅	SD3_D3 is connected to SD Card 3 data bit 3 signal.
BA30	LPE_I2S2_FRM	LPE_I2S_FRM	✅	LPE_I2S2_FRM is connected to I2S frame signal with 10K pull-up resistor R268.
BB5	RESERVED_VSS6	RESERVED_VSS6	✅	RESERVED_VSS6 pin is grounded through R72 as required for reserved VSS pins.
BB7	RESERVED_VSS7	RESERVED_VSS7	✅	RESERVED_VSS7 pin is grounded through R192 as required for reserved VSS pins.
BB10	RESERVED_VSS4	ICLK_SATA_TERMP	✅	RESERVED_VSS4 pin is connected to ICLK_SATA_TERMP and grounded through R73 for integrated clock SATA termination.
BC10	RESERVED_VSS5	ICLK_SATA_TERMN	✅	RESERVED_VSS5 pin is connected to ICLK_SATA_TERMN and grounded through R74 for integrated clock SATA termination.
BC12			✅	GPIO strapping pin with both pull-up and pull-down resistor options (both DNI), providing hardware configuration flexibility.
BC24	SD3_CD#	SD3_CD#	✅	SD3_CD# (card detect) and SD3_WP (write protect) are connected together through 0-ohm resistor R354. This is a Bay Trail-I specific configuration as indicated by schematic annotation, though it represents an unusual design choice that ties two functionally independent SD card signals together.
BD5	SD3_WP_BD5	SD3_WP	✅	SD3_CD# (card detect) and SD3_WP (write protect) are connected together through 0-ohm resistor R354. This is a Bay Trail-I specific configuration as indicated by schematic annotation, though it represents an unusual design choice that ties two functionally independent SD card signals together.
BC30	LPE_I2S2_DATAOUT	LPE_I2S_DATOUT	✅	LPE_I2S2_DATAOUT is connected to I2S data output with optional GPIO configuration.
BD7	~PCIE_CLKREQ_1	CLKREQ1_B	✅	PCIE_CLKREQ_1# is connected with 10K pull-up resistor R190 for PCIe clock request.
BD10	SATA_TXP1	SATA1_TXP	✅	SATA_TXP1 is connected through AC coupling capacitor C179 to mSATA interface.
BD22	~SD3_PWREN	/SD3+PWREN	✅	SD3_PWREN# is connected to power enable signal with test point TP11.
BD26	SD3_D1	SD3_D1	✅	SD3_D1 is connected to SD Card 3 data bit 1 signal.
BD28	LPE_I2S2_DATAIN	LPE_I2S_DATIN	✅	LPE_I2S2_DATAIN is connected to I2S data input signal.
BE3	~PCIE_CLKREQ_3	mPCIe_CLKREQ3_B	✅	PCIE_CLKREQ_3# is connected with 10K pull-up resistor R2 for mini PCIe clock request.
BF6	SATA_TXP_0	SATA0_TXP	✅	SATA_TXP_0 is connected through AC coupling capacitor C10 to SATA connector for SATA port 0 transmit.
BF10	SATA_TXN_1	SATA1_TXN	✅	SATA_TXN_1 is connected through AC coupling capacitor C180 to mSATA interface.
BF20	HDA_LPE_RCOMP	HDA_RCOMP	✅	HDA_LPE_RCOMP is connected with 49.9 ohm resistor R242 to ground for HD Audio compensation.
BF22	SD3_1P8EN	SD3_1P8EN	✅	SD3_1P8EN is connected to 1.8V enable signal with test point TP12.
BF26	SD3_RCOMP	SD3_RCOMP	✅	SD3_RCOMP is connected with 49.9 ohm resistor R258 to ground for SD Card compensation.
BF28	LPE_I2S2_CLK	LPE_I2S_CLK	✅	LPE_I2S2_CLK is connected to I2S clock signal.
BG3	~PCIE_CLKREQ_0	CLKREQ0_B	✅	PCIE_CLKREQ_0# is connected with 10K pull-up resistor R191 for PCIe clock request.
BG5	~PCIE_CLKREQ_2	LAN_CLKREQ2_B	✅	PCIE_CLKREQ_2# is connected with 10K pull-up resistor R71 for LAN PCIe clock request.
BG7	SATA_TXN_0	SATA0_TXN	✅	SATA_TXN_0 is connected through AC coupling capacitor C11 to SATA connector for SATA port 0 transmit.
BG18	GPIO_S0_SC_15		✅	GPIO_S0_SC_14 and GPIO_S0_SC_15 are unconnected GPIO pins.
BH18	GPIO_S0_SC_14		✅	GPIO_S0_SC_14 and GPIO_S0_SC_15 are unconnected GPIO pins.
BG19	HDA_SDI0		✅	HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design.
BG20	HDA_SDO		✅	HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design.
BG21	HDA_SDI1		✅	HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design.
BG22	~HDA_RST		✅	HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design.
BH20	HDA_SYNC		✅	HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design.
BJ21	HDA_CLK		✅	HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design.
AK7	RESERVED_AK7		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AK9	RESERVED_AK9		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AV10	RESERVED_AV10		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AV9	RESERVED_AV9		✅	Reserved pins are correctly left unconnected per datasheet requirements.
BB3	RESERVED_BB3		✅	Reserved pins are correctly left unconnected per datasheet requirements.
BB4	RESERVED_BB4		✅	Reserved pins are correctly left unconnected per datasheet requirements.
N34	RESERVED_N34		✅	Reserved pins are correctly left unconnected per datasheet requirements.
P34	RESERVED_P34		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AP4	PCIE_TXN_3	mPCIE_TX_N	✅	PCIE_TXN_3 is connected to net mPCIE_TX_N for mini PCIe transmit path.
AP6	PCIE_TXP_3	mPCIE_TX_P	✅	PCIE_TXP_3 is connected to net mPCIE_TX_P for mini PCIe transmit path.
AP7	PCIE_RXN_3	mPCIE_RX_N	✅	PCIE_RXN_3 is connected to net mPCIE_RX_N for mini PCIe receive path.
AP9	PCIE_RXP_3	mPCIE_RX_P	✅	PCIE_RXP_3 is connected to net mPCIE_RX_P for mini PCIe receive path.
AP10	PCIE_RXN_2	PCIE_RXN2	✅	PCIE_RXN_2 is connected to net PCIE_RXN2 for PCIe lane 2 receive path.
AP12	PCIE_RXP_2	PCIE_RXP2	✅	PCIE_RXP_2 is connected to net PCIE_RXP2 for PCIe lane 2 receive path.
AP13	PCIE_RCOMP_N_AP13_AP13	PCIE_RCOMP_N	✅	PCIE_RCOMP_N is connected to a 402 ohm resistor (R218) to PCIE_RCOMP_P for PCIe compensation.
AP14	PCIE_RCOMP_P_AP14_AP14	PCIE_RCOMP_P	✅	PCIE_RCOMP_P is connected to a 402 ohm resistor (R218) to PCIE_RCOMP_N for PCIe compensation.
AT6	PCIE_TXN_2	PCIE_TXN2	✅	PCIE_TXN_2 is connected to net PCIE_TXN2 for PCIe lane 2 transmit path.
AT7	PCIE_TXP_2	PCIE_TXP2	✅	PCIE_TXP_2 is connected to net PCIE_TXP2 for PCIe lane 2 transmit path.
AT10	PCIE_RXP_1		✅	PCIe lane 1 receive pins are unconnected, indicating this lane is not implemented.
AT9	PCIE_RXN_1		✅	PCIe lane 1 receive pins are unconnected, indicating this lane is not implemented.
AT13	PCIE_RXN_0		✅	PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented.
AT14	PCIE_RXP_0		✅	PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented.
AV4	PCIE_TXN_1		✅	PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented.
AV6	PCIE_TXP_1		✅	PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented.
AY6	PCIE_TXN_0		✅	PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented.
AY7	PCIE_TXP_0		✅	PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented.
AT18	SATA_RCOMP_N_AT18	SATA_RCOMP_N	✅	SATA_RCOMP_N is connected to a 402 ohm resistor (R239) to SATA_RCOMP_P for SATA compensation.
AT20	MMC1_D3		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AT22	MMC1_CLK		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AT26	MMC1_D6		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AU20	MMC1_D7		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AU22	MMC1_D1		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AU26	MMC1_D5		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AV20	MMC1_D0		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AV22	MMC1_D2		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AV26	MMC1_CMD		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AY24	MMC1_D4		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
BA24	~MMC1_RST		✅	eMMC interface pins are unconnected, indicating eMMC is not implemented in this design.
AT28	SD3_D0	SD3_D0	✅	SD3_D0 is connected to SD Card 3 data bit 0 signal.
AU16	SATA_RXP_0	SATA0_RXP	✅	SATA_RXP_0 is connected through AC coupling capacitor C13 to SATA connector for SATA port 0 receive.
AU18	SATA_RCOMP_P_AU18	SATA_RCOMP_P	✅	SATA_RCOMP_P is connected to a 402 ohm resistor (R239) to SATA_RCOMP_N for SATA compensation.
AU28	SD3_D2	SD3_D2	✅	SD3_D2 is connected to SD Card 3 data bit 2 signal.
AV16	SATA_RXN_0	SATA0_RXN	✅	SATA_RXN_0 is connected through AC coupling capacitor C12 to SATA connector for SATA port 0 receive.
AV28	SD3_CMD	SD3_CMD	✅	SD3_CMD is connected to SD Card 3 command signal.
AY12	~SATA_LED	SATA_LED_B	✅	SATA_LED# is connected through current limiting resistor R179 to LED circuit with jumper J6.
AY14	SATA_GP1	SATA_GP1	✅	SATA_GP1 is connected with 10K pull-down resistor R221 to ground.
AY16	SATA_RXP_1	SATA1_RXP	✅	SATA_RXP_1 is connected through AC coupling capacitor C178 from mSATA interface.
AY18	MMC1_RCOMP	MMC1_RCOMP	✅	MMC1_RCOMP is connected with 49.9 ohm resistor R240 to ground for eMMC compensation.
AY20	SD2_D0		✅	SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design.
AY26	SD3_CLK	SD3_CLK	✅	SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design.
BA18	SD2_CLK		✅	SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design.
BA20	SD2_D2		✅	SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design.
BC18	SD2_CMD		✅	SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design.
BD18	~SD2_D3_CD		✅	SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design.
BD20	SD2_D1		✅	SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design.

C10 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXP_C	✅	Connector side of AC coupling capacitor for SATA0 TX positive differential signal.
2	2	SATA0_TXP	✅	CPU side of AC coupling capacitor for SATA0 TX positive differential signal.

C11 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXN_C	✅	Connector side of AC coupling capacitor for SATA0 TX negative differential signal.
2	2	SATA0_TXN	✅	CPU side of AC coupling capacitor for SATA0 TX negative differential signal.

C12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXN_C	✅	Connector side of AC coupling capacitor for SATA0 RX negative differential signal.
2	2	SATA0_RXN	✅	CPU side of AC coupling capacitor for SATA0 RX negative differential signal.

C13 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXP_C	✅	Connector side of AC coupling capacitor for SATA0 RX positive differential signal.
2	2	SATA0_RXP	✅	CPU side of AC coupling capacitor for SATA0 RX positive differential signal.

C148 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND_EARTH	✅	Chassis ground connection of optional EMI filtering Y-capacitor, marked DNI (Do Not Install).
2	2	GND	✅	Signal ground connection of optional EMI filtering Y-capacitor, marked DNI (Do Not Install).

J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net.
2	2	SATA0_TXP_C	✅	Host transmit positive signal correctly connected through AC coupling capacitor C10 to CPU SATA_TXP_0 pin.
3	3	SATA0_TXN_C	✅	Host transmit negative signal correctly connected through AC coupling capacitor C11 to CPU SATA_TXN_0 pin.
4	4	GND	✅	Ground pin correctly connected to GND net.
5	5	SATA0_RXN_C	✅	Host receive negative signal correctly connected through AC coupling capacitor C12 to CPU SATA_RXN_0 pin.
6	6	SATA0_RXP_C	✅	Host receive positive signal correctly connected through AC coupling capacitor C13 to CPU SATA_RXP_0 pin.
7	7	GND	✅	Ground pin correctly connected to GND net.
MH1			✅	Mounting hole correctly connected to chassis ground (GND_EARTH) for EMI shielding.
MH2			✅	Mounting hole correctly connected to chassis ground (GND_EARTH) for EMI shielding.

C177 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_N	✅	AC coupling capacitor for SATA1 RX negative differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces.
2	2	SATA1_RXN	✅	AC coupling capacitor for SATA1 RX negative differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces.

C179 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_P	✅	AC coupling capacitor for SATA1 TX positive differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces.
2	2	SATA1_TXP	✅	AC coupling capacitor for SATA1 TX positive differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces.

C178 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_P	✅	AC coupling capacitor for SATA1 RX positive differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces.
2	2	SATA1_RXP	✅	AC coupling capacitor for SATA1 RX positive differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces.

C180 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_N	✅	AC coupling capacitor for SATA1 TX negative differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces.
2	2	SATA1_TXN	✅	AC coupling capacitor for SATA1 TX negative differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces.

R239 - 110-0004476 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_RCOMP_N	✅	402 ohm resistor connected between SATA_RCOMP_N and SATA_RCOMP_P, serving as the SATA compensation resistor for the Intel Atom E3825 SOC.
2	2	SATA_RCOMP_P	✅	402 ohm resistor connected between SATA_RCOMP_N and SATA_RCOMP_P, serving as the SATA compensation resistor for the Intel Atom E3825 SOC.

R73 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS4/ICLK_SATA_TERMP) to GND for SATA termination.
2	2	ICLK_SATA_TERMP	✅	0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS4/ICLK_SATA_TERMP) to GND for SATA termination.

R74 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS5/ICLK_SATA_TERMN) to GND for SATA termination.
2	2	ICLK_SATA_TERMN	✅	0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS5/ICLK_SATA_TERMN) to GND for SATA termination.

R179 - 110-0001960 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_LED_B	✅	220 ohm current limiting resistor for SATA LED indicator circuit, connected between CPU SATA_LED output and jumper-selectable power supply.
2	2	SATA_LED_R	✅	220 ohm current limiting resistor for SATA LED indicator circuit, connected between CPU SATA_LED output and jumper-selectable power supply.

J6 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S supply, providing power source for SATA LED circuit when jumper is installed.
2	2	SATA_LED_R	✅	Connected to SATA_LED_R net, which connects through R179 to the CPU SATA LED output.

R220 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	10K pull-down resistor on SATA_GP0 (SATA General Purpose 0) pin, ensuring defined logic level when not driven.
2	2	SATA_GP0	✅	10K pull-down resistor on SATA_GP0 (SATA General Purpose 0) pin, ensuring defined logic level when not driven.

R221 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	10K pull-down resistor on SATA_GP1 (SATA General Purpose 1) pin, ensuring defined logic level when not driven.
2	2	SATA_GP1	✅	10K pull-down resistor on SATA_GP1 (SATA General Purpose 1) pin, ensuring defined logic level when not driven.

R354 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SD3_WP	✅	0-ohm resistor ties SD3_WP (CPU1 pin BD5) to SD3_CD# (CPU1 pin BC24). This unusual connection appears intentional based on schematic note indicating Bay Trail-I platform-specific behavior for pin BD5.
2	2	SD3_CD#	✅	0-ohm resistor ties SD3_WP (CPU1 pin BD5) to SD3_CD# (CPU1 pin BC24). This unusual connection appears intentional based on schematic note indicating Bay Trail-I platform-specific behavior for pin BD5.

R2 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mPCIe_CLKREQ3_B	✅	10K pull-up resistor on mPCIe_CLKREQ3_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.
2	2	+V1P8S	✅	10K pull-up resistor on mPCIe_CLKREQ3_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.

R192 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS7	✅	0 ohm resistor connecting reserved VSS pin RESERVED_VSS7 to GND.
2	2	GND	✅	0 ohm resistor connecting reserved VSS pin RESERVED_VSS7 to GND.

R218 - 110-0004476 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PCIE_RCOMP_P	✅	402 ohm compensation resistor connected between PCIE_RCOMP_P and PCIE_RCOMP_N for PCIe impedance compensation.
2	2	PCIE_RCOMP_N	✅	402 ohm compensation resistor connected between PCIE_RCOMP_P and PCIE_RCOMP_N for PCIe impedance compensation.

R72 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS6	✅	0 ohm resistor connecting reserved VSS pin RESERVED_VSS6 to GND.
2	2	GND	✅	0 ohm resistor connecting reserved VSS pin RESERVED_VSS6 to GND.

R71 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_CLKREQ2_B	✅	10K pull-up resistor on LAN_CLKREQ2_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.
2	2	+V1P8S	✅	10K pull-up resistor on LAN_CLKREQ2_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.

R190 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ1_B	✅	10K pull-up resistor on CLKREQ1_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.
2	2	+V1P8S	✅	10K pull-up resistor on CLKREQ1_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.

R191 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ0_B	✅	10K pull-up resistor on CLKREQ0_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.
2	2	+V1P8S	✅	10K pull-up resistor on CLKREQ0_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request.

R242 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDA_RCOMP	✅	Connected to CPU1 HDA_LPE_RCOMP pin (BF20) for HDA impedance compensation calibration.
2	2	GND	✅	Connected to GND, providing the ground reference for the RCOMP calibration resistor.

R240 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to GND for the MMC1 RCOMP calibration resistor.
2	2	MMC1_RCOMP	✅	Pin 2 is correctly connected to MMC1_RCOMP (CPU1 pin AY18) for eMMC interface impedance calibration.

R260 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_DATOUT	✅	Connected to LPE_I2S_DATOUT. This component is marked DNI (Do Not Install), so it is electrically absent from the circuit.
2	2	GND	✅	Connected to GND. This component is marked DNI, so the pull-down to ground is not present in the final design.

R259 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_10_UNLOCK	✅	Connected to GPIO_S5_10_UNLOCK net. This pin forms one end of a 1K series resistor that connects to the LPE_I2S_DATOUT signal.
2	2	LPE_I2S_DATOUT	✅	Connected to LPE_I2S_DATOUT, which connects to CPU1 pin BC30 (LPE_I2S2_DATAOUT). Text notes indicate this signal can function as GPIO_S0_SC65 strap pin.

R268 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_FRM	✅	Connected to LPE_I2S_FRM, which is the I2S frame sync signal from CPU1 pin BA30. Text notes indicate this signal can function as GPIO_S0_SC63 strap pin.
2	2	+V1P8S	✅	Connected to +V1P8S, providing a 10K pull-up for the LPE_I2S_FRM signal to 1.8V.

R219 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S as part of a pull-up resistor configuration for hardware strap GPIO_S0_SC_56. Component is DNI.
2	2	GPIO_S0_SC_56	✅	Connected to GPIO_S0_SC_56 as part of a pull-up resistor configuration for hardware strap. Component is DNI.

R189 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND as part of a pull-down resistor configuration for hardware strap GPIO_S0_SC_56. Component is DNI.
2	2	GPIO_S0_SC_56	✅	Connected to GPIO_S0_SC_56 as part of a pull-down resistor configuration for hardware strap. Component is DNI.

R255 - 110-0004474 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR_HOT_L	✅	Connected to VR_HOT_L net, which connects to CPU1 pin C24 (PROCHOT). This appears to be part of a thermal monitoring interface between the CPU and voltage regulators.
2	2	+V1P0S	✅	Connected to +V1P0S (1.0V supply rail). Combined with the 73.2Ω resistance, this creates a low-impedance connection that appears to be a termination or interface resistor rather than a typical pull-up.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A9	ILB_RTC_X2	BRTCX2	✅	ILB_RTC_X2 is connected to 32.768 kHz crystal Y1 pin 1 with 18pF load capacitor C42 and 10M feedback resistor R76.
A13	GPIO_S5_9	SOC_USB_HOST_EN1	✅	GPIO_S5_9 is connected to SOC_USB_HOST_EN1 net, used for USB host enable control.
A17	GPIO_S5_3	mPCIE_WAKEB	✅	GPIO_S5_3 is connected to mPCIE_WAKEB net with optional 2.2K pull-up resistor R1 (DNI) to +V1P8A.
A21	PCU_SPI_MOSI	SOC_SPI_MOSI	✅	PCU_SPI_MOSI is connected through 0-ohm series resistor R103 to SOC_SPI_MOSI-R net for SPI communication.
A25	SVID_DATA	SVID_DATA	✅	SVID_DATA is connected through 16.9-ohm series resistor R101 to SVID_DATA-R for voltage regulator control.
B7	PMC_CORE_PWROK	PMC_CORE_PWROK	✅	PMC_CORE_PWROK is connected through 0-ohm resistor R59 to SYS_PWRGD with optional 1uF capacitor C33 (DNI) to GND.
B8	ILB_RTC_EXTPAD	BVCCRTC_EXTPAD	✅	ILB_RTC_EXTPAD is connected to 0.1uF capacitor C41 to GND for RTC external pad filtering.
B10	~PMC_RSMRST	PMC_RSMRST	✅	PMC_RSMRST is connected with 10K pull-up to +3VSB, 100K pull-down to GND, and 10pF capacitor to GND for resume reset timing.
B14	GPIO_S5_6	BOM_OP2	✅	GPIO_S5_6 is connected to net BOM_OP2 for BOM option 2 configuration.
B16	GPIO_S5_1	SOC_GPIO_S5_1	✅	GPIO_S5_1 is connected to net SOC_GPIO_S5_1 for general purpose I/O.
B18	GPIO_S5_0	SOC_GPIO_S5_0	✅	GPIO_S5_0 is connected to net SOC_GPIO_S5_0 for general purpose I/O.
B22	PCU_SPI_MISO	SOC_SPI_MISO	✅	PCU_SPI_MISO is connected through 0-ohm series resistor R36 to SOC_SPI_MISO-R net for SPI communication.
B24	~SVID_ALERT	SVID_ALERT	✅	SVID_ALERT is connected through 20-ohm series resistor R100 to SVID_ALERT-R, then through 69.8-ohm resistor R104 to +V1P0S.
C9	ILB_RTC_X1	BRTCX1	✅	ILB_RTC_X1 is connected to 32.768 kHz crystal Y1 pin 2 with 18pF load capacitor C43 and 10M feedback resistor R76.
C11	~ILB_RTC_TEST	ILB_RTC_TESTB	✅	ILB_RTC_TEST is connected to net ILB_RTC_TESTB for RTC test mode control.
C12	~ILB_RTC_RST	RTCRST_L	✅	ILB_RTC_RST is connected with 20K pull-up to +RTCVCC and 1uF capacitor to GND for RTC reset timing.
C13	GPIO_S5_8	SOC_USB_HOST_EN0	✅	GPIO_S5_8 is connected to net SOC_USB_HOST_EN0 for USB host enable control.
C15	GPIO_S5_7	BOM_OP3	✅	GPIO_S5_7 is connected to net BOM_OP3 for BOM option 3 configuration.
C16	GPIO_S5_5	BOM_OP1	✅	GPIO_S5_5 is connected to net BOM_OP1 for BOM option 1 configuration.
C17	GPIO_S5_4	BOM_OP4	✅	GPIO_S5_4 is connected to net BOM_OP4 for BOM option 4 configuration.
C18	GPIO_S5_2	SOC_GPIO_S5_2	✅	GPIO_S5_2 is connected to net SOC_GPIO_S5_2 for general purpose I/O.
C19	GPIO_S5_10	GPIO_S5_10_UNLOCK	✅	GPIO_S5_10 is connected to net GPIO_S5_10_UNLOCK for GPIO unlock function.
C21	~PCU_SPI_CS_11	SOC_SPI_CS1B	✅	PCU_SPI_CS_11 is connected through 0-ohm series resistor R235 (DNI), effectively leaving SPI CS1 unconnected.
C22	PCU_SPI_CLK	SOC_SPI_CLK	✅	PCU_SPI_CLK is connected through 0-ohm series resistor R98 to SOC_SPI_CLK-R net for SPI clock.
C23	~PCU_SPI_CS_00	SOC_SPI_CS0B	✅	PCU_SPI_CS_00 is connected through 0-ohm series resistor R99 to SOC_SPI_CS0B-R net for SPI chip select 0.
C25	SVID_CLK	SVID_CLK-R	✅	SVID_CLK is connected to net SVID_CLK-R for voltage regulator control clock.
D14	TAP_TCK	XDP_H_TCK	✅	TAP_TCK is connected through 51-ohm resistor R8 to GND. This pull-down on JTAG clock is unusual but may be intentional to keep clock low when debugger is not connected.
D18	~TAP_PRDY	XDP_H_PRDYB	✅	TAP_PRDY is connected to net XDP_H_PRDYB for JTAG probe ready signal.
D20	PMC_ACPRESENT	PMC_ACPRESENT	✅	PMC_ACPRESENT is connected with 2.2K pull-up to +V1P8A for AC present detection.
D22	~PMC_SLP_S3	PMC_SLP_S3_L	✅	PMC_SLP_S3 is connected to level shifter U19 pin 5 with optional 2.2K pull-up R53 (DNI) to +3VSB.
D26	PMC_SUSPWRDNACK	SUSPWRDNACK	✅	PMC_SUSPWRDNACK is connected with 10K pull-up to +V1P8A and optional test point TP14 (DNI).
F12	TAP_TDI	XDP_H_TDI	✅	TAP_TDI is connected through 51-ohm series resistor R10 with pull-up to +V1P8A for JTAG test data in.
F14	TAP_TMS	XDP_H_TMS	✅	TAP_TMS is connected through 51-ohm series resistor R9 with pull-up to +V1P8A for JTAG test mode select.
F16	~TAP_PREQ	XDP_H_PREQB	✅	TAP_PREQ is connected to net XDP_H_PREQB for JTAG probe request signal.
F18	~PMC_SLP_S0IX	PMC_SLP_S0IX	✅	PMC_SLP_S0IX is connected to optional test point TP10 (DNI) for sleep S0ix state monitoring.
F20	~PMC_PLTRST	PMC_PLTRST_R_V1P8	✅	PMC_PLTRST is connected to level shifter U19 pin 2 with optional 2.2K pull-up R56 (DNI) to +3VSB.
F22	~PMC_SLP_S4	PMC_SLP_S4_L	✅	PMC_SLP_S4 is connected to level shifter U19 pin 4 with optional 2.2K pull-up R54 (DNI) to +3VSB.
F26	~PMC_WAKE_PCIE_0	PMC_PCIE_WAKE_R	✅	PMC_WAKE_PCIE_0 is connected through diode D3 to PMC_PCIE_WAKE with 1K pull-up R253 to +V1P8A.
G12	~TAP_TRST	XDP_H_TRSTB	✅	TAP_TRST is connected through 51-ohm resistor R19 to GND for JTAG test reset.
G16	TAP_TDO	XDP_H_TDO	✅	TAP_TDO is connected to net XDP_H_TDO for JTAG test data out.
G18	~PMC_SUS_STAT	LPCPD_L	✅	PMC_SUS_STAT is connected to net LPCPD_L with optional test point TP7 (DNI) for suspend status monitoring.
G24	PMC_SUSCLK0_G24	PMC_SUSCLK0	✅	PMC_SUSCLK0_G24 is connected to level shifter U19 pin 3 with optional 2.2K pull-up R58 (DNI) to +V1P8A.
J18	GPIO_S5_25	XDP_H_OBSDATA_A2	✅	GPIO_S5_25 is connected to net XDP_H_OBSDATA_A2 for debug observation data.
J20	GPIO_S5_14	GPIO_S514_J20	✅	GPIO_S5_14 is connected with 10K pull-up to +V1P8A for GPIO configuration.
J24	GPIO_S5_17	GPIO_S5_17	✅	GPIO_S5_17 is connected to jumper J7 pin 1 with 10K pull-up R183 to +V1P8S for GPIO configuration.
J26	~PMC_PWRBTN	PMC_PWRBTN	✅	PMC_PWRBTN is connected through diode D10 with optional 20K pull-up R161 (DNI) to +V1P8A for power button input.
K18	GPIO_S5_27	EXP_GPIO1	✅	GPIO_S5_27 is connected to net EXP_GPIO1 for expansion GPIO 1.
K20	GPIO_S5_28	EXP_GPIO2	✅	GPIO_S5_28 is connected to net EXP_GPIO2 for expansion GPIO 2.
K24	GPIO_S5_22	GPIO_D2_LED_CTRL	✅	GPIO_S5_22 is connected to net GPIO_D2_LED_CTRL for LED control.
K26	~PMC_BATLOW	PMC_BATLOW	✅	PMC_BATLOW is connected with 20K pull-up to +V1P8A for battery low detection.
M18	GPIO_S5_26	XDP_H_OBSDATA_A3	✅	GPIO_S5_26 is connected to net XDP_H_OBSDATA_A3 for debug observation data.
M20	GPIO_S5_24	XDP_H_OBSDATA_A1	✅	GPIO_S5_24 is connected to net XDP_H_OBSDATA_A1 for debug observation data.
M22	GPIO_S5_29	EXP_GPIO3	✅	GPIO_S5_29 is connected to net EXP_GPIO3 for expansion GPIO 3.
M24	GPIO_S5_30	EXP_GPIO4	✅	GPIO_S5_30 is connected to net EXP_GPIO4 for expansion GPIO 4.
N24	GPIO_S5_23	XDP_H_OBSDATA_A0	✅	GPIO_S5_23 is connected to net XDP_H_OBSDATA_A0 for debug observation data.
N26	GPIO_RCOMP	GPIO_RCOMP	✅	GPIO_RCOMP is connected to 49.9-ohm compensation resistor R238 to ground, correctly configured per datasheet.
BA28	SIO_SPI_MISO	SOC_SIO_SPI_MISO	✅	SIO_SPI_MISO is connected to net SOC_SIO_SPI_MISO for Serial I/O SPI master in slave out.
BA34	~SIO_UART1_RTS	SIO_UART1_RTSB	✅	SIO_UART1_RTS is connected to net SIO_UART1_RTSB for UART1 request to send.
AD9	RESERVED_AD9		✅	RESERVED_AD9 pin has no connection, which is correct for reserved pins.
AD10	RESERVED_AD10		✅	RESERVED_AD10 pin has no connection, which is correct for reserved pins.
AD12	RESERVED_AD12		✅	RESERVED_AD12 pin has no connection, which is correct for reserved pins.
AD13	ICLK_RCOMP	ICLK_RCOMP	✅	ICLK_RCOMP is connected to 47.5-ohm compensation resistor R214 to ground, correctly configured per datasheet.
AD14	ICLK_ICOMP	ICLK_ICOMP	✅	ICLK_ICOMP is connected to 4.02K-ohm compensation resistor R215 to ground, correctly configured per datasheet.
BD32	~SIO_UART2_RTS		✅	SIO_UART2_RTS has no connection, which is acceptable if UART2 hardware flow control is not needed.
BD34	SIO_UART2_TXD	SIO_UART2_TXD	✅	SIO_UART2_TXD is connected to net SIO_UART2_TXD for UART2 transmit data.
AF4	PCIE_CLKP_00		✅	PCIE_CLKP_00 has no connection, which is acceptable if PCIe lane 0 is not used.
AF6	PCIE_CLKN_00		✅	PCIE_CLKN_00 has no connection, which is acceptable if PCIe lane 0 is not used.
AF7	PCIE_CLKP_11		✅	PCIE_CLKP_11 has no connection, which is acceptable if PCIe lane 1 is not used.
AF9	PCIE_CLKN_11		✅	PCIE_CLKN_11 has no connection, which is acceptable if PCIe lane 1 is not used.
BF32	~SIO_UART2_CTS		✅	SIO_UART2_CTS has no connection, which is acceptable if UART2 hardware flow control is not needed.
BF34	SIO_UART2_RXD	SIO_UART2_RXD	✅	SIO_UART2_RXD is connected to net SIO_UART2_RXD for UART2 receive data.
BG9	~PMC_RSTBTN	PMC_RSTBTN	✅	PMC_RSTBTN is connected to net PMC_RSTBTN for reset button input.
AH10	ICLK_OSCOUT	XTAL25_OUT	✅	ICLK_OSCOUT is connected to 25 MHz crystal Y2 pin 3 with 27pF load capacitor C176 and 1M feedback resistor R188.
AH12	ICLK_OSCIN	XTAL25_IN	✅	ICLK_OSCIN is connected to 25 MHz crystal Y2 pin 1 with 27pF load capacitor C175 and 1M feedback resistor R188.
BH4	PMC_PLT_CLK_22		✅	PMC_PLT_CLK_22 has no connection, which is acceptable if platform clock 2 is not needed.
BH5	PMC_PLT_CLK_11		✅	PMC_PLT_CLK_11 has no connection, which is acceptable if platform clock 1 is not needed.
BH6	PMC_PLT_CLK_44		✅	PMC_PLT_CLK_44 has no connection, which is acceptable if platform clock 4 is not needed.
BH7	PMC_PLT_CLK_00		✅	PMC_PLT_CLK_00 has no connection, which is acceptable if platform clock 0 is not needed.
BH8	PMC_PLT_CLK_33	I2S_MCLK	✅	PMC_PLT_CLK_33 is connected to net I2S_MCLK for I2S master clock output.
AK4	PCIE_CLKN_22	PCIE_CLK-N2	✅	PCIE_CLKN_22 is connected to net PCIE_CLK-N2 for PCIe lane 2 clock negative signal.
AK6	PCIE_CLKP_22	PCIE_CLK-P2	✅	PCIE_CLKP_22 is connected to net PCIE_CLK-P2 for PCIe lane 2 clock positive signal.
BJ9	PMC_PLT_CLK_55		✅	PMC_PLT_CLK_55 has no connection, which is acceptable if platform clock 5 is not needed.
AM4	PCIE_CLKN_33	mPCIE_REFCLK_N	✅	PCIE_CLKN_33 is connected to net mPCIE_REFCLK_N for mini-PCIe reference clock negative signal.
AM6	PCIE_CLKP_33	mPCIE_REFCLK_P	✅	PCIE_CLKP_33 is connected to net mPCIE_REFCLK_P for mini-PCIe reference clock positive signal.
AM9	RESERVED_AM9		✅	RESERVED_AM9 pin has no connection, which is correct for reserved pins.
AM10	RESERVED_AM10		✅	RESERVED_AM10 pin has no connection, which is correct for reserved pins.
AT32	SIO_PWM_11	SOC_PWM1	✅	SIO_PWM_11 is connected to net SOC_PWM1 for PWM output 1.
AT34	RESERVED		✅	RESERVED pin has no connection, which is correct for reserved pins.
AU32	SIO_PWM_00	SOC_PWM0	✅	SIO_PWM_00 is connected to net SOC_PWM0 for PWM output 0.
AU34	SIO_UART1_RXD	SIO_UART1_RXD	✅	SIO_UART1_RXD is connected to net SIO_UART1_RXD for UART1 receive data.
AV32	~SIO_SPI_CS	SOC_SIO_SPI_CS1	✅	SIO_SPI_CS is connected to net SOC_SIO_SPI_CS1 for Serial I/O SPI chip select.
AV34	SIO_UART1_TXD	SIO_UART1_TXD	✅	SIO_UART1_TXD is connected to net SIO_UART1_TXD for UART1 transmit data.
AY28	SIO_SPI_MOSI	SOC_SIO_SPI_MOSI	✅	SIO_SPI_MOSI is connected to net SOC_SIO_SPI_MOSI for Serial I/O SPI master out slave in.
AY30	SIO_SPI_CLK	SOC_SIO_SPI_CLK	✅	SIO_SPI_CLK is connected to net SOC_SIO_SPI_CLK for Serial I/O SPI clock.
AY34	~SIO_UART1_CTS	SIO_UART1_CTSB	✅	SIO_UART1_CTS is connected to net SIO_UART1_CTSB for UART1 clear to send.

R57 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pin 1 is correctly connected to +V1P8A, providing the pull-up voltage for the OE pin of U19.
2	2	PMC_OE	✅	Pin 2 is correctly connected to PMC_OE, which connects to the OE pin of U19, enabling the level shifter by default.

U19 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A (1.8V supply) for the A-side voltage reference.
2	A1	PMC_PLTRST_R_V1P8	✅	A1 is correctly connected to PMC_PLTRST_R_V1P8, the 1.8V side of the platform reset signal from CPU1 pin F20.
3	A2	PMC_SUSCLK0	✅	A2 is correctly connected to PMC_SUSCLK0, the 1.8V side of the suspend clock signal from CPU1 pin G24.
4	A3	PMC_SLP_S4_L	✅	A3 is correctly connected to PMC_SLP_S4_L, the 1.8V side of the S4 sleep state signal from CPU1 pin F22.
5	A4	PMC_SLP_S3_L	✅	A4 is correctly connected to PMC_SLP_S3_L, the 1.8V side of the S3 sleep state signal from CPU1 pin D22.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	SLP_S3_L	✅	B4 is correctly connected to SLP_S3_L, the 3.3V side of the S3 sleep state signal.
8	B3	SLP_S4_L	✅	B3 is correctly connected to SLP_S4_L, the 3.3V side of the S4 sleep state signal.
9	B2	SUSCLK_3P3	✅	B2 is correctly connected to SUSCLK_3P3, the 3.3V side of the suspend clock signal.
10	B1	PMC_PLTRST_L	✅	B1 is correctly connected to PMC_PLTRST_L, the 3.3V side of the platform reset signal.
11	VCCB	PWR_BUF1	✅	VCCB is correctly connected to PWR_BUF1, which is effectively +3VSB (3.3V standby supply) through R26.
12	OE	PMC_OE	✅	OE is correctly connected to PMC_OE with a pull-up to +V1P8A through R57 to enable the level shifter.

C41 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BVCCRTC_EXTPAD	✅	Decoupling capacitor for RTC external pad, connected to BVCCRTC_EXTPAD which connects to CPU1 RTC power pin.
2	2	GND	✅	Ground connection for decoupling capacitor.

C286 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for bulk decoupling capacitor on +RTCVCC rail.
2	2	+RTCVCC	✅	Bulk decoupling capacitor for +RTCVCC power rail, providing low-frequency filtering and charge storage.

R279 - 110-0001957 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+RTCVCC	✅	Pull-up resistor connected to +RTCVCC to pull the RTC reset signal high (inactive state).
2	2	RTCRST_L	✅	Pull-up resistor output connected to RTCRST_L, the active-low RTC reset signal going to CPU1.

R278 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VBAT	✅	Series resistor input connected to battery positive terminal (+VBAT).
2	2	+VBAT_R	✅	Series resistor output connected to +VBAT_R, which feeds the battery backup OR-ing diode.

C285 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for filtering capacitor on RTC reset signal.
2	2	RTCRST_L	✅	Filtering capacitor on RTCRST_L signal, forming RC filter with R279 for clean reset signal with ~20ms time constant.

Y1 - 145-0004789 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BRTCX2	✅	Crystal pin 1 connected to BRTCX2, which connects to CPU1 RTC oscillator pin ILB_RTC_X2. Load capacitor C42 (18pF) and feedback resistor R76 (10M) are properly connected.
2	2	BRTCX1	✅	Crystal pin 2 connected to BRTCX1, which connects to CPU1 RTC oscillator pin ILB_RTC_X1. Load capacitor C43 (18pF) and feedback resistor R76 (10M) are properly connected.

BH1 - BATTERY HOLDER VERT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+VBAT	✅	Positive battery terminals connected to +VBAT net. Both pins are tied together for redundancy, which is standard for battery holders.
2	P2	+VBAT	✅	Positive battery terminals connected to +VBAT net. Both pins are tied together for redundancy, which is standard for battery holders.
3	N	GND	✅	Negative battery terminal correctly connected to GND.

D5 - 4536-0009 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	+PS_3VSB	✅	Anode 1 connected to +PS_3VSB (3.3V standby power). This is one input to the OR-ing diode configuration for RTC backup power.
A2	A2	+VBAT_R	✅	Anode 2 connected to +VBAT_R (battery voltage through 1K resistor). This is the backup power input to the OR-ing diode configuration.
C	C	+RTCVCC	✅	Common cathode connected to +RTCVCC, which powers the RTC circuitry. The OR-ing configuration ensures RTC power from either 3VSB or battery, whichever is higher.

C175 - 123-0001107 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor ground terminal correctly connected to GND, providing ground reference for the crystal load capacitor.
2	2	XTAL25_IN	✅	Load capacitor correctly connected to crystal input (XTAL25_IN) to provide required load capacitance for the 25MHz oscillator.

C176 - 123-0001107 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor ground terminal correctly connected to GND, providing ground reference for the crystal load capacitor.
2	2	XTAL25_OUT	✅	Load capacitor correctly connected to crystal output (XTAL25_OUT) to provide required load capacitance for the oscillator.

R188 - 110-0001941 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XTAL25_IN	✅	Feedback resistor correctly connected to XTAL25_IN, providing DC bias for the Pierce oscillator amplifier.
2	2	XTAL25_OUT	✅	Feedback resistor correctly connected to XTAL25_OUT, completing the bias feedback path for the Pierce oscillator.

Y2 - 145-0004792 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XTAL25_IN	✅	Crystal input pin correctly connected to CPU oscillator input (ICLK_OSCIN) through XTAL25_IN net with proper 27pF load capacitor C175 and 1MΩ feedback resistor R188.
2	2	GND	✅	Crystal ground pins correctly connected to system ground, providing proper grounding for the 4-pin crystal package.
4	4	GND	✅	Crystal ground pins correctly connected to system ground, providing proper grounding for the 4-pin crystal package.
3	3	XTAL25_OUT	✅	Crystal output pin correctly connected to CPU oscillator output (ICLK_OSCOUT) through XTAL25_OUT net with proper 27pF load capacitor C176.

R103 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SOC_SPI_MOSI-R	✅	0-ohm series resistor connecting CPU SPI MOSI (SOC_SPI_MOSI) to routed signal (SOC_SPI_MOSI-R). Provides routing flexibility and potential measurement point.
2	2	SOC_SPI_MOSI	✅	0-ohm series resistor connecting CPU SPI MOSI (SOC_SPI_MOSI) to routed signal (SOC_SPI_MOSI-R). Provides routing flexibility and potential measurement point.

R98 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SOC_SPI_CLK-R	✅	0-ohm series resistor connecting CPU SPI clock (SOC_SPI_CLK) to routed signal (SOC_SPI_CLK-R). Provides routing flexibility and potential measurement point. DNI capacitor C69 on routed side is not electrically present.
2	2	SOC_SPI_CLK	✅	0-ohm series resistor connecting CPU SPI clock (SOC_SPI_CLK) to routed signal (SOC_SPI_CLK-R). Provides routing flexibility and potential measurement point. DNI capacitor C69 on routed side is not electrically present.

R36 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SOC_SPI_MISO-R	✅	0-ohm series resistor connecting CPU SPI MISO (SOC_SPI_MISO) to routed signal (SOC_SPI_MISO-R). Provides routing flexibility and potential measurement point.
2	2	SOC_SPI_MISO	✅	0-ohm series resistor connecting CPU SPI MISO (SOC_SPI_MISO) to routed signal (SOC_SPI_MISO-R). Provides routing flexibility and potential measurement point.

R99 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SOC_SPI_CS0B-R	✅	0-ohm series resistor connecting CPU SPI chip select 0 (SOC_SPI_CS0B) to routed signal (SOC_SPI_CS0B-R). Provides routing flexibility and potential measurement point.
2	2	SOC_SPI_CS0B	✅	0-ohm series resistor connecting CPU SPI chip select 0 (SOC_SPI_CS0B) to routed signal (SOC_SPI_CS0B-R). Provides routing flexibility and potential measurement point.

R253 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PCIE_WAKE_R	✅	Connected to PMC_PCIE_WAKE_R net, which is the anode side of diode D3 and connects to the CPU wake input.
2	2	+V1P8A	✅	Connected to +V1P8A rail, providing pull-up voltage for the PMC_PCIE_WAKE_R signal at the CPU input level.

D3 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PCIE_WAKE	✅	Cathode pins connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27. This forms the high-voltage side of a diode-based level shifter.
2	2	PMC_PCIE_WAKE	✅	Cathode pins connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27. This forms the high-voltage side of a diode-based level shifter.
3	3	PMC_PCIE_WAKE_R	✅	Anode pin connected to PMC_PCIE_WAKE_R net, which connects to CPU1 pin F26 and is pulled up to +V1P8A through R253. This forms the low-voltage side of the level shifter.

R27 - 2.2K ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PCIE_WAKE	✅	Connected to PMC_PCIE_WAKE net, which is the cathode side of diode D3 and the source side of the level shifter circuit.
2	2	+3VSB	✅	Connected to +3VSB rail, providing pull-up voltage for the PMC_PCIE_WAKE signal.

R162 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3VSB_OK	✅	Connected to 3VSB_OK signal, providing pull-up function.
2	2	+3VSB	✅	Connected to +3VSB power rail, providing pull-up voltage source.

D10 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	3VSB_OK	✅	Anode connected to 3VSB_OK signal, which is pulled up to +3VSB through R162 (1K). This forms one input of a diode OR gate.
A2	A2	PMC_PWRBTN	✅	Anode connected to PMC_PWRBTN signal, which is pulled up to +3VSB through R27 (2.2K). This forms the second input of the diode OR gate.
C	C	PS_OUT_L	✅	Common cathode output connected to PS_OUT_L. This output goes low when either input (3VSB_OK or PMC_PWRBTN) goes low, implementing a diode OR gate.

R101 - 110-0004468 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA	✅	Connected to SVID_DATA from CPU1 pin A25. This is the CPU side of the SVID data signal.
2	2	SVID_DATA-R	✅	Connected to SVID_DATA-R, which presumably connects to the voltage regulator on another page.

R100 - 110-0001959 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT	✅	Connected to SVID_ALERT from CPU1 pin B24. This is the CPU side of the SVID alert signal.
2	2	SVID_ALERT-R	✅	Connected to SVID_ALERT-R, which connects to pull-up resistor R104 and presumably to the voltage regulator on another page.

R104 - 110-0002104 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Connected to SVID_ALERT-R, providing pull-up for the open-drain SVID alert signal.
2	2	+V1P0S	✅	Connected to +V1P0S (1.0V supply), providing the pull-up voltage for SVID_ALERT.

R9 - 110-0002078 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A power rail, providing pull-up for JTAG TMS signal through 51Ω resistor.
2	2	XDP_H_TMS	✅	Connected to XDP_H_TMS net, which connects to CPU JTAG TMS signal.

R10 - 110-0002078 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A power rail, providing pull-up for JTAG TDI signal through 51Ω resistor.
2	2	XDP_H_TDI	✅	Connected to XDP_H_TDI net, which connects to CPU JTAG TDI signal.

R19 - 110-0002078 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing pull-down for JTAG TRST signal through 51Ω resistor, keeping TAP controller in reset by default.
2	2	XDP_H_TRSTB	✅	Connected to XDP_H_TRSTB net, which connects to CPU JTAG TRST signal.

R8 - 110-0002078 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing pull-down for JTAG TCK signal through 51Ω resistor to prevent spurious clocking.
2	2	XDP_H_TCK	✅	Connected to XDP_H_TCK net, which connects to CPU JTAG TCK signal.

R214 - 110-0004473 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	ICLK_RCOMP	✅	Connected to ICLK_RCOMP compensation pin on CPU1. This resistor sets the output impedance for the Intel Clock interface.
2	2	GND	✅	Connected to ground, providing the reference for the compensation resistor.

R215 - 110-0002053 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	ICLK_ICOMP	✅	Connected to ICLK_ICOMP compensation pin on CPU1. This resistor sets the bias current for the Intel Clock interface.
2	2	GND	✅	Connected to ground, providing the reference for the compensation resistor.

R238 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_RCOMP	✅	Connected to GPIO_RCOMP compensation pin on CPU1. This resistor sets the output impedance for GPIO drivers.
2	2	GND	✅	Connected to ground, providing the reference for the compensation resistor.

R82 - 110-0001859 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSMRST	✅	100K pull-down resistor connecting PMC_RSMRST to GND. Forms part of an RC network with R83 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R82's value is appropriate for its pull-down function.
2	2	GND	✅	100K pull-down resistor connecting PMC_RSMRST to GND. Forms part of an RC network with R83 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R82's value is appropriate for its pull-down function.

R83 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSMRST	✅	10K pull-up resistor connecting PMC_RSMRST to +3VSB standby power. Forms part of an RC network with R82 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R83's value is appropriate for its pull-up function.
2	2	+3VSB	✅	10K pull-up resistor connecting PMC_RSMRST to +3VSB standby power. Forms part of an RC network with R82 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R83's value is appropriate for its pull-up function.

C49 - 123-0001076 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSMRST	❌	10pF filter capacitor on PMC_RSMRST signal. The capacitance value is insufficient to meet the >10μs RC delay requirement noted on the schematic. Should be increased to approximately 1nF to achieve the required delay with the existing 10K pull-up resistor. Pin 1 connects to PMC_RSMRST net (from schematic) Pin 2 connects to GND net (from schematic) C49 is a 10pF capacitor rated for 50V (from schematic) C49 is located at coordinates (459.74, 279.4) (from schematic) A text note 'RC delay >10us' is present at coordinates (401.32, 287.02), spatially near C49 and its associated resistors (from schematic) The RC time constant with R83 (10K pull-up) is τ = 10,000 × 10×10^-12 = 100ns = 0.1μs (reasoning) The RC time constant with R82 (100K pull-down) is τ = 100,000 × 10×10^-12 = 1μs (reasoning) Neither time constant meets the >10μs requirement stated in the schematic note (reasoning) To achieve a 10μs RC delay with the existing 10K pull-up resistor, C49 should be increased from 10pF to approximately 1nF (1000pF) (reasoning) Alternatively, to achieve 10μs delay with the existing 10pF capacitor, R83 would need to be increased to 1MΩ, but this would be impractical for a pull-up resistor (reasoning) The 10pF value is typical for high-frequency noise filtering but inadequate for creating the required delay (reasoning)
2	2	GND	❌	10pF filter capacitor on PMC_RSMRST signal. The capacitance value is insufficient to meet the >10μs RC delay requirement noted on the schematic. Should be increased to approximately 1nF to achieve the required delay with the existing 10K pull-up resistor. Pin 1 connects to PMC_RSMRST net (from schematic) Pin 2 connects to GND net (from schematic) C49 is a 10pF capacitor rated for 50V (from schematic) C49 is located at coordinates (459.74, 279.4) (from schematic) A text note 'RC delay >10us' is present at coordinates (401.32, 287.02), spatially near C49 and its associated resistors (from schematic) The RC time constant with R83 (10K pull-up) is τ = 10,000 × 10×10^-12 = 100ns = 0.1μs (reasoning) The RC time constant with R82 (100K pull-down) is τ = 100,000 × 10×10^-12 = 1μs (reasoning) Neither time constant meets the >10μs requirement stated in the schematic note (reasoning) To achieve a 10μs RC delay with the existing 10K pull-up resistor, C49 should be increased from 10pF to approximately 1nF (1000pF) (reasoning) Alternatively, to achieve 10μs delay with the existing 10pF capacitor, R83 would need to be increased to 1MΩ, but this would be impractical for a pull-up resistor (reasoning) The 10pF value is typical for high-frequency noise filtering but inadequate for creating the required delay (reasoning)

R59 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_CORE_PWROK	✅	0-ohm resistor connecting PMC_CORE_PWROK from CPU to SYS_PWRGD system power good signal. Provides direct signal propagation with option for isolation if needed during debug or rework.
2	2	SYS_PWRGD	✅	0-ohm resistor connecting PMC_CORE_PWROK from CPU to SYS_PWRGD system power good signal. Provides direct signal propagation with option for isolation if needed during debug or rework.

R236 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_ACPRESENT	✅	Connected to PMC_ACPRESENT signal from CPU1 pin D20.
2	2	+V1P8A	✅	Connected to +V1P8A power rail, providing pull-up voltage for PMC_ACPRESENT.

R183 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S power rail, providing pull-up voltage for GPIO_S5_17.
2	2	GPIO_S5_17	✅	Connected to GPIO_S5_17, which goes to CPU1 pin J24 and jumper J7 pin 1.

R237 - 110-0001875 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S514_J20	✅	Connected to GPIO_S514_J20 signal from CPU1 pin J20 (GPIO_S5_14).
2	2	+V1P8A	✅	Connected to +V1P8A power rail, providing pull-up voltage for GPIO_S5_14.

R256 - 110-0001957 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_BATLOW	✅	Connected to PMC_BATLOW signal from CPU1 pin K26 (active-low battery low indicator).
2	2	+V1P8A	✅	Connected to +V1P8A power rail, providing pull-up voltage for PMC_BATLOW.

R254 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SUSPWRDNACK	✅	Connected to SUSPWRDNACK signal from CPU1 pin D26 (PMC_SUSPWRDNACK).
2	2	+V1P8A	✅	Connected to +V1P8A power rail, providing pull-up voltage for SUSPWRDNACK.

J7 - 258-0002513 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_17	✅	Pin 1 connects to GPIO_S5_17, which is a GPIO pin from the CPU. A 10K pull-up resistor (R183) to +V1P8S is present on this net.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the jumper.

R26 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PWR_BUF1	✅	Pin 1 connects to PWR_BUF1, which supplies power to the VCCB pin of level shifter U19. This connection is correct.
2	2	+3VSB	✅	Pin 2 connects to +3VSB, providing 3.3V standby power through R26 to the level shifter. This connection is correct.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A7	USB_HSIC_RCOMP	USB_HSIC0_RCOMP	✅	USB HSIC compensation resistor connection. Connected to 45.3 ohm resistor R77 to ground.
B4	USB_HSIC0_DATA		✅	USB HSIC0 data and strobe signals. Both pins are unconnected, indicating HSIC0 interface is unused.
B5	USB_HSIC0_STROBE		✅	USB HSIC0 data and strobe signals. Both pins are unconnected, indicating HSIC0 interface is unused.
B12	GPIO_S5_43		✅	GPIO_S5[43] pin, can be configured as USB_ULPI_REFCLK. Currently unconnected.
B20	~USB_OC_11	SOC_USB_HOST_OC1	✅	USB overcurrent detection input for port 1 (active low). Connected through 10K pullup R97 to +V1P8A.
C7	USB_RCOMPI	USB_RCOMP	✅	USB 2.0 compensation resistor connections. Both pins connected to same net USB_RCOMP with 45.3 ohm resistor R185 to ground.
D6	USB_RCOMPO	USB_RCOMP	✅	USB 2.0 compensation resistor connections. Both pins connected to same net USB_RCOMP with 45.3 ohm resistor R185 to ground.
C20	~USB_OC_00	SOC_USB_HOST_OC0	✅	USB overcurrent detection input for port 0 (active low). Connected through 10K pullup R84 to +V1P8A.
D2	USB_HSIC1_STROBE		✅	USB HSIC1 strobe and data signals. Both pins are unconnected, indicating HSIC1 interface is unused.
E2	USB_HSIC1_DATA		✅	USB HSIC1 strobe and data signals. Both pins are unconnected, indicating HSIC1 interface is unused.
D4	USB3_RXP0	USB3_RXP0	✅	USB 3.0 receive differential pair for lane 0. Connected to nets USB3_RXP0 and USB3_RXN0.
E3	USB3_RXN0	USB3_RXN0	✅	USB 3.0 receive differential pair for lane 0. Connected to nets USB3_RXP0 and USB3_RXN0.
D10	ICLK_USB_TERM_1	ICLK_USB_TERM_0	✅	USB clock termination pins have swapped net connections. Pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1, and pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0. While functionally correct since both require identical 1K termination to ground, the net naming violates documentation best practices.
F10	ICLK_USB_TERMN	ICLK_USB_TERM_1	✅	USB clock termination pins have swapped net connections. Pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1, and pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0. While functionally correct since both require identical 1K termination to ground, the net naming violates documentation best practices.
G2	GPIO_S5_31		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
G14	USB_DN1	USB_DN1	✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
H3	GPIO_S5_42		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
H4	RESERVED_H4		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
H5	RESERVED_H5		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
H7	RESERVED_H7		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
H8	RESERVED_H8		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
H10	USB_DN3		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
J3	GPIO_S5_40		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
K2	GPIO_S5_34		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
K3	GPIO_S5_35		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
K10	USB_DP3		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
L1	GPIO_S5_33		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
L3	GPIO_S5_39		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
M2	GPIO_S5_36		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
M3	GPIO_S5_32		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
N3	GPIO_S5_37		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
P2	GPIO_S5_38		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
P3	GPIO_S5_41		✅	GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused.
J12	USB_DN2	USB_HOST_DN	✅	USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP.
J14	USB_DP1	USB_DP1	✅	USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP.
K12	USB_DP2	USB_HOST_DP	✅	USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP.
K16	USB_DN0	USB_DN0	✅	USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP.
M16	USB_DP0	USB_DP0	✅	USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP.
K6	USB3_TXP0	USB3_TXP0	✅	USB 3.0 transmit differential pair for lane 0. Connected to nets USB3_TXP0 and USB3_TXN0.
K7	USB3_TXN0	USB3_TXN0	✅	USB 3.0 transmit differential pair for lane 0. Connected to nets USB3_TXP0 and USB3_TXN0.
M4	RESERVED_M4		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
M6	RESERVED_M6		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
M7	RESERVED_M7		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
M9	RESERVED_M9		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
M10	RESERVED_M10		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
P6	RESERVED_P6		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
P7	RESERVED_P7		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
P10	RESERVED_P10		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
P12	RESERVED_P12		✅	Reserved pins. All unconnected per datasheet guidance for reserved pins.
M12	USB3_REXT0	USB3_REXT0	✅	USB 3.0 external resistor connection. Connected to 1.24K ohm resistor R212 to ground.
M13	USB_PLL_MON	USB_PLL_MON	✅	USB PLL monitor output. Connected to test point TP3 via net USB_PLL_MON.
BC12	GPIO_S0_SC_56	GPIO_S0_SC_56	✅	GPIO_S0_SC[56] pin. Connected to net GPIO_S0_SC_56, function not specified on this page.
BC14	GPIO_S0_SC_58	HDMI_CEC	✅	GPIO_S0_SC[58] pin configured for HDMI CEC function. Connected to net HDMI_CEC.
BC16	GPIO_S0_SC_61	PCU_UART3_RXD	✅	GPIO_S0_SC[61] pin configured as UART3 RX. Connected through level shifter U6 to debug connector J4 pin 4.
BD12	GPIO_S0_SC_55	GPIO_S0_SC_55	✅	GPIO_S0_SC[55] pin. Connected to test point TP8 via net GPIO_S0_SC_55.
BD14	GPIO_S0_SC_57	PCU_UART3_TXD	✅	GPIO_S0_SC[57] pin configured as UART3 TX. Connected through level shifter U6 to debug connector J4 pin 5.
BD16	GPIO_S0_SC_60		✅	GPIO_S0_SC[60] pin. Currently unconnected.
BF14	GPIO_S0_SC_59		✅	GPIO_S0_SC[59] pin. Currently unconnected.
BF18	LPC_RCOMP	LPC_RCOMP	✅	LPC compensation resistor connection. Connected to 49.9 ohm resistor R241 to ground.
BF27	SIO_I2C4_DATA		✅	SIO_I2C4_DATA pin. Currently unconnected, indicating I2C4 interface is unused.
BG11	~PCU_SMB_ALERT	PCU_SMB_ALERT	✅	SMBus alert signal (active low). Connected through 10K pullup R75 to +V1P8S, with optional connection to LAN-SMB-ALERT# through DNI resistor R842.
BG12	PCU_SMB_DATA	PCU_SMB_DATA	✅	SMBus data line. Connected through level shifter U5 to DDR_SMB_DATA with 2.2K pullups on both sides.
BG13	ILB_LPC_SERIRQ		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BG14	ILB_LPC_AD_33		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BG15	ILB_LPC_CLK_00		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BG16	~ILB_LPC_CLKRUN		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BG17	~ILB_LPC_FRAME		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BH14	ILB_LPC_CLK_11		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BH16	ILB_LPC_AD_00		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BJ13	ILB_LPC_AD_22		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BJ17	ILB_LPC_AD_11		✅	LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused.
BG23	SIO_I2C0_CLK		✅	SIO_I2C0_CLK pin. Currently unconnected, indicating I2C0 interface is unused.
BG24	SIO_I2C1_DATA	SIO_I2C1_SDA	✅	I2C1 data line. Connected to test point TP6 via net SIO_I2C1_SDA.
BG25	SIO_I2C2_DATA		✅	SIO_I2C2_DATA pin. Currently unconnected, indicating I2C2 interface is unused.
BG26	SIO_I2C3_DATA		✅	SIO_I2C3_DATA pin. Currently unconnected, indicating I2C3 interface is unused.
BG27	SIO_I2C4_CLK		✅	SIO_I2C4_CLK pin. Currently unconnected, indicating I2C4 interface is unused.
BG28	SIO_I2C5_CLK	SI0_I2C5_SCL	✅	I2C5 clock line. Connected through 22 ohm series resistor R270 to I2C5_SCL.
BG29	SIO_I2C6_CLK	SI0_I2C6_SCL	✅	I2C6 clock line. Connected through 22 ohm series resistor R12 to I2C6_SCL.
BG30	GPIO_S0_SC_093	TP10_NET	✅	GPIO_S0_SC[93] pin. Connected to TP10_NET which is grounded through 0-ohm resistor R261.
BH10	PCU_SMB_CLK	PCU_SMB_CLK	✅	SMBus clock line. Connected through level shifter U5 to DDR_SMB_CLK with 2.2K pullups on both sides.
BH12	ILB_8254_SPKR	ILB_8254_SPKR	✅	Speaker output pin. Connected to net ILB_8254_SPKR, destination not shown on this page.
BH22	SIO_I2C0_DATA		✅	SIO_I2C0_DATA pin. Currently unconnected, indicating I2C0 interface is unused.
BH24	SIO_I2C1_CLK	SIO_I2C1_SCL	✅	I2C1 clock line. Connected to test point TP5 via net SIO_I2C1_SCL.
BH26	SIO_I2C3_CLK		✅	SIO_I2C3_CLK pin. Currently unconnected, indicating I2C3 interface is unused.
BH28	SIO_I2C5_DATA	SI0_I2C5_SDA	✅	I2C5 data line. Connected through 22 ohm series resistor R269 to I2C5_SDA.
BH30	GPIO_S0_SC_092	TP9_NET	✅	GPIO_S0_SC[92] pin. Connected to TP9_NET which is grounded through 0-ohm resistor R243.
BJ13	ILB_LPC_AD_22		✅	LPC address/data bit 2 signal. Currently unconnected, indicating LPC interface is unused.
BJ25	SIO_I2C2_CLK		✅	SIO_I2C2_CLK pin. Currently unconnected, indicating I2C2 interface is unused.
BJ29	SIO_I2C6_DATA	SI0_I2C6_SDA	✅	I2C6 data line. Connected through 22 ohm series resistor R11 to I2C6_SDA.

U5 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DDR_SMB_CLK	✅	B2 pin correctly connected to DDR_SMB_CLK with appropriate 2.2K pull-up to +VCC3 through R44.
2	GND	GND	✅	GND pin correctly connected to system ground.
3	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V) supply rail for A-side reference voltage.
4	A2	PCU_SMB_CLK	✅	A2 pin correctly connected to PCU_SMB_CLK with appropriate 2.2K pull-up to +V1P8S through R45.
5	A1	PCU_SMB_DATA	✅	A1 pin correctly connected to PCU_SMB_DATA with appropriate 2.2K pull-up to +V1P8S through R177.
6	OE	PCU_SMB_BUFF_ENB	✅	OE pin correctly connected to PCU_SMB_BUFF_ENB with 2.2K pull-up to +V1P8S through R49, enabling the device by default.
7	VCCB	BUF2_PWR	✅	VCCB pin correctly connected to BUF2_PWR, which connects to +VCC3 (3.3V) through 0-ohm resistor R48.
8	B1	DDR_SMB_DATA	✅	B1 pin correctly connected to DDR_SMB_DATA with appropriate 2.2K pull-up to +VCC3 through R47.

U6 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DBG_UART3_TXD	✅	UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication.
4	A2	PCU_UART3_TXD	✅	UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication.
5	A1	PCU_UART3_RXD	✅	UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication.
8	B1	DBG_UART3_RXD	✅	UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication.
2	GND	GND	✅	GND pin correctly connected to ground plane.
3	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V supply) with local decoupling.
6	OE	LSENB	✅	OE pin correctly connected to LSENB with pull-up to +V1P8S, enabling control of the level translator.
7	VCCB	BUF3_PWR	✅	VCCB pin correctly connected to BUF3_PWR (3.3V standby supply) with local decoupling.

J4 - 258-0004869 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 correctly connected to GND, providing ground reference for the serial cable.
2	2		✅	Pins 2, 3, and 6 are not connected. This is acceptable for a minimal UART interface that only requires GND, TX, and RX.
3	3		✅	Pins 2, 3, and 6 are not connected. This is acceptable for a minimal UART interface that only requires GND, TX, and RX.
6	6		✅	Pins 2, 3, and 6 are not connected. This is acceptable for a minimal UART interface that only requires GND, TX, and RX.
4	4	DBG_UART3_RXD	✅	Pin 4 correctly connected to DBG_UART3_RXD. This is where the board receives data from the debug cable's transmit line at 3.3V levels.
5	5	DBG_UART3_TXD_R	✅	Pin 5 correctly connected to DBG_UART3_TXD_R. This is where the board transmits data to the debug cable's receive line at 3.3V levels.

R51 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BUF3_PWR	✅	0 ohm resistor correctly connects BUF3_PWR to +3VSB, providing power to the B-side of level translator U6. The 0 ohm value allows for easy power measurement or disconnection.
2	2	+3VSB	✅	0 ohm resistor correctly connects BUF3_PWR to +3VSB, providing power to the B-side of level translator U6. The 0 ohm value allows for easy power measurement or disconnection.

R52 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LSENB	✅	2.2K ohm pull-up resistor correctly pulls LSENB to +V1P8S, enabling level translator U6 by default while allowing external control.
2	2	+V1P8S	✅	2.2K ohm pull-up resistor correctly pulls LSENB to +V1P8S, enabling level translator U6 by default while allowing external control.

R75 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	10K ohm pull-up resistor correctly pulls PCU_SMB_ALERT to +V1P8S. This is appropriate for the open-drain SMBus ALERT signal.
2	2	PCU_SMB_ALERT	✅	10K ohm pull-up resistor correctly pulls PCU_SMB_ALERT to +V1P8S. This is appropriate for the open-drain SMBus ALERT signal.

R819 - 110-0002000 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DBG_UART3_TXD	✅	330 ohm series resistor correctly provides current limiting and protection for the UART transmit signal going to the external debug connector.
2	2	DBG_UART3_TXD_R	✅	330 ohm series resistor correctly provides current limiting and protection for the UART transmit signal going to the external debug connector.

R270 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SCL	✅	Series resistor input connected to CPU I2C5 clock line. This resistor provides signal integrity and protection for the I2C5 SCL line.
2	2	I2C5_SCL	✅	Series resistor output connected to external I2C5 SCL bus. This provides the buffered I2C clock signal to external devices.

R11 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SDA	✅	Series resistor input connected to CPU I2C6 data line. This resistor provides signal integrity and protection for the I2C6 SDA line.
2	2	I2C6_SDA	✅	Series resistor output connected to external I2C6 SDA bus. This provides the buffered I2C data signal to external devices.

R12 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SCL	✅	Series resistor input connected to CPU I2C6 clock line. This resistor provides signal integrity and protection for the I2C6 SCL line.
2	2	I2C6_SCL	✅	Series resistor output connected to external I2C6 SCL bus. This provides the buffered I2C clock signal to external devices.

R269 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SDA	✅	Series resistor input connected to CPU I2C5 data line. This resistor provides signal integrity and protection for the I2C5 SDA line.
2	2	I2C5_SDA	✅	Series resistor output connected to external I2C5 SDA bus. This provides the buffered I2C data signal to external devices.

R212 - 110-0004478 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_REXT0	✅	1.24K ohm resistor connected between USB3_REXT0 (CPU pin M12) and ground for USB 3.0 impedance calibration.
2	2	GND	✅	1.24K ohm resistor connected between USB3_REXT0 (CPU pin M12) and ground for USB 3.0 impedance calibration.

R77 - 110-0004472 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU pin A7) and ground for USB HSIC impedance calibration.
2	2	USB_HSIC0_RCOMP	✅	45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU pin A7) and ground for USB HSIC impedance calibration.

R185 - 110-0004472 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	45.3 ohm resistor connected between USB_RCOMP (CPU pins D6 and C7) and ground for USB 2.0 impedance calibration.
2	2	USB_RCOMP	✅	45.3 ohm resistor connected between USB_RCOMP (CPU pins D6 and C7) and ground for USB 2.0 impedance calibration.

R241 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPC_RCOMP	✅	49.9 ohm resistor connected between LPC_RCOMP (CPU pin BF18) and ground for LPC bus impedance calibration.
2	2	GND	✅	49.9 ohm resistor connected between LPC_RCOMP (CPU pin BF18) and ground for LPC bus impedance calibration.

R840 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_DATA	✅	Pin 1 connects to DDR_SMB_DATA, which is the 3.3V level-shifted SMBus data signal from level shifter U5. This 0 ohm jumper allows the CPU's SMBus data line to be routed to the LAN controller.
2	2	LAN-SMB-DATA	✅	Pin 2 connects to LAN-SMB-DATA, which routes the SMBus data signal to a LAN controller (likely on another page). This completes the SMBus data path from CPU to LAN controller.

R842 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-SMB-ALERT#	✅	Pin 1 connects to LAN-SMB-ALERT#, which is the active-low SMBus alert signal from a LAN controller. This 0 ohm jumper allows the LAN's alert signal to be routed to the CPU.
2	2	PCU_SMB_ALERT	✅	Pin 2 connects to PCU_SMB_ALERT, which routes to the CPU's active-low SMBus alert input. The signal has a 10K pullup to +V1P8S through R75.

R841 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_CLK	✅	Pin 1 connects to DDR_SMB_CLK, which is the 3.3V level-shifted SMBus clock signal from level shifter U5. This 0 ohm jumper allows the CPU's SMBus clock line to be routed to the LAN controller.
2	2	LAN-SMB-CLK	✅	Pin 2 connects to LAN-SMB-CLK, which routes the SMBus clock signal to a LAN controller (likely on another page). This completes the SMBus clock path from CPU to LAN controller.

R97 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pin 1 is connected to +V1P8A power rail, providing the pull-up voltage for the USB overcurrent detection signal.
2	2	SOC_USB_HOST_OC1	✅	Pin 2 is connected to SOC_USB_HOST_OC1, an active-low USB overcurrent detection signal from the CPU.

R84 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pin 1 is connected to +V1P8A power rail, providing the pull-up voltage for the USB overcurrent detection signal.
2	2	SOC_USB_HOST_OC0	✅	Pin 2 is connected to SOC_USB_HOST_OC0, an active-low USB overcurrent detection signal from the CPU.

TP1 - TEST_POINT_0.040_SMT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$9N613	✅	Test point correctly connected to CPU1 pin AF30 (TP_CORE_V1P05_S4) for monitoring the 1.05V core voltage rail in S4 power state.

TP2 - TEST_POINT_0.040_SMT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$9N615	✅	Test point correctly connected to CPU1 pin AA22 (TP2_CORE_VCC_S0IX) for monitoring the core VCC voltage rail in S0IX power state.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A48	DRAM_VDD_S4	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AK38	DRAM_VDD_S4_AK38	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AM38	DRAM_VDD_S4_AM38	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AV41	DRAM_VDD_S4_AV41	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AV42	DRAM_VDD_S4_AV42	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BB46	DRAM_VDD_S4_BB46	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BD49	DRAM_VDD_S4_BD49	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BD52	DRAM_VDD_S4_BD52	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BD53	DRAM_VDD_S4_BD53	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BF44	DRAM_VDD_S4_BF44	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BG51	DRAM_VDD_S4_BG51	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BJ48	DRAM_VDD_S4_BJ48	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
C51	DRAM_VDD_S4_C51	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
D44	DRAM_VDD_S4_D44	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
F49	DRAM_VDD_S4_F49	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
F52	DRAM_VDD_S4_F52	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
F53	DRAM_VDD_S4_F53	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
H46	DRAM_VDD_S4_H46	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
M41	DRAM_VDD_S4_M41	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
M42	DRAM_VDD_S4_M42	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
V38	DRAM_VDD_S4_V38	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
Y38	DRAM_VDD_S4_Y38	+VDIMM	✅	DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
N28	CORE_VSS_SENSE_N28	VSS_SENSE	✅	CORE_VSS_SENSE ground sense pin connected to VSS_SENSE net for voltage regulator ground reference.
P26	CORE_VCC_S0IX_P26	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
P27	CORE_VCC_S0IX_P27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
U27	CORE_VCC_S0IX_U27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
U29	CORE_VCC_S0IX_U29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
V27	CORE_VCC_S0IX_V27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
V29	CORE_VCC_S0IX_V29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
V30	CORE_VCC_S0IX_V30	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
Y27	CORE_VCC_S0IX_Y27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
Y29	CORE_VCC_S0IX_Y29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
Y30	CORE_VCC_S0IX_Y30	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AA27	CORE_VCC_S0IX_AA27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AA29	CORE_VCC_S0IX_AA29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AA30	CORE_VCC_S0IX_AA30	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AC27	CORE_VCC_S0IX_AC27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AC29	CORE_VCC_S0IX_AC29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AC30	CORE_VCC_S0IX_AC30	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AD27	CORE_VCC_S0IX_AD27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AD29	CORE_VCC_S0IX_AD29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AD30	CORE_VCC_S0IX_AD30	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AF27	CORE_VCC_S0IX_AF27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AF29	CORE_VCC_S0IX_AF29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AG27	CORE_VCC_S0IX_AG27	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AG29	CORE_VCC_S0IX_AG29	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
AG30	CORE_VCC_S0IX_AG30	+VCORE	✅	CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores.
P28	CORE_VCC_SENSE_P28	VCC_SENSE	✅	CORE_VCC_SENSE voltage sense pin connected to VCC_SENSE net for voltage regulator feedback.
AA22	TP2_CORE_VCC_S0IX	$9N615	✅	TP2_CORE_VCC_S3 test point pin connected to test point TP2 for monitoring core voltage.
AA24	UNCORE_VNN_S3_AA24	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AC22	UNCORE_VNN_S3_AC22	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AC24	UNCORE_VNN_S3_AC24	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AD22	UNCORE_VNN_S3_AD22	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AD24	UNCORE_VNN_S3_AD24	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AF22	UNCORE_VNN_S3_AF22	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AF24	UNCORE_VNN_S3_AF24	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AG22	UNCORE_VNN_S3_AG22	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AG24	UNCORE_VNN_S3_AG24	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AJ22	UNCORE_VNN_S3_AJ22	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AJ24	UNCORE_VNN_S3_AJ24	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AK22	UNCORE_VNN_S3_AK22	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AK24	UNCORE_VNN_S3_AK24	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AK25	UNCORE_VNN_S3_AK25	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AK27	UNCORE_VNN_S3_AK27	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AK29	UNCORE_VNN_S3_AK29	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AK30	UNCORE_VNN_S3_AK30	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AK32	UNCORE_VNN_S3_AK32	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
AM22	UNCORE_VNN_S3_AM22	+VGFX	✅	UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic.
BB8	UNCORE_VNN_SENSE	VCCGT_SENSE	✅	UNCORE_VNN_SENSE voltage sense pin connected to VCCGT_SENSE net for voltage regulator feedback.
AD38	DRAM_VDD_S4_AD38	DRAM_VDD_CLK	✅	DRAM_VDD_S4 power supply pins connected to DRAM_VDD_CLK rail. This is a separate power rail for DDR clock circuitry derived from +VDIMM through a 0-ohm resistor with dedicated decoupling.
AF38	DRAM_VDD_S4_AF38	DRAM_VDD_CLK	✅	DRAM_VDD_S4 power supply pins connected to DRAM_VDD_CLK rail. This is a separate power rail for DDR clock circuitry derived from +VDIMM through a 0-ohm resistor with dedicated decoupling.
AF30	TP_CORE_V1P05_S4	$9N613	✅	TP_CORE_V1P05_S4 test point pin connected to test point TP1 for monitoring 1.05V core voltage.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A3	VSS_A3_A3	GND	✅	VSS ground pins connected to GND.
A5	VSS_A5_A5	GND	✅	VSS ground pins connected to GND.
A6	VSS_A6_A6	GND	✅	VSS ground pins connected to GND.
A49	VSS_A49_A49	GND	✅	VSS ground pins connected to GND.
A51	VSS_A51_A51	GND	✅	VSS ground pins connected to GND.
A52	VSS_A52_A52	GND	✅	VSS ground pins connected to GND.
B2	VSS_B2_B2	GND	✅	VSS ground pins connected to GND.
B52	VSS_B52_B52	GND	✅	VSS ground pins connected to GND.
B53	VSS_B53_B53	GND	✅	VSS ground pins connected to GND.
BE1	VSS_BE1_BE1	GND	✅	VSS ground pins connected to GND.
BE53	VSS_BE53_BE53	GND	✅	VSS ground pins connected to GND.
BG1	VSS_BG1_BG1	GND	✅	VSS ground pins connected to GND.
BG53	VSS_BG53_BG53	GND	✅	VSS ground pins connected to GND.
BH1	VSS_BH1_BH1	GND	✅	VSS ground pins connected to GND.
BH2	VSS_BH2_BH2	GND	✅	VSS ground pins connected to GND.
BH52	VSS_BH52_BH52	GND	✅	VSS ground pins connected to GND.
BH53	VSS_BH53_BH53	GND	✅	VSS ground pins connected to GND.
BJ2	VSS_BJ2_BJ2	GND	✅	VSS ground pins connected to GND.
BJ3	VSS_BJ3_BJ3	GND	✅	VSS ground pins connected to GND.
BJ5	VSS_BJ5_BJ5	GND	✅	VSS ground pins connected to GND.
BJ49	VSS_BJ49_BJ49	GND	✅	VSS ground pins connected to GND.
BJ51	VSS_BJ51_BJ51	GND	✅	VSS ground pins connected to GND.
BJ52	VSS_BJ52_BJ52	GND	✅	VSS ground pins connected to GND.
C1	VSS_C1_C1	GND	✅	VSS ground pins connected to GND.
C53	VSS_C53_C53	GND	✅	VSS ground pins connected to GND.
E1	VSS_E1_E1	GND	✅	VSS ground pins connected to GND.
E53	VSS_E53_E53	GND	✅	VSS ground pins connected to GND.
B6	UNCORE_V1P0_G3_B6	+V1P0A	✅	UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement.
C5	UNCORE_V1P0_G3_C5	+V1P0A	✅	UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement.
U22	UNCORE_V1P0_G3_U22	+V1P0A	✅	UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement.
V22	UNCORE_V1P0_G3_V22	+V1P0A	✅	UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement.
C3	USB3_V1P0_G3_C3	+V1P0A	✅	USB3_V1P0_G3 power pins connected to +V1P0A.
Y19	USB3_V1P0_G3_Y19	+V1P0A	✅	USB3_V1P0_G3 power pins connected to +V1P0A.
F1	RESERVED_F1	$10N1595	✅	RESERVED pin connected to test point TP4 (DNI). Acceptable for debugging purposes.
M14	USB_V1P0_S3_M14	+V1P0S	✅	USB_V1P0_S3 power pins connected to +V1P0S.
U18	USB_V1P0_S3_U18	+V1P0S	✅	USB_V1P0_S3 power pins connected to +V1P0S.
U19	USB_V1P0_S3_U19	+V1P0S	✅	USB_V1P0_S3 power pins connected to +V1P0S.
N18	USB_V3P3_G3_N18	+3VSB	✅	USB_V3P3_G3 power pins connected to +3VSB.
P18	USB_V3P3_G3_P18	+3VSB	✅	USB_V3P3_G3 power pins connected to +3VSB.
N20	USB_V1P8_G3_N20	+V1P8A	✅	USB_V1P8_G3 power pin connected to +V1P8A.
N22	PCU_V3P3_G3_N22	+3VSB	✅	PCU_V3P3_G3 power pin connected to +3VSB with 55mA current requirement.
P22	RTC_VCC_P22	+RTCVCC	✅	RTC_VCC power pin connected to +RTCVCC with 160uA current requirement.
U16	USB_VSSA_U16	GND	✅	USB_VSSA analog ground pin connected to GND.
U24	UNCORE_V1P8_G3_U24	+V1P8A	✅	UNCORE_V1P8_G3 power pins connected to +V1P8A.
AA18	UNCORE_V1P8_G3_AA18	+V1P8A	✅	UNCORE_V1P8_G3 power pins connected to +V1P8A.
U25	PMU_V1P8_G3_U25	+V1P8A	✅	PMU_V1P8_G3 power pin connected to +V1P8A.
V18	USB_HSIC_V1P24_G3_V18	+V1P0A	✅	USB_HSIC_V1P24_G3 power pin connected to +V1P0A instead of V1P24A. Text note indicates this is intentional because USB HSIC is not used.
V24	UNCORE_V1P0_S0IX_V24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering.
Y24	UNCORE_V1P0_S0IX_Y24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering.
Y22	UNCORE_V1P0_S0IX_Y22	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering.
AN29	UNCORE_V1P0_S0IX_AN29	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering.
AN30	UNCORE_V1P0_S0IX_AN30	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering.
V25	PCU_V1P8_G3_V25	+V1P8A	✅	PCU_V1P8_G3 power pin connected to +V1P8A with 65mA current requirement.
V32	SVID_V1P0_S3_V32	+V1P0S	✅	SVID_V1P0_S3 power pin connected to +V1P0S.
AA25	UNCORE_V1P35_S0IX_F5_AA25	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement.
AF19	UNCORE_V1P35_S0IX_F6	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement.
V36	UNCORE_V1P35_S0IX_F3_V36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement.
U36	UNCORE_V1P35_S0IX_F4_U36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement.
AG32	UNCORE_V1P35_S0IX_F2_AG32	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement.
AG19	UNCORE_V1P35_S0IX_F1_AG19	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement.
AA36	DRAM_V1P0_S0IX_AA36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
AD35	DRAM_V1P0_S0IX_AD35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
AF35	DRAM_V1P0_S0IX_AF35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
AF36	DRAM_V1P0_S0IX_AF36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
AJ36	DRAM_V1P0_S0IX_AJ36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
AK35	DRAM_V1P0_S0IX_AK35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
AK36	DRAM_V1P0_S0IX_AK36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
Y35	DRAM_V1P0_S0IX_Y35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
Y36	DRAM_V1P0_S0IX_Y36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering.
AC32	CORE_V1P05_S3_AC32	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
Y32	CORE_V1P05_S3_Y32	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
AA33	CORE_V1P05_S3_AA33	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
AF33	CORE_V1P05_S3_AF33	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
AG33	CORE_V1P05_S3_AG33	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
AG35	CORE_V1P05_S3_AG35	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
U33	CORE_V1P05_S3_U33	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
U35	CORE_V1P05_S3_U35	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
V33	CORE_V1P05_S3_V33	+V1P0S	✅	CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified.
AD16	VSS_AD16	VCC_VSS_V1P2	✅	MIPI_V1P24_S3 power pins connected to VCC_VSS_V1P2 which is grounded through R216. Text note indicates CSI is not used, so grounding is intentional and correct.
AD18	VSS_AD18	VCC_VSS_V1P2	✅	MIPI_V1P24_S3 power pins connected to VCC_VSS_V1P2 which is grounded through R216. Text note indicates CSI is not used, so grounding is intentional and correct.
AD36	DRAM_V1P35_S0IX_F1_AD36	VCC_UNCORE_V1P35	✅	DRAM_V1P35_S0IX_F1 power pin connected to VCC_UNCORE_V1P35, same 1.35V rail as UNCORE pins.
BD1	VGA_V1P35_S3_F1_BD1	VCC_CRT_V1P35	✅	VGA_V1P35_S3_F1 power pin connected to VCC_CRT_V1P35 through ferrite bead FB4 from +V1P35S with 45mA current requirement.
AF16	UNCORE_V1P0_S3_AF16	+V1P0S	✅	UNCORE_V1P0_S3 power pins connected to +V1P0S.
AF18	UNCORE_V1P0_S3_AF18	+V1P0S	✅	UNCORE_V1P0_S3 power pins connected to +V1P0S.
G1	UNCORE_V1P0_S3_G1	+V1P0S	✅	UNCORE_V1P0_S3 power pins connected to +V1P0S.
Y18	UNCORE_V1P0_S3_Y18	+V1P0S	✅	UNCORE_V1P0_S3 power pins connected to +V1P0S.
AF21	UNCORE_V1P0_S0IX_AF21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0, same rail as pins V24, Y24, Y22, AN29, AN30.
AG21	UNCORE_V1P0_S0IX_AG21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0, same rail as pins V24, Y24, Y22, AN29, AN30.
AJ18	DDI_V1P0_S0IX_AJ18	+V1P0S	✅	DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current.
AK19	DDI_V1P0_S0IX_AK19	+V1P0S	✅	DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current.
AK21	DDI_V1P0_S0IX_AK21	+V1P0S	✅	DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current.
AM16	DDI_V1P0_S0IX_AM16	+V1P0S	✅	DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current.
AJ19	ICLK_V1P35_S3_F1_AJ19	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 power pins connected to VCC_ICLK_V1P35 through ferrite bead FB5 from +V1P35S with 350mA current requirement.
AG18	ICLK_V1P35_S3_F2	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 power pins connected to VCC_ICLK_V1P35 through ferrite bead FB5 from +V1P35S with 350mA current requirement.
BJ6	VGA_V1P0_S3_BJ6	+V1P0S	✅	VGA_V1P0_S3 power pin connected to +V1P0S with 900mA current requirement.
AM27	LPC_V1P8V3P3_S3_AM27	+VCC3S	✅	LPC_V1P8V3P3_S3 power pin connected to +VCC3S. Datasheet allows either 1.8V or 3.3V.
AM30	UNCORE_V1P8_S3_AM30	+V1P8S	✅	UNCORE_V1P8_S3 power pins connected to +V1P8S.
AN32	UNCORE_V1P8_S3_AN32	+V1P8S	✅	UNCORE_V1P8_S3 power pins connected to +V1P8S.
U38	UNCORE_V1P8_S3_U38	+V1P8S	✅	UNCORE_V1P8_S3 power pins connected to +V1P8S.
AM32	HDA_LPE_V1P5V1P8_S3_AM32	+V1P8S	✅	HDA_LPE_V1P5V1P8_S3 power pin connected to +V1P8S with 10mA current requirement. Datasheet allows either 1.5V or 1.8V.
AN16	VSSA_AN16	GND	✅	VSSA analog ground pin connected to GND.
AN18	PCIE_SATA_V1P0_S3_AN18	+V1P0S	✅	PCIE_SATA_V1P0_S3 power pin connected to +V1P0S.
AN19	SATA_V1P0_S3_AN19	+V1P0S	✅	SATA_V1P0_S3 power pin connected to +V1P0S.
AN21	PCIE_V1P0_S3_AN21	+V1P0S	✅	PCIE_V1P0_S3 power pins connected to +V1P0S.
AM21	PCIE_V1P0_S3_AM21	+V1P0S	✅	PCIE_V1P0_S3 power pins connected to +V1P0S.
AM18	PCIE_V1P0_S3_AM18	+V1P0S	✅	PCIE_V1P0_S3 power pins connected to +V1P0S.
AK18	PCIE_V1P0_S3_AK18	+V1P0S	✅	PCIE_V1P0_S3 power pins connected to +V1P0S.
AN24	VGA_V3P3_S3_AN24	+VCC3S	✅	VGA_V3P3_S3 power pin connected to +VCC3S.
AN25	GPIO_V1P0_S3_AN25	+V1P0S	✅	GPIO_V1P0_S3 power pin connected to +V1P0S with 45mA current requirement.
AN27	SD3_V1P8V3P3_S3_AN27	+VCC3S	✅	SD3_V1P8V3P3_S3 power pin connected to +VCC3S. Datasheet allows either 1.8V or 3.3V.

FB3 - FERRITE_600OHM_1.3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to +V1P35S source rail. This is the standard input configuration for a ferrite bead filter.
2	2	VCC_UNCORE_V1P35	✅	Output pin connected to VCC_UNCORE_V1P35 filtered rail. This rail supplies multiple CPU pins and has appropriate decoupling capacitors.

FB4 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to +V1P35S source rail. This is the standard input configuration for a ferrite bead filter.
2	2	VCC_CRT_V1P35	✅	Output pin connected to VCC_CRT_V1P35 filtered rail. This rail supplies CPU1 pin BD1 and has appropriate bulk decoupling capacitors.

FB5 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to +V1P35S source rail. This is the standard input configuration for a ferrite bead filter.
2	2	VCC_ICLK_V1P35	✅	Output pin connected to VCC_ICLK_V1P35 filtered rail. This rail supplies CPU1 clock-related pins and has appropriate decoupling capacitors.

R265 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	0-ohm jumper connecting +V1P0S main supply to VCC_DRAM rail which powers DRAM interface pins on the CPU. This is a standard power distribution design allowing separate decoupling for the DRAM interface.
2	2	VCC_DRAM	✅	0-ohm jumper connecting +V1P0S main supply to VCC_DRAM rail which powers DRAM interface pins on the CPU. This is a standard power distribution design allowing separate decoupling for the DRAM interface.

R222 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	0-ohm jumper connecting +V1P0S main supply to VCC_VIS_V1P0 rail which powers vision-related uncore logic pins on the CPU. This is a standard power distribution design allowing separate decoupling for the vision subsystem.
2	2	VCC_VIS_V1P0	✅	0-ohm jumper connecting +V1P0S main supply to VCC_VIS_V1P0 rail which powers vision-related uncore logic pins on the CPU. This is a standard power distribution design allowing separate decoupling for the vision subsystem.

R216 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VSS_V1P2	✅	0-ohm jumper connecting CPU VSS pins (AD16, AD18) to ground. The connection is functionally correct, though the net name VCC_VSS_V1P2 is confusing as it suggests a power rail rather than a ground connection.
2	2	GND	✅	0-ohm jumper connecting CPU VSS pins (AD16, AD18) to ground. The connection is functionally correct, though the net name VCC_VSS_V1P2 is confusing as it suggests a power rail rather than a ground connection.

C28 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, which is correct for a decoupling capacitor.
2	2	VCC_CRT_V1P35	✅	Pin 2 is connected to VCC_CRT_V1P35, which supplies power to CPU1 pin BD1 through ferrite bead FB4 from the +V1P35S rail.

C164 - 22uF 20% 6.3V 0805 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, which is correct for a decoupling capacitor.
2	2	VCC_CRT_V1P35	✅	Pin 2 is connected to VCC_CRT_V1P35, which supplies power to CPU1 pin BD1 through ferrite bead FB4 from the +V1P35S rail.

C224 - 22uF 20% 6.3V 0805 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VIS_V1P0	✅	Pin 1 is correctly connected to VCC_VIS_V1P0 power rail for decoupling.
2	2	GND	✅	Pin 2 is correctly connected to GND for decoupling.

C225 - 22uF 20% 6.3V 0805 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VIS_V1P0	✅	Pin 1 is correctly connected to VCC_VIS_V1P0 power rail for decoupling.
2	2	GND	✅	Pin 2 is correctly connected to GND for decoupling.

C201 - 22uF 20% 6.3V 0805 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VIS_V1P0	✅	Pin 1 is correctly connected to VCC_VIS_V1P0 power rail for decoupling.
2	2	GND	✅	Pin 2 is correctly connected to GND for decoupling.

D7 - D5V0L1B2LP-7B ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Pin N is connected to GND and serves as the ground reference for the bidirectional TVS diode.
P	P	+5VSB	✅	Pin P is connected to the +5VSB rail being protected by this bidirectional TVS diode.

J8 - 3430-0212 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to the +5VSB power rail and serves as the power input terminal of the connector.
2	2	GND	✅	Pin 2 is connected to GND and serves as the ground return terminal of the connector.

C153 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to the +5VSB rail and serves as the positive terminal of the decoupling capacitor.
2	2	GND	✅	Pin 2 is connected to GND and serves as the ground return for the decoupling capacitor.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A11	VSS1	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A15	VSS2	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A19	VSS3	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A23	VSS4	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A27	VSS5	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A31	VSS6	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A35	VSS7	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A39	VSS8	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A43	VSS9	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
A47	VSS10	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA1	VSS11	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA3	VSS15	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA16	VSS12	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA19	VSS13	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA21	VSS14	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA32	VSS16	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA35	VSS17	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA38	VSS18	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AA53	VSS19	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB4	VSS21	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB6	VSS28	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB10	VSS20	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB41	VSS22	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB45	VSS23	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB47	VSS24	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB48	VSS25	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB50	VSS26	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AB51	VSS27	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC16	VSS29	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC18	VSS30	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC19	VSS31	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC21	VSS32	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC25	VSS33	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC33	VSS34	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC35	VSS35	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC36	VSS36	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AC38	VSS37	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AD7	VSS44	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AD19	VSS38	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AD21	VSS39	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AD25	VSS40	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AD32	VSS41	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AD33	VSS42	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AD47	VSS43	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE1	VSS45	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE3	VSS49	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE4	VSS50	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE6	VSS60	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE8	VSS61	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE9	VSS62	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE11	VSS46	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE12	VSS47	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE14	VSS48	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE40	VSS51	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE42	VSS52	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE43	VSS53	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE45	VSS54	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE46	VSS55	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE48	VSS56	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE50	VSS57	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE51	VSS58	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE53	VSS59	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE60			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AE62			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AF10	VSS63	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AF12	VSS64	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AF25	VSS65	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AF32	VSS66	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AF47	VSS67	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AG16	VSS68	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AG25	VSS69	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AG36	VSS70	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AG38	VSS71	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH4	VSS72	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH6	VSS110	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH7	VSS75	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH9	VSS76	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH41	VSS73	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH45	VSS74	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH47	VSS106	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH48	VSS107	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH50	VSS108	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AH51	VSS109	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ1	VSS77	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ3	VSS83	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ16	VSS78	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ21	VSS79	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ25	VSS80	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ27	VSS81	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ29	VSS82	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ30	VSS84	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ32	VSS85	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ33	VSS86	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ35	VSS87	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ38	VSS88	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AJ53	VSS89	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AK10	VSS90	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AK14	VSS91	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AK16	VSS92	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AK33	VSS93	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AK41	VSS94	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AK44	VSS95	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM7	VSS113	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM12	VSS96	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM19	VSS97	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM24	VSS98	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM25	VSS99	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM29	VSS100	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM33	VSS101	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM35	VSS102	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM36	VSS103	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM40	VSS104	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM44	VSS111	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AM51	VSS112	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN1	VSS114	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN3	VSS119	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN5	VSS131	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN6	VSS134	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN8	VSS135	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN9	VSS136	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN11	VSS115	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN12	VSS116	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN14	VSS117	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN22	VSS118	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN33	VSS120	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN35	VSS121	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN36	VSS122	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN38	VSS123	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN40	VSS124	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN42	VSS125	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN43	VSS126	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN45	VSS127	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN46	VSS128	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN48	VSS129	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN49	VSS130	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN51	VSS132	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AN53	VSS133	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AP40	VSS137	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT4	VSS146	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT12	VSS138	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT16	VSS139	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT19	VSS140	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT24	VSS141	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT27	VSS142	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT30	VSS143	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT35	VSS144	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT38	VSS145	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT47	VSS147	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AT52	VSS148	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AU1	VSS149	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AU3	VSS151	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AU24	VSS150	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AU30	VSS152	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AU38	VSS153	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AU51	VSS154	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV7	VSS167	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV12	VSS155	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV13	VSS156	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV14	VSS157	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV18	VSS158	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV19	VSS159	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV24	VSS160	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV27	VSS161	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV30	VSS162	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV35	VSS163	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV38	VSS164	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV47	VSS165	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AV51	VSS166	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AW3	VSS171	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AW13	VSS168	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AW19	VSS169	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AW27	VSS170	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AW35	VSS172	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AY4	VSS177	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AY9	VSS179	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AY10	VSS173	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AY22	VSS174	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AY32	VSS175	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AY36	VSS176	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
AY50	VSS178	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA14	VSS180	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA19	VSS181	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA22	VSS182	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA27	VSS183	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA32	VSS184	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA35	VSS185	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA40	VSS186	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BA53	VSS187	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BB19	VSS188	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BB27	VSS189	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BB35	VSS190	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BC20	VSS191	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BC22	VSS192	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BC26	VSS193	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BC28	VSS194	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BC32	VSS195	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BC34	VSS196	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BC42	VSS197	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BD19	VSS198	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BD24	VSS199	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BD27	VSS200	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BD30	VSS201	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BD35	VSS202	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BE2	VSS204	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BE8	VSS206	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BE19	VSS203	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BE35	VSS205	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BF4	VSS213	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BF12	VSS207	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BF16	VSS208	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BF24	VSS209	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BF30	VSS211	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BF36	VSS212	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BF38	VSS210	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BG31	VSS214	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BG34	VSS215	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BG39	VSS216	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BG42	VSS217	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BG45	VSS218	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BG49	VSS219	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ7	VSS230	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ11	VSS220	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ15	VSS221	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ19	VSS222	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ23	VSS223	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ27	VSS224	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ31	VSS225	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ35	VSS226	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ39	VSS227	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ43	VSS228	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
BJ47	VSS229	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
C14	VSS231	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
C31	VSS232	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
C34	VSS233	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
C39	VSS234	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
C42	VSS235	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
C45	VSS236	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
C49	VSS237	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
D12	VSS238	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
D16	VSS239	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
D24	VSS240	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
D30	VSS241	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
D36	VSS242	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
D38	VSS243	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
E8	VSS246	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
E19	VSS244	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
E35	VSS245	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F2	VSS248	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F5	VSS253	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F7	VSS254	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F19	VSS247	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F24	VSS249	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F27	VSS250	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F30	VSS251	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
F35	VSS252	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G10	VSS255	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G20	VSS256	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G22	VSS257	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G26	VSS258	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G28	VSS259	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G32	VSS260	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G34	VSS261	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
G42	VSS262	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
H19	VSS263	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
H27	VSS264	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
H35	VSS265	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J1	VSS266	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J16	VSS267	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J19	VSS268	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J22	VSS269	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J27	VSS270	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J32	VSS271	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J35	VSS272	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J40	VSS273	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
J53	VSS274	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
K4	VSS279	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
K9	VSS281	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
K14	VSS275	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
K22	VSS276	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
K32	VSS277	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
K36	VSS278	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
K50	VSS280	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
L13	VSS282	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
L19	VSS283	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
L27	VSS284	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
L35	VSS285	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M19	VSS286	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M26	VSS287	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M27	VSS288	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M28	VSS105	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M34	VSS289	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M35	VSS290	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M38	VSS291	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M47	VSS292	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
M51	VSS293	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
N1	VSS294	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
N16	VSS295	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
N38	VSS296	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
N51	VSS297	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P4	VSS306	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P9	VSS309	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P13	VSS298	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P16	VSS299	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P19	VSS300	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P20	VSS301	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P24	VSS302	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P32	VSS303	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P35	VSS304	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P38	VSS305	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P47	VSS307	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
P52	VSS308	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
T40	VSS310	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U1	VSS311	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U3	VSS316	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U5	VSS326	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U6	VSS329	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U8	VSS330	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U9	VSS331	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U11	VSS312	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U12	VSS313	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U14	VSS314	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U21	VSS315	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U30	VSS317	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U32	VSS318	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U40	VSS319	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U42	VSS320	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U43	VSS321	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U45	VSS322	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U46	VSS323	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U48	VSS324	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U49	VSS325	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U51	VSS327	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
U53	VSS328	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V7	VSS340	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V12	VSS332	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V16	VSS333	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V19	VSS334	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V21	VSS335	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V35	VSS336	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V40	VSS337	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V44	VSS338	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
V51	VSS339	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y7	VSS349	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y9	VSS350	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y10	VSS341	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y14	VSS342	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y16	VSS343	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y21	VSS344	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y25	VSS345	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y33	VSS346	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y41	VSS347	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.
Y44	VSS348	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks.

MEM2 - MT41K256M16HA-125:E ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
C1	VDDQ2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
R1	VDD7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
B2	VDD8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
D2	VDDQ9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
H2	VDDQ4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
K2	VDD9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
G7	VDD1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
A8	VDDQ5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
K8	VDD2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
C9	VDDQ6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
N1	VDD6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
F1	VDDQ3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
D9	VDD4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
E9	VDDQ7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
H9	VDDQ8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
N9	VDD3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
R9	VDD5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
B1	VSSQ1	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
D1	VSSQ2	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
E1	VSS1	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
G1	VSSQ3	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
M1	VSS2	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
P1	VSS3	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
T1	VSS4	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
E2	VSSQ4	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
J2	VSS5	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
B3	VSS6	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
D8	VSSQ5	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
E8	VSSQ6	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
G8	VSS7	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
J8	VSS8	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
A9	VSS9	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
B9	VSSQ7	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
F9	VSSQ8	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
G9	VSSQ9	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
M9	VSS10	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
P9	VSS11	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
T9	VSS12	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
C7	DQSU	M_DQS_A_P1	✅	Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P1/M_DQS_A_N1, providing the strobe for upper byte data.
B7	/DQSU	M_DQS_A_N1	✅	Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P1/M_DQS_A_N1, providing the strobe for upper byte data.
D3	DMU	M_DM_A1	✅	Upper byte data mask pin (DMU) is correctly connected to M_DM_A1, allowing masking of upper byte write data.
D7	DQU0	M_DATA_A9	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
C3	DQU1	M_DATA_A10	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
C8	DQU2	M_DATA_A8	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
C2	DQU3	M_DATA_A11	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
A7	DQU4	M_DATA_A13	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
A2	DQU5	M_DATA_A15	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
B8	DQU6	M_DATA_A12	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
A3	DQU7	M_DATA_A14	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization.
E3	DQL0	M_DATA_A0	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
F7	DQL1	M_DATA_A1	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
F2	DQL2	M_DATA_A2	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
F8	DQL3	M_DATA_A3	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
H3	DQL4	M_DATA_A4	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
H8	DQL5	M_DATA_A5	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
G2	DQL6	M_DATA_A6	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
H7	DQL7	M_DATA_A7	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2.
E7	DML	M_DM_A0	✅	Lower byte data mask pin (DML) is correctly connected to M_DM_A0, allowing masking of lower byte write data.
F3	DQSL	M_DQS_A_P0	✅	Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P0/M_DQS_A_N0, providing the strobe for lower byte data.
G3	/DQSL	M_DQS_A_N0	✅	Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P0/M_DQS_A_N0, providing the strobe for lower byte data.
H1	VREFDQ	SM_VREF_DQ1_A	✅	VREFDQ pin is correctly connected to SM_VREF_DQ1_A, which is generated by a resistor divider creating VDIMM/2 as required by the datasheet.
J1	NC1__ODT1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
L1	NC2__/CS1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
J9	NC3__CKE1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
L9	NC4__ZQ1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
M7	NC5		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
J7	CK	M_CLK_A_P0	✅	Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM3 for synchronous operation.
K7	/CK	M_CLK_A_N0	✅	Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM3 for synchronous operation.
K1	ODT	M_ODT_A0	✅	On-die termination enable pin (ODT) is correctly connected to M_ODT_A0, shared with MEM3 for termination control.
K9	CKE	M_CKE_A0	✅	Clock enable pin (CKE) is correctly connected to M_CKE_A0, shared with MEM3 for power management control.
L2	/CS	M_CS_A_L0	✅	Chip select pin (CS#) is correctly connected to M_CS_A_L0, shared with MEM3 to enable both devices simultaneously.
L3	/WE	M_WE_A_L	✅	Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM3 for command decoding.
J3	/RAS	M_RAS_A_L	✅	Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM3 for command decoding.
K3	/CAS	M_CAS_A_L	✅	Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM3 for command decoding.
L8	ZQ	M_ZQ1	✅	ZQ calibration pin is correctly connected to M_ZQ1 with a 240Ω resistor (R140) to ground as required by the datasheet.
M2	BA0	M_BS_A0	✅	Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM3 for bank selection.
N8	BA1	M_BS_A1	✅	Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM3 for bank selection.
M3	BA2	M_BS_A2	✅	Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM3 for bank selection.
M8	VREFCA	SM_VREF_CA1_A	✅	VREFCA pin is correctly connected to SM_VREF_CA1_A, which is generated by a resistor divider creating VDIMM/2 as required by the datasheet.
N3	A0	M_MA_A0	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
P7	A1	M_MA_A1	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
P3	A2	M_MA_A2	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
N2	A3	M_MA_A3	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
P8	A4	M_MA_A4	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
P2	A5	M_MA_A5	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
R8	A6	M_MA_A6	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
R2	A7	M_MA_A7	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
T8	A8	M_MA_A8	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
R3	A9	M_MA_A9	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
L7	A10_AP_	M_MA_A10	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
R7	A11	M_MA_A11	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
N7	A12_/BC_	M_MA_A12	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
T3	A13	M_MA_A13	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
T7	A14	M_MA_A14	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing.
T2	/RESET	M_A_RST_L	✅	Reset pin (RESET#) is correctly connected to M_A_RST_L through a 0-ohm resistor (R353), shared with MEM3 for asynchronous reset control.

MEM3 - MT41K256M16HA-125:E ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
C1	VDDQ2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
R1	VDD7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
B2	VDD8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
D2	VDDQ9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
H2	VDDQ4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
K2	VDD9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
G7	VDD1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
A8	VDDQ5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
K8	VDD2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
C9	VDDQ6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
N1	VDD6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
F1	VDDQ3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
D9	VDD4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
E9	VDDQ7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
H9	VDDQ8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
N9	VDD3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
R9	VDD5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation.
B1	VSSQ1	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
D1	VSSQ2	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
E1	VSS1	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
G1	VSSQ3	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
M1	VSS2	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
P1	VSS3	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
T1	VSS4	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
E2	VSSQ4	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
J2	VSS5	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
B3	VSS6	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
D8	VSSQ5	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
E8	VSSQ6	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
G8	VSS7	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
J8	VSS8	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
A9	VSS9	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
B9	VSSQ7	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
F9	VSSQ8	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
G9	VSSQ9	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
M9	VSS10	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
P9	VSS11	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
T9	VSS12	GND	✅	Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals.
C7	DQSU	M_DQS_A_P3	✅	Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P3/M_DQS_A_N3, providing the strobe for upper byte data.
B7	/DQSU	M_DQS_A_N3	✅	Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P3/M_DQS_A_N3, providing the strobe for upper byte data.
D3	DMU	M_DM_A3	✅	Upper byte data mask pin (DMU) is correctly connected to M_DM_A3, allowing masking of upper byte write data.
D7	DQU0	M_DATA_A29	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
C3	DQU1	M_DATA_A26	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
C8	DQU2	M_DATA_A28	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
C2	DQU3	M_DATA_A27	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
A7	DQU4	M_DATA_A25	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
A2	DQU5	M_DATA_A30	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
B8	DQU6	M_DATA_A24	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
A3	DQU7	M_DATA_A31	✅	Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization.
E3	DQL0	M_DATA_A16	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
F7	DQL1	M_DATA_A17	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
F2	DQL2	M_DATA_A18	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
F8	DQL3	M_DATA_A19	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
H3	DQL4	M_DATA_A20	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
H8	DQL5	M_DATA_A21	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
G2	DQL6	M_DATA_A22	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
H7	DQL7	M_DATA_A23	✅	Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus.
E7	DML	M_DM_A2	✅	Lower byte data mask pin (DML) is correctly connected to M_DM_A2, allowing masking of lower byte write data.
F3	DQSL	M_DQS_A_P2	✅	Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P2/M_DQS_A_N2, providing the strobe for lower byte data.
G3	/DQSL	M_DQS_A_N2	✅	Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P2/M_DQS_A_N2, providing the strobe for lower byte data.
H1	VREFDQ	SM_VREF_DQ1_A	✅	VREFDQ pin is correctly connected to SM_VREF_DQ1_A, shared with MEM2, providing the required VDIMM/2 reference voltage.
J1	NC1__ODT1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
L1	NC2__/CS1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
J9	NC3__CKE1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
L9	NC4__ZQ1_		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
M7	NC5		✅	No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet.
J7	CK	M_CLK_A_P0	✅	Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM2 for synchronous operation.
K7	/CK	M_CLK_A_N0	✅	Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM2 for synchronous operation.
K1	ODT	M_ODT_A0	✅	On-die termination enable pin (ODT) is correctly connected to M_ODT_A0, shared with MEM2 for termination control.
K9	CKE	M_CKE_A0	✅	Clock enable pin (CKE) is correctly connected to M_CKE_A0, shared with MEM2 for power management control.
L2	/CS	M_CS_A_L0	✅	Chip select pin (CS#) is correctly connected to M_CS_A_L0, shared with MEM2 to enable both devices simultaneously as a single rank.
L3	/WE	M_WE_A_L	✅	Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM2 for command decoding.
J3	/RAS	M_RAS_A_L	✅	Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM2 for command decoding.
K3	/CAS	M_CAS_A_L	✅	Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM2 for command decoding.
L8	ZQ	M_ZQ2	✅	ZQ calibration pin is correctly connected to M_ZQ2 with a 240Ω resistor (R327) to ground as required by the datasheet.
M2	BA0	M_BS_A0	✅	Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM2 for bank selection.
N8	BA1	M_BS_A1	✅	Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM2 for bank selection.
M3	BA2	M_BS_A2	✅	Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM2 for bank selection.
M8	VREFCA	SM_VREF_CA1_A	✅	VREFCA pin is correctly connected to SM_VREF_CA1_A, shared with MEM2, providing the required VDIMM/2 reference voltage.
N3	A0	M_MA_A0	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
P7	A1	M_MA_A1	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
P3	A2	M_MA_A2	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
N2	A3	M_MA_A3	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
P8	A4	M_MA_A4	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
P2	A5	M_MA_A5	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
R8	A6	M_MA_A6	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
R2	A7	M_MA_A7	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
T8	A8	M_MA_A8	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
R3	A9	M_MA_A9	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
L7	A10_AP_	M_MA_A10	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
R7	A11	M_MA_A11	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
N7	A12_/BC_	M_MA_A12	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
T3	A13	M_MA_A13	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
T7	A14	M_MA_A14	✅	Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing.
T2	/RESET	M_A_RST_L	✅	Reset pin (RESET#) is correctly connected to M_A_RST_L, shared with MEM2 for asynchronous reset control.

R140 - 110-0001971 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ1	✅	240-ohm ZQ calibration resistor for DDR3 memory MEM2. Pin 1 connects to M_ZQ1 (MEM2 pin L8 ZQ) and pin 2 connects to GND.
2	2	GND	✅	240-ohm ZQ calibration resistor for DDR3 memory MEM2. Pin 1 connects to M_ZQ1 (MEM2 pin L8 ZQ) and pin 2 connects to GND.

R327 - 110-0001971 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ2	✅	240-ohm ZQ calibration resistor for DDR3 memory MEM3. Pin 1 connects to M_ZQ2 (MEM3 pin L8 ZQ) and pin 2 connects to GND.
2	2	GND	✅	240-ohm ZQ calibration resistor for DDR3 memory MEM3. Pin 1 connects to M_ZQ2 (MEM3 pin L8 ZQ) and pin 2 connects to GND.

R353 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_A_DRAMRST_L	✅	0-ohm resistor connecting M_A_DRAMRST_L to M_A_RST_L, which drives the /RESET pins of memory devices MEM2 and MEM3. This provides a series connection for the reset signal path.
2	2	M_A_RST_L	✅	0-ohm resistor connecting M_A_DRAMRST_L to M_A_RST_L, which drives the /RESET pins of memory devices MEM2 and MEM3. This provides a series connection for the reset signal path.

C374 - 123-0001076 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	10pF capacitor from M_A_RST_L to GND, marked DNI (Do Not Install). When populated, would provide high-frequency filtering on the reset line.
2	2	M_A_RST_L	✅	10pF capacitor from M_A_RST_L to GND, marked DNI (Do Not Install). When populated, would provide high-frequency filtering on the reset line.

FL1 - 3750-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CH1-IN	SD3_CD#	✅	Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller.
2	CH2-IN	SD3_D2	✅	Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller.
3	CH3-IN	SD3_D3	✅	Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller.
4	CH4-IN	SD3_CMD	✅	Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller.
5	CH5-IN	SD3_CLK	✅	Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller.
6	CH6-IN	SD3_D0	✅	Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller.
7	CH7-IN	SD3_D1	✅	Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller.
8	CH8-IN		✅	Channel 8 input and output are not connected, which is acceptable since only 7 channels are needed for the SD card interface.
9	CH8-OUT		✅	Channel 8 input and output are not connected, which is acceptable since only 7 channels are needed for the SD card interface.
10	CH7-OUT	SD3_D1_R	✅	Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2.
11	CH6-OUT	SD3_D0_R	✅	Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2.
12	CH5-OUT	SD3_CLK_R	✅	Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2.
13	CH4-OUT	SD3_CMD_R	✅	Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2.
14	CH3-OUT	SD3_D3_R	✅	Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2.
15	CH2-OUT	SD3_D2_R	✅	Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2.
16	CH1-OUT	SD3_CD_R	✅	Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2.
17	GND_PAD	GND	✅	Ground pad is correctly connected to the main ground net.

P2 - SCHA5B0200 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	SD3_D2_R	✅	SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1.
2	CD/DAT3	SD3_D3_R	✅	SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1.
7	DAT0	SD3_D0_R	✅	SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1.
8	DAT1	SD3_D1_R	✅	SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1.
3	CMD	SD3_CMD_R	✅	SD card command line is correctly connected to filtered command signal from the host controller through FL1.
4	VDD	+VCC3	✅	SD card power supply is correctly connected to +VCC3 (3.3V) with appropriate decoupling capacitors C159 and C162.
5	CLOCK	SD3_CLK_R	✅	SD card clock line is correctly connected to filtered clock signal from the host controller through FL1.
6	VSS	GND	✅	SD card ground connections are correctly connected to the main ground net.
9	GND	GND	✅	SD card ground connections are correctly connected to the main ground net.
10	CD	SD3_CD_R	✅	SD card detect signal is correctly connected to filtered card detect signal from the host controller through FL1.
11	GND3	FGND-uSD	✅	Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes.
12	GND4	FGND-uSD	✅	Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes.
15	GND7	FGND-uSD	✅	Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes.
16	GND8	FGND-uSD	✅	Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes.
13	GND5	FGND-uSD-Front	✅	Front frame ground connections are intentionally connected to FGND-uSD-Front, separate from main ground, as documented in the schematic notes.
14	GND6	FGND-uSD-Front	✅	Front frame ground connections are intentionally connected to FGND-uSD-Front, separate from main ground, as documented in the schematic notes.

R29 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CEC	✅	Pin 1 correctly connected to HDMI_CEC net (CEC_A of U2).
2	2	+V1P8S	✅	Pin 2 correctly connected to +V1P8S supply, providing a 10kΩ pullup for the CEC_A signal. This external pullup is redundant with the internal 10kΩ pullup in U2 but not incorrect.

R171 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pin 1 correctly connected to +V1P8S supply.
2	2	HPD_ENB	✅	Pin 2 correctly connected to HPD_ENB net (CT_HPD of U2), providing a 2.2kΩ pullup to enable the load switch and HPD by default.

R30 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCDAT	✅	Pin 1 correctly connected to HDMI_DDCDAT net (SDA_A of U2).
2	2	+V1P8S	✅	Pin 2 correctly connected to +V1P8S supply, providing a 10kΩ pullup for the SDA_A signal. This external pullup is redundant with the internal 10kΩ pullup in U2 but not incorrect.

U2 - TPD12S016PW ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CEC_A	HDMI_CEC	✅	CEC_A pin correctly connected to HDMI_CEC net with external 10kΩ pullup to +V1P8S through R29. The external pullup is redundant with the internal 10kΩ pullup but not incorrect.
2	SCL_A	HDMI_DDCCLK	✅	SCL_A pin correctly connected to HDMI_DDCCLK net with external 10kΩ pullup to +V1P8S through R28. The external pullup is redundant with the internal 10kΩ pullup but not incorrect.
3	SDA_A	HDMI_DDCDAT	✅	SDA_A pin correctly connected to HDMI_DDCDAT net with external 10kΩ pullup to +V1P8S through R30. The external pullup is redundant with the internal 10kΩ pullup but not incorrect.
4	HPD_A	HDMI_HPD	✅	HPD_A pin correctly connected to HDMI_HPD net as the hot plug detect output to the HDMI controller.
5	LS_OE	LS_OE	✅	LS_OE pin correctly connected to LS_OE net with external 2.2kΩ pullup to +V1P8S through R172. The external pullup enables the level shifters by default.
6	GND1	GND	✅	Ground pins correctly connected to GND net.
14	GND2	GND	✅	Ground pins correctly connected to GND net.
19	GND3	GND	✅	Ground pins correctly connected to GND net.
7	CEC_B	C_HDMI_CEC	✅	CEC_B pin correctly connected to C_HDMI_CEC net, which connects to the HDMI connector CEC pin.
8	SCL_B	C_HDMI_SCL	✅	SCL_B pin correctly connected to C_HDMI_SCL net, which connects to the HDMI connector SCL pin.
9	SDA_B	C_HDMI_SDA	✅	SDA_B pin correctly connected to C_HDMI_SDA net, which connects to the HDMI connector SDA pin.
10	HPD_B	C_HDMI_HPD	✅	HPD_B pin correctly connected to C_HDMI_HPD net, which connects to the HDMI connector hot plug detect pin.
11	VCC5V	+5VSB	✅	VCC5V pin correctly connected to +5VSB supply with 0.1µF decoupling capacitor C155.
12	CT_HPD	HPD_ENB	✅	CT_HPD pin correctly connected to HPD_ENB net with external 2.2kΩ pullup to +V1P8S through R171. The external pullup enables the load switch and HPD by default.
13	5V_OUT	+HDMI_CRT_VCC	✅	5V_OUT pin correctly connected to +HDMI_CRT_VCC net with ferrite bead L7 filtering to D5_0V_HDMI and 4.7µF decoupling capacitor C157.
15	CLK-	HDMI_OUT_CLK_DN	✅	CLK- and CLK+ pins correctly connected to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets respectively, providing ESD protection for the HDMI TMDS clock signals.
16	CLK+	HDMI_OUT_CLK_DP	✅	CLK- and CLK+ pins correctly connected to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets respectively, providing ESD protection for the HDMI TMDS clock signals.
17	D0-	HDMI_OUT_TX0_DN	✅	D0- and D0+ pins correctly connected to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets respectively, providing ESD protection for the HDMI TMDS data 0 signals.
18	D0+	HDMI_OUT_TX0_DP	✅	D0- and D0+ pins correctly connected to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets respectively, providing ESD protection for the HDMI TMDS data 0 signals.
20	D1-	HDMI_OUT_TX1_DN	✅	D1- and D1+ pins correctly connected to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets respectively, providing ESD protection for the HDMI TMDS data 1 signals.
21	D1+	HDMI_OUT_TX1_DP	✅	D1- and D1+ pins correctly connected to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets respectively, providing ESD protection for the HDMI TMDS data 1 signals.
22	D2-	HDMI_OUT_TX2_DN	✅	D2- and D2+ pins correctly connected to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets respectively, providing ESD protection for the HDMI TMDS data 2 signals.
23	D2+	HDMI_OUT_TX2_DP	✅	D2- and D2+ pins correctly connected to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets respectively, providing ESD protection for the HDMI TMDS data 2 signals.
24	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S supply with 0.1µF decoupling capacitor C17.

R28 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCCLK	✅	Pin 1 correctly connected to HDMI_DDCCLK net (SCL_A of U2).
2	2	+V1P8S	✅	Pin 2 correctly connected to +V1P8S supply, providing a 10kΩ pullup for the SCL_A signal. This external pullup is redundant with the internal 10kΩ pullup in U2 but not incorrect.

R172 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pin 1 correctly connected to +V1P8S supply.
2	2	LS_OE	✅	Pin 2 correctly connected to LS_OE net (LS_OE of U2), providing a 2.2kΩ pullup to enable the level shifters by default.

L16 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX1_C_DN	✅	IN1 pin connected to HDMI_TX1_C_DN, the negative side of the TX1 data differential pair after AC coupling. This carries the data signal through the common mode choke.
3	IN2	HDMI_TX1_C_DP	✅	IN2 pin connected to HDMI_TX1_C_DP, the positive side of the TX1 data differential pair after AC coupling. This carries the data signal through the common mode choke.
4	OUT2	HDMI_OUT_TX1_DP	✅	OUT2 pin connected to HDMI_OUT_TX1_DP, outputting the positive side of the TX1 data differential pair to the HDMI translator chip U2 and then to connector P1.
6	OUT1	HDMI_OUT_TX1_DN	✅	OUT1 pin connected to HDMI_OUT_TX1_DN, outputting the negative side of the TX1 data differential pair to the HDMI translator chip U2 and then to connector P1.

L14 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_CLK_C_DN	✅	IN1 pin connected to HDMI_CLK_C_DN, the negative side of the clock differential pair after AC coupling. This carries the clock signal through the common mode choke.
3	IN2	HDMI_CLK_C_DP	✅	IN2 pin connected to HDMI_CLK_C_DP, the positive side of the clock differential pair after AC coupling. This carries the clock signal through the common mode choke.
4	OUT2	HDMI_OUT_CLK_DP	✅	OUT2 pin connected to HDMI_OUT_CLK_DP, outputting the positive side of the clock differential pair to the HDMI translator chip U2 and then to connector P1.
6	OUT1	HDMI_OUT_CLK_DN	✅	OUT1 pin connected to HDMI_OUT_CLK_DN, outputting the negative side of the clock differential pair to the HDMI translator chip U2 and then to connector P1.

L17 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX2_C_DN	✅	IN1 pin connected to HDMI_TX2_C_DN, the negative side of the TX2 data differential pair after AC coupling. This carries the data signal through the common mode choke.
3	IN2	HDMI_TX2_C_DP	✅	IN2 pin connected to HDMI_TX2_C_DP, the positive side of the TX2 data differential pair after AC coupling. This carries the data signal through the common mode choke.
4	OUT2	HDMI_OUT_TX2_DP	✅	OUT2 pin connected to HDMI_OUT_TX2_DP, outputting the positive side of the TX2 data differential pair to the HDMI translator chip U2 and then to connector P1.
6	OUT1	HDMI_OUT_TX2_DN	✅	OUT1 pin connected to HDMI_OUT_TX2_DN, outputting the negative side of the TX2 data differential pair to the HDMI translator chip U2 and then to connector P1.

L15 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX0_C_DN	✅	IN1 pin connected to HDMI_TX0_C_DN, the negative side of the TX0 data differential pair after AC coupling. This carries the data signal through the common mode choke.
3	IN2	HDMI_TX0_C_DP	✅	IN2 pin connected to HDMI_TX0_C_DP, the positive side of the TX0 data differential pair after AC coupling. This carries the data signal through the common mode choke.
4	OUT2	HDMI_OUT_TX0_DP	✅	OUT2 pin connected to HDMI_OUT_TX0_DP, outputting the positive side of the TX0 data differential pair to the HDMI translator chip U2 and then to connector P1.
6	OUT1	HDMI_OUT_TX0_DN	✅	OUT1 pin connected to HDMI_OUT_TX0_DN, outputting the negative side of the TX0 data differential pair to the HDMI translator chip U2 and then to connector P1.

Q101 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	HDMI_TERM	✅	Drain pin correctly connected to HDMI_TERM net, which serves as the common termination point for eight 619Ω resistors (R801-R808) connected to HDMI differential signal lines.
G	GATE	$15N747	✅	Gate pin connected to net $15N747, which connects to +VCC3 through 0Ω resistor R809. While the gate is properly connected to its net, the net name starting with '$' indicates an auto-generated net, suggesting this connection scheme may be incomplete or incorrect. See R809 analysis for the root cause.
S	SOURCE	GND	✅	Source pin correctly connected to GND, providing the return path for the low-side switch configuration.

R809 - 110-0001853 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$15N747	❌	R809 is a 0Ω resistor connecting Q101 gate to +VCC3 power rail via auto-generated net $15N747. The auto-generated net name and empty PLACE attribute indicate this connection scheme is likely an error. The gate should typically be driven by a control signal to enable/disable the HDMI termination network as needed, rather than being permanently tied to power. Pin 1 is connected to net $15N747, which also connects to Q101 gate pin G (from schematic) Pin 2 is connected to net +VCC3 (from schematic) R809 has a value of 0Ω, effectively creating a direct connection between Q101 gate and +VCC3 (from schematic) The net name $15N747 starts with '$', which in most EDA tools indicates an auto-generated net name created when there is a floating connection or missing net label (reasoning) R809 has an empty PLACE attribute, suggesting uncertainty about whether this component should be placed or indicating the design is incomplete (from schematic) With the gate tied directly to +VCC3, Q101 will be permanently enabled whenever +VCC3 is present, making the termination network always active with no independent control (reasoning) The circuit includes other control signals (LS_OE, HPD_ENB) for the HDMI interface, suggesting that controllable termination would be more consistent with the overall design intent (from schematic) If permanent enable was the design intent, the gate could be directly connected to +VCC3 without requiring a separate 0Ω resistor and auto-generated net (reasoning) The combination of auto-generated net name, empty PLACE attribute, and unusual connection scheme indicates this is likely an incomplete or incorrect connection rather than intentional design (reasoning)
2	2	+VCC3	❌	R809 is a 0Ω resistor connecting Q101 gate to +VCC3 power rail via auto-generated net $15N747. The auto-generated net name and empty PLACE attribute indicate this connection scheme is likely an error. The gate should typically be driven by a control signal to enable/disable the HDMI termination network as needed, rather than being permanently tied to power. Pin 1 is connected to net $15N747, which also connects to Q101 gate pin G (from schematic) Pin 2 is connected to net +VCC3 (from schematic) R809 has a value of 0Ω, effectively creating a direct connection between Q101 gate and +VCC3 (from schematic) The net name $15N747 starts with '$', which in most EDA tools indicates an auto-generated net name created when there is a floating connection or missing net label (reasoning) R809 has an empty PLACE attribute, suggesting uncertainty about whether this component should be placed or indicating the design is incomplete (from schematic) With the gate tied directly to +VCC3, Q101 will be permanently enabled whenever +VCC3 is present, making the termination network always active with no independent control (reasoning) The circuit includes other control signals (LS_OE, HPD_ENB) for the HDMI interface, suggesting that controllable termination would be more consistent with the overall design intent (from schematic) If permanent enable was the design intent, the gate could be directly connected to +VCC3 without requiring a separate 0Ω resistor and auto-generated net (reasoning) The combination of auto-generated net name, empty PLACE attribute, and unusual connection scheme indicates this is likely an incomplete or incorrect connection rather than intentional design (reasoning)

R805 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_C_DN	✅	Connected to HDMI_TX0_C_DN signal line, providing DC restoration path for the negative differential signal of HDMI data channel 0.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled.

R802 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_C_DP	✅	Connected to HDMI_TX2_C_DP signal line, providing DC restoration path for the positive differential signal of HDMI data channel 2.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled.

R801 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_C_DN	✅	Connected to HDMI_TX2_C_DN signal line, providing DC restoration path for the negative differential signal of HDMI data channel 2.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101 to provide DC bias for HDMI signals.

R806 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_C_DP	✅	Connected to HDMI_TX0_C_DP signal line, providing DC restoration path for the positive differential signal of HDMI data channel 0.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled.

R807 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CLK_C_DP	✅	Connected to HDMI_CLK_C_DP signal line, providing DC restoration path for the positive differential clock signal.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled.

R808 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CLK_C_DN	✅	Connected to HDMI_CLK_C_DN signal line, providing DC restoration path for the negative differential clock signal.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled.

R804 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_C_DP	✅	Connected to HDMI_TX1_C_DP signal line, providing DC restoration path for the positive differential signal of HDMI data channel 1.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled.

R803 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_C_DN	✅	Connected to HDMI_TX1_C_DN signal line, providing DC restoration path for the negative differential signal of HDMI data channel 1.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled.

P1 - 158-0004513 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	HPLG	C_HDMI_HPD	✅	Hot plug detect signal correctly routed through translator IC U2 to system HPD signal.
2	NC		✅	No connect pin correctly left unconnected.
3	DAT2+	HDMI_OUT_TX2_DP	✅	Data channel 2 positive differential signal correctly routed through common mode choke L17 and translator U2 with AC coupling and termination.
4	DAT2_S	GND	✅	Data channel 2 shield correctly connected to ground.
5	DAT2-	HDMI_OUT_TX2_DN	✅	Data channel 2 negative differential signal correctly routed through common mode choke L17 and translator U2 with AC coupling and termination.
6	DAT1+	HDMI_OUT_TX1_DP	✅	Data channel 1 positive differential signal correctly routed through common mode choke L16 and translator U2 with AC coupling and termination.
7	DAT1_S	GND	✅	Data channel 1 shield correctly connected to ground.
8	DAT1-	HDMI_OUT_TX1_DN	✅	Data channel 1 negative differential signal correctly routed through common mode choke L16 and translator U2 with AC coupling and termination.
9	DAT0+	HDMI_OUT_TX0_DP	✅	Data channel 0 positive differential signal correctly routed through common mode choke L15 and translator U2 with AC coupling and termination.
10	DAT0_S	GND	✅	Data channel 0 shield correctly connected to ground.
11	DAT0-	HDMI_OUT_TX0_DN	✅	Data channel 0 negative differential signal correctly routed through common mode choke L15 and translator U2 with AC coupling and termination.
12	CLK+	HDMI_OUT_CLK_DP	✅	Clock positive differential signal correctly routed through common mode choke L14 and translator U2 with AC coupling and termination.
13	CLK_S	GND	✅	Clock shield correctly connected to ground.
14	CLK-	HDMI_OUT_CLK_DN	✅	Clock negative differential signal correctly routed through common mode choke L14 and translator U2 with AC coupling and termination.
15	CEC	C_HDMI_CEC	✅	CEC signal correctly routed through translator IC U2 with appropriate pullup resistor.
16	DDC/CEC_GND	GND	✅	DDC/CEC ground correctly connected to system ground.
17	SCL	C_HDMI_SCL	✅	DDC I2C clock signal correctly routed through translator IC U2 with appropriate pullup resistor.
18	SDA	C_HDMI_SDA	✅	DDC I2C data signal correctly routed through translator IC U2 with appropriate pullup resistor.
19	+5V	D5_0V_HDMI	✅	+5V power supply correctly routed through translator IC U2 with current limiting and filtering via ferrite bead L7.
20	MTG1	GND_EARTH	✅	Mounting tabs correctly connected to earth ground for shielding and EMI control.
21	MTG2	GND_EARTH	✅	Mounting tabs correctly connected to earth ground for shielding and EMI control.
22	MTG3	GND_EARTH	✅	Mounting tabs correctly connected to earth ground for shielding and EMI control.
23	MTG4	GND_EARTH	✅	Mounting tabs correctly connected to earth ground for shielding and EMI control.

L7 - BLM18KG221SN1D ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+HDMI_CRT_VCC	✅	Pin 1 (P1) connects to +HDMI_CRT_VCC from U2 pin 13 (5V_OUT). This is the input side of the ferrite bead filter.
2	P2	D5_0V_HDMI	✅	Pin 2 (P2) connects to D5_0V_HDMI which goes to the HDMI connector P1 pin 19 (+5V). This is the output side of the ferrite bead filter.

C157 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+HDMI_CRT_VCC	✅	Pin 1 connects to +HDMI_CRT_VCC from U2 pin 13 (5V_OUT). This provides decoupling for the 5V output before the ferrite bead filter.
2	2	GND	✅	Pin 2 connects to GND. This completes the decoupling capacitor connection to ground.

C161 - 2267-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to the main circuit ground (GND). This is one side of the safety/isolation capacitor.
2	2	GND_EARTH	✅	Pin 2 is correctly connected to chassis/earth ground (GND_EARTH). This completes the safety/isolation capacitor connection between circuit ground and chassis ground.

R116 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB_HOST_BUFF_ENB	✅	Pull-up resistor correctly configured to enable the level translator by default.
2	2	+V1P8A	✅	Pull-up resistor correctly configured to enable the level translator by default.

R117 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pull-down resistor correctly connected to set default disabled state for USB channel 2 enable signal.
2	2	SOC_USB_HOST_EN1	✅	Pull-down resistor correctly connected to set default disabled state for USB channel 2 enable signal.

U32 - AP2172MPG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	Ground pin correctly connected to GND net.
2	IN	+USBVCC	✅	Input power pin correctly connected to +USBVCC with appropriate bypass capacitors.
3	EN1	USB_HOST_EN0	✅	Enable input for channel 1 correctly connected to level-translated enable signal from SOC.
4	EN2	USB_HOST_EN1	✅	Enable input for channel 2 correctly connected to level-translated enable signal from SOC.
5	OC2#	SOC_USB_HOST_OC1	✅	Overcurrent flag output for channel 2 connected to SOC without visible external pull-up resistor. This open-drain output requires a pull-up resistor per datasheet, which may be provided internally by the SOC but should be verified.
6	OUTB	USBP2	✅	Output power pin for channel 2 correctly connected through ferrite bead to VBUS2 with appropriate output capacitors.
7	OUTA	USBP1	✅	Output power pin for channel 1 correctly connected through ferrite bead to VBUS1 with appropriate output capacitors.
8	OC1#	SOC_USB_HOST_OC0	✅	Overcurrent flag output for channel 1 connected to SOC without visible external pull-up resistor. This open-drain output requires a pull-up resistor per datasheet, which may be provided internally by the SOC but should be verified.
9	GND_PAD	GND	✅	Exposed pad correctly connected to GND for thermal management.

U4 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	USB_HOST_EN0	✅	B-side I/O pin correctly connected to drive USB power switch enable signal.
2	GND	GND	✅	Ground pin correctly connected to GND net.
3	VCCA	+V1P8A	✅	A-side supply voltage correctly connected to +V1P8A for SOC-side level translation.
4	A2	SOC_USB_HOST_EN0	✅	A-side I/O pin correctly connected to receive enable signal from SOC.
5	A1	SOC_USB_HOST_EN1	✅	A-side I/O pin correctly connected to receive enable signal from SOC with pull-down resistor.
6	OE	USB_HOST_BUFF_ENB	✅	Output enable pin correctly connected with pull-up resistor to enable the level translator by default.
7	VCCB	+USBVCC	✅	B-side supply voltage correctly connected to +USBVCC for USB power switch level translation.
8	B1	USB_HOST_EN1	✅	B-side I/O pin correctly connected to drive USB power switch enable signal.

C191 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_TXN0	✅	Connected to USB3_TXN0 from the SOC, this is the input side of the AC coupling capacitor for the negative USB3 TX signal.
2	2	USB3_TX0N-R	✅	Connected to USB3_TX0N-R going to CHOKE2, this is the output side of the AC coupling capacitor for the negative USB3 TX signal.

C192 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_TXP0	✅	Connected to USB3_TXP0 from the SOC, this is the input side of the AC coupling capacitor for the positive USB3 TX signal.
2	2	USB3_TX0P-R	✅	Connected to USB3_TX0P-R going to CHOKE2, this is the output side of the AC coupling capacitor for the positive USB3 TX signal.

U29 - TPD4USB30 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D1+	USB3_TX0P_C	✅	D1+ provides ESD protection for the positive USB3 TX signal (USB3_TX0P_C). Connected between the common mode choke output and the USB connector.
2	D1-	USB3_TX0N_C	✅	D1- provides ESD protection for the negative USB3 TX signal (USB3_TX0N_C). Connected between the common mode choke output and the USB connector.
3	GND1	GND	✅	GND1 is properly connected to the GND net, providing a ground reference for the ESD protection device.
4	D2+	USB3_RX0P_C	✅	D2+ provides ESD protection for the positive USB3 RX signal (USB3_RX0P_C). Connected between the USB connector and the common mode choke input.
5	D2-	USB3_RX0N_C	✅	D2- provides ESD protection for the negative USB3 RX signal (USB3_RX0N_C). Connected between the USB connector and the common mode choke input.
6	NC4	USB3_RX0N_C	✅	NC4 is connected to the same net as D2- (USB3_RX0N_C), likely providing additional ESD protection or capacitance for the negative RX signal.
7	NC3	USB3_RX0P_C	✅	NC3 is connected to the same net as D2+ (USB3_RX0P_C), likely providing additional ESD protection or capacitance for the positive RX signal.
8	GND2	GND	✅	GND2 is properly connected to the GND net, providing a ground reference for the ESD protection device.
9	NC2	USB3_TX0N_C	✅	NC2 is connected to the same net as D1- (USB3_TX0N_C), likely providing additional ESD protection or capacitance for the negative TX signal.
10	NC1	USB3_TX0P_C	✅	NC1 is connected to the same net as D1+ (USB3_TX0P_C), likely providing additional ESD protection or capacitance for the positive TX signal.

CHOKE2 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_TX0P-R	✅	IN1 receives the positive USB3 TX signal (USB3_TX0P-R) after AC coupling through C192. This is the input to the common mode choke for the positive differential signal.
3	IN2	USB3_TX0N-R	✅	IN2 receives the negative USB3 TX signal (USB3_TX0N-R) after AC coupling through C191. This is the input to the common mode choke for the negative differential signal.
4	OUT2	USB3_TX0N_C	✅	OUT2 outputs the filtered negative USB3 TX signal (USB3_TX0N_C) to the ESD protection device U29. This is the output from the common mode choke for the negative differential signal.
6	OUT1	USB3_TX0P_C	✅	OUT1 outputs the filtered positive USB3 TX signal (USB3_TX0P_C) to the ESD protection device U29. This is the output from the common mode choke for the positive differential signal.

CHOKE1 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_RX0N_C	✅	IN1 receives the negative USB3 RX signal (USB3_RX0N_C) from the ESD protection device U29. This is the input to the common mode choke for the negative differential signal.
3	IN2	USB3_RX0P_C	✅	IN2 receives the positive USB3 RX signal (USB3_RX0P_C) from the ESD protection device U29. This is the input to the common mode choke for the positive differential signal.
4	OUT2	USB3_RXP0	✅	OUT2 outputs the filtered positive USB3 RX signal (USB3_RXP0) to the SOC. This is the output from the common mode choke for the positive differential signal.
6	OUT1	USB3_RXN0	✅	OUT1 outputs the filtered negative USB3 RX signal (USB3_RXN0) to the SOC. This is the output from the common mode choke for the negative differential signal.

U9 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H0	✅	D+ pin is connected to USB_H0, providing ESD protection for the USB 2.0 D+ data line between the common mode choke and USB connector.
2	D-	USB_L0	✅	D- pin is connected to USB_L0, providing ESD protection for the USB 2.0 D- data line between the common mode choke and USB connector.
3	ID		✅	ID pin is left unconnected, which is acceptable per the datasheet for non-OTG USB implementations.
4	GND	GND	✅	GND pin is correctly connected to the ground plane.
5	NC		✅	NC pin is correctly left unconnected as it is not internally connected per the datasheet.
6	VBUS	VBUS1	✅	VBUS pin is connected to VBUS1, providing ESD protection for the USB power line with proper filtering through ferrite bead L1 and decoupling capacitors.

CHOKE4 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN0	✅	IN1 is connected to USB_DN0, which is the USB 2.0 D- signal input to the common mode choke.
3	IN2	USB_DP0	✅	IN2 is connected to USB_DP0, which is the USB 2.0 D+ signal input to the common mode choke.
4	OUT2	USB_H0	✅	OUT2 is connected to USB_H0, which routes to the D+ pin of ESD protection device U9 and the DA+ pin of USB connector USB1.
6	OUT1	USB_L0	✅	OUT1 is connected to USB_L0, which routes to the D- pin of ESD protection device U9 and the DA- pin of USB connector USB1.

U8 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H1	✅	D+ pin providing ESD protection for USB high-speed differential data line. Connected to USB_H1 which carries the D+ signal for USB port B.
2	D-	USB_L1	✅	D- pin providing ESD protection for USB high-speed differential data line. Connected to USB_L1 which carries the D- signal for USB port B.
3	ID		✅	ID pin for USB OTG identification, left unconnected. This is acceptable per datasheet as the ID pin can be left floating if not used.
4	GND	GND	✅	Ground pin, correctly connected to the GND net for proper ESD protection operation.
5	NC		✅	NC (Not Connected) pin, correctly left unconnected as it is not internally connected within the device.
6	VBUS	VBUS2	✅	VBUS pin providing ESD protection for the USB power line. Connected to VBUS2 which supplies power to USB port B through ferrite bead L2.

CHOKE3 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN1	✅	Input 1 of common mode choke, connected to USB_DN1 (USB D- signal for port 1). This forms one half of the USB 2.0 differential pair input.
3	IN2	USB_DP1	✅	Input 2 of common mode choke, connected to USB_DP1 (USB D+ signal for port 1). This forms the other half of the USB 2.0 differential pair input.
4	OUT2	USB_H1	✅	Output 2 of common mode choke, connected to USB_H1 (USB D+ signal after filtering). This output goes to ESD protection device U8.
6	OUT1	USB_L1	✅	Output 1 of common mode choke, connected to USB_L1 (USB D- signal after filtering). This output goes to ESD protection device U8.

FB13 - 3044-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input pin connected to +5VSB standby power rail, providing source power for the USB power supply.
2	2	+USBVCC	✅	Output pin connected to +USBVCC, providing filtered USB power supply to the USB power switch (U32) and level shifter (U4).

L1 - BKP2125HS221-T ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP1	✅	Input pin connected to USBP1, receiving switched USB power from the first channel of the AP2172MPG power switch.
2	2	VBUS1	✅	Output pin connected to VBUS1, providing filtered USB power to USB port 1. Note that the bulk capacitance on VBUS1 is insufficient for USB specification compliance.

L2 - BKP2125HS221-T ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP2	✅	Input pin connected to USBP2, receiving switched USB power from the second channel of the AP2172MPG power switch.
2	2	VBUS2	✅	Output pin connected to VBUS2, providing filtered USB power to USB port 2. Note that the bulk capacitance on VBUS2 is insufficient for USB specification compliance.

C91 - 123-0001176 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	❌	Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports. Pin 1 is connected to GND and pin 2 is connected to VBUS1 (from schematic) C91 is a 22uF capacitor providing bulk decoupling for VBUS1 (from schematic) The component attributes show PartDescription '22uF 20% 6.3V 0805', indicating a 6.3V voltage rating (from schematic) The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) (reasoning) USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads (reasoning) The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF (reasoning) The capacitance should be increased to at least 120uF per port to meet USB specification requirements (reasoning)
2	2	VBUS1	❌	Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports. Pin 1 is connected to GND and pin 2 is connected to VBUS1 (from schematic) C91 is a 22uF capacitor providing bulk decoupling for VBUS1 (from schematic) The component attributes show PartDescription '22uF 20% 6.3V 0805', indicating a 6.3V voltage rating (from schematic) The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) (reasoning) USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads (reasoning) The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF (reasoning) The capacitance should be increased to at least 120uF per port to meet USB specification requirements (reasoning)

C103 - 123-0001176 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	❌	Bulk decoupling capacitor for VBUS2 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports. Pin 1 is connected to GND and pin 2 is connected to VBUS2 (from schematic) C103 is a 22uF capacitor providing bulk decoupling for VBUS2 (from schematic) The component attributes show PartDescription '22uF 20% 6.3V 0805', indicating a 6.3V voltage rating (from schematic) The total capacitance on VBUS2 is approximately 22.2uF, including C103 (22uF), C70 (0.1uF), and C234 (0.1uF) (reasoning) USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads (reasoning) The total capacitance of 22.2uF on VBUS2 represents only 18.5% of the USB specification requirement of 120uF (reasoning) The capacitance should be increased to at least 120uF per port to meet USB specification requirements (reasoning)
2	2	VBUS2	❌	Bulk decoupling capacitor for VBUS2 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports. Pin 1 is connected to GND and pin 2 is connected to VBUS2 (from schematic) C103 is a 22uF capacitor providing bulk decoupling for VBUS2 (from schematic) The component attributes show PartDescription '22uF 20% 6.3V 0805', indicating a 6.3V voltage rating (from schematic) The total capacitance on VBUS2 is approximately 22.2uF, including C103 (22uF), C70 (0.1uF), and C234 (0.1uF) (reasoning) USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads (reasoning) The total capacitance of 22.2uF on VBUS2 represents only 18.5% of the USB specification requirement of 120uF (reasoning) The capacitance should be increased to at least 120uF per port to meet USB specification requirements (reasoning)

USB1 - 258-0004503 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUSA	VBUS1	✅	VBUSA provides 5V power to USB port A. Power is sourced from U32 power switch through ferrite bead L1, with ESD protection from U9 and multiple bypass capacitors.
2	DA-	USB_L0	✅	DA- is the USB 2.0 D- signal for port A. Signal is routed through common mode choke CHOKE4 and protected by ESD device U9.
3	DA+	USB_H0	✅	DA+ is the USB 2.0 D+ signal for port A. Signal is routed through common mode choke CHOKE4 and protected by ESD device U9.
4	GNDA	GND	✅	GNDA is the ground reference for USB port A, connected to the main GND net.
5	SSRX-	USB3_RX0N_C	✅	SSRX- is the USB 3.0 SuperSpeed receive negative signal for port A. Signal is routed through common mode choke CHOKE1 and protected by ESD device U29.
6	SSRX+	USB3_RX0P_C	✅	SSRX+ is the USB 3.0 SuperSpeed receive positive signal for port A. Signal is routed through common mode choke CHOKE1 and protected by ESD device U29.
7	GND_DRAIN	GND	✅	GND_DRAIN is a drain/shield ground connection, connected to the main GND net.
8	SSTX-	USB3_TX0N_C	✅	SSTX- is the USB 3.0 SuperSpeed transmit negative signal for port A. Signal is routed through common mode choke CHOKE2 with AC coupling capacitor C191 and protected by ESD device U29.
9	SSTX+	USB3_TX0P_C	✅	SSTX+ is the USB 3.0 SuperSpeed transmit positive signal for port A. Signal is routed through common mode choke CHOKE2 with AC coupling capacitor C192 and protected by ESD device U29.
10	VBUSB	VBUS2	✅	VBUSB provides 5V power to USB port B. Power is sourced from U32 power switch through ferrite bead L2, with ESD protection from U8 and multiple bypass capacitors.
11	DB-	USB_L1	✅	DB- is the USB 2.0 D- signal for port B. Signal is routed through common mode choke CHOKE3 and protected by ESD device U8.
12	DB+	USB_H1	✅	DB+ is the USB 2.0 D+ signal for port B. Signal is routed through common mode choke CHOKE3 and protected by ESD device U8.
13	GNDB	GND	✅	GNDB is the ground reference for USB port B, connected to the main GND net.
MH1	SHIELD1	GND_EARTH	✅	Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity.
MH2	SHIELD2	GND_EARTH	✅	Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity.
MH3	SHIELD3	GND_EARTH	✅	Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity.
MH4	SHIELD4	GND_EARTH	✅	Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity.

C211 - 123-0004408 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to main GND net. This capacitor provides optional capacitive coupling between main ground and shield ground for conducted immunity.
2	2	GND_EARTH	✅	Connected to GND_EARTH net (USB shield ground). This capacitor provides optional capacitive coupling between shield ground and main ground for conducted immunity.

J10 - 5177985-2 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
2	2	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
13	13	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
14	14	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
25	25	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
26	26	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
37	37	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
38	38	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
49	49	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
50	50	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
59	59	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
60	60	GND	✅	Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability.
3	3	mSATA_TX_P	✅	mSATA transmit positive differential signal, part of SATA TX pair with pin 5.
4	4	mSATA_RX_P	✅	mSATA receive positive differential signal, part of SATA RX pair with pin 6.
5	5	mSATA_TX_N	✅	mSATA transmit negative differential signal, part of SATA TX pair with pin 3.
6	6	mSATA_RX_N	✅	mSATA receive negative differential signal, part of SATA RX pair with pin 4.
7	7	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
8	8	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
19	19	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
20	20	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
31	31	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
32	32	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
43	43	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
44	44	+5VSB	✅	5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance.
9	9	mPCIE_REFCLK_P	✅	mPCIE reference clock positive differential signal, part of REFCLK pair with pin 11. Test point TP19 is DNI.
10	10	USB_HOST_DP	✅	USB host data positive signal, part of USB differential pair with pin 12.
11	11	mPCIE_REFCLK_N	✅	mPCIE reference clock negative differential signal, part of REFCLK pair with pin 9. Test point TP20 is DNI.
12	12	USB_HOST_DN	✅	USB host data negative signal, part of USB differential pair with pin 10.
15	15	mPCIE_TX_P	✅	mPCIE transmit positive differential signal, part of PCIe TX pair with pin 17. Test point TP21 is DNI.
16	16	mPCIE_RX_N	✅	mPCIE receive differential pair with intentional polarity inversion. Pin 16 carries negative signal (mPCIE_RX_N) and pin 18 carries positive signal (mPCIE_RX_P). This inversion is noted as intentional for routing ease and is acceptable in PCIe.
18	18	mPCIE_RX_P	✅	mPCIE receive differential pair with intentional polarity inversion. Pin 16 carries negative signal (mPCIE_RX_N) and pin 18 carries positive signal (mPCIE_RX_P). This inversion is noted as intentional for routing ease and is acceptable in PCIe.
17	17	mPCIE_TX_N	✅	mPCIE transmit negative differential signal, part of PCIe TX pair with pin 15. Test point TP22 is DNI.
21	21	I2C6_SCL	✅	I2C clock line with 10K pull-up resistor to +V1P8S through R13.
22	22	mPCIE_WAKEB	✅	mPCIE wake signal (active low) for power management.
23	23	I2C6_SDA	✅	I2C data line with 10K pull-up resistor to +V1P8S through R14.
24	24	mPCIe_CLKREQ3_B	✅	mPCIE clock request signal (active low) for power management.
27	27	EXP_GPIO1	✅	Expansion GPIO signals for general purpose I/O.
28	28	EXP_GPIO3	✅	Expansion GPIO signals for general purpose I/O.
29	29	EXP_GPIO2	✅	Expansion GPIO signals for general purpose I/O.
30	30	EXP_GPIO4	✅	Expansion GPIO signals for general purpose I/O.
33	33	XDP_H_OBSDATA_A1	✅	XDP observation data signals for debug functionality.
34	34	XDP_H_OBSDATA_A0	✅	XDP observation data signals for debug functionality.
35	35	XDP_H_OBSDATA_A2	✅	XDP observation data signals for debug functionality.
36	36	XDP_H_OBSDATA_A3	✅	XDP observation data signals for debug functionality.
39	39	XDP_H_PRDYB	✅	XDP ready signal (active low) for debug handshaking.
40	40	XDP_H_PREQB_PB	✅	XDP request signal (active low) buffered through U1 with 200 ohm pull-up to +V1P8A.
41	41	HOOK0	✅	HOOK0 signal connected through 1K series resistor R15 to PMC_RSMRST.
42	42	HOOK1	✅	HOOK1 signal connected through 0 ohm resistor R5 to FP_PWRBTN. Optional 4.7K pull-down R4 is DNI.
45	45	HOOK2	✅	HOOK2 signal connected through 1K series resistor R16 to PMC_CORE_PWROK.
46	46	PMC_RSTBTN	✅	Reset button signal with 1K pull-up to +V1P8S through R6 and 0.1uF debounce capacitor C1 to ground.
47	47	HOOK6	✅	HOOK6 signal connected through 1K series resistor R17 to PMC_PLTRST_R_V1P8.
48	48	ILB_RTC_TESTB	✅	RTC test signal (active low) with 1K pull-up to +RTCVCC through R7 and 1uF filter capacitor C2 to ground.
51	51	HOOK4	✅	HOOK4 signal connected through 0 ohm resistor R18 to +3VSB power rail.
52	52	XDP_H_TRSTB	✅	XDP test reset signal (active low) for JTAG debug interface.
53	53	HOOK5	✅	HOOK5 signal connected through 0 ohm resistor R20 to +V1P8S power rail.
54	54	XDP_H_TCK	✅	XDP test clock signal for JTAG debug interface.
55	55	+V1P8A	✅	1.8V analog power supply pin with decoupling capacitor C5 nearby.
56	56	XDP_H_TMS	✅	XDP test mode select signal for JTAG debug interface.
57	57	XDP_H_TDO	✅	XDP test data output signal with 51 ohm series termination resistor R21 from +V1P8A.
58	58	XDP_H_TDI	✅	XDP test data input signal for JTAG debug interface.

R3 - 200 ohm resistor ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XDP_H_PREQB_PB	✅	Connected to XDP_H_PREQB_PB signal, providing pull-up function for the buffer input.
2	2	+V1P8A	✅	Connected to +V1P8A supply, providing the pull-up voltage source.

U1 - SN74AUP1G34 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin is correctly left unconnected per datasheet specification.
2	A	XDP_H_PREQB_PB	✅	Input pin A is connected to XDP_H_PREQB_PB signal with a 200 ohm pull-up resistor (R3) to +V1P8A, which is appropriate for this buffer application.
3	GND	GND	✅	Ground pin is correctly connected to the GND net.
4	Y	XDP_H_PREQB	✅	Output pin Y is connected to XDP_H_PREQB net, correctly buffering the input signal.
5	VCC	+V1P8A	✅	VCC pin is connected to +V1P8A (1.8V analog supply) with appropriate bypass capacitor C5 (0.1uF) nearby.

R14 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SDA	✅	Pin 1 connects to I2C6_SDA and serves as one end of the pull-up resistor for the I2C data line.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C6_SDA line.

R13 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SCL	✅	Pin 1 connects to I2C6_SCL and serves as one end of the pull-up resistor for the I2C clock line.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C6_SCL line.

C1 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal for debouncing and filtering. Works in conjunction with pull-up resistor R6.
2	2	GND	✅	Connected to GND, completing the debouncing filter to ground. The 25V rating provides adequate margin for the 1.8V signal.

R6 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal, which goes to connector J10 pin 46 and debouncing capacitor C1. This pin provides the pull-up connection for the reset button signal.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing pull-up voltage for the reset button signal. The 1kΩ value is appropriate for a 1.8V logic level pull-up.

R7 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	ILB_RTC_TESTB	✅	Connected to ILB_RTC_TESTB signal, which is pulled up to +RTCVCC through this resistor and filtered to ground through C2.
2	2	+RTCVCC	✅	Connected to +RTCVCC power rail, providing pull-up voltage for the ILB_RTC_TESTB signal.

C2 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for filtering the ILB_RTC_TESTB signal.
2	2	ILB_RTC_TESTB	✅	Connected to ILB_RTC_TESTB signal, providing noise filtering in conjunction with pull-up resistor R7.

R21 - 110-0002078 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A power rail, forming one side of a 51-ohm pull-up resistor for the XDP_H_TDO JTAG signal.
2	2	XDP_H_TDO	✅	Connected to XDP_H_TDO (JTAG Test Data Out signal). The 51-ohm pull-up configuration is highly unusual for a TDO signal but may be a specific requirement for Intel's XDP interface.

C5 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the decoupling capacitor.
2	2	+V1P8A	✅	Connected to +V1P8A power rail, providing decoupling for U1 buffer IC.

C252 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL1	✅	27pF load capacitor for crystal oscillator XTAL1 pin.
2	2	GND	✅	27pF load capacitor for crystal oscillator XTAL1 pin.

C253 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	27pF load capacitor for crystal oscillator XTAL2 pin.
2	2	GND	✅	27pF load capacitor for crystal oscillator XTAL2 pin.

R836 - 1120-0018 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	4.99K resistor connecting RSET pin to GND to set internal reference current.
2	2	LAN_RSET	✅	4.99K resistor connecting RSET pin to GND to set internal reference current.

C425 - 2221-0017 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2588	✅	0.039uF flying capacitor for internal charge pump between CTOP and CBOT pins.
2	2	$18N2590	✅	0.039uF flying capacitor for internal charge pump between CTOP and CBOT pins.

R827 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	10K pullup resistor for DEV_OFF_N control signal.
2	2	$18N3540	✅	10K pullup resistor for DEV_OFF_N control signal.

R828 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	10K pullup resistor for LAN_PWR_GOOD output signal.
2	2	$18N3538	✅	10K pullup resistor for LAN_PWR_GOOD output signal.

U42 - 4300-0071 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	LAN_PWR_GOOD	$18N3538	✅	LAN_PWR_GOOD output with 10K pullup to +3VSB_LAN. This is a power good indicator signal.
2	NC_SI_CLK_IN	$18N3372	✅	Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K.
3	NC_SI_CRS_DV	$18N3374	✅	Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K.
5	NC_SI_RXD1	$18N3305	✅	Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K.
6	NC_SI_RXD0	$18N3303	✅	Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K.
7	NC_SI_TX_EN	$18N3376	✅	Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K.
8	NC_SI_TXD1	$18N3301	✅	Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K.
9	NC_SI_TXD0	$18N3299	✅	Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K.
4	JTAG_TDO		✅	JTAG_TDO is not connected. This is acceptable as JTAG may not be used in production.
10	VDD3P3_10	+3VSB_LAN	✅	VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling.
27	VDD3P3_27	+3VSB_LAN	✅	VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling.
41	VDD3P3_41	+3VSB_LAN	✅	VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling.
51	VDD3P3_51	+3VSB_LAN	✅	VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling.
64	VDD3P3_64	+3VSB_LAN	✅	VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling.
11	VDD0P9_11	+0V9_LAN	✅	VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling.
32	VDD0P9_32	+0V9_LAN	✅	VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling.
42	VDD0P9_42	+0V9_LAN	✅	VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling.
59	VDD0P9_59	+0V9_LAN	✅	VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling.
12	NVM_SI	$18N2399	✅	NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity.
13	NVM_SK	$18N2397	✅	NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity.
14	NVM_SO	$18N3554	✅	NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity.
15	NVM_CS_N	$18N2395	✅	NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity.
16	PE_WAKE_N	PMC_PCIE_WAKE	✅	PE_WAKE_N connected to PMC_PCIE_WAKE for PCIe wake signaling.
17	PE_RST_N	PMC_PLTRST_L	✅	PE_RST_N connected to PMC_PLTRST_L for PCIe reset signaling.
18	JTAG_TMS	$18N3293	✅	JTAG pins (TMS, CLK, TDI) have 10K pullups to +3VSB_LAN, which is standard practice to prevent floating inputs.
19	JTAG_CLK	$18N3295	✅	JTAG pins (TMS, CLK, TDI) have 10K pullups to +3VSB_LAN, which is standard practice to prevent floating inputs.
29	JTAG_TDI	$18N3297	✅	JTAG pins (TMS, CLK, TDI) have 10K pullups to +3VSB_LAN, which is standard practice to prevent floating inputs.
20	PE_TXN	PCIE_C_RXP2	✅	PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification.
21	PE_TXP	PCIE_C_RXN2	✅	PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification.
23	PE_RXN	PCIE_C_TXP2	✅	PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification.
24	PE_RXP	PCIE_C_TXN2	✅	PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification.
22	NC/INTVCC		✅	NC/INTVCC pin is not connected, indicating internal voltage regulator is not used.
25	PECLK_N	PCIE_CLK-N2	✅	PCIe clock differential pair (PECLK_P/N) correctly connected to PCIE_CLK-P2/N2 with test points.
26	PECLK_P	PCIE_CLK-P2	✅	PCIe clock differential pair (PECLK_P/N) correctly connected to PCIE_CLK-P2/N2 with test points.
28	DEV_OFF_N	$18N3540	✅	DEV_OFF_N with 10K pullup to +3VSB_LAN for device off control.
30	LED1	LAN-LED1	✅	LED output pins correctly connected with current limiting resistors and EMI filtering capacitors.
31	LED0	LAN-LED0	✅	LED output pins correctly connected with current limiting resistors and EMI filtering capacitors.
33	LED2	LAN-LED2	✅	LED output pins correctly connected with current limiting resistors and EMI filtering capacitors.
34	SMB_CLK	LAN-SMB-CLK	✅	SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected for system management.
35	SMB_ALRT_N	LAN-SMB-ALERT#	✅	SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected for system management.
36	SMB_DATA	LAN-SMB-DATA	✅	SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected for system management.
37	CBOT	$18N2590	✅	CBOT and CTOP pins correctly connected through 0.039uF flying capacitor for internal charge pump.
40	CTOP	$18N2588	✅	CBOT and CTOP pins correctly connected through 0.039uF flying capacitor for internal charge pump.
38	VDD0P9_OUT	+0V9_LAN	✅	VDD0P9_OUT connected to +0V9_LAN, output from internal 0.9V regulator.
39	VDD1P5_OUT	+1V5_LAN	✅	VDD1P5_OUT connected to +1V5_LAN, output from internal 1.5V regulator.
43	NC_SI_ARB_IN		✅	Serial interface arbitration pins (NC_SI_ARB_IN/OUT) are not connected, which is acceptable as the serial interface is not used.
44	NC_SI_ARB_OUT		✅	Serial interface arbitration pins (NC_SI_ARB_IN/OUT) are not connected, which is acceptable as the serial interface is not used.
45	XTAL2	LAN_XTAL2	✅	Crystal oscillator pins correctly connected to 25MHz crystal X1 with 27pF load capacitors.
46	XTAL1	LAN_XTAL1	✅	Crystal oscillator pins correctly connected to 25MHz crystal X1 with 27pF load capacitors.
47	VDD1P5_47	+1V5_LAN	✅	VDD1P5 power pins correctly connected to +1V5_LAN supply with appropriate decoupling.
56	VDD1P5_56	+1V5_LAN	✅	VDD1P5 power pins correctly connected to +1V5_LAN supply with appropriate decoupling.
48	RSET	LAN_RSET	✅	RSET pin correctly connected to GND through 4.99K resistor to set internal reference current.
49	MDI_MINUS3/SER_N	MDI_N3	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
50	MDI_PLUS3/SER_P	MDI_P3	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
52	MDI_MINUS2/SET_N	MDI_N2	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
53	MDI_PLUS2	MDI_P2	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
54	MDI_MINUS1/SRDS_SIG_DET	MDI_N1	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
55	MDI_PLUS1/SFP_I2C_CLK	MDI_P1	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
57	MDI_MINUS0/SFP_I2C_DATA	MDI_N0	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
58	MDI_PLUS0/NC	MDI_P0	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface.
60	SDP3		✅	Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used.
61	SDP1/PCIE_DIS		✅	Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used.
62	SDP2		✅	Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used.
63	SDP0		✅	Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used.
65	GND_PAD	GND	✅	Ground pad correctly connected to GND.

X1 - 145-0004792 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Crystal output connected to U42 XTAL2 pin with 27pF load capacitor.
2	2	GND	✅	Crystal ground pins correctly connected to GND.
4	4	GND	✅	Crystal ground pins correctly connected to GND.
3	3	LAN_XTAL1	✅	Crystal input connected to U42 XTAL1 pin with 27pF load capacitor.

R832 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2435	✅	Connected to the SI pin of U43 (SPI flash memory) on net $18N2435.
2	2	$18N2399	✅	Connected to the NVM_SI pin of U42 (Ethernet controller) on net $18N2399.

R835 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2439	✅	Connected to the CS# pin of U43 (SPI flash memory) on net $18N2439.
2	2	$18N2395	✅	Connected to the NVM_CS_N pin of U42 (Ethernet controller) on net $18N2395.

R834 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2437	✅	Connected to the SCK pin of U43 (SPI flash memory) on net $18N2437.
2	2	$18N2397	✅	Connected to the NVM_SK pin of U42 (Ethernet controller) on net $18N2397.

R831 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Connected to +3VSB_LAN power rail.
2	2	$18N3659	✅	Connected to the HOLD# pin of U43 (SPI flash memory) on net $18N3659.

R848 - 1120-0359 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Connected to +3VSB_LAN power rail.
2	2	$18N2435	✅	Connected to the SI pin of U43 (SPI flash memory) on net $18N2435.

R830 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Connected to +3VSB_LAN power rail.
2	2	$18N3609	✅	Connected to the WP# pin of U43 (SPI flash memory) on net $18N3609.

U43 - AT25DF081A-SSH ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	$18N2439	✅	CS# (Chip Select) is correctly connected through a 33.2Ω series resistor (R835) to the NVM_CS_N pin of the Ethernet controller U42.
2	SO	$18N3552	✅	SO (Serial Output) is correctly connected through a 33.2Ω series resistor (R833) to the NVM_SO pin of the Ethernet controller U42.
3	WP#	$18N3609	✅	WP# (Write Protect) is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R830), following datasheet recommendations.
4	GND	GND	✅	GND is correctly connected to the ground reference.
5	SI	$18N2435	✅	SI (Serial Input) is correctly connected through a 33.2Ω series resistor (R832) to the NVM_SI pin of U42, with a 33.2KΩ pull-up to +3VSB_LAN (R848).
6	SCK	$18N2437	✅	SCK (Serial Clock) is correctly connected through a 33.2Ω series resistor (R834) to the NVM_SK pin of the Ethernet controller U42.
7	HOLD#	$18N3659	✅	HOLD# is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R831), following datasheet recommendations.
8	VCC	+3VSB_LAN	✅	VCC is correctly connected to +3VSB_LAN, which should provide 3.3V within the device's 2.7V to 3.6V operating range.

R833 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3554	✅	Connected to the NVM_SO pin of U42 (Ethernet controller) on net $18N3554.
2	2	$18N3552	✅	Connected to the SO pin of U43 (SPI flash memory) on net $18N3552.

J11 - 3362-0042 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	MD1+	MDI_P0	✅	MDI_P0/MDI_N0 differential pair correctly connected to PHY U42 pins 58/57 for Ethernet data transmission.
2	MD1-	MDI_N0	✅	MDI_P0/MDI_N0 differential pair correctly connected to PHY U42 pins 58/57 for Ethernet data transmission.
3	MD2+	MDI_P1	✅	MDI_P1/MDI_N1 differential pair correctly connected to PHY U42 pins 55/54 for Ethernet data transmission.
4	MD2-	MDI_N1	✅	MDI_P1/MDI_N1 differential pair correctly connected to PHY U42 pins 55/54 for Ethernet data transmission.
5	CT1	$18N3856	✅	Center tap pins correctly connected to common node with bypass capacitors for common mode filtering.
6	CT2	$18N3856	✅	Center tap pins correctly connected to common node with bypass capacitors for common mode filtering.
7	MD3+	MDI_P2	✅	MDI_P2/MDI_N2 differential pair correctly connected to PHY U42 pins 53/52 for Ethernet data transmission.
8	MD3-	MDI_N2	✅	MDI_P2/MDI_N2 differential pair correctly connected to PHY U42 pins 53/52 for Ethernet data transmission.
9	MD4+	MDI_P3	✅	MDI_P3/MDI_N3 differential pair correctly connected to PHY U42 pins 50/49 for Ethernet data transmission.
10	MD4-	MDI_N3	✅	MDI_P3/MDI_N3 differential pair correctly connected to PHY U42 pins 50/49 for Ethernet data transmission.
11	LED2_AC1	LAN-LED0	✅	LED2 pins configured as a bi-directional LED driven by two PHY outputs (LED0 and LED2). Pin 11 connects directly to U42 LED0 output, while pin 12 connects through R844 (301Ω) to U42 LED2 output. The single series resistor R844 provides current limiting in both directions, making this configuration correct for bi-directional LED operation.
12	LED2_AD1	1G-LED-N	✅	LED2 pins configured as a bi-directional LED driven by two PHY outputs (LED0 and LED2). Pin 11 connects directly to U42 LED0 output, while pin 12 connects through R844 (301Ω) to U42 LED2 output. The single series resistor R844 provides current limiting in both directions, making this configuration correct for bi-directional LED operation.
13	LED1_C	LINK-LED-N	✅	LED1 correctly configured with anode to power supply and cathode through current limiting resistor to PHY LED1 output for active-low drive.
14	LED1_A	+3VSB_LAN	✅	LED1 correctly configured with anode to power supply and cathode through current limiting resistor to PHY LED1 output for active-low drive.
15	SHLD1	GND_EARTH	✅	Shield pins correctly connected to earth ground for EMI shielding and ESD protection.
16	SHLD2	GND_EARTH	✅	Shield pins correctly connected to earth ground for EMI shielding and ESD protection.

R843 - 1120-0203 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED1	✅	Current limiting resistor for LED1. Pin 1 connects to U42 LED1 output (LAN-LED1), pin 2 connects to J11 LED1 cathode (LINK-LED-N). The 301Ω value provides appropriate LED current limiting for approximately 4-5mA at 3.3V.
2	2	LINK-LED-N	✅	Current limiting resistor for LED1. Pin 1 connects to U42 LED1 output (LAN-LED1), pin 2 connects to J11 LED1 cathode (LINK-LED-N). The 301Ω value provides appropriate LED current limiting for approximately 4-5mA at 3.3V.

R844 - 1120-0203 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED2	✅	Current limiting resistor for LED2 in a bi-directional configuration. Pin 1 connects to U42 LED2 output (LAN-LED2), pin 2 connects to J11 LED2 pin 12 (1G-LED-N). The single 301Ω resistor limits current in both directions for the bi-directional LED.
2	2	1G-LED-N	✅	Current limiting resistor for LED2 in a bi-directional configuration. Pin 1 connects to U42 LED2 output (LAN-LED2), pin 2 connects to J11 LED2 pin 12 (1G-LED-N). The single 301Ω resistor limits current in both directions for the bi-directional LED.

C429 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LINK-LED-N	✅	EMI filter capacitor on LED1 signal line. Pin 1 connects to LINK-LED-N (LED1 cathode signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression without affecting LED switching speed.
2	2	GND	✅	EMI filter capacitor on LED1 signal line. Pin 1 connects to LINK-LED-N (LED1 cathode signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression without affecting LED switching speed.

C430 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1G-LED-N	✅	EMI filter capacitor on LED2 signal line. Pin 1 connects to 1G-LED-N (LED2 pin 12 signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression.
2	2	GND	✅	EMI filter capacitor on LED2 signal line. Pin 1 connects to 1G-LED-N (LED2 pin 12 signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression.

C431 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED0	✅	EMI filter capacitor on LAN-LED0 signal line. Pin 1 connects to LAN-LED0 (LED2 pin 11 signal from U42 LED0 output), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression.
2	2	GND	✅	EMI filter capacitor on LAN-LED0 signal line. Pin 1 connects to LAN-LED0 (LED2 pin 11 signal from U42 LED0 output), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression.

FB12 - 3044-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB	✅	Input pin connected to +3VSB standby power rail, serving as the source for the LAN subsystem power filter.
2	2	+3VSB_LAN	✅	Output pin connected to +3VSB_LAN filtered power rail, providing clean power to the LAN controller U42, SPI flash U43, and associated circuitry.

R837 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3372	✅	Connected to U42 pin 2 (NC_SI_CLK_IN) via net $18N3372, providing a 1K pull-down resistor for this configuration pin.
2	2	GND	✅	Connected to GND, completing the pull-down resistor function.

R838 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3374	✅	Connected to U42 pin 3 (NC_SI_CRS_DV) via net $18N3374, providing a 1K pull-down resistor for this configuration pin.
2	2	GND	✅	Connected to GND, completing the pull-down resistor function.

R839 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3376	✅	Connected to U42 pin 7 (NC_SI_TX_EN) via net $18N3376, providing a 1K pull-down resistor for this configuration pin.
2	2	GND	✅	Connected to GND, completing the pull-down resistor function.

C426 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Connected to the center tap network ($18N3856) of the Ethernet transformer in J11. This pin, along with C427 and C428, provides high-frequency filtering for the center taps.
2	2	GND	✅	Connected to ground, providing the return path for center tap filtering.

C427 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Connected to the center tap network ($18N3856) of the Ethernet transformer in J11. This pin, along with C426 and C428, provides high-frequency filtering for the center taps.
2	2	GND	✅	Connected to ground, providing the return path for center tap filtering.

C428 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Connected to the center tap network ($18N3856) of the Ethernet transformer in J11. This pin provides low-frequency filtering for the center taps.
2	2	GND	✅	Connected to ground, providing the return path for center tap filtering.

U7 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	UART2_RXD	✅	B2 pin connected to UART2_RXD on the 3.3V side of the level translator.
2	GND	GND	✅	GND pin correctly connected to ground plane.
3	VCCA	+V1P8S	✅	VCCA pin connected to +V1P8S with appropriate decoupling.
4	A2	SIO_UART2_RXD	✅	A2 pin connected to SIO_UART2_RXD on the 1.8V SOC side.
5	A1	SIO_UART2_TXD	✅	A1 pin connected to SIO_UART2_TXD on the 1.8V SOC side.
6	OE	PMC_PLTRST_R_V1P8	✅	OE pin connected to PMC_PLTRST_R_V1P8 to enable the translator when platform is out of reset.
7	VCCB	+3VSB	✅	VCCB pin connected to +3VSB with appropriate decoupling.
8	B1	UART2_TXD	✅	B1 pin connected to UART2_TXD on the 3.3V side of the level translator.

U15 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA pin connected to +V1P8S with appropriate decoupling.
2	A1	SIO_UART1_RTSB	✅	A1 pin connected to SIO_UART1_RTSB on the 1.8V SOC side.
3	A2	SIO_UART1_CTSB	✅	A2 pin connected to SIO_UART1_CTSB on the 1.8V SOC side.
4	A3	SIO_UART1_RXD	✅	A3 pin connected to SIO_UART1_RXD on the 1.8V SOC side.
5	A4	SIO_UART1_TXD	✅	A4 pin connected to SIO_UART1_TXD on the 1.8V SOC side.
6	GND	GND	✅	GND pin correctly connected to ground plane.
7	B4	UART1_TXD	✅	B4 pin connected to UART1_TXD on the 3.3V side of the level translator.
8	B3	UART1_RXD	✅	B3 pin connected to UART1_RXD on the 3.3V side of the level translator.
9	B2	UART1_CTSB	✅	B2 pin connected to UART1_CTSB on the 3.3V side of the level translator.
10	B1	UART1_RTSB	✅	B1 pin connected to UART1_RTSB on the 3.3V side of the level translator.
11	VCCB	+3VSB	✅	VCCB pin connected to +3VSB with appropriate decoupling.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin connected to PMC_PLTRST_R_V1P8 to enable the translator when platform is out of reset.

U14 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S, providing the 1.8V reference voltage for the A-side of the level translator.
2	A1	SOC_SIO_SPI_CLK	✅	A1 is correctly connected to SOC_SIO_SPI_CLK, the 1.8V SPI clock signal from the SOC.
3	A2	SOC_SIO_SPI_MOSI	✅	A2 is correctly connected to SOC_SIO_SPI_MOSI, the 1.8V SPI MOSI signal from the SOC.
4	A3	SOC_SIO_SPI_MISO	✅	A3 is correctly connected to SOC_SIO_SPI_MISO, the 1.8V SPI MISO signal from the SOC.
5	A4	SOC_SIO_SPI_CS1	✅	A4 is correctly connected to SOC_SIO_SPI_CS1, the 1.8V SPI chip select signal from the SOC.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	SIO_SPI_CS1	✅	B4 is correctly connected to SIO_SPI_CS1, the 3.3V translated SPI chip select signal.
8	B3	SIO_SPI_MISO	✅	B3 is correctly connected to SIO_SPI_MISO, the 3.3V translated SPI MISO signal.
9	B2	SIO_SPI_MOSI	✅	B2 is correctly connected to SIO_SPI_MOSI, the 3.3V translated SPI MOSI signal.
10	B1	SIO_SPI_CLK	✅	B1 is correctly connected to SIO_SPI_CLK, the 3.3V translated SPI clock signal.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB, providing the 3.3V reference voltage for the B-side of the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset.

U10 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to the 1.8V supply rail (+V1P8A) with proper decoupling.
2	A1	SOC_GPIO_S5_2	✅	A1 is correctly connected to SOC_GPIO_S5_2 for level translation to the 3.3V domain.
3	A2	SOC_GPIO_S5_1	✅	A2 is correctly connected to SOC_GPIO_S5_1 for level translation to the 3.3V domain.
4	A3	SOC_GPIO_S5_0	✅	A3 is correctly connected to SOC_GPIO_S5_0 for level translation to the 3.3V domain.
5	A4		✅	A4 is left unconnected as the fourth channel is not needed in this design.
6	GND	GND	✅	GND is correctly connected to the ground plane.
7	B4	GND	✅	A4 (pin 5) and B4 (pin 7) form the fourth channel of the level translator, which is intentionally unused. A4 is left floating while B4 is grounded, an acceptable configuration for disabling an unused channel.
8	B3	GPIO_S5_0	✅	B3 is correctly connected to GPIO_S5_0 for the translated 3.3V signal output.
9	B2	GPIO_S5_1	✅	B2 is correctly connected to GPIO_S5_1 for the translated 3.3V signal output.
10	B1	GPIO_S5_2	✅	B1 is correctly connected to GPIO_S5_2 for the translated 3.3V signal output.
11	VCCB	+PS_3VSB	✅	VCCB is correctly connected to the 3.3V standby supply (+PS_3VSB) with proper decoupling.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8 to enable the translator when the platform is out of reset.

U16 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA power supply pin correctly connected to +V1P8S (1.8V) with nearby decoupling capacitor C352.
2	A1	I2S_DATIN_R	✅	A1 is correctly connected to I2S_DATIN_R, which translates to the corresponding B1 pin (I2SDI_GPIO) for I2S data input signal level translation.
3	A2	I2S_DATOUT_R	✅	A2 is correctly connected to I2S_DATOUT_R, which translates to the corresponding B2 pin (I2SDO_GPIO) for I2S data output signal level translation.
4	A3	I2S_FRM_R	✅	A3 (I2S_FRM_R) correctly connects to B3 (I2SFRM_GPIO) for I2S frame sync signal translation from 1.8V to 3.3V.
5	A4	I2S_CLK_R	✅	A4 (I2S_CLK_R) correctly connects to B4 (I2SCLK_GPIO) for I2S clock signal translation from 1.8V to 3.3V.
6	GND	GND	✅	GND pin correctly connected to ground plane.
7	B4	I2SCLK_GPIO	✅	B4 (I2SCLK_GPIO) correctly pairs with A4 (I2S_CLK_R) for clock signal.
8	B3	I2SFRM_GPIO	✅	B3 (I2SFRM_GPIO) correctly pairs with A3 (I2S_FRM_R) for frame sync signal.
9	B2	I2SDO_GPIO	✅	B2 is correctly connected to I2SDO_GPIO, corresponding to A2 (I2S_DATOUT_R) for I2S data output signal level translation on the 3.3V side.
10	B1	I2SDI_GPIO	✅	B1 is correctly connected to I2SDI_GPIO, corresponding to A1 (I2S_DATIN_R) for I2S data input signal level translation on the 3.3V side.
11	VCCB	+3VSB	✅	VCCB power supply pin correctly connected to +3VSB (3.3V) with nearby decoupling capacitor C353.
12	OE	PMC_PLTRST_R_V1P8	✅	OE (output enable) pin correctly connected to PMC_PLTRST_R_V1P8, a 1.8V level control signal matching VCCA voltage.

U17 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA power supply pin correctly connected to +V1P8S (1.8V) with nearby decoupling capacitor C348.
2	A1	I2S_MCLK	✅	A1 (I2S_MCLK) correctly connects to B1 (I2SMCLK_GPIO) for I2S master clock signal translation from 1.8V to 3.3V.
3	A2	SOC_PWM1	✅	A2 (SOC_PWM1) correctly connects to B2 (PWM1) for PWM signal translation from 1.8V to 3.3V.
4	A3	SOC_PWM0	✅	A3 (SOC_PWM0) correctly connects to B3 (PWM0) for PWM signal translation from 1.8V to 3.3V.
5	A4		✅	Channel 4 is unused with A4 left floating and B4 grounded. This asymmetric configuration is unusual but acceptable, as it appears to be an intentional design pattern repeated in other similar components (U10) on the schematic.
7	B4	GND	✅	Channel 4 is unused with A4 left floating and B4 grounded. This asymmetric configuration is unusual but acceptable, as it appears to be an intentional design pattern repeated in other similar components (U10) on the schematic.
6	GND	GND	✅	GND pin correctly connected to ground plane.
8	B3	PWM0	✅	B3 (PWM0) correctly pairs with A3 (SOC_PWM0) for PWM signal.
9	B2	PWM1	✅	B2 (PWM1) correctly pairs with A2 (SOC_PWM1) for PWM signal.
10	B1	I2SMCLK_GPIO	✅	B1 (I2SMCLK_GPIO) correctly pairs with A1 (I2S_MCLK) for master clock signal.
11	VCCB	+3VSB	✅	VCCB power supply pin correctly connected to +3VSB (3.3V) with nearby decoupling capacitor C349.
12	OE	PMC_PLTRST_R_V1P8	✅	OE (output enable) pin correctly connected to PMC_PLTRST_R_V1P8, a 1.8V level control signal matching VCCA voltage.

R818 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N2079	✅	This 0-ohm jumper is correctly marked DNI (Do Not Install) for 3.3V operation, preventing connection of $20N2079 to +V1P8A.
2	2	+V1P8A	✅	This 0-ohm jumper is correctly marked DNI (Do Not Install) for 3.3V operation, preventing connection of $20N2079 to +V1P8A.

R152 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N2079	✅	This 0-ohm jumper is correctly populated to connect $20N2079 to +3VSB, selecting 3.3V operation for the W25Q64BVSSIG flash.
2	2	+3VSB	✅	This 0-ohm jumper is correctly populated to connect $20N2079 to +3VSB, selecting 3.3V operation for the W25Q64BVSSIG flash.

U3 - W25Q64BVSSIG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPI_CS0	✅	CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pull-up resistor to +V_SPI, ensuring the flash is deselected when not actively driven.
2	SO/IO1	SPI_MISO	✅	SO/IO1 (Serial Data Output) is correctly connected to SPI_MISO for reading data from the flash memory.
3	WP#/IO2	SPI_WP	✅	WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pull-up to +V_SPI, disabling write protection by default.
4	GND	GND	✅	GND pin is correctly connected to the ground plane.
5	SI/IO0	SPI_MOSI	✅	SI/IO0 (Serial Data Input) is correctly connected to SPI_MOSI for writing data to the flash memory.
6	SCK	SPI_CLK	✅	SCK (Serial Clock) is correctly connected to SPI_CLK for clocking SPI transactions.
7	HOLD#/IO3	SPI_HOLD	✅	HOLD#/IO3 (Hold Input) is correctly connected to SPI_HOLD with a 10K pull-up to +V_SPI, disabling the hold function by default.
8	VCC	+V_SPI	✅	VCC (Power Supply) is correctly connected to +V_SPI, which provides 3.0-3.1V from +3VSB through diode D8, meeting the 2.7-3.6V requirement for the 3.3V version of this flash.

J1 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDP_VCC	✅	Pin 1 is correctly connected to DDP_VCC, allowing the DediProg programmer to provide power to the circuit.
2	2	GND	✅	Pin 2 is correctly connected to GND, providing ground reference for the programmer interface.
3	3	SPI_CS0	✅	Pin 3 is correctly connected to SPI_CS0, providing chip select access to the SPI flash for the programmer.
4	4	SPI_CLK	✅	Pin 4 is correctly connected to SPI_CLK, providing clock access to the SPI flash for the programmer.
5	5	SPI_MISO	✅	Pin 5 is correctly connected to SPI_MISO, providing data output access from the SPI flash for the programmer.
6	6	SPI_MOSI	✅	Pin 6 is correctly connected to SPI_MOSI, providing data input access to the SPI flash for the programmer.
7	7		✅	Pin 7 has no connection, which is acceptable as not all pins are required for the programming interface.
8	8	DDP_IO3L	✅	Pin 8 is correctly connected to DDP_IO3L, allowing the programmer to control the voltage translator enable signal.

D8 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	DDP_VCC	✅	Anode 1 is correctly connected to DDP_VCC, allowing the DediProg programmer to provide power to the SPI flash when connected.
A2	A2	$20N2079	✅	Anode 2 is correctly connected to $20N2079, which is tied to +3VSB through R152, providing board power to the SPI flash.
C	C	+V_SPI	✅	Common cathode is correctly connected to +V_SPI, providing the OR-ed power supply output to the SPI flash at approximately 3.0-3.1V.

R147 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	This 100K pull-up resistor correctly pulls DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control through J1.
2	2	DDP_IO3L	✅	This 100K pull-up resistor correctly pulls DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control through J1.

U18 - NTB0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the 1.8V reference voltage for the A-side (SOC) interface.
2	A1	SOC_SPI_MOSI-R	✅	A1 is correctly connected to SOC_SPI_MOSI-R, translating the 1.8V MOSI signal from the SOC to the 3.3V B-side.
3	A2	SOC_SPI_CLK-R	✅	A2 is correctly connected to SOC_SPI_CLK-R, translating the 1.8V clock signal from the SOC to the 3.3V B-side.
4	A3	SOC_SPI_MISO-R	✅	A3 is correctly connected to SOC_SPI_MISO-R, translating the 1.8V MISO signal from the 3.3V B-side back to the SOC.
5	A4	SOC_SPI_CS0B-R	✅	A4 is correctly connected to SOC_SPI_CS0B-R, translating the 1.8V chip select signal from the SOC to the 3.3V B-side.
6	GND	GND	✅	GND pin is correctly connected to the ground plane.
7	B4	SPI_CS0	✅	B4 is correctly connected to SPI_CS0, providing the translated 3.3V chip select signal to the flash and external connector.
8	B3	SPI_MISO	✅	B3 is correctly connected to SPI_MISO, providing the translated 3.3V data output signal from the flash to the SOC and external connector.
9	B2	SPI_CLK	✅	B2 is correctly connected to SPI_CLK, providing the translated 3.3V clock signal to the flash and external connector.
10	B1	SPI_MOSI	✅	B1 is correctly connected to SPI_MOSI, providing the translated 3.3V data input signal to the flash and external connector.
11	VCCB	+V_SPI	✅	VCCB is correctly connected to +V_SPI, providing the 3.0-3.1V reference voltage for the B-side (flash) interface.
12	OE	DDP_IO3L	✅	OE (Output Enable) is correctly connected to DDP_IO3L with a 100K pull-up to +V1P8A, enabling the translator by default while allowing external control.

R266 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C5_SDA	✅	10kΩ pullup resistor correctly connected between I2C5_SDA and +V1P8S, providing the required pullup for the low-voltage side I2C data line.
2	2	+V1P8S	✅	10kΩ pullup resistor correctly connected between I2C5_SDA and +V1P8S, providing the required pullup for the low-voltage side I2C data line.

R267 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C5_SCL	✅	10kΩ pullup resistor correctly connected between I2C5_SCL and +V1P8S, providing the required pullup for the low-voltage side I2C clock line.
2	2	+V1P8S	✅	10kΩ pullup resistor correctly connected between I2C5_SCL and +V1P8S, providing the required pullup for the low-voltage side I2C clock line.

U40 - PCA9306DCUT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	GND pin correctly connected to ground plane.
2	VREF1	+V1P8S	✅	VREF1 pin correctly connected to +V1P8S (1.8V) low-voltage reference supply.
3	SCL1	I2C5_SCL	✅	SCL1 pin correctly connected to I2C5_SCL with 10K pullup resistor R267 to VREF1.
4	SDA1	I2C5_SDA	✅	SDA1 pin correctly connected to I2C5_SDA with 10K pullup resistor R266 to VREF1.
5	SDA2	GPIO_I2C_SDA	✅	SDA2 and SCL2 pins connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to external connector JP1. No pullup resistors visible on schematic for the high-voltage side, which may be intentional if external pullups are provided, but should be verified.
6	SCL2	GPIO_I2C_SCL	✅	SDA2 and SCL2 pins connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to external connector JP1. No pullup resistors visible on schematic for the high-voltage side, which may be intentional if external pullups are provided, but should be verified.
7	VREF2	$20N1576	✅	VREF2 and EN pins correctly shorted together on net $20N1576 and pulled up to +3VSB through 200K resistor R812, matching datasheet requirements.
8	EN	$20N1576	✅	VREF2 and EN pins correctly shorted together on net $20N1576 and pulled up to +3VSB through 200K resistor R812, matching datasheet requirements.

JP1 - HDR-26 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pins 1 and 2 both connected to GND for ground reference, providing multiple ground connections for signal integrity.
2	2	GND	✅	Pins 1 and 2 both connected to GND for ground reference, providing multiple ground connections for signal integrity.
3	3	+PS_5VSB	✅	Pin 3 connected to +PS_5VSB for 5V standby power output to external devices.
4	4	+3VSB	✅	Pin 4 connected to +3VSB for 3.3V standby power output to external devices.
5	5	SIO_SPI_CS1	✅	Pin 5 connected to SIO_SPI_CS1 for SPI chip select 1 signal, level-translated from the SOC.
6	6	UART1_TXD	✅	Pin 6 connected to UART1_TXD for UART1 transmit signal, level-translated from the SOC.
7	7	SIO_SPI_MISO	✅	Pin 7 connected to SIO_SPI_MISO for SPI MISO signal, level-translated from the SOC.
8	8	UART1_RXD	✅	Pin 8 connected to UART1_RXD for UART1 receive signal, level-translated from the SOC.
9	9	SIO_SPI_MOSI	✅	Pin 9 connected to SIO_SPI_MOSI for SPI MOSI signal, level-translated from the SOC.
10	10	UART1_CTSB	✅	Pin 10 connected to UART1_CTSB for UART1 clear to send signal, level-translated from the SOC.
11	11	SIO_SPI_CLK	✅	Pin 11 connected to SIO_SPI_CLK for SPI clock signal, level-translated from the SOC.
12	12	UART1_RTSB	✅	Pin 12 connected to UART1_RTSB for UART1 request to send signal, level-translated from the SOC.
13	13	GPIO_I2C_SCL	✅	Pin 13 connected to GPIO_I2C_SCL for I2C clock signal, level-translated from the SOC through a bidirectional I2C buffer.
14	14	I2SCLK_GPIO	✅	Pin 14 connected to I2SCLK_GPIO for I2S clock signal, level-translated from the SOC.
15	15	GPIO_I2C_SDA	✅	Pin 15 connected to GPIO_I2C_SDA for I2C data signal, level-translated from the SOC through a bidirectional I2C buffer.
16	16	I2SFRM_GPIO	✅	Pin 16 connected to I2SFRM_GPIO for I2S frame sync signal, level-translated from the SOC.
17	17	UART2_TXD	✅	Pin 17 connected to UART2_TXD for UART2 transmit signal, level-translated from the SOC.
18	18	I2SDO_GPIO	✅	Pin 18 connected to I2SDO_GPIO for I2S data output signal, level-translated from the SOC.
19	19	UART2_RXD	✅	Pin 19 connected to UART2_RXD for UART2 receive signal, level-translated from the SOC.
20	20	I2SDI_GPIO	✅	Pin 20 connected to I2SDI_GPIO for I2S data input signal, level-translated from the SOC.
21	21	GPIO_S5_0	✅	Pin 21 connected to GPIO_S5_0 for general purpose I/O signal 0, level-translated from the SOC.
22	22	PWM0	✅	Pin 22 connected to PWM0 for PWM signal 0, level-translated from the SOC.
23	23	GPIO_S5_1	✅	Pin 23 connected to GPIO_S5_1 for general purpose I/O signal 1, level-translated from the SOC.
24	24	PWM1	✅	Pin 24 connected to PWM1 for PWM signal 1, level-translated from the SOC.
25	25	GPIO_S5_2	✅	Pin 25 connected to GPIO_S5_2 for general purpose I/O signal 2, level-translated from the SOC.
26	26	I2SMCLK_GPIO	✅	Pin 26 connected to I2SMCLK_GPIO for I2S master clock signal, level-translated from the SOC.

R149 - 4.7K ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Pin 1 connects to FP_PWRBTN signal. A schematic note indicates the datasheet recommends a 10K pull-up, but this resistor is 4.7K, which is a deviation that should be verified.
2	2	+PS_5VSB	✅	Pin 2 connects to +PS_5VSB to provide pull-up voltage for the FP_PWRBTN signal.

J5 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Pin 1 connects to FP_PWRBTN, allowing a jumper to be used as an alternative method to activate the power button signal.
2	2	GND	✅	Pin 2 connects to GND, providing the low-side connection when a jumper is installed.

SW1 - 3770-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Pin 1 connects to FP_PWRBTN signal, which is pulled up to +PS_5VSB through R149 and protected by TVS diode D9. When the button is pressed, this pin shorts to GND through pin 2.
2	2	GND	✅	Pin 2 connects to GND, providing the return path when the button is pressed to pull FP_PWRBTN low.
3	GND1	GND_EARTH	✅	Pins 3 and 4 (GND1 and GND2) connect to GND_EARTH for chassis grounding and mechanical shielding of the switch.
4	GND2	GND_EARTH	✅	Pins 3 and 4 (GND1 and GND2) connect to GND_EARTH for chassis grounding and mechanical shielding of the switch.

D9 - DIODE_TVS_5V_84W_XFDFN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Pin N connects to GND, providing the ground reference for the bidirectional TVS diode protection.
P	P	FP_PWRBTN	✅	Pin P connects to FP_PWRBTN signal to provide ESD protection for the power button input.

Q105 - FDN327N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	GPIO_LED_CONTROL	✅	Drain connected to GPIO_LED_CONTROL net, which includes LED D2 anode, current limiting resistor R746 to +VCC, and filter capacitor C149. This creates an inverted-logic LED driver topology where the MOSFET shunts current away from the LED when turned on.
G	GATE	GPIO_D2_LED_CTRL	✅	Gate connected to GPIO_D2_LED_CTRL with 10K pull-down resistor R706 to GND. Correctly configured for GPIO control with defined OFF state ensuring LED is ON by default.
S	SOURCE	GND	✅	Source connected to GND. Standard configuration for N-channel MOSFET in low-side switch application.

D2 - 4560-0045 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GPIO_LED_CONTROL	✅	Anode connected to GPIO_LED_CONTROL node. Part of inverted-logic LED driver where LED is ON when MOSFET Q105 is OFF and vice versa.
C	CATHODE	GND	✅	Cathode connected to GND. Standard LED connection for this circuit topology.

R746 - 1120-0318 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	R746 functions as a current limiting resistor for LED D2, connected between +VCC (pin 1) and GPIO_LED_CONTROL (pin 2). However, it also conducts continuous current when Q105 is ON (LED OFF state), potentially operating at 85% of its power rating if +VCC is 5V, which raises reliability concerns.
2	2	GPIO_LED_CONTROL	✅	R746 functions as a current limiting resistor for LED D2, connected between +VCC (pin 1) and GPIO_LED_CONTROL (pin 2). However, it also conducts continuous current when Q105 is ON (LED OFF state), potentially operating at 85% of its power rating if +VCC is 5V, which raises reliability concerns.

R706 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_D2_LED_CTRL	✅	R706 functions correctly as a 10K pull-down resistor on the MOSFET gate, ensuring Q105 stays OFF by default (LED ON state) when the GPIO is not actively driven.
2	2	GND	✅	R706 functions correctly as a 10K pull-down resistor on the MOSFET gate, ensuring Q105 stays OFF by default (LED ON state) when the GPIO is not actively driven.

C149 - 2.2uF 10% 10V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_LED_CONTROL	✅	C149 provides filtering/decoupling on the GPIO_LED_CONTROL net (pin 1 to GPIO_LED_CONTROL, pin 2 to GND). The 2.2µF value creates an RC time constant of approximately 1ms with R746, causing slow LED turn-on response. When Q105 turns ON, C149 discharges rapidly through the MOSFET, potentially creating a brief high-current pulse that exceeds the datasheet pulsed current rating, though the extremely short duration (nanoseconds) may be within the device's safe operating area.
2	2	GND	✅	C149 provides filtering/decoupling on the GPIO_LED_CONTROL net (pin 1 to GPIO_LED_CONTROL, pin 2 to GND). The 2.2µF value creates an RC time constant of approximately 1ms with R746, causing slow LED turn-on response. When Q105 turns ON, C149 discharges rapidly through the MOSFET, potentially creating a brief high-current pulse that exceeds the datasheet pulsed current rating, though the extremely short duration (nanoseconds) may be within the device's safe operating area.

D1 - 4560-0045 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	+PS_5VSB	✅	Anode is correctly connected to +PS_5VSB supply rail. This provides power to the adaptor power indicator LED.
C	CATHODE	PWR_LEDR	✅	Cathode is correctly connected to PWR_LEDR net, which connects through current limiting resistor R148 (470Ω) to GND. This forms a proper LED indicator circuit.

U13 - NB670 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
10	BST	PS3_BST	❌	BST pin connected to bootstrap circuit with non-standard 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. This deviates from datasheet recommendation of direct capacitor connection between BST and SW pins. Pin 10 (BST) connects to net PS3_BST (from schematic) PS3_BST connects through R291 (4.7Ω) to intermediate node $22N1498 (from schematic) Node $22N1498 connects through C306 (0.1uF) to PS3VSB_PHASE (SW pins) (from schematic) This forms bootstrap circuit: BST → R291 (4.7Ω) → C306 (0.1uF) → SW (from schematic) BST is the bootstrap pin where a capacitor connected between SW and BST pins forms floating supply across high-side switch driver (from datasheet NB670, page 5) Datasheet typical application shows 100nF ceramic capacitor directly between BST and SW pins without any series resistor (from datasheet NB670, page 18) The bootstrap voltage path (BST, capacitor, SW) should be kept as short as possible (from datasheet NB670, page 16) The 4.7Ω series resistor creates RC time constant of 0.47μs with 0.1uF capacitor, which is approximately 24% of the 2μs switching period at 500kHz (reasoning) During bootstrap charging, voltage drop across 4.7Ω resistor would be approximately 0.47-0.94V for typical gate charge currents of 100-200mA, which is 9-19% of the nominal 5V bootstrap voltage (reasoning) While the series resistor might provide benefits such as EMI reduction, inrush current limiting, or damping, this configuration is not documented in the datasheet and deviates from recommended design (reasoning) The non-standard bootstrap circuit configuration could potentially affect gate drive voltage and bootstrap capacitor charging, especially during startup, transient conditions, or at the edges of the operating range (reasoning) This deviation from datasheet recommendation should be verified through testing to ensure proper bootstrap operation across all operating conditions (reasoning)
1	VIN	PS5VSB_VIN	✅	VIN pin correctly connected to PS5VSB_VIN with appropriate input capacitors for decoupling. Input voltage is at the minimum of the recommended operating range.
2	PGND	GND	✅	PGND pin correctly connected to GND plane.
3	N/C		✅	N/C pin correctly left unconnected per datasheet.
4	PG	+PS_3VSB_PG	✅	PG pin correctly connected as open-drain output with 100K pull-up resistor to PS3_VCC.
5	CLK	$22N1411	✅	CLK pin correctly connected to charge pump circuit with capacitors and diodes to generate gate drive voltage.
6	LDO	PS3_LDO	✅	LDO pin correctly connected with 10uF decoupling capacitor, exceeding the minimum 4.7uF requirement.
7	VOUT	+PS_3VSB	✅	VOUT pin correctly connected to output capacitors and load switches, providing 3.3V output sensing and power distribution.
8	SW1	PS3VSB_PHASE	✅	SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis).
9	SW2	PS3VSB_PHASE	✅	SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis).
15	SW3	PS3VSB_PHASE	✅	SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis).
16	SW4	PS3VSB_PHASE	✅	SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis).
11	VCC	PS3_VCC	✅	VCC pin correctly connected with 1.0uF decoupling capacitor meeting minimum requirement.
12	ENLDO		✅	ENLDO pin correctly left open to enable the LDO per datasheet recommendation.
13	EN	PS3_EN	✅	EN pin connected with 499K pull-up resistor to input voltage. Recommended 10nF noise filtering capacitor C85 is marked DNI.
14	AGND	GND	✅	AGND pin correctly connected to GND plane.

L3 - IND_2.2uH_20%_10A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3VSB_PHASE	✅	Inductor pin 1 correctly connected to switching node PS3VSB_PHASE from U13.
2	2	+PS_3VSB	✅	Inductor pin 2 correctly connected to output voltage +PS_3VSB (3.3V).

U35 - NCT3012S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DeepS5_Sel	S5_SEL	✅	DeepS5_Sel pin is connected to S5_SEL net with a 2.2K pull-up to +PS_5VSB and can be pulled low by Q10 (N-channel FET) when 5VSB_CTRL is high. This configures the deep S5 (EuP) mode selection.
2	VSB	+PS_5VSB	✅	VSB pin is connected to +PS_5VSB, providing 5V standby power to the controller. Multiple decoupling capacitors are present on this rail.
3	PS_IN#	PB_RES	✅	PS_IN# pin is connected to PB_RES net, which connects to the front panel power button (FP_PWRBTN) through a 33 ohm series resistor R308. This is the power button input.
4	SLP_S5#	SLP_S4_L	✅	SLP_S5# pin is connected to SLP_S4_L net. There is a naming discrepancy (S5 vs S4), but this could be intentional if the controller uses the S4 sleep signal to control S5 power state transitions.
5	SDA	DDR_SMB_DATA	✅	SDA pin is connected to DDR_SMB_DATA net, providing I2C/SMBus data communication, likely for DDR memory SPD reading or presence detection.
6	SCLK	DDR_SMB_CLK	✅	SCLK pin is connected to DDR_SMB_CLK net, providing I2C/SMBus clock communication, likely for DDR memory SPD reading or presence detection.
7	PS_OUT#	PS_OUT_L	✅	PS_OUT# pin is connected to PS_OUT_L net. R289 (1K pull-up to +PS_3VSB) is marked DNI, so the pin has no pull-up resistor. This suggests the pin is actively driven or doesn't require a pull-up.
8	SYS5VSB_OFF	5VSB_CTRL	✅	SYS5VSB_OFF pin is connected to 5VSB_CTRL net, which controls Q10 to pull S5_SEL low (enabling EuP mode) when high. R288 (1K) provides a pull-up to +PS_5VSB.
9	GND	GND	✅	GND pin is connected to the ground net, providing the ground reference for the controller.

Q104 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+3VSB	✅	Source pins connected to +3VSB output rail. These pins carry the switched output current to the 3VSB rail.
2	S2	+3VSB	✅	Source pins connected to +3VSB output rail. These pins carry the switched output current to the 3VSB rail.
3	S3	+3VSB	✅	Source pins connected to +3VSB output rail. These pins carry the switched output current to the 3VSB rail.
4	G	+3VSB_EN	✅	Gate pin connected to +3VSB_EN control signal. Gate is driven from +10V through R322 (100K) or pulled to GND by Q11.
5	D1	+PS_3VSB	✅	Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply.
6	D2	+PS_3VSB	✅	Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply.
7	D3	+PS_3VSB	✅	Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply.
8	D4	+PS_3VSB	✅	Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply.

Q103 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+5VSB	✅	Source pins connected to +5VSB output rail. These pins carry the switched output current to the 5VSB rail.
2	S2	+5VSB	✅	Source pins connected to +5VSB output rail. These pins carry the switched output current to the 5VSB rail.
3	S3	+5VSB	✅	Source pins connected to +5VSB output rail. These pins carry the switched output current to the 5VSB rail.
4	G	5VSB_LSENB	✅	Gate pin connected to 5VSB_LSENB control signal. Gate is driven from +10V through R324 (100K) or pulled to GND by Q14.
5	D1	+PS_5VSB	✅	Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply.
6	D2	+PS_5VSB	✅	Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply.
7	D3	+PS_5VSB	✅	Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply.
8	D4	+PS_5VSB	✅	Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply.

U36 - IRF9321 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	$22N1502	✅	Source pins connected to net $22N1502, which connects through ferrite beads L13 and L12 to DC_IN_1 (5V input from power jack). These pins carry input current from the DC jack.
2	S2	$22N1502	✅	Source pins connected to net $22N1502, which connects through ferrite beads L13 and L12 to DC_IN_1 (5V input from power jack). These pins carry input current from the DC jack.
3	S3	$22N1502	✅	Source pins connected to net $22N1502, which connects through ferrite beads L13 and L12 to DC_IN_1 (5V input from power jack). These pins carry input current from the DC jack.
4	G	DC_GATE_ENB	✅	Gate pin connected to DC_GATE_ENB control signal. Gate is normally pulled to GND by R309 (100K) to turn on the P-channel device, or pulled toward source by Q106 during overvoltage conditions to turn off the device.
5	D1	+PS_5VSB	✅	Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits.
6	D2	+PS_5VSB	✅	Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits.
7	D3	+PS_5VSB	✅	Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits.
8	D4	+PS_5VSB	✅	Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits.

Q6 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB	✅	Drain pin correctly connected to +3VSB supply rail. This is the input of the high-side switch that provides power to the +VCC3 rail when enabled.
G	GATE	SYS_EN	✅	Gate pin correctly connected to SYS_EN control signal. The gate is pulled up to +10V through R340 (100K) and can be pulled down by Q12 or Q7, providing adequate gate drive voltage.
S	SOURCE	+VCC3	✅	Source pin correctly connected to +VCC3 output rail. This is the output of the high-side switch that supplies power to downstream circuits when Q6 is enabled.

Q13 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+5VSB	✅	Drain pin correctly connected to +5VSB supply rail. This is the input of the high-side switch that provides power to the +VCC rail when enabled.
G	GATE	SYS_EN	✅	Gate pin correctly connected to SYS_EN control signal. The gate is pulled up to +10V through R340 (100K) and can be pulled down by Q12 or Q7, providing adequate gate drive voltage.
S	SOURCE	+VCC	✅	Source pin correctly connected to +VCC output rail. This is the output of the high-side switch that supplies power to downstream circuits when Q13 is enabled.

Q2 - BAV99-7-F-S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	+PS_5VSB	✅	Anode 1 connected to +PS_5VSB for OR-ing the 5V standby supply. Connection is correct.
2	A2	$22N1417	✅	Anode 2 connected to floating node $22N1417. This node is not connected to any voltage source, so this diode will not conduct in normal operation. Purpose is unclear but may be intentional for future expansion.
3	C	$22N1419	✅	Common cathode connected to $22N1419, which feeds into a capacitive voltage divider. Connection is correct for OR-ing output.

Q9 - BAV99-7-F-S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	$22N1417	✅	Anode 1 connected to floating node $22N1417. This node is not connected to any voltage source, so this diode will not conduct in normal operation. Purpose is unclear but may be intentional for future expansion.
2	A2	+10V	✅	Anode 2 connected to +10V boost supply for OR-ing. Connection is correct.
3	C	$22N1467	✅	Common cathode connected to $22N1467, which feeds into a capacitive voltage divider. Connection is correct for OR-ing output.

D6 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB_PG	✅	Anode connected to +PS_3VSB_PG power good signal. Forms one input of an OR gate for the PMC_RSMRST reset signal.
2	2	+3VSB_EN	✅	Anode connected to +3VSB_EN enable signal. Forms the second input of an OR gate for the PMC_RSMRST reset signal.
3	3	PMC_RSMRST	✅	Common cathode connected to PMC_RSMRST reset signal output. Outputs the OR function of the two anode inputs.

Q10 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	S5_ENBL	✅	Drain pin correctly connected to S5_ENBL net, pulling down the signal when EuP is enabled.
G	GATE	5VSB_CTRL	✅	Gate pin correctly connected to 5VSB_CTRL signal from power controller U35 for EuP control.
S	SOURCE	GND	✅	Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration.

Q11 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB_EN	✅	Drain pin correctly connected to +3VSB_EN net, driving the gate of power FET Q104 through pull-up R322.
G	GATE	+3VSB_EN_L	✅	Gate pin correctly connected to +3VSB_EN_L signal from Q4 collector for inverted control.
S	SOURCE	GND	✅	Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration.

Q14 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	5VSB_LSENB	✅	Drain pin correctly connected to 5VSB_LSENB net, driving the gate of power FET Q103 through pull-up R324.
G	GATE	5VSB_GATE	✅	Gate pin correctly connected to 5VSB_GATE signal through R323 for controlled gate drive.
S	SOURCE	GND	✅	Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration.

Q12 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN	✅	Drain pin correctly connected to SYS_EN net with 100K pull-up to +10V, driving gates of power MOSFETs Q13 and Q6.
G	GATE	SYS_EN_GATE	✅	Gate pin correctly connected to SYS_EN_GATE signal from Q7 drain for level-shifted control.
S	SOURCE	GND	✅	Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration.

Q4 - XSTR_NPN_40V_200mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
B	BASE	S5_ENBL	✅	Base pin correctly connected to S5_ENBL control signal through a pull-up resistor network and Q10 FET switch.
C	COLLECTOR	+3VSB_EN_L	✅	Collector pin correctly connected to +3VSB_EN_L net with pull-up resistor R321 to +PS_5VSB, forming an inverter stage.
E	EMITTER	GND	✅	Emitter pin correctly connected to GND as required for NPN transistor common-emitter configuration.

Q7 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN_GATE	✅	Drain pin correctly connected to SYS_EN_GATE net with 33K pull-up to +10V, driving the gate of Q12.
G	GATE	SLP_S3_L	✅	Gate pin correctly connected to SLP_S3_L control signal for sleep state control.
S	SOURCE	GND	✅	Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration.

Q106 - BSS84 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	D	DC_GATE_ENB	✅	Drain pin drives the gate of U36 (P-channel MOSFET) to turn it off when overvoltage is detected. This connection is correct for the overvoltage protection function.
G	G	$22N2300	✅	Gate pin is controlled by a voltage divider formed by R855 (499Ω to source) and D13 (4.3V Zener to ground), creating an overvoltage threshold. This connection is correct for the protection circuit function.
S	S	$22N1502	✅	Source pin is connected to the input voltage through ferrite beads, providing the reference voltage for the protection circuit. This connection is correct.

D13 - 4620-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Anode pin is connected to ground, which is correct for a Zener diode used as a voltage clamp to set the overvoltage protection threshold.
C	CATHODE	$22N2300	✅	Cathode pin is connected to the gate of Q106, clamping it to 4.3V above ground to set the overvoltage protection threshold. This connection is correct.

J9 - JACK_PWR_2.1MM_RAPC712 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DC_IN_1	✅	Center pin connected to DC_IN_1 net, serving as the positive DC power input. The connection includes appropriate filtering capacitors and ferrite beads for EMI suppression.
2	2	GND	✅	Sleeve pin correctly connected to GND net, serving as the ground/negative terminal of the power jack.
3	3	GND	✅	Switch contact pin connected to GND net. This is a valid design choice when plug detection functionality is not required.

U25 - NCP81109GMNTXG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT is connected to VR_HOT_L net. This is a thermal alert output that signals when the controller detects an over-temperature condition.
2	SDIO	$23N2429	✅	SDIO is connected through R80 (16.9Ω) to SVID_DATA-R. This is the SVID data I/O pin with appropriate series resistance for signal integrity.
3	ALERT	$23N2431	✅	ALERT is connected through R62 (0Ω jumper) to SVID_ALERT-R. This is the SVID alert output.
4	SCLK	$23N2430	✅	SCLK is connected through R81 (20Ω) to SVID_CLK-R. This is the SVID clock pin with appropriate series resistance.
5	GND	AGND-VCORE	✅	GND is connected to AGND-VCORE, which connects through R37 (0Ω) to the main GND plane. This provides analog ground reference.
6	VR_RDY	$23N3753	✅	VR_RDY is connected through R79 (0Ω) to VCORE_PG. This is the power good/ready output indicating the regulator output is within regulation.
7	VIN1	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
11	VIN2	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
12	VIN3	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
13	VIN4	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
14	VIN5	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
15	VIN6	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
16	VIN7	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
17	VIN8	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
50	VIN_PAD	+5VSB_SW	✅	VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current.
8	BST	$23N3711	✅	BST is connected to the bootstrap circuit through R154 (2.2Ω) and C50 (0.22µF) to SW1. This provides bootstrap voltage for the high-side gate driver.
9	GH		✅	GH (high-side gate driver output) is not connected in this design. This appears to be intentional as the NCP81109 is an 8-phase capable controller being used in a 7-phase configuration, with the 8th phase (GH/GL) left unpopulated.
10	SW1	$23N3731	✅	SW1 is connected to the bootstrap circuit and represents one of the switch node outputs. It connects through C50 to the bootstrap circuit.
18	SW2	VCORE-SW	✅	SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output.
25	SW3	VCORE-SW	✅	SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output.
26	SW4	VCORE-SW	✅	SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output.
27	SW5	VCORE-SW	✅	SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output.
28	SW6	VCORE-SW	✅	SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output.
29	SW7	VCORE-SW	✅	SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output.
51	SW_PAD	VCORE-SW	✅	SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output.
19	PGND1	GND	✅	PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane.
20	PGND2	GND	✅	PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane.
21	PGND3	GND	✅	PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane.
22	PGND4	GND	✅	PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane.
23	PGND5	GND	✅	PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane.
24	PGND6	GND	✅	PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane.
30	GL		✅	GL (low-side gate driver output) is not connected in this design. This appears to be intentional as the 8th phase capability of the controller is not used in this 7-phase configuration.
31	VBOOT	$23N3477	✅	VBOOT is connected through R70 (88.7kΩ) to AGND-VCORE. This sets the boot voltage reference level.
32	GND1	AGND-VCORE	✅	GND1 and GND_PAD are connected to AGND-VCORE. These analog ground connections are properly tied to the analog ground plane.
49	GND_PAD	AGND-VCORE	✅	GND1 and GND_PAD are connected to AGND-VCORE. These analog ground connections are properly tied to the analog ground plane.
33	VCCP	$23N3625	✅	VCCP is connected through R845 (1Ω) to +5VSB with C48 (4.7µF) decoupling. This is the charge pump output that provides gate drive supply.
34	TSENSE	$23N3665	✅	TSENSE is connected to a temperature sensing network with TH2 (100kΩ thermistor) and R131 (14kΩ) to ground, with C46 (0.1µF) filtering. This provides temperature monitoring.
35	IMAX	$23N3681	✅	IMAX is connected through R105 (44.2kΩ) to AGND-VCORE. This sets the maximum current limit. Text note indicates target of 14A.
36	IOUT	$23N3683	✅	IOUT is connected through R146 (16.5kΩ) to AGND-VCORE with C47 (470pF) filtering. This provides output current monitoring.
37	ILIM	VCORE-ILIM	✅	ILIM is connected through R95 (15kΩ) to VCORE-CSCOMP. This sets the current limit threshold in conjunction with the current sense compensation network.
38	CSCOMP	VCORE-CSCOMP	✅	CSCOMP is the current sense compensation node with complex network including C39, C40, R96, R95, and TH1. This implements current loop compensation with thermal compensation.
39	CSSUM	VCORE-CSSUM	✅	CSSUM is the current sense sum node connected to DCR current sensing through R107 and R106. This sums the current sense signals from all phases.
40	CSREF	VCORE-CSREF	✅	CSREF is connected through R108 (10Ω) to the output with C45 (1000pF) decoupling. This provides the current sense reference voltage.
41	FREQ	$23N2930	✅	FREQ is connected through R93 (18.7kΩ) to AGND-VCORE. This sets the switching frequency. Text note indicates target of 650kHz.
42	COMP	VCORE-COMP	✅	COMP is the voltage loop compensation node with Type III compensation network including C35, C37, R88, and connections to FB. This implements voltage loop stability.
43	FB	VCORE-FB	✅	FB is the feedback input connected to the compensation network and differential amplifier. This senses the output voltage for regulation.
44	DIFFOUT	VCORE-DIFFOUT	✅	DIFFOUT is the differential amplifier output connected through R89 to FB and through R90, C36 to ground. This implements the differential sensing amplifier output.
45	VSN	VR-VCORE-VSN	✅	VSN is the negative remote sense input connected through R65 (10Ω) from the ground sense point. This implements Kelvin sensing for accurate voltage regulation.
46	VSP	VR-VCORE-VSP	✅	VSP is the positive remote sense input connected through R92 (100Ω) to +VCORE and through R63 (0Ω) to VCC_SENSE. This implements Kelvin sensing for accurate voltage regulation.
47	VCC	$23N3860	✅	VCC is connected through R166 (2.2Ω) to +5VSB with C24 (1µF) decoupling. This provides the internal supply voltage for the controller.
48	EN	$23N5607	✅	EN is connected through R849 (0Ω) to +VCC with R851 (10kΩ) pulldown and C433 (0.1µF) filtering. This enables the regulator when VCC is present.

L8 - 3120-0183 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 connects to the +5VSB input supply. This is the correct connection for an input filter inductor.
2	2	+5VSB_SW	✅	Pin 2 connects to the +5VSB_SW filtered input rail that feeds the buck converter U25. This is the correct connection for an input filter inductor.

L18 - 3120-0266 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Pin 1 connects to the VCORE-SW switching node from the multiphase buck controller U25. This is the correct connection for the inductor input in a buck converter topology.
2	2	+VCORE	✅	Pin 2 connects to the +VCORE output rail. This is the correct connection for the inductor output in a buck converter topology.

C37 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP compensation pin of U25.
2	2	$23N2824	✅	Connected to intermediate node $23N2824, forming a zero with R88 in the compensation network.

C36 - 2220-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB feedback node.
2	2	$23N2818	✅	Connected to intermediate node $23N2818, forming an RC filter with R90 for the DIFFOUT signal.

C35 - 2220-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP compensation pin of U25.
2	2	VCORE-FB	✅	Connected to VCORE-FB feedback node, forming the high-frequency pole in the Type III compensation network.

R88 - 1120-0032 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2824	✅	Connected to intermediate node $23N2824 in the voltage loop compensation network, forming a zero with C37.
2	2	VCORE-FB	✅	Connected to VCORE-FB feedback node, completing the compensation network connection to the FB pin of U25.

R90 - 1121-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2818	✅	Connected to intermediate node $23N2818, forming an RC filter with C36.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT, providing filtered connection to the differential output.

R89 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB feedback node.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT, coupling the feedback signal to the differential output pin of U25.

R107 - 1130-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSSUM	✅	Pin 1 connects to VCORE-CSSUM (U25 pin 39), which is the current sense sum input of the multiphase controller. This is part of the current sensing network.
2	2	$23N3209	✅	Pin 2 connects to $23N3209, which connects through SP3 (PCB bridge short) to VCORE-SW (the switching node). This creates a 100K connection from the switching node to CSSUM. While this configuration is unusual for standard DCR current sensing, it may be intentional for the NCP81109GMNTXG controller's specific sensing method.

R108 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSREF	✅	Pin 1 connects to VCORE-CSREF (U25 pin 40), which is the current sense reference pin of the controller. This is part of the current sensing reference network.
2	2	$23N3208	✅	Pin 2 connects to $23N3208, which connects through SP4 (PCB bridge short) to +VCORE (the output voltage). This creates a 10 ohm connection from CSREF to the output voltage, which may be for load line regulation or adaptive voltage positioning (AVP).

SP3 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	PCB bridge short connecting VCORE-SW switching node (pin 1) to net $23N3209 (pin 2), which feeds through R107 (100K) to CSSUM. This configuration is unusual for typical DCR current sensing but appears intentional for the NCP81109GMNTXG controller's sensing method.
2	2	$23N3209	✅	PCB bridge short connecting VCORE-SW switching node (pin 1) to net $23N3209 (pin 2), which feeds through R107 (100K) to CSSUM. This configuration is unusual for typical DCR current sensing but appears intentional for the NCP81109GMNTXG controller's sensing method.

C46 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	Connected to $23N3665 which connects to U25 pin 34 (TSENSE). This provides filtering for the temperature sensing input.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE (analog ground) for proper signal integrity. This provides a clean ground reference for the analog sensing circuit.

R78 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	Connected to $23N3665 which connects to U25 pin 34 (TSENSE). This is the controller side of the temperature sensing circuit.
2	2	$23N3662	✅	Connected to $23N3662 which connects to the TH2/R131 temperature sensing divider. This is the thermistor network side.

R131 - 1120-0055 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to $23N3662 which connects to TH2 and through R78 to the TSENSE pin. This forms the upper part of the temperature sensing divider.
2	2	GND	✅	Connected to GND to complete the temperature sensing divider. This provides the ground reference for the divider.

TH1 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP for current sensing compensation. This pin connects to the current sense compensation network of the DC-DC controller.
2	2	$23N3115	✅	Connected to intermediate node $23N3115 in the current compensation network. This pin connects through R96 to form part of the temperature-dependent divider.

TH2 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to intermediate node $23N3662 which feeds the TSENSE pin through R78. This pin is part of the temperature sensing divider network.
2	2	GND	✅	Connected to GND to complete the temperature sensing divider network. This provides the reference for the TSENSE voltage divider.

R92 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output. Provides local positive voltage sensing path to the regulator.
2	2	VR-VCORE-VSP	✅	Connected to VR-VCORE-VSP which goes to U25 VSP input. Part of the positive voltage sensing path.

R65 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2860	✅	Connected to intermediate node $23N2860. Part of the negative sense path with 10Ω series resistance.
2	2	VR-VCORE-VSN	✅	Connected to VR-VCORE-VSN which goes to U25 VSN input. Completes the negative sense path.

R63 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_SENSE	✅	Connected to VCC_SENSE for remote positive voltage sensing. 0Ω jumper allows direct connection when populated.
2	2	VR-VCORE-VSP	✅	Connected to VR-VCORE-VSP. Shares connection with R92 pin 2 for parallel sensing paths.

C38 - 2221-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2860	✅	Filtering capacitor on negative sense path. Marked DNI, possibly related to DAC feed forward functionality.
2	2	VR-VCORE-VSN	✅	Filtering capacitor on negative sense path. Marked DNI, possibly related to DAC feed forward functionality.

R64 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VSS_SENSE	✅	Connected to VSS_SENSE for remote negative voltage sensing. 0Ω jumper allows direct connection when populated.
2	2	$23N2860	✅	Connected to intermediate node $23N2860. Shares connection with R91 pin 2 for parallel sensing paths.

C34 - 2221-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR-VCORE-VSP	✅	Differential filtering capacitor between VSP and VSN sense inputs. Marked DNI, indicating optional filtering.
2	2	VR-VCORE-VSN	✅	Differential filtering capacitor between VSP and VSN sense inputs. Marked DNI, indicating optional filtering.

R91 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Provides local negative voltage sensing path to the regulator.
2	2	$23N2860	✅	Connected to intermediate node $23N2860. Part of the negative sensing network.

R81 - 1120-0099 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and controller SCLK pin. Provides signal integrity and protection.
2	2	$23N2430	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and controller SCLK pin. Provides signal integrity and protection.

R62 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Zero-ohm jumper on SVID alert line between external SVID_ALERT-R signal and controller ALERT pin. Provides routing flexibility.
2	2	$23N2431	✅	Zero-ohm jumper on SVID alert line between external SVID_ALERT-R signal and controller ALERT pin. Provides routing flexibility.

R86 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect SVID_ALERT-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system.
2	2	SVID_ALERT-R	✅	DNI pull-up resistor that would connect SVID_ALERT-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system.

R80 - 1120-0329 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Series resistor on SVID data line between external SVID_DATA-R signal and controller SDIO pin. Provides signal integrity and protection.
2	2	$23N2429	✅	Series resistor on SVID data line between external SVID_DATA-R signal and controller SDIO pin. Provides signal integrity and protection.

R87 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect SVID_CLK-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system.
2	2	SVID_CLK-R	✅	DNI pull-up resistor that would connect SVID_CLK-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system.

R85 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect SVID_DATA-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system.
2	2	SVID_DATA-R	✅	DNI pull-up resistor that would connect SVID_DATA-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system.

C433 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N5607	✅	Connected to EN pin of U25 through net $23N5607 for filtering and decoupling.
2	2	GND	✅	Connected to GND to provide filtering reference and complete bypass path.

R849 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Connected to +VCC to provide enable signal to U25 EN pin through 0-ohm resistor.
2	2	$23N5607	✅	Connected to EN pin of U25 voltage regulator controller through net $23N5607.

R851 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N5607	✅	Connected to EN pin of U25 through net $23N5607 to provide pull-down.
2	2	GND	✅	Connected to GND to complete pull-down path for EN pin.

R79 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	0-ohm jumper connecting VR_RDY output from U25 pin 6 to VCORE_PG net, allowing the voltage regulator ready signal to be used as the system power good signal.
2	2	$23N3753	✅	0-ohm jumper connecting VR_RDY output from U25 pin 6 to VCORE_PG net, allowing the voltage regulator ready signal to be used as the system power good signal.

R167 - 1120-0052 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	1.91K pull-up resistor connecting VCORE_PG to +VCC3 supply, providing the necessary pull-up for the active-high power good signal.
2	2	VCORE_PG	✅	1.91K pull-up resistor connecting VCORE_PG to +VCC3 supply, providing the necessary pull-up for the active-high power good signal.

R94 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_GFX_PG	✅	1K pull-up resistor connecting VCORE_GFX_PG to +VCC3 supply, providing the necessary pull-up for the combined power good signal output from the diode AND gate.
2	2	+VCC3	✅	1K pull-up resistor connecting VCORE_GFX_PG to +VCC3 supply, providing the necessary pull-up for the combined power good signal output from the diode AND gate.

C25 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	0.1uF decoupling capacitor on VCORE_PG signal to filter noise and provide local charge storage.
2	2	GND	✅	0.1uF decoupling capacitor on VCORE_PG signal to filter noise and provide local charge storage.

C65 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0.1uF decoupling capacitor on VCORE_GFX_PG signal to filter noise and provide local charge storage.
2	2	VCORE_GFX_PG	✅	0.1uF decoupling capacitor on VCORE_GFX_PG signal to filter noise and provide local charge storage.

D4 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Connected to VCORE_PG power good signal. This pin should be an anode for the OR-gate configuration to function correctly with active-high power good signals.
2	2	VGFX_PG	✅	Connected to VGFX_PG power good signal. This pin should be an anode for the OR-gate configuration.
3	3	VCORE_GFX_PG	✅	Connected to VCORE_GFX_PG combined power good output. This pin is the common cathode in standard BAT54A configuration.

R154 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3711	✅	Connected to U25 pin 8 (BST) as part of the bootstrap circuit for the high-side gate driver.
2	2	$23N3733	✅	Connected to C50 pin 1, forming the intermediate node in the bootstrap RC network between BST and SW1.

C50 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3733	✅	Connected to R154 pin 2, forming one side of the bootstrap capacitor in the gate driver circuit.
2	2	$23N3731	✅	Connected to U25 pin 10 (SW1), providing the bootstrap capacitor return path to the switching node.

R70 - 1120-0289 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3477	✅	Connected to U25 pin 31 (VBOOT) to set the boot voltage configuration to 1.1V, which sets the device address to 0x0.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE (analog ground) to provide the ground reference for the VBOOT voltage divider.

R166 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail. This provides the input voltage for the series resistor feeding the VCC pin of U25.
2	2	$23N3860	✅	Connected to net $23N3860 which feeds U25 pin 47 (VCC) and decoupling capacitor C24. This provides power to the controller IC with series resistance for inrush limiting.

C24 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3860	✅	Connected to net $23N3860 which is the VCC supply for U25 through series resistor R166. This is the positive terminal of the VCC decoupling capacitor.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE (analog ground). This provides the ground reference for the VCC decoupling capacitor, correctly using analog ground for the analog supply pin.

R845 - 1130-0193 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail. This provides the input voltage for the series resistor feeding the VCCP pin of U25.
2	2	$23N3625	✅	Connected to net $23N3625 which feeds U25 pin 33 (VCCP) and decoupling capacitor C48. This provides power to the controller IC's power stage circuitry with series resistance for inrush limiting.

C48 - 2232-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3625	✅	Connected to net $23N3625 which is the VCCP supply for U25 through series resistor R845. This is the positive terminal of the VCCP decoupling capacitor.
2	2	GND	✅	Connected to GND (power ground). This provides the ground reference for the VCCP decoupling capacitor, using power ground which is appropriate if VCCP powers gate drivers or power stage circuitry.

R93 - 1120-0351 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2930	✅	Pin 1 connects to the FREQ pin (pin 41) of U25 to set the switching frequency. This connection is correct.
2	2	AGND-VCORE	✅	Pin 2 connects to AGND-VCORE (analog ground) to complete the frequency setting resistor. This connection is correct.

R168 - 1141-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Connected to VCORE-SW switching node. Forms part of an RC snubber network with C52 to dampen switching node ringing.
2	2	$23N3990	✅	Connected to intermediate node $23N3990 which connects to C52 pin 1. Completes the RC snubber network to ground.

C52 - 2240-0005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3990	✅	Connected to intermediate node $23N3990 from R168. Forms part of RC snubber network.
2	2	GND	✅	Connected to GND. Completes the RC snubber path from switching node to ground.

SP4 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output rail. Provides output voltage reference for load line regulation circuit.
2	2	$23N3208	✅	Connected to $23N3208 which feeds through R108 (10Ω) to CSREF pin of U25. Implements load line regulation by referencing CSREF to output voltage.

R37 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0-ohm jumper connecting main ground (GND) to analog ground (AGND-VCORE), providing single-point ground connection between power and analog ground planes.
2	2	AGND-VCORE	✅	0-ohm jumper connecting main ground (GND) to analog ground (AGND-VCORE), providing single-point ground connection between power and analog ground planes.

C53 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3610	✅	1.0uF decoupling capacitor for U26 VCC supply between $24N3610 and AGND-VGFX.
2	2	AGND-VGFX	✅	1.0uF decoupling capacitor for U26 VCC supply between $24N3610 and AGND-VGFX.

C186 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3596	✅	0.22uF bootstrap capacitor between BST pin and SW1 switching node for high-side gate driver.
2	2	$24N3595	✅	0.22uF bootstrap capacitor between BST pin and SW1 switching node for high-side gate driver.

R66 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0 ohm jumper connecting analog ground AGND-VGFX to main ground GND for star ground configuration.
2	2	AGND-VGFX	✅	0 ohm jumper connecting analog ground AGND-VGFX to main ground GND for star ground configuration.

C185 - 2232-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3578	✅	4.7uF decoupling capacitor for U26 VCCP supply between $24N3578 and GND.
2	2	GND	✅	4.7uF decoupling capacitor for U26 VCCP supply between $24N3578 and GND.

R203 - 1120-0351 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3542	✅	18.7K resistor setting switching frequency to 650kHz per text note.
2	2	AGND-VGFX	✅	18.7K resistor setting switching frequency to 650kHz per text note.

R229 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	2.20 ohm resistor providing current limiting and filtering between +5VSB and VCC supply pin of U26.
2	2	$24N3610	✅	2.20 ohm resistor providing current limiting and filtering between +5VSB and VCC supply pin of U26.

R846 - 1130-0193 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	1.00 ohm resistor providing current limiting and filtering between +5VSB and VCCP supply pin of U26.
2	2	$24N3578	✅	1.00 ohm resistor providing current limiting and filtering between +5VSB and VCCP supply pin of U26.

R170 - 1120-0009 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3564	✅	100K resistor pulling down VBOOT pin for address configuration. Text note indicates VBOOT should be 1.1V for ADDR=0x1.
2	2	AGND-VGFX	✅	100K resistor pulling down VBOOT pin for address configuration. Text note indicates VBOOT should be 1.1V for ADDR=0x1.

U26 - NCP81109GMNTXG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT pin connected to VR_HOT_L signal for thermal warning output.
2	SDIO	$24N3490	✅	SDIO pin connected to SVID data line through 16.9 ohm series resistor with 69.8 ohm pull-up to +V1P0S.
3	ALERT	$24N3492	✅	ALERT pin connected to SVID alert line through 0 ohm jumper, but pull-up resistor R196 is DNI.
4	SCLK	$24N3491	✅	SCLK pin connected to SVID clock line through 20 ohm series resistor with 69.8 ohm pull-up to +V1P0S.
5	GND	AGND-VGFX	✅	GND pin connected to AGND-VGFX analog ground, which connects to main GND through 0 ohm jumper R66.
6	VR_RDY	$24N3598	✅	VR_RDY pin connected to power good signal VGFX_PG through 0 ohm jumper, with 1.91K pull-up to +VCC3.
7	VIN1	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
11	VIN2	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
12	VIN3	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
13	VIN4	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
14	VIN5	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
15	VIN6	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
16	VIN7	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
17	VIN8	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors.
8	BST	$24N3593	✅	BST pin connected to bootstrap circuit with 2.20 ohm resistor and 0.22uF capacitor to SW1 node.
9	GH		✅	GH pin has no net connection shown in schematic, likely connects to external high-side MOSFET gate.
10	SW1	$24N3595	✅	SW1 pin connected to bootstrap capacitor return and switching node.
18	SW2	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation.
25	SW3	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation.
26	SW4	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation.
27	SW5	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation.
28	SW6	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation.
29	SW7	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation.
19	PGND1	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
20	PGND2	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
21	PGND3	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
22	PGND4	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
23	PGND5	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
24	PGND6	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
30	GL		✅	GL pin has no net connection shown in schematic, likely connects to external low-side MOSFET gate.
31	VBOOT	$24N3564	✅	VBOOT pin pulled down through 100K resistor to AGND-VGFX. Text note indicates VBOOT should be 1.1V for ADDR=0x1, but no voltage source is visible.
32	GND1	AGND-VGFX	✅	GND1 pin connected to AGND-VGFX analog ground.
33	VCCP	$24N3578	✅	VCCP pin supplied from +5VSB through 1.00 ohm resistor with 4.7uF decoupling capacitor.
34	TSENSE	$24N3584	✅	TSENSE pin connected to thermistor temperature sensing network with 100K@25C thermistor and 14K resistor to ground.
35	IMAX	$24N3588	✅	IMAX pin set to 14A maximum current limit by 44.2K resistor to ground per text note.
36	IOUT	$24N3589	✅	IOUT pin configured for output current monitoring with 16.5K resistor and 470pF filter capacitor.
37	ILIM	VGFX-ILIM	✅	ILIM pin connected to current limit compensation network through 15K resistor.
38	CSCOMP	VGFX-CSCOMP	✅	CSCOMP pin configured with current sense compensation network including thermistor for temperature-dependent current limiting.
39	CSSUM	VGFX-CSSUM	✅	CSSUM pin connected to summed current sense signal through resistor network.
40	CSREF	VGFX-CSREF	✅	CSREF pin connected to current sense reference with 10 ohm resistor and 1000pF filter capacitor.
41	FREQ	$24N3542	✅	FREQ pin set to 650kHz switching frequency by 18.7K resistor per text note.
42	COMP	VGFX-COMP	✅	COMP pin configured with voltage loop compensation network using 47pF and 2200pF capacitors.
43	FB	VGFX-FB	✅	FB pin connected to feedback voltage divider with 3.01K and 1K resistors, plus compensation network.
44	DIFFOUT	VGFX-DIFFOUT	✅	DIFFOUT pin connected to differential amplifier output with 1K and 47 ohm resistors for remote sensing.
45	VSN	VR-VGFX-VSN	✅	VSN pin connected to negative remote sense input through 10 ohm resistor, sensing ground reference.
46	VSP	VR-VGFX-VSP	✅	VSP pin connected to positive remote sense input through 100 ohm resistor, sensing output voltage at remote location.
47	VCC	$24N3610	✅	VCC pin supplied from +5VSB through 2.20 ohm resistor with 1.0uF decoupling capacitor.
48	EN	$24N6011	✅	EN pin connected to +VCC through 0 ohm jumper with 10K pull-down, enabling the regulator when VCC is present.
49	GND_PAD	AGND-VGFX	✅	GND_PAD exposed pad connected to AGND-VGFX analog ground.
50	VIN_PAD	+5VSB_SW	✅	VIN_PAD exposed pad connected to +5VSB_SW input supply.
51	SW_PAD	VGFX-SW	✅	SW_PAD exposed pad connected to VGFX-SW switching node.

R228 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3593	✅	2.20 ohm resistor in bootstrap circuit limiting charging current of bootstrap capacitor C186.
2	2	$24N3596	✅	2.20 ohm resistor in bootstrap circuit limiting charging current of bootstrap capacitor C186.

R193 - 1120-0329 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Series resistor (16.9Ω) between system SVID data line (SVID_DATA-R) and voltage regulator controller SDIO pin. Provides signal integrity and current limiting for the SVID interface.
2	2	$24N3490	✅	Series resistor (16.9Ω) between system SVID data line (SVID_DATA-R) and voltage regulator controller SDIO pin. Provides signal integrity and current limiting for the SVID interface.

R195 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor (69.8Ω) on SVID data line from +V1P0S to SVID_DATA-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage.
2	2	SVID_DATA-R	✅	Pull-up resistor (69.8Ω) on SVID data line from +V1P0S to SVID_DATA-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage.

R67 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Zero-ohm jumper between system SVID alert line (SVID_ALERT-R) and voltage regulator controller ALERT pin. The 0Ω value suggests ALERT is a push-pull output that doesn't require series resistance.
2	2	$24N3492	✅	Zero-ohm jumper between system SVID alert line (SVID_ALERT-R) and voltage regulator controller ALERT pin. The 0Ω value suggests ALERT is a push-pull output that doesn't require series resistance.

C432 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Positive terminal of decoupling capacitor connected to +V1P0S power rail.
2	2	GND	✅	Negative terminal of decoupling capacitor connected to ground.

R197 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor (69.8Ω) on SVID clock line from +V1P0S to SVID_CLK-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage.
2	2	SVID_CLK-R	✅	Pull-up resistor (69.8Ω) on SVID clock line from +V1P0S to SVID_CLK-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage.

R194 - 1120-0099 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Series resistor (20.0Ω) between system SVID clock line (SVID_CLK-R) and voltage regulator controller SCLK pin. Provides signal integrity and current limiting for the SVID interface.
2	2	$24N3491	✅	Series resistor (20.0Ω) between system SVID clock line (SVID_CLK-R) and voltage regulator controller SCLK pin. Provides signal integrity and current limiting for the SVID interface.

R196 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor (69.8Ω) on SVID alert line, marked DNI (Do Not Install). This is consistent with ALERT being a push-pull output that does not require a pull-up resistor.
2	2	SVID_ALERT-R	✅	Pull-up resistor (69.8Ω) on SVID alert line, marked DNI (Do Not Install). This is consistent with ALERT being a push-pull output that does not require a pull-up resistor.

L4 - 3120-0266 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
2	2	+VGFX	❌	Inductor connections are topologically correct (pin 1 to switching node VGFX-SW, pin 2 to output +VGFX), but the inductor current rating is insufficient for the design requirements. Pin 1 connects to net VGFX-SW (switching node from U26) (from schematic) Pin 2 connects to net +VGFX (regulated output voltage) (from schematic) The inductor is specified as 470nH with 17.5A current rating and 4.2mΩ DCR (from schematic) Multiple output capacitors (C66, C67, C68, C78, C79, C80, C81, C76, C77) connect to +VGFX (from schematic) In a buck converter topology, the inductor connects between the switching node and the output voltage rail, which is correct here (reasoning) A text note 'IMAX = 24A' is positioned at coordinates (462.28, 229.87), very close to L4's position at (462.28, 181.61) (from schematic) A separate text note 'IMAX = 14A' is positioned at (388.62, 242.57) near the current limit configuration resistors R207 and R227 (from schematic) R227 (16.5K) connects U26 pin 36 (IOUT) to AGND-VGFX, and R207 (44.2K) connects U26 pin 35 (IMAX) to AGND-VGFX, setting the controller current limit (from schematic) The switching frequency is 650kHz based on text note and R203 (18.7K) connected to the FREQ pin (from schematic) There is a significant discrepancy between the inductor's 17.5A rating and the 24A specification noted near the inductor (reasoning) Even if the controller is configured for 14A average current limit, the peak inductor current including switching ripple could approach or exceed 17.5A (reasoning) For a buck converter with Vin≈5V (from +5VSB_SW) and Vout≈1V (typical GPU core voltage), 470nH inductance, and 650kHz switching frequency, the current ripple would be approximately 2.6A peak-to-peak (reasoning) At 14A average current, the peak current would be approximately 15.3A, which provides minimal margin below the 17.5A rating (reasoning) At 24A average current (if that is the actual requirement), the peak current would exceed 25A, far exceeding the inductor's rating (reasoning) Operating an inductor above its rated current can cause saturation (loss of inductance) or thermal failure (reasoning) The inductor should be rated for at least the maximum expected current with 20-30% design margin (reasoning) The design has conflicting specifications that need resolution: either the 24A requirement should be verified and a higher-rated inductor used, or the 24A specification is incorrect and should be corrected to match the actual 14A design limit (reasoning)
1	1	VGFX-SW	✅	Pin 1 connects to the switching node VGFX-SW from the multiphase controller U26. This is the correct connection for the input side of a buck converter output inductor.

R231 - 1141-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Forms an RC snubber network with C187 to dampen switching node ringing and reduce EMI. Pin 1 connects to VGFX-SW switching node, pin 2 connects through C187 to GND.
2	2	$24N3623	✅	Forms an RC snubber network with C187 to dampen switching node ringing and reduce EMI. Pin 1 connects to VGFX-SW switching node, pin 2 connects through C187 to GND.

C187 - 2240-0005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3623	✅	Forms the capacitive element of an RC snubber network with R231. Pin 1 connects to the snubber resistor, pin 2 connects to GND.
2	2	GND	✅	Forms the capacitive element of an RC snubber network with R231. Pin 1 connects to the snubber resistor, pin 2 connects to GND.

R854 - 1130-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Pre-load resistor connecting +VGFX output to GND. Provides minimum load current for stable regulator operation and faster transient response.
2	2	GND	✅	Pre-load resistor connecting +VGFX output to GND. Provides minimum load current for stable regulator operation and faster transient response.

SP2 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Pin 1 connects to the switching node VGFX-SW. This short provides an optional connection from the switching node to the current sense sum network through R224.
2	2	$24N3558	✅	Pin 2 connects to net $24N3558, which connects through R224 (100kΩ) to VGFX-CSSUM (pin 39 of U26). This samples the switching node voltage for current sensing. A design note specifies this short should be placed on the solder side close to the inductor.

SP1 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Pin 1 connects to the output voltage rail +VGFX. This short provides an optional connection from the output to the current sense reference network through R225.
2	2	$24N3559	✅	Pin 2 connects to net $24N3559, which connects through R225 (10Ω) to VGFX-CSREF (pin 40 of U26). This provides a reference voltage for the current sensing circuit. A design note specifies this short should be placed on the solder side close to the inductor.

R198 - 1120-0032 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3524	✅	Connected to net $24N3524, which is part of the feedback divider and compensation network. This connection appears correct for the voltage feedback compensation circuit.
2	2	VGFX-FB	✅	Connected to VGFX-FB feedback network. This connection is correct for the voltage feedback path.

R200 - 1121-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3522	✅	Connected to net $24N3522, which is part of the differential sensing network. This connection appears correct.
2	2	VGFX-DIFFOUT	✅	Connected to VGFX-DIFFOUT. This connection is correct for the differential sensing network.

C63 - 2220-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-FB	✅	Connected to VGFX-FB feedback network. This connection is correct for the differential sensing path.
2	2	$24N3522	✅	Connected to net $24N3522, which is part of the differential sensing network. This connection is correct for AC coupling or filtering.

C64 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-COMP	✅	Connected to VGFX-COMP compensation pin. This connection is correct for the voltage loop compensation network.
2	2	$24N3524	✅	Connected to net $24N3524, forming an RC compensation network with R198. This connection is correct for Type II or Type III compensation.

R199 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-FB	✅	Connected to VGFX-FB feedback network. This connection is correct for the differential sensing configuration.
2	2	VGFX-DIFFOUT	✅	Connected to VGFX-DIFFOUT, which connects to U26 pin 44 (DIFFOUT). This connection is correct for differential remote voltage sensing.

C62 - 2220-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-COMP	✅	Connected to VGFX-COMP compensation pin. This connection is correct for the voltage loop compensation network.
2	2	VGFX-FB	✅	Connected to VGFX-FB feedback network. This connection is correct for Type II compensation.

R68 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCCGT_SENSE	✅	0Ω jumper connecting remote voltage sense point VCCGT_SENSE to the VSP pin (U26 pin 46) of the voltage regulator controller. This enables remote sensing of the output voltage at the load, compensating for voltage drops in the power distribution network.
2	2	VR-VGFX-VSP	✅	0Ω jumper connecting remote voltage sense point VCCGT_SENSE to the VSP pin (U26 pin 46) of the voltage regulator controller. This enables remote sensing of the output voltage at the load, compensating for voltage drops in the power distribution network.

R69 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0Ω jumper connecting GND to intermediate node $24N3528, which feeds through R169 (10Ω) to the VSN pin (U26 pin 45). This provides a direct ground reference for the differential voltage sense. Part of a design flexibility configuration where either R69 or R201 can be populated.
2	2	$24N3528	✅	0Ω jumper connecting GND to intermediate node $24N3528, which feeds through R169 (10Ω) to the VSN pin (U26 pin 45). This provides a direct ground reference for the differential voltage sense. Part of a design flexibility configuration where either R69 or R201 can be populated.

R201 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	100Ω resistor connecting GND to intermediate node $24N3528, in parallel with 0Ω jumper R69. Provides an alternative configuration option with series resistance if R69 is not populated. Part of a design flexibility feature for different sensing configurations.
2	2	$24N3528	✅	100Ω resistor connecting GND to intermediate node $24N3528, in parallel with 0Ω jumper R69. Provides an alternative configuration option with series resistance if R69 is not populated. Part of a design flexibility feature for different sensing configurations.

R202 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	100Ω resistor connecting +VGFX output to VR-VGFX-VSP (U26 pin 46), providing a local sense path in parallel with the remote sense through R68. Ensures VSP has a valid voltage reference even if remote sense is disconnected, which is a common design practice for robust remote sensing.
2	2	VR-VGFX-VSP	✅	100Ω resistor connecting +VGFX output to VR-VGFX-VSP (U26 pin 46), providing a local sense path in parallel with the remote sense through R68. Ensures VSP has a valid voltage reference even if remote sense is disconnected, which is a common design practice for robust remote sensing.

R169 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3528	✅	10Ω resistor in series with the VSN sense path, connecting intermediate node $24N3528 to VR-VGFX-VSN (U26 pin 45). Provides filtering and current limiting for the negative sense input, forming part of the differential remote sense circuit.
2	2	VR-VGFX-VSN	✅	10Ω resistor in series with the VSN sense path, connecting intermediate node $24N3528 to VR-VGFX-VSN (U26 pin 45). Provides filtering and current limiting for the negative sense input, forming part of the differential remote sense circuit.

C61 - 2221-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR-VGFX-VSP	✅	1000pF capacitor between VSP and VSN sense inputs, marked DNI. Would provide differential mode filtering for the remote sense signals if populated, but is not required for this design.
2	2	VR-VGFX-VSN	✅	1000pF capacitor between VSP and VSN sense inputs, marked DNI. Would provide differential mode filtering for the remote sense signals if populated, but is not required for this design.

C104 - 2221-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3528	✅	0.01µF capacitor between intermediate node $24N3528 and VSN, marked DNI. Would provide additional filtering for the VSN sense path if populated, forming an RC filter with R169 (10Ω).
2	2	VR-VGFX-VSN	✅	0.01µF capacitor between intermediate node $24N3528 and VSN, marked DNI. Would provide additional filtering for the VSN sense path if populated, forming an RC filter with R169 (10Ω).

R204 - 1120-0029 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-ILIM	✅	Connected to VGFX-ILIM (pin 37 of U26). Sets the current limit threshold.
2	2	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP (pin 38 of U26). The 15K value sets the current limit level.

TH3 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP (pin 38 of U26). Provides temperature compensation for current sensing.
2	2	$24N3557	✅	Connected to intermediate node $24N3557. Works with R205 to provide temperature-compensated DCR current sensing.

R224 - 1130-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSSUM	✅	Connected to VGFX-CSSUM (pin 39 of U26). Part of the current sense sum network for DCR current sensing.
2	2	$24N3558	✅	Connected to $24N3558, which connects to VGFX-SW through SP2. This forms the switching node connection for DCR current sensing.

R225 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	Connected to VGFX-CSREF (pin 40 of U26). Provides current sense reference from the output voltage.
2	2	$24N3559	✅	Connected to $24N3559, which connects to +VGFX through SP1. Provides output-tracking current sense reference.

R205 - 1120-0282 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP (pin 38 of U26). Provides DC feedback for current loop compensation.
2	2	$24N3557	✅	Connected to intermediate node $24N3557. In parallel with TH3 to provide temperature-compensated current sensing.

C166 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP (pin 38 of U26). In parallel with C113 for additional filtering.
2	2	VGFX-CSSUM	✅	Connected to VGFX-CSSUM (pin 39 of U26). Provides additional filtering for current sense signal.

C167 - 2220-0035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	Connected to VGFX-CSREF (pin 40 of U26). Filters the current sense reference signal.
2	2	GND	✅	Connected to GND. Provides filtering for the CSREF signal.

C113 - 2220-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP (pin 38 of U26). Provides AC coupling and filtering for current sense signal.
2	2	VGFX-CSSUM	✅	Connected to VGFX-CSSUM (pin 39 of U26). Forms AC coupling path for current loop compensation.

R223 - 1120-0037 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3557	✅	Connected to intermediate node $24N3557, which is shared with R205, TH3, and C166. Part of the current sense scaling network.
2	2	VGFX-CSSUM	✅	Connected to VGFX-CSSUM (pin 39 of U26). Forms part of the voltage divider for current sense scaling.

C184 - 2220-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3589	✅	C184 filters the current sense output signal on U26 pin 36 (IOUT) by connecting between the IOUT pin and AGND-VGFX. The 470pF value provides high-frequency noise filtering.
2	2	AGND-VGFX	✅	C184 filters the current sense output signal on U26 pin 36 (IOUT) by connecting between the IOUT pin and AGND-VGFX. The 470pF value provides high-frequency noise filtering.

TH4 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	TH4 is a 100K NTC thermistor that forms part of the temperature sensing network for U26 pin 34 (TSENSE). It connects between the thermistor network node and GND, working with R226 to create a temperature-dependent voltage divider.
2	2	GND	✅	TH4 is a 100K NTC thermistor that forms part of the temperature sensing network for U26 pin 34 (TSENSE). It connects between the thermistor network node and GND, working with R226 to create a temperature-dependent voltage divider.

R227 - 1120-0338 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3589	✅	R227 sets the current sense gain for the IOUT monitoring pin by connecting U26 pin 36 (IOUT) to AGND-VGFX. The 16.5K value determines the scaling of the current sense output.
2	2	AGND-VGFX	✅	R227 sets the current sense gain for the IOUT monitoring pin by connecting U26 pin 36 (IOUT) to AGND-VGFX. The 16.5K value determines the scaling of the current sense output.

R178 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	R178 is a 0-ohm jumper that connects U26 pin 34 (TSENSE) to the thermistor network. It allows for optional series resistance in the temperature sense path if needed for calibration or filtering.
2	2	$24N3583	✅	R178 is a 0-ohm jumper that connects U26 pin 34 (TSENSE) to the thermistor network. It allows for optional series resistance in the temperature sense path if needed for calibration or filtering.

R226 - 1120-0055 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	R226 forms part of the temperature sensing voltage divider by connecting between the thermistor network node and GND. The 14K value works with TH4 to create a temperature-dependent voltage for U26 pin 34 (TSENSE).
2	2	GND	✅	R226 forms part of the temperature sensing voltage divider by connecting between the thermistor network node and GND. The 14K value works with TH4 to create a temperature-dependent voltage for U26 pin 34 (TSENSE).

C168 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	C168 is a bypass capacitor that filters noise on the TSENSE input by connecting between U26 pin 34 (TSENSE) and AGND-VGFX. The 0.1uF value provides effective filtering of high-frequency noise.
2	2	AGND-VGFX	✅	C168 is a bypass capacitor that filters noise on the TSENSE input by connecting between U26 pin 34 (TSENSE) and AGND-VGFX. The 0.1uF value provides effective filtering of high-frequency noise.

R207 - 1120-0115 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3588	✅	R207 sets the maximum current limit for the voltage regulator by connecting U26 pin 35 (IMAX) to AGND-VGFX. The 44.2K value is intended to set a 14A current limit per the nearby text note.
2	2	AGND-VGFX	✅	R207 sets the maximum current limit for the voltage regulator by connecting U26 pin 35 (IMAX) to AGND-VGFX. The 44.2K value is intended to set a 14A current limit per the nearby text note.

R184 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Connected to VGFX_PG power good signal net.
2	2	$24N3598	✅	Connected to net $24N3598 which is the VR_RDY output (pin 6) of U26.

R850 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Connected to +VCC power rail to provide enable signal to U26.
2	2	$24N6011	✅	Connected to net $24N6011 which drives the EN pin (pin 48) of U26. With R852 also populated, this creates a current path from +VCC through R852 (10K) to GND, wasting approximately 0.5mA (assuming 5V rail).

R852 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	Connected to net $24N6011 which is the enable signal for U26. With R850 also populated, this creates unnecessary current draw from +VCC to GND.
2	2	GND	✅	Connected to GND to provide pull-down for the enable signal.

R230 - 1120-0052 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Connected to +VCC3 power rail to provide pull-up for the open-drain power good signal.
2	2	VGFX_PG	✅	Connected to VGFX_PG signal to pull up the open-drain VR_RDY output from U26.

C60 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Connected to VGFX_PG signal to provide filtering for the power good signal.
2	2	GND	✅	Connected to GND to complete the filtering path.

C434 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	Connected to net $24N6011 to provide filtering/decoupling for the EN pin of U26.
2	2	GND	✅	Connected to GND to complete the decoupling path.

C76 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	Positive terminal correctly connected to +VGFX output rail. This provides bulk output capacitance for the DC/DC GFX regulator.
2	N	GND	✅	Negative terminal correctly connected to GND. Proper polarity for tantalum capacitor operation.

C77 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	Positive terminal correctly connected to +VGFX output rail. This provides bulk output capacitance in parallel with C76 for the DC/DC GFX regulator.
2	N	GND	✅	Negative terminal correctly connected to GND. Proper polarity for tantalum capacitor operation.

U41 - RT8207 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
22	BOOT	$25N771	❌	BOOT pin connected to bootstrap network with C309 (0.1µF) and series resistor R298 (4.7Ω). Bootstrap capacitor is 10x smaller than datasheet recommendation of 1µF, which may cause insufficient gate drive and reliability issues. Pin 22 (BOOT) is connected to net $25N771 (from schematic) BOOT is the boost flying capacitor connection for VDDQ (from datasheet RT8207, page 2) The instantaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins (from datasheet RT8207, page 15) Datasheet typical application circuit shows 1µF bootstrap capacitor (from datasheet RT8207, page 3) For high current applications, adding a resistor in series with BOOT can prevent shoot-through by increasing turn-on rising time (from datasheet RT8207, page 15) The 4.7Ω series resistor R298 is appropriate for shoot-through prevention (reasoning) For typical MOSFET gate charge of 10-30nC, 0.1µF provides 50nC with 0.5V droop, giving margin of only 1.7-5x (reasoning) With recommended 1µF, margin increases to 17-50x, providing much better reliability (reasoning) The 10x reduction from recommended value could cause insufficient gate drive at high frequencies, temperature extremes, or with MOSFETs having higher gate charge (reasoning) Bootstrap capacitor C309 should be increased to 1µF per datasheet recommendation (reasoning)
1	VTTGND	GND	✅	VTTGND pin correctly connected to GND for VTT LDO power ground.
2	VTTSNS	+VDIMM_VTT	✅	VTTSNS pin correctly connected to +VDIMM_VTT for remote voltage sensing of VTT output.
3	GND	GND	✅	GND pin correctly connected to ground plane.
4	MODE	GND	✅	MODE pin connected to GND for mode selection.
5	VTTREF	$25N769	✅	VTTREF pin correctly connected to C342 (0.22uF) for output decoupling.
6	DEM	$25N1291	✅	DEM pin connected to pull-up resistor R810 (10K to +5VSB) for diode emulation mode control.
8	VDDQ	+VDIMM	✅	VDDQ pin correctly connected to +VDIMM output for reference and feedback.
9	FB	$25N987	✅	FB pin correctly connected to resistive divider (R814/R815) setting output to 1.35V for DDR3L.
10	S3	EN_VTT	✅	S3 pin correctly connected to EN_VTT signal for S3 state control.
11	S5	EN_VDDQ	✅	S5 pin correctly connected to EN_VDDQ signal for S5 state control.
12	TON	$25N1081	✅	TON pin connected to R816 (464K) setting switching frequency to approximately 503kHz.
13	PGOOD	DRAM_PWROK	✅	PGOOD pin correctly connected to DRAM_PWROK with pull-up resistor for power good indication.
14	VDD	$25N1195	✅	VDD pin connected to +5VSB through R813 (2.2 ohm) with C380 (1uF) decoupling. Resistor value is smaller than datasheet recommendation of 5.1 ohm but should still function.
15	VDDP	+5VSB	✅	VDDP pin correctly connected to +5VSB for gate driver supply.
16	CS	$25N1238	✅	CS pin correctly connected to R817 (3.83K) setting current limit to approximately 11A.
18	PGND	GND	✅	PGND pin correctly connected to GND for low-side MOSFET power ground.
19	LGATE	$25N901	✅	LGATE pin correctly connected to Q102 pin 8 (low-side MOSFET gate).
20	PHASE	DDR_PHASE	✅	PHASE pin correctly connected to switching node between MOSFETs and output inductor.
21	UGATE	$25N897	✅	UGATE pin correctly connected to Q102 pin 1 (high-side MOSFET gate).
23	VLDOIN	+VDIMM	✅	VLDOIN pin correctly connected to +VDIMM output for VTT LDO power supply.
24	VTT	+VDIMM_VTT	✅	VTT pin correctly connected to +VDIMM_VTT output.
25	GND_PAD	GND	✅	GND_PAD (exposed pad) correctly connected to GND for thermal dissipation.

R816 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	TON timing resistor correctly connected between +5VSB and U41 TON pin. Value is 464KΩ giving ~500kHz switching frequency, though schematic text note specifies 806KΩ for 285kHz operation. Circuit appears designed for actual 500kHz operation based on 1µH inductor selection.
2	2	$25N1081	✅	TON timing resistor correctly connected between +5VSB and U41 TON pin. Value is 464KΩ giving ~500kHz switching frequency, though schematic text note specifies 806KΩ for 285kHz operation. Circuit appears designed for actual 500kHz operation based on 1µH inductor selection.

R813 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

C380 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

C379 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

R817 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

R814 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

R815 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

C382 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

C342 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis

C309 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_PHASE	✅	C309 is a 0.1uF bootstrap capacitor correctly connected between the DDR_BST node and the DDR_PHASE switching node, though with series resistor R298 in the path from the BOOT pin.
2	2	DDR_BST	✅	C309 is a 0.1uF bootstrap capacitor correctly connected between the DDR_BST node and the DDR_PHASE switching node, though with series resistor R298 in the path from the BOOT pin.

Q102 - FDMS3604S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	Q1G	$25N897	✅	Q1G (Gate of control MOSFET Q1) is correctly connected to the UGATE output of the RT8207 controller U41 via net $25N897.
2	VIN_A	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (Drain pins of control MOSFET Q1) are correctly connected to the DDR3L_VIN input supply with appropriate bypass capacitors.
3	VIN_B	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (Drain pins of control MOSFET Q1) are correctly connected to the DDR3L_VIN input supply with appropriate bypass capacitors.
4	VIN_C	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (Drain pins of control MOSFET Q1) are correctly connected to the DDR3L_VIN input supply with appropriate bypass capacitors.
5	PGND_A	GND	✅	PGND_A, PGND_B, PGND_C (Source pins of synchronous MOSFET Q2) are correctly connected to ground.
6	PGND_B	GND	✅	PGND_A, PGND_B, PGND_C (Source pins of synchronous MOSFET Q2) are correctly connected to ground.
7	PGND_C	GND	✅	PGND_A, PGND_B, PGND_C (Source pins of synchronous MOSFET Q2) are correctly connected to ground.
8	Q2G	$25N901	✅	Q2G (Gate of synchronous MOSFET Q2) is correctly connected to the LGATE output of the RT8207 controller U41 via net $25N901.
9	PHASE	DDR_PHASE	✅	PHASE (internally connected switch node) is correctly connected to the output inductor L11, controller feedback pin, and bootstrap capacitor C309.

R298 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N771	✅	R298 is a 4.7 ohm resistor connected in series with the bootstrap capacitor C309 between the RT8207 BOOT pin and the PHASE node. This configuration is unusual but may be intentional for damping or current limiting purposes.
2	2	DDR_BST	✅	R298 is a 4.7 ohm resistor connected in series with the bootstrap capacitor C309 between the RT8207 BOOT pin and the PHASE node. This configuration is unusual but may be intentional for damping or current limiting purposes.

L11 - 125-0004454 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_PHASE	✅	Pin 1 connects to the DDR_PHASE switching node, which is the output of the buck converter MOSFETs. This is the correct connection for the input side of a buck converter output inductor.
2	2	+VDIMM	✅	Pin 2 connects to the +VDIMM output rail. This is the correct connection for the output side of a buck converter output inductor.

C328 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin providing return path for input filtering capacitor.
2	2	DDR3L_VIN	✅	Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter.

L5 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input pin connected to +5VSB supply rail. This provides the unfiltered input to the ferrite bead.
2	2	DDR3L_VIN	✅	Output pin connected to DDR3L_VIN rail. This provides filtered power to the buck converter input stage.

C128 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin providing return path for input filtering capacitor.
2	2	DDR3L_VIN	✅	Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter.

C126 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin providing return path for input filtering capacitor.
2	2	DDR3L_VIN	✅	Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter.

L6 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input pin connected to +5VSB supply rail. This provides the unfiltered input to the ferrite bead, in parallel with L5.
2	2	DDR3L_VIN	✅	Output pin connected to DDR3L_VIN rail. This provides filtered power to the buck converter input stage, in parallel with L5.

C127 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin providing return path for input filtering capacitor.
2	2	DDR3L_VIN	✅	Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter.

C327 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin providing return path for high-frequency decoupling capacitor.
2	2	DDR3L_VIN	✅	Positive pin connected to DDR3L_VIN rail, providing high-frequency decoupling for the buck converter input.

C129 - 123-0005035 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VDIMM	❌	330uF tantalum capacitor connected between +VDIMM (1.35V) and GND for bulk output filtering. The 2V voltage rating provides 48% margin above the 1.35V nominal output, resulting in 67.5% voltage utilization which exceeds the standard 50% derating guideline typically recommended for tantalum capacitors. Pin 1 (P) is connected to +VDIMM net (from schematic) Pin 2 (N) is connected to GND net (from schematic) C129 is a 330uF tantalum capacitor with 2V voltage rating in C7343 package (from schematic) The +VDIMM output voltage is 1.35V according to the text note on the schematic (from schematic) The polarity is correct with positive terminal connected to the positive rail and negative terminal to ground (reasoning) The voltage margin is 2V / 1.35V = 1.48x or 48% above nominal, resulting in 67.5% voltage utilization (reasoning) Industry standard practice for tantalum capacitors recommends 50% voltage derating for reliability, meaning a 2V capacitor should ideally be used at maximum 1V continuous operation (reasoning) Operating at 67.5% of rated voltage exceeds the conservative 50% derating guideline by 35% (reasoning) While some modern tantalum capacitors may be qualified for operation above 50% of rated voltage, this should be verified against the specific part number datasheet (reasoning) For conservative design following standard derating practices at 1.35V, a tantalum capacitor should be rated for at least 2.7V, preferably 4V or higher (reasoning) The marginal voltage rating may impact long-term reliability, particularly under voltage transients or elevated temperature conditions (reasoning) Recommendation: Verify that part number 123-0005035 datasheet explicitly allows operation at 67.5% of rated voltage, or consider replacing with a capacitor rated for at least 4V to provide adequate margin (reasoning)
2	N	GND	❌	330uF tantalum capacitor connected between +VDIMM (1.35V) and GND for bulk output filtering. The 2V voltage rating provides 48% margin above the 1.35V nominal output, resulting in 67.5% voltage utilization which exceeds the standard 50% derating guideline typically recommended for tantalum capacitors. Pin 1 (P) is connected to +VDIMM net (from schematic) Pin 2 (N) is connected to GND net (from schematic) C129 is a 330uF tantalum capacitor with 2V voltage rating in C7343 package (from schematic) The +VDIMM output voltage is 1.35V according to the text note on the schematic (from schematic) The polarity is correct with positive terminal connected to the positive rail and negative terminal to ground (reasoning) The voltage margin is 2V / 1.35V = 1.48x or 48% above nominal, resulting in 67.5% voltage utilization (reasoning) Industry standard practice for tantalum capacitors recommends 50% voltage derating for reliability, meaning a 2V capacitor should ideally be used at maximum 1V continuous operation (reasoning) Operating at 67.5% of rated voltage exceeds the conservative 50% derating guideline by 35% (reasoning) While some modern tantalum capacitors may be qualified for operation above 50% of rated voltage, this should be verified against the specific part number datasheet (reasoning) For conservative design following standard derating practices at 1.35V, a tantalum capacitor should be rated for at least 2.7V, preferably 4V or higher (reasoning) The marginal voltage rating may impact long-term reliability, particularly under voltage transients or elevated temperature conditions (reasoning) Recommendation: Verify that part number 123-0005035 datasheet explicitly allows operation at 67.5% of rated voltage, or consider replacing with a capacitor rated for at least 4V to provide adequate margin (reasoning)

C136 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin.
2	2	+VDIMM	✅	High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin.

C137 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating.
2	2	+VDIMM	✅	Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating.

C138 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin.
2	2	+VDIMM	✅	High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin.

C139 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin.
2	2	+VDIMM	✅	High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin.

C140 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating.
2	2	+VDIMM	✅	Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating.

C141 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating.
2	2	+VDIMM	✅	Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating.

C359 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Medium-value output capacitor for +VDIMM rail, correctly connected between +VDIMM and GND with adequate voltage rating.
2	2	GND	✅	Medium-value output capacitor for +VDIMM rail, correctly connected between +VDIMM and GND with adequate voltage rating.

C343 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This pin provides the ground terminal of the high-frequency decoupling capacitor.
2	2	+VDIMM_VTT	✅	Connected to +VDIMM_VTT power rail. This pin provides high-frequency decoupling for the VTT regulator output.

C362 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM_VTT	✅	Connected to +VDIMM_VTT power rail. This pin provides the positive terminal of the second bulk output capacitor for the VTT regulator.
2	2	GND	✅	Connected to GND. This pin provides the ground return path for the second bulk output capacitor.

C361 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM_VTT	✅	Connected to +VDIMM_VTT power rail. This pin provides the positive terminal of the bulk output capacitor for the VTT regulator.
2	2	GND	✅	Connected to GND. This pin provides the ground return path for the bulk output capacitor.

R24 - 110-0002560 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Upper feedback resistor connected between output voltage +V1P8S and feedback pin.
2	2	+V1P8S_FB	✅	Connected to feedback network at +V1P8S_FB node.

R25 - 110-0004490 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower feedback resistor connected to ground.
2	2	+V1P8S_FB	✅	Connected to feedback network at +V1P8S_FB node.

R22 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1P8V_EN	✅	0-ohm jumper connecting enable control circuit to LDO enable pin.
2	2	+V1P8S_EN	✅	Connected to U21 enable pin through +V1P8S_EN net.

R23 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pull-up resistor for power good signal, connected to output voltage.
2	2	+V1P8S_PGD	✅	Connected to power good signal from U21.

C9 - 123-0001079 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S_FB	✅	150pF capacitor marked DNI (Do Not Install) across feedback network. Since it is not installed, it does not affect the circuit operation.
2	2	+V1P8S	✅	150pF capacitor marked DNI (Do Not Install) across feedback network. Since it is not installed, it does not affect the circuit operation.

U21 - 140-0004526 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P8S_PGD	✅	PGOOD pin connected to +V1P8S_PGD net with 4.7K pull-up resistor R23 to output voltage +V1P8S. This is a typical open-drain power good output configuration.
2	EN	+V1P8S_EN	✅	EN pin connected to +V1P8S_EN net through 0-ohm resistor R22, which connects to enable control circuit with Q3 and pull-up R125. Text note indicates enable threshold > 1.1V.
3	VIN	+PS_3VSB	✅	VIN pin connected to +PS_3VSB (3.3V standby supply) with input decoupling capacitors C6 (10uF) and C3 (0.1uF) nearby.
4	VDD	+PS_3VSB	✅	VDD pin connected to +PS_3VSB, same as VIN. This is typical for LDOs where VDD powers the control circuitry.
5	NC		✅	NC pin is correctly left unconnected as specified.
6	VOUT	+V1P8S	✅	VOUT pin connected to +V1P8S with output capacitors C8 (10uF), C4 (0.1uF), and C7 (22uF) providing total 32.1uF output capacitance. Text note indicates 1.14A expected load current.
7	ADJ	+V1P8S_FB	✅	ADJ pin connected to feedback divider network with R24 (12.1K) to output and R25 (9.53K) to ground. Calculated output voltage is 1.816V using formula Vout=0.8(1+R1/R2), which is within tolerance of target 1.8V.
8	GND1	GND	✅	GND1 and GND2 pins both correctly connected to ground plane.
9	GND2	GND	✅	GND1 and GND2 pins both correctly connected to ground plane.

R150 - 110-0002560 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	R150 (12.1K ohm) forms the upper resistor (R1) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to set the output voltage to 1.8V.
2	2	+V1P8A	✅	R150 (12.1K ohm) forms the upper resistor (R1) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to set the output voltage to 1.8V.

R153 - 110-0002726 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	R153 (27.4K ohm) forms the lower resistor (R2) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and GND (pin 2) to set the output voltage to 1.8V.
2	2	GND	✅	R153 (27.4K ohm) forms the lower resistor (R2) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and GND (pin 2) to set the output voltage to 1.8V.

C152 - 123-0001102 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	C152 (22pF) is a compensation capacitor correctly connected in parallel with R150 between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to improve feedback loop stability and transient response.
2	2	+V1P8A	✅	C152 (22pF) is a compensation capacitor correctly connected in parallel with R150 between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to improve feedback loop stability and transient response.

R151 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	R151 (0 ohm jumper) correctly implements power sequencing by connecting +V1P0A_PWRGD (pin 1) to +V1P8A_EN (pin 2), ensuring the 1.0V rail is stable before enabling the 1.8V rail.
2	2	+V1P8A_EN	✅	R151 (0 ohm jumper) correctly implements power sequencing by connecting +V1P0A_PWRGD (pin 1) to +V1P8A_EN (pin 2), ensuring the 1.0V rail is stable before enabling the 1.8V rail.

U20 - NCP606 ✅

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📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN1	+PS_3VSB	✅	VIN1 is correctly connected to +PS_3VSB (3.3V standby supply) with adequate input decoupling capacitors.
2	GND	GND	✅	GND is correctly connected to the ground plane.
3	EN	+V1P8A_EN	✅	EN (enable) is correctly connected to +V1P8A_EN, which is derived from +V1P0A_PWRGD through 0-ohm resistor R151, implementing proper power sequencing.
4	VOUT	+V1P8A	✅	VOUT is correctly connected to +V1P8A output net with proper output decoupling capacitor C151 (10uF).
5	SENSE/ADJ	+V1P8A_FB	✅	SENSE/ADJ is correctly connected to feedback divider network (R150=12.1K, R153=27.4K) to set output voltage to approximately 1.8V.
6	VIN2	+PS_3VSB	✅	VIN2 is correctly connected to +PS_3VSB, same as VIN1, as required by the datasheet for full output current range operation.
7	GND_PAD	GND	✅	GND_PAD (exposed pad) is correctly connected to ground for thermal dissipation.

R306 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_GFX_PG	✅	0 ohm jumper connecting VCORE_GFX_PG to 1P0V_EN (U38 enable), implementing power sequencing.
2	2	1P0V_EN	✅	0 ohm jumper connecting VCORE_GFX_PG to 1P0V_EN (U38 enable), implementing power sequencing.

R136 - 110-0002029 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FB_V1P0S	✅	Upper feedback resistor (40.2K) in voltage divider for U38, connected between FB_V1P0S and +V1P0S. Sets output voltage to 1.025V with R135.
2	2	+V1P0S	✅	Upper feedback resistor (40.2K) in voltage divider for U38, connected between FB_V1P0S and +V1P0S. Sets output voltage to 1.025V with R135.

C119 - 123-0001107 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FB_V1P0S	✅	27pF compensation capacitor in parallel with R136 in U38 feedback network, providing phase compensation with corner frequency around 147 kHz.
2	2	+V1P0S	✅	27pF compensation capacitor in parallel with R136 in U38 feedback network, providing phase compensation with corner frequency around 147 kHz.

R320 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCNTL_V1P0S	✅	10 ohm resistor connecting +VCC to VCNTL_V1P0S, forming RC filter with C117 (1uF) for U38 VCNTL pin. Without datasheet, cannot verify if this configuration is correct.
2	2	+VCC	✅	10 ohm resistor connecting +VCC to VCNTL_V1P0S, forming RC filter with C117 (1uF) for U38 VCNTL pin. Without datasheet, cannot verify if this configuration is correct.

R319 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	10K pull-up resistor for U38 power good output (V1P0S_PG) to +VCC.
2	2	+VCC	✅	10K pull-up resistor for U38 power good output (V1P0S_PG) to +VCC.

R135 - 110-0004498 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower feedback resistor (143K) in voltage divider for U38, connected between GND and FB_V1P0S. Sets output voltage to 1.025V with R136.
2	2	FB_V1P0S	✅	Lower feedback resistor (143K) in voltage divider for U38, connected between GND and FB_V1P0S. Sets output voltage to 1.025V with R136.

U38 - APL5912KAC-TRGS-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	Ground pin correctly connected to GND.
2	FB	FB_V1P0S	✅	Feedback pin connected to resistive divider network (R136, R135) with compensation capacitor C119. Output voltage calculated to be 1.025V based on 0.8V reference and divider ratio.
3	VOUT-2	+V1P0S	✅	Output pins correctly connected to +V1P0S rail. Multiple output pins are common in high-current LDOs for current distribution.
4	VOUT-1	+V1P0S	✅	Output pins correctly connected to +V1P0S rail. Multiple output pins are common in high-current LDOs for current distribution.
5	VIN-2	+VDIMM	✅	Input pins correctly connected to +VDIMM rail. Multiple input pins are common in high-current LDOs.
9	VIN-1	+VDIMM	✅	Input pins correctly connected to +VDIMM rail. Multiple input pins are common in high-current LDOs.
6	VCNTL	VCNTL_V1P0S	✅	VCNTL pin connected through 10 ohm resistor (R320) to +VCC with 1uF capacitor (C117) to ground, forming an RC filter. Without datasheet, cannot verify if this control voltage configuration is correct.
7	POK	V1P0S_PG	✅	Power good output pin correctly connected with 10K pull-up resistor (R319) to +VCC and used to enable downstream regulator (1P35V_EN through R134).
8	EN	1P0V_EN	✅	Enable pin connected through 0 ohm resistor (R306) to VCORE_GFX_PG, implementing power sequencing. Text note indicates enable threshold is >0.5V.

R34 - 110-0003781 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Upper feedback resistor correctly connected between output voltage (+V1P0A) and feedback node (+V1P0A_FB) to set the 1.0V output voltage.
2	2	+V1P0A	✅	Upper feedback resistor correctly connected between output voltage (+V1P0A) and feedback node (+V1P0A_FB) to set the 1.0V output voltage.

R35 - 110-0004494 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Lower feedback resistor correctly connected between feedback node (+V1P0A_FB) and ground to set the 1.0V output voltage.
2	2	GND	✅	Lower feedback resistor correctly connected between feedback node (+V1P0A_FB) and ground to set the 1.0V output voltage.

R32 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Enable pull-up resistor correctly connected between +5VSB and the enable pin of U24 to enable the LDO when standby power is present.
2	2	+V1P0A_ENABLE	✅	Enable pull-up resistor correctly connected between +5VSB and the enable pin of U24 to enable the LDO when standby power is present.

R33 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB	✅	Power good pull-up resistor correctly connected between +PS_3VSB and the open-drain PGOOD output of U24 to provide a logic high level when the output is in regulation.
2	2	+V1P0A_PWRGD	✅	Power good pull-up resistor correctly connected between +PS_3VSB and the open-drain PGOOD output of U24 to provide a logic high level when the output is in regulation.

C23 - 123-0001079 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Compensation capacitor marked DNI (Do Not Install), intentionally not installed across the upper feedback resistor R34, indicating the LDO regulator is stable without additional phase compensation.
2	2	+V1P0A	✅	Compensation capacitor marked DNI (Do Not Install), intentionally not installed across the upper feedback resistor R34, indicating the LDO regulator is stable without additional phase compensation.

R31 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Enable pull-down resistor marked DNI (Do Not Install), intentionally not installed on the enable pin, indicating that pull-up through R32 alone is sufficient for enable control.
2	2	+V1P0A_ENABLE	✅	Enable pull-down resistor marked DNI (Do Not Install), intentionally not installed on the enable pin, indicating that pull-up through R32 alone is sufficient for enable control.

U24 - APL5933 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P0A_PWRGD	✅	PGOOD output is correctly configured as open-drain with pull-up to +PS_3VSB through R33, and connected to power sequencing logic through D11 to enable downstream regulator U20.
2	EN	+V1P0A_ENABLE	✅	EN input is correctly pulled up to +5VSB through R32 (4.7K), with optional pull-down R31 marked DNI, and decoupled by C20 (0.1uF).
3	VIN	+PS_3VSB	✅	VIN and VDD inputs are both correctly connected to +PS_3VSB supply rail with adequate input decoupling capacitors.
4	VDD	+PS_3VSB	✅	VIN and VDD inputs are both correctly connected to +PS_3VSB supply rail with adequate input decoupling capacitors.
5	NC		✅	NC pin is correctly left unconnected as specified.
6	VOUT	+V1P0A	✅	VOUT is correctly connected to +V1P0A output rail with appropriate output capacitors C21 (22uF) and C22 (0.1uF) for stability and filtering.
7	ADJ	+V1P0A_FB	✅	ADJ feedback pin is correctly connected to resistor divider network (R34=6.04K, R35=23.7K) that sets output voltage to 1.004V, matching the intended 1.0V rail.
8	GND1	GND	✅	GND1 and GND2 (thermal pad) are both correctly connected to ground plane.
9	GND2	GND	✅	GND1 and GND2 (thermal pad) are both correctly connected to ground plane.

R134 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	1K resistor correctly connected between V1P0S_PG and gate of Q5 (1P35V_EN) to provide gate drive current limiting.
2	2	1P35V_EN	✅	1K resistor correctly connected between V1P0S_PG and gate of Q5 (1P35V_EN) to provide gate drive current limiting.

R120 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	10K resistor correctly connected between +V1P35S and base of Q3A (1P35V_PWG) to provide base drive current for power sequencing logic.
2	2	1P35V_PWG	✅	10K resistor correctly connected between +V1P35S and base of Q3A (1P35V_PWG) to provide base drive current for power sequencing logic.

R125 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	4.7K pull-up resistor correctly connected between +VCC and 1P8V_EN to pull the enable signal high when Q3B is off.
2	2	1P8V_EN	✅	4.7K pull-up resistor correctly connected between +VCC and 1P8V_EN to pull the enable signal high when Q3B is off.

R126 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	4.7K pull-up resistor correctly connected between +5VSB and 1P5V_EN_B to pull the base of Q3B high when Q3A is off.
2	2	1P5V_EN_B	✅	4.7K pull-up resistor correctly connected between +5VSB and 1P5V_EN_B to pull the base of Q3B high when Q3A is off.

Q5 - RXR035N03 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+VDIMM	✅	Drain is connected to +VDIMM input power rail, which is correct for a high-side switch configuration.
G	GATE	1P35V_EN	✅	Gate is driven by 1P35V_EN signal through R134 from V1P0S_PG power-good output. Gate voltage should be sufficient to turn on the MOSFET for high-side switching.
S	SOURCE	+V1P35S	✅	Source is connected to +V1P35S output rail (1.35V nominal), which is correct for a high-side switch providing regulated output.

Q3 - MBT3904 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter E1 is correctly connected to GND for common-emitter NPN transistor configuration.
2	B1	1P35V_PWG	✅	Base B1 is driven by 1P35V_PWG signal, which is pulled up to +V1P35S through R120 to control transistor 1.
3	C2	1P8V_EN	✅	Collector C2 of transistor 2 is connected to 1P8V_EN, pulling it low when transistor 2 is on.
4	E2	GND	✅	Emitter E2 is correctly connected to GND for common-emitter NPN transistor configuration.
5	B2	1P5V_EN_B	✅	Base B2 is driven by 1P5V_EN_B signal to control transistor 2 in the power sequencing logic.
6	C1	1P5V_EN_B	✅	Collector C1 of transistor 1 is connected to 1P5V_EN_B, pulling it low when transistor 1 is on to implement inverter logic.

Q1 - 132-0004425 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter of first NPN transistor, correctly connected to ground.
2	B1	PSGOOD	✅	Base of first NPN transistor, correctly connected to PSGOOD signal for switching control.
3	C2	SYS_PWRGD	✅	Collector of second NPN transistor, correctly connected to SYS_PWRGD output signal.
4	E2	GND	✅	Emitter of second NPN transistor, correctly connected to ground.
5	B2	PSPUP	✅	Base of second NPN transistor, correctly connected to PSPUP for cascaded switching.
6	C1	PSPUP	✅	Collector of first NPN transistor, correctly connected to PSPUP to drive the second transistor stage.

D11 - 130-0004403 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	Cathode of first diode in common-anode dual Schottky, correctly connected to +V1P0A_PWRGD for AND gate function.
2	2	SLP_S3_L	✅	Cathode of second diode in common-anode dual Schottky, correctly connected to SLP_S3_L for AND gate function.
3	3	PSGOOD	✅	Common anode of dual Schottky diode, correctly connected to PSGOOD with pull-up and delay capacitor.

FB7 - 110-0002124 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Pin 1 connects to +VCC3, the main 3.3V supply rail. This is the input side of the 0-ohm jumper.
2	2	+VCC3S	✅	Pin 2 connects to +VCC3S, a dedicated 3.3V supply for the CPU. This is the output side of the 0-ohm jumper that isolates the CPU supply for monitoring or filtering.

📤 Upload Missing Datasheets

DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews.

• R151, R192, R216, R22, R306, R353, R354, R41, R42, R43, R46, R48, R51, R72, R73, R74, R809 (110-0001853): 📤 Upload a datasheet
• R147 (110-0001859): 📤 Upload a datasheet
• R102, R112, R114, R116, R120, R189, R190, R191, R2, R209, R210, R211, R219, R220, R221, R260, R266, R267, R268, R28, R29, R30, R31, R319, R400, R71, R75, R84, R97 (110-0001875): 📤 Upload a datasheet
• R134, R208, R233, R234, R259, R401, R94 (110-0001923): 📤 Upload a datasheet
• R206 (110-0001951): 📤 Upload a datasheet
• R60, R61 (110-0001957): 📤 Upload a datasheet
• R179 (110-0001960): 📤 Upload a datasheet
• R11, R12, R269, R270 (110-0001967): 📤 Upload a datasheet
• R140, R327 (110-0001971): 📤 Upload a datasheet
• R115, R117, R171, R172, R177, R257, R44, R45, R47, R49, R52 (110-0001984): 📤 Upload a datasheet
• R819 (110-0002000): 📤 Upload a datasheet
• R136 (110-0002029): 📤 Upload a datasheet
• R125, R126, R144, R23, R310, R32, R325, R326, R33 (110-0002058): 📤 Upload a datasheet
• FB7, R152, R222, R265, R275, R818 (110-0002124): 📤 Upload a datasheet
• R150, R24 (110-0002560): 📤 Upload a datasheet
• R213, R38, R39 (110-0002631): 📤 Upload a datasheet
• R153 (110-0002726): 📤 Upload a datasheet
• R240, R241, R242, R258 (110-0003059): 📤 Upload a datasheet
• R34 (110-0003781): 📤 Upload a datasheet
• R185, R77 (110-0004472): 📤 Upload a datasheet
• R255 (110-0004474): 📤 Upload a datasheet
• R217, R218, R239 (110-0004476): 📤 Upload a datasheet
• R212 (110-0004478): 📤 Upload a datasheet
• R25 (110-0004490): 📤 Upload a datasheet
• R35 (110-0004494): 📤 Upload a datasheet
• R135 (110-0004498): 📤 Upload a datasheet
• R40 (110-0004695): 📤 Upload a datasheet
• R832, R833, R834, R835 (1120-0003): 📤 Upload a datasheet
• R837, R838, R839 (1120-0010): 📤 Upload a datasheet
• R820, R821, R822, R823, R824, R825, R826, R827, R828, R830, R831 (1120-0011): 📤 Upload a datasheet
• R836 (1120-0018): 📤 Upload a datasheet
• R320 (1120-0022): 📤 Upload a datasheet
• R801, R802, R803, R804, R805, R806, R807, R808 (1120-0119): 📤 Upload a datasheet
• R843, R844 (1120-0203): 📤 Upload a datasheet
• R848 (1120-0359): 📤 Upload a datasheet
• R840, R841, R842 (1121-0001): 📤 Upload a datasheet
• R155, R156, R157, R173, R174, R180, R182 (1121-0011): 📤 Upload a datasheet
• C10, C11, C12, C13, C177, C178, C179, C180 (123-0001038): 📤 Upload a datasheet
• C124, C133, C191, C192, C205, C206, C207, C208, C329, C344, C65 (123-0001056): 📤 Upload a datasheet
• C374 (123-0001076): 📤 Upload a datasheet
• C23, C9 (123-0001079): 📤 Upload a datasheet
• C152 (123-0001102): 📤 Upload a datasheet
• C119 (123-0001107): 📤 Upload a datasheet
• C103, C164, C201, C224, C225, C91 (123-0001176): 📤 Upload a datasheet
• C148, C211 (123-0004408): 📤 Upload a datasheet
• C110, C111, C134, C135, C145, C146, C318, C319, C363, C364, C369, C370 (123-0004765): 📤 Upload a datasheet
• C76, C77, C87 (123-0005035): 📤 Upload a datasheet
• L3 (125-0004501): 📤 Upload a datasheet
• FB3 (126-0001423): 📤 Upload a datasheet
• L11 (126-0004454): 📤 Upload a datasheet
• FB4, FB5, L5, L6 (126-0004457): 📤 Upload a datasheet
• D11, D3 (130-0004403): 📤 Upload a datasheet
• U38 (140-0004525): 📤 Upload a datasheet
• U21, U24 (140-0004526): 📤 Upload a datasheet
• Y1 (145-0004789): 📤 Upload a datasheet
• X1, Y2 (145-0004792): 📤 Upload a datasheet
• P1 (158-0004513): 📤 Upload a datasheet
• C429, C430, C431 (2220-0039): 📤 Upload a datasheet
• C425 (2221-0017): 📤 Upload a datasheet
• C428 (2222-0014): 📤 Upload a datasheet
• C426, C427 (2222-0016): 📤 Upload a datasheet
• C159, C162, C28, C360, C419, C420, C421, C422, C423, C424 (2232-0012): 📤 Upload a datasheet
• C161 (2267-0004): 📤 Upload a datasheet
• J5, J6, J7 (258-0002513): 📤 Upload a datasheet
• USB1 (258-0004503): 📤 Upload a datasheet
• J1 (258-0004612): 📤 Upload a datasheet
• J4 (258-0004869): 📤 Upload a datasheet
• JP1 (258-0005019): 📤 Upload a datasheet
• FB12 (3044-0010): 📤 Upload a datasheet
• FB13 (3044-0012): 📤 Upload a datasheet
• L8 (3120-0183): 📤 Upload a datasheet
• L18, L4 (3120-0266): 📤 Upload a datasheet
• CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17 (3142-0014): 📤 Upload a datasheet
• J11 (3362-0042): 📤 Upload a datasheet
• J8 (3430-0212): 📤 Upload a datasheet
• BH1 (353-0003073): 📤 Upload a datasheet
• FL1 (3750-0010): 📤 Upload a datasheet
• SW1 (3770-0026): 📤 Upload a datasheet
• TH1, TH2, TH3, TH4 (3880-0004): 📤 Upload a datasheet
• U42 (4300-0071): 📤 Upload a datasheet
• U19 (4327-0010): 📤 Upload a datasheet
• D10, D5 (4536-0009): 📤 Upload a datasheet
• D1, D2 (4560-0045): 📤 Upload a datasheet
• D13 (4620-0026): 📤 Upload a datasheet
• J10 (5177985-2): 📤 Upload a datasheet
• TP11, TP12 (999-0000002): 📤 Upload a datasheet
• TP1, TP17, TP18, TP2 (999-0000003): 📤 Upload a datasheet
• SP1, SP2, SP3, SP4 (999-0000005): 📤 Upload a datasheet
• D4, D6 (BAT54A-S): 📤 Upload a datasheet
• D8 (BAT754C): 📤 Upload a datasheet
• Q2, Q9 (BAV99-7-F-S-X): 📤 Upload a datasheet
• L1, L2 (BKP2125HS221-T): 📤 Upload a datasheet
• U25, U26 (NCP81109GMNTXG): 📤 Upload a datasheet
• U35 (NCT3012S-X): 📤 Upload a datasheet
• U18 (NTB0104GU12): 📤 Upload a datasheet
• U4, U5, U6, U7 (NTS0102GT): 📤 Upload a datasheet
• U10, U14, U15, U16, U17 (NTS0104GU12): 📤 Upload a datasheet
• P2 (SCHA5B0200): 📤 Upload a datasheet
• U29 (TPD4USB30): 📤 Upload a datasheet

_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 448 component(s) to review, and found 12 potential issue(s) in 12 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary><b>Component Details</b></summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AK12 | DDI0_RCOMP_P | DDI_RCOMP_N | ❌ | <details><summary>DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P, positive) is connected to DDI_RCOMP_N net, and pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅, negative) is connected to DDI_RCOMP_P net. These connections should be reversed.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,31.55,45.57,39.05" aspect-ratio="1.29" } <ul><li>Pin AK12 is named DDI0_RCOMP_P (positive) in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>Pin AK13 is named DDI_RCOMP_N (negative) in the datasheet, shown with overline in schematic as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>Pin AK12 connects to net DDI_RCOMP_N in the schematic <em>(from schematic)</em></li><li>Pin AK13 connects to net DDI_RCOMP_P in the schematic <em>(from schematic)</em></li><li>Compensation resistor R217 (402 ohms) connects between DDI_RCOMP_N and DDI_RCOMP_P nets <em>(from schematic)</em></li><li>For differential compensation resistors, the positive pin should connect to the positive side and negative pin to the negative side <em>(reasoning)</em></li><li>The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) <em>(reasoning)</em></li><li>The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) <em>(reasoning)</em></li><li>The pins are swapped and should be corrected: AK12 should connect to DDI_RCOMP_P and AK13 should connect to DDI_RCOMP_N <em>(reasoning)</em></li></ul></details> | | AK13 | ~DDI0_RCOMP | DDI_RCOMP_P | ❌ | <details><summary>DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P, positive) is connected to DDI_RCOMP_N net, and pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅, negative) is connected to DDI_RCOMP_P net. These connections should be reversed.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,38.46" aspect-ratio="1.29" } <ul><li>Pin AK12 is named DDI0_RCOMP_P (positive) in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>Pin AK13 is named DDI_RCOMP_N (negative) in the datasheet, shown with overline in schematic as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>Pin AK12 connects to net DDI_RCOMP_N in the schematic <em>(from schematic)</em></li><li>Pin AK13 connects to net DDI_RCOMP_P in the schematic <em>(from schematic)</em></li><li>Compensation resistor R217 (402 ohms) connects between DDI_RCOMP_N and DDI_RCOMP_P nets <em>(from schematic)</em></li><li>For differential compensation resistors, the positive pin should connect to the positive side and negative pin to the negative side <em>(reasoning)</em></li><li>The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) <em>(reasoning)</em></li><li>The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) <em>(reasoning)</em></li><li>The pins are swapped and should be corrected: AK12 should connect to DDI_RCOMP_P and AK13 should connect to DDI_RCOMP_N <em>(reasoning)</em></li></ul></details> | | A29 | RESERVED_A29 | GPIO_NC13 | ✅ | RESERVED_A29 pin connected to GPIO_NC13 net with 10K pull-down resistor R102 to ground. This configuration is correct for an unused/reserved GPIO pin. | | B26 | DDI0_BKLTCTL | | ✅ | DDI0 control pins (BKLTCTL, VDDEN, BKLTEN) are unconnected. This may be acceptable if backlight and panel power control are handled externally or not needed for HDMI. | | B28 | DDI0_VDDEN | | ✅ | DDI0 control pins (BKLTCTL, VDDEN, BKLTEN) are unconnected. This may be acceptable if backlight and panel power control are handled externally or not needed for HDMI. | | C27 | DDI0_BKLTEN | | ✅ | DDI0 control pins (BKLTCTL, VDDEN, BKLTEN) are unconnected. This may be acceptable if backlight and panel power control are handled externally or not needed for HDMI. | | B30 | GPIO_S0_NC12 | $3N566 | ✅ | GPIO_S0_NC12 pin connected to test point TP15 (DNI). This is correct for a test point on a GPIO pin. | | C26 | DDI0_DDCDATA | HDMI_DDCDAT | ✅ | DDI0 DDC pins (DDCDATA, DDCCLK) connected to HDMI DDC signals (HDMI_DDCDAT, HDMI_DDCCLK). This is correct for HDMI DDC/EDID communication. | | C28 | DDI0_DDCCLK | HDMI_DDCCLK | ✅ | DDI0 DDC pins (DDCDATA, DDCCLK) connected to HDMI DDC signals (HDMI_DDCDAT, HDMI_DDCCLK). This is correct for HDMI DDC/EDID communication. | | D27 | DDI0_HPD | HDMI_HPD_B | ✅ | DDI0_HPD pin connected to HDMI_HPD_B (inverted hot plug detect signal from U39). This is correct. | | G30 | DDI1_DDCCLK | GND | ✅ | DDI1 control pins. DDCCLK and HPD are tied to ground, DDCDATA has 2.2K pull-down through R257. This correctly disables the DDI1 interface. | | K30 | DDI1_HPD | GND | ✅ | DDI1 control pins. DDCCLK and HPD are tied to ground, DDCDATA has 2.2K pull-down through R257. This correctly disables the DDI1 interface. | | P30 | DDI1_DDCDATA | DDI1_DDCDAT | ✅ | DDI1 control pins. DDCCLK and HPD are tied to ground, DDCDATA has 2.2K pull-down through R257. This correctly disables the DDI1 interface. | | J30 | DDI1_BKLTEN | | ✅ | DDI1 control pins (BKLTEN, BKLTCTL, VDDEN) are unconnected. This is correct as DDI1 interface is disabled. | | M30 | DDI1_BKLTCTL | | ✅ | DDI1 control pins (BKLTEN, BKLTCTL, VDDEN) are unconnected. This is correct as DDI1 interface is disabled. | | N30 | DDI1_VDDEN | | ✅ | DDI1 control pins (BKLTEN, BKLTCTL, VDDEN) are unconnected. This is correct as DDI1 interface is disabled. | | P14 | RESERVED_P14 | MCSI_RCOMP | ✅ | MCSI_RCOMP pin connected through 150-ohm resistor R213 to ground. This provides compensation for the MIPI camera interface and is correct. | | AB2 | RESERVED_AB2 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AB3 | RESERVED_AB3 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AB7 | RESERVED_AB7 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AB9 | RESERVED_AB9 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AB12 | RESERVED_AB12 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AB13 | RESERVED_AB13 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AB14 | RESERVED_AB14 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AD4 | RESERVED_AD4 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AD6 | RESERVED_AD6 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AF13 | RESERVED_AF13 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AF14 | RESERVED_AF14 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AH13 | RESERVED_AH13 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AH14 | RESERVED_AH14 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AM13 | RESERVED_AM13 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AM14 | RESERVED_AM14 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | C29 | RESERVED_C29 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | C30 | RESERVED_C30 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | D28 | RESERVED_D28 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | D32 | RESERVED_D32 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | D34 | RESERVED_D34 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | F28 | RESERVED_F28 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | F32 | RESERVED_F32 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | F34 | RESERVED_F34 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | J28 | RESERVED_J28 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | J34 | RESERVED_J34 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | K28 | RESERVED_K28 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | K34 | RESERVED_K34 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | M32 | RESERVED_M32 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | N32 | RESERVED_N32 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | R1 | RESERVED_R1 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | R3 | RESERVED_R3 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T2 | RESERVED_T2 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T3 | RESERVED_T3 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T4 | RESERVED_T4 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T6 | RESERVED_T6 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T7 | RESERVED_T7 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T9 | RESERVED_T9 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T10 | RESERVED_T10 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T12 | RESERVED_T12 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T13 | RESERVED_T13 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | T14 | RESERVED_T14 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V2 | RESERVED_V2 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V3 | RESERVED_V3 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V4 | RESERVED_V4 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V6 | RESERVED_V6 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V9 | RESERVED_V9 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V10 | RESERVED_V10 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V13 | RESERVED_V13 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | V14 | RESERVED_V14 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | W1 | RESERVED_W1 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | W3 | RESERVED_W3 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | Y2 | RESERVED_Y2 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | Y3 | RESERVED_Y3 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | Y4 | RESERVED_Y4 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | Y6 | RESERVED_Y6 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | Y12 | RESERVED_Y12 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | Y13 | RESERVED_Y13 | | ✅ | Reserved pins listed in schematic but not connected on this page. These are likely connected elsewhere in the design or intentionally left unconnected. | | AC1 | DDI1_TXN_3 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AC3 | DDI1_TXP_3 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AD2 | DDI1_TXN_2 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AD3 | DDI1_TXP_2 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AF2 | DDI1_TXN_1 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AF3 | DDI1_TXP_1 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AG1 | DDI1_TXN_0 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AG3 | DDI1_TXP_0 | | ✅ | DDI1 transmit pins (DDI1_TXN_3, DDI1_TXP_3, DDI1_TXN_2, DDI1_TXP_2, DDI1_TXN_1, DDI1_TXP_1, DDI1_TXN_0, DDI1_TXP_0) are left unconnected. This is correct as DDI1 interface is disabled per design note 'Bay Trail-M Remove eDP Port'. | | AH2 | RESERVED_VSS3 | $3N554 | ✅ | Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct. | | AH3 | RESERVED_VSS2 | $3N552 | ✅ | Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct. | | AM2 | RESERVED_VSS1 | $3N589 | ✅ | Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct. | | AM3 | RESERVED_VSS0 | $3N579 | ✅ | Reserved ground pins (RSVD_GND[3], RSVD_GND[2], RESERVED_VSS1, RESERVED_VSS0) are connected to ground through 0-ohm resistors R43, R46, R41, R42 respectively. This is correct. | | AK2 | DDI1_AUXN | | ✅ | DDI1 auxiliary pins (DDI1_AUXN, DDI1_AUXP) are left unconnected. This is correct as DDI1 interface is disabled. | | AK3 | DDI1_AUXP | | ✅ | DDI1 auxiliary pins (DDI1_AUXN, DDI1_AUXP) are left unconnected. This is correct as DDI1 interface is disabled. | | AL1 | DDI0_AUXN | | ✅ | DDI0 auxiliary pins (DDI0_AUXN, DDI0_AUXP) are left unconnected. This is acceptable as HDMI does not use auxiliary channel (used for DisplayPort). | | AL3 | DDI0_AUXP | | ✅ | DDI0 auxiliary pins (DDI0_AUXN, DDI0_AUXP) are left unconnected. This is acceptable as HDMI does not use auxiliary channel (used for DisplayPort). | | AP2 | DDI0_TXN_3 | HDMI_CLK_DN | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AP3 | DDI0_TXP_3 | HDMI_CLK_DP | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AR1 | DDI0_TXN_2 | HDMI_TX0_DN | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AR3 | DDI0_TXP_2 | HDMI_TX0_DP | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AT2 | DDI0_TXP_1 | HDMI_TX1_DP | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AT3 | DDI0_TXN_1 | HDMI_TX1_DN | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AV2 | DDI0_TXN_0 | HDMI_TX2_DN | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AV3 | DDI0_TXP_0 | HDMI_TX2_DP | ✅ | DDI0 transmit pins connected to HDMI signals with intentional bit order reversal. TX0→HDMI_TX2, TX1→HDMI_TX1, TX2→HDMI_TX0, TX3→HDMI_CLK. This is correct per design note. | | AW1 | VGA_IREF | $3N548 | ✅ | VGA_IREF pin connected through 357-ohm resistor R40 to ground. This sets the VGA DAC reference current and is correct. | | AY2 | VGA_BLUE | | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | | AY3 | VGA_IRTN | GND | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | | BA1 | VGA_GREEN | | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | | BA3 | VGA_RED | | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | | BC1 | VGA_DDCCLK | CRT_CLK | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | | BC2 | VGA_DDCDATA | CRT_DAT | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | | BD2 | VGA_HSYNC | | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | | BF2 | VGA_VSYNC | | ✅ | VGA interface pins. Video outputs (BLUE, RED, GREEN, HSYNC, VSYNC) are unconnected. DDC pins (DDCCLK, DDCDATA) have 150-ohm resistors to ground. IRTN is grounded. VGA interface appears unused, configuration is acceptable. | </details> <details> <summary><b>U39</b> - SN74LVC1G14DCKR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf?ts=1753365169590&ref_url=https%25253A%25252F%25252Fwww.ti.com%25252Fproduct%25252FSN74LVC1G14) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/SN74LVC1G14DCKR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin is left unconnected in the schematic. This is acceptable per the datasheet which states the pin has no internal connection. | | 2 | A | HDMI_HPD | ✅ | Input pin A is correctly connected to HDMI_HPD signal for Schmitt-trigger conditioning of the HDMI Hot Plug Detect signal. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | HDMI_HPD_B | ✅ | Output pin Y is correctly connected to HDMI_HPD_B which drives the CPU's DDI0_HPD input, providing an inverted and conditioned HDMI Hot Plug Detect signal. | | 5 | VCC | +V1P8S | ✅ | VCC power pin is correctly connected to +V1P8S (1.8V supply), which is within the specified 1.65V to 5.5V operating range. A 0.1uF bypass capacitor (C375) is present on this power rail. | </details> <details> <summary><b>R38</b> - 110-0002631 ❌</summary> DRCY flagged 2 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_DAT | ❌ | <details><summary>Pin 1 connects to CRT_DAT (VGA_DDCDATA from CPU1 pin BC2), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,40.96,76.02,48.46" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_DAT <em>(from schematic)</em></li><li>Net CRT_DAT connects to CPU1 pin BC2, which is labeled VGA_DDCDATA <em>(from schematic)</em></li><li>Pin 2 connects to GND, creating a 150Ω pull-down configuration <em>(from schematic)</em></li><li>VGA_DDCDATA is the I2C SDA (data) line for the VGA Display Data Channel (DDC) interface <em>(reasoning)</em></li><li>DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground <em>(reasoning)</em></li><li>Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements <em>(reasoning)</em></li><li>A 150Ω pull-down resistor would pull the DDC data line low and prevent proper I2C communication by fighting against the required pull-up <em>(reasoning)</em></li><li>This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional <em>(reasoning)</em></li><li>The same issue affects R39 on the CRT_CLK line, indicating a systematic problem with the VGA DDC interface design <em>(reasoning)</em></li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>Connected to GND, creating a 150 ohm pull-down on the VGA DDC data line. This is incorrect for I2C/DDC operation which requires pull-up resistors.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,40.96,76.93,48.46" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to GND <em>(from schematic)</em></li><li>This creates a 150 ohm pull-down resistor on the VGA_DDCDATA signal <em>(reasoning)</em></li><li>I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors <em>(reasoning)</em></li><li>A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication <em>(reasoning)</em></li><li>This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R39</b> - 110-0002631 ❌</summary> DRCY flagged 2 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_CLK | ❌ | <details><summary>Pin 1 connects to CRT_CLK (VGA_DDCCLK from CPU1 pin BC1), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,39.19,76.02,46.69" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_CLK <em>(from schematic)</em></li><li>Net CRT_CLK connects to CPU1 pin BC1, which is labeled VGA_DDCCLK <em>(from schematic)</em></li><li>Pin 2 connects to GND, creating a 150Ω pull-down configuration <em>(from schematic)</em></li><li>VGA_DDCCLK is the I2C SCL (clock) line for the VGA Display Data Channel (DDC) interface <em>(reasoning)</em></li><li>DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground <em>(reasoning)</em></li><li>Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements <em>(reasoning)</em></li><li>A 150Ω pull-down resistor would pull the DDC clock line low and prevent proper I2C communication by fighting against the required pull-up <em>(reasoning)</em></li><li>This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional <em>(reasoning)</em></li><li>The same issue affects R38 on the CRT_DAT line, indicating a systematic problem with the VGA DDC interface design <em>(reasoning)</em></li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>Connected to GND, creating a 150 ohm pull-down on the VGA DDC clock line. This is incorrect for I2C/DDC operation which requires pull-up resistors.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,39.19,76.93,46.69" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to GND <em>(from schematic)</em></li><li>This creates a 150 ohm pull-down resistor on the VGA_DDCCLK signal <em>(reasoning)</em></li><li>I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors <em>(reasoning)</em></li><li>A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication <em>(reasoning)</em></li><li>This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R213</b> - 110-0002631 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCSI_RCOMP | ✅ | Connected to MCSI_RCOMP net, which connects to CPU1 pin P14 (marked as RESERVED_P14 but used for MCSI compensation on Bay Trail-I variant). | | 2 | 2 | GND | ✅ | Connected to GND, forming a compensation resistor configuration where MCSI_RCOMP is terminated to ground through 150 ohms. | </details> <details> <summary><b>R217</b> - 110-0004476 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI_RCOMP_N | ✅ | 402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming a compensation resistor for the DDI0 interface. The net naming appears swapped relative to CPU pin naming conventions, but this does not affect electrical functionality. | | 2 | 2 | DDI_RCOMP_P | ✅ | 402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming a compensation resistor for the DDI0 interface. The net naming appears swapped relative to CPU pin naming conventions, but this does not affect electrical functionality. | </details> <details> <summary><b>R46</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N552 | ✅ | Pin 1 connects to CPU1 pin AH3 (RESERVED_VSS2) through net $3N552. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, completing the connection from CPU1 RESERVED_VSS2 pin to ground. | </details> <details> <summary><b>R43</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N554 | ✅ | Pin 1 connects to CPU1 pin AH2 (RESERVED_VSS3) through net $3N554. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, completing the connection from CPU1 RESERVED_VSS3 pin to ground. | </details> <details> <summary><b>R42</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This is one side of a 0-ohm resistor connecting CPU1 RESERVED_VSS0 pin to ground. | | 2 | 2 | $3N579 | ✅ | Pin 2 connects to CPU1 pin AM3 (RESERVED_VSS0) through net $3N579. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor. | </details> <details> <summary><b>R41</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This is one side of a 0-ohm resistor connecting CPU1 RESERVED_VSS1 pin to ground. | | 2 | 2 | $3N589 | ✅ | Pin 2 connects to CPU1 pin AM2 (RESERVED_VSS1) through net $3N589. This is a reserved ground pin on the CPU being connected to GND through a 0-ohm resistor. | </details> <details> <summary><b>R102</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 10K ohm pull-down resistor on GPIO_NC13 (CPU1 pin A29). Provides a defined logic low level for this reserved GPIO pin. | | 2 | 2 | GPIO_NC13 | ✅ | 10K ohm pull-down resistor on GPIO_NC13 (CPU1 pin A29). Provides a defined logic low level for this reserved GPIO pin. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C24 | ~PROCHOT | VR_HOT_L | ✅ | PROCHOT# is connected with 73.2 ohm resistor R255 to +V1P0S for thermal management. | | BA12 | SATA_GP0 | SATA_GP0 | ✅ | SATA_GP0 is connected with 10K pull-down resistor R220 to ground. | | BA16 | SATA_RXN_1 | SATA1_RXN | ✅ | SATA_RXN_1 is connected through AC coupling capacitor C177 from mSATA interface. | | BA26 | SD3_D3 | SD3_D3 | ✅ | SD3_D3 is connected to SD Card 3 data bit 3 signal. | | BA30 | LPE_I2S2_FRM | LPE_I2S_FRM | ✅ | LPE_I2S2_FRM is connected to I2S frame signal with 10K pull-up resistor R268. | | BB5 | RESERVED_VSS6 | RESERVED_VSS6 | ✅ | RESERVED_VSS6 pin is grounded through R72 as required for reserved VSS pins. | | BB7 | RESERVED_VSS7 | RESERVED_VSS7 | ✅ | RESERVED_VSS7 pin is grounded through R192 as required for reserved VSS pins. | | BB10 | RESERVED_VSS4 | ICLK_SATA_TERMP | ✅ | RESERVED_VSS4 pin is connected to ICLK_SATA_TERMP and grounded through R73 for integrated clock SATA termination. | | BC10 | RESERVED_VSS5 | ICLK_SATA_TERMN | ✅ | RESERVED_VSS5 pin is connected to ICLK_SATA_TERMN and grounded through R74 for integrated clock SATA termination. | | BC12 | | | ✅ | GPIO strapping pin with both pull-up and pull-down resistor options (both DNI), providing hardware configuration flexibility. | | BC24 | SD3_CD# | SD3_CD# | ✅ | SD3_CD# (card detect) and SD3_WP (write protect) are connected together through 0-ohm resistor R354. This is a Bay Trail-I specific configuration as indicated by schematic annotation, though it represents an unusual design choice that ties two functionally independent SD card signals together. | | BD5 | SD3_WP_BD5 | SD3_WP | ✅ | SD3_CD# (card detect) and SD3_WP (write protect) are connected together through 0-ohm resistor R354. This is a Bay Trail-I specific configuration as indicated by schematic annotation, though it represents an unusual design choice that ties two functionally independent SD card signals together. | | BC30 | LPE_I2S2_DATAOUT | LPE_I2S_DATOUT | ✅ | LPE_I2S2_DATAOUT is connected to I2S data output with optional GPIO configuration. | | BD7 | ~PCIE_CLKREQ_1 | CLKREQ1_B | ✅ | PCIE_CLKREQ_1# is connected with 10K pull-up resistor R190 for PCIe clock request. | | BD10 | SATA_TXP1 | SATA1_TXP | ✅ | SATA_TXP1 is connected through AC coupling capacitor C179 to mSATA interface. | | BD22 | ~SD3_PWREN | /SD3+PWREN | ✅ | SD3_PWREN# is connected to power enable signal with test point TP11. | | BD26 | SD3_D1 | SD3_D1 | ✅ | SD3_D1 is connected to SD Card 3 data bit 1 signal. | | BD28 | LPE_I2S2_DATAIN | LPE_I2S_DATIN | ✅ | LPE_I2S2_DATAIN is connected to I2S data input signal. | | BE3 | ~PCIE_CLKREQ_3 | mPCIe_CLKREQ3_B | ✅ | PCIE_CLKREQ_3# is connected with 10K pull-up resistor R2 for mini PCIe clock request. | | BF6 | SATA_TXP_0 | SATA0_TXP | ✅ | SATA_TXP_0 is connected through AC coupling capacitor C10 to SATA connector for SATA port 0 transmit. | | BF10 | SATA_TXN_1 | SATA1_TXN | ✅ | SATA_TXN_1 is connected through AC coupling capacitor C180 to mSATA interface. | | BF20 | HDA_LPE_RCOMP | HDA_RCOMP | ✅ | HDA_LPE_RCOMP is connected with 49.9 ohm resistor R242 to ground for HD Audio compensation. | | BF22 | SD3_1P8EN | SD3_1P8EN | ✅ | SD3_1P8EN is connected to 1.8V enable signal with test point TP12. | | BF26 | SD3_RCOMP | SD3_RCOMP | ✅ | SD3_RCOMP is connected with 49.9 ohm resistor R258 to ground for SD Card compensation. | | BF28 | LPE_I2S2_CLK | LPE_I2S_CLK | ✅ | LPE_I2S2_CLK is connected to I2S clock signal. | | BG3 | ~PCIE_CLKREQ_0 | CLKREQ0_B | ✅ | PCIE_CLKREQ_0# is connected with 10K pull-up resistor R191 for PCIe clock request. | | BG5 | ~PCIE_CLKREQ_2 | LAN_CLKREQ2_B | ✅ | PCIE_CLKREQ_2# is connected with 10K pull-up resistor R71 for LAN PCIe clock request. | | BG7 | SATA_TXN_0 | SATA0_TXN | ✅ | SATA_TXN_0 is connected through AC coupling capacitor C11 to SATA connector for SATA port 0 transmit. | | BG18 | GPIO_S0_SC_15 | | ✅ | GPIO_S0_SC_14 and GPIO_S0_SC_15 are unconnected GPIO pins. | | BH18 | GPIO_S0_SC_14 | | ✅ | GPIO_S0_SC_14 and GPIO_S0_SC_15 are unconnected GPIO pins. | | BG19 | HDA_SDI0 | | ✅ | HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design. | | BG20 | HDA_SDO | | ✅ | HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design. | | BG21 | HDA_SDI1 | | ✅ | HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design. | | BG22 | ~HDA_RST | | ✅ | HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design. | | BH20 | HDA_SYNC | | ✅ | HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design. | | BJ21 | HDA_CLK | | ✅ | HD Audio interface pins are unconnected, indicating HD Audio is not implemented in this design. | | AK7 | RESERVED_AK7 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AK9 | RESERVED_AK9 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AV10 | RESERVED_AV10 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AV9 | RESERVED_AV9 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | BB3 | RESERVED_BB3 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | BB4 | RESERVED_BB4 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | N34 | RESERVED_N34 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | P34 | RESERVED_P34 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AP4 | PCIE_TXN_3 | mPCIE_TX_N | ✅ | PCIE_TXN_3 is connected to net mPCIE_TX_N for mini PCIe transmit path. | | AP6 | PCIE_TXP_3 | mPCIE_TX_P | ✅ | PCIE_TXP_3 is connected to net mPCIE_TX_P for mini PCIe transmit path. | | AP7 | PCIE_RXN_3 | mPCIE_RX_N | ✅ | PCIE_RXN_3 is connected to net mPCIE_RX_N for mini PCIe receive path. | | AP9 | PCIE_RXP_3 | mPCIE_RX_P | ✅ | PCIE_RXP_3 is connected to net mPCIE_RX_P for mini PCIe receive path. | | AP10 | PCIE_RXN_2 | PCIE_RXN2 | ✅ | PCIE_RXN_2 is connected to net PCIE_RXN2 for PCIe lane 2 receive path. | | AP12 | PCIE_RXP_2 | PCIE_RXP2 | ✅ | PCIE_RXP_2 is connected to net PCIE_RXP2 for PCIe lane 2 receive path. | | AP13 | PCIE_RCOMP_N_AP13_AP13 | PCIE_RCOMP_N | ✅ | PCIE_RCOMP_N is connected to a 402 ohm resistor (R218) to PCIE_RCOMP_P for PCIe compensation. | | AP14 | PCIE_RCOMP_P_AP14_AP14 | PCIE_RCOMP_P | ✅ | PCIE_RCOMP_P is connected to a 402 ohm resistor (R218) to PCIE_RCOMP_N for PCIe compensation. | | AT6 | PCIE_TXN_2 | PCIE_TXN2 | ✅ | PCIE_TXN_2 is connected to net PCIE_TXN2 for PCIe lane 2 transmit path. | | AT7 | PCIE_TXP_2 | PCIE_TXP2 | ✅ | PCIE_TXP_2 is connected to net PCIE_TXP2 for PCIe lane 2 transmit path. | | AT10 | PCIE_RXP_1 | | ✅ | PCIe lane 1 receive pins are unconnected, indicating this lane is not implemented. | | AT9 | PCIE_RXN_1 | | ✅ | PCIe lane 1 receive pins are unconnected, indicating this lane is not implemented. | | AT13 | PCIE_RXN_0 | | ✅ | PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented. | | AT14 | PCIE_RXP_0 | | ✅ | PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented. | | AV4 | PCIE_TXN_1 | | ✅ | PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented. | | AV6 | PCIE_TXP_1 | | ✅ | PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented. | | AY6 | PCIE_TXN_0 | | ✅ | PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented. | | AY7 | PCIE_TXP_0 | | ✅ | PCIe lane 0 and lane 1 transmit/receive pins are unconnected, indicating these lanes are not implemented. | | AT18 | SATA_RCOMP_N_AT18 | SATA_RCOMP_N | ✅ | SATA_RCOMP_N is connected to a 402 ohm resistor (R239) to SATA_RCOMP_P for SATA compensation. | | AT20 | MMC1_D3 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AT22 | MMC1_CLK | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AT26 | MMC1_D6 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AU20 | MMC1_D7 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AU22 | MMC1_D1 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AU26 | MMC1_D5 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AV20 | MMC1_D0 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AV22 | MMC1_D2 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AV26 | MMC1_CMD | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AY24 | MMC1_D4 | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | BA24 | ~MMC1_RST | | ✅ | eMMC interface pins are unconnected, indicating eMMC is not implemented in this design. | | AT28 | SD3_D0 | SD3_D0 | ✅ | SD3_D0 is connected to SD Card 3 data bit 0 signal. | | AU16 | SATA_RXP_0 | SATA0_RXP | ✅ | SATA_RXP_0 is connected through AC coupling capacitor C13 to SATA connector for SATA port 0 receive. | | AU18 | SATA_RCOMP_P_AU18 | SATA_RCOMP_P | ✅ | SATA_RCOMP_P is connected to a 402 ohm resistor (R239) to SATA_RCOMP_N for SATA compensation. | | AU28 | SD3_D2 | SD3_D2 | ✅ | SD3_D2 is connected to SD Card 3 data bit 2 signal. | | AV16 | SATA_RXN_0 | SATA0_RXN | ✅ | SATA_RXN_0 is connected through AC coupling capacitor C12 to SATA connector for SATA port 0 receive. | | AV28 | SD3_CMD | SD3_CMD | ✅ | SD3_CMD is connected to SD Card 3 command signal. | | AY12 | ~SATA_LED | SATA_LED_B | ✅ | SATA_LED# is connected through current limiting resistor R179 to LED circuit with jumper J6. | | AY14 | SATA_GP1 | SATA_GP1 | ✅ | SATA_GP1 is connected with 10K pull-down resistor R221 to ground. | | AY16 | SATA_RXP_1 | SATA1_RXP | ✅ | SATA_RXP_1 is connected through AC coupling capacitor C178 from mSATA interface. | | AY18 | MMC1_RCOMP | MMC1_RCOMP | ✅ | MMC1_RCOMP is connected with 49.9 ohm resistor R240 to ground for eMMC compensation. | | AY20 | SD2_D0 | | ✅ | SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design. | | AY26 | SD3_CLK | SD3_CLK | ✅ | SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design. | | BA18 | SD2_CLK | | ✅ | SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design. | | BA20 | SD2_D2 | | ✅ | SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design. | | BC18 | SD2_CMD | | ✅ | SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design. | | BD18 | ~SD2_D3_CD | | ✅ | SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design. | | BD20 | SD2_D1 | | ✅ | SD Card 2 interface pins are unconnected, indicating SD2 is not implemented in this design. | </details> <details> <summary><b>C10</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXP_C | ✅ | Connector side of AC coupling capacitor for SATA0 TX positive differential signal. | | 2 | 2 | SATA0_TXP | ✅ | CPU side of AC coupling capacitor for SATA0 TX positive differential signal. | </details> <details> <summary><b>C11</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXN_C | ✅ | Connector side of AC coupling capacitor for SATA0 TX negative differential signal. | | 2 | 2 | SATA0_TXN | ✅ | CPU side of AC coupling capacitor for SATA0 TX negative differential signal. | </details> <details> <summary><b>C12</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXN_C | ✅ | Connector side of AC coupling capacitor for SATA0 RX negative differential signal. | | 2 | 2 | SATA0_RXN | ✅ | CPU side of AC coupling capacitor for SATA0 RX negative differential signal. | </details> <details> <summary><b>C13</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXP_C | ✅ | Connector side of AC coupling capacitor for SATA0 RX positive differential signal. | | 2 | 2 | SATA0_RXP | ✅ | CPU side of AC coupling capacitor for SATA0 RX positive differential signal. | </details> <details> <summary><b>C148</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0004408) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND_EARTH | ✅ | Chassis ground connection of optional EMI filtering Y-capacitor, marked DNI (Do Not Install). | | 2 | 2 | GND | ✅ | Signal ground connection of optional EMI filtering Y-capacitor, marked DNI (Do Not Install). | </details> <details> <summary><b>J3</b> - HDR_7POS_SER_GOLD_SATA_R/A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-67490-001.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0003610) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | 2 | SATA0_TXP_C | ✅ | Host transmit positive signal correctly connected through AC coupling capacitor C10 to CPU SATA_TXP_0 pin. | | 3 | 3 | SATA0_TXN_C | ✅ | Host transmit negative signal correctly connected through AC coupling capacitor C11 to CPU SATA_TXN_0 pin. | | 4 | 4 | GND | ✅ | Ground pin correctly connected to GND net. | | 5 | 5 | SATA0_RXN_C | ✅ | Host receive negative signal correctly connected through AC coupling capacitor C12 to CPU SATA_RXN_0 pin. | | 6 | 6 | SATA0_RXP_C | ✅ | Host receive positive signal correctly connected through AC coupling capacitor C13 to CPU SATA_RXP_0 pin. | | 7 | 7 | GND | ✅ | Ground pin correctly connected to GND net. | | MH1 | | | ✅ | Mounting hole correctly connected to chassis ground (GND_EARTH) for EMI shielding. | | MH2 | | | ✅ | Mounting hole correctly connected to chassis ground (GND_EARTH) for EMI shielding. | </details> <details> <summary><b>C177</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_N | ✅ | AC coupling capacitor for SATA1 RX negative differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces. | | 2 | 2 | SATA1_RXN | ✅ | AC coupling capacitor for SATA1 RX negative differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces. | </details> <details> <summary><b>C179</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_P | ✅ | AC coupling capacitor for SATA1 TX positive differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces. | | 2 | 2 | SATA1_TXP | ✅ | AC coupling capacitor for SATA1 TX positive differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces. | </details> <details> <summary><b>C178</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_P | ✅ | AC coupling capacitor for SATA1 RX positive differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces. | | 2 | 2 | SATA1_RXP | ✅ | AC coupling capacitor for SATA1 RX positive differential signal between mSATA connector and CPU. This is a standard configuration for SATA interfaces. | </details> <details> <summary><b>C180</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_N | ✅ | AC coupling capacitor for SATA1 TX negative differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces. | | 2 | 2 | SATA1_TXN | ✅ | AC coupling capacitor for SATA1 TX negative differential signal between CPU and mSATA connector. This is a standard configuration for SATA interfaces. | </details> <details> <summary><b>R239</b> - 110-0004476 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_RCOMP_N | ✅ | 402 ohm resistor connected between SATA_RCOMP_N and SATA_RCOMP_P, serving as the SATA compensation resistor for the Intel Atom E3825 SOC. | | 2 | 2 | SATA_RCOMP_P | ✅ | 402 ohm resistor connected between SATA_RCOMP_N and SATA_RCOMP_P, serving as the SATA compensation resistor for the Intel Atom E3825 SOC. | </details> <details> <summary><b>R73</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS4/ICLK_SATA_TERMP) to GND for SATA termination. | | 2 | 2 | ICLK_SATA_TERMP | ✅ | 0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS4/ICLK_SATA_TERMP) to GND for SATA termination. | </details> <details> <summary><b>R74</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS5/ICLK_SATA_TERMN) to GND for SATA termination. | | 2 | 2 | ICLK_SATA_TERMN | ✅ | 0 ohm resistor connecting CPU1 reserved VSS pin (RESERVED_VSS5/ICLK_SATA_TERMN) to GND for SATA termination. | </details> <details> <summary><b>R179</b> - 110-0001960 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001960) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_LED_B | ✅ | 220 ohm current limiting resistor for SATA LED indicator circuit, connected between CPU SATA_LED output and jumper-selectable power supply. | | 2 | 2 | SATA_LED_R | ✅ | 220 ohm current limiting resistor for SATA LED indicator circuit, connected between CPU SATA_LED output and jumper-selectable power supply. | </details> <details> <summary><b>J6</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S supply, providing power source for SATA LED circuit when jumper is installed. | | 2 | 2 | SATA_LED_R | ✅ | Connected to SATA_LED_R net, which connects through R179 to the CPU SATA LED output. | </details> <details> <summary><b>R220</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 10K pull-down resistor on SATA_GP0 (SATA General Purpose 0) pin, ensuring defined logic level when not driven. | | 2 | 2 | SATA_GP0 | ✅ | 10K pull-down resistor on SATA_GP0 (SATA General Purpose 0) pin, ensuring defined logic level when not driven. | </details> <details> <summary><b>R221</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 10K pull-down resistor on SATA_GP1 (SATA General Purpose 1) pin, ensuring defined logic level when not driven. | | 2 | 2 | SATA_GP1 | ✅ | 10K pull-down resistor on SATA_GP1 (SATA General Purpose 1) pin, ensuring defined logic level when not driven. | </details> <details> <summary><b>R354</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SD3_WP | ✅ | 0-ohm resistor ties SD3_WP (CPU1 pin BD5) to SD3_CD# (CPU1 pin BC24). This unusual connection appears intentional based on schematic note indicating Bay Trail-I platform-specific behavior for pin BD5. | | 2 | 2 | SD3_CD# | ✅ | 0-ohm resistor ties SD3_WP (CPU1 pin BD5) to SD3_CD# (CPU1 pin BC24). This unusual connection appears intentional based on schematic note indicating Bay Trail-I platform-specific behavior for pin BD5. | </details> <details> <summary><b>R2</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mPCIe_CLKREQ3_B | ✅ | 10K pull-up resistor on mPCIe_CLKREQ3_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | | 2 | 2 | +V1P8S | ✅ | 10K pull-up resistor on mPCIe_CLKREQ3_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | </details> <details> <summary><b>R192</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS7 | ✅ | 0 ohm resistor connecting reserved VSS pin RESERVED_VSS7 to GND. | | 2 | 2 | GND | ✅ | 0 ohm resistor connecting reserved VSS pin RESERVED_VSS7 to GND. | </details> <details> <summary><b>R218</b> - 110-0004476 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PCIE_RCOMP_P | ✅ | 402 ohm compensation resistor connected between PCIE_RCOMP_P and PCIE_RCOMP_N for PCIe impedance compensation. | | 2 | 2 | PCIE_RCOMP_N | ✅ | 402 ohm compensation resistor connected between PCIE_RCOMP_P and PCIE_RCOMP_N for PCIe impedance compensation. | </details> <details> <summary><b>R72</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS6 | ✅ | 0 ohm resistor connecting reserved VSS pin RESERVED_VSS6 to GND. | | 2 | 2 | GND | ✅ | 0 ohm resistor connecting reserved VSS pin RESERVED_VSS6 to GND. | </details> <details> <summary><b>R71</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_CLKREQ2_B | ✅ | 10K pull-up resistor on LAN_CLKREQ2_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | | 2 | 2 | +V1P8S | ✅ | 10K pull-up resistor on LAN_CLKREQ2_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | </details> <details> <summary><b>R190</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ1_B | ✅ | 10K pull-up resistor on CLKREQ1_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | | 2 | 2 | +V1P8S | ✅ | 10K pull-up resistor on CLKREQ1_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | </details> <details> <summary><b>R191</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ0_B | ✅ | 10K pull-up resistor on CLKREQ0_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | | 2 | 2 | +V1P8S | ✅ | 10K pull-up resistor on CLKREQ0_B signal to +V1P8S, providing proper logic level for active-low PCIe clock request. | </details> <details> <summary><b>R242</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDA_RCOMP | ✅ | Connected to CPU1 HDA_LPE_RCOMP pin (BF20) for HDA impedance compensation calibration. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the RCOMP calibration resistor. | </details> <details> <summary><b>R240</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to GND for the MMC1 RCOMP calibration resistor. | | 2 | 2 | MMC1_RCOMP | ✅ | Pin 2 is correctly connected to MMC1_RCOMP (CPU1 pin AY18) for eMMC interface impedance calibration. | </details> <details> <summary><b>R260</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_DATOUT | ✅ | Connected to LPE_I2S_DATOUT. This component is marked DNI (Do Not Install), so it is electrically absent from the circuit. | | 2 | 2 | GND | ✅ | Connected to GND. This component is marked DNI, so the pull-down to ground is not present in the final design. | </details> <details> <summary><b>R259</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_10_UNLOCK | ✅ | Connected to GPIO_S5_10_UNLOCK net. This pin forms one end of a 1K series resistor that connects to the LPE_I2S_DATOUT signal. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | Connected to LPE_I2S_DATOUT, which connects to CPU1 pin BC30 (LPE_I2S2_DATAOUT). Text notes indicate this signal can function as GPIO_S0_SC65 strap pin. | </details> <details> <summary><b>R268</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_FRM | ✅ | Connected to LPE_I2S_FRM, which is the I2S frame sync signal from CPU1 pin BA30. Text notes indicate this signal can function as GPIO_S0_SC63 strap pin. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S, providing a 10K pull-up for the LPE_I2S_FRM signal to 1.8V. | </details> <details> <summary><b>R219</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S as part of a pull-up resistor configuration for hardware strap GPIO_S0_SC_56. Component is DNI. | | 2 | 2 | GPIO_S0_SC_56 | ✅ | Connected to GPIO_S0_SC_56 as part of a pull-up resistor configuration for hardware strap. Component is DNI. | </details> <details> <summary><b>R189</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND as part of a pull-down resistor configuration for hardware strap GPIO_S0_SC_56. Component is DNI. | | 2 | 2 | GPIO_S0_SC_56 | ✅ | Connected to GPIO_S0_SC_56 as part of a pull-down resistor configuration for hardware strap. Component is DNI. | </details> <details> <summary><b>R255</b> - 110-0004474 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004474) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR_HOT_L | ✅ | Connected to VR_HOT_L net, which connects to CPU1 pin C24 (PROCHOT). This appears to be part of a thermal monitoring interface between the CPU and voltage regulators. | | 2 | 2 | +V1P0S | ✅ | Connected to +V1P0S (1.0V supply rail). Combined with the 73.2Ω resistance, this creates a low-impedance connection that appears to be a termination or interface resistor rather than a typical pull-up. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A9 | ILB_RTC_X2 | BRTCX2 | ✅ | ILB_RTC_X2 is connected to 32.768 kHz crystal Y1 pin 1 with 18pF load capacitor C42 and 10M feedback resistor R76. | | A13 | GPIO_S5_9 | SOC_USB_HOST_EN1 | ✅ | GPIO_S5_9 is connected to SOC_USB_HOST_EN1 net, used for USB host enable control. | | A17 | GPIO_S5_3 | mPCIE_WAKEB | ✅ | GPIO_S5_3 is connected to mPCIE_WAKEB net with optional 2.2K pull-up resistor R1 (DNI) to +V1P8A. | | A21 | PCU_SPI_MOSI | SOC_SPI_MOSI | ✅ | PCU_SPI_MOSI is connected through 0-ohm series resistor R103 to SOC_SPI_MOSI-R net for SPI communication. | | A25 | SVID_DATA | SVID_DATA | ✅ | SVID_DATA is connected through 16.9-ohm series resistor R101 to SVID_DATA-R for voltage regulator control. | | B7 | PMC_CORE_PWROK | PMC_CORE_PWROK | ✅ | PMC_CORE_PWROK is connected through 0-ohm resistor R59 to SYS_PWRGD with optional 1uF capacitor C33 (DNI) to GND. | | B8 | ILB_RTC_EXTPAD | BVCCRTC_EXTPAD | ✅ | ILB_RTC_EXTPAD is connected to 0.1uF capacitor C41 to GND for RTC external pad filtering. | | B10 | ~PMC_RSMRST | PMC_RSMRST | ✅ | PMC_RSMRST is connected with 10K pull-up to +3VSB, 100K pull-down to GND, and 10pF capacitor to GND for resume reset timing. | | B14 | GPIO_S5_6 | BOM_OP2 | ✅ | GPIO_S5_6 is connected to net BOM_OP2 for BOM option 2 configuration. | | B16 | GPIO_S5_1 | SOC_GPIO_S5_1 | ✅ | GPIO_S5_1 is connected to net SOC_GPIO_S5_1 for general purpose I/O. | | B18 | GPIO_S5_0 | SOC_GPIO_S5_0 | ✅ | GPIO_S5_0 is connected to net SOC_GPIO_S5_0 for general purpose I/O. | | B22 | PCU_SPI_MISO | SOC_SPI_MISO | ✅ | PCU_SPI_MISO is connected through 0-ohm series resistor R36 to SOC_SPI_MISO-R net for SPI communication. | | B24 | ~SVID_ALERT | SVID_ALERT | ✅ | SVID_ALERT is connected through 20-ohm series resistor R100 to SVID_ALERT-R, then through 69.8-ohm resistor R104 to +V1P0S. | | C9 | ILB_RTC_X1 | BRTCX1 | ✅ | ILB_RTC_X1 is connected to 32.768 kHz crystal Y1 pin 2 with 18pF load capacitor C43 and 10M feedback resistor R76. | | C11 | ~ILB_RTC_TEST | ILB_RTC_TESTB | ✅ | ILB_RTC_TEST is connected to net ILB_RTC_TESTB for RTC test mode control. | | C12 | ~ILB_RTC_RST | RTCRST_L | ✅ | ILB_RTC_RST is connected with 20K pull-up to +RTCVCC and 1uF capacitor to GND for RTC reset timing. | | C13 | GPIO_S5_8 | SOC_USB_HOST_EN0 | ✅ | GPIO_S5_8 is connected to net SOC_USB_HOST_EN0 for USB host enable control. | | C15 | GPIO_S5_7 | BOM_OP3 | ✅ | GPIO_S5_7 is connected to net BOM_OP3 for BOM option 3 configuration. | | C16 | GPIO_S5_5 | BOM_OP1 | ✅ | GPIO_S5_5 is connected to net BOM_OP1 for BOM option 1 configuration. | | C17 | GPIO_S5_4 | BOM_OP4 | ✅ | GPIO_S5_4 is connected to net BOM_OP4 for BOM option 4 configuration. | | C18 | GPIO_S5_2 | SOC_GPIO_S5_2 | ✅ | GPIO_S5_2 is connected to net SOC_GPIO_S5_2 for general purpose I/O. | | C19 | GPIO_S5_10 | GPIO_S5_10_UNLOCK | ✅ | GPIO_S5_10 is connected to net GPIO_S5_10_UNLOCK for GPIO unlock function. | | C21 | ~PCU_SPI_CS_11 | SOC_SPI_CS1B | ✅ | PCU_SPI_CS_11 is connected through 0-ohm series resistor R235 (DNI), effectively leaving SPI CS1 unconnected. | | C22 | PCU_SPI_CLK | SOC_SPI_CLK | ✅ | PCU_SPI_CLK is connected through 0-ohm series resistor R98 to SOC_SPI_CLK-R net for SPI clock. | | C23 | ~PCU_SPI_CS_00 | SOC_SPI_CS0B | ✅ | PCU_SPI_CS_00 is connected through 0-ohm series resistor R99 to SOC_SPI_CS0B-R net for SPI chip select 0. | | C25 | SVID_CLK | SVID_CLK-R | ✅ | SVID_CLK is connected to net SVID_CLK-R for voltage regulator control clock. | | D14 | TAP_TCK | XDP_H_TCK | ✅ | TAP_TCK is connected through 51-ohm resistor R8 to GND. This pull-down on JTAG clock is unusual but may be intentional to keep clock low when debugger is not connected. | | D18 | ~TAP_PRDY | XDP_H_PRDYB | ✅ | TAP_PRDY is connected to net XDP_H_PRDYB for JTAG probe ready signal. | | D20 | PMC_ACPRESENT | PMC_ACPRESENT | ✅ | PMC_ACPRESENT is connected with 2.2K pull-up to +V1P8A for AC present detection. | | D22 | ~PMC_SLP_S3 | PMC_SLP_S3_L | ✅ | PMC_SLP_S3 is connected to level shifter U19 pin 5 with optional 2.2K pull-up R53 (DNI) to +3VSB. | | D26 | PMC_SUSPWRDNACK | SUSPWRDNACK | ✅ | PMC_SUSPWRDNACK is connected with 10K pull-up to +V1P8A and optional test point TP14 (DNI). | | F12 | TAP_TDI | XDP_H_TDI | ✅ | TAP_TDI is connected through 51-ohm series resistor R10 with pull-up to +V1P8A for JTAG test data in. | | F14 | TAP_TMS | XDP_H_TMS | ✅ | TAP_TMS is connected through 51-ohm series resistor R9 with pull-up to +V1P8A for JTAG test mode select. | | F16 | ~TAP_PREQ | XDP_H_PREQB | ✅ | TAP_PREQ is connected to net XDP_H_PREQB for JTAG probe request signal. | | F18 | ~PMC_SLP_S0IX | PMC_SLP_S0IX | ✅ | PMC_SLP_S0IX is connected to optional test point TP10 (DNI) for sleep S0ix state monitoring. | | F20 | ~PMC_PLTRST | PMC_PLTRST_R_V1P8 | ✅ | PMC_PLTRST is connected to level shifter U19 pin 2 with optional 2.2K pull-up R56 (DNI) to +3VSB. | | F22 | ~PMC_SLP_S4 | PMC_SLP_S4_L | ✅ | PMC_SLP_S4 is connected to level shifter U19 pin 4 with optional 2.2K pull-up R54 (DNI) to +3VSB. | | F26 | ~PMC_WAKE_PCIE_0 | PMC_PCIE_WAKE_R | ✅ | PMC_WAKE_PCIE_0 is connected through diode D3 to PMC_PCIE_WAKE with 1K pull-up R253 to +V1P8A. | | G12 | ~TAP_TRST | XDP_H_TRSTB | ✅ | TAP_TRST is connected through 51-ohm resistor R19 to GND for JTAG test reset. | | G16 | TAP_TDO | XDP_H_TDO | ✅ | TAP_TDO is connected to net XDP_H_TDO for JTAG test data out. | | G18 | ~PMC_SUS_STAT | LPCPD_L | ✅ | PMC_SUS_STAT is connected to net LPCPD_L with optional test point TP7 (DNI) for suspend status monitoring. | | G24 | PMC_SUSCLK0_G24 | PMC_SUSCLK0 | ✅ | PMC_SUSCLK0_G24 is connected to level shifter U19 pin 3 with optional 2.2K pull-up R58 (DNI) to +V1P8A. | | J18 | GPIO_S5_25 | XDP_H_OBSDATA_A2 | ✅ | GPIO_S5_25 is connected to net XDP_H_OBSDATA_A2 for debug observation data. | | J20 | GPIO_S5_14 | GPIO_S514_J20 | ✅ | GPIO_S5_14 is connected with 10K pull-up to +V1P8A for GPIO configuration. | | J24 | GPIO_S5_17 | GPIO_S5_17 | ✅ | GPIO_S5_17 is connected to jumper J7 pin 1 with 10K pull-up R183 to +V1P8S for GPIO configuration. | | J26 | ~PMC_PWRBTN | PMC_PWRBTN | ✅ | PMC_PWRBTN is connected through diode D10 with optional 20K pull-up R161 (DNI) to +V1P8A for power button input. | | K18 | GPIO_S5_27 | EXP_GPIO1 | ✅ | GPIO_S5_27 is connected to net EXP_GPIO1 for expansion GPIO 1. | | K20 | GPIO_S5_28 | EXP_GPIO2 | ✅ | GPIO_S5_28 is connected to net EXP_GPIO2 for expansion GPIO 2. | | K24 | GPIO_S5_22 | GPIO_D2_LED_CTRL | ✅ | GPIO_S5_22 is connected to net GPIO_D2_LED_CTRL for LED control. | | K26 | ~PMC_BATLOW | PMC_BATLOW | ✅ | PMC_BATLOW is connected with 20K pull-up to +V1P8A for battery low detection. | | M18 | GPIO_S5_26 | XDP_H_OBSDATA_A3 | ✅ | GPIO_S5_26 is connected to net XDP_H_OBSDATA_A3 for debug observation data. | | M20 | GPIO_S5_24 | XDP_H_OBSDATA_A1 | ✅ | GPIO_S5_24 is connected to net XDP_H_OBSDATA_A1 for debug observation data. | | M22 | GPIO_S5_29 | EXP_GPIO3 | ✅ | GPIO_S5_29 is connected to net EXP_GPIO3 for expansion GPIO 3. | | M24 | GPIO_S5_30 | EXP_GPIO4 | ✅ | GPIO_S5_30 is connected to net EXP_GPIO4 for expansion GPIO 4. | | N24 | GPIO_S5_23 | XDP_H_OBSDATA_A0 | ✅ | GPIO_S5_23 is connected to net XDP_H_OBSDATA_A0 for debug observation data. | | N26 | GPIO_RCOMP | GPIO_RCOMP | ✅ | GPIO_RCOMP is connected to 49.9-ohm compensation resistor R238 to ground, correctly configured per datasheet. | | BA28 | SIO_SPI_MISO | SOC_SIO_SPI_MISO | ✅ | SIO_SPI_MISO is connected to net SOC_SIO_SPI_MISO for Serial I/O SPI master in slave out. | | BA34 | ~SIO_UART1_RTS | SIO_UART1_RTSB | ✅ | SIO_UART1_RTS is connected to net SIO_UART1_RTSB for UART1 request to send. | | AD9 | RESERVED_AD9 | | ✅ | RESERVED_AD9 pin has no connection, which is correct for reserved pins. | | AD10 | RESERVED_AD10 | | ✅ | RESERVED_AD10 pin has no connection, which is correct for reserved pins. | | AD12 | RESERVED_AD12 | | ✅ | RESERVED_AD12 pin has no connection, which is correct for reserved pins. | | AD13 | ICLK_RCOMP | ICLK_RCOMP | ✅ | ICLK_RCOMP is connected to 47.5-ohm compensation resistor R214 to ground, correctly configured per datasheet. | | AD14 | ICLK_ICOMP | ICLK_ICOMP | ✅ | ICLK_ICOMP is connected to 4.02K-ohm compensation resistor R215 to ground, correctly configured per datasheet. | | BD32 | ~SIO_UART2_RTS | | ✅ | SIO_UART2_RTS has no connection, which is acceptable if UART2 hardware flow control is not needed. | | BD34 | SIO_UART2_TXD | SIO_UART2_TXD | ✅ | SIO_UART2_TXD is connected to net SIO_UART2_TXD for UART2 transmit data. | | AF4 | PCIE_CLKP_00 | | ✅ | PCIE_CLKP_00 has no connection, which is acceptable if PCIe lane 0 is not used. | | AF6 | PCIE_CLKN_00 | | ✅ | PCIE_CLKN_00 has no connection, which is acceptable if PCIe lane 0 is not used. | | AF7 | PCIE_CLKP_11 | | ✅ | PCIE_CLKP_11 has no connection, which is acceptable if PCIe lane 1 is not used. | | AF9 | PCIE_CLKN_11 | | ✅ | PCIE_CLKN_11 has no connection, which is acceptable if PCIe lane 1 is not used. | | BF32 | ~SIO_UART2_CTS | | ✅ | SIO_UART2_CTS has no connection, which is acceptable if UART2 hardware flow control is not needed. | | BF34 | SIO_UART2_RXD | SIO_UART2_RXD | ✅ | SIO_UART2_RXD is connected to net SIO_UART2_RXD for UART2 receive data. | | BG9 | ~PMC_RSTBTN | PMC_RSTBTN | ✅ | PMC_RSTBTN is connected to net PMC_RSTBTN for reset button input. | | AH10 | ICLK_OSCOUT | XTAL25_OUT | ✅ | ICLK_OSCOUT is connected to 25 MHz crystal Y2 pin 3 with 27pF load capacitor C176 and 1M feedback resistor R188. | | AH12 | ICLK_OSCIN | XTAL25_IN | ✅ | ICLK_OSCIN is connected to 25 MHz crystal Y2 pin 1 with 27pF load capacitor C175 and 1M feedback resistor R188. | | BH4 | PMC_PLT_CLK_22 | | ✅ | PMC_PLT_CLK_22 has no connection, which is acceptable if platform clock 2 is not needed. | | BH5 | PMC_PLT_CLK_11 | | ✅ | PMC_PLT_CLK_11 has no connection, which is acceptable if platform clock 1 is not needed. | | BH6 | PMC_PLT_CLK_44 | | ✅ | PMC_PLT_CLK_44 has no connection, which is acceptable if platform clock 4 is not needed. | | BH7 | PMC_PLT_CLK_00 | | ✅ | PMC_PLT_CLK_00 has no connection, which is acceptable if platform clock 0 is not needed. | | BH8 | PMC_PLT_CLK_33 | I2S_MCLK | ✅ | PMC_PLT_CLK_33 is connected to net I2S_MCLK for I2S master clock output. | | AK4 | PCIE_CLKN_22 | PCIE_CLK-N2 | ✅ | PCIE_CLKN_22 is connected to net PCIE_CLK-N2 for PCIe lane 2 clock negative signal. | | AK6 | PCIE_CLKP_22 | PCIE_CLK-P2 | ✅ | PCIE_CLKP_22 is connected to net PCIE_CLK-P2 for PCIe lane 2 clock positive signal. | | BJ9 | PMC_PLT_CLK_55 | | ✅ | PMC_PLT_CLK_55 has no connection, which is acceptable if platform clock 5 is not needed. | | AM4 | PCIE_CLKN_33 | mPCIE_REFCLK_N | ✅ | PCIE_CLKN_33 is connected to net mPCIE_REFCLK_N for mini-PCIe reference clock negative signal. | | AM6 | PCIE_CLKP_33 | mPCIE_REFCLK_P | ✅ | PCIE_CLKP_33 is connected to net mPCIE_REFCLK_P for mini-PCIe reference clock positive signal. | | AM9 | RESERVED_AM9 | | ✅ | RESERVED_AM9 pin has no connection, which is correct for reserved pins. | | AM10 | RESERVED_AM10 | | ✅ | RESERVED_AM10 pin has no connection, which is correct for reserved pins. | | AT32 | SIO_PWM_11 | SOC_PWM1 | ✅ | SIO_PWM_11 is connected to net SOC_PWM1 for PWM output 1. | | AT34 | RESERVED | | ✅ | RESERVED pin has no connection, which is correct for reserved pins. | | AU32 | SIO_PWM_00 | SOC_PWM0 | ✅ | SIO_PWM_00 is connected to net SOC_PWM0 for PWM output 0. | | AU34 | SIO_UART1_RXD | SIO_UART1_RXD | ✅ | SIO_UART1_RXD is connected to net SIO_UART1_RXD for UART1 receive data. | | AV32 | ~SIO_SPI_CS | SOC_SIO_SPI_CS1 | ✅ | SIO_SPI_CS is connected to net SOC_SIO_SPI_CS1 for Serial I/O SPI chip select. | | AV34 | SIO_UART1_TXD | SIO_UART1_TXD | ✅ | SIO_UART1_TXD is connected to net SIO_UART1_TXD for UART1 transmit data. | | AY28 | SIO_SPI_MOSI | SOC_SIO_SPI_MOSI | ✅ | SIO_SPI_MOSI is connected to net SOC_SIO_SPI_MOSI for Serial I/O SPI master out slave in. | | AY30 | SIO_SPI_CLK | SOC_SIO_SPI_CLK | ✅ | SIO_SPI_CLK is connected to net SOC_SIO_SPI_CLK for Serial I/O SPI clock. | | AY34 | ~SIO_UART1_CTS | SIO_UART1_CTSB | ✅ | SIO_UART1_CTS is connected to net SIO_UART1_CTSB for UART1 clear to send. | </details> <details> <summary><b>R57</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pin 1 is correctly connected to +V1P8A, providing the pull-up voltage for the OE pin of U19. | | 2 | 2 | PMC_OE | ✅ | Pin 2 is correctly connected to PMC_OE, which connects to the OE pin of U19, enabling the level shifter by default. | </details> <details> <summary><b>U19</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A (1.8V supply) for the A-side voltage reference. | | 2 | A1 | PMC_PLTRST_R_V1P8 | ✅ | A1 is correctly connected to PMC_PLTRST_R_V1P8, the 1.8V side of the platform reset signal from CPU1 pin F20. | | 3 | A2 | PMC_SUSCLK0 | ✅ | A2 is correctly connected to PMC_SUSCLK0, the 1.8V side of the suspend clock signal from CPU1 pin G24. | | 4 | A3 | PMC_SLP_S4_L | ✅ | A3 is correctly connected to PMC_SLP_S4_L, the 1.8V side of the S4 sleep state signal from CPU1 pin F22. | | 5 | A4 | PMC_SLP_S3_L | ✅ | A4 is correctly connected to PMC_SLP_S3_L, the 1.8V side of the S3 sleep state signal from CPU1 pin D22. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SLP_S3_L | ✅ | B4 is correctly connected to SLP_S3_L, the 3.3V side of the S3 sleep state signal. | | 8 | B3 | SLP_S4_L | ✅ | B3 is correctly connected to SLP_S4_L, the 3.3V side of the S4 sleep state signal. | | 9 | B2 | SUSCLK_3P3 | ✅ | B2 is correctly connected to SUSCLK_3P3, the 3.3V side of the suspend clock signal. | | 10 | B1 | PMC_PLTRST_L | ✅ | B1 is correctly connected to PMC_PLTRST_L, the 3.3V side of the platform reset signal. | | 11 | VCCB | PWR_BUF1 | ✅ | VCCB is correctly connected to PWR_BUF1, which is effectively +3VSB (3.3V standby supply) through R26. | | 12 | OE | PMC_OE | ✅ | OE is correctly connected to PMC_OE with a pull-up to +V1P8A through R57 to enable the level shifter. | </details> <details> <summary><b>C41</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BVCCRTC_EXTPAD | ✅ | Decoupling capacitor for RTC external pad, connected to BVCCRTC_EXTPAD which connects to CPU1 RTC power pin. | | 2 | 2 | GND | ✅ | Ground connection for decoupling capacitor. | </details> <details> <summary><b>C286</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for bulk decoupling capacitor on +RTCVCC rail. | | 2 | 2 | +RTCVCC | ✅ | Bulk decoupling capacitor for +RTCVCC power rail, providing low-frequency filtering and charge storage. | </details> <details> <summary><b>R279</b> - 110-0001957 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +RTCVCC | ✅ | Pull-up resistor connected to +RTCVCC to pull the RTC reset signal high (inactive state). | | 2 | 2 | RTCRST_L | ✅ | Pull-up resistor output connected to RTCRST_L, the active-low RTC reset signal going to CPU1. | </details> <details> <summary><b>R278</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VBAT | ✅ | Series resistor input connected to battery positive terminal (+VBAT). | | 2 | 2 | +VBAT_R | ✅ | Series resistor output connected to +VBAT_R, which feeds the battery backup OR-ing diode. | </details> <details> <summary><b>C285</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for filtering capacitor on RTC reset signal. | | 2 | 2 | RTCRST_L | ✅ | Filtering capacitor on RTCRST_L signal, forming RC filter with R279 for clean reset signal with ~20ms time constant. | </details> <details> <summary><b>Y1</b> - 145-0004789 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/145-0004789) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BRTCX2 | ✅ | Crystal pin 1 connected to BRTCX2, which connects to CPU1 RTC oscillator pin ILB_RTC_X2. Load capacitor C42 (18pF) and feedback resistor R76 (10M) are properly connected. | | 2 | 2 | BRTCX1 | ✅ | Crystal pin 2 connected to BRTCX1, which connects to CPU1 RTC oscillator pin ILB_RTC_X1. Load capacitor C43 (18pF) and feedback resistor R76 (10M) are properly connected. | </details> <details> <summary><b>BH1</b> - BATTERY HOLDER VERT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/353-0003073) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +VBAT | ✅ | Positive battery terminals connected to +VBAT net. Both pins are tied together for redundancy, which is standard for battery holders. | | 2 | P2 | +VBAT | ✅ | Positive battery terminals connected to +VBAT net. Both pins are tied together for redundancy, which is standard for battery holders. | | 3 | N | GND | ✅ | Negative battery terminal correctly connected to GND. | </details> <details> <summary><b>D5</b> - 4536-0009 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | +PS_3VSB | ✅ | Anode 1 connected to +PS_3VSB (3.3V standby power). This is one input to the OR-ing diode configuration for RTC backup power. | | A2 | A2 | +VBAT_R | ✅ | Anode 2 connected to +VBAT_R (battery voltage through 1K resistor). This is the backup power input to the OR-ing diode configuration. | | C | C | +RTCVCC | ✅ | Common cathode connected to +RTCVCC, which powers the RTC circuitry. The OR-ing configuration ensures RTC power from either 3VSB or battery, whichever is higher. | </details> <details> <summary><b>C175</b> - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor ground terminal correctly connected to GND, providing ground reference for the crystal load capacitor. | | 2 | 2 | XTAL25_IN | ✅ | Load capacitor correctly connected to crystal input (XTAL25_IN) to provide required load capacitance for the 25MHz oscillator. | </details> <details> <summary><b>C176</b> - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor ground terminal correctly connected to GND, providing ground reference for the crystal load capacitor. | | 2 | 2 | XTAL25_OUT | ✅ | Load capacitor correctly connected to crystal output (XTAL25_OUT) to provide required load capacitance for the oscillator. | </details> <details> <summary><b>R188</b> - 110-0001941 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XTAL25_IN | ✅ | Feedback resistor correctly connected to XTAL25_IN, providing DC bias for the Pierce oscillator amplifier. | | 2 | 2 | XTAL25_OUT | ✅ | Feedback resistor correctly connected to XTAL25_OUT, completing the bias feedback path for the Pierce oscillator. | </details> <details> <summary><b>Y2</b> - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XTAL25_IN | ✅ | Crystal input pin correctly connected to CPU oscillator input (ICLK_OSCIN) through XTAL25_IN net with proper 27pF load capacitor C175 and 1MΩ feedback resistor R188. | | 2 | 2 | GND | ✅ | Crystal ground pins correctly connected to system ground, providing proper grounding for the 4-pin crystal package. | | 4 | 4 | GND | ✅ | Crystal ground pins correctly connected to system ground, providing proper grounding for the 4-pin crystal package. | | 3 | 3 | XTAL25_OUT | ✅ | Crystal output pin correctly connected to CPU oscillator output (ICLK_OSCOUT) through XTAL25_OUT net with proper 27pF load capacitor C176. | </details> <details> <summary><b>R103</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SOC_SPI_MOSI-R | ✅ | 0-ohm series resistor connecting CPU SPI MOSI (SOC_SPI_MOSI) to routed signal (SOC_SPI_MOSI-R). Provides routing flexibility and potential measurement point. | | 2 | 2 | SOC_SPI_MOSI | ✅ | 0-ohm series resistor connecting CPU SPI MOSI (SOC_SPI_MOSI) to routed signal (SOC_SPI_MOSI-R). Provides routing flexibility and potential measurement point. | </details> <details> <summary><b>R98</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SOC_SPI_CLK-R | ✅ | 0-ohm series resistor connecting CPU SPI clock (SOC_SPI_CLK) to routed signal (SOC_SPI_CLK-R). Provides routing flexibility and potential measurement point. DNI capacitor C69 on routed side is not electrically present. | | 2 | 2 | SOC_SPI_CLK | ✅ | 0-ohm series resistor connecting CPU SPI clock (SOC_SPI_CLK) to routed signal (SOC_SPI_CLK-R). Provides routing flexibility and potential measurement point. DNI capacitor C69 on routed side is not electrically present. | </details> <details> <summary><b>R36</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SOC_SPI_MISO-R | ✅ | 0-ohm series resistor connecting CPU SPI MISO (SOC_SPI_MISO) to routed signal (SOC_SPI_MISO-R). Provides routing flexibility and potential measurement point. | | 2 | 2 | SOC_SPI_MISO | ✅ | 0-ohm series resistor connecting CPU SPI MISO (SOC_SPI_MISO) to routed signal (SOC_SPI_MISO-R). Provides routing flexibility and potential measurement point. | </details> <details> <summary><b>R99</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SOC_SPI_CS0B-R | ✅ | 0-ohm series resistor connecting CPU SPI chip select 0 (SOC_SPI_CS0B) to routed signal (SOC_SPI_CS0B-R). Provides routing flexibility and potential measurement point. | | 2 | 2 | SOC_SPI_CS0B | ✅ | 0-ohm series resistor connecting CPU SPI chip select 0 (SOC_SPI_CS0B) to routed signal (SOC_SPI_CS0B-R). Provides routing flexibility and potential measurement point. | </details> <details> <summary><b>R253</b> - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE_R | ✅ | Connected to PMC_PCIE_WAKE_R net, which is the anode side of diode D3 and connects to the CPU wake input. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A rail, providing pull-up voltage for the PMC_PCIE_WAKE_R signal at the CPU input level. | </details> <details> <summary><b>D3</b> - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE | ✅ | Cathode pins connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27. This forms the high-voltage side of a diode-based level shifter. | | 2 | 2 | PMC_PCIE_WAKE | ✅ | Cathode pins connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27. This forms the high-voltage side of a diode-based level shifter. | | 3 | 3 | PMC_PCIE_WAKE_R | ✅ | Anode pin connected to PMC_PCIE_WAKE_R net, which connects to CPU1 pin F26 and is pulled up to +V1P8A through R253. This forms the low-voltage side of the level shifter. | </details> <details> <summary><b>R27</b> - 2.2K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE | ✅ | Connected to PMC_PCIE_WAKE net, which is the cathode side of diode D3 and the source side of the level shifter circuit. | | 2 | 2 | +3VSB | ✅ | Connected to +3VSB rail, providing pull-up voltage for the PMC_PCIE_WAKE signal. | </details> <details> <summary><b>R162</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3VSB_OK | ✅ | Connected to 3VSB_OK signal, providing pull-up function. | | 2 | 2 | +3VSB | ✅ | Connected to +3VSB power rail, providing pull-up voltage source. | </details> <details> <summary><b>D10</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | 3VSB_OK | ✅ | Anode connected to 3VSB_OK signal, which is pulled up to +3VSB through R162 (1K). This forms one input of a diode OR gate. | | A2 | A2 | PMC_PWRBTN | ✅ | Anode connected to PMC_PWRBTN signal, which is pulled up to +3VSB through R27 (2.2K). This forms the second input of the diode OR gate. | | C | C | PS_OUT_L | ✅ | Common cathode output connected to PS_OUT_L. This output goes low when either input (3VSB_OK or PMC_PWRBTN) goes low, implementing a diode OR gate. | </details> <details> <summary><b>R101</b> - 110-0004468 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA | ✅ | Connected to SVID_DATA from CPU1 pin A25. This is the CPU side of the SVID data signal. | | 2 | 2 | SVID_DATA-R | ✅ | Connected to SVID_DATA-R, which presumably connects to the voltage regulator on another page. | </details> <details> <summary><b>R100</b> - 110-0001959 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT | ✅ | Connected to SVID_ALERT from CPU1 pin B24. This is the CPU side of the SVID alert signal. | | 2 | 2 | SVID_ALERT-R | ✅ | Connected to SVID_ALERT-R, which connects to pull-up resistor R104 and presumably to the voltage regulator on another page. | </details> <details> <summary><b>R104</b> - 110-0002104 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Connected to SVID_ALERT-R, providing pull-up for the open-drain SVID alert signal. | | 2 | 2 | +V1P0S | ✅ | Connected to +V1P0S (1.0V supply), providing the pull-up voltage for SVID_ALERT. | </details> <details> <summary><b>R9</b> - 110-0002078 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing pull-up for JTAG TMS signal through 51Ω resistor. | | 2 | 2 | XDP_H_TMS | ✅ | Connected to XDP_H_TMS net, which connects to CPU JTAG TMS signal. | </details> <details> <summary><b>R10</b> - 110-0002078 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing pull-up for JTAG TDI signal through 51Ω resistor. | | 2 | 2 | XDP_H_TDI | ✅ | Connected to XDP_H_TDI net, which connects to CPU JTAG TDI signal. | </details> <details> <summary><b>R19</b> - 110-0002078 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing pull-down for JTAG TRST signal through 51Ω resistor, keeping TAP controller in reset by default. | | 2 | 2 | XDP_H_TRSTB | ✅ | Connected to XDP_H_TRSTB net, which connects to CPU JTAG TRST signal. | </details> <details> <summary><b>R8</b> - 110-0002078 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing pull-down for JTAG TCK signal through 51Ω resistor to prevent spurious clocking. | | 2 | 2 | XDP_H_TCK | ✅ | Connected to XDP_H_TCK net, which connects to CPU JTAG TCK signal. | </details> <details> <summary><b>R214</b> - 110-0004473 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | ICLK_RCOMP | ✅ | Connected to ICLK_RCOMP compensation pin on CPU1. This resistor sets the output impedance for the Intel Clock interface. | | 2 | 2 | GND | ✅ | Connected to ground, providing the reference for the compensation resistor. | </details> <details> <summary><b>R215</b> - 110-0002053 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | ICLK_ICOMP | ✅ | Connected to ICLK_ICOMP compensation pin on CPU1. This resistor sets the bias current for the Intel Clock interface. | | 2 | 2 | GND | ✅ | Connected to ground, providing the reference for the compensation resistor. | </details> <details> <summary><b>R238</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_RCOMP | ✅ | Connected to GPIO_RCOMP compensation pin on CPU1. This resistor sets the output impedance for GPIO drivers. | | 2 | 2 | GND | ✅ | Connected to ground, providing the reference for the compensation resistor. | </details> <details> <summary><b>R82</b> - 110-0001859 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSMRST | ✅ | 100K pull-down resistor connecting PMC_RSMRST to GND. Forms part of an RC network with R83 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R82's value is appropriate for its pull-down function. | | 2 | 2 | GND | ✅ | 100K pull-down resistor connecting PMC_RSMRST to GND. Forms part of an RC network with R83 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R82's value is appropriate for its pull-down function. | </details> <details> <summary><b>R83</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSMRST | ✅ | 10K pull-up resistor connecting PMC_RSMRST to +3VSB standby power. Forms part of an RC network with R82 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R83's value is appropriate for its pull-up function. | | 2 | 2 | +3VSB | ✅ | 10K pull-up resistor connecting PMC_RSMRST to +3VSB standby power. Forms part of an RC network with R82 and C49 that does not meet the >10μs delay requirement noted on the schematic, but R83's value is appropriate for its pull-up function. | </details> <details> <summary><b>C49</b> - 123-0001076 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSMRST | ❌ | <details><summary>10pF filter capacitor on PMC_RSMRST signal. The capacitance value is insufficient to meet the >10μs RC delay requirement noted on the schematic. Should be increased to approximately 1nF to achieve the required delay with the existing 10K pull-up resistor.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c66f35d31fb1590e57a5" diff-visibility="full" variant="default" view-coords="78.97,30.96,86.47,38.46" aspect-ratio="1.29" } <ul><li>Pin 1 connects to PMC_RSMRST net <em>(from schematic)</em></li><li>Pin 2 connects to GND net <em>(from schematic)</em></li><li>C49 is a 10pF capacitor rated for 50V <em>(from schematic)</em></li><li>C49 is located at coordinates (459.74, 279.4) <em>(from schematic)</em></li><li>A text note &#x27;RC delay &gt;10us&#x27; is present at coordinates (401.32, 287.02), spatially near C49 and its associated resistors <em>(from schematic)</em></li><li>The RC time constant with R83 (10K pull-up) is τ = 10,000 × 10×10^-12 = 100ns = 0.1μs <em>(reasoning)</em></li><li>The RC time constant with R82 (100K pull-down) is τ = 100,000 × 10×10^-12 = 1μs <em>(reasoning)</em></li><li>Neither time constant meets the &gt;10μs requirement stated in the schematic note <em>(reasoning)</em></li><li>To achieve a 10μs RC delay with the existing 10K pull-up resistor, C49 should be increased from 10pF to approximately 1nF (1000pF) <em>(reasoning)</em></li><li>Alternatively, to achieve 10μs delay with the existing 10pF capacitor, R83 would need to be increased to 1MΩ, but this would be impractical for a pull-up resistor <em>(reasoning)</em></li><li>The 10pF value is typical for high-frequency noise filtering but inadequate for creating the required delay <em>(reasoning)</em></li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>10pF filter capacitor on PMC_RSMRST signal. The capacitance value is insufficient to meet the >10μs RC delay requirement noted on the schematic. Should be increased to approximately 1nF to achieve the required delay with the existing 10K pull-up resistor.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c66f35d31fb1590e57a5" diff-visibility="full" variant="default" view-coords="79.42,30.96,86.92,38.46" aspect-ratio="1.29" } <ul><li>Pin 1 connects to PMC_RSMRST net <em>(from schematic)</em></li><li>Pin 2 connects to GND net <em>(from schematic)</em></li><li>C49 is a 10pF capacitor rated for 50V <em>(from schematic)</em></li><li>C49 is located at coordinates (459.74, 279.4) <em>(from schematic)</em></li><li>A text note &#x27;RC delay &gt;10us&#x27; is present at coordinates (401.32, 287.02), spatially near C49 and its associated resistors <em>(from schematic)</em></li><li>The RC time constant with R83 (10K pull-up) is τ = 10,000 × 10×10^-12 = 100ns = 0.1μs <em>(reasoning)</em></li><li>The RC time constant with R82 (100K pull-down) is τ = 100,000 × 10×10^-12 = 1μs <em>(reasoning)</em></li><li>Neither time constant meets the &gt;10μs requirement stated in the schematic note <em>(reasoning)</em></li><li>To achieve a 10μs RC delay with the existing 10K pull-up resistor, C49 should be increased from 10pF to approximately 1nF (1000pF) <em>(reasoning)</em></li><li>Alternatively, to achieve 10μs delay with the existing 10pF capacitor, R83 would need to be increased to 1MΩ, but this would be impractical for a pull-up resistor <em>(reasoning)</em></li><li>The 10pF value is typical for high-frequency noise filtering but inadequate for creating the required delay <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R59</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_CORE_PWROK | ✅ | 0-ohm resistor connecting PMC_CORE_PWROK from CPU to SYS_PWRGD system power good signal. Provides direct signal propagation with option for isolation if needed during debug or rework. | | 2 | 2 | SYS_PWRGD | ✅ | 0-ohm resistor connecting PMC_CORE_PWROK from CPU to SYS_PWRGD system power good signal. Provides direct signal propagation with option for isolation if needed during debug or rework. | </details> <details> <summary><b>R236</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_ACPRESENT | ✅ | Connected to PMC_ACPRESENT signal from CPU1 pin D20. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing pull-up voltage for PMC_ACPRESENT. | </details> <details> <summary><b>R183</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing pull-up voltage for GPIO_S5_17. | | 2 | 2 | GPIO_S5_17 | ✅ | Connected to GPIO_S5_17, which goes to CPU1 pin J24 and jumper J7 pin 1. | </details> <details> <summary><b>R237</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S514_J20 | ✅ | Connected to GPIO_S514_J20 signal from CPU1 pin J20 (GPIO_S5_14). | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing pull-up voltage for GPIO_S5_14. | </details> <details> <summary><b>R256</b> - 110-0001957 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_BATLOW | ✅ | Connected to PMC_BATLOW signal from CPU1 pin K26 (active-low battery low indicator). | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing pull-up voltage for PMC_BATLOW. | </details> <details> <summary><b>R254</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SUSPWRDNACK | ✅ | Connected to SUSPWRDNACK signal from CPU1 pin D26 (PMC_SUSPWRDNACK). | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing pull-up voltage for SUSPWRDNACK. | </details> <details> <summary><b>J7</b> - 258-0002513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_17 | ✅ | Pin 1 connects to GPIO_S5_17, which is a GPIO pin from the CPU. A 10K pull-up resistor (R183) to +V1P8S is present on this net. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the jumper. | </details> <details> <summary><b>R26</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PWR_BUF1 | ✅ | Pin 1 connects to PWR_BUF1, which supplies power to the VCCB pin of level shifter U19. This connection is correct. | | 2 | 2 | +3VSB | ✅ | Pin 2 connects to +3VSB, providing 3.3V standby power through R26 to the level shifter. This connection is correct. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A7 | USB_HSIC_RCOMP | USB_HSIC0_RCOMP | ✅ | USB HSIC compensation resistor connection. Connected to 45.3 ohm resistor R77 to ground. | | B4 | USB_HSIC0_DATA | | ✅ | USB HSIC0 data and strobe signals. Both pins are unconnected, indicating HSIC0 interface is unused. | | B5 | USB_HSIC0_STROBE | | ✅ | USB HSIC0 data and strobe signals. Both pins are unconnected, indicating HSIC0 interface is unused. | | B12 | GPIO_S5_43 | | ✅ | GPIO_S5[43] pin, can be configured as USB_ULPI_REFCLK. Currently unconnected. | | B20 | ~USB_OC_11 | SOC_USB_HOST_OC1 | ✅ | USB overcurrent detection input for port 1 (active low). Connected through 10K pullup R97 to +V1P8A. | | C7 | USB_RCOMPI | USB_RCOMP | ✅ | USB 2.0 compensation resistor connections. Both pins connected to same net USB_RCOMP with 45.3 ohm resistor R185 to ground. | | D6 | USB_RCOMPO | USB_RCOMP | ✅ | USB 2.0 compensation resistor connections. Both pins connected to same net USB_RCOMP with 45.3 ohm resistor R185 to ground. | | C20 | ~USB_OC_00 | SOC_USB_HOST_OC0 | ✅ | USB overcurrent detection input for port 0 (active low). Connected through 10K pullup R84 to +V1P8A. | | D2 | USB_HSIC1_STROBE | | ✅ | USB HSIC1 strobe and data signals. Both pins are unconnected, indicating HSIC1 interface is unused. | | E2 | USB_HSIC1_DATA | | ✅ | USB HSIC1 strobe and data signals. Both pins are unconnected, indicating HSIC1 interface is unused. | | D4 | USB3_RXP0 | USB3_RXP0 | ✅ | USB 3.0 receive differential pair for lane 0. Connected to nets USB3_RXP0 and USB3_RXN0. | | E3 | USB3_RXN0 | USB3_RXN0 | ✅ | USB 3.0 receive differential pair for lane 0. Connected to nets USB3_RXP0 and USB3_RXN0. | | D10 | ICLK_USB_TERM_1 | ICLK_USB_TERM_0 | ✅ | USB clock termination pins have swapped net connections. Pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1, and pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0. While functionally correct since both require identical 1K termination to ground, the net naming violates documentation best practices. | | F10 | ICLK_USB_TERMN | ICLK_USB_TERM_1 | ✅ | USB clock termination pins have swapped net connections. Pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1, and pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0. While functionally correct since both require identical 1K termination to ground, the net naming violates documentation best practices. | | G2 | GPIO_S5_31 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | G14 | USB_DN1 | USB_DN1 | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | H3 | GPIO_S5_42 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | H4 | RESERVED_H4 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | H5 | RESERVED_H5 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | H7 | RESERVED_H7 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | H8 | RESERVED_H8 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | H10 | USB_DN3 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | J3 | GPIO_S5_40 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | K2 | GPIO_S5_34 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | K3 | GPIO_S5_35 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | K10 | USB_DP3 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | L1 | GPIO_S5_33 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | L3 | GPIO_S5_39 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | M2 | GPIO_S5_36 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | M3 | GPIO_S5_32 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | N3 | GPIO_S5_37 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | P2 | GPIO_S5_38 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | P3 | GPIO_S5_41 | | ✅ | GPIO_S5 pins and unused USB port 3 pins. All unconnected, indicating these interfaces are unused. | | J12 | USB_DN2 | USB_HOST_DN | ✅ | USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP. | | J14 | USB_DP1 | USB_DP1 | ✅ | USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP. | | K12 | USB_DP2 | USB_HOST_DP | ✅ | USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP. | | K16 | USB_DN0 | USB_DN0 | ✅ | USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP. | | M16 | USB_DP0 | USB_DP0 | ✅ | USB 2.0 data differential pairs for ports 0, 1, and 2. Port 2 (J12/K12) connects to USB_HOST_DN/DP. | | K6 | USB3_TXP0 | USB3_TXP0 | ✅ | USB 3.0 transmit differential pair for lane 0. Connected to nets USB3_TXP0 and USB3_TXN0. | | K7 | USB3_TXN0 | USB3_TXN0 | ✅ | USB 3.0 transmit differential pair for lane 0. Connected to nets USB3_TXP0 and USB3_TXN0. | | M4 | RESERVED_M4 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | M6 | RESERVED_M6 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | M7 | RESERVED_M7 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | M9 | RESERVED_M9 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | M10 | RESERVED_M10 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | P6 | RESERVED_P6 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | P7 | RESERVED_P7 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | P10 | RESERVED_P10 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | P12 | RESERVED_P12 | | ✅ | Reserved pins. All unconnected per datasheet guidance for reserved pins. | | M12 | USB3_REXT0 | USB3_REXT0 | ✅ | USB 3.0 external resistor connection. Connected to 1.24K ohm resistor R212 to ground. | | M13 | USB_PLL_MON | USB_PLL_MON | ✅ | USB PLL monitor output. Connected to test point TP3 via net USB_PLL_MON. | | BC12 | GPIO_S0_SC_56 | GPIO_S0_SC_56 | ✅ | GPIO_S0_SC[56] pin. Connected to net GPIO_S0_SC_56, function not specified on this page. | | BC14 | GPIO_S0_SC_58 | HDMI_CEC | ✅ | GPIO_S0_SC[58] pin configured for HDMI CEC function. Connected to net HDMI_CEC. | | BC16 | GPIO_S0_SC_61 | PCU_UART3_RXD | ✅ | GPIO_S0_SC[61] pin configured as UART3 RX. Connected through level shifter U6 to debug connector J4 pin 4. | | BD12 | GPIO_S0_SC_55 | GPIO_S0_SC_55 | ✅ | GPIO_S0_SC[55] pin. Connected to test point TP8 via net GPIO_S0_SC_55. | | BD14 | GPIO_S0_SC_57 | PCU_UART3_TXD | ✅ | GPIO_S0_SC[57] pin configured as UART3 TX. Connected through level shifter U6 to debug connector J4 pin 5. | | BD16 | GPIO_S0_SC_60 | | ✅ | GPIO_S0_SC[60] pin. Currently unconnected. | | BF14 | GPIO_S0_SC_59 | | ✅ | GPIO_S0_SC[59] pin. Currently unconnected. | | BF18 | LPC_RCOMP | LPC_RCOMP | ✅ | LPC compensation resistor connection. Connected to 49.9 ohm resistor R241 to ground. | | BF27 | SIO_I2C4_DATA | | ✅ | SIO_I2C4_DATA pin. Currently unconnected, indicating I2C4 interface is unused. | | BG11 | ~PCU_SMB_ALERT | PCU_SMB_ALERT | ✅ | SMBus alert signal (active low). Connected through 10K pullup R75 to +V1P8S, with optional connection to LAN-SMB-ALERT# through DNI resistor R842. | | BG12 | PCU_SMB_DATA | PCU_SMB_DATA | ✅ | SMBus data line. Connected through level shifter U5 to DDR_SMB_DATA with 2.2K pullups on both sides. | | BG13 | ILB_LPC_SERIRQ | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BG14 | ILB_LPC_AD_33 | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BG15 | ILB_LPC_CLK_00 | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BG16 | ~ILB_LPC_CLKRUN | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BG17 | ~ILB_LPC_FRAME | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BH14 | ILB_LPC_CLK_11 | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BH16 | ILB_LPC_AD_00 | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BJ13 | ILB_LPC_AD_22 | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BJ17 | ILB_LPC_AD_11 | | ✅ | LPC (Low Pin Count) bus signals. All unconnected, indicating LPC interface is unused. | | BG23 | SIO_I2C0_CLK | | ✅ | SIO_I2C0_CLK pin. Currently unconnected, indicating I2C0 interface is unused. | | BG24 | SIO_I2C1_DATA | SIO_I2C1_SDA | ✅ | I2C1 data line. Connected to test point TP6 via net SIO_I2C1_SDA. | | BG25 | SIO_I2C2_DATA | | ✅ | SIO_I2C2_DATA pin. Currently unconnected, indicating I2C2 interface is unused. | | BG26 | SIO_I2C3_DATA | | ✅ | SIO_I2C3_DATA pin. Currently unconnected, indicating I2C3 interface is unused. | | BG27 | SIO_I2C4_CLK | | ✅ | SIO_I2C4_CLK pin. Currently unconnected, indicating I2C4 interface is unused. | | BG28 | SIO_I2C5_CLK | SI0_I2C5_SCL | ✅ | I2C5 clock line. Connected through 22 ohm series resistor R270 to I2C5_SCL. | | BG29 | SIO_I2C6_CLK | SI0_I2C6_SCL | ✅ | I2C6 clock line. Connected through 22 ohm series resistor R12 to I2C6_SCL. | | BG30 | GPIO_S0_SC_093 | TP10_NET | ✅ | GPIO_S0_SC[93] pin. Connected to TP10_NET which is grounded through 0-ohm resistor R261. | | BH10 | PCU_SMB_CLK | PCU_SMB_CLK | ✅ | SMBus clock line. Connected through level shifter U5 to DDR_SMB_CLK with 2.2K pullups on both sides. | | BH12 | ILB_8254_SPKR | ILB_8254_SPKR | ✅ | Speaker output pin. Connected to net ILB_8254_SPKR, destination not shown on this page. | | BH22 | SIO_I2C0_DATA | | ✅ | SIO_I2C0_DATA pin. Currently unconnected, indicating I2C0 interface is unused. | | BH24 | SIO_I2C1_CLK | SIO_I2C1_SCL | ✅ | I2C1 clock line. Connected to test point TP5 via net SIO_I2C1_SCL. | | BH26 | SIO_I2C3_CLK | | ✅ | SIO_I2C3_CLK pin. Currently unconnected, indicating I2C3 interface is unused. | | BH28 | SIO_I2C5_DATA | SI0_I2C5_SDA | ✅ | I2C5 data line. Connected through 22 ohm series resistor R269 to I2C5_SDA. | | BH30 | GPIO_S0_SC_092 | TP9_NET | ✅ | GPIO_S0_SC[92] pin. Connected to TP9_NET which is grounded through 0-ohm resistor R243. | | BJ13 | ILB_LPC_AD_22 | | ✅ | LPC address/data bit 2 signal. Currently unconnected, indicating LPC interface is unused. | | BJ25 | SIO_I2C2_CLK | | ✅ | SIO_I2C2_CLK pin. Currently unconnected, indicating I2C2 interface is unused. | | BJ29 | SIO_I2C6_DATA | SI0_I2C6_SDA | ✅ | I2C6 data line. Connected through 22 ohm series resistor R11 to I2C6_SDA. | </details> <details> <summary><b>U5</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DDR_SMB_CLK | ✅ | B2 pin correctly connected to DDR_SMB_CLK with appropriate 2.2K pull-up to +VCC3 through R44. | | 2 | GND | GND | ✅ | GND pin correctly connected to system ground. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V) supply rail for A-side reference voltage. | | 4 | A2 | PCU_SMB_CLK | ✅ | A2 pin correctly connected to PCU_SMB_CLK with appropriate 2.2K pull-up to +V1P8S through R45. | | 5 | A1 | PCU_SMB_DATA | ✅ | A1 pin correctly connected to PCU_SMB_DATA with appropriate 2.2K pull-up to +V1P8S through R177. | | 6 | OE | PCU_SMB_BUFF_ENB | ✅ | OE pin correctly connected to PCU_SMB_BUFF_ENB with 2.2K pull-up to +V1P8S through R49, enabling the device by default. | | 7 | VCCB | BUF2_PWR | ✅ | VCCB pin correctly connected to BUF2_PWR, which connects to +VCC3 (3.3V) through 0-ohm resistor R48. | | 8 | B1 | DDR_SMB_DATA | ✅ | B1 pin correctly connected to DDR_SMB_DATA with appropriate 2.2K pull-up to +VCC3 through R47. | </details> <details> <summary><b>U6</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DBG_UART3_TXD | ✅ | UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication. | | 4 | A2 | PCU_UART3_TXD | ✅ | UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication. | | 5 | A1 | PCU_UART3_RXD | ✅ | UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication. | | 8 | B1 | DBG_UART3_RXD | ✅ | UART TX and RX lines are correctly connected. Pin 4 (A2) receives CPU transmit at 1.8V, pin 1 (B2) outputs to debug connector at 3.3V through series resistor. Pin 8 (B1) receives from debug connector at 3.3V, pin 5 (A1) outputs to CPU receive at 1.8V. The signal routing properly crosses TX to RX as required for UART communication. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply) with local decoupling. | | 6 | OE | LSENB | ✅ | OE pin correctly connected to LSENB with pull-up to +V1P8S, enabling control of the level translator. | | 7 | VCCB | BUF3_PWR | ✅ | VCCB pin correctly connected to BUF3_PWR (3.3V standby supply) with local decoupling. | </details> <details> <summary><b>J4</b> - 258-0004869 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0004869) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 correctly connected to GND, providing ground reference for the serial cable. | | 2 | 2 | | ✅ | Pins 2, 3, and 6 are not connected. This is acceptable for a minimal UART interface that only requires GND, TX, and RX. | | 3 | 3 | | ✅ | Pins 2, 3, and 6 are not connected. This is acceptable for a minimal UART interface that only requires GND, TX, and RX. | | 6 | 6 | | ✅ | Pins 2, 3, and 6 are not connected. This is acceptable for a minimal UART interface that only requires GND, TX, and RX. | | 4 | 4 | DBG_UART3_RXD | ✅ | Pin 4 correctly connected to DBG_UART3_RXD. This is where the board receives data from the debug cable's transmit line at 3.3V levels. | | 5 | 5 | DBG_UART3_TXD_R | ✅ | Pin 5 correctly connected to DBG_UART3_TXD_R. This is where the board transmits data to the debug cable's receive line at 3.3V levels. | </details> <details> <summary><b>R51</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF3_PWR | ✅ | 0 ohm resistor correctly connects BUF3_PWR to +3VSB, providing power to the B-side of level translator U6. The 0 ohm value allows for easy power measurement or disconnection. | | 2 | 2 | +3VSB | ✅ | 0 ohm resistor correctly connects BUF3_PWR to +3VSB, providing power to the B-side of level translator U6. The 0 ohm value allows for easy power measurement or disconnection. | </details> <details> <summary><b>R52</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LSENB | ✅ | 2.2K ohm pull-up resistor correctly pulls LSENB to +V1P8S, enabling level translator U6 by default while allowing external control. | | 2 | 2 | +V1P8S | ✅ | 2.2K ohm pull-up resistor correctly pulls LSENB to +V1P8S, enabling level translator U6 by default while allowing external control. | </details> <details> <summary><b>R75</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 10K ohm pull-up resistor correctly pulls PCU_SMB_ALERT to +V1P8S. This is appropriate for the open-drain SMBus ALERT signal. | | 2 | 2 | PCU_SMB_ALERT | ✅ | 10K ohm pull-up resistor correctly pulls PCU_SMB_ALERT to +V1P8S. This is appropriate for the open-drain SMBus ALERT signal. | </details> <details> <summary><b>R819</b> - 110-0002000 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002000) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DBG_UART3_TXD | ✅ | 330 ohm series resistor correctly provides current limiting and protection for the UART transmit signal going to the external debug connector. | | 2 | 2 | DBG_UART3_TXD_R | ✅ | 330 ohm series resistor correctly provides current limiting and protection for the UART transmit signal going to the external debug connector. | </details> <details> <summary><b>R270</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SCL | ✅ | Series resistor input connected to CPU I2C5 clock line. This resistor provides signal integrity and protection for the I2C5 SCL line. | | 2 | 2 | I2C5_SCL | ✅ | Series resistor output connected to external I2C5 SCL bus. This provides the buffered I2C clock signal to external devices. | </details> <details> <summary><b>R11</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SDA | ✅ | Series resistor input connected to CPU I2C6 data line. This resistor provides signal integrity and protection for the I2C6 SDA line. | | 2 | 2 | I2C6_SDA | ✅ | Series resistor output connected to external I2C6 SDA bus. This provides the buffered I2C data signal to external devices. | </details> <details> <summary><b>R12</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SCL | ✅ | Series resistor input connected to CPU I2C6 clock line. This resistor provides signal integrity and protection for the I2C6 SCL line. | | 2 | 2 | I2C6_SCL | ✅ | Series resistor output connected to external I2C6 SCL bus. This provides the buffered I2C clock signal to external devices. | </details> <details> <summary><b>R269</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SDA | ✅ | Series resistor input connected to CPU I2C5 data line. This resistor provides signal integrity and protection for the I2C5 SDA line. | | 2 | 2 | I2C5_SDA | ✅ | Series resistor output connected to external I2C5 SDA bus. This provides the buffered I2C data signal to external devices. | </details> <details> <summary><b>R212</b> - 110-0004478 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004478) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_REXT0 | ✅ | 1.24K ohm resistor connected between USB3_REXT0 (CPU pin M12) and ground for USB 3.0 impedance calibration. | | 2 | 2 | GND | ✅ | 1.24K ohm resistor connected between USB3_REXT0 (CPU pin M12) and ground for USB 3.0 impedance calibration. | </details> <details> <summary><b>R77</b> - 110-0004472 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU pin A7) and ground for USB HSIC impedance calibration. | | 2 | 2 | USB_HSIC0_RCOMP | ✅ | 45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU pin A7) and ground for USB HSIC impedance calibration. | </details> <details> <summary><b>R185</b> - 110-0004472 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 45.3 ohm resistor connected between USB_RCOMP (CPU pins D6 and C7) and ground for USB 2.0 impedance calibration. | | 2 | 2 | USB_RCOMP | ✅ | 45.3 ohm resistor connected between USB_RCOMP (CPU pins D6 and C7) and ground for USB 2.0 impedance calibration. | </details> <details> <summary><b>R241</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPC_RCOMP | ✅ | 49.9 ohm resistor connected between LPC_RCOMP (CPU pin BF18) and ground for LPC bus impedance calibration. | | 2 | 2 | GND | ✅ | 49.9 ohm resistor connected between LPC_RCOMP (CPU pin BF18) and ground for LPC bus impedance calibration. | </details> <details> <summary><b>R840</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_DATA | ✅ | Pin 1 connects to DDR_SMB_DATA, which is the 3.3V level-shifted SMBus data signal from level shifter U5. This 0 ohm jumper allows the CPU's SMBus data line to be routed to the LAN controller. | | 2 | 2 | LAN-SMB-DATA | ✅ | Pin 2 connects to LAN-SMB-DATA, which routes the SMBus data signal to a LAN controller (likely on another page). This completes the SMBus data path from CPU to LAN controller. | </details> <details> <summary><b>R842</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-SMB-ALERT# | ✅ | Pin 1 connects to LAN-SMB-ALERT#, which is the active-low SMBus alert signal from a LAN controller. This 0 ohm jumper allows the LAN's alert signal to be routed to the CPU. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Pin 2 connects to PCU_SMB_ALERT, which routes to the CPU's active-low SMBus alert input. The signal has a 10K pullup to +V1P8S through R75. | </details> <details> <summary><b>R841</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_CLK | ✅ | Pin 1 connects to DDR_SMB_CLK, which is the 3.3V level-shifted SMBus clock signal from level shifter U5. This 0 ohm jumper allows the CPU's SMBus clock line to be routed to the LAN controller. | | 2 | 2 | LAN-SMB-CLK | ✅ | Pin 2 connects to LAN-SMB-CLK, which routes the SMBus clock signal to a LAN controller (likely on another page). This completes the SMBus clock path from CPU to LAN controller. | </details> <details> <summary><b>R97</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pin 1 is connected to +V1P8A power rail, providing the pull-up voltage for the USB overcurrent detection signal. | | 2 | 2 | SOC_USB_HOST_OC1 | ✅ | Pin 2 is connected to SOC_USB_HOST_OC1, an active-low USB overcurrent detection signal from the CPU. | </details> <details> <summary><b>R84</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pin 1 is connected to +V1P8A power rail, providing the pull-up voltage for the USB overcurrent detection signal. | | 2 | 2 | SOC_USB_HOST_OC0 | ✅ | Pin 2 is connected to SOC_USB_HOST_OC0, an active-low USB overcurrent detection signal from the CPU. | </details> <details> <summary><b>TP1</b> - TEST_POINT_0.040_SMT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $9N613 | ✅ | Test point correctly connected to CPU1 pin AF30 (TP_CORE_V1P05_S4) for monitoring the 1.05V core voltage rail in S4 power state. | </details> <details> <summary><b>TP2</b> - TEST_POINT_0.040_SMT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $9N615 | ✅ | Test point correctly connected to CPU1 pin AA22 (TP2_CORE_VCC_S0IX) for monitoring the core VCC voltage rail in S0IX power state. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A48 | DRAM_VDD_S4 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AK38 | DRAM_VDD_S4_AK38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AM38 | DRAM_VDD_S4_AM38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AV41 | DRAM_VDD_S4_AV41 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AV42 | DRAM_VDD_S4_AV42 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BB46 | DRAM_VDD_S4_BB46 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BD49 | DRAM_VDD_S4_BD49 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BD52 | DRAM_VDD_S4_BD52 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BD53 | DRAM_VDD_S4_BD53 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BF44 | DRAM_VDD_S4_BF44 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BG51 | DRAM_VDD_S4_BG51 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BJ48 | DRAM_VDD_S4_BJ48 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | C51 | DRAM_VDD_S4_C51 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | D44 | DRAM_VDD_S4_D44 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | F49 | DRAM_VDD_S4_F49 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | F52 | DRAM_VDD_S4_F52 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | F53 | DRAM_VDD_S4_F53 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | H46 | DRAM_VDD_S4_H46 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | M41 | DRAM_VDD_S4_M41 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | M42 | DRAM_VDD_S4_M42 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | V38 | DRAM_VDD_S4_V38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | Y38 | DRAM_VDD_S4_Y38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | N28 | CORE_VSS_SENSE_N28 | VSS_SENSE | ✅ | CORE_VSS_SENSE ground sense pin connected to VSS_SENSE net for voltage regulator ground reference. | | P26 | CORE_VCC_S0IX_P26 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | P27 | CORE_VCC_S0IX_P27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | U27 | CORE_VCC_S0IX_U27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | U29 | CORE_VCC_S0IX_U29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | V27 | CORE_VCC_S0IX_V27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | V29 | CORE_VCC_S0IX_V29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | V30 | CORE_VCC_S0IX_V30 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | Y27 | CORE_VCC_S0IX_Y27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | Y29 | CORE_VCC_S0IX_Y29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | Y30 | CORE_VCC_S0IX_Y30 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AA27 | CORE_VCC_S0IX_AA27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AA29 | CORE_VCC_S0IX_AA29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AA30 | CORE_VCC_S0IX_AA30 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AC27 | CORE_VCC_S0IX_AC27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AC29 | CORE_VCC_S0IX_AC29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AC30 | CORE_VCC_S0IX_AC30 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AD27 | CORE_VCC_S0IX_AD27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AD29 | CORE_VCC_S0IX_AD29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AD30 | CORE_VCC_S0IX_AD30 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AF27 | CORE_VCC_S0IX_AF27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AF29 | CORE_VCC_S0IX_AF29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AG27 | CORE_VCC_S0IX_AG27 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AG29 | CORE_VCC_S0IX_AG29 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | AG30 | CORE_VCC_S0IX_AG30 | +VCORE | ✅ | CORE_VCC_S3 power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) to the processor cores. | | P28 | CORE_VCC_SENSE_P28 | VCC_SENSE | ✅ | CORE_VCC_SENSE voltage sense pin connected to VCC_SENSE net for voltage regulator feedback. | | AA22 | TP2_CORE_VCC_S0IX | $9N615 | ✅ | TP2_CORE_VCC_S3 test point pin connected to test point TP2 for monitoring core voltage. | | AA24 | UNCORE_VNN_S3_AA24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AC22 | UNCORE_VNN_S3_AC22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AC24 | UNCORE_VNN_S3_AC24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AD22 | UNCORE_VNN_S3_AD22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AD24 | UNCORE_VNN_S3_AD24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AF22 | UNCORE_VNN_S3_AF22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AF24 | UNCORE_VNN_S3_AF24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AG22 | UNCORE_VNN_S3_AG22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AG24 | UNCORE_VNN_S3_AG24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AJ22 | UNCORE_VNN_S3_AJ22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AJ24 | UNCORE_VNN_S3_AJ24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AK22 | UNCORE_VNN_S3_AK22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AK24 | UNCORE_VNN_S3_AK24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AK25 | UNCORE_VNN_S3_AK25 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AK27 | UNCORE_VNN_S3_AK27 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AK29 | UNCORE_VNN_S3_AK29 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AK30 | UNCORE_VNN_S3_AK30 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AK32 | UNCORE_VNN_S3_AK32 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | AM22 | UNCORE_VNN_S3_AM22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) to the uncore/graphics logic. | | BB8 | UNCORE_VNN_SENSE | VCCGT_SENSE | ✅ | UNCORE_VNN_SENSE voltage sense pin connected to VCCGT_SENSE net for voltage regulator feedback. | | AD38 | DRAM_VDD_S4_AD38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 power supply pins connected to DRAM_VDD_CLK rail. This is a separate power rail for DDR clock circuitry derived from +VDIMM through a 0-ohm resistor with dedicated decoupling. | | AF38 | DRAM_VDD_S4_AF38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 power supply pins connected to DRAM_VDD_CLK rail. This is a separate power rail for DDR clock circuitry derived from +VDIMM through a 0-ohm resistor with dedicated decoupling. | | AF30 | TP_CORE_V1P05_S4 | $9N613 | ✅ | TP_CORE_V1P05_S4 test point pin connected to test point TP1 for monitoring 1.05V core voltage. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A3 | VSS_A3_A3 | GND | ✅ | VSS ground pins connected to GND. | | A5 | VSS_A5_A5 | GND | ✅ | VSS ground pins connected to GND. | | A6 | VSS_A6_A6 | GND | ✅ | VSS ground pins connected to GND. | | A49 | VSS_A49_A49 | GND | ✅ | VSS ground pins connected to GND. | | A51 | VSS_A51_A51 | GND | ✅ | VSS ground pins connected to GND. | | A52 | VSS_A52_A52 | GND | ✅ | VSS ground pins connected to GND. | | B2 | VSS_B2_B2 | GND | ✅ | VSS ground pins connected to GND. | | B52 | VSS_B52_B52 | GND | ✅ | VSS ground pins connected to GND. | | B53 | VSS_B53_B53 | GND | ✅ | VSS ground pins connected to GND. | | BE1 | VSS_BE1_BE1 | GND | ✅ | VSS ground pins connected to GND. | | BE53 | VSS_BE53_BE53 | GND | ✅ | VSS ground pins connected to GND. | | BG1 | VSS_BG1_BG1 | GND | ✅ | VSS ground pins connected to GND. | | BG53 | VSS_BG53_BG53 | GND | ✅ | VSS ground pins connected to GND. | | BH1 | VSS_BH1_BH1 | GND | ✅ | VSS ground pins connected to GND. | | BH2 | VSS_BH2_BH2 | GND | ✅ | VSS ground pins connected to GND. | | BH52 | VSS_BH52_BH52 | GND | ✅ | VSS ground pins connected to GND. | | BH53 | VSS_BH53_BH53 | GND | ✅ | VSS ground pins connected to GND. | | BJ2 | VSS_BJ2_BJ2 | GND | ✅ | VSS ground pins connected to GND. | | BJ3 | VSS_BJ3_BJ3 | GND | ✅ | VSS ground pins connected to GND. | | BJ5 | VSS_BJ5_BJ5 | GND | ✅ | VSS ground pins connected to GND. | | BJ49 | VSS_BJ49_BJ49 | GND | ✅ | VSS ground pins connected to GND. | | BJ51 | VSS_BJ51_BJ51 | GND | ✅ | VSS ground pins connected to GND. | | BJ52 | VSS_BJ52_BJ52 | GND | ✅ | VSS ground pins connected to GND. | | C1 | VSS_C1_C1 | GND | ✅ | VSS ground pins connected to GND. | | C53 | VSS_C53_C53 | GND | ✅ | VSS ground pins connected to GND. | | E1 | VSS_E1_E1 | GND | ✅ | VSS ground pins connected to GND. | | E53 | VSS_E53_E53 | GND | ✅ | VSS ground pins connected to GND. | | B6 | UNCORE_V1P0_G3_B6 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement. | | C5 | UNCORE_V1P0_G3_C5 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement. | | U22 | UNCORE_V1P0_G3_U22 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement. | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins connected to +V1P0A with 400mA current requirement. | | C3 | USB3_V1P0_G3_C3 | +V1P0A | ✅ | USB3_V1P0_G3 power pins connected to +V1P0A. | | Y19 | USB3_V1P0_G3_Y19 | +V1P0A | ✅ | USB3_V1P0_G3 power pins connected to +V1P0A. | | F1 | RESERVED_F1 | $10N1595 | ✅ | RESERVED pin connected to test point TP4 (DNI). Acceptable for debugging purposes. | | M14 | USB_V1P0_S3_M14 | +V1P0S | ✅ | USB_V1P0_S3 power pins connected to +V1P0S. | | U18 | USB_V1P0_S3_U18 | +V1P0S | ✅ | USB_V1P0_S3 power pins connected to +V1P0S. | | U19 | USB_V1P0_S3_U19 | +V1P0S | ✅ | USB_V1P0_S3 power pins connected to +V1P0S. | | N18 | USB_V3P3_G3_N18 | +3VSB | ✅ | USB_V3P3_G3 power pins connected to +3VSB. | | P18 | USB_V3P3_G3_P18 | +3VSB | ✅ | USB_V3P3_G3 power pins connected to +3VSB. | | N20 | USB_V1P8_G3_N20 | +V1P8A | ✅ | USB_V1P8_G3 power pin connected to +V1P8A. | | N22 | PCU_V3P3_G3_N22 | +3VSB | ✅ | PCU_V3P3_G3 power pin connected to +3VSB with 55mA current requirement. | | P22 | RTC_VCC_P22 | +RTCVCC | ✅ | RTC_VCC power pin connected to +RTCVCC with 160uA current requirement. | | U16 | USB_VSSA_U16 | GND | ✅ | USB_VSSA analog ground pin connected to GND. | | U24 | UNCORE_V1P8_G3_U24 | +V1P8A | ✅ | UNCORE_V1P8_G3 power pins connected to +V1P8A. | | AA18 | UNCORE_V1P8_G3_AA18 | +V1P8A | ✅ | UNCORE_V1P8_G3 power pins connected to +V1P8A. | | U25 | PMU_V1P8_G3_U25 | +V1P8A | ✅ | PMU_V1P8_G3 power pin connected to +V1P8A. | | V18 | USB_HSIC_V1P24_G3_V18 | +V1P0A | ✅ | USB_HSIC_V1P24_G3 power pin connected to +V1P0A instead of V1P24A. Text note indicates this is intentional because USB HSIC is not used. | | V24 | UNCORE_V1P0_S0IX_V24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering. | | Y24 | UNCORE_V1P0_S0IX_Y24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering. | | Y22 | UNCORE_V1P0_S0IX_Y22 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering. | | AN29 | UNCORE_V1P0_S0IX_AN29 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering. | | AN30 | UNCORE_V1P0_S0IX_AN30 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0 through 0-ohm jumper R222 from +V1P0S. Multiple 1uF and 22uF decoupling capacitors provide filtering. | | V25 | PCU_V1P8_G3_V25 | +V1P8A | ✅ | PCU_V1P8_G3 power pin connected to +V1P8A with 65mA current requirement. | | V32 | SVID_V1P0_S3_V32 | +V1P0S | ✅ | SVID_V1P0_S3 power pin connected to +V1P0S. | | AA25 | UNCORE_V1P35_S0IX_F5_AA25 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement. | | AF19 | UNCORE_V1P35_S0IX_F6 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement. | | V36 | UNCORE_V1P35_S0IX_F3_V36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement. | | U36 | UNCORE_V1P35_S0IX_F4_U36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement. | | AG32 | UNCORE_V1P35_S0IX_F2_AG32 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement. | | AG19 | UNCORE_V1P35_S0IX_F1_AG19 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins connected to VCC_UNCORE_V1P35 through ferrite bead FB3 from +V1P35S with 400mA current requirement. | | AA36 | DRAM_V1P0_S0IX_AA36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | AD35 | DRAM_V1P0_S0IX_AD35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | AF35 | DRAM_V1P0_S0IX_AF35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | AF36 | DRAM_V1P0_S0IX_AF36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | AJ36 | DRAM_V1P0_S0IX_AJ36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | AK35 | DRAM_V1P0_S0IX_AK35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | AK36 | DRAM_V1P0_S0IX_AK36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | Y35 | DRAM_V1P0_S0IX_Y35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | Y36 | DRAM_V1P0_S0IX_Y36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins connected to VCC_DRAM through 0-ohm jumper R265 from +V1P0S. Multiple 1uF decoupling capacitors provide filtering. | | AC32 | CORE_V1P05_S3_AC32 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | Y32 | CORE_V1P05_S3_Y32 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | AA33 | CORE_V1P05_S3_AA33 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | AF33 | CORE_V1P05_S3_AF33 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | AG33 | CORE_V1P05_S3_AG33 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | AG35 | CORE_V1P05_S3_AG35 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | U33 | CORE_V1P05_S3_U33 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | U35 | CORE_V1P05_S3_U35 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | V33 | CORE_V1P05_S3_V33 | +V1P0S | ✅ | CORE_V1P05_S3 power pins connected to +V1P0S with multiple 1uF decoupling capacitors. Datasheet specifies 1.05V but net name suggests 1.0V - potential naming inconsistency that should be verified. | | AD16 | VSS_AD16 | VCC_VSS_V1P2 | ✅ | MIPI_V1P24_S3 power pins connected to VCC_VSS_V1P2 which is grounded through R216. Text note indicates CSI is not used, so grounding is intentional and correct. | | AD18 | VSS_AD18 | VCC_VSS_V1P2 | ✅ | MIPI_V1P24_S3 power pins connected to VCC_VSS_V1P2 which is grounded through R216. Text note indicates CSI is not used, so grounding is intentional and correct. | | AD36 | DRAM_V1P35_S0IX_F1_AD36 | VCC_UNCORE_V1P35 | ✅ | DRAM_V1P35_S0IX_F1 power pin connected to VCC_UNCORE_V1P35, same 1.35V rail as UNCORE pins. | | BD1 | VGA_V1P35_S3_F1_BD1 | VCC_CRT_V1P35 | ✅ | VGA_V1P35_S3_F1 power pin connected to VCC_CRT_V1P35 through ferrite bead FB4 from +V1P35S with 45mA current requirement. | | AF16 | UNCORE_V1P0_S3_AF16 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins connected to +V1P0S. | | AF18 | UNCORE_V1P0_S3_AF18 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins connected to +V1P0S. | | G1 | UNCORE_V1P0_S3_G1 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins connected to +V1P0S. | | Y18 | UNCORE_V1P0_S3_Y18 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins connected to +V1P0S. | | AF21 | UNCORE_V1P0_S0IX_AF21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0, same rail as pins V24, Y24, Y22, AN29, AN30. | | AG21 | UNCORE_V1P0_S0IX_AG21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins connected to VCC_VIS_V1P0, same rail as pins V24, Y24, Y22, AN29, AN30. | | AJ18 | DDI_V1P0_S0IX_AJ18 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current. | | AK19 | DDI_V1P0_S0IX_AK19 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current. | | AK21 | DDI_V1P0_S0IX_AK21 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current. | | AM16 | DDI_V1P0_S0IX_AM16 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins connected to +V1P0S. Text notes indicate placement requirements and 900mA current. | | AJ19 | ICLK_V1P35_S3_F1_AJ19 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 power pins connected to VCC_ICLK_V1P35 through ferrite bead FB5 from +V1P35S with 350mA current requirement. | | AG18 | ICLK_V1P35_S3_F2 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 power pins connected to VCC_ICLK_V1P35 through ferrite bead FB5 from +V1P35S with 350mA current requirement. | | BJ6 | VGA_V1P0_S3_BJ6 | +V1P0S | ✅ | VGA_V1P0_S3 power pin connected to +V1P0S with 900mA current requirement. | | AM27 | LPC_V1P8V3P3_S3_AM27 | +VCC3S | ✅ | LPC_V1P8V3P3_S3 power pin connected to +VCC3S. Datasheet allows either 1.8V or 3.3V. | | AM30 | UNCORE_V1P8_S3_AM30 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins connected to +V1P8S. | | AN32 | UNCORE_V1P8_S3_AN32 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins connected to +V1P8S. | | U38 | UNCORE_V1P8_S3_U38 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins connected to +V1P8S. | | AM32 | HDA_LPE_V1P5V1P8_S3_AM32 | +V1P8S | ✅ | HDA_LPE_V1P5V1P8_S3 power pin connected to +V1P8S with 10mA current requirement. Datasheet allows either 1.5V or 1.8V. | | AN16 | VSSA_AN16 | GND | ✅ | VSSA analog ground pin connected to GND. | | AN18 | PCIE_SATA_V1P0_S3_AN18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3 power pin connected to +V1P0S. | | AN19 | SATA_V1P0_S3_AN19 | +V1P0S | ✅ | SATA_V1P0_S3 power pin connected to +V1P0S. | | AN21 | PCIE_V1P0_S3_AN21 | +V1P0S | ✅ | PCIE_V1P0_S3 power pins connected to +V1P0S. | | AM21 | PCIE_V1P0_S3_AM21 | +V1P0S | ✅ | PCIE_V1P0_S3 power pins connected to +V1P0S. | | AM18 | PCIE_V1P0_S3_AM18 | +V1P0S | ✅ | PCIE_V1P0_S3 power pins connected to +V1P0S. | | AK18 | PCIE_V1P0_S3_AK18 | +V1P0S | ✅ | PCIE_V1P0_S3 power pins connected to +V1P0S. | | AN24 | VGA_V3P3_S3_AN24 | +VCC3S | ✅ | VGA_V3P3_S3 power pin connected to +VCC3S. | | AN25 | GPIO_V1P0_S3_AN25 | +V1P0S | ✅ | GPIO_V1P0_S3 power pin connected to +V1P0S with 45mA current requirement. | | AN27 | SD3_V1P8V3P3_S3_AN27 | +VCC3S | ✅ | SD3_V1P8V3P3_S3 power pin connected to +VCC3S. Datasheet allows either 1.8V or 3.3V. | </details> <details> <summary><b>FB3</b> - FERRITE_600OHM_1.3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0001423) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to +V1P35S source rail. This is the standard input configuration for a ferrite bead filter. | | 2 | 2 | VCC_UNCORE_V1P35 | ✅ | Output pin connected to VCC_UNCORE_V1P35 filtered rail. This rail supplies multiple CPU pins and has appropriate decoupling capacitors. | </details> <details> <summary><b>FB4</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to +V1P35S source rail. This is the standard input configuration for a ferrite bead filter. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Output pin connected to VCC_CRT_V1P35 filtered rail. This rail supplies CPU1 pin BD1 and has appropriate bulk decoupling capacitors. | </details> <details> <summary><b>FB5</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to +V1P35S source rail. This is the standard input configuration for a ferrite bead filter. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Output pin connected to VCC_ICLK_V1P35 filtered rail. This rail supplies CPU1 clock-related pins and has appropriate decoupling capacitors. | </details> <details> <summary><b>R265</b> - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | 0-ohm jumper connecting +V1P0S main supply to VCC_DRAM rail which powers DRAM interface pins on the CPU. This is a standard power distribution design allowing separate decoupling for the DRAM interface. | | 2 | 2 | VCC_DRAM | ✅ | 0-ohm jumper connecting +V1P0S main supply to VCC_DRAM rail which powers DRAM interface pins on the CPU. This is a standard power distribution design allowing separate decoupling for the DRAM interface. | </details> <details> <summary><b>R222</b> - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | 0-ohm jumper connecting +V1P0S main supply to VCC_VIS_V1P0 rail which powers vision-related uncore logic pins on the CPU. This is a standard power distribution design allowing separate decoupling for the vision subsystem. | | 2 | 2 | VCC_VIS_V1P0 | ✅ | 0-ohm jumper connecting +V1P0S main supply to VCC_VIS_V1P0 rail which powers vision-related uncore logic pins on the CPU. This is a standard power distribution design allowing separate decoupling for the vision subsystem. | </details> <details> <summary><b>R216</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VSS_V1P2 | ✅ | 0-ohm jumper connecting CPU VSS pins (AD16, AD18) to ground. The connection is functionally correct, though the net name VCC_VSS_V1P2 is confusing as it suggests a power rail rather than a ground connection. | | 2 | 2 | GND | ✅ | 0-ohm jumper connecting CPU VSS pins (AD16, AD18) to ground. The connection is functionally correct, though the net name VCC_VSS_V1P2 is confusing as it suggests a power rail rather than a ground connection. | </details> <details> <summary><b>C28</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, which is correct for a decoupling capacitor. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Pin 2 is connected to VCC_CRT_V1P35, which supplies power to CPU1 pin BD1 through ferrite bead FB4 from the +V1P35S rail. | </details> <details> <summary><b>C164</b> - 22uF 20% 6.3V 0805 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, which is correct for a decoupling capacitor. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Pin 2 is connected to VCC_CRT_V1P35, which supplies power to CPU1 pin BD1 through ferrite bead FB4 from the +V1P35S rail. | </details> <details> <summary><b>C224</b> - 22uF 20% 6.3V 0805 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VIS_V1P0 | ✅ | Pin 1 is correctly connected to VCC_VIS_V1P0 power rail for decoupling. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND for decoupling. | </details> <details> <summary><b>C225</b> - 22uF 20% 6.3V 0805 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VIS_V1P0 | ✅ | Pin 1 is correctly connected to VCC_VIS_V1P0 power rail for decoupling. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND for decoupling. | </details> <details> <summary><b>C201</b> - 22uF 20% 6.3V 0805 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VIS_V1P0 | ✅ | Pin 1 is correctly connected to VCC_VIS_V1P0 power rail for decoupling. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND for decoupling. | </details> <details> <summary><b>D7</b> - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N is connected to GND and serves as the ground reference for the bidirectional TVS diode. | | P | P | +5VSB | ✅ | Pin P is connected to the +5VSB rail being protected by this bidirectional TVS diode. | </details> <details> <summary><b>J8</b> - 3430-0212 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3430-0212) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to the +5VSB power rail and serves as the power input terminal of the connector. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND and serves as the ground return terminal of the connector. | </details> <details> <summary><b>C153</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to the +5VSB rail and serves as the positive terminal of the decoupling capacitor. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND and serves as the ground return for the decoupling capacitor. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A11 | VSS1 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A15 | VSS2 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A19 | VSS3 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A23 | VSS4 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A27 | VSS5 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A31 | VSS6 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A35 | VSS7 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A39 | VSS8 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A43 | VSS9 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | A47 | VSS10 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA1 | VSS11 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA3 | VSS15 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA16 | VSS12 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA19 | VSS13 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA21 | VSS14 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA32 | VSS16 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA35 | VSS17 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA38 | VSS18 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AA53 | VSS19 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB4 | VSS21 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB6 | VSS28 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB10 | VSS20 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB41 | VSS22 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB45 | VSS23 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB47 | VSS24 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB48 | VSS25 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB50 | VSS26 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AB51 | VSS27 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC16 | VSS29 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC18 | VSS30 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC19 | VSS31 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC21 | VSS32 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC25 | VSS33 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC33 | VSS34 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC35 | VSS35 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC36 | VSS36 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AC38 | VSS37 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AD7 | VSS44 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AD19 | VSS38 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AD21 | VSS39 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AD25 | VSS40 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AD32 | VSS41 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AD33 | VSS42 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AD47 | VSS43 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE1 | VSS45 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE3 | VSS49 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE4 | VSS50 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE6 | VSS60 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE8 | VSS61 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE9 | VSS62 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE11 | VSS46 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE12 | VSS47 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE14 | VSS48 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE40 | VSS51 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE42 | VSS52 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE43 | VSS53 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE45 | VSS54 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE46 | VSS55 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE48 | VSS56 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE50 | VSS57 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE51 | VSS58 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE53 | VSS59 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE60 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AE62 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AF10 | VSS63 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AF12 | VSS64 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AF25 | VSS65 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AF32 | VSS66 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AF47 | VSS67 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AG16 | VSS68 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AG25 | VSS69 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AG36 | VSS70 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AG38 | VSS71 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH4 | VSS72 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH6 | VSS110 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH7 | VSS75 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH9 | VSS76 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH41 | VSS73 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH45 | VSS74 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH47 | VSS106 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH48 | VSS107 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH50 | VSS108 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AH51 | VSS109 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ1 | VSS77 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ3 | VSS83 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ16 | VSS78 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ21 | VSS79 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ25 | VSS80 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ27 | VSS81 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ29 | VSS82 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ30 | VSS84 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ32 | VSS85 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ33 | VSS86 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ35 | VSS87 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ38 | VSS88 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AJ53 | VSS89 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AK10 | VSS90 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AK14 | VSS91 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AK16 | VSS92 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AK33 | VSS93 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AK41 | VSS94 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AK44 | VSS95 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM7 | VSS113 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM12 | VSS96 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM19 | VSS97 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM24 | VSS98 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM25 | VSS99 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM29 | VSS100 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM33 | VSS101 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM35 | VSS102 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM36 | VSS103 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM40 | VSS104 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM44 | VSS111 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AM51 | VSS112 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN1 | VSS114 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN3 | VSS119 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN5 | VSS131 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN6 | VSS134 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN8 | VSS135 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN9 | VSS136 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN11 | VSS115 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN12 | VSS116 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN14 | VSS117 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN22 | VSS118 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN33 | VSS120 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN35 | VSS121 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN36 | VSS122 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN38 | VSS123 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN40 | VSS124 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN42 | VSS125 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN43 | VSS126 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN45 | VSS127 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN46 | VSS128 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN48 | VSS129 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN49 | VSS130 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN51 | VSS132 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AN53 | VSS133 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AP40 | VSS137 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT4 | VSS146 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT12 | VSS138 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT16 | VSS139 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT19 | VSS140 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT24 | VSS141 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT27 | VSS142 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT30 | VSS143 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT35 | VSS144 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT38 | VSS145 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT47 | VSS147 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AT52 | VSS148 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AU1 | VSS149 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AU3 | VSS151 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AU24 | VSS150 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AU30 | VSS152 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AU38 | VSS153 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AU51 | VSS154 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV7 | VSS167 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV12 | VSS155 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV13 | VSS156 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV14 | VSS157 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV18 | VSS158 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV19 | VSS159 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV24 | VSS160 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV27 | VSS161 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV30 | VSS162 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV35 | VSS163 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV38 | VSS164 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV47 | VSS165 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AV51 | VSS166 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AW3 | VSS171 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AW13 | VSS168 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AW19 | VSS169 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AW27 | VSS170 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AW35 | VSS172 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AY4 | VSS177 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AY9 | VSS179 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AY10 | VSS173 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AY22 | VSS174 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AY32 | VSS175 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AY36 | VSS176 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | AY50 | VSS178 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA14 | VSS180 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA19 | VSS181 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA22 | VSS182 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA27 | VSS183 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA32 | VSS184 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA35 | VSS185 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA40 | VSS186 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BA53 | VSS187 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BB19 | VSS188 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BB27 | VSS189 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BB35 | VSS190 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BC20 | VSS191 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BC22 | VSS192 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BC26 | VSS193 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BC28 | VSS194 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BC32 | VSS195 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BC34 | VSS196 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BC42 | VSS197 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BD19 | VSS198 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BD24 | VSS199 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BD27 | VSS200 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BD30 | VSS201 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BD35 | VSS202 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BE2 | VSS204 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BE8 | VSS206 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BE19 | VSS203 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BE35 | VSS205 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BF4 | VSS213 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BF12 | VSS207 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BF16 | VSS208 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BF24 | VSS209 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BF30 | VSS211 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BF36 | VSS212 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BF38 | VSS210 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BG31 | VSS214 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BG34 | VSS215 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BG39 | VSS216 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BG42 | VSS217 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BG45 | VSS218 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BG49 | VSS219 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ7 | VSS230 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ11 | VSS220 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ15 | VSS221 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ19 | VSS222 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ23 | VSS223 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ27 | VSS224 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ31 | VSS225 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ35 | VSS226 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ39 | VSS227 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ43 | VSS228 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | BJ47 | VSS229 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | C14 | VSS231 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | C31 | VSS232 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | C34 | VSS233 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | C39 | VSS234 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | C42 | VSS235 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | C45 | VSS236 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | C49 | VSS237 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | D12 | VSS238 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | D16 | VSS239 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | D24 | VSS240 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | D30 | VSS241 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | D36 | VSS242 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | D38 | VSS243 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | E8 | VSS246 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | E19 | VSS244 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | E35 | VSS245 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F2 | VSS248 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F5 | VSS253 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F7 | VSS254 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F19 | VSS247 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F24 | VSS249 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F27 | VSS250 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F30 | VSS251 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | F35 | VSS252 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G10 | VSS255 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G20 | VSS256 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G22 | VSS257 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G26 | VSS258 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G28 | VSS259 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G32 | VSS260 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G34 | VSS261 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | G42 | VSS262 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | H19 | VSS263 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | H27 | VSS264 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | H35 | VSS265 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J1 | VSS266 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J16 | VSS267 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J19 | VSS268 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J22 | VSS269 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J27 | VSS270 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J32 | VSS271 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J35 | VSS272 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J40 | VSS273 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | J53 | VSS274 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | K4 | VSS279 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | K9 | VSS281 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | K14 | VSS275 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | K22 | VSS276 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | K32 | VSS277 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | K36 | VSS278 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | K50 | VSS280 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | L13 | VSS282 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | L19 | VSS283 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | L27 | VSS284 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | L35 | VSS285 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M19 | VSS286 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M26 | VSS287 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M27 | VSS288 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M28 | VSS105 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M34 | VSS289 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M35 | VSS290 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M38 | VSS291 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M47 | VSS292 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | M51 | VSS293 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | N1 | VSS294 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | N16 | VSS295 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | N38 | VSS296 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | N51 | VSS297 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P4 | VSS306 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P9 | VSS309 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P13 | VSS298 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P16 | VSS299 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P19 | VSS300 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P20 | VSS301 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P24 | VSS302 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P32 | VSS303 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P35 | VSS304 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P38 | VSS305 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P47 | VSS307 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | P52 | VSS308 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | T40 | VSS310 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U1 | VSS311 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U3 | VSS316 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U5 | VSS326 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U6 | VSS329 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U8 | VSS330 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U9 | VSS331 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U11 | VSS312 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U12 | VSS313 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U14 | VSS314 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U21 | VSS315 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U30 | VSS317 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U32 | VSS318 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U40 | VSS319 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U42 | VSS320 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U43 | VSS321 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U45 | VSS322 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U46 | VSS323 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U48 | VSS324 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U49 | VSS325 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U51 | VSS327 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | U53 | VSS328 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V7 | VSS340 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V12 | VSS332 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V16 | VSS333 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V19 | VSS334 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V21 | VSS335 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V35 | VSS336 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V40 | VSS337 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V44 | VSS338 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | V51 | VSS339 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y7 | VSS349 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y9 | VSS350 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y10 | VSS341 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y14 | VSS342 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y16 | VSS343 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y21 | VSS344 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y25 | VSS345 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y33 | VSS346 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y41 | VSS347 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | | Y44 | VSS348 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference for the Intel Atom E3825 SoC across multiple power domains and functional blocks. | </details> <details> <summary><b>MEM2</b> - MT41K256M16HA-125:E ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | C1 | VDDQ2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | R1 | VDD7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | B2 | VDD8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | D2 | VDDQ9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | H2 | VDDQ4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | K2 | VDD9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | G7 | VDD1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | A8 | VDDQ5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | K8 | VDD2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | C9 | VDDQ6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | N1 | VDD6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | F1 | VDDQ3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | D9 | VDD4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | E9 | VDDQ7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | H9 | VDDQ8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | N9 | VDD3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | R9 | VDD5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | B1 | VSSQ1 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | D1 | VSSQ2 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | E1 | VSS1 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | G1 | VSSQ3 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | M1 | VSS2 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | P1 | VSS3 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | T1 | VSS4 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | E2 | VSSQ4 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | J2 | VSS5 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | B3 | VSS6 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | D8 | VSSQ5 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | E8 | VSSQ6 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | G8 | VSS7 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | J8 | VSS8 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | A9 | VSS9 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | B9 | VSSQ7 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | F9 | VSSQ8 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | G9 | VSSQ9 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | M9 | VSS10 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | P9 | VSS11 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | T9 | VSS12 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | C7 | DQSU | M_DQS_A_P1 | ✅ | Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P1/M_DQS_A_N1, providing the strobe for upper byte data. | | B7 | /DQSU | M_DQS_A_N1 | ✅ | Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P1/M_DQS_A_N1, providing the strobe for upper byte data. | | D3 | DMU | M_DM_A1 | ✅ | Upper byte data mask pin (DMU) is correctly connected to M_DM_A1, allowing masking of upper byte write data. | | D7 | DQU0 | M_DATA_A9 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | C3 | DQU1 | M_DATA_A10 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | C8 | DQU2 | M_DATA_A8 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | C2 | DQU3 | M_DATA_A11 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | A7 | DQU4 | M_DATA_A13 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | A2 | DQU5 | M_DATA_A15 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | B8 | DQU6 | M_DATA_A12 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | A3 | DQU7 | M_DATA_A14 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[15,13,12,14,11,10,9,8] in non-sequential order, providing bits [15:8] of the 16-bit data bus for MEM2 with intentional routing optimization. | | E3 | DQL0 | M_DATA_A0 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | F7 | DQL1 | M_DATA_A1 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | F2 | DQL2 | M_DATA_A2 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | F8 | DQL3 | M_DATA_A3 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | H3 | DQL4 | M_DATA_A4 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | H8 | DQL5 | M_DATA_A5 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | G2 | DQL6 | M_DATA_A6 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | H7 | DQL7 | M_DATA_A7 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[7:0] in sequential order, providing the lower 8 bits of the 16-bit data bus for MEM2. | | E7 | DML | M_DM_A0 | ✅ | Lower byte data mask pin (DML) is correctly connected to M_DM_A0, allowing masking of lower byte write data. | | F3 | DQSL | M_DQS_A_P0 | ✅ | Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P0/M_DQS_A_N0, providing the strobe for lower byte data. | | G3 | /DQSL | M_DQS_A_N0 | ✅ | Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P0/M_DQS_A_N0, providing the strobe for lower byte data. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ pin is correctly connected to SM_VREF_DQ1_A, which is generated by a resistor divider creating VDIMM/2 as required by the datasheet. | | J1 | NC1__ODT1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | L1 | NC2__/CS1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | J9 | NC3__CKE1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | L9 | NC4__ZQ1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | M7 | NC5 | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM3 for synchronous operation. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM3 for synchronous operation. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination enable pin (ODT) is correctly connected to M_ODT_A0, shared with MEM3 for termination control. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable pin (CKE) is correctly connected to M_CKE_A0, shared with MEM3 for power management control. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select pin (CS#) is correctly connected to M_CS_A_L0, shared with MEM3 to enable both devices simultaneously. | | L3 | /WE | M_WE_A_L | ✅ | Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM3 for command decoding. | | J3 | /RAS | M_RAS_A_L | ✅ | Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM3 for command decoding. | | K3 | /CAS | M_CAS_A_L | ✅ | Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM3 for command decoding. | | L8 | ZQ | M_ZQ1 | ✅ | ZQ calibration pin is correctly connected to M_ZQ1 with a 240Ω resistor (R140) to ground as required by the datasheet. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM3 for bank selection. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM3 for bank selection. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM3 for bank selection. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA pin is correctly connected to SM_VREF_CA1_A, which is generated by a resistor divider creating VDIMM/2 as required by the datasheet. | | N3 | A0 | M_MA_A0 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | P7 | A1 | M_MA_A1 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | P3 | A2 | M_MA_A2 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | N2 | A3 | M_MA_A3 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | P8 | A4 | M_MA_A4 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | P2 | A5 | M_MA_A5 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | R8 | A6 | M_MA_A6 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | R2 | A7 | M_MA_A7 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | T8 | A8 | M_MA_A8 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | R3 | A9 | M_MA_A9 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | R7 | A11 | M_MA_A11 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | T3 | A13 | M_MA_A13 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | T7 | A14 | M_MA_A14 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM3 for row/column addressing. | | T2 | /RESET | M_A_RST_L | ✅ | Reset pin (RESET#) is correctly connected to M_A_RST_L through a 0-ohm resistor (R353), shared with MEM3 for asynchronous reset control. | </details> <details> <summary><b>MEM3</b> - MT41K256M16HA-125:E ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | C1 | VDDQ2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | R1 | VDD7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | B2 | VDD8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | D2 | VDDQ9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | H2 | VDDQ4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | K2 | VDD9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | G7 | VDD1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | A8 | VDDQ5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | K8 | VDD2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | C9 | VDDQ6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | N1 | VDD6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | F1 | VDDQ3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | D9 | VDD4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | E9 | VDDQ7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | H9 | VDDQ8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | N9 | VDD3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | R9 | VDD5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are all correctly connected to +VDIMM, providing 1.35V nominal for DDR3L operation. | | B1 | VSSQ1 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | D1 | VSSQ2 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | E1 | VSS1 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | G1 | VSSQ3 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | M1 | VSS2 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | P1 | VSS3 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | T1 | VSS4 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | E2 | VSSQ4 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | J2 | VSS5 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | B3 | VSS6 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | D8 | VSSQ5 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | E8 | VSSQ6 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | G8 | VSS7 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | J8 | VSS8 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | A9 | VSS9 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | B9 | VSSQ7 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | F9 | VSSQ8 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | G9 | VSSQ9 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | M9 | VSS10 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | P9 | VSS11 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | T9 | VSS12 | GND | ✅ | Ground pins (VSS and VSSQ) are all correctly connected to GND, providing proper ground reference for core logic and I/O signals. | | C7 | DQSU | M_DQS_A_P3 | ✅ | Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P3/M_DQS_A_N3, providing the strobe for upper byte data. | | B7 | /DQSU | M_DQS_A_N3 | ✅ | Upper byte differential data strobe pair (DQSU/DQSU#) is correctly connected to M_DQS_A_P3/M_DQS_A_N3, providing the strobe for upper byte data. | | D3 | DMU | M_DM_A3 | ✅ | Upper byte data mask pin (DMU) is correctly connected to M_DM_A3, allowing masking of upper byte write data. | | D7 | DQU0 | M_DATA_A29 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | C3 | DQU1 | M_DATA_A26 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | C8 | DQU2 | M_DATA_A28 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | C2 | DQU3 | M_DATA_A27 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | A7 | DQU4 | M_DATA_A25 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | A2 | DQU5 | M_DATA_A30 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | B8 | DQU6 | M_DATA_A24 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | A3 | DQU7 | M_DATA_A31 | ✅ | Upper byte data pins (DQU0-DQU7) are connected to M_DATA_A[31,25,24,30,27,26,29,28] in non-sequential order, providing bits [31:24] with intentional routing optimization. | | E3 | DQL0 | M_DATA_A16 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | F7 | DQL1 | M_DATA_A17 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | F2 | DQL2 | M_DATA_A18 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | F8 | DQL3 | M_DATA_A19 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | H3 | DQL4 | M_DATA_A20 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | H8 | DQL5 | M_DATA_A21 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | G2 | DQL6 | M_DATA_A22 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | H7 | DQL7 | M_DATA_A23 | ✅ | Lower byte data pins (DQL0-DQL7) are connected to M_DATA_A[23:16] in sequential order, providing bits [23:16] of the 32-bit data bus. | | E7 | DML | M_DM_A2 | ✅ | Lower byte data mask pin (DML) is correctly connected to M_DM_A2, allowing masking of lower byte write data. | | F3 | DQSL | M_DQS_A_P2 | ✅ | Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P2/M_DQS_A_N2, providing the strobe for lower byte data. | | G3 | /DQSL | M_DQS_A_N2 | ✅ | Lower byte differential data strobe pair (DQSL/DQSL#) is correctly connected to M_DQS_A_P2/M_DQS_A_N2, providing the strobe for lower byte data. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ pin is correctly connected to SM_VREF_DQ1_A, shared with MEM2, providing the required VDIMM/2 reference voltage. | | J1 | NC1__ODT1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | L1 | NC2__/CS1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | J9 | NC3__CKE1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | L9 | NC4__ZQ1_ | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | M7 | NC5 | | ✅ | No-connect pins (NC1-NC5) are correctly left unconnected as specified in the datasheet. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM2 for synchronous operation. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock input pair (CK/CK#) is correctly connected to M_CLK_A_P0/M_CLK_A_N0, shared with MEM2 for synchronous operation. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination enable pin (ODT) is correctly connected to M_ODT_A0, shared with MEM2 for termination control. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable pin (CKE) is correctly connected to M_CKE_A0, shared with MEM2 for power management control. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select pin (CS#) is correctly connected to M_CS_A_L0, shared with MEM2 to enable both devices simultaneously as a single rank. | | L3 | /WE | M_WE_A_L | ✅ | Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM2 for command decoding. | | J3 | /RAS | M_RAS_A_L | ✅ | Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM2 for command decoding. | | K3 | /CAS | M_CAS_A_L | ✅ | Command pins (WE#, RAS#, CAS#) are correctly connected to M_WE_A_L, M_RAS_A_L, M_CAS_A_L, shared with MEM2 for command decoding. | | L8 | ZQ | M_ZQ2 | ✅ | ZQ calibration pin is correctly connected to M_ZQ2 with a 240Ω resistor (R327) to ground as required by the datasheet. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM2 for bank selection. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM2 for bank selection. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address pins (BA0, BA1, BA2) are correctly connected to M_BS_A0, M_BS_A1, M_BS_A2, shared with MEM2 for bank selection. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA pin is correctly connected to SM_VREF_CA1_A, shared with MEM2, providing the required VDIMM/2 reference voltage. | | N3 | A0 | M_MA_A0 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | P7 | A1 | M_MA_A1 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | P3 | A2 | M_MA_A2 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | N2 | A3 | M_MA_A3 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | P8 | A4 | M_MA_A4 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | P2 | A5 | M_MA_A5 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | R8 | A6 | M_MA_A6 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | R2 | A7 | M_MA_A7 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | T8 | A8 | M_MA_A8 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | R3 | A9 | M_MA_A9 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | R7 | A11 | M_MA_A11 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | T3 | A13 | M_MA_A13 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | T7 | A14 | M_MA_A14 | ✅ | Address pins (A0-A14) are correctly connected to M_MA_A0 through M_MA_A14, shared with MEM2 for row/column addressing. | | T2 | /RESET | M_A_RST_L | ✅ | Reset pin (RESET#) is correctly connected to M_A_RST_L, shared with MEM2 for asynchronous reset control. | </details> <details> <summary><b>R140</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001971) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ1 | ✅ | 240-ohm ZQ calibration resistor for DDR3 memory MEM2. Pin 1 connects to M_ZQ1 (MEM2 pin L8 ZQ) and pin 2 connects to GND. | | 2 | 2 | GND | ✅ | 240-ohm ZQ calibration resistor for DDR3 memory MEM2. Pin 1 connects to M_ZQ1 (MEM2 pin L8 ZQ) and pin 2 connects to GND. | </details> <details> <summary><b>R327</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001971) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ2 | ✅ | 240-ohm ZQ calibration resistor for DDR3 memory MEM3. Pin 1 connects to M_ZQ2 (MEM3 pin L8 ZQ) and pin 2 connects to GND. | | 2 | 2 | GND | ✅ | 240-ohm ZQ calibration resistor for DDR3 memory MEM3. Pin 1 connects to M_ZQ2 (MEM3 pin L8 ZQ) and pin 2 connects to GND. | </details> <details> <summary><b>R353</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_A_DRAMRST_L | ✅ | 0-ohm resistor connecting M_A_DRAMRST_L to M_A_RST_L, which drives the /RESET pins of memory devices MEM2 and MEM3. This provides a series connection for the reset signal path. | | 2 | 2 | M_A_RST_L | ✅ | 0-ohm resistor connecting M_A_DRAMRST_L to M_A_RST_L, which drives the /RESET pins of memory devices MEM2 and MEM3. This provides a series connection for the reset signal path. | </details> <details> <summary><b>C374</b> - 123-0001076 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001076) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 10pF capacitor from M_A_RST_L to GND, marked DNI (Do Not Install). When populated, would provide high-frequency filtering on the reset line. | | 2 | 2 | M_A_RST_L | ✅ | 10pF capacitor from M_A_RST_L to GND, marked DNI (Do Not Install). When populated, would provide high-frequency filtering on the reset line. | </details> <details> <summary><b>FL1</b> - 3750-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3750-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CH1-IN | SD3_CD# | ✅ | Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller. | | 2 | CH2-IN | SD3_D2 | ✅ | Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller. | | 3 | CH3-IN | SD3_D3 | ✅ | Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller. | | 4 | CH4-IN | SD3_CMD | ✅ | Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller. | | 5 | CH5-IN | SD3_CLK | ✅ | Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller. | | 6 | CH6-IN | SD3_D0 | ✅ | Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller. | | 7 | CH7-IN | SD3_D1 | ✅ | Input channels for SD card signals (card detect, data lines, command, and clock) are correctly connected to their respective SD signals from the host controller. | | 8 | CH8-IN | | ✅ | Channel 8 input and output are not connected, which is acceptable since only 7 channels are needed for the SD card interface. | | 9 | CH8-OUT | | ✅ | Channel 8 input and output are not connected, which is acceptable since only 7 channels are needed for the SD card interface. | | 10 | CH7-OUT | SD3_D1_R | ✅ | Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2. | | 11 | CH6-OUT | SD3_D0_R | ✅ | Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2. | | 12 | CH5-OUT | SD3_CLK_R | ✅ | Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2. | | 13 | CH4-OUT | SD3_CMD_R | ✅ | Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2. | | 14 | CH3-OUT | SD3_D3_R | ✅ | Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2. | | 15 | CH2-OUT | SD3_D2_R | ✅ | Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2. | | 16 | CH1-OUT | SD3_CD_R | ✅ | Output channels for filtered SD card signals are correctly connected to their respective filtered SD signals going to the SD card connector P2. | | 17 | GND_PAD | GND | ✅ | Ground pad is correctly connected to the main ground net. | </details> <details> <summary><b>P2</b> - SCHA5B0200 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/SCHA5B0200) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | SD3_D2_R | ✅ | SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1. | | 2 | CD/DAT3 | SD3_D3_R | ✅ | SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1. | | 7 | DAT0 | SD3_D0_R | ✅ | SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1. | | 8 | DAT1 | SD3_D1_R | ✅ | SD card data lines (DAT0-DAT3) are correctly connected to filtered SD data signals from the host controller through FL1. | | 3 | CMD | SD3_CMD_R | ✅ | SD card command line is correctly connected to filtered command signal from the host controller through FL1. | | 4 | VDD | +VCC3 | ✅ | SD card power supply is correctly connected to +VCC3 (3.3V) with appropriate decoupling capacitors C159 and C162. | | 5 | CLOCK | SD3_CLK_R | ✅ | SD card clock line is correctly connected to filtered clock signal from the host controller through FL1. | | 6 | VSS | GND | ✅ | SD card ground connections are correctly connected to the main ground net. | | 9 | GND | GND | ✅ | SD card ground connections are correctly connected to the main ground net. | | 10 | CD | SD3_CD_R | ✅ | SD card detect signal is correctly connected to filtered card detect signal from the host controller through FL1. | | 11 | GND3 | FGND-uSD | ✅ | Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes. | | 12 | GND4 | FGND-uSD | ✅ | Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes. | | 15 | GND7 | FGND-uSD | ✅ | Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes. | | 16 | GND8 | FGND-uSD | ✅ | Frame ground connections are intentionally connected to FGND-uSD, separate from main ground, as documented in the schematic notes. | | 13 | GND5 | FGND-uSD-Front | ✅ | Front frame ground connections are intentionally connected to FGND-uSD-Front, separate from main ground, as documented in the schematic notes. | | 14 | GND6 | FGND-uSD-Front | ✅ | Front frame ground connections are intentionally connected to FGND-uSD-Front, separate from main ground, as documented in the schematic notes. | </details> <details> <summary><b>R29</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CEC | ✅ | Pin 1 correctly connected to HDMI_CEC net (CEC_A of U2). | | 2 | 2 | +V1P8S | ✅ | Pin 2 correctly connected to +V1P8S supply, providing a 10kΩ pullup for the CEC_A signal. This external pullup is redundant with the internal 10kΩ pullup in U2 but not incorrect. | </details> <details> <summary><b>R171</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pin 1 correctly connected to +V1P8S supply. | | 2 | 2 | HPD_ENB | ✅ | Pin 2 correctly connected to HPD_ENB net (CT_HPD of U2), providing a 2.2kΩ pullup to enable the load switch and HPD by default. | </details> <details> <summary><b>R30</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCDAT | ✅ | Pin 1 correctly connected to HDMI_DDCDAT net (SDA_A of U2). | | 2 | 2 | +V1P8S | ✅ | Pin 2 correctly connected to +V1P8S supply, providing a 10kΩ pullup for the SDA_A signal. This external pullup is redundant with the internal 10kΩ pullup in U2 but not incorrect. | </details> <details> <summary><b>U2</b> - TPD12S016PW ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/TPD12S016PW) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CEC_A | HDMI_CEC | ✅ | CEC_A pin correctly connected to HDMI_CEC net with external 10kΩ pullup to +V1P8S through R29. The external pullup is redundant with the internal 10kΩ pullup but not incorrect. | | 2 | SCL_A | HDMI_DDCCLK | ✅ | SCL_A pin correctly connected to HDMI_DDCCLK net with external 10kΩ pullup to +V1P8S through R28. The external pullup is redundant with the internal 10kΩ pullup but not incorrect. | | 3 | SDA_A | HDMI_DDCDAT | ✅ | SDA_A pin correctly connected to HDMI_DDCDAT net with external 10kΩ pullup to +V1P8S through R30. The external pullup is redundant with the internal 10kΩ pullup but not incorrect. | | 4 | HPD_A | HDMI_HPD | ✅ | HPD_A pin correctly connected to HDMI_HPD net as the hot plug detect output to the HDMI controller. | | 5 | LS_OE | LS_OE | ✅ | LS_OE pin correctly connected to LS_OE net with external 2.2kΩ pullup to +V1P8S through R172. The external pullup enables the level shifters by default. | | 6 | GND1 | GND | ✅ | Ground pins correctly connected to GND net. | | 14 | GND2 | GND | ✅ | Ground pins correctly connected to GND net. | | 19 | GND3 | GND | ✅ | Ground pins correctly connected to GND net. | | 7 | CEC_B | C_HDMI_CEC | ✅ | CEC_B pin correctly connected to C_HDMI_CEC net, which connects to the HDMI connector CEC pin. | | 8 | SCL_B | C_HDMI_SCL | ✅ | SCL_B pin correctly connected to C_HDMI_SCL net, which connects to the HDMI connector SCL pin. | | 9 | SDA_B | C_HDMI_SDA | ✅ | SDA_B pin correctly connected to C_HDMI_SDA net, which connects to the HDMI connector SDA pin. | | 10 | HPD_B | C_HDMI_HPD | ✅ | HPD_B pin correctly connected to C_HDMI_HPD net, which connects to the HDMI connector hot plug detect pin. | | 11 | VCC5V | +5VSB | ✅ | VCC5V pin correctly connected to +5VSB supply with 0.1µF decoupling capacitor C155. | | 12 | CT_HPD | HPD_ENB | ✅ | CT_HPD pin correctly connected to HPD_ENB net with external 2.2kΩ pullup to +V1P8S through R171. The external pullup enables the load switch and HPD by default. | | 13 | 5V_OUT | +HDMI_CRT_VCC | ✅ | 5V_OUT pin correctly connected to +HDMI_CRT_VCC net with ferrite bead L7 filtering to D5_0V_HDMI and 4.7µF decoupling capacitor C157. | | 15 | CLK- | HDMI_OUT_CLK_DN | ✅ | CLK- and CLK+ pins correctly connected to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets respectively, providing ESD protection for the HDMI TMDS clock signals. | | 16 | CLK+ | HDMI_OUT_CLK_DP | ✅ | CLK- and CLK+ pins correctly connected to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets respectively, providing ESD protection for the HDMI TMDS clock signals. | | 17 | D0- | HDMI_OUT_TX0_DN | ✅ | D0- and D0+ pins correctly connected to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets respectively, providing ESD protection for the HDMI TMDS data 0 signals. | | 18 | D0+ | HDMI_OUT_TX0_DP | ✅ | D0- and D0+ pins correctly connected to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets respectively, providing ESD protection for the HDMI TMDS data 0 signals. | | 20 | D1- | HDMI_OUT_TX1_DN | ✅ | D1- and D1+ pins correctly connected to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets respectively, providing ESD protection for the HDMI TMDS data 1 signals. | | 21 | D1+ | HDMI_OUT_TX1_DP | ✅ | D1- and D1+ pins correctly connected to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets respectively, providing ESD protection for the HDMI TMDS data 1 signals. | | 22 | D2- | HDMI_OUT_TX2_DN | ✅ | D2- and D2+ pins correctly connected to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets respectively, providing ESD protection for the HDMI TMDS data 2 signals. | | 23 | D2+ | HDMI_OUT_TX2_DP | ✅ | D2- and D2+ pins correctly connected to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets respectively, providing ESD protection for the HDMI TMDS data 2 signals. | | 24 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S supply with 0.1µF decoupling capacitor C17. | </details> <details> <summary><b>R28</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCCLK | ✅ | Pin 1 correctly connected to HDMI_DDCCLK net (SCL_A of U2). | | 2 | 2 | +V1P8S | ✅ | Pin 2 correctly connected to +V1P8S supply, providing a 10kΩ pullup for the SCL_A signal. This external pullup is redundant with the internal 10kΩ pullup in U2 but not incorrect. | </details> <details> <summary><b>R172</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pin 1 correctly connected to +V1P8S supply. | | 2 | 2 | LS_OE | ✅ | Pin 2 correctly connected to LS_OE net (LS_OE of U2), providing a 2.2kΩ pullup to enable the level shifters by default. | </details> <details> <summary><b>L16</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX1_C_DN | ✅ | IN1 pin connected to HDMI_TX1_C_DN, the negative side of the TX1 data differential pair after AC coupling. This carries the data signal through the common mode choke. | | 3 | IN2 | HDMI_TX1_C_DP | ✅ | IN2 pin connected to HDMI_TX1_C_DP, the positive side of the TX1 data differential pair after AC coupling. This carries the data signal through the common mode choke. | | 4 | OUT2 | HDMI_OUT_TX1_DP | ✅ | OUT2 pin connected to HDMI_OUT_TX1_DP, outputting the positive side of the TX1 data differential pair to the HDMI translator chip U2 and then to connector P1. | | 6 | OUT1 | HDMI_OUT_TX1_DN | ✅ | OUT1 pin connected to HDMI_OUT_TX1_DN, outputting the negative side of the TX1 data differential pair to the HDMI translator chip U2 and then to connector P1. | </details> <details> <summary><b>L14</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_CLK_C_DN | ✅ | IN1 pin connected to HDMI_CLK_C_DN, the negative side of the clock differential pair after AC coupling. This carries the clock signal through the common mode choke. | | 3 | IN2 | HDMI_CLK_C_DP | ✅ | IN2 pin connected to HDMI_CLK_C_DP, the positive side of the clock differential pair after AC coupling. This carries the clock signal through the common mode choke. | | 4 | OUT2 | HDMI_OUT_CLK_DP | ✅ | OUT2 pin connected to HDMI_OUT_CLK_DP, outputting the positive side of the clock differential pair to the HDMI translator chip U2 and then to connector P1. | | 6 | OUT1 | HDMI_OUT_CLK_DN | ✅ | OUT1 pin connected to HDMI_OUT_CLK_DN, outputting the negative side of the clock differential pair to the HDMI translator chip U2 and then to connector P1. | </details> <details> <summary><b>L17</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX2_C_DN | ✅ | IN1 pin connected to HDMI_TX2_C_DN, the negative side of the TX2 data differential pair after AC coupling. This carries the data signal through the common mode choke. | | 3 | IN2 | HDMI_TX2_C_DP | ✅ | IN2 pin connected to HDMI_TX2_C_DP, the positive side of the TX2 data differential pair after AC coupling. This carries the data signal through the common mode choke. | | 4 | OUT2 | HDMI_OUT_TX2_DP | ✅ | OUT2 pin connected to HDMI_OUT_TX2_DP, outputting the positive side of the TX2 data differential pair to the HDMI translator chip U2 and then to connector P1. | | 6 | OUT1 | HDMI_OUT_TX2_DN | ✅ | OUT1 pin connected to HDMI_OUT_TX2_DN, outputting the negative side of the TX2 data differential pair to the HDMI translator chip U2 and then to connector P1. | </details> <details> <summary><b>L15</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX0_C_DN | ✅ | IN1 pin connected to HDMI_TX0_C_DN, the negative side of the TX0 data differential pair after AC coupling. This carries the data signal through the common mode choke. | | 3 | IN2 | HDMI_TX0_C_DP | ✅ | IN2 pin connected to HDMI_TX0_C_DP, the positive side of the TX0 data differential pair after AC coupling. This carries the data signal through the common mode choke. | | 4 | OUT2 | HDMI_OUT_TX0_DP | ✅ | OUT2 pin connected to HDMI_OUT_TX0_DP, outputting the positive side of the TX0 data differential pair to the HDMI translator chip U2 and then to connector P1. | | 6 | OUT1 | HDMI_OUT_TX0_DN | ✅ | OUT1 pin connected to HDMI_OUT_TX0_DN, outputting the negative side of the TX0 data differential pair to the HDMI translator chip U2 and then to connector P1. | </details> <details> <summary><b>Q101</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | HDMI_TERM | ✅ | Drain pin correctly connected to HDMI_TERM net, which serves as the common termination point for eight 619Ω resistors (R801-R808) connected to HDMI differential signal lines. | | G | GATE | $15N747 | ✅ | Gate pin connected to net $15N747, which connects to +VCC3 through 0Ω resistor R809. While the gate is properly connected to its net, the net name starting with '$' indicates an auto-generated net, suggesting this connection scheme may be incomplete or incorrect. See R809 analysis for the root cause. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND, providing the return path for the low-side switch configuration. | </details> <details> <summary><b>R809</b> - 110-0001853 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $15N747 | ❌ | <details><summary>R809 is a 0Ω resistor connecting Q101 gate to +VCC3 power rail via auto-generated net $15N747. The auto-generated net name and empty PLACE attribute indicate this connection scheme is likely an error. The gate should typically be driven by a control signal to enable/disable the HDMI termination network as needed, rather than being permanently tied to power.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="20.12,37.14,27.62,44.64" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net $15N747, which also connects to Q101 gate pin G <em>(from schematic)</em></li><li>Pin 2 is connected to net +VCC3 <em>(from schematic)</em></li><li>R809 has a value of 0Ω, effectively creating a direct connection between Q101 gate and +VCC3 <em>(from schematic)</em></li><li>The net name $15N747 starts with &#x27;$&#x27;, which in most EDA tools indicates an auto-generated net name created when there is a floating connection or missing net label <em>(reasoning)</em></li><li>R809 has an empty PLACE attribute, suggesting uncertainty about whether this component should be placed or indicating the design is incomplete <em>(from schematic)</em></li><li>With the gate tied directly to +VCC3, Q101 will be permanently enabled whenever +VCC3 is present, making the termination network always active with no independent control <em>(reasoning)</em></li><li>The circuit includes other control signals (LS_OE, HPD_ENB) for the HDMI interface, suggesting that controllable termination would be more consistent with the overall design intent <em>(from schematic)</em></li><li>If permanent enable was the design intent, the gate could be directly connected to +VCC3 without requiring a separate 0Ω resistor and auto-generated net <em>(reasoning)</em></li><li>The combination of auto-generated net name, empty PLACE attribute, and unusual connection scheme indicates this is likely an incomplete or incorrect connection rather than intentional design <em>(reasoning)</em></li></ul></details> | | 2 | 2 | +VCC3 | ❌ | <details><summary>R809 is a 0Ω resistor connecting Q101 gate to +VCC3 power rail via auto-generated net $15N747. The auto-generated net name and empty PLACE attribute indicate this connection scheme is likely an error. The gate should typically be driven by a control signal to enable/disable the HDMI termination network as needed, rather than being permanently tied to power.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="19.21,37.14,26.71,44.64" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net $15N747, which also connects to Q101 gate pin G <em>(from schematic)</em></li><li>Pin 2 is connected to net +VCC3 <em>(from schematic)</em></li><li>R809 has a value of 0Ω, effectively creating a direct connection between Q101 gate and +VCC3 <em>(from schematic)</em></li><li>The net name $15N747 starts with &#x27;$&#x27;, which in most EDA tools indicates an auto-generated net name created when there is a floating connection or missing net label <em>(reasoning)</em></li><li>R809 has an empty PLACE attribute, suggesting uncertainty about whether this component should be placed or indicating the design is incomplete <em>(from schematic)</em></li><li>With the gate tied directly to +VCC3, Q101 will be permanently enabled whenever +VCC3 is present, making the termination network always active with no independent control <em>(reasoning)</em></li><li>The circuit includes other control signals (LS_OE, HPD_ENB) for the HDMI interface, suggesting that controllable termination would be more consistent with the overall design intent <em>(from schematic)</em></li><li>If permanent enable was the design intent, the gate could be directly connected to +VCC3 without requiring a separate 0Ω resistor and auto-generated net <em>(reasoning)</em></li><li>The combination of auto-generated net name, empty PLACE attribute, and unusual connection scheme indicates this is likely an incomplete or incorrect connection rather than intentional design <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R805</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DN | ✅ | Connected to HDMI_TX0_C_DN signal line, providing DC restoration path for the negative differential signal of HDMI data channel 0. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled. | </details> <details> <summary><b>R802</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DP | ✅ | Connected to HDMI_TX2_C_DP signal line, providing DC restoration path for the positive differential signal of HDMI data channel 2. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled. | </details> <details> <summary><b>R801</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DN | ✅ | Connected to HDMI_TX2_C_DN signal line, providing DC restoration path for the negative differential signal of HDMI data channel 2. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101 to provide DC bias for HDMI signals. | </details> <details> <summary><b>R806</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DP | ✅ | Connected to HDMI_TX0_C_DP signal line, providing DC restoration path for the positive differential signal of HDMI data channel 0. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled. | </details> <details> <summary><b>R807</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CLK_C_DP | ✅ | Connected to HDMI_CLK_C_DP signal line, providing DC restoration path for the positive differential clock signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled. | </details> <details> <summary><b>R808</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CLK_C_DN | ✅ | Connected to HDMI_CLK_C_DN signal line, providing DC restoration path for the negative differential clock signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled. | </details> <details> <summary><b>R804</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DP | ✅ | Connected to HDMI_TX1_C_DP signal line, providing DC restoration path for the positive differential signal of HDMI data channel 1. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled. | </details> <details> <summary><b>R803</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DN | ✅ | Connected to HDMI_TX1_C_DN signal line, providing DC restoration path for the negative differential signal of HDMI data channel 1. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, providing DC bias path when Q101 is enabled. | </details> <details> <summary><b>P1</b> - 158-0004513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/158-0004513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | HPLG | C_HDMI_HPD | ✅ | Hot plug detect signal correctly routed through translator IC U2 to system HPD signal. | | 2 | NC | | ✅ | No connect pin correctly left unconnected. | | 3 | DAT2+ | HDMI_OUT_TX2_DP | ✅ | Data channel 2 positive differential signal correctly routed through common mode choke L17 and translator U2 with AC coupling and termination. | | 4 | DAT2_S | GND | ✅ | Data channel 2 shield correctly connected to ground. | | 5 | DAT2- | HDMI_OUT_TX2_DN | ✅ | Data channel 2 negative differential signal correctly routed through common mode choke L17 and translator U2 with AC coupling and termination. | | 6 | DAT1+ | HDMI_OUT_TX1_DP | ✅ | Data channel 1 positive differential signal correctly routed through common mode choke L16 and translator U2 with AC coupling and termination. | | 7 | DAT1_S | GND | ✅ | Data channel 1 shield correctly connected to ground. | | 8 | DAT1- | HDMI_OUT_TX1_DN | ✅ | Data channel 1 negative differential signal correctly routed through common mode choke L16 and translator U2 with AC coupling and termination. | | 9 | DAT0+ | HDMI_OUT_TX0_DP | ✅ | Data channel 0 positive differential signal correctly routed through common mode choke L15 and translator U2 with AC coupling and termination. | | 10 | DAT0_S | GND | ✅ | Data channel 0 shield correctly connected to ground. | | 11 | DAT0- | HDMI_OUT_TX0_DN | ✅ | Data channel 0 negative differential signal correctly routed through common mode choke L15 and translator U2 with AC coupling and termination. | | 12 | CLK+ | HDMI_OUT_CLK_DP | ✅ | Clock positive differential signal correctly routed through common mode choke L14 and translator U2 with AC coupling and termination. | | 13 | CLK_S | GND | ✅ | Clock shield correctly connected to ground. | | 14 | CLK- | HDMI_OUT_CLK_DN | ✅ | Clock negative differential signal correctly routed through common mode choke L14 and translator U2 with AC coupling and termination. | | 15 | CEC | C_HDMI_CEC | ✅ | CEC signal correctly routed through translator IC U2 with appropriate pullup resistor. | | 16 | DDC/CEC_GND | GND | ✅ | DDC/CEC ground correctly connected to system ground. | | 17 | SCL | C_HDMI_SCL | ✅ | DDC I2C clock signal correctly routed through translator IC U2 with appropriate pullup resistor. | | 18 | SDA | C_HDMI_SDA | ✅ | DDC I2C data signal correctly routed through translator IC U2 with appropriate pullup resistor. | | 19 | +5V | D5_0V_HDMI | ✅ | +5V power supply correctly routed through translator IC U2 with current limiting and filtering via ferrite bead L7. | | 20 | MTG1 | GND_EARTH | ✅ | Mounting tabs correctly connected to earth ground for shielding and EMI control. | | 21 | MTG2 | GND_EARTH | ✅ | Mounting tabs correctly connected to earth ground for shielding and EMI control. | | 22 | MTG3 | GND_EARTH | ✅ | Mounting tabs correctly connected to earth ground for shielding and EMI control. | | 23 | MTG4 | GND_EARTH | ✅ | Mounting tabs correctly connected to earth ground for shielding and EMI control. | </details> <details> <summary><b>L7</b> - BLM18KG221SN1D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/ferriteBeadInductortypefilter/ENFA0003_PDF_FERRITEBEADINDUCTORTYPEFILTER?lastModifiedDatetime=20250707190934) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BLM18KG221SN1D) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +HDMI_CRT_VCC | ✅ | Pin 1 (P1) connects to +HDMI_CRT_VCC from U2 pin 13 (5V_OUT). This is the input side of the ferrite bead filter. | | 2 | P2 | D5_0V_HDMI | ✅ | Pin 2 (P2) connects to D5_0V_HDMI which goes to the HDMI connector P1 pin 19 (+5V). This is the output side of the ferrite bead filter. | </details> <details> <summary><b>C157</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +HDMI_CRT_VCC | ✅ | Pin 1 connects to +HDMI_CRT_VCC from U2 pin 13 (5V_OUT). This provides decoupling for the 5V output before the ferrite bead filter. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This completes the decoupling capacitor connection to ground. | </details> <details> <summary><b>C161</b> - 2267-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2267-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to the main circuit ground (GND). This is one side of the safety/isolation capacitor. | | 2 | 2 | GND_EARTH | ✅ | Pin 2 is correctly connected to chassis/earth ground (GND_EARTH). This completes the safety/isolation capacitor connection between circuit ground and chassis ground. | </details> <details> <summary><b>R116</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB_HOST_BUFF_ENB | ✅ | Pull-up resistor correctly configured to enable the level translator by default. | | 2 | 2 | +V1P8A | ✅ | Pull-up resistor correctly configured to enable the level translator by default. | </details> <details> <summary><b>R117</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pull-down resistor correctly connected to set default disabled state for USB channel 2 enable signal. | | 2 | 2 | SOC_USB_HOST_EN1 | ✅ | Pull-down resistor correctly connected to set default disabled state for USB channel 2 enable signal. | </details> <details> <summary><b>U32</b> - AP2172MPG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP2162_72.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/AP2172MPG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | IN | +USBVCC | ✅ | Input power pin correctly connected to +USBVCC with appropriate bypass capacitors. | | 3 | EN1 | USB_HOST_EN0 | ✅ | Enable input for channel 1 correctly connected to level-translated enable signal from SOC. | | 4 | EN2 | USB_HOST_EN1 | ✅ | Enable input for channel 2 correctly connected to level-translated enable signal from SOC. | | 5 | OC2# | SOC_USB_HOST_OC1 | ✅ | Overcurrent flag output for channel 2 connected to SOC without visible external pull-up resistor. This open-drain output requires a pull-up resistor per datasheet, which may be provided internally by the SOC but should be verified. | | 6 | OUTB | USBP2 | ✅ | Output power pin for channel 2 correctly connected through ferrite bead to VBUS2 with appropriate output capacitors. | | 7 | OUTA | USBP1 | ✅ | Output power pin for channel 1 correctly connected through ferrite bead to VBUS1 with appropriate output capacitors. | | 8 | OC1# | SOC_USB_HOST_OC0 | ✅ | Overcurrent flag output for channel 1 connected to SOC without visible external pull-up resistor. This open-drain output requires a pull-up resistor per datasheet, which may be provided internally by the SOC but should be verified. | | 9 | GND_PAD | GND | ✅ | Exposed pad correctly connected to GND for thermal management. | </details> <details> <summary><b>U4</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | USB_HOST_EN0 | ✅ | B-side I/O pin correctly connected to drive USB power switch enable signal. | | 2 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 3 | VCCA | +V1P8A | ✅ | A-side supply voltage correctly connected to +V1P8A for SOC-side level translation. | | 4 | A2 | SOC_USB_HOST_EN0 | ✅ | A-side I/O pin correctly connected to receive enable signal from SOC. | | 5 | A1 | SOC_USB_HOST_EN1 | ✅ | A-side I/O pin correctly connected to receive enable signal from SOC with pull-down resistor. | | 6 | OE | USB_HOST_BUFF_ENB | ✅ | Output enable pin correctly connected with pull-up resistor to enable the level translator by default. | | 7 | VCCB | +USBVCC | ✅ | B-side supply voltage correctly connected to +USBVCC for USB power switch level translation. | | 8 | B1 | USB_HOST_EN1 | ✅ | B-side I/O pin correctly connected to drive USB power switch enable signal. | </details> <details> <summary><b>C191</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXN0 | ✅ | Connected to USB3_TXN0 from the SOC, this is the input side of the AC coupling capacitor for the negative USB3 TX signal. | | 2 | 2 | USB3_TX0N-R | ✅ | Connected to USB3_TX0N-R going to CHOKE2, this is the output side of the AC coupling capacitor for the negative USB3 TX signal. | </details> <details> <summary><b>C192</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXP0 | ✅ | Connected to USB3_TXP0 from the SOC, this is the input side of the AC coupling capacitor for the positive USB3 TX signal. | | 2 | 2 | USB3_TX0P-R | ✅ | Connected to USB3_TX0P-R going to CHOKE2, this is the output side of the AC coupling capacitor for the positive USB3 TX signal. | </details> <details> <summary><b>U29</b> - TPD4USB30 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/TPD4USB30) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D1+ | USB3_TX0P_C | ✅ | D1+ provides ESD protection for the positive USB3 TX signal (USB3_TX0P_C). Connected between the common mode choke output and the USB connector. | | 2 | D1- | USB3_TX0N_C | ✅ | D1- provides ESD protection for the negative USB3 TX signal (USB3_TX0N_C). Connected between the common mode choke output and the USB connector. | | 3 | GND1 | GND | ✅ | GND1 is properly connected to the GND net, providing a ground reference for the ESD protection device. | | 4 | D2+ | USB3_RX0P_C | ✅ | D2+ provides ESD protection for the positive USB3 RX signal (USB3_RX0P_C). Connected between the USB connector and the common mode choke input. | | 5 | D2- | USB3_RX0N_C | ✅ | D2- provides ESD protection for the negative USB3 RX signal (USB3_RX0N_C). Connected between the USB connector and the common mode choke input. | | 6 | NC4 | USB3_RX0N_C | ✅ | NC4 is connected to the same net as D2- (USB3_RX0N_C), likely providing additional ESD protection or capacitance for the negative RX signal. | | 7 | NC3 | USB3_RX0P_C | ✅ | NC3 is connected to the same net as D2+ (USB3_RX0P_C), likely providing additional ESD protection or capacitance for the positive RX signal. | | 8 | GND2 | GND | ✅ | GND2 is properly connected to the GND net, providing a ground reference for the ESD protection device. | | 9 | NC2 | USB3_TX0N_C | ✅ | NC2 is connected to the same net as D1- (USB3_TX0N_C), likely providing additional ESD protection or capacitance for the negative TX signal. | | 10 | NC1 | USB3_TX0P_C | ✅ | NC1 is connected to the same net as D1+ (USB3_TX0P_C), likely providing additional ESD protection or capacitance for the positive TX signal. | </details> <details> <summary><b>CHOKE2</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_TX0P-R | ✅ | IN1 receives the positive USB3 TX signal (USB3_TX0P-R) after AC coupling through C192. This is the input to the common mode choke for the positive differential signal. | | 3 | IN2 | USB3_TX0N-R | ✅ | IN2 receives the negative USB3 TX signal (USB3_TX0N-R) after AC coupling through C191. This is the input to the common mode choke for the negative differential signal. | | 4 | OUT2 | USB3_TX0N_C | ✅ | OUT2 outputs the filtered negative USB3 TX signal (USB3_TX0N_C) to the ESD protection device U29. This is the output from the common mode choke for the negative differential signal. | | 6 | OUT1 | USB3_TX0P_C | ✅ | OUT1 outputs the filtered positive USB3 TX signal (USB3_TX0P_C) to the ESD protection device U29. This is the output from the common mode choke for the positive differential signal. | </details> <details> <summary><b>CHOKE1</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_RX0N_C | ✅ | IN1 receives the negative USB3 RX signal (USB3_RX0N_C) from the ESD protection device U29. This is the input to the common mode choke for the negative differential signal. | | 3 | IN2 | USB3_RX0P_C | ✅ | IN2 receives the positive USB3 RX signal (USB3_RX0P_C) from the ESD protection device U29. This is the input to the common mode choke for the positive differential signal. | | 4 | OUT2 | USB3_RXP0 | ✅ | OUT2 outputs the filtered positive USB3 RX signal (USB3_RXP0) to the SOC. This is the output from the common mode choke for the positive differential signal. | | 6 | OUT1 | USB3_RXN0 | ✅ | OUT1 outputs the filtered negative USB3 RX signal (USB3_RXN0) to the SOC. This is the output from the common mode choke for the negative differential signal. | </details> <details> <summary><b>U9</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H0 | ✅ | D+ pin is connected to USB_H0, providing ESD protection for the USB 2.0 D+ data line between the common mode choke and USB connector. | | 2 | D- | USB_L0 | ✅ | D- pin is connected to USB_L0, providing ESD protection for the USB 2.0 D- data line between the common mode choke and USB connector. | | 3 | ID | | ✅ | ID pin is left unconnected, which is acceptable per the datasheet for non-OTG USB implementations. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the ground plane. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as it is not internally connected per the datasheet. | | 6 | VBUS | VBUS1 | ✅ | VBUS pin is connected to VBUS1, providing ESD protection for the USB power line with proper filtering through ferrite bead L1 and decoupling capacitors. | </details> <details> <summary><b>CHOKE4</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN0 | ✅ | IN1 is connected to USB_DN0, which is the USB 2.0 D- signal input to the common mode choke. | | 3 | IN2 | USB_DP0 | ✅ | IN2 is connected to USB_DP0, which is the USB 2.0 D+ signal input to the common mode choke. | | 4 | OUT2 | USB_H0 | ✅ | OUT2 is connected to USB_H0, which routes to the D+ pin of ESD protection device U9 and the DA+ pin of USB connector USB1. | | 6 | OUT1 | USB_L0 | ✅ | OUT1 is connected to USB_L0, which routes to the D- pin of ESD protection device U9 and the DA- pin of USB connector USB1. | </details> <details> <summary><b>U8</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H1 | ✅ | D+ pin providing ESD protection for USB high-speed differential data line. Connected to USB_H1 which carries the D+ signal for USB port B. | | 2 | D- | USB_L1 | ✅ | D- pin providing ESD protection for USB high-speed differential data line. Connected to USB_L1 which carries the D- signal for USB port B. | | 3 | ID | | ✅ | ID pin for USB OTG identification, left unconnected. This is acceptable per datasheet as the ID pin can be left floating if not used. | | 4 | GND | GND | ✅ | Ground pin, correctly connected to the GND net for proper ESD protection operation. | | 5 | NC | | ✅ | NC (Not Connected) pin, correctly left unconnected as it is not internally connected within the device. | | 6 | VBUS | VBUS2 | ✅ | VBUS pin providing ESD protection for the USB power line. Connected to VBUS2 which supplies power to USB port B through ferrite bead L2. | </details> <details> <summary><b>CHOKE3</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN1 | ✅ | Input 1 of common mode choke, connected to USB_DN1 (USB D- signal for port 1). This forms one half of the USB 2.0 differential pair input. | | 3 | IN2 | USB_DP1 | ✅ | Input 2 of common mode choke, connected to USB_DP1 (USB D+ signal for port 1). This forms the other half of the USB 2.0 differential pair input. | | 4 | OUT2 | USB_H1 | ✅ | Output 2 of common mode choke, connected to USB_H1 (USB D+ signal after filtering). This output goes to ESD protection device U8. | | 6 | OUT1 | USB_L1 | ✅ | Output 1 of common mode choke, connected to USB_L1 (USB D- signal after filtering). This output goes to ESD protection device U8. | </details> <details> <summary><b>FB13</b> - 3044-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3044-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input pin connected to +5VSB standby power rail, providing source power for the USB power supply. | | 2 | 2 | +USBVCC | ✅ | Output pin connected to +USBVCC, providing filtered USB power supply to the USB power switch (U32) and level shifter (U4). | </details> <details> <summary><b>L1</b> - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP1 | ✅ | Input pin connected to USBP1, receiving switched USB power from the first channel of the AP2172MPG power switch. | | 2 | 2 | VBUS1 | ✅ | Output pin connected to VBUS1, providing filtered USB power to USB port 1. Note that the bulk capacitance on VBUS1 is insufficient for USB specification compliance. | </details> <details> <summary><b>L2</b> - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP2 | ✅ | Input pin connected to USBP2, receiving switched USB power from the second channel of the AP2172MPG power switch. | | 2 | 2 | VBUS2 | ✅ | Output pin connected to VBUS2, providing filtered USB power to USB port 2. Note that the bulk capacitance on VBUS2 is insufficient for USB specification compliance. | </details> <details> <summary><b>C91</b> - 123-0001176 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ❌ | <details><summary>Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="55.34,46.84,62.84,54.34" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to VBUS1 <em>(from schematic)</em></li><li>C91 is a 22uF capacitor providing bulk decoupling for VBUS1 <em>(from schematic)</em></li><li>The component attributes show PartDescription &#x27;22uF 20% 6.3V 0805&#x27;, indicating a 6.3V voltage rating <em>(from schematic)</em></li><li>The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) <em>(reasoning)</em></li><li>USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads <em>(reasoning)</em></li><li>The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF <em>(reasoning)</em></li><li>The capacitance should be increased to at least 120uF per port to meet USB specification requirements <em>(reasoning)</em></li></ul></details> | | 2 | 2 | VBUS1 | ❌ | <details><summary>Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="55.34,46.25,62.84,53.75" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to VBUS1 <em>(from schematic)</em></li><li>C91 is a 22uF capacitor providing bulk decoupling for VBUS1 <em>(from schematic)</em></li><li>The component attributes show PartDescription &#x27;22uF 20% 6.3V 0805&#x27;, indicating a 6.3V voltage rating <em>(from schematic)</em></li><li>The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) <em>(reasoning)</em></li><li>USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads <em>(reasoning)</em></li><li>The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF <em>(reasoning)</em></li><li>The capacitance should be increased to at least 120uF per port to meet USB specification requirements <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>C103</b> - 123-0001176 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ❌ | <details><summary>Bulk decoupling capacitor for VBUS2 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="58.06,46.84,65.56,54.34" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to VBUS2 <em>(from schematic)</em></li><li>C103 is a 22uF capacitor providing bulk decoupling for VBUS2 <em>(from schematic)</em></li><li>The component attributes show PartDescription &#x27;22uF 20% 6.3V 0805&#x27;, indicating a 6.3V voltage rating <em>(from schematic)</em></li><li>The total capacitance on VBUS2 is approximately 22.2uF, including C103 (22uF), C70 (0.1uF), and C234 (0.1uF) <em>(reasoning)</em></li><li>USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads <em>(reasoning)</em></li><li>The total capacitance of 22.2uF on VBUS2 represents only 18.5% of the USB specification requirement of 120uF <em>(reasoning)</em></li><li>The capacitance should be increased to at least 120uF per port to meet USB specification requirements <em>(reasoning)</em></li></ul></details> | | 2 | 2 | VBUS2 | ❌ | <details><summary>Bulk decoupling capacitor for VBUS2 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="58.06,46.25,65.56,53.75" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to VBUS2 <em>(from schematic)</em></li><li>C103 is a 22uF capacitor providing bulk decoupling for VBUS2 <em>(from schematic)</em></li><li>The component attributes show PartDescription &#x27;22uF 20% 6.3V 0805&#x27;, indicating a 6.3V voltage rating <em>(from schematic)</em></li><li>The total capacitance on VBUS2 is approximately 22.2uF, including C103 (22uF), C70 (0.1uF), and C234 (0.1uF) <em>(reasoning)</em></li><li>USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads <em>(reasoning)</em></li><li>The total capacitance of 22.2uF on VBUS2 represents only 18.5% of the USB specification requirement of 120uF <em>(reasoning)</em></li><li>The capacitance should be increased to at least 120uF per port to meet USB specification requirements <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>USB1</b> - 258-0004503 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0004503) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUSA | VBUS1 | ✅ | VBUSA provides 5V power to USB port A. Power is sourced from U32 power switch through ferrite bead L1, with ESD protection from U9 and multiple bypass capacitors. | | 2 | DA- | USB_L0 | ✅ | DA- is the USB 2.0 D- signal for port A. Signal is routed through common mode choke CHOKE4 and protected by ESD device U9. | | 3 | DA+ | USB_H0 | ✅ | DA+ is the USB 2.0 D+ signal for port A. Signal is routed through common mode choke CHOKE4 and protected by ESD device U9. | | 4 | GNDA | GND | ✅ | GNDA is the ground reference for USB port A, connected to the main GND net. | | 5 | SSRX- | USB3_RX0N_C | ✅ | SSRX- is the USB 3.0 SuperSpeed receive negative signal for port A. Signal is routed through common mode choke CHOKE1 and protected by ESD device U29. | | 6 | SSRX+ | USB3_RX0P_C | ✅ | SSRX+ is the USB 3.0 SuperSpeed receive positive signal for port A. Signal is routed through common mode choke CHOKE1 and protected by ESD device U29. | | 7 | GND_DRAIN | GND | ✅ | GND_DRAIN is a drain/shield ground connection, connected to the main GND net. | | 8 | SSTX- | USB3_TX0N_C | ✅ | SSTX- is the USB 3.0 SuperSpeed transmit negative signal for port A. Signal is routed through common mode choke CHOKE2 with AC coupling capacitor C191 and protected by ESD device U29. | | 9 | SSTX+ | USB3_TX0P_C | ✅ | SSTX+ is the USB 3.0 SuperSpeed transmit positive signal for port A. Signal is routed through common mode choke CHOKE2 with AC coupling capacitor C192 and protected by ESD device U29. | | 10 | VBUSB | VBUS2 | ✅ | VBUSB provides 5V power to USB port B. Power is sourced from U32 power switch through ferrite bead L2, with ESD protection from U8 and multiple bypass capacitors. | | 11 | DB- | USB_L1 | ✅ | DB- is the USB 2.0 D- signal for port B. Signal is routed through common mode choke CHOKE3 and protected by ESD device U8. | | 12 | DB+ | USB_H1 | ✅ | DB+ is the USB 2.0 D+ signal for port B. Signal is routed through common mode choke CHOKE3 and protected by ESD device U8. | | 13 | GNDB | GND | ✅ | GNDB is the ground reference for USB port B, connected to the main GND net. | | MH1 | SHIELD1 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity. | | MH2 | SHIELD2 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity. | | MH3 | SHIELD3 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity. | | MH4 | SHIELD4 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH net, which is isolated from main GND. This provides shield grounding with optional capacitive coupling through C211 (DNI) for conducted immunity. | </details> <details> <summary><b>C211</b> - 123-0004408 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0004408) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to main GND net. This capacitor provides optional capacitive coupling between main ground and shield ground for conducted immunity. | | 2 | 2 | GND_EARTH | ✅ | Connected to GND_EARTH net (USB shield ground). This capacitor provides optional capacitive coupling between shield ground and main ground for conducted immunity. | </details> <details> <summary><b>J10</b> - 5177985-2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/5177985-2) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 2 | 2 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 13 | 13 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 14 | 14 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 25 | 25 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 26 | 26 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 37 | 37 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 38 | 38 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 49 | 49 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 50 | 50 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 59 | 59 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 60 | 60 | GND | ✅ | Ground pins correctly connected to GND net. Multiple ground pins provide low impedance return path and mechanical stability. | | 3 | 3 | mSATA_TX_P | ✅ | mSATA transmit positive differential signal, part of SATA TX pair with pin 5. | | 4 | 4 | mSATA_RX_P | ✅ | mSATA receive positive differential signal, part of SATA RX pair with pin 6. | | 5 | 5 | mSATA_TX_N | ✅ | mSATA transmit negative differential signal, part of SATA TX pair with pin 3. | | 6 | 6 | mSATA_RX_N | ✅ | mSATA receive negative differential signal, part of SATA RX pair with pin 4. | | 7 | 7 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 8 | 8 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 19 | 19 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 20 | 20 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 31 | 31 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 32 | 32 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 43 | 43 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 44 | 44 | +5VSB | ✅ | 5V standby power pins correctly connected to +5VSB net. Multiple power pins distribute current and reduce impedance. | | 9 | 9 | mPCIE_REFCLK_P | ✅ | mPCIE reference clock positive differential signal, part of REFCLK pair with pin 11. Test point TP19 is DNI. | | 10 | 10 | USB_HOST_DP | ✅ | USB host data positive signal, part of USB differential pair with pin 12. | | 11 | 11 | mPCIE_REFCLK_N | ✅ | mPCIE reference clock negative differential signal, part of REFCLK pair with pin 9. Test point TP20 is DNI. | | 12 | 12 | USB_HOST_DN | ✅ | USB host data negative signal, part of USB differential pair with pin 10. | | 15 | 15 | mPCIE_TX_P | ✅ | mPCIE transmit positive differential signal, part of PCIe TX pair with pin 17. Test point TP21 is DNI. | | 16 | 16 | mPCIE_RX_N | ✅ | mPCIE receive differential pair with intentional polarity inversion. Pin 16 carries negative signal (mPCIE_RX_N) and pin 18 carries positive signal (mPCIE_RX_P). This inversion is noted as intentional for routing ease and is acceptable in PCIe. | | 18 | 18 | mPCIE_RX_P | ✅ | mPCIE receive differential pair with intentional polarity inversion. Pin 16 carries negative signal (mPCIE_RX_N) and pin 18 carries positive signal (mPCIE_RX_P). This inversion is noted as intentional for routing ease and is acceptable in PCIe. | | 17 | 17 | mPCIE_TX_N | ✅ | mPCIE transmit negative differential signal, part of PCIe TX pair with pin 15. Test point TP22 is DNI. | | 21 | 21 | I2C6_SCL | ✅ | I2C clock line with 10K pull-up resistor to +V1P8S through R13. | | 22 | 22 | mPCIE_WAKEB | ✅ | mPCIE wake signal (active low) for power management. | | 23 | 23 | I2C6_SDA | ✅ | I2C data line with 10K pull-up resistor to +V1P8S through R14. | | 24 | 24 | mPCIe_CLKREQ3_B | ✅ | mPCIE clock request signal (active low) for power management. | | 27 | 27 | EXP_GPIO1 | ✅ | Expansion GPIO signals for general purpose I/O. | | 28 | 28 | EXP_GPIO3 | ✅ | Expansion GPIO signals for general purpose I/O. | | 29 | 29 | EXP_GPIO2 | ✅ | Expansion GPIO signals for general purpose I/O. | | 30 | 30 | EXP_GPIO4 | ✅ | Expansion GPIO signals for general purpose I/O. | | 33 | 33 | XDP_H_OBSDATA_A1 | ✅ | XDP observation data signals for debug functionality. | | 34 | 34 | XDP_H_OBSDATA_A0 | ✅ | XDP observation data signals for debug functionality. | | 35 | 35 | XDP_H_OBSDATA_A2 | ✅ | XDP observation data signals for debug functionality. | | 36 | 36 | XDP_H_OBSDATA_A3 | ✅ | XDP observation data signals for debug functionality. | | 39 | 39 | XDP_H_PRDYB | ✅ | XDP ready signal (active low) for debug handshaking. | | 40 | 40 | XDP_H_PREQB_PB | ✅ | XDP request signal (active low) buffered through U1 with 200 ohm pull-up to +V1P8A. | | 41 | 41 | HOOK0 | ✅ | HOOK0 signal connected through 1K series resistor R15 to PMC_RSMRST. | | 42 | 42 | HOOK1 | ✅ | HOOK1 signal connected through 0 ohm resistor R5 to FP_PWRBTN. Optional 4.7K pull-down R4 is DNI. | | 45 | 45 | HOOK2 | ✅ | HOOK2 signal connected through 1K series resistor R16 to PMC_CORE_PWROK. | | 46 | 46 | PMC_RSTBTN | ✅ | Reset button signal with 1K pull-up to +V1P8S through R6 and 0.1uF debounce capacitor C1 to ground. | | 47 | 47 | HOOK6 | ✅ | HOOK6 signal connected through 1K series resistor R17 to PMC_PLTRST_R_V1P8. | | 48 | 48 | ILB_RTC_TESTB | ✅ | RTC test signal (active low) with 1K pull-up to +RTCVCC through R7 and 1uF filter capacitor C2 to ground. | | 51 | 51 | HOOK4 | ✅ | HOOK4 signal connected through 0 ohm resistor R18 to +3VSB power rail. | | 52 | 52 | XDP_H_TRSTB | ✅ | XDP test reset signal (active low) for JTAG debug interface. | | 53 | 53 | HOOK5 | ✅ | HOOK5 signal connected through 0 ohm resistor R20 to +V1P8S power rail. | | 54 | 54 | XDP_H_TCK | ✅ | XDP test clock signal for JTAG debug interface. | | 55 | 55 | +V1P8A | ✅ | 1.8V analog power supply pin with decoupling capacitor C5 nearby. | | 56 | 56 | XDP_H_TMS | ✅ | XDP test mode select signal for JTAG debug interface. | | 57 | 57 | XDP_H_TDO | ✅ | XDP test data output signal with 51 ohm series termination resistor R21 from +V1P8A. | | 58 | 58 | XDP_H_TDI | ✅ | XDP test data input signal for JTAG debug interface. | </details> <details> <summary><b>R3</b> - 200 ohm resistor ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XDP_H_PREQB_PB | ✅ | Connected to XDP_H_PREQB_PB signal, providing pull-up function for the buffer input. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A supply, providing the pull-up voltage source. | </details> <details> <summary><b>U1</b> - SN74AUP1G34 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74aup1g34) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/SN74AUP1G34) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin is correctly left unconnected per datasheet specification. | | 2 | A | XDP_H_PREQB_PB | ✅ | Input pin A is connected to XDP_H_PREQB_PB signal with a 200 ohm pull-up resistor (R3) to +V1P8A, which is appropriate for this buffer application. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | XDP_H_PREQB | ✅ | Output pin Y is connected to XDP_H_PREQB net, correctly buffering the input signal. | | 5 | VCC | +V1P8A | ✅ | VCC pin is connected to +V1P8A (1.8V analog supply) with appropriate bypass capacitor C5 (0.1uF) nearby. | </details> <details> <summary><b>R14</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SDA | ✅ | Pin 1 connects to I2C6_SDA and serves as one end of the pull-up resistor for the I2C data line. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C6_SDA line. | </details> <details> <summary><b>R13</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SCL | ✅ | Pin 1 connects to I2C6_SCL and serves as one end of the pull-up resistor for the I2C clock line. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C6_SCL line. | </details> <details> <summary><b>C1</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal for debouncing and filtering. Works in conjunction with pull-up resistor R6. | | 2 | 2 | GND | ✅ | Connected to GND, completing the debouncing filter to ground. The 25V rating provides adequate margin for the 1.8V signal. | </details> <details> <summary><b>R6</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal, which goes to connector J10 pin 46 and debouncing capacitor C1. This pin provides the pull-up connection for the reset button signal. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing pull-up voltage for the reset button signal. The 1kΩ value is appropriate for a 1.8V logic level pull-up. | </details> <details> <summary><b>R7</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | ILB_RTC_TESTB | ✅ | Connected to ILB_RTC_TESTB signal, which is pulled up to +RTCVCC through this resistor and filtered to ground through C2. | | 2 | 2 | +RTCVCC | ✅ | Connected to +RTCVCC power rail, providing pull-up voltage for the ILB_RTC_TESTB signal. | </details> <details> <summary><b>C2</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for filtering the ILB_RTC_TESTB signal. | | 2 | 2 | ILB_RTC_TESTB | ✅ | Connected to ILB_RTC_TESTB signal, providing noise filtering in conjunction with pull-up resistor R7. | </details> <details> <summary><b>R21</b> - 110-0002078 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A power rail, forming one side of a 51-ohm pull-up resistor for the XDP_H_TDO JTAG signal. | | 2 | 2 | XDP_H_TDO | ✅ | Connected to XDP_H_TDO (JTAG Test Data Out signal). The 51-ohm pull-up configuration is highly unusual for a TDO signal but may be a specific requirement for Intel's XDP interface. | </details> <details> <summary><b>C5</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the decoupling capacitor. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing decoupling for U1 buffer IC. | </details> <details> <summary><b>C252</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL1 | ✅ | 27pF load capacitor for crystal oscillator XTAL1 pin. | | 2 | 2 | GND | ✅ | 27pF load capacitor for crystal oscillator XTAL1 pin. | </details> <details> <summary><b>C253</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | 27pF load capacitor for crystal oscillator XTAL2 pin. | | 2 | 2 | GND | ✅ | 27pF load capacitor for crystal oscillator XTAL2 pin. | </details> <details> <summary><b>R836</b> - 1120-0018 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0018) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 4.99K resistor connecting RSET pin to GND to set internal reference current. | | 2 | 2 | LAN_RSET | ✅ | 4.99K resistor connecting RSET pin to GND to set internal reference current. | </details> <details> <summary><b>C425</b> - 2221-0017 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2221-0017) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2588 | ✅ | 0.039uF flying capacitor for internal charge pump between CTOP and CBOT pins. | | 2 | 2 | $18N2590 | ✅ | 0.039uF flying capacitor for internal charge pump between CTOP and CBOT pins. | </details> <details> <summary><b>R827</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | 10K pullup resistor for DEV_OFF_N control signal. | | 2 | 2 | $18N3540 | ✅ | 10K pullup resistor for DEV_OFF_N control signal. | </details> <details> <summary><b>R828</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | 10K pullup resistor for LAN_PWR_GOOD output signal. | | 2 | 2 | $18N3538 | ✅ | 10K pullup resistor for LAN_PWR_GOOD output signal. | </details> <details> <summary><b>U42</b> - 4300-0071 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4300-0071) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | LAN_PWR_GOOD | $18N3538 | ✅ | LAN_PWR_GOOD output with 10K pullup to +3VSB_LAN. This is a power good indicator signal. | | 2 | NC_SI_CLK_IN | $18N3372 | ✅ | Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K. | | 3 | NC_SI_CRS_DV | $18N3374 | ✅ | Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K. | | 5 | NC_SI_RXD1 | $18N3305 | ✅ | Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K. | | 6 | NC_SI_RXD0 | $18N3303 | ✅ | Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K. | | 7 | NC_SI_TX_EN | $18N3376 | ✅ | Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K. | | 8 | NC_SI_TXD1 | $18N3301 | ✅ | Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K. | | 9 | NC_SI_TXD0 | $18N3299 | ✅ | Serial interface pins (NC_SI_*) are unused and properly terminated. Clock/control signals pulled to GND through 1K, data signals pulled to +3VSB_LAN through 10K. | | 4 | JTAG_TDO | | ✅ | JTAG_TDO is not connected. This is acceptable as JTAG may not be used in production. | | 10 | VDD3P3_10 | +3VSB_LAN | ✅ | VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling. | | 27 | VDD3P3_27 | +3VSB_LAN | ✅ | VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling. | | 41 | VDD3P3_41 | +3VSB_LAN | ✅ | VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling. | | 51 | VDD3P3_51 | +3VSB_LAN | ✅ | VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling. | | 64 | VDD3P3_64 | +3VSB_LAN | ✅ | VDD3P3 power pins correctly connected to +3VSB_LAN supply with appropriate decoupling. | | 11 | VDD0P9_11 | +0V9_LAN | ✅ | VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling. | | 32 | VDD0P9_32 | +0V9_LAN | ✅ | VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling. | | 42 | VDD0P9_42 | +0V9_LAN | ✅ | VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling. | | 59 | VDD0P9_59 | +0V9_LAN | ✅ | VDD0P9 power pins correctly connected to +0V9_LAN supply with appropriate decoupling. | | 12 | NVM_SI | $18N2399 | ✅ | NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity. | | 13 | NVM_SK | $18N2397 | ✅ | NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity. | | 14 | NVM_SO | $18N3554 | ✅ | NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity. | | 15 | NVM_CS_N | $18N2395 | ✅ | NVM interface pins correctly connected to SPI EEPROM U43 through 33.2 ohm series resistors for signal integrity. | | 16 | PE_WAKE_N | PMC_PCIE_WAKE | ✅ | PE_WAKE_N connected to PMC_PCIE_WAKE for PCIe wake signaling. | | 17 | PE_RST_N | PMC_PLTRST_L | ✅ | PE_RST_N connected to PMC_PLTRST_L for PCIe reset signaling. | | 18 | JTAG_TMS | $18N3293 | ✅ | JTAG pins (TMS, CLK, TDI) have 10K pullups to +3VSB_LAN, which is standard practice to prevent floating inputs. | | 19 | JTAG_CLK | $18N3295 | ✅ | JTAG pins (TMS, CLK, TDI) have 10K pullups to +3VSB_LAN, which is standard practice to prevent floating inputs. | | 29 | JTAG_TDI | $18N3297 | ✅ | JTAG pins (TMS, CLK, TDI) have 10K pullups to +3VSB_LAN, which is standard practice to prevent floating inputs. | | 20 | PE_TXN | PCIE_C_RXP2 | ✅ | PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification. | | 21 | PE_TXP | PCIE_C_RXN2 | ✅ | PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification. | | 23 | PE_RXN | PCIE_C_TXP2 | ✅ | PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification. | | 24 | PE_RXP | PCIE_C_TXN2 | ✅ | PCIe TX/RX differential pairs have intentional polarity inversion for ease of layout. Both TX/RX swap and P/N polarity inversion are applied, which is valid per PCIe specification. | | 22 | NC/INTVCC | | ✅ | NC/INTVCC pin is not connected, indicating internal voltage regulator is not used. | | 25 | PECLK_N | PCIE_CLK-N2 | ✅ | PCIe clock differential pair (PECLK_P/N) correctly connected to PCIE_CLK-P2/N2 with test points. | | 26 | PECLK_P | PCIE_CLK-P2 | ✅ | PCIe clock differential pair (PECLK_P/N) correctly connected to PCIE_CLK-P2/N2 with test points. | | 28 | DEV_OFF_N | $18N3540 | ✅ | DEV_OFF_N with 10K pullup to +3VSB_LAN for device off control. | | 30 | LED1 | LAN-LED1 | ✅ | LED output pins correctly connected with current limiting resistors and EMI filtering capacitors. | | 31 | LED0 | LAN-LED0 | ✅ | LED output pins correctly connected with current limiting resistors and EMI filtering capacitors. | | 33 | LED2 | LAN-LED2 | ✅ | LED output pins correctly connected with current limiting resistors and EMI filtering capacitors. | | 34 | SMB_CLK | LAN-SMB-CLK | ✅ | SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected for system management. | | 35 | SMB_ALRT_N | LAN-SMB-ALERT# | ✅ | SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected for system management. | | 36 | SMB_DATA | LAN-SMB-DATA | ✅ | SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected for system management. | | 37 | CBOT | $18N2590 | ✅ | CBOT and CTOP pins correctly connected through 0.039uF flying capacitor for internal charge pump. | | 40 | CTOP | $18N2588 | ✅ | CBOT and CTOP pins correctly connected through 0.039uF flying capacitor for internal charge pump. | | 38 | VDD0P9_OUT | +0V9_LAN | ✅ | VDD0P9_OUT connected to +0V9_LAN, output from internal 0.9V regulator. | | 39 | VDD1P5_OUT | +1V5_LAN | ✅ | VDD1P5_OUT connected to +1V5_LAN, output from internal 1.5V regulator. | | 43 | NC_SI_ARB_IN | | ✅ | Serial interface arbitration pins (NC_SI_ARB_IN/OUT) are not connected, which is acceptable as the serial interface is not used. | | 44 | NC_SI_ARB_OUT | | ✅ | Serial interface arbitration pins (NC_SI_ARB_IN/OUT) are not connected, which is acceptable as the serial interface is not used. | | 45 | XTAL2 | LAN_XTAL2 | ✅ | Crystal oscillator pins correctly connected to 25MHz crystal X1 with 27pF load capacitors. | | 46 | XTAL1 | LAN_XTAL1 | ✅ | Crystal oscillator pins correctly connected to 25MHz crystal X1 with 27pF load capacitors. | | 47 | VDD1P5_47 | +1V5_LAN | ✅ | VDD1P5 power pins correctly connected to +1V5_LAN supply with appropriate decoupling. | | 56 | VDD1P5_56 | +1V5_LAN | ✅ | VDD1P5 power pins correctly connected to +1V5_LAN supply with appropriate decoupling. | | 48 | RSET | LAN_RSET | ✅ | RSET pin correctly connected to GND through 4.99K resistor to set internal reference current. | | 49 | MDI_MINUS3/SER_N | MDI_N3 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 50 | MDI_PLUS3/SER_P | MDI_P3 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 52 | MDI_MINUS2/SET_N | MDI_N2 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 53 | MDI_PLUS2 | MDI_P2 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 54 | MDI_MINUS1/SRDS_SIG_DET | MDI_N1 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 55 | MDI_PLUS1/SFP_I2C_CLK | MDI_P1 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 57 | MDI_MINUS0/SFP_I2C_DATA | MDI_N0 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 58 | MDI_PLUS0/NC | MDI_P0 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Ethernet PHY interface. | | 60 | SDP3 | | ✅ | Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used. | | 61 | SDP1/PCIE_DIS | | ✅ | Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used. | | 62 | SDP2 | | ✅ | Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used. | | 63 | SDP0 | | ✅ | Software defined pins (SDP0-3) are not connected, which is acceptable if these features are not used. | | 65 | GND_PAD | GND | ✅ | Ground pad correctly connected to GND. | </details> <details> <summary><b>X1</b> - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Crystal output connected to U42 XTAL2 pin with 27pF load capacitor. | | 2 | 2 | GND | ✅ | Crystal ground pins correctly connected to GND. | | 4 | 4 | GND | ✅ | Crystal ground pins correctly connected to GND. | | 3 | 3 | LAN_XTAL1 | ✅ | Crystal input connected to U42 XTAL1 pin with 27pF load capacitor. | </details> <details> <summary><b>R832</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2435 | ✅ | Connected to the SI pin of U43 (SPI flash memory) on net $18N2435. | | 2 | 2 | $18N2399 | ✅ | Connected to the NVM_SI pin of U42 (Ethernet controller) on net $18N2399. | </details> <details> <summary><b>R835</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2439 | ✅ | Connected to the CS# pin of U43 (SPI flash memory) on net $18N2439. | | 2 | 2 | $18N2395 | ✅ | Connected to the NVM_CS_N pin of U42 (Ethernet controller) on net $18N2395. | </details> <details> <summary><b>R834</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2437 | ✅ | Connected to the SCK pin of U43 (SPI flash memory) on net $18N2437. | | 2 | 2 | $18N2397 | ✅ | Connected to the NVM_SK pin of U42 (Ethernet controller) on net $18N2397. | </details> <details> <summary><b>R831</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Connected to +3VSB_LAN power rail. | | 2 | 2 | $18N3659 | ✅ | Connected to the HOLD# pin of U43 (SPI flash memory) on net $18N3659. | </details> <details> <summary><b>R848</b> - 1120-0359 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0359) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Connected to +3VSB_LAN power rail. | | 2 | 2 | $18N2435 | ✅ | Connected to the SI pin of U43 (SPI flash memory) on net $18N2435. | </details> <details> <summary><b>R830</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Connected to +3VSB_LAN power rail. | | 2 | 2 | $18N3609 | ✅ | Connected to the WP# pin of U43 (SPI flash memory) on net $18N3609. | </details> <details> <summary><b>U43</b> - AT25DF081A-SSH ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25df081a-datasheet?language=en) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4356-0082) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | $18N2439 | ✅ | CS# (Chip Select) is correctly connected through a 33.2Ω series resistor (R835) to the NVM_CS_N pin of the Ethernet controller U42. | | 2 | SO | $18N3552 | ✅ | SO (Serial Output) is correctly connected through a 33.2Ω series resistor (R833) to the NVM_SO pin of the Ethernet controller U42. | | 3 | WP# | $18N3609 | ✅ | WP# (Write Protect) is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R830), following datasheet recommendations. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground reference. | | 5 | SI | $18N2435 | ✅ | SI (Serial Input) is correctly connected through a 33.2Ω series resistor (R832) to the NVM_SI pin of U42, with a 33.2KΩ pull-up to +3VSB_LAN (R848). | | 6 | SCK | $18N2437 | ✅ | SCK (Serial Clock) is correctly connected through a 33.2Ω series resistor (R834) to the NVM_SK pin of the Ethernet controller U42. | | 7 | HOLD# | $18N3659 | ✅ | HOLD# is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R831), following datasheet recommendations. | | 8 | VCC | +3VSB_LAN | ✅ | VCC is correctly connected to +3VSB_LAN, which should provide 3.3V within the device's 2.7V to 3.6V operating range. | </details> <details> <summary><b>R833</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3554 | ✅ | Connected to the NVM_SO pin of U42 (Ethernet controller) on net $18N3554. | | 2 | 2 | $18N3552 | ✅ | Connected to the SO pin of U43 (SPI flash memory) on net $18N3552. | </details> <details> <summary><b>J11</b> - 3362-0042 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3362-0042) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | MD1+ | MDI_P0 | ✅ | MDI_P0/MDI_N0 differential pair correctly connected to PHY U42 pins 58/57 for Ethernet data transmission. | | 2 | MD1- | MDI_N0 | ✅ | MDI_P0/MDI_N0 differential pair correctly connected to PHY U42 pins 58/57 for Ethernet data transmission. | | 3 | MD2+ | MDI_P1 | ✅ | MDI_P1/MDI_N1 differential pair correctly connected to PHY U42 pins 55/54 for Ethernet data transmission. | | 4 | MD2- | MDI_N1 | ✅ | MDI_P1/MDI_N1 differential pair correctly connected to PHY U42 pins 55/54 for Ethernet data transmission. | | 5 | CT1 | $18N3856 | ✅ | Center tap pins correctly connected to common node with bypass capacitors for common mode filtering. | | 6 | CT2 | $18N3856 | ✅ | Center tap pins correctly connected to common node with bypass capacitors for common mode filtering. | | 7 | MD3+ | MDI_P2 | ✅ | MDI_P2/MDI_N2 differential pair correctly connected to PHY U42 pins 53/52 for Ethernet data transmission. | | 8 | MD3- | MDI_N2 | ✅ | MDI_P2/MDI_N2 differential pair correctly connected to PHY U42 pins 53/52 for Ethernet data transmission. | | 9 | MD4+ | MDI_P3 | ✅ | MDI_P3/MDI_N3 differential pair correctly connected to PHY U42 pins 50/49 for Ethernet data transmission. | | 10 | MD4- | MDI_N3 | ✅ | MDI_P3/MDI_N3 differential pair correctly connected to PHY U42 pins 50/49 for Ethernet data transmission. | | 11 | LED2_AC1 | LAN-LED0 | ✅ | LED2 pins configured as a bi-directional LED driven by two PHY outputs (LED0 and LED2). Pin 11 connects directly to U42 LED0 output, while pin 12 connects through R844 (301Ω) to U42 LED2 output. The single series resistor R844 provides current limiting in both directions, making this configuration correct for bi-directional LED operation. | | 12 | LED2_AD1 | 1G-LED-N | ✅ | LED2 pins configured as a bi-directional LED driven by two PHY outputs (LED0 and LED2). Pin 11 connects directly to U42 LED0 output, while pin 12 connects through R844 (301Ω) to U42 LED2 output. The single series resistor R844 provides current limiting in both directions, making this configuration correct for bi-directional LED operation. | | 13 | LED1_C | LINK-LED-N | ✅ | LED1 correctly configured with anode to power supply and cathode through current limiting resistor to PHY LED1 output for active-low drive. | | 14 | LED1_A | +3VSB_LAN | ✅ | LED1 correctly configured with anode to power supply and cathode through current limiting resistor to PHY LED1 output for active-low drive. | | 15 | SHLD1 | GND_EARTH | ✅ | Shield pins correctly connected to earth ground for EMI shielding and ESD protection. | | 16 | SHLD2 | GND_EARTH | ✅ | Shield pins correctly connected to earth ground for EMI shielding and ESD protection. | </details> <details> <summary><b>R843</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED1 | ✅ | Current limiting resistor for LED1. Pin 1 connects to U42 LED1 output (LAN-LED1), pin 2 connects to J11 LED1 cathode (LINK-LED-N). The 301Ω value provides appropriate LED current limiting for approximately 4-5mA at 3.3V. | | 2 | 2 | LINK-LED-N | ✅ | Current limiting resistor for LED1. Pin 1 connects to U42 LED1 output (LAN-LED1), pin 2 connects to J11 LED1 cathode (LINK-LED-N). The 301Ω value provides appropriate LED current limiting for approximately 4-5mA at 3.3V. | </details> <details> <summary><b>R844</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED2 | ✅ | Current limiting resistor for LED2 in a bi-directional configuration. Pin 1 connects to U42 LED2 output (LAN-LED2), pin 2 connects to J11 LED2 pin 12 (1G-LED-N). The single 301Ω resistor limits current in both directions for the bi-directional LED. | | 2 | 2 | 1G-LED-N | ✅ | Current limiting resistor for LED2 in a bi-directional configuration. Pin 1 connects to U42 LED2 output (LAN-LED2), pin 2 connects to J11 LED2 pin 12 (1G-LED-N). The single 301Ω resistor limits current in both directions for the bi-directional LED. | </details> <details> <summary><b>C429</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LINK-LED-N | ✅ | EMI filter capacitor on LED1 signal line. Pin 1 connects to LINK-LED-N (LED1 cathode signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression without affecting LED switching speed. | | 2 | 2 | GND | ✅ | EMI filter capacitor on LED1 signal line. Pin 1 connects to LINK-LED-N (LED1 cathode signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression without affecting LED switching speed. | </details> <details> <summary><b>C430</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1G-LED-N | ✅ | EMI filter capacitor on LED2 signal line. Pin 1 connects to 1G-LED-N (LED2 pin 12 signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression. | | 2 | 2 | GND | ✅ | EMI filter capacitor on LED2 signal line. Pin 1 connects to 1G-LED-N (LED2 pin 12 signal), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression. | </details> <details> <summary><b>C431</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED0 | ✅ | EMI filter capacitor on LAN-LED0 signal line. Pin 1 connects to LAN-LED0 (LED2 pin 11 signal from U42 LED0 output), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression. | | 2 | 2 | GND | ✅ | EMI filter capacitor on LAN-LED0 signal line. Pin 1 connects to LAN-LED0 (LED2 pin 11 signal from U42 LED0 output), pin 2 connects to ground. The 560pF value provides high-frequency noise suppression. | </details> <details> <summary><b>FB12</b> - 3044-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3044-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB | ✅ | Input pin connected to +3VSB standby power rail, serving as the source for the LAN subsystem power filter. | | 2 | 2 | +3VSB_LAN | ✅ | Output pin connected to +3VSB_LAN filtered power rail, providing clean power to the LAN controller U42, SPI flash U43, and associated circuitry. | </details> <details> <summary><b>R837</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3372 | ✅ | Connected to U42 pin 2 (NC_SI_CLK_IN) via net $18N3372, providing a 1K pull-down resistor for this configuration pin. | | 2 | 2 | GND | ✅ | Connected to GND, completing the pull-down resistor function. | </details> <details> <summary><b>R838</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3374 | ✅ | Connected to U42 pin 3 (NC_SI_CRS_DV) via net $18N3374, providing a 1K pull-down resistor for this configuration pin. | | 2 | 2 | GND | ✅ | Connected to GND, completing the pull-down resistor function. | </details> <details> <summary><b>R839</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3376 | ✅ | Connected to U42 pin 7 (NC_SI_TX_EN) via net $18N3376, providing a 1K pull-down resistor for this configuration pin. | | 2 | 2 | GND | ✅ | Connected to GND, completing the pull-down resistor function. | </details> <details> <summary><b>C426</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Connected to the center tap network ($18N3856) of the Ethernet transformer in J11. This pin, along with C427 and C428, provides high-frequency filtering for the center taps. | | 2 | 2 | GND | ✅ | Connected to ground, providing the return path for center tap filtering. | </details> <details> <summary><b>C427</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Connected to the center tap network ($18N3856) of the Ethernet transformer in J11. This pin, along with C426 and C428, provides high-frequency filtering for the center taps. | | 2 | 2 | GND | ✅ | Connected to ground, providing the return path for center tap filtering. | </details> <details> <summary><b>C428</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2222-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Connected to the center tap network ($18N3856) of the Ethernet transformer in J11. This pin provides low-frequency filtering for the center taps. | | 2 | 2 | GND | ✅ | Connected to ground, providing the return path for center tap filtering. | </details> <details> <summary><b>U7</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | UART2_RXD | ✅ | B2 pin connected to UART2_RXD on the 3.3V side of the level translator. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin connected to +V1P8S with appropriate decoupling. | | 4 | A2 | SIO_UART2_RXD | ✅ | A2 pin connected to SIO_UART2_RXD on the 1.8V SOC side. | | 5 | A1 | SIO_UART2_TXD | ✅ | A1 pin connected to SIO_UART2_TXD on the 1.8V SOC side. | | 6 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin connected to PMC_PLTRST_R_V1P8 to enable the translator when platform is out of reset. | | 7 | VCCB | +3VSB | ✅ | VCCB pin connected to +3VSB with appropriate decoupling. | | 8 | B1 | UART2_TXD | ✅ | B1 pin connected to UART2_TXD on the 3.3V side of the level translator. | </details> <details> <summary><b>U15</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin connected to +V1P8S with appropriate decoupling. | | 2 | A1 | SIO_UART1_RTSB | ✅ | A1 pin connected to SIO_UART1_RTSB on the 1.8V SOC side. | | 3 | A2 | SIO_UART1_CTSB | ✅ | A2 pin connected to SIO_UART1_CTSB on the 1.8V SOC side. | | 4 | A3 | SIO_UART1_RXD | ✅ | A3 pin connected to SIO_UART1_RXD on the 1.8V SOC side. | | 5 | A4 | SIO_UART1_TXD | ✅ | A4 pin connected to SIO_UART1_TXD on the 1.8V SOC side. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 7 | B4 | UART1_TXD | ✅ | B4 pin connected to UART1_TXD on the 3.3V side of the level translator. | | 8 | B3 | UART1_RXD | ✅ | B3 pin connected to UART1_RXD on the 3.3V side of the level translator. | | 9 | B2 | UART1_CTSB | ✅ | B2 pin connected to UART1_CTSB on the 3.3V side of the level translator. | | 10 | B1 | UART1_RTSB | ✅ | B1 pin connected to UART1_RTSB on the 3.3V side of the level translator. | | 11 | VCCB | +3VSB | ✅ | VCCB pin connected to +3VSB with appropriate decoupling. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin connected to PMC_PLTRST_R_V1P8 to enable the translator when platform is out of reset. | </details> <details> <summary><b>U14</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing the 1.8V reference voltage for the A-side of the level translator. | | 2 | A1 | SOC_SIO_SPI_CLK | ✅ | A1 is correctly connected to SOC_SIO_SPI_CLK, the 1.8V SPI clock signal from the SOC. | | 3 | A2 | SOC_SIO_SPI_MOSI | ✅ | A2 is correctly connected to SOC_SIO_SPI_MOSI, the 1.8V SPI MOSI signal from the SOC. | | 4 | A3 | SOC_SIO_SPI_MISO | ✅ | A3 is correctly connected to SOC_SIO_SPI_MISO, the 1.8V SPI MISO signal from the SOC. | | 5 | A4 | SOC_SIO_SPI_CS1 | ✅ | A4 is correctly connected to SOC_SIO_SPI_CS1, the 1.8V SPI chip select signal from the SOC. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SIO_SPI_CS1 | ✅ | B4 is correctly connected to SIO_SPI_CS1, the 3.3V translated SPI chip select signal. | | 8 | B3 | SIO_SPI_MISO | ✅ | B3 is correctly connected to SIO_SPI_MISO, the 3.3V translated SPI MISO signal. | | 9 | B2 | SIO_SPI_MOSI | ✅ | B2 is correctly connected to SIO_SPI_MOSI, the 3.3V translated SPI MOSI signal. | | 10 | B1 | SIO_SPI_CLK | ✅ | B1 is correctly connected to SIO_SPI_CLK, the 3.3V translated SPI clock signal. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing the 3.3V reference voltage for the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset. | </details> <details> <summary><b>U10</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to the 1.8V supply rail (+V1P8A) with proper decoupling. | | 2 | A1 | SOC_GPIO_S5_2 | ✅ | A1 is correctly connected to SOC_GPIO_S5_2 for level translation to the 3.3V domain. | | 3 | A2 | SOC_GPIO_S5_1 | ✅ | A2 is correctly connected to SOC_GPIO_S5_1 for level translation to the 3.3V domain. | | 4 | A3 | SOC_GPIO_S5_0 | ✅ | A3 is correctly connected to SOC_GPIO_S5_0 for level translation to the 3.3V domain. | | 5 | A4 | | ✅ | A4 is left unconnected as the fourth channel is not needed in this design. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 7 | B4 | GND | ✅ | A4 (pin 5) and B4 (pin 7) form the fourth channel of the level translator, which is intentionally unused. A4 is left floating while B4 is grounded, an acceptable configuration for disabling an unused channel. | | 8 | B3 | GPIO_S5_0 | ✅ | B3 is correctly connected to GPIO_S5_0 for the translated 3.3V signal output. | | 9 | B2 | GPIO_S5_1 | ✅ | B2 is correctly connected to GPIO_S5_1 for the translated 3.3V signal output. | | 10 | B1 | GPIO_S5_2 | ✅ | B1 is correctly connected to GPIO_S5_2 for the translated 3.3V signal output. | | 11 | VCCB | +PS_3VSB | ✅ | VCCB is correctly connected to the 3.3V standby supply (+PS_3VSB) with proper decoupling. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8 to enable the translator when the platform is out of reset. | </details> <details> <summary><b>U16</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA power supply pin correctly connected to +V1P8S (1.8V) with nearby decoupling capacitor C352. | | 2 | A1 | I2S_DATIN_R | ✅ | A1 is correctly connected to I2S_DATIN_R, which translates to the corresponding B1 pin (I2SDI_GPIO) for I2S data input signal level translation. | | 3 | A2 | I2S_DATOUT_R | ✅ | A2 is correctly connected to I2S_DATOUT_R, which translates to the corresponding B2 pin (I2SDO_GPIO) for I2S data output signal level translation. | | 4 | A3 | I2S_FRM_R | ✅ | A3 (I2S_FRM_R) correctly connects to B3 (I2SFRM_GPIO) for I2S frame sync signal translation from 1.8V to 3.3V. | | 5 | A4 | I2S_CLK_R | ✅ | A4 (I2S_CLK_R) correctly connects to B4 (I2SCLK_GPIO) for I2S clock signal translation from 1.8V to 3.3V. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 7 | B4 | I2SCLK_GPIO | ✅ | B4 (I2SCLK_GPIO) correctly pairs with A4 (I2S_CLK_R) for clock signal. | | 8 | B3 | I2SFRM_GPIO | ✅ | B3 (I2SFRM_GPIO) correctly pairs with A3 (I2S_FRM_R) for frame sync signal. | | 9 | B2 | I2SDO_GPIO | ✅ | B2 is correctly connected to I2SDO_GPIO, corresponding to A2 (I2S_DATOUT_R) for I2S data output signal level translation on the 3.3V side. | | 10 | B1 | I2SDI_GPIO | ✅ | B1 is correctly connected to I2SDI_GPIO, corresponding to A1 (I2S_DATIN_R) for I2S data input signal level translation on the 3.3V side. | | 11 | VCCB | +3VSB | ✅ | VCCB power supply pin correctly connected to +3VSB (3.3V) with nearby decoupling capacitor C353. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE (output enable) pin correctly connected to PMC_PLTRST_R_V1P8, a 1.8V level control signal matching VCCA voltage. | </details> <details> <summary><b>U17</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA power supply pin correctly connected to +V1P8S (1.8V) with nearby decoupling capacitor C348. | | 2 | A1 | I2S_MCLK | ✅ | A1 (I2S_MCLK) correctly connects to B1 (I2SMCLK_GPIO) for I2S master clock signal translation from 1.8V to 3.3V. | | 3 | A2 | SOC_PWM1 | ✅ | A2 (SOC_PWM1) correctly connects to B2 (PWM1) for PWM signal translation from 1.8V to 3.3V. | | 4 | A3 | SOC_PWM0 | ✅ | A3 (SOC_PWM0) correctly connects to B3 (PWM0) for PWM signal translation from 1.8V to 3.3V. | | 5 | A4 | | ✅ | Channel 4 is unused with A4 left floating and B4 grounded. This asymmetric configuration is unusual but acceptable, as it appears to be an intentional design pattern repeated in other similar components (U10) on the schematic. | | 7 | B4 | GND | ✅ | Channel 4 is unused with A4 left floating and B4 grounded. This asymmetric configuration is unusual but acceptable, as it appears to be an intentional design pattern repeated in other similar components (U10) on the schematic. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 8 | B3 | PWM0 | ✅ | B3 (PWM0) correctly pairs with A3 (SOC_PWM0) for PWM signal. | | 9 | B2 | PWM1 | ✅ | B2 (PWM1) correctly pairs with A2 (SOC_PWM1) for PWM signal. | | 10 | B1 | I2SMCLK_GPIO | ✅ | B1 (I2SMCLK_GPIO) correctly pairs with A1 (I2S_MCLK) for master clock signal. | | 11 | VCCB | +3VSB | ✅ | VCCB power supply pin correctly connected to +3VSB (3.3V) with nearby decoupling capacitor C349. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE (output enable) pin correctly connected to PMC_PLTRST_R_V1P8, a 1.8V level control signal matching VCCA voltage. | </details> <details> <summary><b>R818</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | This 0-ohm jumper is correctly marked DNI (Do Not Install) for 3.3V operation, preventing connection of $20N2079 to +V1P8A. | | 2 | 2 | +V1P8A | ✅ | This 0-ohm jumper is correctly marked DNI (Do Not Install) for 3.3V operation, preventing connection of $20N2079 to +V1P8A. | </details> <details> <summary><b>R152</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | This 0-ohm jumper is correctly populated to connect $20N2079 to +3VSB, selecting 3.3V operation for the W25Q64BVSSIG flash. | | 2 | 2 | +3VSB | ✅ | This 0-ohm jumper is correctly populated to connect $20N2079 to +3VSB, selecting 3.3V operation for the W25Q64BVSSIG flash. | </details> <details> <summary><b>U3</b> - W25Q64BVSSIG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/653/W25Q64BV.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/W25Q64BVSSIG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPI_CS0 | ✅ | CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pull-up resistor to +V_SPI, ensuring the flash is deselected when not actively driven. | | 2 | SO/IO1 | SPI_MISO | ✅ | SO/IO1 (Serial Data Output) is correctly connected to SPI_MISO for reading data from the flash memory. | | 3 | WP#/IO2 | SPI_WP | ✅ | WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pull-up to +V_SPI, disabling write protection by default. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the ground plane. | | 5 | SI/IO0 | SPI_MOSI | ✅ | SI/IO0 (Serial Data Input) is correctly connected to SPI_MOSI for writing data to the flash memory. | | 6 | SCK | SPI_CLK | ✅ | SCK (Serial Clock) is correctly connected to SPI_CLK for clocking SPI transactions. | | 7 | HOLD#/IO3 | SPI_HOLD | ✅ | HOLD#/IO3 (Hold Input) is correctly connected to SPI_HOLD with a 10K pull-up to +V_SPI, disabling the hold function by default. | | 8 | VCC | +V_SPI | ✅ | VCC (Power Supply) is correctly connected to +V_SPI, which provides 3.0-3.1V from +3VSB through diode D8, meeting the 2.7-3.6V requirement for the 3.3V version of this flash. | </details> <details> <summary><b>J1</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0004612) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDP_VCC | ✅ | Pin 1 is correctly connected to DDP_VCC, allowing the DediProg programmer to provide power to the circuit. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND, providing ground reference for the programmer interface. | | 3 | 3 | SPI_CS0 | ✅ | Pin 3 is correctly connected to SPI_CS0, providing chip select access to the SPI flash for the programmer. | | 4 | 4 | SPI_CLK | ✅ | Pin 4 is correctly connected to SPI_CLK, providing clock access to the SPI flash for the programmer. | | 5 | 5 | SPI_MISO | ✅ | Pin 5 is correctly connected to SPI_MISO, providing data output access from the SPI flash for the programmer. | | 6 | 6 | SPI_MOSI | ✅ | Pin 6 is correctly connected to SPI_MOSI, providing data input access to the SPI flash for the programmer. | | 7 | 7 | | ✅ | Pin 7 has no connection, which is acceptable as not all pins are required for the programming interface. | | 8 | 8 | DDP_IO3L | ✅ | Pin 8 is correctly connected to DDP_IO3L, allowing the programmer to control the voltage translator enable signal. | </details> <details> <summary><b>D8</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | DDP_VCC | ✅ | Anode 1 is correctly connected to DDP_VCC, allowing the DediProg programmer to provide power to the SPI flash when connected. | | A2 | A2 | $20N2079 | ✅ | Anode 2 is correctly connected to $20N2079, which is tied to +3VSB through R152, providing board power to the SPI flash. | | C | C | +V_SPI | ✅ | Common cathode is correctly connected to +V_SPI, providing the OR-ed power supply output to the SPI flash at approximately 3.0-3.1V. | </details> <details> <summary><b>R147</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001859) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | This 100K pull-up resistor correctly pulls DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control through J1. | | 2 | 2 | DDP_IO3L | ✅ | This 100K pull-up resistor correctly pulls DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control through J1. | </details> <details> <summary><b>U18</b> - NTB0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTB0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the 1.8V reference voltage for the A-side (SOC) interface. | | 2 | A1 | SOC_SPI_MOSI-R | ✅ | A1 is correctly connected to SOC_SPI_MOSI-R, translating the 1.8V MOSI signal from the SOC to the 3.3V B-side. | | 3 | A2 | SOC_SPI_CLK-R | ✅ | A2 is correctly connected to SOC_SPI_CLK-R, translating the 1.8V clock signal from the SOC to the 3.3V B-side. | | 4 | A3 | SOC_SPI_MISO-R | ✅ | A3 is correctly connected to SOC_SPI_MISO-R, translating the 1.8V MISO signal from the 3.3V B-side back to the SOC. | | 5 | A4 | SOC_SPI_CS0B-R | ✅ | A4 is correctly connected to SOC_SPI_CS0B-R, translating the 1.8V chip select signal from the SOC to the 3.3V B-side. | | 6 | GND | GND | ✅ | GND pin is correctly connected to the ground plane. | | 7 | B4 | SPI_CS0 | ✅ | B4 is correctly connected to SPI_CS0, providing the translated 3.3V chip select signal to the flash and external connector. | | 8 | B3 | SPI_MISO | ✅ | B3 is correctly connected to SPI_MISO, providing the translated 3.3V data output signal from the flash to the SOC and external connector. | | 9 | B2 | SPI_CLK | ✅ | B2 is correctly connected to SPI_CLK, providing the translated 3.3V clock signal to the flash and external connector. | | 10 | B1 | SPI_MOSI | ✅ | B1 is correctly connected to SPI_MOSI, providing the translated 3.3V data input signal to the flash and external connector. | | 11 | VCCB | +V_SPI | ✅ | VCCB is correctly connected to +V_SPI, providing the 3.0-3.1V reference voltage for the B-side (flash) interface. | | 12 | OE | DDP_IO3L | ✅ | OE (Output Enable) is correctly connected to DDP_IO3L with a 100K pull-up to +V1P8A, enabling the translator by default while allowing external control. | </details> <details> <summary><b>R266</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C5_SDA | ✅ | 10kΩ pullup resistor correctly connected between I2C5_SDA and +V1P8S, providing the required pullup for the low-voltage side I2C data line. | | 2 | 2 | +V1P8S | ✅ | 10kΩ pullup resistor correctly connected between I2C5_SDA and +V1P8S, providing the required pullup for the low-voltage side I2C data line. | </details> <details> <summary><b>R267</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C5_SCL | ✅ | 10kΩ pullup resistor correctly connected between I2C5_SCL and +V1P8S, providing the required pullup for the low-voltage side I2C clock line. | | 2 | 2 | +V1P8S | ✅ | 10kΩ pullup resistor correctly connected between I2C5_SCL and +V1P8S, providing the required pullup for the low-voltage side I2C clock line. | </details> <details> <summary><b>U40</b> - PCA9306DCUT ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fpca9306) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/PCA9306DCUT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 2 | VREF1 | +V1P8S | ✅ | VREF1 pin correctly connected to +V1P8S (1.8V) low-voltage reference supply. | | 3 | SCL1 | I2C5_SCL | ✅ | SCL1 pin correctly connected to I2C5_SCL with 10K pullup resistor R267 to VREF1. | | 4 | SDA1 | I2C5_SDA | ✅ | SDA1 pin correctly connected to I2C5_SDA with 10K pullup resistor R266 to VREF1. | | 5 | SDA2 | GPIO_I2C_SDA | ✅ | SDA2 and SCL2 pins connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to external connector JP1. No pullup resistors visible on schematic for the high-voltage side, which may be intentional if external pullups are provided, but should be verified. | | 6 | SCL2 | GPIO_I2C_SCL | ✅ | SDA2 and SCL2 pins connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to external connector JP1. No pullup resistors visible on schematic for the high-voltage side, which may be intentional if external pullups are provided, but should be verified. | | 7 | VREF2 | $20N1576 | ✅ | VREF2 and EN pins correctly shorted together on net $20N1576 and pulled up to +3VSB through 200K resistor R812, matching datasheet requirements. | | 8 | EN | $20N1576 | ✅ | VREF2 and EN pins correctly shorted together on net $20N1576 and pulled up to +3VSB through 200K resistor R812, matching datasheet requirements. | </details> <details> <summary><b>JP1</b> - HDR-26 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0005019) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pins 1 and 2 both connected to GND for ground reference, providing multiple ground connections for signal integrity. | | 2 | 2 | GND | ✅ | Pins 1 and 2 both connected to GND for ground reference, providing multiple ground connections for signal integrity. | | 3 | 3 | +PS_5VSB | ✅ | Pin 3 connected to +PS_5VSB for 5V standby power output to external devices. | | 4 | 4 | +3VSB | ✅ | Pin 4 connected to +3VSB for 3.3V standby power output to external devices. | | 5 | 5 | SIO_SPI_CS1 | ✅ | Pin 5 connected to SIO_SPI_CS1 for SPI chip select 1 signal, level-translated from the SOC. | | 6 | 6 | UART1_TXD | ✅ | Pin 6 connected to UART1_TXD for UART1 transmit signal, level-translated from the SOC. | | 7 | 7 | SIO_SPI_MISO | ✅ | Pin 7 connected to SIO_SPI_MISO for SPI MISO signal, level-translated from the SOC. | | 8 | 8 | UART1_RXD | ✅ | Pin 8 connected to UART1_RXD for UART1 receive signal, level-translated from the SOC. | | 9 | 9 | SIO_SPI_MOSI | ✅ | Pin 9 connected to SIO_SPI_MOSI for SPI MOSI signal, level-translated from the SOC. | | 10 | 10 | UART1_CTSB | ✅ | Pin 10 connected to UART1_CTSB for UART1 clear to send signal, level-translated from the SOC. | | 11 | 11 | SIO_SPI_CLK | ✅ | Pin 11 connected to SIO_SPI_CLK for SPI clock signal, level-translated from the SOC. | | 12 | 12 | UART1_RTSB | ✅ | Pin 12 connected to UART1_RTSB for UART1 request to send signal, level-translated from the SOC. | | 13 | 13 | GPIO_I2C_SCL | ✅ | Pin 13 connected to GPIO_I2C_SCL for I2C clock signal, level-translated from the SOC through a bidirectional I2C buffer. | | 14 | 14 | I2SCLK_GPIO | ✅ | Pin 14 connected to I2SCLK_GPIO for I2S clock signal, level-translated from the SOC. | | 15 | 15 | GPIO_I2C_SDA | ✅ | Pin 15 connected to GPIO_I2C_SDA for I2C data signal, level-translated from the SOC through a bidirectional I2C buffer. | | 16 | 16 | I2SFRM_GPIO | ✅ | Pin 16 connected to I2SFRM_GPIO for I2S frame sync signal, level-translated from the SOC. | | 17 | 17 | UART2_TXD | ✅ | Pin 17 connected to UART2_TXD for UART2 transmit signal, level-translated from the SOC. | | 18 | 18 | I2SDO_GPIO | ✅ | Pin 18 connected to I2SDO_GPIO for I2S data output signal, level-translated from the SOC. | | 19 | 19 | UART2_RXD | ✅ | Pin 19 connected to UART2_RXD for UART2 receive signal, level-translated from the SOC. | | 20 | 20 | I2SDI_GPIO | ✅ | Pin 20 connected to I2SDI_GPIO for I2S data input signal, level-translated from the SOC. | | 21 | 21 | GPIO_S5_0 | ✅ | Pin 21 connected to GPIO_S5_0 for general purpose I/O signal 0, level-translated from the SOC. | | 22 | 22 | PWM0 | ✅ | Pin 22 connected to PWM0 for PWM signal 0, level-translated from the SOC. | | 23 | 23 | GPIO_S5_1 | ✅ | Pin 23 connected to GPIO_S5_1 for general purpose I/O signal 1, level-translated from the SOC. | | 24 | 24 | PWM1 | ✅ | Pin 24 connected to PWM1 for PWM signal 1, level-translated from the SOC. | | 25 | 25 | GPIO_S5_2 | ✅ | Pin 25 connected to GPIO_S5_2 for general purpose I/O signal 2, level-translated from the SOC. | | 26 | 26 | I2SMCLK_GPIO | ✅ | Pin 26 connected to I2SMCLK_GPIO for I2S master clock signal, level-translated from the SOC. | </details> <details> <summary><b>R149</b> - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Pin 1 connects to FP_PWRBTN signal. A schematic note indicates the datasheet recommends a 10K pull-up, but this resistor is 4.7K, which is a deviation that should be verified. | | 2 | 2 | +PS_5VSB | ✅ | Pin 2 connects to +PS_5VSB to provide pull-up voltage for the FP_PWRBTN signal. | </details> <details> <summary><b>J5</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Pin 1 connects to FP_PWRBTN, allowing a jumper to be used as an alternative method to activate the power button signal. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the low-side connection when a jumper is installed. | </details> <details> <summary><b>SW1</b> - 3770-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3770-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Pin 1 connects to FP_PWRBTN signal, which is pulled up to +PS_5VSB through R149 and protected by TVS diode D9. When the button is pressed, this pin shorts to GND through pin 2. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the return path when the button is pressed to pull FP_PWRBTN low. | | 3 | GND1 | GND_EARTH | ✅ | Pins 3 and 4 (GND1 and GND2) connect to GND_EARTH for chassis grounding and mechanical shielding of the switch. | | 4 | GND2 | GND_EARTH | ✅ | Pins 3 and 4 (GND1 and GND2) connect to GND_EARTH for chassis grounding and mechanical shielding of the switch. | </details> <details> <summary><b>D9</b> - DIODE_TVS_5V_84W_XFDFN ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N connects to GND, providing the ground reference for the bidirectional TVS diode protection. | | P | P | FP_PWRBTN | ✅ | Pin P connects to FP_PWRBTN signal to provide ESD protection for the power button input. | </details> <details> <summary><b>Q105</b> - FDN327N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/FDN327N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | GPIO_LED_CONTROL | ✅ | Drain connected to GPIO_LED_CONTROL net, which includes LED D2 anode, current limiting resistor R746 to +VCC, and filter capacitor C149. This creates an inverted-logic LED driver topology where the MOSFET shunts current away from the LED when turned on. | | G | GATE | GPIO_D2_LED_CTRL | ✅ | Gate connected to GPIO_D2_LED_CTRL with 10K pull-down resistor R706 to GND. Correctly configured for GPIO control with defined OFF state ensuring LED is ON by default. | | S | SOURCE | GND | ✅ | Source connected to GND. Standard configuration for N-channel MOSFET in low-side switch application. | </details> <details> <summary><b>D2</b> - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GPIO_LED_CONTROL | ✅ | Anode connected to GPIO_LED_CONTROL node. Part of inverted-logic LED driver where LED is ON when MOSFET Q105 is OFF and vice versa. | | C | CATHODE | GND | ✅ | Cathode connected to GND. Standard LED connection for this circuit topology. | </details> <details> <summary><b>R746</b> - 1120-0318 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | R746 functions as a current limiting resistor for LED D2, connected between +VCC (pin 1) and GPIO_LED_CONTROL (pin 2). However, it also conducts continuous current when Q105 is ON (LED OFF state), potentially operating at 85% of its power rating if +VCC is 5V, which raises reliability concerns. | | 2 | 2 | GPIO_LED_CONTROL | ✅ | R746 functions as a current limiting resistor for LED D2, connected between +VCC (pin 1) and GPIO_LED_CONTROL (pin 2). However, it also conducts continuous current when Q105 is ON (LED OFF state), potentially operating at 85% of its power rating if +VCC is 5V, which raises reliability concerns. | </details> <details> <summary><b>R706</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_D2_LED_CTRL | ✅ | R706 functions correctly as a 10K pull-down resistor on the MOSFET gate, ensuring Q105 stays OFF by default (LED ON state) when the GPIO is not actively driven. | | 2 | 2 | GND | ✅ | R706 functions correctly as a 10K pull-down resistor on the MOSFET gate, ensuring Q105 stays OFF by default (LED ON state) when the GPIO is not actively driven. | </details> <details> <summary><b>C149</b> - 2.2uF 10% 10V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_LED_CONTROL | ✅ | C149 provides filtering/decoupling on the GPIO_LED_CONTROL net (pin 1 to GPIO_LED_CONTROL, pin 2 to GND). The 2.2µF value creates an RC time constant of approximately 1ms with R746, causing slow LED turn-on response. When Q105 turns ON, C149 discharges rapidly through the MOSFET, potentially creating a brief high-current pulse that exceeds the datasheet pulsed current rating, though the extremely short duration (nanoseconds) may be within the device's safe operating area. | | 2 | 2 | GND | ✅ | C149 provides filtering/decoupling on the GPIO_LED_CONTROL net (pin 1 to GPIO_LED_CONTROL, pin 2 to GND). The 2.2µF value creates an RC time constant of approximately 1ms with R746, causing slow LED turn-on response. When Q105 turns ON, C149 discharges rapidly through the MOSFET, potentially creating a brief high-current pulse that exceeds the datasheet pulsed current rating, though the extremely short duration (nanoseconds) may be within the device's safe operating area. | </details> <details> <summary><b>D1</b> - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | +PS_5VSB | ✅ | Anode is correctly connected to +PS_5VSB supply rail. This provides power to the adaptor power indicator LED. | | C | CATHODE | PWR_LEDR | ✅ | Cathode is correctly connected to PWR_LEDR net, which connects through current limiting resistor R148 (470Ω) to GND. This forms a proper LED indicator circuit. | </details> <details> <summary><b>U13</b> - NB670 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NB670) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | BST | PS3_BST | ❌ | <details><summary>BST pin connected to bootstrap circuit with non-standard 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. This deviates from datasheet recommendation of direct capacitor connection between BST and SW pins.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="61.70,20.38,69.20,27.88" aspect-ratio="1.29" } <ul><li>Pin 10 (BST) connects to net PS3_BST <em>(from schematic)</em></li><li>PS3_BST connects through R291 (4.7Ω) to intermediate node $22N1498 <em>(from schematic)</em></li><li>Node $22N1498 connects through C306 (0.1uF) to PS3VSB_PHASE (SW pins) <em>(from schematic)</em></li><li>This forms bootstrap circuit: BST → R291 (4.7Ω) → C306 (0.1uF) → SW <em>(from schematic)</em></li><li>BST is the bootstrap pin where a capacitor connected between SW and BST pins forms floating supply across high-side switch driver <em>(from datasheet <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=5">NB670</a>, page 5)</em></li><li>Datasheet typical application shows 100nF ceramic capacitor directly between BST and SW pins without any series resistor <em>(from datasheet <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=18">NB670</a>, page 18)</em></li><li>The bootstrap voltage path (BST, capacitor, SW) should be kept as short as possible <em>(from datasheet <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=16">NB670</a>, page 16)</em></li><li>The 4.7Ω series resistor creates RC time constant of 0.47μs with 0.1uF capacitor, which is approximately 24% of the 2μs switching period at 500kHz <em>(reasoning)</em></li><li>During bootstrap charging, voltage drop across 4.7Ω resistor would be approximately 0.47-0.94V for typical gate charge currents of 100-200mA, which is 9-19% of the nominal 5V bootstrap voltage <em>(reasoning)</em></li><li>While the series resistor might provide benefits such as EMI reduction, inrush current limiting, or damping, this configuration is not documented in the datasheet and deviates from recommended design <em>(reasoning)</em></li><li>The non-standard bootstrap circuit configuration could potentially affect gate drive voltage and bootstrap capacitor charging, especially during startup, transient conditions, or at the edges of the operating range <em>(reasoning)</em></li><li>This deviation from datasheet recommendation should be verified through testing to ensure proper bootstrap operation across all operating conditions <em>(reasoning)</em></li></ul></details> | | 1 | VIN | PS5VSB_VIN | ✅ | VIN pin correctly connected to PS5VSB_VIN with appropriate input capacitors for decoupling. Input voltage is at the minimum of the recommended operating range. | | 2 | PGND | GND | ✅ | PGND pin correctly connected to GND plane. | | 3 | N/C | | ✅ | N/C pin correctly left unconnected per datasheet. | | 4 | PG | +PS_3VSB_PG | ✅ | PG pin correctly connected as open-drain output with 100K pull-up resistor to PS3_VCC. | | 5 | CLK | $22N1411 | ✅ | CLK pin correctly connected to charge pump circuit with capacitors and diodes to generate gate drive voltage. | | 6 | LDO | PS3_LDO | ✅ | LDO pin correctly connected with 10uF decoupling capacitor, exceeding the minimum 4.7uF requirement. | | 7 | VOUT | +PS_3VSB | ✅ | VOUT pin correctly connected to output capacitors and load switches, providing 3.3V output sensing and power distribution. | | 8 | SW1 | PS3VSB_PHASE | ✅ | SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis). | | 9 | SW2 | PS3VSB_PHASE | ✅ | SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis). | | 15 | SW3 | PS3VSB_PHASE | ✅ | SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis). | | 16 | SW4 | PS3VSB_PHASE | ✅ | SW1, SW2, SW3, SW4 pins correctly connected together to switching node PS3VSB_PHASE which drives output inductor L3. However, bootstrap circuit configuration is non-standard (see pin 10 analysis). | | 11 | VCC | PS3_VCC | ✅ | VCC pin correctly connected with 1.0uF decoupling capacitor meeting minimum requirement. | | 12 | ENLDO | | ✅ | ENLDO pin correctly left open to enable the LDO per datasheet recommendation. | | 13 | EN | PS3_EN | ✅ | EN pin connected with 499K pull-up resistor to input voltage. Recommended 10nF noise filtering capacitor C85 is marked DNI. | | 14 | AGND | GND | ✅ | AGND pin correctly connected to GND plane. | </details> <details> <summary><b>L3</b> - IND_2.2uH_20%_10A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/125-0004501) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | Inductor pin 1 correctly connected to switching node PS3VSB_PHASE from U13. | | 2 | 2 | +PS_3VSB | ✅ | Inductor pin 2 correctly connected to output voltage +PS_3VSB (3.3V). | </details> <details> <summary><b>U35</b> - NCT3012S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NCT3012S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DeepS5_Sel | S5_SEL | ✅ | DeepS5_Sel pin is connected to S5_SEL net with a 2.2K pull-up to +PS_5VSB and can be pulled low by Q10 (N-channel FET) when 5VSB_CTRL is high. This configures the deep S5 (EuP) mode selection. | | 2 | VSB | +PS_5VSB | ✅ | VSB pin is connected to +PS_5VSB, providing 5V standby power to the controller. Multiple decoupling capacitors are present on this rail. | | 3 | PS_IN# | PB_RES | ✅ | PS_IN# pin is connected to PB_RES net, which connects to the front panel power button (FP_PWRBTN) through a 33 ohm series resistor R308. This is the power button input. | | 4 | SLP_S5# | SLP_S4_L | ✅ | SLP_S5# pin is connected to SLP_S4_L net. There is a naming discrepancy (S5 vs S4), but this could be intentional if the controller uses the S4 sleep signal to control S5 power state transitions. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA pin is connected to DDR_SMB_DATA net, providing I2C/SMBus data communication, likely for DDR memory SPD reading or presence detection. | | 6 | SCLK | DDR_SMB_CLK | ✅ | SCLK pin is connected to DDR_SMB_CLK net, providing I2C/SMBus clock communication, likely for DDR memory SPD reading or presence detection. | | 7 | PS_OUT# | PS_OUT_L | ✅ | PS_OUT# pin is connected to PS_OUT_L net. R289 (1K pull-up to +PS_3VSB) is marked DNI, so the pin has no pull-up resistor. This suggests the pin is actively driven or doesn't require a pull-up. | | 8 | SYS5VSB_OFF | 5VSB_CTRL | ✅ | SYS5VSB_OFF pin is connected to 5VSB_CTRL net, which controls Q10 to pull S5_SEL low (enabling EuP mode) when high. R288 (1K) provides a pull-up to +PS_5VSB. | | 9 | GND | GND | ✅ | GND pin is connected to the ground net, providing the ground reference for the controller. | </details> <details> <summary><b>Q104</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +3VSB | ✅ | Source pins connected to +3VSB output rail. These pins carry the switched output current to the 3VSB rail. | | 2 | S2 | +3VSB | ✅ | Source pins connected to +3VSB output rail. These pins carry the switched output current to the 3VSB rail. | | 3 | S3 | +3VSB | ✅ | Source pins connected to +3VSB output rail. These pins carry the switched output current to the 3VSB rail. | | 4 | G | +3VSB_EN | ✅ | Gate pin connected to +3VSB_EN control signal. Gate is driven from +10V through R322 (100K) or pulled to GND by Q11. | | 5 | D1 | +PS_3VSB | ✅ | Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply. | | 6 | D2 | +PS_3VSB | ✅ | Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply. | | 7 | D3 | +PS_3VSB | ✅ | Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply. | | 8 | D4 | +PS_3VSB | ✅ | Drain pins connected to +PS_3VSB input power rail. These pins receive power from the 3VSB power supply. | </details> <details> <summary><b>Q103</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +5VSB | ✅ | Source pins connected to +5VSB output rail. These pins carry the switched output current to the 5VSB rail. | | 2 | S2 | +5VSB | ✅ | Source pins connected to +5VSB output rail. These pins carry the switched output current to the 5VSB rail. | | 3 | S3 | +5VSB | ✅ | Source pins connected to +5VSB output rail. These pins carry the switched output current to the 5VSB rail. | | 4 | G | 5VSB_LSENB | ✅ | Gate pin connected to 5VSB_LSENB control signal. Gate is driven from +10V through R324 (100K) or pulled to GND by Q14. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB input power rail. These pins receive power from the 5VSB power supply. | </details> <details> <summary><b>U36</b> - IRF9321 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.umw-ic.com/static/pdf/b379d167af492bcd72ba51c793d83236.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/IRF9321) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | $22N1502 | ✅ | Source pins connected to net $22N1502, which connects through ferrite beads L13 and L12 to DC_IN_1 (5V input from power jack). These pins carry input current from the DC jack. | | 2 | S2 | $22N1502 | ✅ | Source pins connected to net $22N1502, which connects through ferrite beads L13 and L12 to DC_IN_1 (5V input from power jack). These pins carry input current from the DC jack. | | 3 | S3 | $22N1502 | ✅ | Source pins connected to net $22N1502, which connects through ferrite beads L13 and L12 to DC_IN_1 (5V input from power jack). These pins carry input current from the DC jack. | | 4 | G | DC_GATE_ENB | ✅ | Gate pin connected to DC_GATE_ENB control signal. Gate is normally pulled to GND by R309 (100K) to turn on the P-channel device, or pulled toward source by Q106 during overvoltage conditions to turn off the device. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB output rail. These pins supply power to the 5VSB rail and downstream circuits. | </details> <details> <summary><b>Q6</b> - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB | ✅ | Drain pin correctly connected to +3VSB supply rail. This is the input of the high-side switch that provides power to the +VCC3 rail when enabled. | | G | GATE | SYS_EN | ✅ | Gate pin correctly connected to SYS_EN control signal. The gate is pulled up to +10V through R340 (100K) and can be pulled down by Q12 or Q7, providing adequate gate drive voltage. | | S | SOURCE | +VCC3 | ✅ | Source pin correctly connected to +VCC3 output rail. This is the output of the high-side switch that supplies power to downstream circuits when Q6 is enabled. | </details> <details> <summary><b>Q13</b> - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +5VSB | ✅ | Drain pin correctly connected to +5VSB supply rail. This is the input of the high-side switch that provides power to the +VCC rail when enabled. | | G | GATE | SYS_EN | ✅ | Gate pin correctly connected to SYS_EN control signal. The gate is pulled up to +10V through R340 (100K) and can be pulled down by Q12 or Q7, providing adequate gate drive voltage. | | S | SOURCE | +VCC | ✅ | Source pin correctly connected to +VCC output rail. This is the output of the high-side switch that supplies power to downstream circuits when Q13 is enabled. | </details> <details> <summary><b>Q2</b> - BAV99-7-F-S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | +PS_5VSB | ✅ | Anode 1 connected to +PS_5VSB for OR-ing the 5V standby supply. Connection is correct. | | 2 | A2 | $22N1417 | ✅ | Anode 2 connected to floating node $22N1417. This node is not connected to any voltage source, so this diode will not conduct in normal operation. Purpose is unclear but may be intentional for future expansion. | | 3 | C | $22N1419 | ✅ | Common cathode connected to $22N1419, which feeds into a capacitive voltage divider. Connection is correct for OR-ing output. | </details> <details> <summary><b>Q9</b> - BAV99-7-F-S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | $22N1417 | ✅ | Anode 1 connected to floating node $22N1417. This node is not connected to any voltage source, so this diode will not conduct in normal operation. Purpose is unclear but may be intentional for future expansion. | | 2 | A2 | +10V | ✅ | Anode 2 connected to +10V boost supply for OR-ing. Connection is correct. | | 3 | C | $22N1467 | ✅ | Common cathode connected to $22N1467, which feeds into a capacitive voltage divider. Connection is correct for OR-ing output. | </details> <details> <summary><b>D6</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB_PG | ✅ | Anode connected to +PS_3VSB_PG power good signal. Forms one input of an OR gate for the PMC_RSMRST reset signal. | | 2 | 2 | +3VSB_EN | ✅ | Anode connected to +3VSB_EN enable signal. Forms the second input of an OR gate for the PMC_RSMRST reset signal. | | 3 | 3 | PMC_RSMRST | ✅ | Common cathode connected to PMC_RSMRST reset signal output. Outputs the OR function of the two anode inputs. | </details> <details> <summary><b>Q10</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | S5_ENBL | ✅ | Drain pin correctly connected to S5_ENBL net, pulling down the signal when EuP is enabled. | | G | GATE | 5VSB_CTRL | ✅ | Gate pin correctly connected to 5VSB_CTRL signal from power controller U35 for EuP control. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration. | </details> <details> <summary><b>Q11</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB_EN | ✅ | Drain pin correctly connected to +3VSB_EN net, driving the gate of power FET Q104 through pull-up R322. | | G | GATE | +3VSB_EN_L | ✅ | Gate pin correctly connected to +3VSB_EN_L signal from Q4 collector for inverted control. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration. | </details> <details> <summary><b>Q14</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | 5VSB_LSENB | ✅ | Drain pin correctly connected to 5VSB_LSENB net, driving the gate of power FET Q103 through pull-up R324. | | G | GATE | 5VSB_GATE | ✅ | Gate pin correctly connected to 5VSB_GATE signal through R323 for controlled gate drive. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration. | </details> <details> <summary><b>Q12</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN | ✅ | Drain pin correctly connected to SYS_EN net with 100K pull-up to +10V, driving gates of power MOSFETs Q13 and Q6. | | G | GATE | SYS_EN_GATE | ✅ | Gate pin correctly connected to SYS_EN_GATE signal from Q7 drain for level-shifted control. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration. | </details> <details> <summary><b>Q4</b> - XSTR_NPN_40V_200mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/MMBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B | BASE | S5_ENBL | ✅ | Base pin correctly connected to S5_ENBL control signal through a pull-up resistor network and Q10 FET switch. | | C | COLLECTOR | +3VSB_EN_L | ✅ | Collector pin correctly connected to +3VSB_EN_L net with pull-up resistor R321 to +PS_5VSB, forming an inverter stage. | | E | EMITTER | GND | ✅ | Emitter pin correctly connected to GND as required for NPN transistor common-emitter configuration. | </details> <details> <summary><b>Q7</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN_GATE | ✅ | Drain pin correctly connected to SYS_EN_GATE net with 33K pull-up to +10V, driving the gate of Q12. | | G | GATE | SLP_S3_L | ✅ | Gate pin correctly connected to SLP_S3_L control signal for sleep state control. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND as required for N-channel MOSFET common-source configuration. | </details> <details> <summary><b>Q106</b> - BSS84 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/bss84-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BSS84) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | D | DC_GATE_ENB | ✅ | Drain pin drives the gate of U36 (P-channel MOSFET) to turn it off when overvoltage is detected. This connection is correct for the overvoltage protection function. | | G | G | $22N2300 | ✅ | Gate pin is controlled by a voltage divider formed by R855 (499Ω to source) and D13 (4.3V Zener to ground), creating an overvoltage threshold. This connection is correct for the protection circuit function. | | S | S | $22N1502 | ✅ | Source pin is connected to the input voltage through ferrite beads, providing the reference voltage for the protection circuit. This connection is correct. | </details> <details> <summary><b>D13</b> - 4620-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4620-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode pin is connected to ground, which is correct for a Zener diode used as a voltage clamp to set the overvoltage protection threshold. | | C | CATHODE | $22N2300 | ✅ | Cathode pin is connected to the gate of Q106, clamping it to 4.3V above ground to set the overvoltage protection threshold. This connection is correct. | </details> <details> <summary><b>J9</b> - JACK_PWR_2.1MM_RAPC712 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/414/RAPC712_cd.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/RAPC712) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DC_IN_1 | ✅ | Center pin connected to DC_IN_1 net, serving as the positive DC power input. The connection includes appropriate filtering capacitors and ferrite beads for EMI suppression. | | 2 | 2 | GND | ✅ | Sleeve pin correctly connected to GND net, serving as the ground/negative terminal of the power jack. | | 3 | 3 | GND | ✅ | Switch contact pin connected to GND net. This is a valid design choice when plug detection functionality is not required. | </details> <details> <summary><b>U25</b> - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT is connected to VR_HOT_L net. This is a thermal alert output that signals when the controller detects an over-temperature condition. | | 2 | SDIO | $23N2429 | ✅ | SDIO is connected through R80 (16.9Ω) to SVID_DATA-R. This is the SVID data I/O pin with appropriate series resistance for signal integrity. | | 3 | ALERT | $23N2431 | ✅ | ALERT is connected through R62 (0Ω jumper) to SVID_ALERT-R. This is the SVID alert output. | | 4 | SCLK | $23N2430 | ✅ | SCLK is connected through R81 (20Ω) to SVID_CLK-R. This is the SVID clock pin with appropriate series resistance. | | 5 | GND | AGND-VCORE | ✅ | GND is connected to AGND-VCORE, which connects through R37 (0Ω) to the main GND plane. This provides analog ground reference. | | 6 | VR_RDY | $23N3753 | ✅ | VR_RDY is connected through R79 (0Ω) to VCORE_PG. This is the power good/ready output indicating the regulator output is within regulation. | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN1-VIN8 and VIN_PAD are all connected to +5VSB_SW. These input voltage pins are properly paralleled to handle the input current. | | 8 | BST | $23N3711 | ✅ | BST is connected to the bootstrap circuit through R154 (2.2Ω) and C50 (0.22µF) to SW1. This provides bootstrap voltage for the high-side gate driver. | | 9 | GH | | ✅ | GH (high-side gate driver output) is not connected in this design. This appears to be intentional as the NCP81109 is an 8-phase capable controller being used in a 7-phase configuration, with the 8th phase (GH/GL) left unpopulated. | | 10 | SW1 | $23N3731 | ✅ | SW1 is connected to the bootstrap circuit and represents one of the switch node outputs. It connects through C50 to the bootstrap circuit. | | 18 | SW2 | VCORE-SW | ✅ | SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output. | | 25 | SW3 | VCORE-SW | ✅ | SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output. | | 26 | SW4 | VCORE-SW | ✅ | SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output. | | 27 | SW5 | VCORE-SW | ✅ | SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output. | | 28 | SW6 | VCORE-SW | ✅ | SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output. | | 29 | SW7 | VCORE-SW | ✅ | SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output. | | 51 | SW_PAD | VCORE-SW | ✅ | SW2-SW7 and SW_PAD are all connected to VCORE-SW. These switch nodes are paralleled and connect through L18 (470nH) to the output. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 are all connected to GND. These power ground pins are properly connected to the main ground plane. | | 30 | GL | | ✅ | GL (low-side gate driver output) is not connected in this design. This appears to be intentional as the 8th phase capability of the controller is not used in this 7-phase configuration. | | 31 | VBOOT | $23N3477 | ✅ | VBOOT is connected through R70 (88.7kΩ) to AGND-VCORE. This sets the boot voltage reference level. | | 32 | GND1 | AGND-VCORE | ✅ | GND1 and GND_PAD are connected to AGND-VCORE. These analog ground connections are properly tied to the analog ground plane. | | 49 | GND_PAD | AGND-VCORE | ✅ | GND1 and GND_PAD are connected to AGND-VCORE. These analog ground connections are properly tied to the analog ground plane. | | 33 | VCCP | $23N3625 | ✅ | VCCP is connected through R845 (1Ω) to +5VSB with C48 (4.7µF) decoupling. This is the charge pump output that provides gate drive supply. | | 34 | TSENSE | $23N3665 | ✅ | TSENSE is connected to a temperature sensing network with TH2 (100kΩ thermistor) and R131 (14kΩ) to ground, with C46 (0.1µF) filtering. This provides temperature monitoring. | | 35 | IMAX | $23N3681 | ✅ | IMAX is connected through R105 (44.2kΩ) to AGND-VCORE. This sets the maximum current limit. Text note indicates target of 14A. | | 36 | IOUT | $23N3683 | ✅ | IOUT is connected through R146 (16.5kΩ) to AGND-VCORE with C47 (470pF) filtering. This provides output current monitoring. | | 37 | ILIM | VCORE-ILIM | ✅ | ILIM is connected through R95 (15kΩ) to VCORE-CSCOMP. This sets the current limit threshold in conjunction with the current sense compensation network. | | 38 | CSCOMP | VCORE-CSCOMP | ✅ | CSCOMP is the current sense compensation node with complex network including C39, C40, R96, R95, and TH1. This implements current loop compensation with thermal compensation. | | 39 | CSSUM | VCORE-CSSUM | ✅ | CSSUM is the current sense sum node connected to DCR current sensing through R107 and R106. This sums the current sense signals from all phases. | | 40 | CSREF | VCORE-CSREF | ✅ | CSREF is connected through R108 (10Ω) to the output with C45 (1000pF) decoupling. This provides the current sense reference voltage. | | 41 | FREQ | $23N2930 | ✅ | FREQ is connected through R93 (18.7kΩ) to AGND-VCORE. This sets the switching frequency. Text note indicates target of 650kHz. | | 42 | COMP | VCORE-COMP | ✅ | COMP is the voltage loop compensation node with Type III compensation network including C35, C37, R88, and connections to FB. This implements voltage loop stability. | | 43 | FB | VCORE-FB | ✅ | FB is the feedback input connected to the compensation network and differential amplifier. This senses the output voltage for regulation. | | 44 | DIFFOUT | VCORE-DIFFOUT | ✅ | DIFFOUT is the differential amplifier output connected through R89 to FB and through R90, C36 to ground. This implements the differential sensing amplifier output. | | 45 | VSN | VR-VCORE-VSN | ✅ | VSN is the negative remote sense input connected through R65 (10Ω) from the ground sense point. This implements Kelvin sensing for accurate voltage regulation. | | 46 | VSP | VR-VCORE-VSP | ✅ | VSP is the positive remote sense input connected through R92 (100Ω) to +VCORE and through R63 (0Ω) to VCC_SENSE. This implements Kelvin sensing for accurate voltage regulation. | | 47 | VCC | $23N3860 | ✅ | VCC is connected through R166 (2.2Ω) to +5VSB with C24 (1µF) decoupling. This provides the internal supply voltage for the controller. | | 48 | EN | $23N5607 | ✅ | EN is connected through R849 (0Ω) to +VCC with R851 (10kΩ) pulldown and C433 (0.1µF) filtering. This enables the regulator when VCC is present. | </details> <details> <summary><b>L8</b> - 3120-0183 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3120-0183) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to the +5VSB input supply. This is the correct connection for an input filter inductor. | | 2 | 2 | +5VSB_SW | ✅ | Pin 2 connects to the +5VSB_SW filtered input rail that feeds the buck converter U25. This is the correct connection for an input filter inductor. | </details> <details> <summary><b>L18</b> - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Pin 1 connects to the VCORE-SW switching node from the multiphase buck controller U25. This is the correct connection for the inductor input in a buck converter topology. | | 2 | 2 | +VCORE | ✅ | Pin 2 connects to the +VCORE output rail. This is the correct connection for the inductor output in a buck converter topology. | </details> <details> <summary><b>C37</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP compensation pin of U25. | | 2 | 2 | $23N2824 | ✅ | Connected to intermediate node $23N2824, forming a zero with R88 in the compensation network. | </details> <details> <summary><b>C36</b> - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node. | | 2 | 2 | $23N2818 | ✅ | Connected to intermediate node $23N2818, forming an RC filter with R90 for the DIFFOUT signal. | </details> <details> <summary><b>C35</b> - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP compensation pin of U25. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node, forming the high-frequency pole in the Type III compensation network. | </details> <details> <summary><b>R88</b> - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2824 | ✅ | Connected to intermediate node $23N2824 in the voltage loop compensation network, forming a zero with C37. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node, completing the compensation network connection to the FB pin of U25. | </details> <details> <summary><b>R90</b> - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2818 | ✅ | Connected to intermediate node $23N2818, forming an RC filter with C36. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT, providing filtered connection to the differential output. | </details> <details> <summary><b>R89</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT, coupling the feedback signal to the differential output pin of U25. | </details> <details> <summary><b>R107</b> - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSSUM | ✅ | Pin 1 connects to VCORE-CSSUM (U25 pin 39), which is the current sense sum input of the multiphase controller. This is part of the current sensing network. | | 2 | 2 | $23N3209 | ✅ | Pin 2 connects to $23N3209, which connects through SP3 (PCB bridge short) to VCORE-SW (the switching node). This creates a 100K connection from the switching node to CSSUM. While this configuration is unusual for standard DCR current sensing, it may be intentional for the NCP81109GMNTXG controller's specific sensing method. | </details> <details> <summary><b>R108</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSREF | ✅ | Pin 1 connects to VCORE-CSREF (U25 pin 40), which is the current sense reference pin of the controller. This is part of the current sensing reference network. | | 2 | 2 | $23N3208 | ✅ | Pin 2 connects to $23N3208, which connects through SP4 (PCB bridge short) to +VCORE (the output voltage). This creates a 10 ohm connection from CSREF to the output voltage, which may be for load line regulation or adaptive voltage positioning (AVP). | </details> <details> <summary><b>SP3</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | PCB bridge short connecting VCORE-SW switching node (pin 1) to net $23N3209 (pin 2), which feeds through R107 (100K) to CSSUM. This configuration is unusual for typical DCR current sensing but appears intentional for the NCP81109GMNTXG controller's sensing method. | | 2 | 2 | $23N3209 | ✅ | PCB bridge short connecting VCORE-SW switching node (pin 1) to net $23N3209 (pin 2), which feeds through R107 (100K) to CSSUM. This configuration is unusual for typical DCR current sensing but appears intentional for the NCP81109GMNTXG controller's sensing method. | </details> <details> <summary><b>C46</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | Connected to $23N3665 which connects to U25 pin 34 (TSENSE). This provides filtering for the temperature sensing input. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE (analog ground) for proper signal integrity. This provides a clean ground reference for the analog sensing circuit. | </details> <details> <summary><b>R78</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | Connected to $23N3665 which connects to U25 pin 34 (TSENSE). This is the controller side of the temperature sensing circuit. | | 2 | 2 | $23N3662 | ✅ | Connected to $23N3662 which connects to the TH2/R131 temperature sensing divider. This is the thermistor network side. | </details> <details> <summary><b>R131</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to $23N3662 which connects to TH2 and through R78 to the TSENSE pin. This forms the upper part of the temperature sensing divider. | | 2 | 2 | GND | ✅ | Connected to GND to complete the temperature sensing divider. This provides the ground reference for the divider. | </details> <details> <summary><b>TH1</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP for current sensing compensation. This pin connects to the current sense compensation network of the DC-DC controller. | | 2 | 2 | $23N3115 | ✅ | Connected to intermediate node $23N3115 in the current compensation network. This pin connects through R96 to form part of the temperature-dependent divider. | </details> <details> <summary><b>TH2</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to intermediate node $23N3662 which feeds the TSENSE pin through R78. This pin is part of the temperature sensing divider network. | | 2 | 2 | GND | ✅ | Connected to GND to complete the temperature sensing divider network. This provides the reference for the TSENSE voltage divider. | </details> <details> <summary><b>R92</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output. Provides local positive voltage sensing path to the regulator. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP which goes to U25 VSP input. Part of the positive voltage sensing path. | </details> <details> <summary><b>R65</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | Connected to intermediate node $23N2860. Part of the negative sense path with 10Ω series resistance. | | 2 | 2 | VR-VCORE-VSN | ✅ | Connected to VR-VCORE-VSN which goes to U25 VSN input. Completes the negative sense path. | </details> <details> <summary><b>R63</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_SENSE | ✅ | Connected to VCC_SENSE for remote positive voltage sensing. 0Ω jumper allows direct connection when populated. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP. Shares connection with R92 pin 2 for parallel sensing paths. | </details> <details> <summary><b>C38</b> - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | Filtering capacitor on negative sense path. Marked DNI, possibly related to DAC feed forward functionality. | | 2 | 2 | VR-VCORE-VSN | ✅ | Filtering capacitor on negative sense path. Marked DNI, possibly related to DAC feed forward functionality. | </details> <details> <summary><b>R64</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VSS_SENSE | ✅ | Connected to VSS_SENSE for remote negative voltage sensing. 0Ω jumper allows direct connection when populated. | | 2 | 2 | $23N2860 | ✅ | Connected to intermediate node $23N2860. Shares connection with R91 pin 2 for parallel sensing paths. | </details> <details> <summary><b>C34</b> - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VCORE-VSP | ✅ | Differential filtering capacitor between VSP and VSN sense inputs. Marked DNI, indicating optional filtering. | | 2 | 2 | VR-VCORE-VSN | ✅ | Differential filtering capacitor between VSP and VSN sense inputs. Marked DNI, indicating optional filtering. | </details> <details> <summary><b>R91</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Provides local negative voltage sensing path to the regulator. | | 2 | 2 | $23N2860 | ✅ | Connected to intermediate node $23N2860. Part of the negative sensing network. | </details> <details> <summary><b>R81</b> - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and controller SCLK pin. Provides signal integrity and protection. | | 2 | 2 | $23N2430 | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and controller SCLK pin. Provides signal integrity and protection. | </details> <details> <summary><b>R62</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Zero-ohm jumper on SVID alert line between external SVID_ALERT-R signal and controller ALERT pin. Provides routing flexibility. | | 2 | 2 | $23N2431 | ✅ | Zero-ohm jumper on SVID alert line between external SVID_ALERT-R signal and controller ALERT pin. Provides routing flexibility. | </details> <details> <summary><b>R86</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect SVID_ALERT-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_ALERT-R | ✅ | DNI pull-up resistor that would connect SVID_ALERT-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system. | </details> <details> <summary><b>R80</b> - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and controller SDIO pin. Provides signal integrity and protection. | | 2 | 2 | $23N2429 | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and controller SDIO pin. Provides signal integrity and protection. | </details> <details> <summary><b>R87</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect SVID_CLK-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_CLK-R | ✅ | DNI pull-up resistor that would connect SVID_CLK-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system. | </details> <details> <summary><b>R85</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect SVID_DATA-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_DATA-R | ✅ | DNI pull-up resistor that would connect SVID_DATA-R to +V1P0S if installed. Not populated, suggesting pull-ups are provided elsewhere in the system. | </details> <details> <summary><b>C433</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ✅ | Connected to EN pin of U25 through net $23N5607 for filtering and decoupling. | | 2 | 2 | GND | ✅ | Connected to GND to provide filtering reference and complete bypass path. | </details> <details> <summary><b>R849</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC to provide enable signal to U25 EN pin through 0-ohm resistor. | | 2 | 2 | $23N5607 | ✅ | Connected to EN pin of U25 voltage regulator controller through net $23N5607. | </details> <details> <summary><b>R851</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ✅ | Connected to EN pin of U25 through net $23N5607 to provide pull-down. | | 2 | 2 | GND | ✅ | Connected to GND to complete pull-down path for EN pin. | </details> <details> <summary><b>R79</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | 0-ohm jumper connecting VR_RDY output from U25 pin 6 to VCORE_PG net, allowing the voltage regulator ready signal to be used as the system power good signal. | | 2 | 2 | $23N3753 | ✅ | 0-ohm jumper connecting VR_RDY output from U25 pin 6 to VCORE_PG net, allowing the voltage regulator ready signal to be used as the system power good signal. | </details> <details> <summary><b>R167</b> - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | 1.91K pull-up resistor connecting VCORE_PG to +VCC3 supply, providing the necessary pull-up for the active-high power good signal. | | 2 | 2 | VCORE_PG | ✅ | 1.91K pull-up resistor connecting VCORE_PG to +VCC3 supply, providing the necessary pull-up for the active-high power good signal. | </details> <details> <summary><b>R94</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | 1K pull-up resistor connecting VCORE_GFX_PG to +VCC3 supply, providing the necessary pull-up for the combined power good signal output from the diode AND gate. | | 2 | 2 | +VCC3 | ✅ | 1K pull-up resistor connecting VCORE_GFX_PG to +VCC3 supply, providing the necessary pull-up for the combined power good signal output from the diode AND gate. | </details> <details> <summary><b>C25</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | 0.1uF decoupling capacitor on VCORE_PG signal to filter noise and provide local charge storage. | | 2 | 2 | GND | ✅ | 0.1uF decoupling capacitor on VCORE_PG signal to filter noise and provide local charge storage. | </details> <details> <summary><b>C65</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0.1uF decoupling capacitor on VCORE_GFX_PG signal to filter noise and provide local charge storage. | | 2 | 2 | VCORE_GFX_PG | ✅ | 0.1uF decoupling capacitor on VCORE_GFX_PG signal to filter noise and provide local charge storage. | </details> <details> <summary><b>D4</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Connected to VCORE_PG power good signal. This pin should be an anode for the OR-gate configuration to function correctly with active-high power good signals. | | 2 | 2 | VGFX_PG | ✅ | Connected to VGFX_PG power good signal. This pin should be an anode for the OR-gate configuration. | | 3 | 3 | VCORE_GFX_PG | ✅ | Connected to VCORE_GFX_PG combined power good output. This pin is the common cathode in standard BAT54A configuration. | </details> <details> <summary><b>R154</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3711 | ✅ | Connected to U25 pin 8 (BST) as part of the bootstrap circuit for the high-side gate driver. | | 2 | 2 | $23N3733 | ✅ | Connected to C50 pin 1, forming the intermediate node in the bootstrap RC network between BST and SW1. | </details> <details> <summary><b>C50</b> - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3733 | ✅ | Connected to R154 pin 2, forming one side of the bootstrap capacitor in the gate driver circuit. | | 2 | 2 | $23N3731 | ✅ | Connected to U25 pin 10 (SW1), providing the bootstrap capacitor return path to the switching node. | </details> <details> <summary><b>R70</b> - 1120-0289 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3477 | ✅ | Connected to U25 pin 31 (VBOOT) to set the boot voltage configuration to 1.1V, which sets the device address to 0x0. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE (analog ground) to provide the ground reference for the VBOOT voltage divider. | </details> <details> <summary><b>R166</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This provides the input voltage for the series resistor feeding the VCC pin of U25. | | 2 | 2 | $23N3860 | ✅ | Connected to net $23N3860 which feeds U25 pin 47 (VCC) and decoupling capacitor C24. This provides power to the controller IC with series resistance for inrush limiting. | </details> <details> <summary><b>C24</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3860 | ✅ | Connected to net $23N3860 which is the VCC supply for U25 through series resistor R166. This is the positive terminal of the VCC decoupling capacitor. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE (analog ground). This provides the ground reference for the VCC decoupling capacitor, correctly using analog ground for the analog supply pin. | </details> <details> <summary><b>R845</b> - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This provides the input voltage for the series resistor feeding the VCCP pin of U25. | | 2 | 2 | $23N3625 | ✅ | Connected to net $23N3625 which feeds U25 pin 33 (VCCP) and decoupling capacitor C48. This provides power to the controller IC's power stage circuitry with series resistance for inrush limiting. | </details> <details> <summary><b>C48</b> - 2232-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3625 | ✅ | Connected to net $23N3625 which is the VCCP supply for U25 through series resistor R845. This is the positive terminal of the VCCP decoupling capacitor. | | 2 | 2 | GND | ✅ | Connected to GND (power ground). This provides the ground reference for the VCCP decoupling capacitor, using power ground which is appropriate if VCCP powers gate drivers or power stage circuitry. | </details> <details> <summary><b>R93</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2930 | ✅ | Pin 1 connects to the FREQ pin (pin 41) of U25 to set the switching frequency. This connection is correct. | | 2 | 2 | AGND-VCORE | ✅ | Pin 2 connects to AGND-VCORE (analog ground) to complete the frequency setting resistor. This connection is correct. | </details> <details> <summary><b>R168</b> - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Connected to VCORE-SW switching node. Forms part of an RC snubber network with C52 to dampen switching node ringing. | | 2 | 2 | $23N3990 | ✅ | Connected to intermediate node $23N3990 which connects to C52 pin 1. Completes the RC snubber network to ground. | </details> <details> <summary><b>C52</b> - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3990 | ✅ | Connected to intermediate node $23N3990 from R168. Forms part of RC snubber network. | | 2 | 2 | GND | ✅ | Connected to GND. Completes the RC snubber path from switching node to ground. | </details> <details> <summary><b>SP4</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output rail. Provides output voltage reference for load line regulation circuit. | | 2 | 2 | $23N3208 | ✅ | Connected to $23N3208 which feeds through R108 (10Ω) to CSREF pin of U25. Implements load line regulation by referencing CSREF to output voltage. | </details> <details> <summary><b>R37</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0-ohm jumper connecting main ground (GND) to analog ground (AGND-VCORE), providing single-point ground connection between power and analog ground planes. | | 2 | 2 | AGND-VCORE | ✅ | 0-ohm jumper connecting main ground (GND) to analog ground (AGND-VCORE), providing single-point ground connection between power and analog ground planes. | </details> <details> <summary><b>C53</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3610 | ✅ | 1.0uF decoupling capacitor for U26 VCC supply between $24N3610 and AGND-VGFX. | | 2 | 2 | AGND-VGFX | ✅ | 1.0uF decoupling capacitor for U26 VCC supply between $24N3610 and AGND-VGFX. | </details> <details> <summary><b>C186</b> - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3596 | ✅ | 0.22uF bootstrap capacitor between BST pin and SW1 switching node for high-side gate driver. | | 2 | 2 | $24N3595 | ✅ | 0.22uF bootstrap capacitor between BST pin and SW1 switching node for high-side gate driver. | </details> <details> <summary><b>R66</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0 ohm jumper connecting analog ground AGND-VGFX to main ground GND for star ground configuration. | | 2 | 2 | AGND-VGFX | ✅ | 0 ohm jumper connecting analog ground AGND-VGFX to main ground GND for star ground configuration. | </details> <details> <summary><b>C185</b> - 2232-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3578 | ✅ | 4.7uF decoupling capacitor for U26 VCCP supply between $24N3578 and GND. | | 2 | 2 | GND | ✅ | 4.7uF decoupling capacitor for U26 VCCP supply between $24N3578 and GND. | </details> <details> <summary><b>R203</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3542 | ✅ | 18.7K resistor setting switching frequency to 650kHz per text note. | | 2 | 2 | AGND-VGFX | ✅ | 18.7K resistor setting switching frequency to 650kHz per text note. | </details> <details> <summary><b>R229</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | 2.20 ohm resistor providing current limiting and filtering between +5VSB and VCC supply pin of U26. | | 2 | 2 | $24N3610 | ✅ | 2.20 ohm resistor providing current limiting and filtering between +5VSB and VCC supply pin of U26. | </details> <details> <summary><b>R846</b> - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | 1.00 ohm resistor providing current limiting and filtering between +5VSB and VCCP supply pin of U26. | | 2 | 2 | $24N3578 | ✅ | 1.00 ohm resistor providing current limiting and filtering between +5VSB and VCCP supply pin of U26. | </details> <details> <summary><b>R170</b> - 1120-0009 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3564 | ✅ | 100K resistor pulling down VBOOT pin for address configuration. Text note indicates VBOOT should be 1.1V for ADDR=0x1. | | 2 | 2 | AGND-VGFX | ✅ | 100K resistor pulling down VBOOT pin for address configuration. Text note indicates VBOOT should be 1.1V for ADDR=0x1. | </details> <details> <summary><b>U26</b> - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin connected to VR_HOT_L signal for thermal warning output. | | 2 | SDIO | $24N3490 | ✅ | SDIO pin connected to SVID data line through 16.9 ohm series resistor with 69.8 ohm pull-up to +V1P0S. | | 3 | ALERT | $24N3492 | ✅ | ALERT pin connected to SVID alert line through 0 ohm jumper, but pull-up resistor R196 is DNI. | | 4 | SCLK | $24N3491 | ✅ | SCLK pin connected to SVID clock line through 20 ohm series resistor with 69.8 ohm pull-up to +V1P0S. | | 5 | GND | AGND-VGFX | ✅ | GND pin connected to AGND-VGFX analog ground, which connects to main GND through 0 ohm jumper R66. | | 6 | VR_RDY | $24N3598 | ✅ | VR_RDY pin connected to power good signal VGFX_PG through 0 ohm jumper, with 1.91K pull-up to +VCC3. | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22uF and 0.1uF decoupling capacitors. | | 8 | BST | $24N3593 | ✅ | BST pin connected to bootstrap circuit with 2.20 ohm resistor and 0.22uF capacitor to SW1 node. | | 9 | GH | | ✅ | GH pin has no net connection shown in schematic, likely connects to external high-side MOSFET gate. | | 10 | SW1 | $24N3595 | ✅ | SW1 pin connected to bootstrap capacitor return and switching node. | | 18 | SW2 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation. | | 25 | SW3 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation. | | 26 | SW4 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation. | | 27 | SW5 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation. | | 28 | SW6 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation. | | 29 | SW7 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW switching node for paralleled multiphase operation. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 30 | GL | | ✅ | GL pin has no net connection shown in schematic, likely connects to external low-side MOSFET gate. | | 31 | VBOOT | $24N3564 | ✅ | VBOOT pin pulled down through 100K resistor to AGND-VGFX. Text note indicates VBOOT should be 1.1V for ADDR=0x1, but no voltage source is visible. | | 32 | GND1 | AGND-VGFX | ✅ | GND1 pin connected to AGND-VGFX analog ground. | | 33 | VCCP | $24N3578 | ✅ | VCCP pin supplied from +5VSB through 1.00 ohm resistor with 4.7uF decoupling capacitor. | | 34 | TSENSE | $24N3584 | ✅ | TSENSE pin connected to thermistor temperature sensing network with 100K@25C thermistor and 14K resistor to ground. | | 35 | IMAX | $24N3588 | ✅ | IMAX pin set to 14A maximum current limit by 44.2K resistor to ground per text note. | | 36 | IOUT | $24N3589 | ✅ | IOUT pin configured for output current monitoring with 16.5K resistor and 470pF filter capacitor. | | 37 | ILIM | VGFX-ILIM | ✅ | ILIM pin connected to current limit compensation network through 15K resistor. | | 38 | CSCOMP | VGFX-CSCOMP | ✅ | CSCOMP pin configured with current sense compensation network including thermistor for temperature-dependent current limiting. | | 39 | CSSUM | VGFX-CSSUM | ✅ | CSSUM pin connected to summed current sense signal through resistor network. | | 40 | CSREF | VGFX-CSREF | ✅ | CSREF pin connected to current sense reference with 10 ohm resistor and 1000pF filter capacitor. | | 41 | FREQ | $24N3542 | ✅ | FREQ pin set to 650kHz switching frequency by 18.7K resistor per text note. | | 42 | COMP | VGFX-COMP | ✅ | COMP pin configured with voltage loop compensation network using 47pF and 2200pF capacitors. | | 43 | FB | VGFX-FB | ✅ | FB pin connected to feedback voltage divider with 3.01K and 1K resistors, plus compensation network. | | 44 | DIFFOUT | VGFX-DIFFOUT | ✅ | DIFFOUT pin connected to differential amplifier output with 1K and 47 ohm resistors for remote sensing. | | 45 | VSN | VR-VGFX-VSN | ✅ | VSN pin connected to negative remote sense input through 10 ohm resistor, sensing ground reference. | | 46 | VSP | VR-VGFX-VSP | ✅ | VSP pin connected to positive remote sense input through 100 ohm resistor, sensing output voltage at remote location. | | 47 | VCC | $24N3610 | ✅ | VCC pin supplied from +5VSB through 2.20 ohm resistor with 1.0uF decoupling capacitor. | | 48 | EN | $24N6011 | ✅ | EN pin connected to +VCC through 0 ohm jumper with 10K pull-down, enabling the regulator when VCC is present. | | 49 | GND_PAD | AGND-VGFX | ✅ | GND_PAD exposed pad connected to AGND-VGFX analog ground. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN_PAD exposed pad connected to +5VSB_SW input supply. | | 51 | SW_PAD | VGFX-SW | ✅ | SW_PAD exposed pad connected to VGFX-SW switching node. | </details> <details> <summary><b>R228</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3593 | ✅ | 2.20 ohm resistor in bootstrap circuit limiting charging current of bootstrap capacitor C186. | | 2 | 2 | $24N3596 | ✅ | 2.20 ohm resistor in bootstrap circuit limiting charging current of bootstrap capacitor C186. | </details> <details> <summary><b>R193</b> - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Series resistor (16.9Ω) between system SVID data line (SVID_DATA-R) and voltage regulator controller SDIO pin. Provides signal integrity and current limiting for the SVID interface. | | 2 | 2 | $24N3490 | ✅ | Series resistor (16.9Ω) between system SVID data line (SVID_DATA-R) and voltage regulator controller SDIO pin. Provides signal integrity and current limiting for the SVID interface. | </details> <details> <summary><b>R195</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor (69.8Ω) on SVID data line from +V1P0S to SVID_DATA-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage. | | 2 | 2 | SVID_DATA-R | ✅ | Pull-up resistor (69.8Ω) on SVID data line from +V1P0S to SVID_DATA-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage. | </details> <details> <summary><b>R67</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Zero-ohm jumper between system SVID alert line (SVID_ALERT-R) and voltage regulator controller ALERT pin. The 0Ω value suggests ALERT is a push-pull output that doesn't require series resistance. | | 2 | 2 | $24N3492 | ✅ | Zero-ohm jumper between system SVID alert line (SVID_ALERT-R) and voltage regulator controller ALERT pin. The 0Ω value suggests ALERT is a push-pull output that doesn't require series resistance. | </details> <details> <summary><b>C432</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Positive terminal of decoupling capacitor connected to +V1P0S power rail. | | 2 | 2 | GND | ✅ | Negative terminal of decoupling capacitor connected to ground. | </details> <details> <summary><b>R197</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor (69.8Ω) on SVID clock line from +V1P0S to SVID_CLK-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage. | | 2 | 2 | SVID_CLK-R | ✅ | Pull-up resistor (69.8Ω) on SVID clock line from +V1P0S to SVID_CLK-R. The value is unusually low for typical I2C pull-ups but may be optimized for high-speed SVID operation at low voltage. | </details> <details> <summary><b>R194</b> - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Series resistor (20.0Ω) between system SVID clock line (SVID_CLK-R) and voltage regulator controller SCLK pin. Provides signal integrity and current limiting for the SVID interface. | | 2 | 2 | $24N3491 | ✅ | Series resistor (20.0Ω) between system SVID clock line (SVID_CLK-R) and voltage regulator controller SCLK pin. Provides signal integrity and current limiting for the SVID interface. | </details> <details> <summary><b>R196</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor (69.8Ω) on SVID alert line, marked DNI (Do Not Install). This is consistent with ALERT being a push-pull output that does not require a pull-up resistor. | | 2 | 2 | SVID_ALERT-R | ✅ | Pull-up resistor (69.8Ω) on SVID alert line, marked DNI (Do Not Install). This is consistent with ALERT being a push-pull output that does not require a pull-up resistor. | </details> <details> <summary><b>L4</b> - 3120-0266 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | 2 | +VGFX | ❌ | <details><summary>Inductor connections are topologically correct (pin 1 to switching node VGFX-SW, pin 2 to output +VGFX), but the inductor current rating is insufficient for the design requirements.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="80.79,53.60,88.29,61.10" aspect-ratio="1.29" } <ul><li>Pin 1 connects to net VGFX-SW (switching node from U26) <em>(from schematic)</em></li><li>Pin 2 connects to net +VGFX (regulated output voltage) <em>(from schematic)</em></li><li>The inductor is specified as 470nH with 17.5A current rating and 4.2mΩ DCR <em>(from schematic)</em></li><li>Multiple output capacitors (C66, C67, C68, C78, C79, C80, C81, C76, C77) connect to +VGFX <em>(from schematic)</em></li><li>In a buck converter topology, the inductor connects between the switching node and the output voltage rail, which is correct here <em>(reasoning)</em></li><li>A text note &#x27;IMAX = 24A&#x27; is positioned at coordinates (462.28, 229.87), very close to L4&#x27;s position at (462.28, 181.61) <em>(from schematic)</em></li><li>A separate text note &#x27;IMAX = 14A&#x27; is positioned at (388.62, 242.57) near the current limit configuration resistors R207 and R227 <em>(from schematic)</em></li><li>R227 (16.5K) connects U26 pin 36 (IOUT) to AGND-VGFX, and R207 (44.2K) connects U26 pin 35 (IMAX) to AGND-VGFX, setting the controller current limit <em>(from schematic)</em></li><li>The switching frequency is 650kHz based on text note and R203 (18.7K) connected to the FREQ pin <em>(from schematic)</em></li><li>There is a significant discrepancy between the inductor&#x27;s 17.5A rating and the 24A specification noted near the inductor <em>(reasoning)</em></li><li>Even if the controller is configured for 14A average current limit, the peak inductor current including switching ripple could approach or exceed 17.5A <em>(reasoning)</em></li><li>For a buck converter with Vin≈5V (from +5VSB_SW) and Vout≈1V (typical GPU core voltage), 470nH inductance, and 650kHz switching frequency, the current ripple would be approximately 2.6A peak-to-peak <em>(reasoning)</em></li><li>At 14A average current, the peak current would be approximately 15.3A, which provides minimal margin below the 17.5A rating <em>(reasoning)</em></li><li>At 24A average current (if that is the actual requirement), the peak current would exceed 25A, far exceeding the inductor&#x27;s rating <em>(reasoning)</em></li><li>Operating an inductor above its rated current can cause saturation (loss of inductance) or thermal failure <em>(reasoning)</em></li><li>The inductor should be rated for at least the maximum expected current with 20-30% design margin <em>(reasoning)</em></li><li>The design has conflicting specifications that need resolution: either the 24A requirement should be verified and a higher-rated inductor used, or the 24A specification is incorrect and should be corrected to match the actual 14A design limit <em>(reasoning)</em></li></ul></details> | | 1 | 1 | VGFX-SW | ✅ | Pin 1 connects to the switching node VGFX-SW from the multiphase controller U26. This is the correct connection for the input side of a buck converter output inductor. | </details> <details> <summary><b>R231</b> - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Forms an RC snubber network with C187 to dampen switching node ringing and reduce EMI. Pin 1 connects to VGFX-SW switching node, pin 2 connects through C187 to GND. | | 2 | 2 | $24N3623 | ✅ | Forms an RC snubber network with C187 to dampen switching node ringing and reduce EMI. Pin 1 connects to VGFX-SW switching node, pin 2 connects through C187 to GND. | </details> <details> <summary><b>C187</b> - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3623 | ✅ | Forms the capacitive element of an RC snubber network with R231. Pin 1 connects to the snubber resistor, pin 2 connects to GND. | | 2 | 2 | GND | ✅ | Forms the capacitive element of an RC snubber network with R231. Pin 1 connects to the snubber resistor, pin 2 connects to GND. | </details> <details> <summary><b>R854</b> - 1130-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Pre-load resistor connecting +VGFX output to GND. Provides minimum load current for stable regulator operation and faster transient response. | | 2 | 2 | GND | ✅ | Pre-load resistor connecting +VGFX output to GND. Provides minimum load current for stable regulator operation and faster transient response. | </details> <details> <summary><b>SP2</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Pin 1 connects to the switching node VGFX-SW. This short provides an optional connection from the switching node to the current sense sum network through R224. | | 2 | 2 | $24N3558 | ✅ | Pin 2 connects to net $24N3558, which connects through R224 (100kΩ) to VGFX-CSSUM (pin 39 of U26). This samples the switching node voltage for current sensing. A design note specifies this short should be placed on the solder side close to the inductor. | </details> <details> <summary><b>SP1</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Pin 1 connects to the output voltage rail +VGFX. This short provides an optional connection from the output to the current sense reference network through R225. | | 2 | 2 | $24N3559 | ✅ | Pin 2 connects to net $24N3559, which connects through R225 (10Ω) to VGFX-CSREF (pin 40 of U26). This provides a reference voltage for the current sensing circuit. A design note specifies this short should be placed on the solder side close to the inductor. | </details> <details> <summary><b>R198</b> - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3524 | ✅ | Connected to net $24N3524, which is part of the feedback divider and compensation network. This connection appears correct for the voltage feedback compensation circuit. | | 2 | 2 | VGFX-FB | ✅ | Connected to VGFX-FB feedback network. This connection is correct for the voltage feedback path. | </details> <details> <summary><b>R200</b> - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3522 | ✅ | Connected to net $24N3522, which is part of the differential sensing network. This connection appears correct. | | 2 | 2 | VGFX-DIFFOUT | ✅ | Connected to VGFX-DIFFOUT. This connection is correct for the differential sensing network. | </details> <details> <summary><b>C63</b> - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | Connected to VGFX-FB feedback network. This connection is correct for the differential sensing path. | | 2 | 2 | $24N3522 | ✅ | Connected to net $24N3522, which is part of the differential sensing network. This connection is correct for AC coupling or filtering. | </details> <details> <summary><b>C64</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | Connected to VGFX-COMP compensation pin. This connection is correct for the voltage loop compensation network. | | 2 | 2 | $24N3524 | ✅ | Connected to net $24N3524, forming an RC compensation network with R198. This connection is correct for Type II or Type III compensation. | </details> <details> <summary><b>R199</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | Connected to VGFX-FB feedback network. This connection is correct for the differential sensing configuration. | | 2 | 2 | VGFX-DIFFOUT | ✅ | Connected to VGFX-DIFFOUT, which connects to U26 pin 44 (DIFFOUT). This connection is correct for differential remote voltage sensing. | </details> <details> <summary><b>C62</b> - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | Connected to VGFX-COMP compensation pin. This connection is correct for the voltage loop compensation network. | | 2 | 2 | VGFX-FB | ✅ | Connected to VGFX-FB feedback network. This connection is correct for Type II compensation. | </details> <details> <summary><b>R68</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCCGT_SENSE | ✅ | 0Ω jumper connecting remote voltage sense point VCCGT_SENSE to the VSP pin (U26 pin 46) of the voltage regulator controller. This enables remote sensing of the output voltage at the load, compensating for voltage drops in the power distribution network. | | 2 | 2 | VR-VGFX-VSP | ✅ | 0Ω jumper connecting remote voltage sense point VCCGT_SENSE to the VSP pin (U26 pin 46) of the voltage regulator controller. This enables remote sensing of the output voltage at the load, compensating for voltage drops in the power distribution network. | </details> <details> <summary><b>R69</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0Ω jumper connecting GND to intermediate node $24N3528, which feeds through R169 (10Ω) to the VSN pin (U26 pin 45). This provides a direct ground reference for the differential voltage sense. Part of a design flexibility configuration where either R69 or R201 can be populated. | | 2 | 2 | $24N3528 | ✅ | 0Ω jumper connecting GND to intermediate node $24N3528, which feeds through R169 (10Ω) to the VSN pin (U26 pin 45). This provides a direct ground reference for the differential voltage sense. Part of a design flexibility configuration where either R69 or R201 can be populated. | </details> <details> <summary><b>R201</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 100Ω resistor connecting GND to intermediate node $24N3528, in parallel with 0Ω jumper R69. Provides an alternative configuration option with series resistance if R69 is not populated. Part of a design flexibility feature for different sensing configurations. | | 2 | 2 | $24N3528 | ✅ | 100Ω resistor connecting GND to intermediate node $24N3528, in parallel with 0Ω jumper R69. Provides an alternative configuration option with series resistance if R69 is not populated. Part of a design flexibility feature for different sensing configurations. | </details> <details> <summary><b>R202</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | 100Ω resistor connecting +VGFX output to VR-VGFX-VSP (U26 pin 46), providing a local sense path in parallel with the remote sense through R68. Ensures VSP has a valid voltage reference even if remote sense is disconnected, which is a common design practice for robust remote sensing. | | 2 | 2 | VR-VGFX-VSP | ✅ | 100Ω resistor connecting +VGFX output to VR-VGFX-VSP (U26 pin 46), providing a local sense path in parallel with the remote sense through R68. Ensures VSP has a valid voltage reference even if remote sense is disconnected, which is a common design practice for robust remote sensing. | </details> <details> <summary><b>R169</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | 10Ω resistor in series with the VSN sense path, connecting intermediate node $24N3528 to VR-VGFX-VSN (U26 pin 45). Provides filtering and current limiting for the negative sense input, forming part of the differential remote sense circuit. | | 2 | 2 | VR-VGFX-VSN | ✅ | 10Ω resistor in series with the VSN sense path, connecting intermediate node $24N3528 to VR-VGFX-VSN (U26 pin 45). Provides filtering and current limiting for the negative sense input, forming part of the differential remote sense circuit. | </details> <details> <summary><b>C61</b> - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VGFX-VSP | ✅ | 1000pF capacitor between VSP and VSN sense inputs, marked DNI. Would provide differential mode filtering for the remote sense signals if populated, but is not required for this design. | | 2 | 2 | VR-VGFX-VSN | ✅ | 1000pF capacitor between VSP and VSN sense inputs, marked DNI. Would provide differential mode filtering for the remote sense signals if populated, but is not required for this design. | </details> <details> <summary><b>C104</b> - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | 0.01µF capacitor between intermediate node $24N3528 and VSN, marked DNI. Would provide additional filtering for the VSN sense path if populated, forming an RC filter with R169 (10Ω). | | 2 | 2 | VR-VGFX-VSN | ✅ | 0.01µF capacitor between intermediate node $24N3528 and VSN, marked DNI. Would provide additional filtering for the VSN sense path if populated, forming an RC filter with R169 (10Ω). | </details> <details> <summary><b>R204</b> - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-ILIM | ✅ | Connected to VGFX-ILIM (pin 37 of U26). Sets the current limit threshold. | | 2 | 2 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP (pin 38 of U26). The 15K value sets the current limit level. | </details> <details> <summary><b>TH3</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP (pin 38 of U26). Provides temperature compensation for current sensing. | | 2 | 2 | $24N3557 | ✅ | Connected to intermediate node $24N3557. Works with R205 to provide temperature-compensated DCR current sensing. | </details> <details> <summary><b>R224</b> - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM (pin 39 of U26). Part of the current sense sum network for DCR current sensing. | | 2 | 2 | $24N3558 | ✅ | Connected to $24N3558, which connects to VGFX-SW through SP2. This forms the switching node connection for DCR current sensing. | </details> <details> <summary><b>R225</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Connected to VGFX-CSREF (pin 40 of U26). Provides current sense reference from the output voltage. | | 2 | 2 | $24N3559 | ✅ | Connected to $24N3559, which connects to +VGFX through SP1. Provides output-tracking current sense reference. | </details> <details> <summary><b>R205</b> - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP (pin 38 of U26). Provides DC feedback for current loop compensation. | | 2 | 2 | $24N3557 | ✅ | Connected to intermediate node $24N3557. In parallel with TH3 to provide temperature-compensated current sensing. | </details> <details> <summary><b>C166</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP (pin 38 of U26). In parallel with C113 for additional filtering. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM (pin 39 of U26). Provides additional filtering for current sense signal. | </details> <details> <summary><b>C167</b> - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Connected to VGFX-CSREF (pin 40 of U26). Filters the current sense reference signal. | | 2 | 2 | GND | ✅ | Connected to GND. Provides filtering for the CSREF signal. | </details> <details> <summary><b>C113</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP (pin 38 of U26). Provides AC coupling and filtering for current sense signal. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM (pin 39 of U26). Forms AC coupling path for current loop compensation. | </details> <details> <summary><b>R223</b> - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3557 | ✅ | Connected to intermediate node $24N3557, which is shared with R205, TH3, and C166. Part of the current sense scaling network. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM (pin 39 of U26). Forms part of the voltage divider for current sense scaling. | </details> <details> <summary><b>C184</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | C184 filters the current sense output signal on U26 pin 36 (IOUT) by connecting between the IOUT pin and AGND-VGFX. The 470pF value provides high-frequency noise filtering. | | 2 | 2 | AGND-VGFX | ✅ | C184 filters the current sense output signal on U26 pin 36 (IOUT) by connecting between the IOUT pin and AGND-VGFX. The 470pF value provides high-frequency noise filtering. | </details> <details> <summary><b>TH4</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | TH4 is a 100K NTC thermistor that forms part of the temperature sensing network for U26 pin 34 (TSENSE). It connects between the thermistor network node and GND, working with R226 to create a temperature-dependent voltage divider. | | 2 | 2 | GND | ✅ | TH4 is a 100K NTC thermistor that forms part of the temperature sensing network for U26 pin 34 (TSENSE). It connects between the thermistor network node and GND, working with R226 to create a temperature-dependent voltage divider. | </details> <details> <summary><b>R227</b> - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | R227 sets the current sense gain for the IOUT monitoring pin by connecting U26 pin 36 (IOUT) to AGND-VGFX. The 16.5K value determines the scaling of the current sense output. | | 2 | 2 | AGND-VGFX | ✅ | R227 sets the current sense gain for the IOUT monitoring pin by connecting U26 pin 36 (IOUT) to AGND-VGFX. The 16.5K value determines the scaling of the current sense output. | </details> <details> <summary><b>R178</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | R178 is a 0-ohm jumper that connects U26 pin 34 (TSENSE) to the thermistor network. It allows for optional series resistance in the temperature sense path if needed for calibration or filtering. | | 2 | 2 | $24N3583 | ✅ | R178 is a 0-ohm jumper that connects U26 pin 34 (TSENSE) to the thermistor network. It allows for optional series resistance in the temperature sense path if needed for calibration or filtering. | </details> <details> <summary><b>R226</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | R226 forms part of the temperature sensing voltage divider by connecting between the thermistor network node and GND. The 14K value works with TH4 to create a temperature-dependent voltage for U26 pin 34 (TSENSE). | | 2 | 2 | GND | ✅ | R226 forms part of the temperature sensing voltage divider by connecting between the thermistor network node and GND. The 14K value works with TH4 to create a temperature-dependent voltage for U26 pin 34 (TSENSE). | </details> <details> <summary><b>C168</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | C168 is a bypass capacitor that filters noise on the TSENSE input by connecting between U26 pin 34 (TSENSE) and AGND-VGFX. The 0.1uF value provides effective filtering of high-frequency noise. | | 2 | 2 | AGND-VGFX | ✅ | C168 is a bypass capacitor that filters noise on the TSENSE input by connecting between U26 pin 34 (TSENSE) and AGND-VGFX. The 0.1uF value provides effective filtering of high-frequency noise. | </details> <details> <summary><b>R207</b> - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3588 | ✅ | R207 sets the maximum current limit for the voltage regulator by connecting U26 pin 35 (IMAX) to AGND-VGFX. The 44.2K value is intended to set a 14A current limit per the nearby text note. | | 2 | 2 | AGND-VGFX | ✅ | R207 sets the maximum current limit for the voltage regulator by connecting U26 pin 35 (IMAX) to AGND-VGFX. The 44.2K value is intended to set a 14A current limit per the nearby text note. | </details> <details> <summary><b>R184</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG power good signal net. | | 2 | 2 | $24N3598 | ✅ | Connected to net $24N3598 which is the VR_RDY output (pin 6) of U26. | </details> <details> <summary><b>R850</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC power rail to provide enable signal to U26. | | 2 | 2 | $24N6011 | ✅ | Connected to net $24N6011 which drives the EN pin (pin 48) of U26. With R852 also populated, this creates a current path from +VCC through R852 (10K) to GND, wasting approximately 0.5mA (assuming 5V rail). | </details> <details> <summary><b>R852</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to net $24N6011 which is the enable signal for U26. With R850 also populated, this creates unnecessary current draw from +VCC to GND. | | 2 | 2 | GND | ✅ | Connected to GND to provide pull-down for the enable signal. | </details> <details> <summary><b>R230</b> - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 power rail to provide pull-up for the open-drain power good signal. | | 2 | 2 | VGFX_PG | ✅ | Connected to VGFX_PG signal to pull up the open-drain VR_RDY output from U26. | </details> <details> <summary><b>C60</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG signal to provide filtering for the power good signal. | | 2 | 2 | GND | ✅ | Connected to GND to complete the filtering path. | </details> <details> <summary><b>C434</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to net $24N6011 to provide filtering/decoupling for the EN pin of U26. | | 2 | 2 | GND | ✅ | Connected to GND to complete the decoupling path. | </details> <details> <summary><b>C76</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal correctly connected to +VGFX output rail. This provides bulk output capacitance for the DC/DC GFX regulator. | | 2 | N | GND | ✅ | Negative terminal correctly connected to GND. Proper polarity for tantalum capacitor operation. | </details> <details> <summary><b>C77</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal correctly connected to +VGFX output rail. This provides bulk output capacitance in parallel with C76 for the DC/DC GFX regulator. | | 2 | N | GND | ✅ | Negative terminal correctly connected to GND. Proper polarity for tantalum capacitor operation. | </details> <details> <summary><b>U41</b> - RT8207 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.richtek.com/SaveDownload.aspx?specid=RT8207P) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/RT8207) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 22 | BOOT | $25N771 | ❌ | <details><summary>BOOT pin connected to bootstrap network with C309 (0.1µF) and series resistor R298 (4.7Ω). Bootstrap capacitor is 10x smaller than datasheet recommendation of 1µF, which may cause insufficient gate drive and reliability issues.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="45.80,38.02,53.30,45.52" aspect-ratio="1.29" } <ul><li>Pin 22 (BOOT) is connected to net $25N771 <em>(from schematic)</em></li><li>BOOT is the boost flying capacitor connection for VDDQ <em>(from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=2">RT8207</a>, page 2)</em></li><li>The instantaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins <em>(from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=15">RT8207</a>, page 15)</em></li><li>Datasheet typical application circuit shows 1µF bootstrap capacitor <em>(from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=3">RT8207</a>, page 3)</em></li><li>For high current applications, adding a resistor in series with BOOT can prevent shoot-through by increasing turn-on rising time <em>(from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=15">RT8207</a>, page 15)</em></li><li>The 4.7Ω series resistor R298 is appropriate for shoot-through prevention <em>(reasoning)</em></li><li>For typical MOSFET gate charge of 10-30nC, 0.1µF provides 50nC with 0.5V droop, giving margin of only 1.7-5x <em>(reasoning)</em></li><li>With recommended 1µF, margin increases to 17-50x, providing much better reliability <em>(reasoning)</em></li><li>The 10x reduction from recommended value could cause insufficient gate drive at high frequencies, temperature extremes, or with MOSFETs having higher gate charge <em>(reasoning)</em></li><li>Bootstrap capacitor C309 should be increased to 1µF per datasheet recommendation <em>(reasoning)</em></li></ul></details> | | 1 | VTTGND | GND | ✅ | VTTGND pin correctly connected to GND for VTT LDO power ground. | | 2 | VTTSNS | +VDIMM_VTT | ✅ | VTTSNS pin correctly connected to +VDIMM_VTT for remote voltage sensing of VTT output. | | 3 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 4 | MODE | GND | ✅ | MODE pin connected to GND for mode selection. | | 5 | VTTREF | $25N769 | ✅ | VTTREF pin correctly connected to C342 (0.22uF) for output decoupling. | | 6 | DEM | $25N1291 | ✅ | DEM pin connected to pull-up resistor R810 (10K to +5VSB) for diode emulation mode control. | | 8 | VDDQ | +VDIMM | ✅ | VDDQ pin correctly connected to +VDIMM output for reference and feedback. | | 9 | FB | $25N987 | ✅ | FB pin correctly connected to resistive divider (R814/R815) setting output to 1.35V for DDR3L. | | 10 | S3 | EN_VTT | ✅ | S3 pin correctly connected to EN_VTT signal for S3 state control. | | 11 | S5 | EN_VDDQ | ✅ | S5 pin correctly connected to EN_VDDQ signal for S5 state control. | | 12 | TON | $25N1081 | ✅ | TON pin connected to R816 (464K) setting switching frequency to approximately 503kHz. | | 13 | PGOOD | DRAM_PWROK | ✅ | PGOOD pin correctly connected to DRAM_PWROK with pull-up resistor for power good indication. | | 14 | VDD | $25N1195 | ✅ | VDD pin connected to +5VSB through R813 (2.2 ohm) with C380 (1uF) decoupling. Resistor value is smaller than datasheet recommendation of 5.1 ohm but should still function. | | 15 | VDDP | +5VSB | ✅ | VDDP pin correctly connected to +5VSB for gate driver supply. | | 16 | CS | $25N1238 | ✅ | CS pin correctly connected to R817 (3.83K) setting current limit to approximately 11A. | | 18 | PGND | GND | ✅ | PGND pin correctly connected to GND for low-side MOSFET power ground. | | 19 | LGATE | $25N901 | ✅ | LGATE pin correctly connected to Q102 pin 8 (low-side MOSFET gate). | | 20 | PHASE | DDR_PHASE | ✅ | PHASE pin correctly connected to switching node between MOSFETs and output inductor. | | 21 | UGATE | $25N897 | ✅ | UGATE pin correctly connected to Q102 pin 1 (high-side MOSFET gate). | | 23 | VLDOIN | +VDIMM | ✅ | VLDOIN pin correctly connected to +VDIMM output for VTT LDO power supply. | | 24 | VTT | +VDIMM_VTT | ✅ | VTT pin correctly connected to +VDIMM_VTT output. | | 25 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) correctly connected to GND for thermal dissipation. | </details> <details> <summary><b>R816</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | TON timing resistor correctly connected between +5VSB and U41 TON pin. Value is 464KΩ giving ~500kHz switching frequency, though schematic text note specifies 806KΩ for 285kHz operation. Circuit appears designed for actual 500kHz operation based on 1µH inductor selection. | | 2 | 2 | $25N1081 | ✅ | TON timing resistor correctly connected between +5VSB and U41 TON pin. Value is 464KΩ giving ~500kHz switching frequency, though schematic text note specifies 806KΩ for 285kHz operation. Circuit appears designed for actual 500kHz operation based on 1µH inductor selection. | </details> <details> <summary><b>R813</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>C380</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>C379</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>R817</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>R814</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>R815</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>C382</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>C342</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| </details> <details> <summary><b>C309</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | C309 is a 0.1uF bootstrap capacitor correctly connected between the DDR_BST node and the DDR_PHASE switching node, though with series resistor R298 in the path from the BOOT pin. | | 2 | 2 | DDR_BST | ✅ | C309 is a 0.1uF bootstrap capacitor correctly connected between the DDR_BST node and the DDR_PHASE switching node, though with series resistor R298 in the path from the BOOT pin. | </details> <details> <summary><b>Q102</b> - FDMS3604S ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pub/Collateral/FDMS3604S-D.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/FDMS3604S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Q1G | $25N897 | ✅ | Q1G (Gate of control MOSFET Q1) is correctly connected to the UGATE output of the RT8207 controller U41 via net $25N897. | | 2 | VIN_A | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (Drain pins of control MOSFET Q1) are correctly connected to the DDR3L_VIN input supply with appropriate bypass capacitors. | | 3 | VIN_B | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (Drain pins of control MOSFET Q1) are correctly connected to the DDR3L_VIN input supply with appropriate bypass capacitors. | | 4 | VIN_C | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (Drain pins of control MOSFET Q1) are correctly connected to the DDR3L_VIN input supply with appropriate bypass capacitors. | | 5 | PGND_A | GND | ✅ | PGND_A, PGND_B, PGND_C (Source pins of synchronous MOSFET Q2) are correctly connected to ground. | | 6 | PGND_B | GND | ✅ | PGND_A, PGND_B, PGND_C (Source pins of synchronous MOSFET Q2) are correctly connected to ground. | | 7 | PGND_C | GND | ✅ | PGND_A, PGND_B, PGND_C (Source pins of synchronous MOSFET Q2) are correctly connected to ground. | | 8 | Q2G | $25N901 | ✅ | Q2G (Gate of synchronous MOSFET Q2) is correctly connected to the LGATE output of the RT8207 controller U41 via net $25N901. | | 9 | PHASE | DDR_PHASE | ✅ | PHASE (internally connected switch node) is correctly connected to the output inductor L11, controller feedback pin, and bootstrap capacitor C309. | </details> <details> <summary><b>R298</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N771 | ✅ | R298 is a 4.7 ohm resistor connected in series with the bootstrap capacitor C309 between the RT8207 BOOT pin and the PHASE node. This configuration is unusual but may be intentional for damping or current limiting purposes. | | 2 | 2 | DDR_BST | ✅ | R298 is a 4.7 ohm resistor connected in series with the bootstrap capacitor C309 between the RT8207 BOOT pin and the PHASE node. This configuration is unusual but may be intentional for damping or current limiting purposes. | </details> <details> <summary><b>L11</b> - 125-0004454 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0004454) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | Pin 1 connects to the DDR_PHASE switching node, which is the output of the buck converter MOSFETs. This is the correct connection for the input side of a buck converter output inductor. | | 2 | 2 | +VDIMM | ✅ | Pin 2 connects to the +VDIMM output rail. This is the correct connection for the output side of a buck converter output inductor. | </details> <details> <summary><b>C328</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin providing return path for input filtering capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter. | </details> <details> <summary><b>L5</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input pin connected to +5VSB supply rail. This provides the unfiltered input to the ferrite bead. | | 2 | 2 | DDR3L_VIN | ✅ | Output pin connected to DDR3L_VIN rail. This provides filtered power to the buck converter input stage. | </details> <details> <summary><b>C128</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin providing return path for input filtering capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter. | </details> <details> <summary><b>C126</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin providing return path for input filtering capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter. | </details> <details> <summary><b>L6</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input pin connected to +5VSB supply rail. This provides the unfiltered input to the ferrite bead, in parallel with L5. | | 2 | 2 | DDR3L_VIN | ✅ | Output pin connected to DDR3L_VIN rail. This provides filtered power to the buck converter input stage, in parallel with L5. | </details> <details> <summary><b>C127</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin providing return path for input filtering capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Positive pin connected to DDR3L_VIN rail, providing bulk input capacitance for the buck converter. | </details> <details> <summary><b>C327</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin providing return path for high-frequency decoupling capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Positive pin connected to DDR3L_VIN rail, providing high-frequency decoupling for the buck converter input. | </details> <details> <summary><b>C129</b> - 123-0005035 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VDIMM | ❌ | <details><summary>330uF tantalum capacitor connected between +VDIMM (1.35V) and GND for bulk output filtering. The 2V voltage rating provides 48% margin above the 1.35V nominal output, resulting in 67.5% voltage utilization which exceeds the standard 50% derating guideline typically recommended for tantalum capacitors.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="79.88,43.31,87.38,50.81" aspect-ratio="1.29" } <ul><li>Pin 1 (P) is connected to +VDIMM net <em>(from schematic)</em></li><li>Pin 2 (N) is connected to GND net <em>(from schematic)</em></li><li>C129 is a 330uF tantalum capacitor with 2V voltage rating in C7343 package <em>(from schematic)</em></li><li>The +VDIMM output voltage is 1.35V according to the text note on the schematic <em>(from schematic)</em></li><li>The polarity is correct with positive terminal connected to the positive rail and negative terminal to ground <em>(reasoning)</em></li><li>The voltage margin is 2V / 1.35V = 1.48x or 48% above nominal, resulting in 67.5% voltage utilization <em>(reasoning)</em></li><li>Industry standard practice for tantalum capacitors recommends 50% voltage derating for reliability, meaning a 2V capacitor should ideally be used at maximum 1V continuous operation <em>(reasoning)</em></li><li>Operating at 67.5% of rated voltage exceeds the conservative 50% derating guideline by 35% <em>(reasoning)</em></li><li>While some modern tantalum capacitors may be qualified for operation above 50% of rated voltage, this should be verified against the specific part number datasheet <em>(reasoning)</em></li><li>For conservative design following standard derating practices at 1.35V, a tantalum capacitor should be rated for at least 2.7V, preferably 4V or higher <em>(reasoning)</em></li><li>The marginal voltage rating may impact long-term reliability, particularly under voltage transients or elevated temperature conditions <em>(reasoning)</em></li><li>Recommendation: Verify that part number 123-0005035 datasheet explicitly allows operation at 67.5% of rated voltage, or consider replacing with a capacitor rated for at least 4V to provide adequate margin <em>(reasoning)</em></li></ul></details> | | 2 | N | GND | ❌ | <details><summary>330uF tantalum capacitor connected between +VDIMM (1.35V) and GND for bulk output filtering. The 2V voltage rating provides 48% margin above the 1.35V nominal output, resulting in 67.5% voltage utilization which exceeds the standard 50% derating guideline typically recommended for tantalum capacitors.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="79.88,43.90,87.38,51.40" aspect-ratio="1.29" } <ul><li>Pin 1 (P) is connected to +VDIMM net <em>(from schematic)</em></li><li>Pin 2 (N) is connected to GND net <em>(from schematic)</em></li><li>C129 is a 330uF tantalum capacitor with 2V voltage rating in C7343 package <em>(from schematic)</em></li><li>The +VDIMM output voltage is 1.35V according to the text note on the schematic <em>(from schematic)</em></li><li>The polarity is correct with positive terminal connected to the positive rail and negative terminal to ground <em>(reasoning)</em></li><li>The voltage margin is 2V / 1.35V = 1.48x or 48% above nominal, resulting in 67.5% voltage utilization <em>(reasoning)</em></li><li>Industry standard practice for tantalum capacitors recommends 50% voltage derating for reliability, meaning a 2V capacitor should ideally be used at maximum 1V continuous operation <em>(reasoning)</em></li><li>Operating at 67.5% of rated voltage exceeds the conservative 50% derating guideline by 35% <em>(reasoning)</em></li><li>While some modern tantalum capacitors may be qualified for operation above 50% of rated voltage, this should be verified against the specific part number datasheet <em>(reasoning)</em></li><li>For conservative design following standard derating practices at 1.35V, a tantalum capacitor should be rated for at least 2.7V, preferably 4V or higher <em>(reasoning)</em></li><li>The marginal voltage rating may impact long-term reliability, particularly under voltage transients or elevated temperature conditions <em>(reasoning)</em></li><li>Recommendation: Verify that part number 123-0005035 datasheet explicitly allows operation at 67.5% of rated voltage, or consider replacing with a capacitor rated for at least 4V to provide adequate margin <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>C136</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin. | | 2 | 2 | +VDIMM | ✅ | High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin. | </details> <details> <summary><b>C137</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating. | | 2 | 2 | +VDIMM | ✅ | Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating. | </details> <details> <summary><b>C138</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin. | | 2 | 2 | +VDIMM | ✅ | High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin. | </details> <details> <summary><b>C139</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin. | | 2 | 2 | +VDIMM | ✅ | High-frequency decoupling capacitor for +VDIMM output, correctly connected between GND and +VDIMM with excellent voltage margin. | </details> <details> <summary><b>C140</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating. | | 2 | 2 | +VDIMM | ✅ | Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating. | </details> <details> <summary><b>C141</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating. | | 2 | 2 | +VDIMM | ✅ | Bulk output capacitor for +VDIMM rail, correctly connected between GND and +VDIMM with adequate voltage rating. | </details> <details> <summary><b>C359</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Medium-value output capacitor for +VDIMM rail, correctly connected between +VDIMM and GND with adequate voltage rating. | | 2 | 2 | GND | ✅ | Medium-value output capacitor for +VDIMM rail, correctly connected between +VDIMM and GND with adequate voltage rating. | </details> <details> <summary><b>C343</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This pin provides the ground terminal of the high-frequency decoupling capacitor. | | 2 | 2 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT power rail. This pin provides high-frequency decoupling for the VTT regulator output. | </details> <details> <summary><b>C362</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT power rail. This pin provides the positive terminal of the second bulk output capacitor for the VTT regulator. | | 2 | 2 | GND | ✅ | Connected to GND. This pin provides the ground return path for the second bulk output capacitor. | </details> <details> <summary><b>C361</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT power rail. This pin provides the positive terminal of the bulk output capacitor for the VTT regulator. | | 2 | 2 | GND | ✅ | Connected to GND. This pin provides the ground return path for the bulk output capacitor. | </details> <details> <summary><b>R24</b> - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Upper feedback resistor connected between output voltage +V1P8S and feedback pin. | | 2 | 2 | +V1P8S_FB | ✅ | Connected to feedback network at +V1P8S_FB node. | </details> <details> <summary><b>R25</b> - 110-0004490 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004490) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor connected to ground. | | 2 | 2 | +V1P8S_FB | ✅ | Connected to feedback network at +V1P8S_FB node. | </details> <details> <summary><b>R22</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V_EN | ✅ | 0-ohm jumper connecting enable control circuit to LDO enable pin. | | 2 | 2 | +V1P8S_EN | ✅ | Connected to U21 enable pin through +V1P8S_EN net. | </details> <details> <summary><b>R23</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor for power good signal, connected to output voltage. | | 2 | 2 | +V1P8S_PGD | ✅ | Connected to power good signal from U21. | </details> <details> <summary><b>C9</b> - 123-0001079 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001079) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S_FB | ✅ | 150pF capacitor marked DNI (Do Not Install) across feedback network. Since it is not installed, it does not affect the circuit operation. | | 2 | 2 | +V1P8S | ✅ | 150pF capacitor marked DNI (Do Not Install) across feedback network. Since it is not installed, it does not affect the circuit operation. | </details> <details> <summary><b>U21</b> - 140-0004526 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P8S_PGD | ✅ | PGOOD pin connected to +V1P8S_PGD net with 4.7K pull-up resistor R23 to output voltage +V1P8S. This is a typical open-drain power good output configuration. | | 2 | EN | +V1P8S_EN | ✅ | EN pin connected to +V1P8S_EN net through 0-ohm resistor R22, which connects to enable control circuit with Q3 and pull-up R125. Text note indicates enable threshold > 1.1V. | | 3 | VIN | +PS_3VSB | ✅ | VIN pin connected to +PS_3VSB (3.3V standby supply) with input decoupling capacitors C6 (10uF) and C3 (0.1uF) nearby. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin connected to +PS_3VSB, same as VIN. This is typical for LDOs where VDD powers the control circuitry. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as specified. | | 6 | VOUT | +V1P8S | ✅ | VOUT pin connected to +V1P8S with output capacitors C8 (10uF), C4 (0.1uF), and C7 (22uF) providing total 32.1uF output capacitance. Text note indicates 1.14A expected load current. | | 7 | ADJ | +V1P8S_FB | ✅ | ADJ pin connected to feedback divider network with R24 (12.1K) to output and R25 (9.53K) to ground. Calculated output voltage is 1.816V using formula Vout=0.8(1+R1/R2), which is within tolerance of target 1.8V. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins both correctly connected to ground plane. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins both correctly connected to ground plane. | </details> <details> <summary><b>R150</b> - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R150 (12.1K ohm) forms the upper resistor (R1) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to set the output voltage to 1.8V. | | 2 | 2 | +V1P8A | ✅ | R150 (12.1K ohm) forms the upper resistor (R1) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to set the output voltage to 1.8V. | </details> <details> <summary><b>R153</b> - 110-0002726 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002726) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R153 (27.4K ohm) forms the lower resistor (R2) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and GND (pin 2) to set the output voltage to 1.8V. | | 2 | 2 | GND | ✅ | R153 (27.4K ohm) forms the lower resistor (R2) in the feedback divider network for U20, correctly connected between +V1P8A_FB (pin 1) and GND (pin 2) to set the output voltage to 1.8V. | </details> <details> <summary><b>C152</b> - 123-0001102 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001102) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | C152 (22pF) is a compensation capacitor correctly connected in parallel with R150 between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to improve feedback loop stability and transient response. | | 2 | 2 | +V1P8A | ✅ | C152 (22pF) is a compensation capacitor correctly connected in parallel with R150 between +V1P8A_FB (pin 1) and +V1P8A (pin 2) to improve feedback loop stability and transient response. | </details> <details> <summary><b>R151</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | R151 (0 ohm jumper) correctly implements power sequencing by connecting +V1P0A_PWRGD (pin 1) to +V1P8A_EN (pin 2), ensuring the 1.0V rail is stable before enabling the 1.8V rail. | | 2 | 2 | +V1P8A_EN | ✅ | R151 (0 ohm jumper) correctly implements power sequencing by connecting +V1P0A_PWRGD (pin 1) to +V1P8A_EN (pin 2), ensuring the 1.0V rail is stable before enabling the 1.8V rail. | </details> <details> <summary><b>U20</b> - NCP606 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncp605-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004677) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN1 | +PS_3VSB | ✅ | VIN1 is correctly connected to +PS_3VSB (3.3V standby supply) with adequate input decoupling capacitors. | | 2 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 3 | EN | +V1P8A_EN | ✅ | EN (enable) is correctly connected to +V1P8A_EN, which is derived from +V1P0A_PWRGD through 0-ohm resistor R151, implementing proper power sequencing. | | 4 | VOUT | +V1P8A | ✅ | VOUT is correctly connected to +V1P8A output net with proper output decoupling capacitor C151 (10uF). | | 5 | SENSE/ADJ | +V1P8A_FB | ✅ | SENSE/ADJ is correctly connected to feedback divider network (R150=12.1K, R153=27.4K) to set output voltage to approximately 1.8V. | | 6 | VIN2 | +PS_3VSB | ✅ | VIN2 is correctly connected to +PS_3VSB, same as VIN1, as required by the datasheet for full output current range operation. | | 7 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) is correctly connected to ground for thermal dissipation. | </details> <details> <summary><b>R306</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | 0 ohm jumper connecting VCORE_GFX_PG to 1P0V_EN (U38 enable), implementing power sequencing. | | 2 | 2 | 1P0V_EN | ✅ | 0 ohm jumper connecting VCORE_GFX_PG to 1P0V_EN (U38 enable), implementing power sequencing. | </details> <details> <summary><b>R136</b> - 110-0002029 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002029) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FB_V1P0S | ✅ | Upper feedback resistor (40.2K) in voltage divider for U38, connected between FB_V1P0S and +V1P0S. Sets output voltage to 1.025V with R135. | | 2 | 2 | +V1P0S | ✅ | Upper feedback resistor (40.2K) in voltage divider for U38, connected between FB_V1P0S and +V1P0S. Sets output voltage to 1.025V with R135. | </details> <details> <summary><b>C119</b> - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FB_V1P0S | ✅ | 27pF compensation capacitor in parallel with R136 in U38 feedback network, providing phase compensation with corner frequency around 147 kHz. | | 2 | 2 | +V1P0S | ✅ | 27pF compensation capacitor in parallel with R136 in U38 feedback network, providing phase compensation with corner frequency around 147 kHz. | </details> <details> <summary><b>R320</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCNTL_V1P0S | ✅ | 10 ohm resistor connecting +VCC to VCNTL_V1P0S, forming RC filter with C117 (1uF) for U38 VCNTL pin. Without datasheet, cannot verify if this configuration is correct. | | 2 | 2 | +VCC | ✅ | 10 ohm resistor connecting +VCC to VCNTL_V1P0S, forming RC filter with C117 (1uF) for U38 VCNTL pin. Without datasheet, cannot verify if this configuration is correct. | </details> <details> <summary><b>R319</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | 10K pull-up resistor for U38 power good output (V1P0S_PG) to +VCC. | | 2 | 2 | +VCC | ✅ | 10K pull-up resistor for U38 power good output (V1P0S_PG) to +VCC. | </details> <details> <summary><b>R135</b> - 110-0004498 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004498) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor (143K) in voltage divider for U38, connected between GND and FB_V1P0S. Sets output voltage to 1.025V with R136. | | 2 | 2 | FB_V1P0S | ✅ | Lower feedback resistor (143K) in voltage divider for U38, connected between GND and FB_V1P0S. Sets output voltage to 1.025V with R136. | </details> <details> <summary><b>U38</b> - APL5912KAC-TRGS-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004525) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 2 | FB | FB_V1P0S | ✅ | Feedback pin connected to resistive divider network (R136, R135) with compensation capacitor C119. Output voltage calculated to be 1.025V based on 0.8V reference and divider ratio. | | 3 | VOUT-2 | +V1P0S | ✅ | Output pins correctly connected to +V1P0S rail. Multiple output pins are common in high-current LDOs for current distribution. | | 4 | VOUT-1 | +V1P0S | ✅ | Output pins correctly connected to +V1P0S rail. Multiple output pins are common in high-current LDOs for current distribution. | | 5 | VIN-2 | +VDIMM | ✅ | Input pins correctly connected to +VDIMM rail. Multiple input pins are common in high-current LDOs. | | 9 | VIN-1 | +VDIMM | ✅ | Input pins correctly connected to +VDIMM rail. Multiple input pins are common in high-current LDOs. | | 6 | VCNTL | VCNTL_V1P0S | ✅ | VCNTL pin connected through 10 ohm resistor (R320) to +VCC with 1uF capacitor (C117) to ground, forming an RC filter. Without datasheet, cannot verify if this control voltage configuration is correct. | | 7 | POK | V1P0S_PG | ✅ | Power good output pin correctly connected with 10K pull-up resistor (R319) to +VCC and used to enable downstream regulator (1P35V_EN through R134). | | 8 | EN | 1P0V_EN | ✅ | Enable pin connected through 0 ohm resistor (R306) to VCORE_GFX_PG, implementing power sequencing. Text note indicates enable threshold is >0.5V. | </details> <details> <summary><b>R34</b> - 110-0003781 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0003781) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Upper feedback resistor correctly connected between output voltage (+V1P0A) and feedback node (+V1P0A_FB) to set the 1.0V output voltage. | | 2 | 2 | +V1P0A | ✅ | Upper feedback resistor correctly connected between output voltage (+V1P0A) and feedback node (+V1P0A_FB) to set the 1.0V output voltage. | </details> <details> <summary><b>R35</b> - 110-0004494 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004494) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Lower feedback resistor correctly connected between feedback node (+V1P0A_FB) and ground to set the 1.0V output voltage. | | 2 | 2 | GND | ✅ | Lower feedback resistor correctly connected between feedback node (+V1P0A_FB) and ground to set the 1.0V output voltage. | </details> <details> <summary><b>R32</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Enable pull-up resistor correctly connected between +5VSB and the enable pin of U24 to enable the LDO when standby power is present. | | 2 | 2 | +V1P0A_ENABLE | ✅ | Enable pull-up resistor correctly connected between +5VSB and the enable pin of U24 to enable the LDO when standby power is present. | </details> <details> <summary><b>R33</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | Power good pull-up resistor correctly connected between +PS_3VSB and the open-drain PGOOD output of U24 to provide a logic high level when the output is in regulation. | | 2 | 2 | +V1P0A_PWRGD | ✅ | Power good pull-up resistor correctly connected between +PS_3VSB and the open-drain PGOOD output of U24 to provide a logic high level when the output is in regulation. | </details> <details> <summary><b>C23</b> - 123-0001079 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001079) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Compensation capacitor marked DNI (Do Not Install), intentionally not installed across the upper feedback resistor R34, indicating the LDO regulator is stable without additional phase compensation. | | 2 | 2 | +V1P0A | ✅ | Compensation capacitor marked DNI (Do Not Install), intentionally not installed across the upper feedback resistor R34, indicating the LDO regulator is stable without additional phase compensation. | </details> <details> <summary><b>R31</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Enable pull-down resistor marked DNI (Do Not Install), intentionally not installed on the enable pin, indicating that pull-up through R32 alone is sufficient for enable control. | | 2 | 2 | +V1P0A_ENABLE | ✅ | Enable pull-down resistor marked DNI (Do Not Install), intentionally not installed on the enable pin, indicating that pull-up through R32 alone is sufficient for enable control. | </details> <details> <summary><b>U24</b> - APL5933 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P0A_PWRGD | ✅ | PGOOD output is correctly configured as open-drain with pull-up to +PS_3VSB through R33, and connected to power sequencing logic through D11 to enable downstream regulator U20. | | 2 | EN | +V1P0A_ENABLE | ✅ | EN input is correctly pulled up to +5VSB through R32 (4.7K), with optional pull-down R31 marked DNI, and decoupled by C20 (0.1uF). | | 3 | VIN | +PS_3VSB | ✅ | VIN and VDD inputs are both correctly connected to +PS_3VSB supply rail with adequate input decoupling capacitors. | | 4 | VDD | +PS_3VSB | ✅ | VIN and VDD inputs are both correctly connected to +PS_3VSB supply rail with adequate input decoupling capacitors. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as specified. | | 6 | VOUT | +V1P0A | ✅ | VOUT is correctly connected to +V1P0A output rail with appropriate output capacitors C21 (22uF) and C22 (0.1uF) for stability and filtering. | | 7 | ADJ | +V1P0A_FB | ✅ | ADJ feedback pin is correctly connected to resistor divider network (R34=6.04K, R35=23.7K) that sets output voltage to 1.004V, matching the intended 1.0V rail. | | 8 | GND1 | GND | ✅ | GND1 and GND2 (thermal pad) are both correctly connected to ground plane. | | 9 | GND2 | GND | ✅ | GND1 and GND2 (thermal pad) are both correctly connected to ground plane. | </details> <details> <summary><b>R134</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | 1K resistor correctly connected between V1P0S_PG and gate of Q5 (1P35V_EN) to provide gate drive current limiting. | | 2 | 2 | 1P35V_EN | ✅ | 1K resistor correctly connected between V1P0S_PG and gate of Q5 (1P35V_EN) to provide gate drive current limiting. | </details> <details> <summary><b>R120</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | 10K resistor correctly connected between +V1P35S and base of Q3A (1P35V_PWG) to provide base drive current for power sequencing logic. | | 2 | 2 | 1P35V_PWG | ✅ | 10K resistor correctly connected between +V1P35S and base of Q3A (1P35V_PWG) to provide base drive current for power sequencing logic. | </details> <details> <summary><b>R125</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | 4.7K pull-up resistor correctly connected between +VCC and 1P8V_EN to pull the enable signal high when Q3B is off. | | 2 | 2 | 1P8V_EN | ✅ | 4.7K pull-up resistor correctly connected between +VCC and 1P8V_EN to pull the enable signal high when Q3B is off. | </details> <details> <summary><b>R126</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | 4.7K pull-up resistor correctly connected between +5VSB and 1P5V_EN_B to pull the base of Q3B high when Q3A is off. | | 2 | 2 | 1P5V_EN_B | ✅ | 4.7K pull-up resistor correctly connected between +5VSB and 1P5V_EN_B to pull the base of Q3B high when Q3A is off. | </details> <details> <summary><b>Q5</b> - RXR035N03 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/132-0004421) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +VDIMM | ✅ | Drain is connected to +VDIMM input power rail, which is correct for a high-side switch configuration. | | G | GATE | 1P35V_EN | ✅ | Gate is driven by 1P35V_EN signal through R134 from V1P0S_PG power-good output. Gate voltage should be sufficient to turn on the MOSFET for high-side switching. | | S | SOURCE | +V1P35S | ✅ | Source is connected to +V1P35S output rail (1.35V nominal), which is correct for a high-side switch providing regulated output. | </details> <details> <summary><b>Q3</b> - MBT3904 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter E1 is correctly connected to GND for common-emitter NPN transistor configuration. | | 2 | B1 | 1P35V_PWG | ✅ | Base B1 is driven by 1P35V_PWG signal, which is pulled up to +V1P35S through R120 to control transistor 1. | | 3 | C2 | 1P8V_EN | ✅ | Collector C2 of transistor 2 is connected to 1P8V_EN, pulling it low when transistor 2 is on. | | 4 | E2 | GND | ✅ | Emitter E2 is correctly connected to GND for common-emitter NPN transistor configuration. | | 5 | B2 | 1P5V_EN_B | ✅ | Base B2 is driven by 1P5V_EN_B signal to control transistor 2 in the power sequencing logic. | | 6 | C1 | 1P5V_EN_B | ✅ | Collector C1 of transistor 1 is connected to 1P5V_EN_B, pulling it low when transistor 1 is on to implement inverter logic. | </details> <details> <summary><b>Q1</b> - 132-0004425 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter of first NPN transistor, correctly connected to ground. | | 2 | B1 | PSGOOD | ✅ | Base of first NPN transistor, correctly connected to PSGOOD signal for switching control. | | 3 | C2 | SYS_PWRGD | ✅ | Collector of second NPN transistor, correctly connected to SYS_PWRGD output signal. | | 4 | E2 | GND | ✅ | Emitter of second NPN transistor, correctly connected to ground. | | 5 | B2 | PSPUP | ✅ | Base of second NPN transistor, correctly connected to PSPUP for cascaded switching. | | 6 | C1 | PSPUP | ✅ | Collector of first NPN transistor, correctly connected to PSPUP to drive the second transistor stage. | </details> <details> <summary><b>D11</b> - 130-0004403 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | Cathode of first diode in common-anode dual Schottky, correctly connected to +V1P0A_PWRGD for AND gate function. | | 2 | 2 | SLP_S3_L | ✅ | Cathode of second diode in common-anode dual Schottky, correctly connected to SLP_S3_L for AND gate function. | | 3 | 3 | PSGOOD | ✅ | Common anode of dual Schottky diode, correctly connected to PSGOOD with pull-up and delay capacitor. | </details> <details> <summary><b>FB7</b> - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Pin 1 connects to +VCC3, the main 3.3V supply rail. This is the input side of the 0-ohm jumper. | | 2 | 2 | +VCC3S | ✅ | Pin 2 connects to +VCC3S, a dedicated 3.3V supply for the CPU. This is the output side of the 0-ohm jumper that isolates the CPU supply for monitoring or filtering. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **R151, R192, R216, R22, R306, R353, R354, R41, R42, R43, R46, R48, R51, R72, R73, R74, R809** (110-0001853): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853) - **R147** (110-0001859): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001859) - **R102, R112, R114, R116, R120, R189, R190, R191, R2, R209, R210, R211, R219, R220, R221, R260, R266, R267, R268, R28, R29, R30, R31, R319, R400, R71, R75, R84, R97** (110-0001875): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001875) - **R134, R208, R233, R234, R259, R401, R94** (110-0001923): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001923) - **R206** (110-0001951): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001951) - **R60, R61** (110-0001957): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001957) - **R179** (110-0001960): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001960) - **R11, R12, R269, R270** (110-0001967): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001967) - **R140, R327** (110-0001971): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001971) - **R115, R117, R171, R172, R177, R257, R44, R45, R47, R49, R52** (110-0001984): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001984) - **R819** (110-0002000): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002000) - **R136** (110-0002029): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002029) - **R125, R126, R144, R23, R310, R32, R325, R326, R33** (110-0002058): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002058) - **FB7, R152, R222, R265, R275, R818** (110-0002124): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002124) - **R150, R24** (110-0002560): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002560) - **R213, R38, R39** (110-0002631): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631) - **R153** (110-0002726): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002726) - **R240, R241, R242, R258** (110-0003059): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0003059) - **R34** (110-0003781): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0003781) - **R185, R77** (110-0004472): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004472) - **R255** (110-0004474): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004474) - **R217, R218, R239** (110-0004476): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004476) - **R212** (110-0004478): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004478) - **R25** (110-0004490): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004490) - **R35** (110-0004494): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004494) - **R135** (110-0004498): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004498) - **R40** (110-0004695): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0004695) - **R832, R833, R834, R835** (1120-0003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0003) - **R837, R838, R839** (1120-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0010) - **R820, R821, R822, R823, R824, R825, R826, R827, R828, R830, R831** (1120-0011): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0011) - **R836** (1120-0018): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0018) - **R320** (1120-0022): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0022) - **R801, R802, R803, R804, R805, R806, R807, R808** (1120-0119): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0119) - **R843, R844** (1120-0203): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0203) - **R848** (1120-0359): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1120-0359) - **R840, R841, R842** (1121-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1121-0001) - **R155, R156, R157, R173, R174, R180, R182** (1121-0011): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/1121-0011) - **C10, C11, C12, C13, C177, C178, C179, C180** (123-0001038): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001038) - **C124, C133, C191, C192, C205, C206, C207, C208, C329, C344, C65** (123-0001056): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001056) - **C374** (123-0001076): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001076) - **C23, C9** (123-0001079): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001079) - **C152** (123-0001102): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001102) - **C119** (123-0001107): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001107) - **C103, C164, C201, C224, C225, C91** (123-0001176): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) - **C148, C211** (123-0004408): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0004408) - **C110, C111, C134, C135, C145, C146, C318, C319, C363, C364, C369, C370** (123-0004765): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0004765) - **C76, C77, C87** (123-0005035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0005035) - **L3** (125-0004501): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/125-0004501) - **FB3** (126-0001423): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0001423) - **L11** (126-0004454): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0004454) - **FB4, FB5, L5, L6** (126-0004457): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/126-0004457) - **D11, D3** (130-0004403): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/130-0004403) - **U38** (140-0004525): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004525) - **U21, U24** (140-0004526): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004526) - **Y1** (145-0004789): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/145-0004789) - **X1, Y2** (145-0004792): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/145-0004792) - **P1** (158-0004513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/158-0004513) - **C429, C430, C431** (2220-0039): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2220-0039) - **C425** (2221-0017): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2221-0017) - **C428** (2222-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2222-0014) - **C426, C427** (2222-0016): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2222-0016) - **C159, C162, C28, C360, C419, C420, C421, C422, C423, C424** (2232-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2232-0012) - **C161** (2267-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/2267-0004) - **J5, J6, J7** (258-0002513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0002513) - **USB1** (258-0004503): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0004503) - **J1** (258-0004612): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0004612) - **J4** (258-0004869): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0004869) - **JP1** (258-0005019): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/258-0005019) - **FB12** (3044-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3044-0010) - **FB13** (3044-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3044-0012) - **L8** (3120-0183): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3120-0183) - **L18, L4** (3120-0266): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3120-0266) - **CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17** (3142-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3142-0014) - **J11** (3362-0042): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3362-0042) - **J8** (3430-0212): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3430-0212) - **BH1** (353-0003073): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/353-0003073) - **FL1** (3750-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3750-0010) - **SW1** (3770-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3770-0026) - **TH1, TH2, TH3, TH4** (3880-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3880-0004) - **U42** (4300-0071): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4300-0071) - **U19** (4327-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4327-0010) - **D10, D5** (4536-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4536-0009) - **D1, D2** (4560-0045): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4560-0045) - **D13** (4620-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/4620-0026) - **J10** (5177985-2): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/5177985-2) - **TP11, TP12** (999-0000002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000002) - **TP1, TP17, TP18, TP2** (999-0000003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000003) - **SP1, SP2, SP3, SP4** (999-0000005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/999-0000005) - **D4, D6** (BAT54A-S): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAT54A-S) - **D8** (BAT754C): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAT754C) - **Q2, Q9** (BAV99-7-F-S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BAV99-7-F-S-X) - **L1, L2** (BKP2125HS221-T): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/BKP2125HS221-T) - **U25, U26** (NCP81109GMNTXG): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NCP81109GMNTXG) - **U35** (NCT3012S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NCT3012S-X) - **U18** (NTB0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTB0104GU12) - **U4, U5, U6, U7** (NTS0102GT): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0102GT) - **U10, U14, U15, U16, U17** (NTS0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NTS0104GU12) - **P2** (SCHA5B0200): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/SCHA5B0200) - **U29** (TPD4USB30): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/TPD4USB30) </details> _{^{Note: DRCY uses AI. Please verify the outputs.}}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component CPU1, pins AK12, AK13: DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P, positive) is connected to DDI_RCOMP_N net, and pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅, negative) is connected to DDI_RCOMP_P net. These connections should be reversed.

• Pin AK12 is named DDI0_RCOMP_P (positive) in the datasheet (from datasheet 140-0004628)
• Pin AK13 is named DDI_RCOMP_N (negative) in the datasheet, shown with overline in schematic as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (from datasheet 140-0004628)
• Pin AK12 connects to net DDI_RCOMP_N in the schematic (from schematic)
• Pin AK13 connects to net DDI_RCOMP_P in the schematic (from schematic)
• Compensation resistor R217 (402 ohms) connects between DDI_RCOMP_N and DDI_RCOMP_P nets (from schematic)
• For differential compensation resistors, the positive pin should connect to the positive side and negative pin to the negative side (reasoning)
• The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning)
• The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning)
• The pins are swapped and should be corrected: AK12 should connect to DDI_RCOMP_P and AK13 should connect to DDI_RCOMP_N (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AK12, AK13`: DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P, positive) is connected to DDI_RCOMP_N net, and pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅, negative) is connected to DDI_RCOMP_P net. These connections should be reversed.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,39.05" aspect-ratio="1.29" } - Pin AK12 is named DDI0_RCOMP_P (positive) in the datasheet *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - Pin AK13 is named DDI_RCOMP_N (negative) in the datasheet, shown with overline in schematic as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5f47a223a6ef8e398e129ab6b1219f25d430a057/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - Pin AK12 connects to net DDI_RCOMP_N in the schematic *(from schematic)* - Pin AK13 connects to net DDI_RCOMP_P in the schematic *(from schematic)* - Compensation resistor R217 (402 ohms) connects between DDI_RCOMP_N and DDI_RCOMP_P nets *(from schematic)* - For differential compensation resistors, the positive pin should connect to the positive side and negative pin to the negative side *(reasoning)* - The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) *(reasoning)* - The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) *(reasoning)* - The pins are swapped and should be corrected: AK12 should connect to DDI_RCOMP_P and AK13 should connect to DDI_RCOMP_N *(reasoning)* _{Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/140-0004628)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component R38, pin 1: Pin 1 connects to CRT_DAT (VGA_DDCDATA from CPU1 pin BC2), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation.

• Pin 1 is connected to net CRT_DAT (from schematic)
• Net CRT_DAT connects to CPU1 pin BC2, which is labeled VGA_DDCDATA (from schematic)
• Pin 2 connects to GND, creating a 150Ω pull-down configuration (from schematic)
• VGA_DDCDATA is the I2C SDA (data) line for the VGA Display Data Channel (DDC) interface (reasoning)
• DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground (reasoning)
• Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements (reasoning)
• A 150Ω pull-down resistor would pull the DDC data line low and prevent proper I2C communication by fighting against the required pull-up (reasoning)
• This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional (reasoning)
• The same issue affects R39 on the CRT_CLK line, indicating a systematic problem with the VGA DDC interface design (reasoning)

_{Upload a datasheet: 📤 R38}

[🚨 Error] **Component `R38`, pin `1`: Pin 1 connects to CRT_DAT (VGA_DDCDATA from CPU1 pin BC2), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,40.96,76.02,48.46" aspect-ratio="1.29" } - Pin 1 is connected to net CRT_DAT *(from schematic)* - Net CRT_DAT connects to CPU1 pin BC2, which is labeled VGA_DDCDATA *(from schematic)* - Pin 2 connects to GND, creating a 150Ω pull-down configuration *(from schematic)* - VGA_DDCDATA is the I2C SDA (data) line for the VGA Display Data Channel (DDC) interface *(reasoning)* - DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground *(reasoning)* - Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements *(reasoning)* - A 150Ω pull-down resistor would pull the DDC data line low and prevent proper I2C communication by fighting against the required pull-up *(reasoning)* - This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional *(reasoning)* - The same issue affects R39 on the CRT_CLK line, indicating a systematic problem with the VGA DDC interface design *(reasoning)* _{Upload a datasheet: [📤 R38](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component R38, pin 2: Connected to GND, creating a 150 ohm pull-down on the VGA DDC data line. This is incorrect for I2C/DDC operation which requires pull-up resistors.

• Pin 2 is connected to GND (from schematic)
• This creates a 150 ohm pull-down resistor on the VGA_DDCDATA signal (reasoning)
• I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors (reasoning)
• A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication (reasoning)
• This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled (reasoning)

_{Upload a datasheet: 📤 R38}

[🚨 Error] **Component `R38`, pin `2`: Connected to GND, creating a 150 ohm pull-down on the VGA DDC data line. This is incorrect for I2C/DDC operation which requires pull-up resistors.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,40.96,76.93,48.46" aspect-ratio="1.29" } - Pin 2 is connected to GND *(from schematic)* - This creates a 150 ohm pull-down resistor on the VGA_DDCDATA signal *(reasoning)* - I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors *(reasoning)* - A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication *(reasoning)* - This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled *(reasoning)* _{Upload a datasheet: [📤 R38](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component R39, pin 1: Pin 1 connects to CRT_CLK (VGA_DDCCLK from CPU1 pin BC1), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation.

• Pin 1 is connected to net CRT_CLK (from schematic)
• Net CRT_CLK connects to CPU1 pin BC1, which is labeled VGA_DDCCLK (from schematic)
• Pin 2 connects to GND, creating a 150Ω pull-down configuration (from schematic)
• VGA_DDCCLK is the I2C SCL (clock) line for the VGA Display Data Channel (DDC) interface (reasoning)
• DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground (reasoning)
• Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements (reasoning)
• A 150Ω pull-down resistor would pull the DDC clock line low and prevent proper I2C communication by fighting against the required pull-up (reasoning)
• This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional (reasoning)
• The same issue affects R38 on the CRT_DAT line, indicating a systematic problem with the VGA DDC interface design (reasoning)

_{Upload a datasheet: 📤 R39}

[🚨 Error] **Component `R39`, pin `1`: Pin 1 connects to CRT_CLK (VGA_DDCCLK from CPU1 pin BC1), forming a 150Ω pull-down resistor to ground. This configuration is incorrect for DDC/I2C interfaces, which require pull-up resistors for proper operation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,39.19,76.02,46.69" aspect-ratio="1.29" } - Pin 1 is connected to net CRT_CLK *(from schematic)* - Net CRT_CLK connects to CPU1 pin BC1, which is labeled VGA_DDCCLK *(from schematic)* - Pin 2 connects to GND, creating a 150Ω pull-down configuration *(from schematic)* - VGA_DDCCLK is the I2C SCL (clock) line for the VGA Display Data Channel (DDC) interface *(reasoning)* - DDC/I2C interfaces require pull-up resistors to VCC for proper open-drain operation, not pull-down resistors to ground *(reasoning)* - Standard DDC pull-up resistor values are typically 2.2kΩ to 10kΩ, depending on bus capacitance and speed requirements *(reasoning)* - A 150Ω pull-down resistor would pull the DDC clock line low and prevent proper I2C communication by fighting against the required pull-up *(reasoning)* - This resistor should be reconfigured as a pull-up resistor (2.2kΩ to 10kΩ) connected to an appropriate voltage rail if the VGA DDC interface is intended to be functional *(reasoning)* - The same issue affects R38 on the CRT_DAT line, indicating a systematic problem with the VGA DDC interface design *(reasoning)* _{Upload a datasheet: [📤 R39](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component R39, pin 2: Connected to GND, creating a 150 ohm pull-down on the VGA DDC clock line. This is incorrect for I2C/DDC operation which requires pull-up resistors.

• Pin 2 is connected to GND (from schematic)
• This creates a 150 ohm pull-down resistor on the VGA_DDCCLK signal (reasoning)
• I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors (reasoning)
• A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication (reasoning)
• This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled (reasoning)

_{Upload a datasheet: 📤 R39}

[🚨 Error] **Component `R39`, pin `2`: Connected to GND, creating a 150 ohm pull-down on the VGA DDC clock line. This is incorrect for I2C/DDC operation which requires pull-up resistors.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,39.19,76.93,46.69" aspect-ratio="1.29" } - Pin 2 is connected to GND *(from schematic)* - This creates a 150 ohm pull-down resistor on the VGA_DDCCLK signal *(reasoning)* - I2C/DDC interfaces require pull-up resistors (typically 4.7k-10k ohms to VCC), not pull-down resistors *(reasoning)* - A 150 ohm pull-down would draw excessive current (approximately 22mA at 3.3V) and prevent proper I2C communication *(reasoning)* - This resistor should either be reconfigured as a pull-up to an appropriate voltage rail, removed if external pull-ups exist, or changed to a much higher value (10k+) if the interface is intentionally disabled *(reasoning)* _{Upload a datasheet: [📤 R39](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0002631)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component C49, pins 1, 2: 10pF filter capacitor on PMC_RSMRST signal. The capacitance value is insufficient to meet the >10μs RC delay requirement noted on the schematic. Should be increased to approximately 1nF to achieve the required delay with the existing 10K pull-up resistor.

• Pin 1 connects to PMC_RSMRST net (from schematic)
• Pin 2 connects to GND net (from schematic)
• C49 is a 10pF capacitor rated for 50V (from schematic)
• C49 is located at coordinates (459.74, 279.4) (from schematic)
• A text note 'RC delay >10us' is present at coordinates (401.32, 287.02), spatially near C49 and its associated resistors (from schematic)
• The RC time constant with R83 (10K pull-up) is τ = 10,000 × 10×10^-12 = 100ns = 0.1μs (reasoning)
• The RC time constant with R82 (100K pull-down) is τ = 100,000 × 10×10^-12 = 1μs (reasoning)
• Neither time constant meets the >10μs requirement stated in the schematic note (reasoning)
• To achieve a 10μs RC delay with the existing 10K pull-up resistor, C49 should be increased from 10pF to approximately 1nF (1000pF) (reasoning)
• Alternatively, to achieve 10μs delay with the existing 10pF capacitor, R83 would need to be increased to 1MΩ, but this would be impractical for a pull-up resistor (reasoning)
• The 10pF value is typical for high-frequency noise filtering but inadequate for creating the required delay (reasoning)

[🚨 Error] **Component `C49`, pins `1, 2`: 10pF filter capacitor on PMC_RSMRST signal. The capacitance value is insufficient to meet the >10μs RC delay requirement noted on the schematic. Should be increased to approximately 1nF to achieve the required delay with the existing 10K pull-up resistor.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="c66f35d31fb1590e57a5" diff-visibility="full" variant="default" view-coords="78.97,30.96,86.92,38.46" aspect-ratio="1.29" } - Pin 1 connects to PMC_RSMRST net *(from schematic)* - Pin 2 connects to GND net *(from schematic)* - C49 is a 10pF capacitor rated for 50V *(from schematic)* - C49 is located at coordinates (459.74, 279.4) *(from schematic)* - A text note &#x27;RC delay &gt;10us&#x27; is present at coordinates (401.32, 287.02), spatially near C49 and its associated resistors *(from schematic)* - The RC time constant with R83 (10K pull-up) is τ = 10,000 × 10×10^-12 = 100ns = 0.1μs *(reasoning)* - The RC time constant with R82 (100K pull-down) is τ = 100,000 × 10×10^-12 = 1μs *(reasoning)* - Neither time constant meets the &gt;10μs requirement stated in the schematic note *(reasoning)* - To achieve a 10μs RC delay with the existing 10K pull-up resistor, C49 should be increased from 10pF to approximately 1nF (1000pF) *(reasoning)* - Alternatively, to achieve 10μs delay with the existing 10pF capacitor, R83 would need to be increased to 1MΩ, but this would be impractical for a pull-up resistor *(reasoning)* - The 10pF value is typical for high-frequency noise filtering but inadequate for creating the required delay *(reasoning)*

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component R809, pins 1, 2: R809 is a 0Ω resistor connecting Q101 gate to +VCC3 power rail via auto-generated net $15N747. The auto-generated net name and empty PLACE attribute indicate this connection scheme is likely an error. The gate should typically be driven by a control signal to enable/disable the HDMI termination network as needed, rather than being permanently tied to power.

• Pin 1 is connected to net $15N747, which also connects to Q101 gate pin G (from schematic)
• Pin 2 is connected to net +VCC3 (from schematic)
• R809 has a value of 0Ω, effectively creating a direct connection between Q101 gate and +VCC3 (from schematic)
• The net name $15N747 starts with '$', which in most EDA tools indicates an auto-generated net name created when there is a floating connection or missing net label (reasoning)
• R809 has an empty PLACE attribute, suggesting uncertainty about whether this component should be placed or indicating the design is incomplete (from schematic)
• With the gate tied directly to +VCC3, Q101 will be permanently enabled whenever +VCC3 is present, making the termination network always active with no independent control (reasoning)
• The circuit includes other control signals (LS_OE, HPD_ENB) for the HDMI interface, suggesting that controllable termination would be more consistent with the overall design intent (from schematic)
• If permanent enable was the design intent, the gate could be directly connected to +VCC3 without requiring a separate 0Ω resistor and auto-generated net (reasoning)
• The combination of auto-generated net name, empty PLACE attribute, and unusual connection scheme indicates this is likely an incomplete or incorrect connection rather than intentional design (reasoning)

_{Upload a datasheet: 📤 R809}

[🚨 Error] **Component `R809`, pins `1, 2`: R809 is a 0Ω resistor connecting Q101 gate to +VCC3 power rail via auto-generated net $15N747. The auto-generated net name and empty PLACE attribute indicate this connection scheme is likely an error. The gate should typically be driven by a control signal to enable/disable the HDMI termination network as needed, rather than being permanently tied to power.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="19.21,37.14,27.62,44.64" aspect-ratio="1.29" } - Pin 1 is connected to net $15N747, which also connects to Q101 gate pin G *(from schematic)* - Pin 2 is connected to net +VCC3 *(from schematic)* - R809 has a value of 0Ω, effectively creating a direct connection between Q101 gate and +VCC3 *(from schematic)* - The net name $15N747 starts with &#x27;$&#x27;, which in most EDA tools indicates an auto-generated net name created when there is a floating connection or missing net label *(reasoning)* - R809 has an empty PLACE attribute, suggesting uncertainty about whether this component should be placed or indicating the design is incomplete *(from schematic)* - With the gate tied directly to +VCC3, Q101 will be permanently enabled whenever +VCC3 is present, making the termination network always active with no independent control *(reasoning)* - The circuit includes other control signals (LS_OE, HPD_ENB) for the HDMI interface, suggesting that controllable termination would be more consistent with the overall design intent *(from schematic)* - If permanent enable was the design intent, the gate could be directly connected to +VCC3 without requiring a separate 0Ω resistor and auto-generated net *(reasoning)* - The combination of auto-generated net name, empty PLACE attribute, and unusual connection scheme indicates this is likely an incomplete or incorrect connection rather than intentional design *(reasoning)* _{Upload a datasheet: [📤 R809](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/110-0001853)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component C91, pins 1, 2: Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.

• Pin 1 is connected to GND and pin 2 is connected to VBUS1 (from schematic)
• C91 is a 22uF capacitor providing bulk decoupling for VBUS1 (from schematic)
• The component attributes show PartDescription '22uF 20% 6.3V 0805', indicating a 6.3V voltage rating (from schematic)
• The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) (reasoning)
• USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads (reasoning)
• The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF (reasoning)
• The capacitance should be increased to at least 120uF per port to meet USB specification requirements (reasoning)

All affected pins

Component C91, pins `1, 2`: Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.

• Pin 1 is connected to GND and pin 2 is connected to VBUS1 (from schematic)
• C91 is a 22uF capacitor providing bulk decoupling for VBUS1 (from schematic)
• The component attributes show PartDescription '22uF 20% 6.3V 0805', indicating a 6.3V voltage rating (from schematic)
• The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) (reasoning)
• USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads (reasoning)
• The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF (reasoning)
• The capacitance should be increased to at least 120uF per port to meet USB specification requirements (reasoning)

Component C103, pins `1, 2`: Bulk decoupling capacitor for VBUS2 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.

• Pin 1 is connected to GND and pin 2 is connected to VBUS2 (from schematic)
• C103 is a 22uF capacitor providing bulk decoupling for VBUS2 (from schematic)
• The component attributes show PartDescription '22uF 20% 6.3V 0805', indicating a 6.3V voltage rating (from schematic)
• The total capacitance on VBUS2 is approximately 22.2uF, including C103 (22uF), C70 (0.1uF), and C234 (0.1uF) (reasoning)
• USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads (reasoning)
• The total capacitance of 22.2uF on VBUS2 represents only 18.5% of the USB specification requirement of 120uF (reasoning)
• The capacitance should be increased to at least 120uF per port to meet USB specification requirements (reasoning)

_{Upload a datasheet: 📤 C103 📤 C91}

[🚨 Error] **Component `C91`, pins `1, 2`: Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="55.34,46.25,62.84,54.34" aspect-ratio="1.29" } - Pin 1 is connected to GND and pin 2 is connected to VBUS1 *(from schematic)* - C91 is a 22uF capacitor providing bulk decoupling for VBUS1 *(from schematic)* - The component attributes show PartDescription &#x27;22uF 20% 6.3V 0805&#x27;, indicating a 6.3V voltage rating *(from schematic)* - The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) *(reasoning)* - USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads *(reasoning)* - The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF *(reasoning)* - The capacitance should be increased to at least 120uF per port to meet USB specification requirements *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>C91</code>, pins `1, 2`: Bulk decoupling capacitor for VBUS1 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.</summary> - Pin 1 is connected to GND and pin 2 is connected to VBUS1 *(from schematic)* - C91 is a 22uF capacitor providing bulk decoupling for VBUS1 *(from schematic)* - The component attributes show PartDescription &#x27;22uF 20% 6.3V 0805&#x27;, indicating a 6.3V voltage rating *(from schematic)* - The total capacitance on VBUS1 is approximately 22.2uF, including C91 (22uF), C82 (0.1uF), and C235 (0.1uF) *(reasoning)* - USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads *(reasoning)* - The total capacitance of 22.2uF on VBUS1 represents only 18.5% of the USB specification requirement of 120uF *(reasoning)* - The capacitance should be increased to at least 120uF per port to meet USB specification requirements *(reasoning)* </details> <details> <summary>Component <code>C103</code>, pins `1, 2`: Bulk decoupling capacitor for VBUS2 with insufficient capacitance for USB specification compliance. The 22uF value is significantly below the required 120uF minimum for USB host ports.</summary> - Pin 1 is connected to GND and pin 2 is connected to VBUS2 *(from schematic)* - C103 is a 22uF capacitor providing bulk decoupling for VBUS2 *(from schematic)* - The component attributes show PartDescription &#x27;22uF 20% 6.3V 0805&#x27;, indicating a 6.3V voltage rating *(from schematic)* - The total capacitance on VBUS2 is approximately 22.2uF, including C103 (22uF), C70 (0.1uF), and C234 (0.1uF) *(reasoning)* - USB 2.0 specification section 7.2.4.1 requires a minimum of 120μF of capacitance on VBUS for host or hub ports to handle inrush current and provide stable voltage during transient loads *(reasoning)* - The total capacitance of 22.2uF on VBUS2 represents only 18.5% of the USB specification requirement of 120uF *(reasoning)* - The capacitance should be increased to at least 120uF per port to meet USB specification requirements *(reasoning)* </details> </details> _{Upload a datasheet: [📤 C103](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176) [📤 C91](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/123-0001176)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component U13, pin 10: BST pin connected to bootstrap circuit with non-standard 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. This deviates from datasheet recommendation of direct capacitor connection between BST and SW pins.

• Pin 10 (BST) connects to net PS3_BST (from schematic)
• PS3_BST connects through R291 (4.7Ω) to intermediate node $22N1498 (from schematic)
• Node $22N1498 connects through C306 (0.1uF) to PS3VSB_PHASE (SW pins) (from schematic)
• This forms bootstrap circuit: BST → R291 (4.7Ω) → C306 (0.1uF) → SW (from schematic)
• BST is the bootstrap pin where a capacitor connected between SW and BST pins forms floating supply across high-side switch driver (from datasheet NB670, page 5)
• Datasheet typical application shows 100nF ceramic capacitor directly between BST and SW pins without any series resistor (from datasheet NB670, page 18)
• The bootstrap voltage path (BST, capacitor, SW) should be kept as short as possible (from datasheet NB670, page 16)
• The 4.7Ω series resistor creates RC time constant of 0.47μs with 0.1uF capacitor, which is approximately 24% of the 2μs switching period at 500kHz (reasoning)
• During bootstrap charging, voltage drop across 4.7Ω resistor would be approximately 0.47-0.94V for typical gate charge currents of 100-200mA, which is 9-19% of the nominal 5V bootstrap voltage (reasoning)
• While the series resistor might provide benefits such as EMI reduction, inrush current limiting, or damping, this configuration is not documented in the datasheet and deviates from recommended design (reasoning)
• The non-standard bootstrap circuit configuration could potentially affect gate drive voltage and bootstrap capacitor charging, especially during startup, transient conditions, or at the edges of the operating range (reasoning)
• This deviation from datasheet recommendation should be verified through testing to ensure proper bootstrap operation across all operating conditions (reasoning)

_{Replace a datasheet: 📤 U13}

[🚨 Error] **Component `U13`, pin `10`: BST pin connected to bootstrap circuit with non-standard 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. This deviates from datasheet recommendation of direct capacitor connection between BST and SW pins.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="61.70,20.38,69.20,27.88" aspect-ratio="1.29" } - Pin 10 (BST) connects to net PS3_BST *(from schematic)* - PS3_BST connects through R291 (4.7Ω) to intermediate node $22N1498 *(from schematic)* - Node $22N1498 connects through C306 (0.1uF) to PS3VSB_PHASE (SW pins) *(from schematic)* - This forms bootstrap circuit: BST → R291 (4.7Ω) → C306 (0.1uF) → SW *(from schematic)* - BST is the bootstrap pin where a capacitor connected between SW and BST pins forms floating supply across high-side switch driver *(from datasheet [NB670](<https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=5>), page 5)* - Datasheet typical application shows 100nF ceramic capacitor directly between BST and SW pins without any series resistor *(from datasheet [NB670](<https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=18>), page 18)* - The bootstrap voltage path (BST, capacitor, SW) should be kept as short as possible *(from datasheet [NB670](<https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=16>), page 16)* - The 4.7Ω series resistor creates RC time constant of 0.47μs with 0.1uF capacitor, which is approximately 24% of the 2μs switching period at 500kHz *(reasoning)* - During bootstrap charging, voltage drop across 4.7Ω resistor would be approximately 0.47-0.94V for typical gate charge currents of 100-200mA, which is 9-19% of the nominal 5V bootstrap voltage *(reasoning)* - While the series resistor might provide benefits such as EMI reduction, inrush current limiting, or damping, this configuration is not documented in the datasheet and deviates from recommended design *(reasoning)* - The non-standard bootstrap circuit configuration could potentially affect gate drive voltage and bootstrap capacitor charging, especially during startup, transient conditions, or at the edges of the operating range *(reasoning)* - This deviation from datasheet recommendation should be verified through testing to ensure proper bootstrap operation across all operating conditions *(reasoning)* _{Replace a datasheet: [📤 U13](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/NB670)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component L4, pin 2: Inductor connections are topologically correct (pin 1 to switching node VGFX-SW, pin 2 to output +VGFX), but the inductor current rating is insufficient for the design requirements.

• Pin 1 connects to net VGFX-SW (switching node from U26) (from schematic)
• Pin 2 connects to net +VGFX (regulated output voltage) (from schematic)
• The inductor is specified as 470nH with 17.5A current rating and 4.2mΩ DCR (from schematic)
• Multiple output capacitors (C66, C67, C68, C78, C79, C80, C81, C76, C77) connect to +VGFX (from schematic)
• In a buck converter topology, the inductor connects between the switching node and the output voltage rail, which is correct here (reasoning)
• A text note 'IMAX = 24A' is positioned at coordinates (462.28, 229.87), very close to L4's position at (462.28, 181.61) (from schematic)
• A separate text note 'IMAX = 14A' is positioned at (388.62, 242.57) near the current limit configuration resistors R207 and R227 (from schematic)
• R227 (16.5K) connects U26 pin 36 (IOUT) to AGND-VGFX, and R207 (44.2K) connects U26 pin 35 (IMAX) to AGND-VGFX, setting the controller current limit (from schematic)
• The switching frequency is 650kHz based on text note and R203 (18.7K) connected to the FREQ pin (from schematic)
• There is a significant discrepancy between the inductor's 17.5A rating and the 24A specification noted near the inductor (reasoning)
• Even if the controller is configured for 14A average current limit, the peak inductor current including switching ripple could approach or exceed 17.5A (reasoning)
• For a buck converter with Vin≈5V (from +5VSB_SW) and Vout≈1V (typical GPU core voltage), 470nH inductance, and 650kHz switching frequency, the current ripple would be approximately 2.6A peak-to-peak (reasoning)
• At 14A average current, the peak current would be approximately 15.3A, which provides minimal margin below the 17.5A rating (reasoning)
• At 24A average current (if that is the actual requirement), the peak current would exceed 25A, far exceeding the inductor's rating (reasoning)
• Operating an inductor above its rated current can cause saturation (loss of inductance) or thermal failure (reasoning)
• The inductor should be rated for at least the maximum expected current with 20-30% design margin (reasoning)
• The design has conflicting specifications that need resolution: either the 24A requirement should be verified and a higher-rated inductor used, or the 24A specification is incorrect and should be corrected to match the actual 14A design limit (reasoning)

_{Upload a datasheet: 📤 L4}

[🚨 Error] **Component `L4`, pin `2`: Inductor connections are topologically correct (pin 1 to switching node VGFX-SW, pin 2 to output +VGFX), but the inductor current rating is insufficient for the design requirements.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="80.79,53.60,88.29,61.10" aspect-ratio="1.29" } - Pin 1 connects to net VGFX-SW (switching node from U26) *(from schematic)* - Pin 2 connects to net +VGFX (regulated output voltage) *(from schematic)* - The inductor is specified as 470nH with 17.5A current rating and 4.2mΩ DCR *(from schematic)* - Multiple output capacitors (C66, C67, C68, C78, C79, C80, C81, C76, C77) connect to +VGFX *(from schematic)* - In a buck converter topology, the inductor connects between the switching node and the output voltage rail, which is correct here *(reasoning)* - A text note &#x27;IMAX = 24A&#x27; is positioned at coordinates (462.28, 229.87), very close to L4&#x27;s position at (462.28, 181.61) *(from schematic)* - A separate text note &#x27;IMAX = 14A&#x27; is positioned at (388.62, 242.57) near the current limit configuration resistors R207 and R227 *(from schematic)* - R227 (16.5K) connects U26 pin 36 (IOUT) to AGND-VGFX, and R207 (44.2K) connects U26 pin 35 (IMAX) to AGND-VGFX, setting the controller current limit *(from schematic)* - The switching frequency is 650kHz based on text note and R203 (18.7K) connected to the FREQ pin *(from schematic)* - There is a significant discrepancy between the inductor&#x27;s 17.5A rating and the 24A specification noted near the inductor *(reasoning)* - Even if the controller is configured for 14A average current limit, the peak inductor current including switching ripple could approach or exceed 17.5A *(reasoning)* - For a buck converter with Vin≈5V (from +5VSB_SW) and Vout≈1V (typical GPU core voltage), 470nH inductance, and 650kHz switching frequency, the current ripple would be approximately 2.6A peak-to-peak *(reasoning)* - At 14A average current, the peak current would be approximately 15.3A, which provides minimal margin below the 17.5A rating *(reasoning)* - At 24A average current (if that is the actual requirement), the peak current would exceed 25A, far exceeding the inductor&#x27;s rating *(reasoning)* - Operating an inductor above its rated current can cause saturation (loss of inductance) or thermal failure *(reasoning)* - The inductor should be rated for at least the maximum expected current with 20-30% design margin *(reasoning)* - The design has conflicting specifications that need resolution: either the 24A requirement should be verified and a higher-rated inductor used, or the 24A specification is incorrect and should be corrected to match the actual 14A design limit *(reasoning)* _{Upload a datasheet: [📤 L4](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/3120-0266)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[🚨 Error] Component U41, pin 22: BOOT pin connected to bootstrap network with C309 (0.1µF) and series resistor R298 (4.7Ω). Bootstrap capacitor is 10x smaller than datasheet recommendation of 1µF, which may cause insufficient gate drive and reliability issues.

• Pin 22 (BOOT) is connected to net $25N771 (from schematic)
• BOOT is the boost flying capacitor connection for VDDQ (from datasheet RT8207, page 2)
• The instantaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins (from datasheet RT8207, page 15)
• Datasheet typical application circuit shows 1µF bootstrap capacitor (from datasheet RT8207, page 3)
• For high current applications, adding a resistor in series with BOOT can prevent shoot-through by increasing turn-on rising time (from datasheet RT8207, page 15)
• The 4.7Ω series resistor R298 is appropriate for shoot-through prevention (reasoning)
• For typical MOSFET gate charge of 10-30nC, 0.1µF provides 50nC with 0.5V droop, giving margin of only 1.7-5x (reasoning)
• With recommended 1µF, margin increases to 17-50x, providing much better reliability (reasoning)
• The 10x reduction from recommended value could cause insufficient gate drive at high frequencies, temperature extremes, or with MOSFETs having higher gate charge (reasoning)
• Bootstrap capacitor C309 should be increased to 1µF per datasheet recommendation (reasoning)

_{Replace a datasheet: 📤 U41}

[🚨 Error] **Component `U41`, pin `22`: BOOT pin connected to bootstrap network with C309 (0.1µF) and series resistor R298 (4.7Ω). Bootstrap capacitor is 10x smaller than datasheet recommendation of 1µF, which may cause insufficient gate drive and reliability issues.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="45.80,38.02,53.30,45.52" aspect-ratio="1.29" } - Pin 22 (BOOT) is connected to net $25N771 *(from schematic)* - BOOT is the boost flying capacitor connection for VDDQ *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=2>), page 2)* - The instantaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=15>), page 15)* - Datasheet typical application circuit shows 1µF bootstrap capacitor *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=3>), page 3)* - For high current applications, adding a resistor in series with BOOT can prevent shoot-through by increasing turn-on rising time *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=15>), page 15)* - The 4.7Ω series resistor R298 is appropriate for shoot-through prevention *(reasoning)* - For typical MOSFET gate charge of 10-30nC, 0.1µF provides 50nC with 0.5V droop, giving margin of only 1.7-5x *(reasoning)* - With recommended 1µF, margin increases to 17-50x, providing much better reliability *(reasoning)* - The 10x reduction from recommended value could cause insufficient gate drive at high frequencies, temperature extremes, or with MOSFETs having higher gate charge *(reasoning)* - Bootstrap capacitor C309 should be increased to 1µF per datasheet recommendation *(reasoning)* _{Replace a datasheet: [📤 U41](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/4e527de7/.allspice/datasheets/RT8207)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-16 00:04:44 +00:00

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[⚠️ Warning] Component C129, pins 1, 2: 330uF tantalum capacitor connected between +VDIMM (1.35V) and GND for bulk output filtering. The 2V voltage rating provides 48% margin above the 1.35V nominal output, resulting in 67.5% voltage utilization which exceeds the standard 50% derating guideline typically recommended for tantalum capacitors.

• Pin 1 (P) is connected to +VDIMM net (from schematic)
• Pin 2 (N) is connected to GND net (from schematic)
• C129 is a 330uF tantalum capacitor with 2V voltage rating in C7343 package (from schematic)
• The +VDIMM output voltage is 1.35V according to the text note on the schematic (from schematic)
• The polarity is correct with positive terminal connected to the positive rail and negative terminal to ground (reasoning)
• The voltage margin is 2V / 1.35V = 1.48x or 48% above nominal, resulting in 67.5% voltage utilization (reasoning)
• Industry standard practice for tantalum capacitors recommends 50% voltage derating for reliability, meaning a 2V capacitor should ideally be used at maximum 1V continuous operation (reasoning)
• Operating at 67.5% of rated voltage exceeds the conservative 50% derating guideline by 35% (reasoning)
• While some modern tantalum capacitors may be qualified for operation above 50% of rated voltage, this should be verified against the specific part number datasheet (reasoning)
• For conservative design following standard derating practices at 1.35V, a tantalum capacitor should be rated for at least 2.7V, preferably 4V or higher (reasoning)
• The marginal voltage rating may impact long-term reliability, particularly under voltage transients or elevated temperature conditions (reasoning)
• Recommendation: Verify that part number 123-0005035 datasheet explicitly allows operation at 67.5% of rated voltage, or consider replacing with a capacitor rated for at least 4V to provide adequate margin (reasoning)

[⚠️ Warning] **Component `C129`, pins `1, 2`: 330uF tantalum capacitor connected between +VDIMM (1.35V) and GND for bulk output filtering. The 2V voltage rating provides 48% margin above the 1.35V nominal output, resulting in 67.5% voltage utilization which exceeds the standard 50% derating guideline typically recommended for tantalum capacitors.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5f47a223a6ef8e398e129ab6b1219f25d430a057" pr="185" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="79.88,43.31,87.38,51.40" aspect-ratio="1.29" } - Pin 1 (P) is connected to +VDIMM net *(from schematic)* - Pin 2 (N) is connected to GND net *(from schematic)* - C129 is a 330uF tantalum capacitor with 2V voltage rating in C7343 package *(from schematic)* - The +VDIMM output voltage is 1.35V according to the text note on the schematic *(from schematic)* - The polarity is correct with positive terminal connected to the positive rail and negative terminal to ground *(reasoning)* - The voltage margin is 2V / 1.35V = 1.48x or 48% above nominal, resulting in 67.5% voltage utilization *(reasoning)* - Industry standard practice for tantalum capacitors recommends 50% voltage derating for reliability, meaning a 2V capacitor should ideally be used at maximum 1V continuous operation *(reasoning)* - Operating at 67.5% of rated voltage exceeds the conservative 50% derating guideline by 35% *(reasoning)* - While some modern tantalum capacitors may be qualified for operation above 50% of rated voltage, this should be verified against the specific part number datasheet *(reasoning)* - For conservative design following standard derating practices at 1.35V, a tantalum capacitor should be rated for at least 2.7V, preferably 4V or higher *(reasoning)* - The marginal voltage rating may impact long-term reliability, particularly under voltage transients or elevated temperature conditions *(reasoning)* - Recommendation: Verify that part number 123-0005035 datasheet explicitly allows operation at 67.5% of rated voltage, or consider replacing with a capacitor rated for at least 4V to provide adequate margin *(reasoning)*

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Reference: NoIndexTests/E2E-Turbot-BOMGEN#185

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