NoIndexTests/E2E-Turbot-BOMGEN
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E2E @ f552732b - push to main #193

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shrikanthup wants to merge 2 commits from refs/pull/193/head into main
pull from: refs/pull/193/head
merge into: NoIndexTests:main
Conversation 2 Commits 2 Changes 7 +512 -81
shrikanthup commented 2026-05-27 18:43:31 +00:00 (Migrated from staging.allspice.dev)
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Source: push to main
Ref: f552732b4884a517c69cfc30202d0763774a9fea
Mode: e2e
Cache: enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache)
Cleanup: auto-closed after 7 days

Resolved config 
{
  "dump_analysis_dir": "debug_dump",
  "libraries": [
    {
      "ipn_column": "IPN",
      "mpn_column": "MPN",
      "path": ".allspice/library.csv",
      "type": "csv"
    },
    {
      "digikey_client_id_env": "DIGIKEY_CLIENT_ID",
      "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET",
      "type": "digikey"
    }
  ]
}

Triggered at 2026-05-27T18:43:29.200916Z. Branch 2702cc92 will be deleted on cleanup.

**Source:** push to main **Ref:** [`f552732b4884a517c69cfc30202d0763774a9fea`](https://github.com/AllSpiceIO/connections-checker/tree/f552732b4884a517c69cfc30202d0763774a9fea) **Mode:** e2e **Cache:** enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache) **Cleanup:** auto-closed after 7 days <details> <summary>Resolved config</summary> ```json { "dump_analysis_dir": "debug_dump", "libraries": [ { "ipn_column": "IPN", "mpn_column": "MPN", "path": ".allspice/library.csv", "type": "csv" }, { "digikey_client_id_env": "DIGIKEY_CLIENT_ID", "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET", "type": "digikey" } ] } ``` </details> Triggered at 2026-05-27T18:43:29.200916Z. Branch `2702cc92` will be deleted on cleanup.
AllSpiceAlice commented 2026-05-27 19:04:20 +00:00 (Migrated from staging.allspice.dev)
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DRCY has reviewed this Design Review, and there should be a review posted below.

DRCY has reviewed this Design Review, and there should be a review posted below.
AllSpiceAlice (Migrated from staging.allspice.dev) reviewed 2026-05-27 22:07:01 +00:00
AllSpiceAlice (Migrated from staging.allspice.dev) left a comment
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DRCY Connections Checker Review

DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 400 component(s) to review, and found 12 potential issue(s) in 15 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator Pin Name Net Correct? Analysis
AK12 DDI0_RCOMP_P DDI_RCOMP_N ❌
DDI0 RCOMP pins are swapped. AK13 (negative RCOMP) is connected to DDI_RCOMP_P, and AK12 (positive RCOMP) is connected to DDI_RCOMP_N.
  • Pin AK13 has the name D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating negative/complement signal (from schematic)
  • Pin AK12 has the name DDI0_RCOMP_P with _P suffix indicating positive signal (from schematic)
  • Pin AK13 is connected to net DDI_RCOMP_P (positive net name) (from schematic)
  • Pin AK12 is connected to net DDI_RCOMP_N (negative net name) (from schematic)
  • The overline notation in pin names is a standard convention to indicate active-low or complement signals (reasoning)
  • A 402 ohm resistor (R217) is connected between DDI_RCOMP_N and DDI_RCOMP_P (from schematic)
  • The RCOMP pins require an external resistor for display port compensation per Intel Atom E3800 design guidelines (from datasheet 140-0004628)
  • The polarity of the RCOMP connections is reversed - the negative pin is connected to the positive net and vice versa (reasoning)
  • The connections should be corrected: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)
AK13 ~DDI0_RCOMP DDI_RCOMP_P ❌
DDI0 RCOMP pins are swapped. AK13 (negative RCOMP) is connected to DDI_RCOMP_P, and AK12 (positive RCOMP) is connected to DDI_RCOMP_N.
  • Pin AK13 has the name D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating negative/complement signal (from schematic)
  • Pin AK12 has the name DDI0_RCOMP_P with _P suffix indicating positive signal (from schematic)
  • Pin AK13 is connected to net DDI_RCOMP_P (positive net name) (from schematic)
  • Pin AK12 is connected to net DDI_RCOMP_N (negative net name) (from schematic)
  • The overline notation in pin names is a standard convention to indicate active-low or complement signals (reasoning)
  • A 402 ohm resistor (R217) is connected between DDI_RCOMP_N and DDI_RCOMP_P (from schematic)
  • The RCOMP pins require an external resistor for display port compensation per Intel Atom E3800 design guidelines (from datasheet 140-0004628)
  • The polarity of the RCOMP connections is reversed - the negative pin is connected to the positive net and vice versa (reasoning)
  • The connections should be corrected: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)
A29 RESERVED_A29 GPIO_NC13 ✅ RESERVED_A29 pin connected to GPIO_NC13 with 10K pull-down resistor R102.
B26 DDI0_BKLTCTL ✅ DDI0_BKLTCTL pin for backlight control, connection not shown in this schematic section.
B28 DDI0_VDDEN ✅ DDI0_VDDEN signal is not connected, which is acceptable for HDMI mode operation.
B30 GPIO_S0_NC12 $3N566 ✅ GPIO_S0_NC12 connected to test point TP15 which is marked DNI, leaving the pin effectively floating.
C26 DDI0_DDCDATA HDMI_DDCDAT ✅ DDI0_DDCDATA connected to HDMI_DDCDAT for HDMI monitor communication via DDC.
C27 DDI0_BKLTEN ✅ DDI0_BKLTEN signal is not connected, which is acceptable for HDMI mode operation.
C28 DDI0_DDCCLK HDMI_DDCCLK ✅ DDI0_DDCCLK connected to HDMI_DDCCLK for HDMI monitor communication via DDC.
C29 RESERVED_C29 ✅ Reserved pins with no connections, which is standard practice.
C30 RESERVED_C30 ✅ Reserved pins with no connections, which is standard practice.
D27 DDI0_HPD HDMI_HPD_B ✅ DDI0_HPD connected to HDMI_HPD_B, which is the inverted hot plug detect signal from U39.
D28 RESERVED_D28 ✅ Reserved pins with no connections, which is standard practice.
D32 RESERVED_D32 ✅ Reserved pins with no connections, which is standard practice.
D34 RESERVED_D34 ✅ Reserved pins with no connections, which is standard practice.
F28 RESERVED_F28 ✅ Reserved pins with no connections, which is standard practice.
F32 RESERVED_F32 ✅ Reserved pins with no connections, which is standard practice.
F34 RESERVED_F34 ✅ Reserved pins with no connections, which is standard practice.
G30 DDI1_DDCCLK GND ✅ DDI1_DDCCLK grounded, indicating DDI1 port is disabled.
J28 RESERVED_J28 ✅ DDI1_BKLTEN is not connected and J28, J34 are reserved pins, all consistent with DDI1 being disabled.
J30 DDI1_BKLTEN ✅ DDI1_BKLTEN is not connected and J28, J34 are reserved pins, all consistent with DDI1 being disabled.
J34 RESERVED_J34 ✅ DDI1_BKLTEN is not connected and J28, J34 are reserved pins, all consistent with DDI1 being disabled.
K28 RESERVED_K28 ✅ DDI1_HPD is connected to GND to disable the port, and K28, K34 are reserved pins.
K34 RESERVED_K34 ✅ DDI1_HPD is connected to GND to disable the port, and K28, K34 are reserved pins.
K30 DDI1_HPD GND ✅ DDI1_HPD grounded, indicating DDI1 port is disabled.
M30 DDI1_BKLTCTL ✅ DDI1_BKLTCTL is not connected, consistent with DDI1 being disabled.
M32 RESERVED_M32 ✅ Reserved pin with no connection, which is standard practice.
N30 DDI1_VDDEN ✅ DDI1_VDDEN is not connected, consistent with DDI1 being disabled.
N32 RESERVED_N32 ✅ Reserved pin with no connection, which is standard practice.
P14 RESERVED_P14 MCSI_RCOMP ✅ RESERVED_P14 connected to MCSI_RCOMP with 150 ohm termination resistor R213.
P30 DDI1_DDCDATA DDI1_DDCDAT ✅ DDI1_DDCDATA connected to DDI1_DDCDAT with 2.2K pull-down resistor R257, though DDI1 is otherwise disabled.
R1 RESERVED_R1 ✅ Reserved pins with no connections, which is standard practice.
R3 RESERVED_R3 ✅ Reserved pins with no connections, which is standard practice.
T2 RESERVED_T2 ✅ Reserved pins with no connections, which is standard practice.
T3 RESERVED_T3 ✅ Reserved pins with no connections, which is standard practice.
T4 RESERVED_T4 ✅ Reserved pins with no connections, which is standard practice.
T6 RESERVED_T6 ✅ Reserved pins with no connections, which is standard practice.
T7 RESERVED_T7 ✅ Reserved pins with no connections, which is standard practice.
T9 RESERVED_T9 ✅ Reserved pins with no connections, which is standard practice.
T10 RESERVED_T10 ✅ Reserved pins with no connections, which is standard practice.
T12 RESERVED_T12 ✅ Reserved pins with no connections, which is standard practice.
T13 RESERVED_T13 ✅ Reserved pins with no connections, which is standard practice.
T14 RESERVED_T14 ✅ Reserved pins with no connections, which is standard practice.
V2 RESERVED_V2 ✅ Reserved pins with no connections, which is standard practice.
V3 RESERVED_V3 ✅ Reserved pins with no connections, which is standard practice.
V4 RESERVED_V4 ✅ Reserved pins with no connections, which is standard practice.
V6 RESERVED_V6 ✅ Reserved pins with no connections, which is standard practice.
V9 RESERVED_V9 ✅ Reserved pins with no connections, which is standard practice.
V10 RESERVED_V10 ✅ Reserved pins with no connections, which is standard practice.
V13 RESERVED_V13 ✅ Reserved pins with no connections, which is standard practice.
V14 RESERVED_V14 ✅ Reserved pins with no connections, which is standard practice.
W1 RESERVED_W1 ✅ Reserved pins with no connections, which is standard practice.
W3 RESERVED_W3 ✅ Reserved pins with no connections, which is standard practice.
Y2 RESERVED_Y2 ✅ Reserved pins with no connections, which is standard practice.
Y3 RESERVED_Y3 ✅ Reserved pins with no connections, which is standard practice.
Y4 RESERVED_Y4 ✅ Reserved pins with no connections, which is standard practice.
Y6 RESERVED_Y6 ✅ Reserved pins with no connections, which is standard practice.
Y12 RESERVED_Y12 ✅ Reserved pins with no connections, which is standard practice.
Y13 RESERVED_Y13 ✅ Reserved pins with no connections, which is standard practice.
BA1 VGA_GREEN ✅ VGA_GREEN analog output is not connected, consistent with VGA interface not being fully implemented.
AB2 RESERVED_AB2 ✅ Reserved pins with no connections, which is standard practice.
AB3 RESERVED_AB3 ✅ Reserved pins with no connections, which is standard practice.
AB7 RESERVED_AB7 ✅ Reserved pins with no connections, which is standard practice.
AB9 RESERVED_AB9 ✅ Reserved pins with no connections, which is standard practice.
AB12 RESERVED_AB12 ✅ Reserved pins with no connections, which is standard practice.
AB13 RESERVED_AB13 ✅ Reserved pins with no connections, which is standard practice.
AB14 RESERVED_AB14 ✅ Reserved pins with no connections, which is standard practice.
BA3 VGA_RED ✅ VGA_RED analog output is not connected, consistent with VGA interface not being fully implemented.
AC1 DDI1_TXN_3 ✅ DDI1_TXN_3 and DDI1_TXP_3 differential transmit lane 3 signals are not connected, consistent with DDI1 port being intentionally disabled.
AC3 DDI1_TXP_3 ✅ DDI1_TXN_3 and DDI1_TXP_3 differential transmit lane 3 signals are not connected, consistent with DDI1 port being intentionally disabled.
BC1 VGA_DDCCLK CRT_CLK ✅ VGA_DDCCLK connected to CRT_CLK with 150 ohm series termination resistor R39.
AD2 DDI1_TXN_2 ✅ DDI1_TXN_2 and DDI1_TXP_2 differential transmit lane 2 signals are not connected, consistent with DDI1 port being disabled.
AD3 DDI1_TXP_2 ✅ DDI1_TXN_2 and DDI1_TXP_2 differential transmit lane 2 signals are not connected, consistent with DDI1 port being disabled.
BC2 VGA_DDCDATA CRT_DAT ✅ VGA_DDCDATA connected to CRT_DAT with 150 ohm series termination resistor R38.
AD4 RESERVED_AD4 ✅ Reserved pins with no connections, which is standard practice.
AD6 RESERVED_AD6 ✅ Reserved pins with no connections, which is standard practice.
BD2 VGA_HSYNC ✅ VGA_HSYNC signal is not connected, consistent with VGA interface not being fully implemented.
AF2 DDI1_TXN_1 ✅ DDI1_TXN_1 and DDI1_TXP_1 differential transmit lane 1 signals are not connected, consistent with DDI1 port being disabled.
AF3 DDI1_TXP_1 ✅ DDI1_TXN_1 and DDI1_TXP_1 differential transmit lane 1 signals are not connected, consistent with DDI1 port being disabled.
AF13 RESERVED_AF13 ✅ Reserved pins with no connections, which is standard practice.
AF14 RESERVED_AF14 ✅ Reserved pins with no connections, which is standard practice.
AH13 RESERVED_AH13 ✅ Reserved pins with no connections, which is standard practice.
AH14 RESERVED_AH14 ✅ Reserved pins with no connections, which is standard practice.
AG1 DDI1_TXN_0 ✅ DDI1_TXN_0 and DDI1_TXP_0 differential transmit lane 0 signals are not connected, consistent with DDI1 port being disabled.
AG3 DDI1_TXP_0 ✅ DDI1_TXN_0 and DDI1_TXP_0 differential transmit lane 0 signals are not connected, consistent with DDI1 port being disabled.
BF2 VGA_VSYNC ✅ VGA_VSYNC signal is not connected, consistent with VGA interface not being fully implemented.
AH2 RESERVED_VSS3 $3N554 ✅ RESERVED_VSS3 pin correctly connected to ground through 0 ohm resistor R43.
AH3 RESERVED_VSS2 $3N552 ✅ RESERVED_VSS2 pin correctly connected to ground through 0 ohm resistor R46.
AK2 DDI1_AUXN ✅ DDI1_AUXN and DDI1_AUXP auxiliary channel differential pair is not connected, consistent with DDI1 port being disabled.
AK3 DDI1_AUXP ✅ DDI1_AUXN and DDI1_AUXP auxiliary channel differential pair is not connected, consistent with DDI1 port being disabled.
AL1 DDI0_AUXN ✅ DDI0_AUXN and DDI0_AUXP auxiliary channel is not connected, which is correct for HDMI mode operation.
AL3 DDI0_AUXP ✅ DDI0_AUXN and DDI0_AUXP auxiliary channel is not connected, which is correct for HDMI mode operation.
AM2 RESERVED_VSS1 $3N589 ✅ RESERVED_VSS1 pin correctly connected to ground through 0 ohm resistor R41.
AM3 RESERVED_VSS0 $3N579 ✅ RESERVED_VSS0 pin correctly connected to ground through 0 ohm resistor R42.
AM13 RESERVED_AM13 ✅ Reserved pins with no connections, which is standard practice.
AM14 RESERVED_AM14 ✅ Reserved pins with no connections, which is standard practice.
AP2 DDI0_TXN_3 HDMI_CLK_DN ✅ DDI0_TXN_3 connected to HDMI_CLK_DN, providing the negative differential clock signal for HDMI interface.
AP3 DDI0_TXP_3 HDMI_CLK_DP ✅ DDI0_TXP_3 connected to HDMI_CLK_DP, providing the positive differential clock signal for HDMI interface.
AR1 DDI0_TXN_2 HDMI_TX0_DN ✅ DDI0_TXN_2 connected to HDMI_TX0_DN, providing negative differential data signal for HDMI data lane 0.
AR3 DDI0_TXP_2 HDMI_TX0_DP ✅ DDI0_TXP_2 connected to HDMI_TX0_DP, providing positive differential data signal for HDMI data lane 0.
AT2 DDI0_TXP_1 HDMI_TX1_DP ✅ DDI0_TXP_1 connected to HDMI_TX1_DP, providing positive differential data signal for HDMI data lane 1.
AT3 DDI0_TXN_1 HDMI_TX1_DN ✅ DDI0_TXN_1 connected to HDMI_TX1_DN, providing negative differential data signal for HDMI data lane 1.
AV2 DDI0_TXN_0 HDMI_TX2_DN ✅ DDI0_TXN_0 connected to HDMI_TX2_DN, providing negative differential data signal for HDMI data lane 2.
AV3 DDI0_TXP_0 HDMI_TX2_DP ✅ DDI0_TXP_0 connected to HDMI_TX2_DP, providing positive differential data signal for HDMI data lane 2.
AW1 VGA_IREF $3N548 ✅ VGA_IREF connected to 357 ohm reference resistor R40 to set VGA DAC output current.
AY2 VGA_BLUE ✅ VGA_BLUE analog output is not connected, consistent with VGA interface not being fully implemented.
AY3 VGA_IRTN GND ✅ VGA_IRTN connected to ground, providing the return path for VGA DAC reference current.
U39 - SN74LVC1G14DCKR ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 NC ✅ NC (No Connect) pin is left unconnected, which is acceptable per datasheet.
2 A HDMI_HPD ✅ Input pin A receives HDMI_HPD signal for Schmitt-trigger noise filtering before inversion.
3 GND GND ✅ Ground pin correctly connected to GND net.
4 Y HDMI_HPD_B ✅ Output pin Y provides inverted HDMI_HPD signal as HDMI_HPD_B to CPU DDI0_HPD input.
5 VCC +V1P8S ✅ Power pin correctly supplied by +V1P8S (1.8V) with proper decoupling capacitor.
R40 - 110-0004695 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 1 $3N548 ✅ 357Ω reference resistor connected between VGA_IREF (CPU1 pin AW1) and GND. Sets the VGA DAC reference current for analog video output.
2 2 GND ✅ 357Ω reference resistor connected between VGA_IREF (CPU1 pin AW1) and GND. Sets the VGA DAC reference current for analog video output.
R38 - 110-0002631 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 1 CRT_DAT ✅ R38 is connected as a 150Ω pull-down resistor on the VGA DDC data line (CRT_DAT). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors.
2 2 GND ✅ R38 is connected as a 150Ω pull-down resistor on the VGA DDC data line (CRT_DAT). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors.
R39 - 110-0002631 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 1 CRT_CLK ✅ R39 is connected as a 150Ω pull-down resistor on the VGA DDC clock line (CRT_CLK). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors.
2 2 GND ✅ R39 is connected as a 150Ω pull-down resistor on the VGA DDC clock line (CRT_CLK). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors.
R217 - 402 ohm 1% 1/4W 0402 ✅

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⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 1 DDI_RCOMP_N ✅ This 402Ω resistor is correctly connected between the two DDI0 RCOMP pins of the CPU (AK12 and AK13) through nets DDI_RCOMP_N and DDI_RCOMP_P. However, the net names are swapped relative to the CPU pin designations - DDI_RCOMP_N connects to CPU pin AK12 (DDI0_RCOMP_P) and DDI_RCOMP_P connects to CPU pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅). Since this is a non-polarized resistor, the swap does not affect electrical functionality. The root cause of the naming inconsistency is at the CPU pin connections.
2 2 DDI_RCOMP_P ✅ This 402Ω resistor is correctly connected between the two DDI0 RCOMP pins of the CPU (AK12 and AK13) through nets DDI_RCOMP_N and DDI_RCOMP_P. However, the net names are swapped relative to the CPU pin designations - DDI_RCOMP_N connects to CPU pin AK12 (DDI0_RCOMP_P) and DDI_RCOMP_P connects to CPU pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅). Since this is a non-polarized resistor, the swap does not affect electrical functionality. The root cause of the naming inconsistency is at the CPU pin connections.
R213 - 150 ohm 1% 1/16W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 1 MCSI_RCOMP ✅ Connected to CPU1 pin P14 (MCSI_RCOMP) to provide compensation resistance for the MCSI interface on Bay Trail-I variant.
2 2 GND ✅ Connected to ground to complete the MCSI compensation network.
R257 - 2.2K ohm 1% 1/10W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 1 DDI1_DDCDAT ✅ Pull-down resistor on DDI1_DDCDAT signal. This is part of intentionally disabling the DDI1 (Display Port 1) interface.
2 2 GND ✅ Connected to ground as part of pull-down configuration.
R102 - 110-0001875 ✅

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⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND, providing the ground reference for the pull-down resistor.
2 2 GPIO_NC13 ✅ Connected to GPIO_NC13, pulling this GPIO signal to ground through 10K resistance.
CPU1 - INTEL_ATOM_E3825_SOC ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator Pin Name Net Correct? Analysis
C24 ~PROCHOT VR_HOT_L ✅ PROCHOT thermal management signal, correctly connected with current limiting resistor to voltage rail.
N34 RESERVED_N34 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
P34 RESERVED_P34 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
BA12 SATA_GP0 SATA_GP0 ✅ SATA general purpose signal 0, correctly connected with pull-down resistor.
BA16 SATA_RXN_1 SATA1_RXN ✅ SATA port 1 receive negative signal, correctly connected through AC coupling capacitor to mSATA interface.
BA18 SD2_CLK ✅ SD2 clock signal, not connected. This is acceptable if SD2 interface is not used.
BA20 SD2_D2 ✅ SD2 data bit 2 signal, not connected. This is acceptable if SD2 interface is not used.
BA24 ~MMC1_RST ✅ MMC1 reset signal, not connected. This is acceptable if MMC1 interface is not used.
BA26 SD3_D3 SD3_D3 ✅ SD3 data bit 3 signal, connected to SD3_D3 for SD card interface.
BA30 LPE_I2S2_FRM LPE_I2S_FRM ✅ I2S frame sync signal, correctly connected with pull-up resistor.
BB3 RESERVED_BB3 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
BB4 RESERVED_BB4 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
BB5 RESERVED_VSS6 RESERVED_VSS6 ✅ Reserved VSS pin, correctly connected to ground through 0 ohm resistor.
BB7 RESERVED_VSS7 RESERVED_VSS7 ✅ Reserved VSS pin, correctly connected to ground through 0 ohm resistor.
BB10 RESERVED_VSS4 ICLK_SATA_TERMP ✅ SATA clock termination positive pin, correctly connected to ground through 0 ohm resistor.
BC10 RESERVED_VSS5 ICLK_SATA_TERMN ✅ SATA clock termination negative pin, correctly connected to ground through 0 ohm resistor.
BC18 SD2_CMD ✅ SD2 command signal, not connected. This is acceptable if SD2 interface is not used.
BC24 SD3_CD# SD3_CD# ✅ SD3 card detect signal, connected through 0 ohm resistor to SD3_WP. This is an intentional design decision for Bay Trail-I variant.
BC30 LPE_I2S2_DATAOUT LPE_I2S_DATOUT ✅ I2S data output signal, connected with series resistor and optional pull-down for hardware strapping.
BD5 SD3_WP_BD5 SD3_WP ✅ SD3 write protect signal, connected through 0 ohm resistor to SD3_CD#. This is an intentional design decision for Bay Trail-I variant.
BD7 ~PCIE_CLKREQ_1 CLKREQ1_B ✅ PCIe clock request 1 signal, correctly connected with pull-up resistor.
BD10 SATA_TXP1 SATA1_TXP ✅ SATA port 1 transmit positive signal, correctly connected through AC coupling capacitor to mSATA interface.
BD18 ~SD2_D3_CD ✅ SD2 data bit 3 / card detect signal, not connected. This is acceptable if SD2 interface is not used.
BD20 SD2_D1 ✅ SD2 data bit 1 signal, not connected. This is acceptable if SD2 interface is not used.
BD22 ~SD3_PWREN /SD3+PWREN ✅ SD3 power enable signal, connected to test point for monitoring.
BD26 SD3_D1 SD3_D1 ✅ SD3 data bit 1 signal, connected to SD3_D1 for SD card interface.
BD28 LPE_I2S2_DATAIN LPE_I2S_DATIN ✅ I2S data input signal, connected to LPE_I2S_DATIN for audio input.
BE3 ~PCIE_CLKREQ_3 mPCIe_CLKREQ3_B ✅ PCIe clock request 3 signal, correctly connected with pull-up resistor for mini PCIe interface.
BF6 SATA_TXP_0 SATA0_TXP ✅ SATA port 0 transmit positive signal, correctly connected through AC coupling capacitor to SATA connector.
BF10 SATA_TXN_1 SATA1_TXN ✅ SATA port 1 transmit negative signal, correctly connected through AC coupling capacitor to mSATA interface.
BF20 HDA_LPE_RCOMP HDA_RCOMP ✅ HD Audio / Low Power Engine compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
BF22 SD3_1P8EN SD3_1P8EN ✅ SD3 1.8V enable signal, connected to test point for monitoring.
BF26 SD3_RCOMP SD3_RCOMP ✅ SD3 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
BF28 LPE_I2S2_CLK LPE_I2S_CLK ✅ I2S clock signal, connected with pull-up resistor and series resistor for hardware strapping.
BG3 ~PCIE_CLKREQ_0 CLKREQ0_B ✅ PCIe clock request 0 signal, correctly connected with pull-up resistor.
BG5 ~PCIE_CLKREQ_2 LAN_CLKREQ2_B ✅ PCIe clock request 2 signal, correctly connected with pull-up resistor for LAN interface.
BG7 SATA_TXN_0 SATA0_TXN ✅ SATA port 0 transmit negative signal, correctly connected through AC coupling capacitor to SATA connector.
BG18 GPIO_S0_SC_15 ✅ GPIO signal, not connected. This is acceptable if this GPIO is not used.
BG19 HDA_SDI0 ✅ HD Audio SDI0 signal, not connected. This is acceptable if HD Audio interface is not used.
BG20 HDA_SDO ✅ HD Audio SDO signal, not connected. This is acceptable if HD Audio interface is not used.
BG21 HDA_SDI1 ✅ HD Audio SDI1 signal, not connected. This is acceptable if HD Audio interface is not used.
BG22 ~HDA_RST ✅ HD Audio reset signal, not connected. This is acceptable if HD Audio interface is not used.
BH18 GPIO_S0_SC_14 ✅ GPIO signal, not connected. This is acceptable if this GPIO is not used.
BH20 HDA_SYNC ✅ HD Audio sync signal, not connected. This is acceptable if HD Audio interface is not used.
AK7 RESERVED_AK7 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
AK9 RESERVED_AK9 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
BJ21 HDA_CLK ✅ HD Audio clock signal, not connected. This is acceptable if HD Audio interface is not used.
AP4 PCIE_TXN_3 mPCIE_TX_N ✅ PCIe port 3 transmit negative signal, connected to mPCIE_TX_N for mini PCIe interface.
AP6 PCIE_TXP_3 mPCIE_TX_P ✅ PCIe port 3 transmit positive signal, connected to mPCIE_TX_P for mini PCIe interface.
AP7 PCIE_RXN_3 mPCIE_RX_N ✅ PCIe port 3 receive negative signal, connected to mPCIE_RX_N for mini PCIe interface.
AP9 PCIE_RXP_3 mPCIE_RX_P ✅ PCIe port 3 receive positive signal, connected to mPCIE_RX_P for mini PCIe interface.
AP10 PCIE_RXN_2 PCIE_RXN2 ✅ PCIe port 2 receive negative signal, connected to PCIE_RXN2 for LAN interface.
AP12 PCIE_RXP_2 PCIE_RXP2 ✅ PCIe port 2 receive positive signal, connected to PCIE_RXP2 for LAN interface.
AP13 PCIE_RCOMP_N_AP13_AP13 PCIE_RCOMP_N ✅ PCIe compensation resistor negative pin, correctly connected to PCIE_RCOMP_N with 402 ohm resistor to PCIE_RCOMP_P.
AP14 PCIE_RCOMP_P_AP14_AP14 PCIE_RCOMP_P ✅ PCIe compensation resistor positive pin, correctly connected to PCIE_RCOMP_P with 402 ohm resistor to PCIE_RCOMP_N.
AT6 PCIE_TXN_2 PCIE_TXN2 ✅ PCIe port 2 transmit negative signal, connected to PCIE_TXN2 for LAN interface.
AT7 PCIE_TXP_2 PCIE_TXP2 ✅ PCIe port 2 transmit positive signal, connected to PCIE_TXP2 for LAN interface.
AT9 PCIE_RXN_1 ✅ PCIe port 1 receive negative signal, not connected. This is acceptable if PCIe port 1 is not used.
AT10 PCIE_RXP_1 ✅ PCIe port 1 receive positive signal, not connected. This is acceptable if PCIe port 1 is not used.
AT13 PCIE_RXN_0 ✅ PCIe port 0 receive negative signal, not connected. This is acceptable if PCIe port 0 is not used.
AT14 PCIE_RXP_0 ✅ PCIe port 0 receive positive signal, not connected. This is acceptable if PCIe port 0 is not used.
AT18 SATA_RCOMP_N_AT18 SATA_RCOMP_N ✅ SATA compensation resistor negative pin, correctly connected to SATA_RCOMP_N with 402 ohm resistor to SATA_RCOMP_P.
AT20 MMC1_D3 ✅ MMC1 data bit 3 signal, not connected. This is acceptable if MMC1 interface is not used.
AT22 MMC1_CLK ✅ MMC1 clock signal, not connected. This is acceptable if MMC1 interface is not used.
AT26 MMC1_D6 ✅ MMC1 data bit 6 signal, not connected. This is acceptable if MMC1 interface is not used.
AT28 SD3_D0 SD3_D0 ✅ SD3 data bit 0 signal, connected to SD3_D0 for SD card interface.
AU16 SATA_RXP_0 SATA0_RXP ✅ SATA port 0 receive positive signal, correctly connected through AC coupling capacitor to SATA connector.
AU18 SATA_RCOMP_P_AU18 SATA_RCOMP_P ✅ SATA compensation resistor positive pin, correctly connected to SATA_RCOMP_P with 402 ohm resistor to SATA_RCOMP_N.
AU20 MMC1_D7 ✅ MMC1 data bit 7 signal, not connected. This is acceptable if MMC1 interface is not used.
AU22 MMC1_D1 ✅ MMC1 data bit 1 signal, not connected. This is acceptable if MMC1 interface is not used.
AU26 MMC1_D5 ✅ MMC1 data bit 5 signal, not connected. This is acceptable if MMC1 interface is not used.
AU28 SD3_D2 SD3_D2 ✅ SD3 data bit 2 signal, connected to SD3_D2 for SD card interface.
AV4 PCIE_TXN_1 ✅ PCIe port 1 transmit negative signal, not connected. This is acceptable if PCIe port 1 is not used.
AV6 PCIE_TXP_1 ✅ PCIe port 1 transmit positive signal, not connected. This is acceptable if PCIe port 1 is not used.
AV9 RESERVED_AV9 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
AV10 RESERVED_AV10 ✅ Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved.
AV16 SATA_RXN_0 SATA0_RXN ✅ SATA port 0 receive negative signal, correctly connected through AC coupling capacitor to SATA connector.
AV20 MMC1_D0 ✅ MMC1 data bit 0 signal, not connected. This is acceptable if MMC1 interface is not used.
AV22 MMC1_D2 ✅ MMC1 data bit 2 signal, not connected. This is acceptable if MMC1 interface is not used.
AV26 MMC1_CMD ✅ MMC1 command signal, not connected. This is acceptable if MMC1 interface is not used.
AV28 SD3_CMD SD3_CMD ✅ SD3 command signal, connected to SD3_CMD for SD card interface.
AY6 PCIE_TXN_0 ✅ PCIe port 0 transmit negative signal, not connected. This is acceptable if PCIe port 0 is not used.
AY7 PCIE_TXP_0 ✅ PCIe port 0 transmit positive signal, not connected. This is acceptable if PCIe port 0 is not used.
AY12 ~SATA_LED SATA_LED_B ✅ SATA LED signal, correctly connected through current limiting resistor to LED indicator with jumper.
AY14 SATA_GP1 SATA_GP1 ✅ SATA general purpose signal 1, correctly connected with pull-down resistor.
AY16 SATA_RXP_1 SATA1_RXP ✅ SATA port 1 receive positive signal, correctly connected through AC coupling capacitor to mSATA interface.
AY18 MMC1_RCOMP MMC1_RCOMP ✅ MMC1 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
AY20 SD2_D0 ✅ SD2 data bit 0 signal, not connected. This is acceptable if SD2 interface is not used.
AY24 MMC1_D4 ✅ MMC1 data bit 4 signal, not connected. This is acceptable if MMC1 interface is not used.
AY26 SD3_CLK SD3_CLK ✅ SD3 clock signal, connected to SD3_CLK for SD card interface.
J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Ground pins for SATA differential signal pairs. These pins provide ground reference for the high-speed SATA signals.
4 4 GND ✅ Ground pins for SATA differential signal pairs. These pins provide ground reference for the high-speed SATA signals.
7 7 GND ✅ Ground pins for SATA differential signal pairs. These pins provide ground reference for the high-speed SATA signals.
2 2 SATA0_TXP_C ✅ SATA transmit positive signal (A+). Connected to CPU SATA0_TXP through AC coupling capacitor C10.
3 3 SATA0_TXN_C ✅ SATA transmit negative signal (A-). Connected to CPU SATA0_TXN through AC coupling capacitor C11.
5 5 SATA0_RXN_C ✅ SATA receive negative signal (B-). Connected to CPU SATA0_RXN through AC coupling capacitor C12.
6 6 SATA0_RXP_C ✅ SATA receive positive signal (B+). Connected to CPU SATA0_RXP through AC coupling capacitor C13.
8 MH1 GND_EARTH ✅ Mounting holes connected to chassis ground (GND_EARTH) for EMI shielding. This provides proper separation between signal ground and chassis ground.
9 MH2 GND_EARTH ✅ Mounting holes connected to chassis ground (GND_EARTH) for EMI shielding. This provides proper separation between signal ground and chassis ground.
J6 - HDR_2POS_DUAL_TIN ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Supply voltage (+V1P8S, 1.8V) for SATA activity LED circuit. This pin provides power to the LED when connected.
2 2 SATA_LED_R ✅ LED cathode connection (SATA_LED_R). Connects through current-limiting resistor R179 to CPU SATA LED output.
C177 - 123-0001038 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 mSATA_RX_N ✅ Connected to mSATA_RX_N net, providing AC coupling for SATA1 receive negative differential signal from mSATA interface to CPU.
2 2 SATA1_RXN ✅ Connected to SATA1_RXN net, which connects to CPU1 pin BA16 (SATA_RXN_1), completing the AC coupling path for the negative differential receive signal.
C178 - 123-0001038 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 mSATA_RX_P ✅ Connected to mSATA_RX_P net, providing AC coupling for SATA1 receive positive differential signal from mSATA interface to CPU.
2 2 SATA1_RXP ✅ Connected to SATA1_RXP net, which connects to CPU1 pin AY16 (SATA_RXP_1), completing the AC coupling path for the positive differential receive signal.
C179 - 123-0001038 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 mSATA_TX_P ✅ Connected to mSATA_TX_P net, providing AC coupling for SATA1 transmit positive differential signal from CPU to mSATA interface.
2 2 SATA1_TXP ✅ Connected to SATA1_TXP net, which connects to CPU1 pin BD10 (SATA_TXP1), completing the AC coupling path for the positive differential transmit signal.
C180 - 123-0001038 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 mSATA_TX_N ✅ Connected to mSATA_TX_N net, providing AC coupling for SATA1 transmit negative differential signal from CPU to mSATA interface.
2 2 SATA1_TXN ✅ Connected to SATA1_TXN net, which connects to CPU1 pin BF10 (SATA_TXN_1), completing the AC coupling path for the negative differential transmit signal.
R218 - 110-0004476 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 PCIE_RCOMP_P ✅ R218 is a 402 ohm RCOMP resistor connected between the CPU's PCIe compensation pins PCIE_RCOMP_P (pin AP14) and PCIE_RCOMP_N (pin AP13). This resistor is used for impedance calibration of the PCIe interface.
2 2 PCIE_RCOMP_N ✅ R218 is a 402 ohm RCOMP resistor connected between the CPU's PCIe compensation pins PCIE_RCOMP_P (pin AP14) and PCIE_RCOMP_N (pin AP13). This resistor is used for impedance calibration of the PCIe interface.
R242 - 110-0003059 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDA_RCOMP ✅ Pin 1 is connected to HDA_RCOMP, which connects to CPU1 pin BF20 to set the output driver impedance for the HDA interface.
2 2 GND ✅ Pin 2 is connected to GND, providing the ground reference for the HDA_RCOMP resistor.
R240 - 110-0003059 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pin 1 is connected to GND, providing the ground reference for the MMC1_RCOMP resistor.
2 2 MMC1_RCOMP ✅ Pin 2 is connected to MMC1_RCOMP, which connects to CPU1 pin AY18 to set the output driver impedance for the MMC1 interface.
R258 - 110-0003059 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pin 1 is connected to GND, providing the ground reference for the SD3_RCOMP resistor.
2 2 SD3_RCOMP ✅ Pin 2 is connected to SD3_RCOMP, which connects to CPU1 pin BF26 to set the output driver impedance for the SD3 interface.
R189 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pull-down resistor connection to GND for hardware strap GPIO_S0_SC_56. Component is DNI (Do Not Install) for field configuration.
2 2 GPIO_S0_SC_56 ✅ Connected to GPIO_S0_SC_56 hardware strap signal, shared with R219 pin 2. Component is DNI for field configuration.
R219 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Pull-up resistor connection to +V1P8S for hardware strap GPIO_S0_SC_56. Component is DNI (Do Not Install) for field configuration.
2 2 GPIO_S0_SC_56 ✅ Connected to GPIO_S0_SC_56 hardware strap signal, shared with R189 pin 2. Component is DNI for field configuration.
R234 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 BOM_OP3 ✅ 1K pull-down resistor connecting BOM_OP3 to GND, setting hardware ID bit 3 to logic 0. Part of a hardware identification circuit that reads '1001'.
2 2 GND ✅ 1K pull-down resistor connecting BOM_OP3 to GND, setting hardware ID bit 3 to logic 0. Part of a hardware identification circuit that reads '1001'.
R208 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 BOM_OP2 ✅ 1K pull-down resistor connecting BOM_OP2 to GND, setting hardware ID bit 2 to logic 0. Part of a hardware identification circuit that reads '1001'.
2 2 GND ✅ 1K pull-down resistor connecting BOM_OP2 to GND, setting hardware ID bit 2 to logic 0. Part of a hardware identification circuit that reads '1001'.
R233 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 BOM_OP1 ✅ 1K pull-down resistor marked DNI on BOM_OP1, allowing the net to be pulled high by R211. Part of a hardware identification circuit that reads '1001'.
2 2 GND ✅ 1K pull-down resistor marked DNI on BOM_OP1, allowing the net to be pulled high by R211. Part of a hardware identification circuit that reads '1001'.
R401 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 BOM_OP4 ✅ 1K pull-down resistor marked DNI on BOM_OP4, allowing the net to be pulled high by R400. Part of a hardware identification circuit that reads '1001'.
2 2 GND ✅ 1K pull-down resistor marked DNI on BOM_OP4, allowing the net to be pulled high by R400. Part of a hardware identification circuit that reads '1001'.
R209 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ✅ 10K pull-up resistor marked DNI on BOM_OP2, allowing the net to be pulled low by R208. Part of a hardware identification circuit that reads '1001'.
2 2 BOM_OP2 ✅ 10K pull-up resistor marked DNI on BOM_OP2, allowing the net to be pulled low by R208. Part of a hardware identification circuit that reads '1001'.
R210 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ✅ 10K pull-up resistor marked DNI on BOM_OP3, allowing the net to be pulled low by R234. Part of a hardware identification circuit that reads '1001'.
2 2 BOM_OP3 ✅ 10K pull-up resistor marked DNI on BOM_OP3, allowing the net to be pulled low by R234. Part of a hardware identification circuit that reads '1001'.
R211 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ✅ 10K pull-up resistor connecting BOM_OP1 to +V1P8A, setting hardware ID bit 1 to logic 1. Part of a hardware identification circuit that reads '1001'.
2 2 BOM_OP1 ✅ 10K pull-up resistor connecting BOM_OP1 to +V1P8A, setting hardware ID bit 1 to logic 1. Part of a hardware identification circuit that reads '1001'.
R400 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ✅ 10K pull-up resistor connecting BOM_OP4 to +V1P8A, setting hardware ID bit 4 to logic 1. Part of a hardware identification circuit that reads '1001'.
2 2 BOM_OP4 ✅ 10K pull-up resistor connecting BOM_OP4 to +V1P8A, setting hardware ID bit 4 to logic 1. Part of a hardware identification circuit that reads '1001'.
R191 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 CLKREQ0_B ✅ Connected to CLKREQ0_B signal, which goes to CPU1 pin BG3 (PCIE_CLKREQ_0). This is the pull-down side of the pull-up resistor.
2 2 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ0 signal.
R190 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 CLKREQ1_B ✅ Connected to CLKREQ1_B signal, which goes to CPU1 pin BD7 (PCIE_CLKREQ_1). This is the pull-down side of the pull-up resistor.
2 2 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ1 signal.
R71 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN_CLKREQ2_B ✅ Connected to LAN_CLKREQ2_B signal, which goes to CPU1 pin BG5 (PCIE_CLKREQ_2). This is the pull-down side of the pull-up resistor for the LAN interface.
2 2 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ2 signal.
R2 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 mPCIe_CLKREQ3_B ✅ Connected to mPCIe_CLKREQ3_B signal, which goes to CPU1 pin BE3 (PCIE_CLKREQ_3). This is the pull-down side of the pull-up resistor for the mPCIe card slot.
2 2 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ3 signal.
R260 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LPE_I2S_DATOUT ✅ Pin 1 connects to LPE_I2S_DATOUT net. This resistor is marked DNI (Do Not Install) and is electrically absent from the circuit.
2 2 GND ✅ Pin 2 connects to GND. This resistor is marked DNI (Do Not Install) and is electrically absent from the circuit.
R268 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LPE_I2S_FRM ✅ Pin 1 connects to LPE_I2S_FRM net, which is also known as GPIO_S0_SC63 and serves as a hardware strap for BIOS Boot Selection.
2 2 +V1P8S ✅ Pin 2 connects to +V1P8S supply, providing the pull-up voltage for the hardware strap.
R259 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GPIO_S5_10_UNLOCK ✅ Pin 1 connects to GPIO_S5_10_UNLOCK net. This pin is one end of a series resistor used to control the hardware strap value of the LPE_I2S_DATOUT signal.
2 2 LPE_I2S_DATOUT ✅ Pin 2 connects to LPE_I2S_DATOUT net, which is also known as GPIO_S0_SC65 and serves as a hardware strap for Security Flash Descriptors configuration.
R72 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 RESERVED_VSS6 ✅ Pin 1 connects to RESERVED_VSS6, which connects to CPU1 pin BB5 (RESERVED_VSS6). This is part of grounding a reserved CPU pin.
2 2 GND ✅ Pin 2 connects to GND. This completes the connection to ground a reserved CPU pin through a 0-ohm resistor.
R73 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pin 1 connects to GND. This is one side of a 0-ohm resistor used to ground a reserved CPU pin.
2 2 ICLK_SATA_TERMP ✅ Pin 2 connects to ICLK_SATA_TERMP, which connects to CPU1 pin BB10 (RESERVED_VSS4). This grounds a reserved CPU pin.
R74 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pin 1 connects to GND. This is one side of a 0-ohm resistor used to ground a reserved CPU pin.
2 2 ICLK_SATA_TERMN ✅ Pin 2 connects to ICLK_SATA_TERMN, which connects to CPU1 pin BC10 (RESERVED_VSS5). This grounds a reserved CPU pin.
R192 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 RESERVED_VSS7 ✅ Pin 1 connects to RESERVED_VSS7, which connects to CPU1 pin BB7 (RESERVED_VSS7). This is part of grounding a reserved CPU pin.
2 2 GND ✅ Pin 2 connects to GND. This completes the connection to ground a reserved CPU pin through a 0-ohm resistor.
R354 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SD3_WP ✅ 0 ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect) signals. This unusual configuration may be intentional due to Bay Trail-I processor-specific requirements.
2 2 SD3_CD# ✅ 0 ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect) signals. This unusual configuration may be intentional due to Bay Trail-I processor-specific requirements.
R255 - 110-0004474 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VR_HOT_L ✅ Pin 1 connects to VR_HOT_L net, which is the PROCHOT (processor hot) signal from CPU1 pin C24. This is an active-low thermal management signal.
2 2 +V1P0S ✅ Pin 2 connects to +V1P0S (1.0V supply), providing a pull-up for the PROCHOT signal. The 73.2 ohm value is unusually low for a typical pull-up but appears intentional.
CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator Pin Name Net Correct? Analysis
A9 ILB_RTC_X2 BRTCX2 ✅ ILB_RTC_X2 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor.
A13 GPIO_S5_9 SOC_USB_HOST_EN1 ✅ GPIO_S5_9 is routed off-page as SOC_USB_HOST_EN1, likely used for USB host port enable control.
A17 GPIO_S5_3 mPCIE_WAKEB ✅ GPIO_S5_3 is correctly configured as mPCIE wake input with optional pull-up resistor.
A21 PCU_SPI_MOSI SOC_SPI_MOSI ✅ PCU_SPI_MOSI is correctly connected through series resistor to the SPI flash interface.
A25 SVID_DATA SVID_DATA ✅ SVID_DATA is correctly connected through series resistor for voltage regulator communication.
B7 PMC_CORE_PWROK PMC_CORE_PWROK ✅ PMC_CORE_PWROK is correctly connected to system power good signal through series resistor.
B8 ILB_RTC_EXTPAD BVCCRTC_EXTPAD ✅ ILB_RTC_EXTPAD is correctly connected to decoupling capacitor for RTC battery backup.
B10 ~PMC_RSMRST PMC_RSMRST ✅ PMC_RSMRST is correctly connected with pull-up, pull-down, and RC filtering for resume reset control.
B14 GPIO_S5_6 BOM_OP2 ✅ GPIO_S5_6 routes off-page as BOM_OP2, likely used for board option configuration.
B16 GPIO_S5_1 SOC_GPIO_S5_1 ✅ GPIO_S5_1 routes off-page as SOC_GPIO_S5_1 for general purpose I/O.
B18 GPIO_S5_0 SOC_GPIO_S5_0 ✅ GPIO_S5_0 routes off-page as SOC_GPIO_S5_0 for general purpose I/O.
B22 PCU_SPI_MISO SOC_SPI_MISO ✅ PCU_SPI_MISO is correctly connected through series resistor to the SPI flash interface.
B24 ~SVID_ALERT SVID_ALERT ✅ SVID_ALERT is correctly connected through series resistor with pull-up for voltage regulator alert signaling.
C9 ILB_RTC_X1 BRTCX1 ✅ ILB_RTC_X1 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor.
C11 ~ILB_RTC_TEST ILB_RTC_TESTB ✅ ILB_RTC_TEST routes off-page for RTC test mode control.
C12 ~ILB_RTC_RST RTCRST_L ✅ ILB_RTC_RST is correctly connected with pull-up resistor and decoupling capacitor for RTC reset control.
C13 GPIO_S5_8 SOC_USB_HOST_EN0 ✅ GPIO_S5_8 routes off-page as SOC_USB_HOST_EN0, likely used for USB host port enable control.
C15 GPIO_S5_7 BOM_OP3 ✅ GPIO_S5_7 routes off-page as BOM_OP3, likely used for board option configuration.
C16 GPIO_S5_5 BOM_OP1 ✅ GPIO_S5_5 routes off-page as BOM_OP1, likely used for board option configuration.
C17 GPIO_S5_4 BOM_OP4 ✅ GPIO_S5_4 routes off-page as BOM_OP4, likely used for board option configuration.
C18 GPIO_S5_2 SOC_GPIO_S5_2 ✅ GPIO_S5_2 routes off-page as SOC_GPIO_S5_2 for general purpose I/O.
C19 GPIO_S5_10 GPIO_S5_10_UNLOCK ✅ GPIO_S5_10 routes off-page as GPIO_S5_10_UNLOCK for general purpose I/O.
C21 ~PCU_SPI_CS_11 SOC_SPI_CS1B ✅ PCU_SPI_CS_11 is connected through DNI series resistor, indicating SPI chip select 1 is not used.
C22 PCU_SPI_CLK SOC_SPI_CLK ✅ PCU_SPI_CLK is correctly connected through series resistor with optional capacitor for SPI clock signal.
C23 ~PCU_SPI_CS_00 SOC_SPI_CS0B ✅ PCU_SPI_CS_00 is correctly connected through series resistor to the SPI flash chip select.
C25 SVID_CLK SVID_CLK-R ✅ SVID_CLK routes off-page for Serial VID clock signal to voltage regulator.
D14 TAP_TCK XDP_H_TCK ✅ TAP_TCK is correctly connected with pull-down resistor for JTAG test clock.
D18 ~TAP_PRDY XDP_H_PRDYB ✅ TAP_PRDY routes off-page for JTAG probe ready signal.
D20 PMC_ACPRESENT PMC_ACPRESENT ✅ PMC_ACPRESENT is correctly connected with pull-up resistor for AC power present indication.
D22 ~PMC_SLP_S3 PMC_SLP_S3_L ✅ PMC_SLP_S3 is correctly connected to level shifter for sleep state S3 indication.
D26 PMC_SUSPWRDNACK SUSPWRDNACK ✅ PMC_SUSPWRDNACK is correctly connected with pull-up resistor and test point for suspend power down acknowledge.
F12 TAP_TDI XDP_H_TDI ✅ TAP_TDI is correctly connected with pull-up resistor for JTAG test data input.
F14 TAP_TMS XDP_H_TMS ✅ TAP_TMS is correctly connected with pull-up resistor for JTAG test mode select.
F16 ~TAP_PREQ XDP_H_PREQB ✅ TAP_PREQ routes off-page for JTAG probe request signal.
F18 ~PMC_SLP_S0IX PMC_SLP_S0IX ✅ PMC_SLP_S0IX is connected to test point only for sleep state S0IX indication.
F20 ~PMC_PLTRST PMC_PLTRST_R_V1P8 ✅ PMC_PLTRST is correctly connected to level shifter for platform reset signal translation.
F22 ~PMC_SLP_S4 PMC_SLP_S4_L ✅ PMC_SLP_S4 is correctly connected to level shifter for sleep state S4 indication.
F26 ~PMC_WAKE_PCIE_0 PMC_PCIE_WAKE_R ✅ PMC_WAKE_PCIE_0 is correctly connected with diode OR logic and pull-up for PCIe wake signaling.
G12 ~TAP_TRST XDP_H_TRSTB ✅ TAP_TRST is correctly connected with pull-down resistor for JTAG test reset.
G16 TAP_TDO XDP_H_TDO ✅ TAP_TDO routes off-page for JTAG test data output.
G18 ~PMC_SUS_STAT LPCPD_L ✅ PMC_SUS_STAT is connected to test point only for suspend status monitoring.
G24 PMC_SUSCLK0_G24 PMC_SUSCLK0 ✅ PMC_SUSCLK0 is correctly connected to level shifter with optional pull-up for suspend clock output.
J18 GPIO_S5_25 XDP_H_OBSDATA_A2 ✅ GPIO_S5_25 routes off-page as XDP_H_OBSDATA_A2 for debug observation data.
J20 GPIO_S5_14 GPIO_S514_J20 ✅ GPIO_S5_14 is correctly connected with pull-up resistor for general purpose I/O.
J24 GPIO_S5_17 GPIO_S5_17 ✅ GPIO_S5_17 is correctly connected to jumper header with pull-up for user-configurable option.
J26 ~PMC_PWRBTN PMC_PWRBTN ✅ PMC_PWRBTN is connected to power button logic with diode OR and optional pull-up.
K18 GPIO_S5_27 EXP_GPIO1 ✅ GPIO_S5_27 routes off-page as EXP_GPIO1 for expansion bus GPIO.
K20 GPIO_S5_28 EXP_GPIO2 ✅ GPIO_S5_28 routes off-page as EXP_GPIO2 for expansion bus GPIO.
K24 GPIO_S5_22 GPIO_D2_LED_CTRL ✅ GPIO_S5_22 routes off-page as GPIO_D2_LED_CTRL, likely used for LED control.
K26 ~PMC_BATLOW PMC_BATLOW ✅ PMC_BATLOW is correctly connected with pull-up resistor for battery low indication.
M18 GPIO_S5_26 XDP_H_OBSDATA_A3 ✅ GPIO_S5_26 routes off-page as XDP_H_OBSDATA_A3 for debug observation data.
M20 GPIO_S5_24 XDP_H_OBSDATA_A1 ✅ GPIO_S5_24 routes off-page as XDP_H_OBSDATA_A1 for debug observation data.
M22 GPIO_S5_29 EXP_GPIO3 ✅ GPIO_S5_29 routes off-page as EXP_GPIO3 for expansion bus GPIO.
M24 GPIO_S5_30 EXP_GPIO4 ✅ GPIO_S5_30 routes off-page as EXP_GPIO4 for expansion bus GPIO.
N24 GPIO_S5_23 XDP_H_OBSDATA_A0 ✅ GPIO_S5_23 routes off-page as XDP_H_OBSDATA_A0 for debug observation data.
N26 GPIO_RCOMP GPIO_RCOMP ✅ GPIO_RCOMP is correctly connected to 49.9 ohm compensation resistor to ground.
BA28 SIO_SPI_MISO SOC_SIO_SPI_MISO ✅ SIO_SPI_MISO routes off-page for Serial I/O SPI master in slave out.
BA34 ~SIO_UART1_RTS SIO_UART1_RTSB ✅ SIO_UART1_RTS routes off-page for UART1 request to send flow control.
AD9 RESERVED_AD9 ✅ RESERVED_AD9 is correctly left unconnected as specified.
AD10 RESERVED_AD10 ✅ RESERVED_AD10 is correctly left unconnected as specified.
AD12 RESERVED_AD12 ✅ RESERVED_AD12 is correctly left unconnected as specified.
AD13 ICLK_RCOMP ICLK_RCOMP ✅ ICLK_RCOMP is correctly connected to 47.5 ohm compensation resistor to ground.
AD14 ICLK_ICOMP ICLK_ICOMP ✅ ICLK_ICOMP is correctly connected to 4.02K ohm compensation resistor to ground.
BD32 ~SIO_UART2_RTS ✅ SIO_UART2_RTS is not connected, indicating UART2 flow control is not used.
BD34 SIO_UART2_TXD SIO_UART2_TXD ✅ SIO_UART2_TXD routes off-page for UART2 transmit data.
AF4 PCIE_CLKP_00 ✅ PCIE_CLKP_00 is not connected, indicating PCIe port 0 is not used.
AF6 PCIE_CLKN_00 ✅ PCIE_CLKN_00 is not connected, indicating PCIe port 0 is not used.
AF7 PCIE_CLKP_11 ✅ PCIE_CLKP_11 is not connected, indicating PCIe port 1 is not used.
AF9 PCIE_CLKN_11 ✅ PCIE_CLKN_11 is not connected, indicating PCIe port 1 is not used.
BF32 ~SIO_UART2_CTS ✅ SIO_UART2_CTS is not connected, indicating UART2 flow control is not used.
BF34 SIO_UART2_RXD SIO_UART2_RXD ✅ SIO_UART2_RXD routes off-page for UART2 receive data.
BG9 ~PMC_RSTBTN PMC_RSTBTN ✅ PMC_RSTBTN routes off-page for reset button input.
AH10 ICLK_OSCOUT XTAL25_OUT ✅ ICLK_OSCOUT (AH10) and ICLK_OSCIN (AH12) are correctly connected to a 25MHz crystal with appropriate load capacitors and feedback resistor.
AH12 ICLK_OSCIN XTAL25_IN ✅ ICLK_OSCOUT (AH10) and ICLK_OSCIN (AH12) are correctly connected to a 25MHz crystal with appropriate load capacitors and feedback resistor.
BH4 PMC_PLT_CLK_22 ✅ PMC_PLT_CLK_22 is not connected, indicating platform clock 2 is not used.
BH5 PMC_PLT_CLK_11 ✅ PMC_PLT_CLK_11 is not connected, indicating platform clock 1 is not used.
BH6 PMC_PLT_CLK_44 ✅ PMC_PLT_CLK_44 is not connected, indicating platform clock 4 is not used.
BH7 PMC_PLT_CLK_00 ✅ PMC_PLT_CLK_00 is not connected, indicating platform clock 0 is not used.
BH8 PMC_PLT_CLK_33 I2S_MCLK ✅ PMC_PLT_CLK_33 routes off-page as I2S_MCLK to provide master clock for I2S audio interface.
AK4 PCIE_CLKN_22 PCIE_CLK-N2 ✅ PCIE_CLKN_22 routes off-page to provide PCIe reference clock for port 2.
AK6 PCIE_CLKP_22 PCIE_CLK-P2 ✅ PCIE_CLKP_22 routes off-page to provide PCIe reference clock for port 2.
BJ9 PMC_PLT_CLK_55 ✅ PMC_PLT_CLK_55 is not connected, indicating platform clock 5 is not used.
AM4 PCIE_CLKN_33 mPCIE_REFCLK_N ✅ PCIE_CLKN_33 routes off-page to provide PCIe reference clock for mPCIE slot.
AM6 PCIE_CLKP_33 mPCIE_REFCLK_P ✅ PCIE_CLKP_33 routes off-page to provide PCIe reference clock for mPCIE slot.
AM9 RESERVED_AM9 ✅ RESERVED_AM9 is correctly left unconnected as specified.
AM10 RESERVED_AM10 ✅ RESERVED_AM10 is correctly left unconnected as specified.
AT32 SIO_PWM_11 SOC_PWM1 ✅ SIO_PWM_11 routes off-page, likely used for PWM control function.
AT34 RESERVED ✅ RESERVED pin is correctly left unconnected as specified.
AU32 SIO_PWM_00 SOC_PWM0 ✅ SIO_PWM_00 routes off-page, likely used for PWM control function.
AU34 SIO_UART1_RXD SIO_UART1_RXD ✅ SIO_UART1_RXD routes off-page for UART1 receive data.
AV32 ~SIO_SPI_CS SOC_SIO_SPI_CS1 ✅ SIO_SPI_CS routes off-page for Serial I/O SPI chip select.
AV34 SIO_UART1_TXD SIO_UART1_TXD ✅ SIO_UART1_TXD routes off-page for UART1 transmit data.
AY28 SIO_SPI_MOSI SOC_SIO_SPI_MOSI ✅ SIO_SPI_MOSI routes off-page for Serial I/O SPI master out slave in.
AY30 SIO_SPI_CLK SOC_SIO_SPI_CLK ✅ SIO_SPI_CLK routes off-page for Serial I/O SPI clock.
AY34 ~SIO_UART1_CTS SIO_UART1_CTSB ✅ SIO_UART1_CTS routes off-page for UART1 clear to send flow control.
U19 - NTS0104GU12 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VCCA +V1P8A ✅ VCCA supply pin correctly connected to +V1P8A (1.8V) rail, providing power for the A-side of the level shifter.
2 A1 PMC_PLTRST_R_V1P8 ✅ A1 pin correctly connected to PMC_PLTRST_R_V1P8 from CPU1 pin F20, translating the platform reset signal from 1.8V to 3.3V.
3 A2 PMC_SUSCLK0 ✅ A2 pin correctly connected to PMC_SUSCLK0 from CPU1 pin G24, translating the suspend clock signal from 1.8V to 3.3V.
4 A3 PMC_SLP_S4_L ✅ A3 pin correctly connected to PMC_SLP_S4_L from CPU1 pin F22, translating the S4 sleep state signal from 1.8V to 3.3V.
5 A4 PMC_SLP_S3_L ✅ A4 pin correctly connected to PMC_SLP_S3_L from CPU1 pin D22, translating the S3 sleep state signal from 1.8V to 3.3V.
6 GND GND ✅ GND pin correctly connected to the ground net.
7 B4 SLP_S3_L ✅ B4 pin correctly connected to SLP_S3_L, the 3.3V side of the S3 sleep state signal, pairing with A4.
8 B3 SLP_S4_L ✅ B3 pin correctly connected to SLP_S4_L, the 3.3V side of the S4 sleep state signal, pairing with A3.
9 B2 SUSCLK_3P3 ✅ B2 pin correctly connected to SUSCLK_3P3, the 3.3V side of the suspend clock signal, pairing with A2.
10 B1 PMC_PLTRST_L ✅ B1 pin correctly connected to PMC_PLTRST_L, the 3.3V side of the platform reset signal, pairing with A1.
11 VCCB PWR_BUF1 ✅ VCCB supply pin correctly connected to PWR_BUF1, which is connected through R26 (0-ohm) to +3VSB, providing 3.3V standby power for the B-side.
12 OE PMC_OE ✅ OE pin correctly connected to PMC_OE with a 2.2K pull-up resistor (R57) to +V1P8A, enabling the level shifter.
Y1 - 145-0004789 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 BRTCX2 ✅ Crystal pin connected to CPU RTC oscillator pin X2 with proper load capacitor and feedback resistor.
2 2 BRTCX1 ✅ Crystal pin connected to CPU RTC oscillator pin X1 with proper load capacitor and feedback resistor.
D5 - BAT754C ✅

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Pin Designator Pin Name Net Correct? Analysis
A1 A1 +PS_3VSB ✅ Anode 1 connected to 3.3V standby rail for primary RTC power through OR-ing diode.
A2 A2 +VBAT_R ✅ Anode 2 connected to battery voltage for backup RTC power through OR-ing diode.
C C +RTCVCC ✅ Common cathode output providing OR-ed power to RTC circuit from either main power or battery.
BH1 - 353-0003073 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 P1 +VBAT ✅ Positive battery terminal connected to +VBAT net through current limiting resistor to OR-ing diode for RTC backup power.
2 P2 +VBAT ✅ Redundant positive battery terminal connected to +VBAT net, same as pin 1.
3 N GND ✅ Negative battery terminal correctly connected to ground.
Y2 - 145-0004792 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 XTAL25_IN ✅ Crystal input pin correctly connected to CPU oscillator input (ICLK_OSCIN) through net XTAL25_IN with proper load capacitor C175 (27pF) to ground and feedback resistor R188 (1M) to pin 3.
2 2 GND ✅ Ground pin correctly connected to GND net, standard for 4-pin crystal packages.
3 3 XTAL25_OUT ✅ Crystal output pin correctly connected to CPU oscillator output (ICLK_OSCOUT) through net XTAL25_OUT with proper load capacitor C176 (27pF) to ground.
4 4 GND ✅ Ground pin correctly connected to GND net, standard for 4-pin crystal packages.
D3 - BAT54A-S ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 PMC_PCIE_WAKE ✅ Both anode pins are connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27 (2.2K). This parallels the two diodes in the package.
2 2 PMC_PCIE_WAKE ✅ Both anode pins are connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27 (2.2K). This parallels the two diodes in the package.
3 3 PMC_PCIE_WAKE_R ✅ Cathode pin connected to PMC_PCIE_WAKE_R net, which connects to CPU1 pin F26 and is pulled up to +V1P8A through R253 (1K). This creates a unidirectional level shifter allowing the CPU to pull the wake signal low while protecting it from the higher +3VSB voltage.
D10 - BAT754C ✅

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Pin Designator Pin Name Net Correct? Analysis
A1 A1 3VSB_OK ✅ Anode 1 connected to 3VSB_OK net, which is pulled up to +3VSB through R162 (1K). This allows the power supply good signal to control PS_OUT_L.
A2 A2 PMC_PWRBTN ✅ Anode 2 connected to PMC_PWRBTN net, which connects to CPU1 pin J26 (active-low power button signal). This allows the power button to control PS_OUT_L.
C C PS_OUT_L ✅ Common cathode connected to PS_OUT_L net. This output is pulled low when either 3VSB_OK or PMC_PWRBTN goes low, implementing an OR gate for power control.
J7 - HDR_2POS_DUAL_TIN ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GPIO_S5_17 ✅ Connected to GPIO_S5_17 from the CPU, serving as the signal pin of the jumper header.
2 2 GND ✅ Connected to GND, providing the ground reference for the jumper.
R183 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Connected to +V1P8S supply rail, providing the pull-up voltage source.
2 2 GPIO_S5_17 ✅ Connected to GPIO_S5_17, completing the pull-up resistor circuit.
CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator Pin Name Net Correct? Analysis
A7 USB_HSIC_RCOMP USB_HSIC0_RCOMP ✅ USB_HSIC_RCOMP is correctly connected to a 45.3 ohm resistor to ground for USB HSIC impedance calibration.
B4 USB_HSIC0_DATA ✅ USB_HSIC0_DATA and USB_HSIC0_STROBE are not connected, indicating USB HSIC port 0 is not used in this design.
B5 USB_HSIC0_STROBE ✅ USB_HSIC0_DATA and USB_HSIC0_STROBE are not connected, indicating USB HSIC port 0 is not used in this design.
B12 GPIO_S5_43 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
G2 GPIO_S5_31 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
H3 GPIO_S5_42 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
J3 GPIO_S5_40 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
K2 GPIO_S5_34 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
K3 GPIO_S5_35 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
L1 GPIO_S5_33 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
L3 GPIO_S5_39 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
M2 GPIO_S5_36 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
M3 GPIO_S5_32 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
N3 GPIO_S5_37 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
P2 GPIO_S5_38 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
P3 GPIO_S5_41 ✅ GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design.
B20 ~USB_OC_11 SOC_USB_HOST_OC1 ✅ USB_OC[1]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection.
C7 USB_RCOMPI USB_RCOMP ✅ USB_RCOMPI and USB_RCOMPO are correctly connected together to a 45.3 ohm resistor to ground for USB 2.0 impedance calibration.
D6 USB_RCOMPO USB_RCOMP ✅ USB_RCOMPI and USB_RCOMPO are correctly connected together to a 45.3 ohm resistor to ground for USB 2.0 impedance calibration.
C20 ~USB_OC_00 SOC_USB_HOST_OC0 ✅ USB_OC[0]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection.
D2 USB_HSIC1_STROBE ✅ USB_HSIC1_STROBE and USB_HSIC1_DATA are not connected, indicating USB HSIC port 1 is not used in this design.
E2 USB_HSIC1_DATA ✅ USB_HSIC1_STROBE and USB_HSIC1_DATA are not connected, indicating USB HSIC port 1 is not used in this design.
D4 USB3_RXP0 USB3_RXP0 ✅ USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation.
E3 USB3_RXN0 USB3_RXN0 ✅ USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation.
K6 USB3_TXP0 USB3_TXP0 ✅ USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation.
K7 USB3_TXN0 USB3_TXN0 ✅ USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation.
D10 ICLK_USB_TERM_1 ICLK_USB_TERM_0 ✅ ICLK_USB_TERM_1 and ICLK_USB_TERMN are correctly connected to 1K ohm resistors to ground for USB clock termination.
F10 ICLK_USB_TERMN ICLK_USB_TERM_1 ✅ ICLK_USB_TERM_1 and ICLK_USB_TERMN are correctly connected to 1K ohm resistors to ground for USB clock termination.
G14 USB_DN1 USB_DN1 ✅ USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets.
J14 USB_DP1 USB_DP1 ✅ USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets.
K16 USB_DN0 USB_DN0 ✅ USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets.
M16 USB_DP0 USB_DP0 ✅ USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets.
H4 RESERVED_H4 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
H5 RESERVED_H5 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
H7 RESERVED_H7 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
H8 RESERVED_H8 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
M10 RESERVED_M10 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
M4 RESERVED_M4 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
M6 RESERVED_M6 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
M7 RESERVED_M7 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
M9 RESERVED_M9 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
P10 RESERVED_P10 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
P12 RESERVED_P12 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
P6 RESERVED_P6 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
P7 RESERVED_P7 ✅ Reserved pins are correctly left unconnected as per datasheet requirements.
H10 USB_DN3 ✅ USB_DN3 and USB_DP3 are not connected, indicating USB port 3 is not used in this design.
K10 USB_DP3 ✅ USB_DN3 and USB_DP3 are not connected, indicating USB port 3 is not used in this design.
J12 USB_DN2 USB_HOST_DN ✅ USB 2.0 differential pair for port 2 (USB_DN2, USB_DP2) is connected to USB_HOST_DN and USB_HOST_DP nets.
K12 USB_DP2 USB_HOST_DP ✅ USB 2.0 differential pair for port 2 (USB_DN2, USB_DP2) is connected to USB_HOST_DN and USB_HOST_DP nets.
M12 USB3_REXT0 USB3_REXT0 ✅ USB3_REXT0 is correctly connected to a 1.24K ohm resistor to ground for USB 3.0 impedance calibration.
M13 USB_PLL_MON USB_PLL_MON ✅ USB_PLL_MON is correctly connected to a test point for USB PLL monitoring and debug.
BC12 GPIO_S0_SC_56 GPIO_S0_SC_56 ✅ GPIO_S0_SC_56 is connected to net GPIO_S0_SC_56 for GPIO functionality.
BC14 GPIO_S0_SC_58 HDMI_CEC ✅ GPIO_S0_SC_58 is connected to net HDMI_CEC for HDMI Consumer Electronics Control functionality.
BC16 GPIO_S0_SC_61 PCU_UART3_RXD ✅ GPIO_S0_SC_61 is correctly configured as UART3 receive and connected to level shifter U6 for debug serial input.
BD12 GPIO_S0_SC_55 GPIO_S0_SC_55 ✅ GPIO_S0_SC_55 is correctly connected to a test point for GPIO monitoring.
BD14 GPIO_S0_SC_57 PCU_UART3_TXD ✅ GPIO_S0_SC_57 is correctly configured as UART3 transmit and connected to level shifter U6 for debug serial output.
BD16 GPIO_S0_SC_60 ✅ GPIO_S0_SC_60 is not connected, indicating this GPIO is not used in this design.
BF14 GPIO_S0_SC_59 ✅ GPIO_S0_SC_59 is not connected, indicating this GPIO is not used in this design.
BF18 LPC_RCOMP LPC_RCOMP ✅ LPC_RCOMP is correctly connected to a 49.9 ohm resistor to ground for LPC bus impedance calibration.
BF27 SIO_I2C4_DATA ✅ SIO_I2C4_DATA and SIO_I2C4_CLK are not connected, indicating I2C4 interface is not used in this design.
BG27 SIO_I2C4_CLK ✅ SIO_I2C4_DATA and SIO_I2C4_CLK are not connected, indicating I2C4 interface is not used in this design.
BG11 ~PCU_SMB_ALERT PCU_SMB_ALERT ✅ PCU_SMB_ALERT# is correctly connected with a 10K pull-up to +V1P8S and routed through a 0 ohm resistor to LAN-SMB-ALERT#.
BG12 PCU_SMB_DATA PCU_SMB_DATA ✅ PCU_SMB_DATA is correctly connected with a 2.2K pull-up to +V1P8S and routed to level shifter U5 for SMBus data signal.
BG13 ILB_LPC_SERIRQ ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BG14 ILB_LPC_AD_33 ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BG15 ILB_LPC_CLK_00 ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BG16 ~ILB_LPC_CLKRUN ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BG17 ~ILB_LPC_FRAME ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BH14 ILB_LPC_CLK_11 ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BH16 ILB_LPC_AD_00 ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BJ13 ILB_LPC_AD_22 ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BJ17 ILB_LPC_AD_11 ✅ LPC interface pins are not connected, indicating the LPC bus is not used in this design.
BG23 SIO_I2C0_CLK ✅ SIO_I2C0_CLK and SIO_I2C0_DATA are not connected, indicating I2C0 interface is not used in this design.
BH22 SIO_I2C0_DATA ✅ SIO_I2C0_CLK and SIO_I2C0_DATA are not connected, indicating I2C0 interface is not used in this design.
BG24 SIO_I2C1_DATA SIO_I2C1_SDA ✅ SIO_I2C1_DATA and SIO_I2C1_CLK are correctly connected to test points TP6 and TP5 for I2C monitoring.
BH24 SIO_I2C1_CLK SIO_I2C1_SCL ✅ SIO_I2C1_DATA and SIO_I2C1_CLK are correctly connected to test points TP6 and TP5 for I2C monitoring.
BG25 SIO_I2C2_DATA ✅ SIO_I2C2_DATA and SIO_I2C2_CLK are not connected, indicating I2C2 interface is not used in this design.
BJ25 SIO_I2C2_CLK ✅ SIO_I2C2_DATA and SIO_I2C2_CLK are not connected, indicating I2C2 interface is not used in this design.
BG26 SIO_I2C3_DATA ✅ SIO_I2C3_DATA and SIO_I2C3_CLK are not connected, indicating I2C3 interface is not used in this design.
BH26 SIO_I2C3_CLK ✅ SIO_I2C3_DATA and SIO_I2C3_CLK are not connected, indicating I2C3 interface is not used in this design.
BG28 SIO_I2C5_CLK SI0_I2C5_SCL ✅ SIO_I2C5_CLK and SIO_I2C5_DATA are correctly connected with 22 ohm series resistors to I2C5_SCL and I2C5_SDA nets.
BH28 SIO_I2C5_DATA SI0_I2C5_SDA ✅ SIO_I2C5_CLK and SIO_I2C5_DATA are correctly connected with 22 ohm series resistors to I2C5_SCL and I2C5_SDA nets.
BG29 SIO_I2C6_CLK SI0_I2C6_SCL ✅ SIO_I2C6_CLK and SIO_I2C6_DATA are correctly connected with 22 ohm series resistors to I2C6_SCL and I2C6_SDA nets.
BJ29 SIO_I2C6_DATA SI0_I2C6_SDA ✅ SIO_I2C6_CLK and SIO_I2C6_DATA are correctly connected with 22 ohm series resistors to I2C6_SCL and I2C6_SDA nets.
BG30 GPIO_S0_SC_093 TP10_NET ✅ GPIO_S0_SC_093 and GPIO_S0_SC_092 are intentionally grounded through 0 ohm resistors with test points, as indicated by schematic notes.
BH30 GPIO_S0_SC_092 TP9_NET ✅ GPIO_S0_SC_093 and GPIO_S0_SC_092 are intentionally grounded through 0 ohm resistors with test points, as indicated by schematic notes.
BH10 PCU_SMB_CLK PCU_SMB_CLK ✅ PCU_SMB_CLK is correctly connected with a 2.2K pull-up to +V1P8S and routed to level shifter U5 for SMBus clock signal.
BH12 ILB_8254_SPKR ILB_8254_SPKR ✅ ILB_8254_SPKR is connected to net ILB_8254_SPKR for PC speaker output functionality.
R48 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 BUF2_PWR ✅ Connected to BUF2_PWR, which supplies power to the high-voltage side of level shifter U5.
2 2 +VCC3 ✅ Connected to +VCC3 (3.3V supply), providing power through the 0 ohm resistor to BUF2_PWR.
R44 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DDR_SMB_CLK ✅ Connected to DDR_SMB_CLK, providing pull-up for the SMBus clock line on the 3.3V side.
2 2 +VCC3 ✅ Connected to +VCC3 (3.3V supply), providing the pull-up voltage for DDR_SMB_CLK.
R47 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DDR_SMB_DATA ✅ Connected to DDR_SMB_DATA, providing pull-up for the SMBus data line on the 3.3V side.
2 2 +VCC3 ✅ Connected to +VCC3 (3.3V supply), providing the pull-up voltage for DDR_SMB_DATA.
R45 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_CLK.
2 2 PCU_SMB_CLK ✅ Connected to PCU_SMB_CLK, providing pull-up for the SMBus clock line on the 1.8V side.
R177 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_DATA.
2 2 PCU_SMB_DATA ✅ Connected to PCU_SMB_DATA, providing pull-up for the SMBus data line on the 1.8V side.
R49 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_BUFF_ENB.
2 2 PCU_SMB_BUFF_ENB ✅ Connected to PCU_SMB_BUFF_ENB, providing pull-up to enable the level shifter U5 by default.
R75 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_ALERT.
2 2 PCU_SMB_ALERT ✅ Connected to PCU_SMB_ALERT, providing pull-up for the SMBus alert signal.
R840 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DDR_SMB_DATA ✅ Connected to DDR_SMB_DATA, allowing the SMBus data line to be shared with LAN interface.
2 2 LAN-SMB-DATA ✅ Connected to LAN-SMB-DATA, extending the SMBus data line to the LAN interface.
R841 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DDR_SMB_CLK ✅ Connected to DDR_SMB_CLK, allowing the SMBus clock line to be shared with LAN interface.
2 2 LAN-SMB-CLK ✅ Connected to LAN-SMB-CLK, extending the SMBus clock line to the LAN interface.
R842 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN-SMB-ALERT# ✅ Connected to LAN-SMB-ALERT#, extending the SMBus alert line to the LAN interface.
2 2 PCU_SMB_ALERT ✅ Connected to PCU_SMB_ALERT, allowing the SMBus alert line to be shared with LAN interface.
U5 - NTS0102GT ✅

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Pin Designator Pin Name Net Correct? Analysis
1 B2 DDR_SMB_CLK ✅ B2 pin correctly connected to DDR_SMB_CLK for 3.3V side clock signal translation.
2 GND GND ✅ GND pin correctly connected to ground plane.
3 VCCA +V1P8S ✅ VCCA pin correctly connected to +V1P8S (1.8V) for A-side voltage reference.
4 A2 PCU_SMB_CLK ✅ A2 pin correctly connected to PCU_SMB_CLK for 1.8V side clock signal translation.
5 A1 PCU_SMB_DATA ✅ A1 pin correctly connected to PCU_SMB_DATA for 1.8V side data signal translation.
6 OE PCU_SMB_BUFF_ENB ✅ OE pin connected to PCU_SMB_BUFF_ENB with pull-up to +V1P8S, keeping the level shifter enabled.
7 VCCB BUF2_PWR ✅ VCCB pin correctly connected to BUF2_PWR (3.3V via R48) for B-side voltage reference.
8 B1 DDR_SMB_DATA ✅ B1 pin correctly connected to DDR_SMB_DATA for 3.3V side data signal translation.
J4 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pin 1 correctly connected to GND for the debug serial connector ground reference.
2 2 ✅ Pins 2, 3, and 6 are not connected, which is appropriate for a minimal 3-wire UART interface (GND, TX, RX).
3 3 ✅ Pins 2, 3, and 6 are not connected, which is appropriate for a minimal 3-wire UART interface (GND, TX, RX).
6 6 ✅ Pins 2, 3, and 6 are not connected, which is appropriate for a minimal 3-wire UART interface (GND, TX, RX).
4 4 DBG_UART3_RXD ✅ Pin 4 correctly connected to DBG_UART3_RXD, which is the receive input to the board from the external serial cable.
5 5 DBG_UART3_TXD_R ✅ Pin 5 correctly connected to DBG_UART3_TXD_R, which is the transmit output from the board to the external serial cable.
R51 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 BUF3_PWR ✅ 0-ohm resistor correctly connecting +3VSB to BUF3_PWR, providing 3.3V standby power to the level translator's B-side.
2 2 +3VSB ✅ 0-ohm resistor correctly connecting +3VSB to BUF3_PWR, providing 3.3V standby power to the level translator's B-side.
R819 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DBG_UART3_TXD ✅ 330-ohm series resistor correctly placed in the UART transmit path for protection against shorts and ESD events.
2 2 DBG_UART3_TXD_R ✅ 330-ohm series resistor correctly placed in the UART transmit path for protection against shorts and ESD events.
R50 ❌

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ❌
R50 is a 100K pull-down resistor on the UART RX line. This is incorrect - UART signals should idle high (mark state), so this should be a pull-up resistor to +3VSB or BUF3_PWR instead of a pull-down to GND.
  • Pin 1 is connected to net GND (from schematic)
  • Pin 2 is connected to net DBG_UART3_RXD (from schematic)
  • R50 is a 100K-ohm resistor (part number 110-0001859) configured as a pull-down (from schematic)
  • DBG_UART3_RXD connects to U6 pin 8 (B1) and J4 pin 4 (from schematic)
  • In UART protocol, the idle state is logic high (mark state), and the start bit is logic low (reasoning)
  • When no cable is connected to the debug port, the RX line should be pulled high to indicate the proper idle state (reasoning)
  • A pull-down resistor causes the line to be low when nothing is connected, which violates the UART idle state requirement (reasoning)
  • A low RX line when disconnected could be interpreted by the UART receiver as a continuous start bit or break condition, potentially causing spurious interrupts or errors (reasoning)
  • When a cable is connected and transmitting logic high, the pull-down resistor fights against the external device's driver, though the 100K value is weak enough that this may not cause immediate functional problems (reasoning)
  • R50 should be changed to a pull-up resistor to +3VSB or BUF3_PWR (3.3V) instead of a pull-down to GND to maintain the correct UART idle state (reasoning)
  • The 100K ohm value is appropriate for a UART pull resistor, but the polarity is incorrect (reasoning)
2 2 DBG_UART3_RXD ❌
R50 is a 100K pull-down resistor on the UART RX line. This is incorrect - UART signals should idle high (mark state), so this should be a pull-up resistor to +3VSB or BUF3_PWR instead of a pull-down to GND.
  • Pin 1 is connected to net GND (from schematic)
  • Pin 2 is connected to net DBG_UART3_RXD (from schematic)
  • R50 is a 100K-ohm resistor (part number 110-0001859) configured as a pull-down (from schematic)
  • DBG_UART3_RXD connects to U6 pin 8 (B1) and J4 pin 4 (from schematic)
  • In UART protocol, the idle state is logic high (mark state), and the start bit is logic low (reasoning)
  • When no cable is connected to the debug port, the RX line should be pulled high to indicate the proper idle state (reasoning)
  • A pull-down resistor causes the line to be low when nothing is connected, which violates the UART idle state requirement (reasoning)
  • A low RX line when disconnected could be interpreted by the UART receiver as a continuous start bit or break condition, potentially causing spurious interrupts or errors (reasoning)
  • When a cable is connected and transmitting logic high, the pull-down resistor fights against the external device's driver, though the 100K value is weak enough that this may not cause immediate functional problems (reasoning)
  • R50 should be changed to a pull-up resistor to +3VSB or BUF3_PWR (3.3V) instead of a pull-down to GND to maintain the correct UART idle state (reasoning)
  • The 100K ohm value is appropriate for a UART pull resistor, but the polarity is incorrect (reasoning)
R52 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LSENB ✅ 2.2K-ohm pull-up resistor on LSENB signal to +V1P8S, keeping the level translator's OE pin high by default to enable the buffer.
2 2 +V1P8S ✅ 2.2K-ohm pull-up resistor on LSENB signal to +V1P8S, keeping the level translator's OE pin high by default to enable the buffer.
U6 - NTS0102GT ✅

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Pin Designator Pin Name Net Correct? Analysis
1 B2 DBG_UART3_TXD ✅ B2 pin correctly connected to DBG_UART3_TXD, which routes through series resistor R819 to connector J4 pin 5. This translates the CPU's 1.8V UART TX signal to 3.3V for the external debug connector.
2 GND GND ✅ GND pin correctly connected to ground plane.
3 VCCA +V1P8S ✅ VCCA pin correctly connected to +V1P8S (1.8V supply), providing reference voltage for the A-side (CPU side) of the level translator.
4 A2 PCU_UART3_TXD ✅ A2 pin correctly connected to PCU_UART3_TXD from CPU GPIO_S0_SC_57. This is the low-voltage side of the UART transmit path.
5 A1 PCU_UART3_RXD ✅ A1 pin correctly connected to PCU_UART3_RXD from CPU GPIO_S0_SC_61. This is the low-voltage side of the UART receive path.
6 OE LSENB ✅ OE pin connected to LSENB with 2.2K pull-up to +V1P8S. The signal name suggests active-low enable, but the pull-up configuration indicates active-high operation, which would keep the buffer enabled by default. Without datasheet confirmation, this appears correct assuming typical active-high OE behavior.
7 VCCB BUF3_PWR ✅ VCCB pin correctly connected to BUF3_PWR, which is tied to +3VSB (3.3V standby) through 0-ohm resistor R51. This provides the reference voltage for the B-side (connector side) of the level translator.
8 B1 DBG_UART3_RXD ✅ B1 pin correctly connected to DBG_UART3_RXD, which routes to connector J4 pin 4 and has a 100K pull-down resistor R50. This translates the external 3.3V UART RX signal to 1.8V for the CPU.
R269 - 110-0001967 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SI0_I2C5_SDA ✅ 22 ohm series resistor on I2C5 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line.
2 2 I2C5_SDA ✅ 22 ohm series resistor on I2C5 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line.
R12 - 110-0001967 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SI0_I2C6_SCL ✅ 22 ohm series resistor on I2C6 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line.
2 2 I2C6_SCL ✅ 22 ohm series resistor on I2C6 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line.
R11 - 110-0001967 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SI0_I2C6_SDA ✅ 22 ohm series resistor on I2C6 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line.
2 2 I2C6_SDA ✅ 22 ohm series resistor on I2C6 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line.
R270 - 110-0001967 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SI0_I2C5_SCL ✅ 22 ohm series resistor on I2C5 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line.
2 2 I2C5_SCL ✅ 22 ohm series resistor on I2C5 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line.
R84 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ✅ Pull-up resistor connection to +V1P8A power rail for USB overcurrent signal SOC_USB_HOST_OC0.
2 2 SOC_USB_HOST_OC0 ✅ Connected to SOC_USB_HOST_OC0, an active-low USB overcurrent signal from CPU1 pin C20.
R97 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ✅ Pull-up resistor connection to +V1P8A power rail for USB overcurrent signal SOC_USB_HOST_OC1.
2 2 SOC_USB_HOST_OC1 ✅ Connected to SOC_USB_HOST_OC1, an active-low USB overcurrent signal from CPU1 pin B20.
TP16 - 999-0000002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 TP10_NET ✅ DNI test point on net TP10_NET providing access to GPIO_S0_SC_093 signal for testing and debugging.
R243 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 TP9_NET ✅ 0-ohm resistor connecting GPIO_S0_SC_092 (CPU1 pin BH30) to ground through TP9_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'.
2 2 GND ✅ 0-ohm resistor connecting GPIO_S0_SC_092 (CPU1 pin BH30) to ground through TP9_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'.
TP13 - 999-0000002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 TP9_NET ✅ DNI test point on net TP9_NET providing access to GPIO_S0_SC_092 signal for testing and debugging.
R261 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 TP10_NET ✅ 0-ohm resistor connecting GPIO_S0_SC_093 (CPU1 pin BG30) to ground through TP10_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'.
2 2 GND ✅ 0-ohm resistor connecting GPIO_S0_SC_093 (CPU1 pin BG30) to ground through TP10_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'.
CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator Pin Name Net Correct? Analysis
A48 DRAM_VDD_S4 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
AK38 DRAM_VDD_S4_AK38 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
AM38 DRAM_VDD_S4_AM38 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
AV41 DRAM_VDD_S4_AV41 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
AV42 DRAM_VDD_S4_AV42 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
BB46 DRAM_VDD_S4_BB46 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
BD49 DRAM_VDD_S4_BD49 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
BD52 DRAM_VDD_S4_BD52 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
BD53 DRAM_VDD_S4_BD53 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
BF44 DRAM_VDD_S4_BF44 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
BG51 DRAM_VDD_S4_BG51 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
BJ48 DRAM_VDD_S4_BJ48 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
C51 DRAM_VDD_S4_C51 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
D44 DRAM_VDD_S4_D44 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
F49 DRAM_VDD_S4_F49 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
F52 DRAM_VDD_S4_F52 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
F53 DRAM_VDD_S4_F53 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
H46 DRAM_VDD_S4_H46 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
M41 DRAM_VDD_S4_M41 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
M42 DRAM_VDD_S4_M42 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
V38 DRAM_VDD_S4_V38 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
Y38 DRAM_VDD_S4_Y38 +VDIMM ✅ DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors.
N28 CORE_VSS_SENSE_N28 VSS_SENSE ✅ CORE_VSS_SENSE is a ground sense pin for voltage regulation feedback. It is connected to the VSS_SENSE net for remote ground sensing.
P28 CORE_VCC_SENSE_P28 VCC_SENSE ✅ CORE_VCC_SENSE is a voltage sense pin for SVID regulation feedback. It is connected to the VCC_SENSE net for remote sensing of the core voltage.
AA22 TP2_CORE_VCC_S0IX $9N615 ✅ TP2_CORE_VCC_S0IX is a test point pin for monitoring core voltage. It is connected to test point TP2 which is marked DNI.
AA24 UNCORE_VNN_S3_AA24 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AC22 UNCORE_VNN_S3_AC22 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AC24 UNCORE_VNN_S3_AC24 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AD22 UNCORE_VNN_S3_AD22 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AD24 UNCORE_VNN_S3_AD24 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AF22 UNCORE_VNN_S3_AF22 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AF24 UNCORE_VNN_S3_AF24 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AG22 UNCORE_VNN_S3_AG22 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AG24 UNCORE_VNN_S3_AG24 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AJ22 UNCORE_VNN_S3_AJ22 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AJ24 UNCORE_VNN_S3_AJ24 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AK22 UNCORE_VNN_S3_AK22 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AK24 UNCORE_VNN_S3_AK24 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AK25 UNCORE_VNN_S3_AK25 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AK27 UNCORE_VNN_S3_AK27 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AK29 UNCORE_VNN_S3_AK29 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AK30 UNCORE_VNN_S3_AK30 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AK32 UNCORE_VNN_S3_AK32 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AM22 UNCORE_VNN_S3_AM22 +VGFX ✅ UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling.
AA27 CORE_VCC_S0IX_AA27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AA29 CORE_VCC_S0IX_AA29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AA30 CORE_VCC_S0IX_AA30 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AC27 CORE_VCC_S0IX_AC27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AC29 CORE_VCC_S0IX_AC29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AC30 CORE_VCC_S0IX_AC30 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AD27 CORE_VCC_S0IX_AD27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AD29 CORE_VCC_S0IX_AD29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AD30 CORE_VCC_S0IX_AD30 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AF27 CORE_VCC_S0IX_AF27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AF29 CORE_VCC_S0IX_AF29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AG27 CORE_VCC_S0IX_AG27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AG29 CORE_VCC_S0IX_AG29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
AG30 CORE_VCC_S0IX_AG30 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
P26 CORE_VCC_S0IX_P26 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
P27 CORE_VCC_S0IX_P27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
U27 CORE_VCC_S0IX_U27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
U29 CORE_VCC_S0IX_U29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
V27 CORE_VCC_S0IX_V27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
V29 CORE_VCC_S0IX_V29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
V30 CORE_VCC_S0IX_V30 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
Y27 CORE_VCC_S0IX_Y27 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
Y29 CORE_VCC_S0IX_Y29 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
Y30 CORE_VCC_S0IX_Y30 +VCORE ✅ CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling.
BB8 UNCORE_VNN_SENSE VCCGT_SENSE ✅ UNCORE_VNN_SENSE is a voltage sense pin for SVID regulation feedback. It is connected to the VCCGT_SENSE net for remote sensing of the uncore voltage.
AD38 DRAM_VDD_S4_AD38 DRAM_VDD_CLK ✅ DRAM_VDD_S4 clock power pins supply power to the DDR3L clock circuits. These pins are correctly connected to DRAM_VDD_CLK, which is filtered from +VDIMM through a 0-ohm jumper.
AF38 DRAM_VDD_S4_AF38 DRAM_VDD_CLK ✅ DRAM_VDD_S4 clock power pins supply power to the DDR3L clock circuits. These pins are correctly connected to DRAM_VDD_CLK, which is filtered from +VDIMM through a 0-ohm jumper.
AF30 TP_CORE_V1P05_S4 $9N613 ✅ TP_CORE_V1P05_S4 is a test point pin for monitoring 1.05V core rail. It is connected to test point TP1 which is marked DNI.
R275 - 110-0002124 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM ✅ Connected to +VDIMM, the main DRAM voltage supply rail. This is the source side of the 0-ohm jumper.
2 2 DRAM_VDD_CLK ✅ Connected to DRAM_VDD_CLK, a separate DRAM voltage rail for clock circuitry. This is the load side of the 0-ohm jumper.
C292 - 123-0001066 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND. Standard ground connection for decoupling capacitor.
2 2 DRAM_VDD_CLK ✅ Connected to DRAM_VDD_CLK. Provides bulk decoupling for the DRAM clock voltage rail.
C291 - 123-0001056 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND. Standard ground connection for decoupling capacitor.
2 2 DRAM_VDD_CLK ✅ Connected to DRAM_VDD_CLK. Provides high-frequency decoupling for the DRAM clock voltage rail.
CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator Pin Name Net Correct? Analysis
AC32 CORE_V1P05_S3_AC32 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
Y32 CORE_V1P05_S3_Y32 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
AA33 CORE_V1P05_S3_AA33 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
AF33 CORE_V1P05_S3_AF33 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
AG33 CORE_V1P05_S3_AG33 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
AG35 CORE_V1P05_S3_AG35 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
U33 CORE_V1P05_S3_U33 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
U35 CORE_V1P05_S3_U35 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
V33 CORE_V1P05_S3_V33 +V1P0S ❌
CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.
  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)
A3 VSS_A3_A3 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
A5 VSS_A5_A5 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
A6 VSS_A6_A6 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
A49 VSS_A49_A49 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
A51 VSS_A51_A51 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
A52 VSS_A52_A52 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
AN16 VSSA_AN16 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
B2 VSS_B2_B2 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
B52 VSS_B52_B52 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
B53 VSS_B53_B53 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BE1 VSS_BE1_BE1 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BE53 VSS_BE53_BE53 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BG1 VSS_BG1_BG1 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BG53 VSS_BG53_BG53 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BH1 VSS_BH1_BH1 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BH2 VSS_BH2_BH2 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BH52 VSS_BH52_BH52 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BH53 VSS_BH53_BH53 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BJ2 VSS_BJ2_BJ2 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BJ3 VSS_BJ3_BJ3 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BJ5 VSS_BJ5_BJ5 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BJ49 VSS_BJ49_BJ49 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BJ51 VSS_BJ51_BJ51 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
BJ52 VSS_BJ52_BJ52 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
C1 VSS_C1_C1 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
C53 VSS_C53_C53 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
E1 VSS_E1_E1 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
E53 VSS_E53_E53 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
U16 USB_VSSA_U16 GND ✅ Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC.
B6 UNCORE_V1P0_G3_B6 +V1P0A ✅ UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided.
C5 UNCORE_V1P0_G3_C5 +V1P0A ✅ UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided.
U22 UNCORE_V1P0_G3_U22 +V1P0A ✅ UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided.
V22 UNCORE_V1P0_G3_V22 +V1P0A ✅ UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided.
C3 USB3_V1P0_G3_C3 +V1P0A ✅ UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided.
Y19 USB3_V1P0_G3_Y19 +V1P0A ✅ UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided.
F1 RESERVED_F1 $10N1595 ✅ RESERVED_F1 pin connected to test point TP4 on net $10N1595. Connection to test point is acceptable for reserved pin.
M14 USB_V1P0_S3_M14 +V1P0S ✅ USB_V1P0_S3 pins correctly connected to +V1P0S rail. Powers USB digital logic with adequate decoupling.
U18 USB_V1P0_S3_U18 +V1P0S ✅ USB_V1P0_S3 pins correctly connected to +V1P0S rail. Powers USB digital logic with adequate decoupling.
U19 USB_V1P0_S3_U19 +V1P0S ✅ USB_V1P0_S3 pins correctly connected to +V1P0S rail. Powers USB digital logic with adequate decoupling.
N18 USB_V3P3_G3_N18 +3VSB ✅ USB_V3P3_G3 and PCU_V3P3_G3 pins correctly connected to +3VSB rail (3.3V standby supply). Adequate decoupling provided.
P18 USB_V3P3_G3_P18 +3VSB ✅ USB_V3P3_G3 and PCU_V3P3_G3 pins correctly connected to +3VSB rail (3.3V standby supply). Adequate decoupling provided.
N22 PCU_V3P3_G3_N22 +3VSB ✅ USB_V3P3_G3 and PCU_V3P3_G3 pins correctly connected to +3VSB rail (3.3V standby supply). Adequate decoupling provided.
N20 USB_V1P8_G3_N20 +V1P8A ✅ USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided.
U24 UNCORE_V1P8_G3_U24 +V1P8A ✅ USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided.
U25 PMU_V1P8_G3_U25 +V1P8A ✅ USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided.
V25 PCU_V1P8_G3_V25 +V1P8A ✅ USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided.
AA18 UNCORE_V1P8_G3_AA18 +V1P8A ✅ USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided.
P22 RTC_VCC_P22 +RTCVCC ✅ RTC_VCC pin correctly connected to +RTCVCC rail (RTC battery backup supply). Proper decoupling provided.
V18 USB_HSIC_V1P24_G3_V18 +V1P0A ✅ USB_HSIC_V1P24_G3 pin connected to +V1P0A rail (1.0V instead of 1.24V). This is correct per datasheet guidance when USB HSIC is not used.
V32 SVID_V1P0_S3_V32 +V1P0S ✅ SVID_V1P0_S3 pin correctly connected to +V1P0S rail. Powers SVID interface logic with proper decoupling.
AD16 VSS_AD16 VCC_VSS_V1P2 ✅ VSS pins connected to VCC_VSS_V1P2 net which connects to GND via 0-ohm resistor R216. This configuration is correct for designs where MIPI CSI is not used.
AD18 VSS_AD18 VCC_VSS_V1P2 ✅ VSS pins connected to VCC_VSS_V1P2 net which connects to GND via 0-ohm resistor R216. This configuration is correct for designs where MIPI CSI is not used.
AD35 DRAM_V1P0_S0IX_AD35 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
AF35 DRAM_V1P0_S0IX_AF35 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
AF36 DRAM_V1P0_S0IX_AF36 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
AJ36 DRAM_V1P0_S0IX_AJ36 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
AK35 DRAM_V1P0_S0IX_AK35 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
AK36 DRAM_V1P0_S0IX_AK36 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
Y35 DRAM_V1P0_S0IX_Y35 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
Y36 DRAM_V1P0_S0IX_Y36 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
AA36 DRAM_V1P0_S0IX_AA36 VCC_DRAM ✅ DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided.
BD1 VGA_V1P35_S3_F1_BD1 VCC_CRT_V1P35 ✅ VGA_V1P35_S3_F1 pin correctly connected to VCC_CRT_V1P35 rail, fed from +V1P35S through ferrite FB4. Powers VGA CRT interface.
AF16 UNCORE_V1P0_S3_AF16 +V1P0S ✅ UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling.
AF18 UNCORE_V1P0_S3_AF18 +V1P0S ✅ UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling.
G1 UNCORE_V1P0_S3_G1 +V1P0S ✅ UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling.
Y18 UNCORE_V1P0_S3_Y18 +V1P0S ✅ UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling.
AF19 UNCORE_V1P35_S0IX_F6 VCC_UNCORE_V1P35 ✅ UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided.
AG19 UNCORE_V1P35_S0IX_F1_AG19 VCC_UNCORE_V1P35 ✅ UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided.
AG32 UNCORE_V1P35_S0IX_F2_AG32 VCC_UNCORE_V1P35 ✅ UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided.
U36 UNCORE_V1P35_S0IX_F4_U36 VCC_UNCORE_V1P35 ✅ UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided.
V36 UNCORE_V1P35_S0IX_F3_V36 VCC_UNCORE_V1P35 ✅ UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided.
AA25 UNCORE_V1P35_S0IX_F5_AA25 VCC_UNCORE_V1P35 ✅ UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided.
AD36 DRAM_V1P35_S0IX_F1_AD36 VCC_UNCORE_V1P35 ✅ UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided.
AF21 UNCORE_V1P0_S0IX_AF21 VCC_VIS_V1P0 ✅ UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic.
AG21 UNCORE_V1P0_S0IX_AG21 VCC_VIS_V1P0 ✅ UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic.
V24 UNCORE_V1P0_S0IX_V24 VCC_VIS_V1P0 ✅ UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic.
Y22 UNCORE_V1P0_S0IX_Y22 VCC_VIS_V1P0 ✅ UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic.
Y24 UNCORE_V1P0_S0IX_Y24 VCC_VIS_V1P0 ✅ UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic.
AN29 UNCORE_V1P0_S0IX_AN29 VCC_VIS_V1P0 ✅ UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic.
AN30 UNCORE_V1P0_S0IX_AN30 VCC_VIS_V1P0 ✅ UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic.
AJ18 DDI_V1P0_S0IX_AJ18 +V1P0S ✅ DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling.
AK19 DDI_V1P0_S0IX_AK19 +V1P0S ✅ DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling.
AK21 DDI_V1P0_S0IX_AK21 +V1P0S ✅ DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling.
AM16 DDI_V1P0_S0IX_AM16 +V1P0S ✅ DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling.
AJ19 ICLK_V1P35_S3_F1_AJ19 VCC_ICLK_V1P35 ✅ ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail, fed from +V1P35S through ferrite FB5. Powers integrated clock logic.
AG18 ICLK_V1P35_S3_F2 VCC_ICLK_V1P35 ✅ ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail, fed from +V1P35S through ferrite FB5. Powers integrated clock logic.
BJ6 VGA_V1P0_S3_BJ6 +V1P0S ✅ VGA_V1P0_S3 pin correctly connected to +V1P0S rail. Powers VGA digital logic with proper decoupling.
AK18 PCIE_V1P0_S3_AK18 +V1P0S ✅ PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling.
AM18 PCIE_V1P0_S3_AM18 +V1P0S ✅ PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling.
AM21 PCIE_V1P0_S3_AM21 +V1P0S ✅ PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling.
AN18 PCIE_SATA_V1P0_S3_AN18 +V1P0S ✅ PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling.
AN19 SATA_V1P0_S3_AN19 +V1P0S ✅ PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling.
AN21 PCIE_V1P0_S3_AN21 +V1P0S ✅ PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling.
AM27 LPC_V1P8V3P3_S3_AM27 +VCC3S ✅ LPC, SD, and VGA 1.8V/3.3V power pins correctly connected to +VCC3S rail (3.3V supply). Proper decoupling provided.
AN27 SD3_V1P8V3P3_S3_AN27 +VCC3S ✅ LPC, SD, and VGA 1.8V/3.3V power pins correctly connected to +VCC3S rail (3.3V supply). Proper decoupling provided.
AN24 VGA_V3P3_S3_AN24 +VCC3S ✅ LPC, SD, and VGA 1.8V/3.3V power pins correctly connected to +VCC3S rail (3.3V supply). Proper decoupling provided.
AM30 UNCORE_V1P8_S3_AM30 +V1P8S ✅ UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided.
AN32 UNCORE_V1P8_S3_AN32 +V1P8S ✅ UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided.
U38 UNCORE_V1P8_S3_U38 +V1P8S ✅ UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided.
AM32 HDA_LPE_V1P5V1P8_S3_AM32 +V1P8S ✅ UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided.
AN25 GPIO_V1P0_S3_AN25 +V1P0S ✅ GPIO_V1P0_S3 pin correctly connected to +V1P0S rail. Powers GPIO logic with proper decoupling.
FB4 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P35S ✅ Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply.
2 2 VCC_CRT_V1P35 ✅ Output pin connected to VCC_CRT_V1P35, which powers the VGA/CRT interface. The ferrite provides filtering for this power domain.
FB3 - FERRITE_600OHM_1.3A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P35S ✅ Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply.
2 2 VCC_UNCORE_V1P35 ✅ Output pin connected to VCC_UNCORE_V1P35, which powers multiple CPU UNCORE and DRAM voltage pins. The ferrite provides filtering for this power domain.
FB5 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P35S ✅ Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply.
2 2 VCC_ICLK_V1P35 ✅ Output pin connected to VCC_ICLK_V1P35, which powers the internal clock circuitry. The ferrite provides filtering for this power domain.
R222 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ✅ Connected to +V1P0S power rail, which supplies multiple 1.0V power domains for the Intel Atom E3825 CPU including core, peripherals, and I/O interfaces.
2 2 VCC_VIS_V1P0 ✅ Connected to VCC_VIS_V1P0 power rail, which supplies the CPU's graphics/VIS (Visual Intelligence) uncore domain during S0ix low-power state.
R265 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ✅ Connected to +V1P0S power rail, which supplies multiple 1.0V power domains for the CPU.
2 2 VCC_DRAM ✅ Connected to VCC_DRAM power rail, which supplies the CPU's DRAM interface power pins in S0ix state.
R216 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCC_VSS_V1P2 ✅ Connected to VCC_VSS_V1P2 net, which connects to CPU VSS pins AD16 and AD18. This net is grounded through the 0-ohm resistor when MIPI CSI is not used.
2 2 GND ✅ Connected to GND, providing the ground connection for the CPU VSS pins through the 0-ohm resistor.
D7 - D5V0L1B2LP-7B ✅

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Pin Designator Pin Name Net Correct? Analysis
N N GND ✅ Pin N is correctly connected to GND, serving as the reference terminal for this bidirectional TVS diode.
P P +5VSB ✅ Pin P is correctly connected to the +5VSB rail, serving as the protected line terminal of this bidirectional TVS diode for ESD protection.
J8 - 3430-0212 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Pin 1 is correctly connected to the +5VSB power rail, serving as the power input/output terminal for this 2x1 vertical header connector.
2 2 GND ✅ Pin 2 is correctly connected to GND, serving as the ground return terminal for this connector.
J2 - 258-0004524 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Pin 1 is connected to +5VSB but the component is marked DNI (Do Not Install), so it is electrically absent from the circuit.
2 2 GND ✅ Pin 2 is connected to GND but the component is marked DNI (Do Not Install), so it is electrically absent from the circuit.
CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator Pin Name Net Correct? Analysis
A11 VSS1 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A15 VSS2 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A19 VSS3 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A23 VSS4 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A27 VSS5 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A31 VSS6 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A35 VSS7 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A39 VSS8 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A43 VSS9 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
A47 VSS10 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA1 VSS11 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA3 VSS15 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA16 VSS12 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA19 VSS13 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA21 VSS14 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA32 VSS16 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA35 VSS17 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA38 VSS18 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AA53 VSS19 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB4 VSS21 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB6 VSS28 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB10 VSS20 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB41 VSS22 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB45 VSS23 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB47 VSS24 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB48 VSS25 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB50 VSS26 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AB51 VSS27 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC16 VSS29 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC18 VSS30 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC19 VSS31 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC21 VSS32 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC25 VSS33 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC33 VSS34 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC35 VSS35 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC36 VSS36 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AC38 VSS37 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AD7 VSS44 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AD19 VSS38 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AD21 VSS39 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AD25 VSS40 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AD32 VSS41 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AD33 VSS42 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AD47 VSS43 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE1 VSS45 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE3 VSS49 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE4 VSS50 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE6 VSS60 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE8 VSS61 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE9 VSS62 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE11 VSS46 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE12 VSS47 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE14 VSS48 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE40 VSS51 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE42 VSS52 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE43 VSS53 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE45 VSS54 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE46 VSS55 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE48 VSS56 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE50 VSS57 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE51 VSS58 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AE53 VSS59 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AF10 VSS63 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AF12 VSS64 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AF25 VSS65 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AF32 VSS66 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AF47 VSS67 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AG16 VSS68 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AG25 VSS69 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AG36 VSS70 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AG38 VSS71 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH4 VSS72 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH6 VSS110 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH7 VSS75 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH9 VSS76 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH41 VSS73 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH45 VSS74 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH47 VSS106 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH48 VSS107 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH50 VSS108 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AH51 VSS109 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ1 VSS77 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ3 VSS83 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ16 VSS78 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ21 VSS79 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ25 VSS80 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ27 VSS81 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ29 VSS82 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ30 VSS84 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ32 VSS85 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ33 VSS86 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ35 VSS87 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ38 VSS88 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AJ53 VSS89 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AK10 VSS90 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AK14 VSS91 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AK16 VSS92 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AK33 VSS93 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AK41 VSS94 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AK44 VSS95 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM7 VSS113 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM12 VSS96 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM19 VSS97 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM24 VSS98 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM25 VSS99 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM29 VSS100 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM33 VSS101 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM35 VSS102 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM36 VSS103 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM40 VSS104 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM44 VSS111 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AM51 VSS112 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN1 VSS114 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN3 VSS119 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN5 VSS131 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN6 VSS134 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN8 VSS135 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN9 VSS136 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN11 VSS115 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN12 VSS116 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN14 VSS117 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN22 VSS118 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN33 VSS120 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN35 VSS121 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN36 VSS122 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN38 VSS123 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN40 VSS124 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN42 VSS125 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN43 VSS126 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN45 VSS127 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN46 VSS128 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN48 VSS129 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN49 VSS130 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN51 VSS132 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AN53 VSS133 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AP40 VSS137 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT4 VSS146 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT12 VSS138 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT16 VSS139 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT19 VSS140 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT24 VSS141 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT27 VSS142 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT30 VSS143 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT35 VSS144 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT38 VSS145 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT47 VSS147 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AT52 VSS148 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AU1 VSS149 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AU3 VSS151 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AU24 VSS150 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AU30 VSS152 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AU38 VSS153 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AU51 VSS154 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV7 VSS167 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV12 VSS155 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV13 VSS156 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV14 VSS157 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV18 VSS158 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV19 VSS159 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV24 VSS160 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV27 VSS161 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV30 VSS162 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV35 VSS163 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV38 VSS164 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV47 VSS165 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AV51 VSS166 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AW3 VSS171 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AW13 VSS168 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AW19 VSS169 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AW27 VSS170 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AW35 VSS172 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AY4 VSS177 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AY9 VSS179 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AY10 VSS173 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AY22 VSS174 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AY32 VSS175 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AY36 VSS176 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
AY50 VSS178 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA14 VSS180 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA19 VSS181 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA22 VSS182 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA27 VSS183 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA32 VSS184 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA35 VSS185 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA40 VSS186 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BA53 VSS187 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BB19 VSS188 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BB27 VSS189 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BB35 VSS190 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BC20 VSS191 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BC22 VSS192 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BC26 VSS193 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BC28 VSS194 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BC32 VSS195 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BC34 VSS196 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BC42 VSS197 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BD19 VSS198 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BD24 VSS199 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BD27 VSS200 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BD30 VSS201 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BD35 VSS202 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BE2 VSS204 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BE8 VSS206 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BE19 VSS203 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BE35 VSS205 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BF4 VSS213 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BF12 VSS207 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BF16 VSS208 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BF24 VSS209 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BF30 VSS211 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BF36 VSS212 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BF38 VSS210 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BG31 VSS214 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BG34 VSS215 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BG39 VSS216 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BG42 VSS217 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BG45 VSS218 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BG49 VSS219 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ7 VSS230 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ11 VSS220 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ15 VSS221 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ19 VSS222 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ23 VSS223 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ27 VSS224 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ31 VSS225 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ35 VSS226 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ39 VSS227 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ43 VSS228 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
BJ47 VSS229 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
C14 VSS231 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
C31 VSS232 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
C34 VSS233 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
C39 VSS234 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
C42 VSS235 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
C45 VSS236 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
C49 VSS237 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
D12 VSS238 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
D16 VSS239 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
D24 VSS240 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
D30 VSS241 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
D36 VSS242 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
D38 VSS243 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
E8 VSS246 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
E19 VSS244 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
E35 VSS245 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F2 VSS248 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F5 VSS253 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F7 VSS254 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F19 VSS247 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F24 VSS249 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F27 VSS250 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F30 VSS251 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
F35 VSS252 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G10 VSS255 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G20 VSS256 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G22 VSS257 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G26 VSS258 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G28 VSS259 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G32 VSS260 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G34 VSS261 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
G42 VSS262 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
H19 VSS263 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
H27 VSS264 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
H35 VSS265 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J1 VSS266 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J16 VSS267 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J19 VSS268 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J22 VSS269 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J27 VSS270 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J32 VSS271 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J35 VSS272 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J40 VSS273 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
J53 VSS274 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
K4 VSS279 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
K9 VSS281 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
K14 VSS275 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
K22 VSS276 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
K32 VSS277 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
K36 VSS278 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
K50 VSS280 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
L13 VSS282 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
L19 VSS283 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
L27 VSS284 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
L35 VSS285 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M19 VSS286 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M26 VSS287 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M27 VSS288 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M28 VSS105 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M34 VSS289 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M35 VSS290 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M38 VSS291 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M47 VSS292 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
M51 VSS293 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
N1 VSS294 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
N16 VSS295 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
N38 VSS296 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
N51 VSS297 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P4 VSS306 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P9 VSS309 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P13 VSS298 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P16 VSS299 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P19 VSS300 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P20 VSS301 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P24 VSS302 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P32 VSS303 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P35 VSS304 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P38 VSS305 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P47 VSS307 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
P52 VSS308 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
T40 VSS310 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U1 VSS311 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U3 VSS316 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U5 VSS326 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U6 VSS329 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U8 VSS330 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U9 VSS331 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U11 VSS312 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U12 VSS313 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U14 VSS314 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U21 VSS315 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U30 VSS317 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U32 VSS318 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U40 VSS319 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U42 VSS320 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U43 VSS321 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U45 VSS322 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U46 VSS323 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U48 VSS324 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U49 VSS325 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U51 VSS327 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
U53 VSS328 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V7 VSS340 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V12 VSS332 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V16 VSS333 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V19 VSS334 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V21 VSS335 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V35 VSS336 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V40 VSS337 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V44 VSS338 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
V51 VSS339 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y7 VSS349 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y9 VSS350 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y10 VSS341 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y14 VSS342 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y16 VSS343 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y21 VSS344 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y25 VSS345 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y33 VSS346 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y41 VSS347 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
Y44 VSS348 GND ✅ All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page.
MEM2 - MICRON MT41K256M16HA ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator Pin Name Net Correct? Analysis
A1 VDDQ1 +VDIMM ✅ VDDQ1 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
A2 DQU5 M_DATA_A15 ✅ DQ13 data pin correctly connected to M_DATA_A15 for upper byte data bit 5.
A3 DQU7 M_DATA_A14 ✅ DQ15 data pin correctly connected to M_DATA_A14 for upper byte data bit 7.
A7 DQU4 M_DATA_A13 ✅ DQ12 data pin correctly connected to M_DATA_A13 for upper byte data bit 4.
A8 VDDQ5 +VDIMM ✅ VDDQ5 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
A9 VSS9 GND ✅ VSS9 ground pin correctly connected to GND.
B1 VSSQ1 GND ✅ VSSQ1 DQ ground pin correctly connected to GND for isolated noise immunity.
B2 VDD8 +VDIMM ✅ VDD8 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
B3 VSS6 GND ✅ VSS6 ground pin correctly connected to GND.
B7 /DQSU M_DQS_A_N1 ✅ Upper byte data strobe complement correctly connected to M_DQS_A_N1 for differential signaling.
B8 DQU6 M_DATA_A12 ✅ DQ14 data pin correctly connected to M_DATA_A12 for upper byte data bit 6.
B9 VSSQ7 GND ✅ VSSQ7 DQ ground pin correctly connected to GND for isolated noise immunity.
C1 VDDQ2 +VDIMM ✅ VDDQ2 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
C2 DQU3 M_DATA_A11 ✅ DQ11 data pin correctly connected to M_DATA_A11 for upper byte data bit 3.
C3 DQU1 M_DATA_A10 ✅ DQ9 data pin correctly connected to M_DATA_A10 for upper byte data bit 1.
C7 DQSU M_DQS_A_P1 ✅ Upper byte data strobe correctly connected to M_DQS_A_P1 for differential signaling.
C8 DQU2 M_DATA_A8 ✅ DQ10 data pin correctly connected to M_DATA_A8 for upper byte data bit 2.
C9 VDDQ6 +VDIMM ✅ VDDQ6 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
D1 VSSQ2 GND ✅ VSSQ2 DQ ground pin correctly connected to GND for isolated noise immunity.
D2 VDDQ9 +VDIMM ✅ VDDQ9 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
D3 DMU M_DM_A1 ✅ Upper byte data mask pin correctly connected to M_DM_A1 for write data masking.
D7 DQU0 M_DATA_A9 ✅ DQ8 data pin correctly connected to M_DATA_A9 for upper byte data bit 0.
D8 VSSQ5 GND ✅ VSSQ5 DQ ground pin correctly connected to GND for isolated noise immunity.
D9 VDD4 +VDIMM ✅ VDD4 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
E1 VSS1 GND ✅ VSS1 ground pin correctly connected to GND.
E2 VSSQ4 GND ✅ VSSQ4 DQ ground pin correctly connected to GND for isolated noise immunity.
E3 DQL0 M_DATA_A0 ✅ DQ0 data pin correctly connected to M_DATA_A0 for lower byte data bit 0.
E7 DML M_DM_A0 ✅ Lower byte data mask pin correctly connected to M_DM_A0 for write data masking.
E8 VSSQ6 GND ✅ VSSQ6 DQ ground pin correctly connected to GND for isolated noise immunity.
E9 VDDQ7 +VDIMM ✅ VDDQ7 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
F1 VDDQ3 +VDIMM ✅ VDDQ3 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
F2 DQL2 M_DATA_A2 ✅ DQ2 data pin correctly connected to M_DATA_A2 for lower byte data bit 2.
F3 DQSL M_DQS_A_P0 ✅ Lower byte data strobe correctly connected to M_DQS_A_P0 for differential signaling.
F7 DQL1 M_DATA_A1 ✅ DQ1 data pin correctly connected to M_DATA_A1 for lower byte data bit 1.
F8 DQL3 M_DATA_A3 ✅ DQ3 data pin correctly connected to M_DATA_A3 for lower byte data bit 3.
F9 VSSQ8 GND ✅ VSSQ8 DQ ground pin correctly connected to GND for isolated noise immunity.
G1 VSSQ3 GND ✅ VSSQ3 DQ ground pin correctly connected to GND for isolated noise immunity.
G2 DQL6 M_DATA_A6 ✅ DQ6 data pin correctly connected to M_DATA_A6 for lower byte data bit 6.
G3 /DQSL M_DQS_A_N0 ✅ Lower byte data strobe complement correctly connected to M_DQS_A_N0 for differential signaling.
G7 VDD1 +VDIMM ✅ VDD1 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
G8 VSS7 GND ✅ VSS7 ground pin correctly connected to GND.
G9 VSSQ9 GND ✅ VSSQ9 DQ ground pin correctly connected to GND for isolated noise immunity.
H1 VREFDQ SM_VREF_DQ1_A ✅ VREFDQ reference voltage correctly connected to SM_VREF_DQ1_A with proper voltage divider generating VDDQ/2.
H2 VDDQ4 +VDIMM ✅ VDDQ4 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
H3 DQL4 M_DATA_A4 ✅ DQ4 data pin correctly connected to M_DATA_A4 for lower byte data bit 4.
H7 DQL7 M_DATA_A7 ✅ DQ7 data pin correctly connected to M_DATA_A7 for lower byte data bit 7.
H8 DQL5 M_DATA_A5 ✅ DQ5 data pin correctly connected to M_DATA_A5 for lower byte data bit 5.
H9 VDDQ8 +VDIMM ✅ VDDQ8 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
J1 NC1__ODT1_ ✅ NC1 (ODT1) no-connect pin correctly left unconnected per datasheet.
J2 VSS5 GND ✅ VSS5 ground pin correctly connected to GND.
J3 /RAS M_RAS_A_L ✅ Row address strobe command input correctly connected to M_RAS_A_L, shared with MEM3.
J7 CK M_CLK_A_P0 ✅ Differential clock input positive correctly connected to M_CLK_A_P0, shared with MEM3.
J8 VSS8 GND ✅ VSS8 ground pin correctly connected to GND.
J9 NC3__CKE1_ ✅ NC3 (CKE1) no-connect pin correctly left unconnected per datasheet.
K1 ODT M_ODT_A0 ✅ On-die termination enable correctly connected to M_ODT_A0, shared with MEM3.
K2 VDD9 +VDIMM ✅ VDD9 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
K3 /CAS M_CAS_A_L ✅ Column address strobe command input correctly connected to M_CAS_A_L, shared with MEM3.
K7 /CK M_CLK_A_N0 ✅ Differential clock input complement correctly connected to M_CLK_A_N0, shared with MEM3.
K8 VDD2 +VDIMM ✅ VDD2 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
K9 CKE M_CKE_A0 ✅ Clock enable correctly connected to M_CKE_A0, shared with MEM3.
L1 NC2__/CS1_ ✅ NC2 (CS1) no-connect pin correctly left unconnected per datasheet.
L2 /CS M_CS_A_L0 ✅ Chip select command input correctly connected to M_CS_A_L0, shared with MEM3.
L3 /WE M_WE_A_L ✅ Write enable command input correctly connected to M_WE_A_L, shared with MEM3.
L7 A10_AP_ M_MA_A10 ✅ Address A10 with auto-precharge function correctly connected to M_MA_A10, shared with MEM3.
L8 ZQ M_ZQ1 ✅ ZQ calibration pin correctly connected to M_ZQ1 with 240 ohm resistor to ground.
L9 NC4__ZQ1_ ✅ NC4 (ZQ1) no-connect pin correctly left unconnected per datasheet.
M1 VSS2 GND ✅ VSS2 ground pin correctly connected to GND.
M2 BA0 M_BS_A0 ✅ Bank address BA0 correctly connected to M_BS_A0, shared with MEM3.
M3 BA2 M_BS_A2 ✅ Bank address BA2 correctly connected to M_BS_A2, shared with MEM3.
M7 NC5 ✅ NC5 no-connect pin correctly left unconnected per datasheet.
M8 VREFCA SM_VREF_CA1_A ✅ VREFCA reference voltage correctly connected to SM_VREF_CA1_A with proper voltage divider generating VDDQ/2.
M9 VSS10 GND ✅ VSS10 ground pin correctly connected to GND.
N1 VDD6 +VDIMM ✅ VDD6 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
N2 A3 M_MA_A3 ✅ Address A3 correctly connected to M_MA_A3, shared with MEM3.
N3 A0 M_MA_A0 ✅ Address A0 correctly connected to M_MA_A0, shared with MEM3.
N7 A12_/BC_ M_MA_A12 ✅ Address A12 with burst chop function correctly connected to M_MA_A12, shared with MEM3.
N8 BA1 M_BS_A1 ✅ Bank address BA1 correctly connected to M_BS_A1, shared with MEM3.
N9 VDD3 +VDIMM ✅ VDD3 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
P1 VSS3 GND ✅ VSS3 ground pin correctly connected to GND.
P2 A5 M_MA_A5 ✅ Address A5 correctly connected to M_MA_A5, shared with MEM3.
P3 A2 M_MA_A2 ✅ Address A2 correctly connected to M_MA_A2, shared with MEM3.
P7 A1 M_MA_A1 ✅ Address A1 correctly connected to M_MA_A1, shared with MEM3.
P8 A4 M_MA_A4 ✅ Address A4 correctly connected to M_MA_A4, shared with MEM3.
P9 VSS11 GND ✅ VSS11 ground pin correctly connected to GND.
R1 VDD7 +VDIMM ✅ VDD7 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
R2 A7 M_MA_A7 ✅ Address A7 correctly connected to M_MA_A7, shared with MEM3.
R3 A9 M_MA_A9 ✅ Address A9 correctly connected to M_MA_A9, shared with MEM3.
R7 A11 M_MA_A11 ✅ Address A11 correctly connected to M_MA_A11, shared with MEM3.
R8 A6 M_MA_A6 ✅ Address A6 correctly connected to M_MA_A6, shared with MEM3.
R9 VDD5 +VDIMM ✅ VDD5 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation.
T1 VSS4 GND ✅ VSS4 ground pin correctly connected to GND.
T2 /RESET M_A_RST_L ✅ Active-low reset input correctly connected to M_A_RST_L, shared with MEM3.
T3 A13 M_MA_A13 ✅ Address A13 correctly connected to M_MA_A13, shared with MEM3.
T7 A14 M_MA_A14 ✅ Address A14 correctly connected to M_MA_A14, shared with MEM3.
T8 A8 M_MA_A8 ✅ Address A8 correctly connected to M_MA_A8, shared with MEM3.
T9 VSS12 GND ✅ VSS12 ground pin correctly connected to GND.
MEM3 - MICRON MT41K256M16HA ✅

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Pin Designator Pin Name Net Correct? Analysis
A1 VDDQ1 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
C1 VDDQ2 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
F1 VDDQ3 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
H2 VDDQ4 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
A8 VDDQ5 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
C9 VDDQ6 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
D2 VDDQ9 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
E9 VDDQ7 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
H9 VDDQ8 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
D9 VDD4 +VDIMM ✅ VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
B1 VSSQ1 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
D1 VSSQ2 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
G1 VSSQ3 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
E2 VSSQ4 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
D8 VSSQ5 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
E8 VSSQ6 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
B9 VSSQ7 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
F9 VSSQ8 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
G9 VSSQ9 GND ✅ VSSQ DQ ground pins correctly connected to GND for isolated noise immunity.
B2 VDD8 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
K2 VDD9 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
G7 VDD1 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
K8 VDD2 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
N1 VDD6 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
N9 VDD3 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
R1 VDD7 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
R9 VDD5 +VDIMM ✅ VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation.
C7 DQSU M_DQS_A_P3 ✅ Upper byte data strobe differential pair correctly connected to M_DQS_A_P3 and M_DQS_A_N3.
B7 /DQSU M_DQS_A_N3 ✅ Upper byte data strobe differential pair correctly connected to M_DQS_A_P3 and M_DQS_A_N3.
D3 DMU M_DM_A3 ✅ Upper byte data mask pin correctly connected to M_DM_A3 for write data masking.
D7 DQU0 M_DATA_A29 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
C3 DQU1 M_DATA_A26 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
C8 DQU2 M_DATA_A28 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
C2 DQU3 M_DATA_A27 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
A7 DQU4 M_DATA_A25 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
A2 DQU5 M_DATA_A30 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
B8 DQU6 M_DATA_A24 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
A3 DQU7 M_DATA_A31 ✅ Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus.
E1 VSS1 GND ✅ VSS ground pins correctly connected to GND.
M1 VSS2 GND ✅ VSS ground pins correctly connected to GND.
P1 VSS3 GND ✅ VSS ground pins correctly connected to GND.
T1 VSS4 GND ✅ VSS ground pins correctly connected to GND.
J2 VSS5 GND ✅ VSS ground pins correctly connected to GND.
B3 VSS6 GND ✅ VSS ground pins correctly connected to GND.
G8 VSS7 GND ✅ VSS ground pins correctly connected to GND.
J8 VSS8 GND ✅ VSS ground pins correctly connected to GND.
A9 VSS9 GND ✅ VSS ground pins correctly connected to GND.
M9 VSS10 GND ✅ VSS ground pins correctly connected to GND.
P9 VSS11 GND ✅ VSS ground pins correctly connected to GND.
T9 VSS12 GND ✅ VSS ground pins correctly connected to GND.
E3 DQL0 M_DATA_A16 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
F7 DQL1 M_DATA_A17 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
F2 DQL2 M_DATA_A18 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
F8 DQL3 M_DATA_A19 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
H3 DQL4 M_DATA_A20 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
H8 DQL5 M_DATA_A21 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
G2 DQL6 M_DATA_A22 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
H7 DQL7 M_DATA_A23 ✅ Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus.
E7 DML M_DM_A2 ✅ Lower byte data mask pin correctly connected to M_DM_A2 for write data masking.
F3 DQSL M_DQS_A_P2 ✅ Lower byte data strobe differential pair correctly connected to M_DQS_A_P2 and M_DQS_A_N2.
G3 /DQSL M_DQS_A_N2 ✅ Lower byte data strobe differential pair correctly connected to M_DQS_A_P2 and M_DQS_A_N2.
H1 VREFDQ SM_VREF_DQ1_A ✅ VREFDQ reference voltage correctly connected to SM_VREF_DQ1_A with proper voltage divider generating VDDQ/2, shared with MEM2.
J1 NC1__ODT1_ ✅ No-connect pins correctly left unconnected per datasheet.
L1 NC2__/CS1_ ✅ No-connect pins correctly left unconnected per datasheet.
J9 NC3__CKE1_ ✅ No-connect pins correctly left unconnected per datasheet.
L9 NC4__ZQ1_ ✅ No-connect pins correctly left unconnected per datasheet.
M7 NC5 ✅ No-connect pins correctly left unconnected per datasheet.
J3 /RAS M_RAS_A_L ✅ Command inputs (RAS, CAS, WE) correctly connected to shared command bus with MEM2.
K3 /CAS M_CAS_A_L ✅ Command inputs (RAS, CAS, WE) correctly connected to shared command bus with MEM2.
L3 /WE M_WE_A_L ✅ Command inputs (RAS, CAS, WE) correctly connected to shared command bus with MEM2.
J7 CK M_CLK_A_P0 ✅ Differential clock inputs correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2.
K7 /CK M_CLK_A_N0 ✅ Differential clock inputs correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2.
K1 ODT M_ODT_A0 ✅ On-die termination enable correctly connected to M_ODT_A0, shared with MEM2.
K9 CKE M_CKE_A0 ✅ Clock enable correctly connected to M_CKE_A0, shared with MEM2.
L2 /CS M_CS_A_L0 ✅ Chip select command input correctly connected to M_CS_A_L0, shared with MEM2.
L8 ZQ M_ZQ2 ✅ ZQ calibration pin correctly connected to M_ZQ2 with 240 ohm resistor to ground.
M2 BA0 M_BS_A0 ✅ Bank address inputs correctly connected to shared bank address bus with MEM2.
N8 BA1 M_BS_A1 ✅ Bank address inputs correctly connected to shared bank address bus with MEM2.
M3 BA2 M_BS_A2 ✅ Bank address inputs correctly connected to shared bank address bus with MEM2.
M8 VREFCA SM_VREF_CA1_A ✅ VREFCA reference voltage correctly connected to SM_VREF_CA1_A with proper voltage divider generating VDDQ/2, shared with MEM2.
N3 A0 M_MA_A0 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
P7 A1 M_MA_A1 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
P3 A2 M_MA_A2 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
N2 A3 M_MA_A3 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
P8 A4 M_MA_A4 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
P2 A5 M_MA_A5 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
R8 A6 M_MA_A6 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
R2 A7 M_MA_A7 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
T8 A8 M_MA_A8 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
R3 A9 M_MA_A9 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
L7 A10_AP_ M_MA_A10 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
R7 A11 M_MA_A11 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
N7 A12_/BC_ M_MA_A12 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
T3 A13 M_MA_A13 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
T7 A14 M_MA_A14 ✅ Address inputs A0-A14 correctly connected to shared address bus with MEM2.
T2 /RESET M_A_RST_L ✅ Active-low reset input correctly connected to M_A_RST_L, shared with MEM2.
C124 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SM_VREF_DQ1_A ✅ Connected to SM_VREF_DQ1_A to provide AC decoupling for the DDR3 VREFDQ reference voltage.
2 2 GND ✅ Connected to GND to complete the decoupling path for the reference voltage.
R310 - 110-0002058 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM ✅ Connected to +VDIMM to form the upper leg of a voltage divider for DDR3 VREFDQ reference voltage generation.
2 2 SM_VREF_DQ1_A ✅ Connected to SM_VREF_DQ1_A reference voltage net, providing the midpoint of the voltage divider.
C329 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SM_VREF_DQ1_A ✅ Connected to SM_VREF_DQ1_A to provide additional AC decoupling for the DDR3 VREFDQ reference voltage.
2 2 GND ✅ Connected to GND to complete the decoupling path for the reference voltage.
R325 - 110-0002058 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND to form the lower leg of the voltage divider for DDR3 VREFDQ reference voltage generation.
2 2 SM_VREF_DQ1_A ✅ Connected to SM_VREF_DQ1_A reference voltage net, providing the midpoint of the voltage divider.
R327 - 110-0001971 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 M_ZQ2 ✅ Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM3 via net M_ZQ2. This provides the reference impedance for the memory's output driver calibration.
2 2 GND ✅ Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit.
R140 - 110-0001971 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 M_ZQ1 ✅ Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM2 via net M_ZQ1. This provides the reference impedance for the memory's output driver calibration.
2 2 GND ✅ Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit.
C374 - 10pF 5% 50V 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND. However, C374 is marked DNI (Do Not Install), so this connection is not electrically present in the final circuit.
2 2 M_A_RST_L ✅ Connected to M_A_RST_L, the reset signal net for the memory devices. However, C374 is marked DNI (Do Not Install), so this connection is not electrically present in the final circuit.
R353 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 M_A_DRAMRST_L ✅ Connected to M_A_DRAMRST_L net, which is the source of the DRAM reset signal. This pin serves as the input side of the 0-ohm series resistor.
2 2 M_A_RST_L ✅ Connected to M_A_RST_L net, which connects to the /RESET pins of memory devices MEM2 and MEM3. This pin serves as the output side of the 0-ohm series resistor.
C287 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Decoupling capacitor negative terminal correctly connected to GND.
2 2 +VCC3 ✅ Decoupling capacitor positive terminal correctly connected to +VCC3 power rail.
U33 - M24C02-WMN6TP-X ✅

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Pin Designator Pin Name Net Correct? Analysis
1 E0 DDR_E0 ✅ E0 address input pin connected to DDR_E0 net. Pin is floating because pull-down resistor R118 is DNI.
2 E1 DDR_E1 ✅ E1 address input pin connected to DDR_E1 net. Pin is floating because pull-down resistor R123 is DNI.
3 E2 GND ✅ E2 address input pin correctly connected to GND to set address bit to 0.
4 GND GND ✅ Ground pin correctly connected to GND net.
5 SDA DDR_SMB_DATA ✅ SDA pin correctly connected to DDR_SMB_DATA for I2C data communication.
6 SCL DDR_SMB_CLK ✅ SCL pin correctly connected to DDR_SMB_CLK for I2C clock communication.
7 ~WC DDR_WP_A ✅ Write Control pin connected to DDR_WP_A net. Pin is floating because both configuration resistors R121 and R122 are DNI.
8 VCC +VCC3 ✅ VCC power pin correctly connected to +VCC3 with decoupling capacitor C287.
C145 - 123-0004765 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM_VTT ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
2 2 GND ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
C146 - 123-0004765 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM_VTT ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
2 2 GND ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
C369 - 123-0004765 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM_VTT ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
2 2 GND ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
C370 - 123-0004765 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM_VTT ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
2 2 GND ✅ Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND.
C331 - 3.3pF 10% 25V 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 M_CLK_A_N0 ✅ C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization.
2 2 M_CLK_A_P0 ✅ C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization.
FL1 - 3750-0010 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 CH1-IN SD3_CD# ✅ CH1-IN is connected to SD3_CD# (card detect signal) which has a 100K pull-up to +V1P8S via R182. This channel filters the card detect signal before it goes to the microSD connector.
2 CH2-IN SD3_D2 ✅ CH2-IN is connected to SD3_D2 (data line 2) which has a 100K pull-up to +VCC3 via R174. This channel filters the data line before it goes to the microSD connector.
3 CH3-IN SD3_D3 ✅ CH3-IN is connected to SD3_D3 (data line 3) which has a 100K pull-up to +VCC3 via R180. This channel filters the data line before it goes to the microSD connector.
4 CH4-IN SD3_CMD ✅ CH4-IN is connected to SD3_CMD (command line) which has a 100K pull-up to +VCC3 via R173. This channel filters the command line before it goes to the microSD connector.
5 CH5-IN SD3_CLK ✅ CH5-IN is connected to SD3_CLK (clock line) which has a 100K pull-up to +VCC3 via R157. This channel filters the clock line before it goes to the microSD connector.
6 CH6-IN SD3_D0 ✅ CH6-IN is connected to SD3_D0 (data line 0) which has a 100K pull-up to +VCC3 via R156. This channel filters the data line before it goes to the microSD connector.
7 CH7-IN SD3_D1 ✅ CH7-IN is connected to SD3_D1 (data line 1) which has a 100K pull-up to +VCC3 via R155. This channel filters the data line before it goes to the microSD connector.
8 CH8-IN ✅ CH8-IN is unconnected. Channel 8 is unused in this design.
9 CH8-OUT ✅ CH8-OUT is unconnected. Channel 8 is unused in this design.
10 CH7-OUT SD3_D1_R ✅ CH7-OUT is connected to SD3_D1_R which goes to P2 pin 8 (DAT1). This is the filtered output for data line 1.
11 CH6-OUT SD3_D0_R ✅ CH6-OUT is connected to SD3_D0_R which goes to P2 pin 7 (DAT0). This is the filtered output for data line 0.
12 CH5-OUT SD3_CLK_R ✅ CH5-OUT is connected to SD3_CLK_R which goes to P2 pin 5 (CLOCK). This is the filtered output for the clock line.
13 CH4-OUT SD3_CMD_R ✅ CH4-OUT is connected to SD3_CMD_R which goes to P2 pin 3 (CMD). This is the filtered output for the command line.
14 CH3-OUT SD3_D3_R ✅ CH3-OUT is connected to SD3_D3_R which goes to P2 pin 2 (CD/DAT3). This is the filtered output for data line 3.
15 CH2-OUT SD3_D2_R ✅ CH2-OUT is connected to SD3_D2_R which goes to P2 pin 1 (DAT2). This is the filtered output for data line 2.
16 CH1-OUT SD3_CD_R ✅ CH1-OUT is connected to SD3_CD_R which goes to P2 pin 10 (CD). This is the filtered output for the card detect signal.
17 GND_PAD GND ✅ GND_PAD is connected to GND. This provides the ground reference for the passive filter.
P2 - 158-0001269 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 DAT2 SD3_D2_R ✅ DAT2 is connected to SD3_D2_R, the filtered data line 2 from FL1 channel 2. This is correct for the microSD interface.
2 CD/DAT3 SD3_D3_R ✅ CD/DAT3 is connected to SD3_D3_R, the filtered data line 3 from FL1 channel 3. This is correct for the microSD interface.
3 CMD SD3_CMD_R ✅ CMD is connected to SD3_CMD_R, the filtered command line from FL1 channel 4. This is correct for the microSD interface.
4 VDD +VCC3 ✅ VDD is connected to +VCC3 with decoupling capacitors C162 and C159 (both 10uF). This provides proper power to the microSD card.
5 CLOCK SD3_CLK_R ✅ CLOCK is connected to SD3_CLK_R, the filtered clock line from FL1 channel 5. This is correct for the microSD interface.
6 VSS GND ✅ VSS is connected to GND. This provides the ground reference for the microSD card.
7 DAT0 SD3_D0_R ✅ DAT0 is connected to SD3_D0_R, the filtered data line 0 from FL1 channel 6. This is correct for the microSD interface.
8 DAT1 SD3_D1_R ✅ DAT1 is connected to SD3_D1_R, the filtered data line 1 from FL1 channel 7. This is correct for the microSD interface.
9 GND GND ✅ GND is connected to GND. This provides an additional ground connection for the microSD card.
10 CD SD3_CD_R ✅ CD is connected to SD3_CD_R, the filtered card detect signal from FL1 channel 1. The card detect has a pull-up to +V1P8S (1.8V) instead of +VCC3 (3.3V), which is likely intentional for host controller I/O compatibility.
11 GND3 FGND-uSD ✅ GND3 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection.
12 GND4 FGND-uSD ✅ GND4 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection.
13 GND5 FGND-uSD-Front ✅ GND5 is connected to FGND-uSD-Front. This is a frame ground connection for EMI/ESD protection.
14 GND6 FGND-uSD-Front ✅ GND6 is connected to FGND-uSD-Front. This is a frame ground connection for EMI/ESD protection.
15 GND7 FGND-uSD ✅ GND7 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection.
16 GND8 FGND-uSD ✅ GND8 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection.
R171 - 110-0001984 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ 2.2K pullup resistor correctly connected between +V1P8S and HPD_ENB (U2 CT_HPD control pin).
2 2 HPD_ENB ✅ 2.2K pullup resistor correctly connected between +V1P8S and HPD_ENB (U2 CT_HPD control pin).
R172 - 110-0001984 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ 2.2K pullup resistor correctly connected between +V1P8S and LS_OE (U2 level shifter enable pin).
2 2 LS_OE ✅ 2.2K pullup resistor correctly connected between +V1P8S and LS_OE (U2 level shifter enable pin).
C17 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ 0.1µF decoupling capacitor correctly connected between GND and +V1P8S (U2 VCCA supply).
2 2 +V1P8S ✅ 0.1µF decoupling capacitor correctly connected between GND and +V1P8S (U2 VCCA supply).
C155 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ 0.1µF decoupling capacitor correctly connected between GND and +5VSB (U2 VCC5V supply).
2 2 +5VSB ✅ 0.1µF decoupling capacitor correctly connected between GND and +5VSB (U2 VCC5V supply).
C157 - 123-0001144 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +HDMI_CRT_VCC ✅ 4.7µF decoupling capacitor correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and GND.
2 2 GND ✅ 4.7µF decoupling capacitor correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and GND.
L7 - 126-0001418 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 P1 +HDMI_CRT_VCC ✅ Ferrite bead correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and D5_0V_HDMI (HDMI connector +5V) for EMI filtering.
2 P2 D5_0V_HDMI ✅ Ferrite bead correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and D5_0V_HDMI (HDMI connector +5V) for EMI filtering.
U2 - TPD12S016PW ❌

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Pin Designator Pin Name Net Correct? Analysis
15 CLK- HDMI_OUT_CLK_DN ❌
CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.
  • Pin 15 is connected to net HDMI_OUT_CLK_DN (from schematic)
  • Pin 16 is connected to net HDMI_OUT_CLK_DP (from schematic)
  • Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet (from schematic)
  • The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) (from schematic)
  • The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
16 CLK+ HDMI_OUT_CLK_DP ❌
CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.
  • Pin 15 is connected to net HDMI_OUT_CLK_DN (from schematic)
  • Pin 16 is connected to net HDMI_OUT_CLK_DP (from schematic)
  • Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet (from schematic)
  • The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) (from schematic)
  • The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
17 D0- HDMI_OUT_TX0_DN ❌
D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.
  • Pin 17 is connected to net HDMI_OUT_TX0_DN (from schematic)
  • Pin 18 is connected to net HDMI_OUT_TX0_DP (from schematic)
  • Pin 22 is connected to net HDMI_OUT_TX2_DN (from schematic)
  • Pin 23 is connected to net HDMI_OUT_TX2_DP (from schematic)
  • Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet (from schematic)
  • The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
18 D0+ HDMI_OUT_TX0_DP ❌
D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.
  • Pin 17 is connected to net HDMI_OUT_TX0_DN (from schematic)
  • Pin 18 is connected to net HDMI_OUT_TX0_DP (from schematic)
  • Pin 22 is connected to net HDMI_OUT_TX2_DN (from schematic)
  • Pin 23 is connected to net HDMI_OUT_TX2_DP (from schematic)
  • Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet (from schematic)
  • The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
22 D2- HDMI_OUT_TX2_DN ❌
D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.
  • Pin 17 is connected to net HDMI_OUT_TX0_DN (from schematic)
  • Pin 18 is connected to net HDMI_OUT_TX0_DP (from schematic)
  • Pin 22 is connected to net HDMI_OUT_TX2_DN (from schematic)
  • Pin 23 is connected to net HDMI_OUT_TX2_DP (from schematic)
  • Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet (from schematic)
  • The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
23 D2+ HDMI_OUT_TX2_DP ❌
D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.
  • Pin 17 is connected to net HDMI_OUT_TX0_DN (from schematic)
  • Pin 18 is connected to net HDMI_OUT_TX0_DP (from schematic)
  • Pin 22 is connected to net HDMI_OUT_TX2_DN (from schematic)
  • Pin 23 is connected to net HDMI_OUT_TX2_DP (from schematic)
  • Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet (from schematic)
  • The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
20 D1- HDMI_OUT_TX1_DN ❌
D1+ and D1- pins are swapped. Pin 20 should be D1+ but is connected to HDMI_OUT_TX1_DN, and pin 21 should be D1- but is connected to HDMI_OUT_TX1_DP.
  • Pin 20 is connected to net HDMI_OUT_TX1_DN (from schematic)
  • Pin 21 is connected to net HDMI_OUT_TX1_DP (from schematic)
  • Pin 20 should be D1+ (HDMI TMDS data channel 1 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 21 should be D1- (HDMI TMDS data channel 1 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pin 20 labeled as D1- and pin 21 labeled as D1+, which is opposite to the datasheet (from schematic)
  • The D1 data channel signals are inverted due to the pin swap, which will prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
21 D1+ HDMI_OUT_TX1_DP ❌
D1+ and D1- pins are swapped. Pin 20 should be D1+ but is connected to HDMI_OUT_TX1_DN, and pin 21 should be D1- but is connected to HDMI_OUT_TX1_DP.
  • Pin 20 is connected to net HDMI_OUT_TX1_DN (from schematic)
  • Pin 21 is connected to net HDMI_OUT_TX1_DP (from schematic)
  • Pin 20 should be D1+ (HDMI TMDS data channel 1 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 21 should be D1- (HDMI TMDS data channel 1 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pin 20 labeled as D1- and pin 21 labeled as D1+, which is opposite to the datasheet (from schematic)
  • The D1 data channel signals are inverted due to the pin swap, which will prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
1 CEC_A HDMI_CEC ✅ CEC_A pin correctly connected to HDMI_CEC net with 10K pullup resistor R29 to +V1P8S.
2 SCL_A HDMI_DDCCLK ✅ SCL_A pin correctly connected to HDMI_DDCCLK net with 10K pullup resistor R28 to +V1P8S.
3 SDA_A HDMI_DDCDAT ✅ SDA_A pin correctly connected to HDMI_DDCDAT net with 10K pullup resistor R30 to +V1P8S.
4 HPD_A HDMI_HPD ✅ HPD_A pin correctly connected to HDMI_HPD net for hot plug detect output to HDMI controller.
5 LS_OE LS_OE ✅ LS_OE pin correctly connected to LS_OE net with 2.2K pullup resistor R172 to +V1P8S for level shifter enable control.
6 GND1 GND ✅ Ground pins correctly connected to GND net.
14 GND2 GND ✅ Ground pins correctly connected to GND net.
19 GND3 GND ✅ Ground pins correctly connected to GND net.
7 CEC_B C_HDMI_CEC ✅ CEC_B pin correctly connected to C_HDMI_CEC net for HDMI connector side CEC signal.
8 SCL_B C_HDMI_SCL ✅ SCL_B pin correctly connected to C_HDMI_SCL net for HDMI connector side SCL signal.
9 SDA_B C_HDMI_SDA ✅ SDA_B pin correctly connected to C_HDMI_SDA net for HDMI connector side SDA signal.
10 HPD_B C_HDMI_HPD ✅ HPD_B pin correctly connected to C_HDMI_HPD net for hot plug detect input from HDMI connector.
11 VCC5V +5VSB ✅ VCC5V pin correctly connected to +5VSB net with 0.1uF decoupling capacitor C155.
12 CT_HPD HPD_ENB ✅ CT_HPD pin correctly connected to HPD_ENB net with 2.2K pullup resistor R171 to +V1P8S for load switch and HPD control.
13 5V_OUT +HDMI_CRT_VCC ✅ 5V_OUT pin correctly connected to +HDMI_CRT_VCC net with 4.7uF decoupling capacitor C157 and ferrite bead L7 to HDMI connector.
24 VCCA +V1P8S ✅ VCCA pin correctly connected to +V1P8S net with 0.1uF decoupling capacitor C17.
L14 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 HDMI_CLK_C_DN ✅ IN1 pin connects to HDMI_CLK_C_DN through AC coupling capacitor C401, providing common mode filtering for the negative clock signal.
3 IN2 HDMI_CLK_C_DP ✅ IN2 pin connects to HDMI_CLK_C_DP through AC coupling capacitor C400, providing common mode filtering for the positive clock signal.
4 OUT2 HDMI_OUT_CLK_DP ✅ OUT2 pin connects to HDMI_OUT_CLK_DP, outputting the filtered positive clock signal to U2 and then to the HDMI connector.
6 OUT1 HDMI_OUT_CLK_DN ✅ OUT1 pin connects to HDMI_OUT_CLK_DN, outputting the filtered negative clock signal to U2 and then to the HDMI connector.
L17 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 HDMI_TX2_C_DN ✅ IN1 pin connects to HDMI_TX2_C_DN through AC coupling capacitor C407, providing common mode filtering for the negative data signal of channel 2.
3 IN2 HDMI_TX2_C_DP ✅ IN2 pin connects to HDMI_TX2_C_DP through AC coupling capacitor C406, providing common mode filtering for the positive data signal of channel 2.
4 OUT2 HDMI_OUT_TX2_DP ✅ OUT2 pin connects to HDMI_OUT_TX2_DP, outputting the filtered positive data signal to U2 and then to the HDMI connector.
6 OUT1 HDMI_OUT_TX2_DN ✅ OUT1 pin connects to HDMI_OUT_TX2_DN, outputting the filtered negative data signal to U2 and then to the HDMI connector.
L16 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 HDMI_TX1_C_DN ✅ IN1 pin connects to HDMI_TX1_C_DN through AC coupling capacitor C405, providing common mode filtering for the negative data signal of channel 1.
3 IN2 HDMI_TX1_C_DP ✅ IN2 pin connects to HDMI_TX1_C_DP through AC coupling capacitor C404, providing common mode filtering for the positive data signal of channel 1.
4 OUT2 HDMI_OUT_TX1_DP ✅ OUT2 pin connects to HDMI_OUT_TX1_DP, outputting the filtered positive data signal to U2 and then to the HDMI connector.
6 OUT1 HDMI_OUT_TX1_DN ✅ OUT1 pin connects to HDMI_OUT_TX1_DN, outputting the filtered negative data signal to U2 and then to the HDMI connector.
L15 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 HDMI_TX0_C_DN ✅ IN1 pin connects to HDMI_TX0_C_DN through AC coupling capacitor C403, providing common mode filtering for the negative data signal of channel 0.
3 IN2 HDMI_TX0_C_DP ✅ IN2 pin connects to HDMI_TX0_C_DP through AC coupling capacitor C402, providing common mode filtering for the positive data signal of channel 0.
4 OUT2 HDMI_OUT_TX0_DP ✅ OUT2 pin connects to HDMI_OUT_TX0_DP, outputting the filtered positive data signal to U2 and then to the HDMI connector.
6 OUT1 HDMI_OUT_TX0_DN ✅ OUT1 pin connects to HDMI_OUT_TX0_DN, outputting the filtered negative data signal to U2 and then to the HDMI connector.
R801 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_TX2_C_DN ✅ Connected to HDMI_TX2_C_DN, providing DC bias path for AC-coupled HDMI data signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
R802 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_TX2_C_DP ✅ Connected to HDMI_TX2_C_DP, providing DC bias path for AC-coupled HDMI data signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
R803 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_TX1_C_DN ✅ Connected to HDMI_TX1_C_DN, providing DC bias path for AC-coupled HDMI data signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
R804 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_TX1_C_DP ✅ Connected to HDMI_TX1_C_DP, providing DC bias path for AC-coupled HDMI data signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
R805 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_TX0_C_DN ✅ Connected to HDMI_TX0_C_DN, providing DC bias path for AC-coupled HDMI data signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
R806 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_TX0_C_DP ✅ Connected to HDMI_TX0_C_DP, providing DC bias path for AC-coupled HDMI data signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
R807 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_CLK_C_DP ✅ Connected to HDMI_CLK_C_DP, providing DC bias path for AC-coupled HDMI clock signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
R808 - 1120-0119 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_CLK_C_DN ✅ Connected to HDMI_CLK_C_DN, providing DC bias path for AC-coupled HDMI clock signal.
2 2 HDMI_TERM ✅ Connected to HDMI_TERM net, which is switchably connected to ground through Q101.
Q101 - 2N7002K ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN HDMI_TERM ✅ Drain connects to HDMI_TERM net, which is the common termination point for eight 619Ω resistors (R801-R808) connected to HDMI differential signal lines. When Q101 is on, it pulls HDMI_TERM to ground, providing a DC bias path for AC-coupled HDMI signals.
G GATE $15N747 ✅ Gate connects to net $15N747, which is driven by +VCC3 through 0Ω resistor R809. This keeps Q101 always on, continuously pulling HDMI_TERM to ground.
S SOURCE GND ✅ Source connects to GND, providing the return path for drain current when Q101 is on.
R809 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $15N747 ✅ Connects to gate of Q101 via net $15N747.
2 2 +VCC3 ✅ Connects to +VCC3 supply, providing gate drive voltage to Q101 through the 0Ω resistor.
P1 - 158-0004513 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 HPLG C_HDMI_HPD ✅ Hot Plug Detect (HPLG) pin correctly connected to the HPD signal path through U2 (TPD12S016PW) ESD protection device.
2 NC ✅ No Connect (NC) pin is correctly left unconnected.
3 DAT2+ HDMI_OUT_TX2_DP ✅ TMDS Data2+ pin correctly connected through common mode choke L17 and AC coupling capacitor C406 to the HDMI transmitter.
4 DAT2_S GND ✅ TMDS Data2 shield pin correctly connected to ground for EMI shielding.
5 DAT2- HDMI_OUT_TX2_DN ✅ TMDS Data2- pin correctly connected through common mode choke L17 and AC coupling capacitor C407 to the HDMI transmitter.
6 DAT1+ HDMI_OUT_TX1_DP ✅ TMDS Data1+ pin correctly connected through common mode choke L16 and AC coupling capacitor C404 to the HDMI transmitter.
7 DAT1_S GND ✅ TMDS Data1 shield pin correctly connected to ground for EMI shielding.
8 DAT1- HDMI_OUT_TX1_DN ✅ TMDS Data1- pin correctly connected through common mode choke L16 and AC coupling capacitor C405 to the HDMI transmitter.
9 DAT0+ HDMI_OUT_TX0_DP ✅ TMDS Data0+ pin correctly connected through common mode choke L15 and AC coupling capacitor C402 to the HDMI transmitter.
10 DAT0_S GND ✅ TMDS Data0 shield pin correctly connected to ground for EMI shielding.
11 DAT0- HDMI_OUT_TX0_DN ✅ TMDS Data0- pin correctly connected through common mode choke L15 and AC coupling capacitor C403 to the HDMI transmitter.
12 CLK+ HDMI_OUT_CLK_DP ✅ TMDS Clock+ pin correctly connected through common mode choke L14 and AC coupling capacitor C400 to the HDMI transmitter.
13 CLK_S GND ✅ TMDS Clock shield pin correctly connected to ground for EMI shielding.
14 CLK- HDMI_OUT_CLK_DN ✅ TMDS Clock- pin correctly connected through common mode choke L14 and AC coupling capacitor C401 to the HDMI transmitter.
15 CEC C_HDMI_CEC ✅ CEC pin correctly connected through U2 ESD protection to the system CEC signal with appropriate pull-up resistor.
16 DDC/CEC_GND GND ✅ DDC/CEC ground pin correctly connected to system ground.
17 SCL C_HDMI_SCL ✅ DDC SCL pin correctly connected through U2 ESD protection to the system I2C clock signal with appropriate pull-up resistor.
18 SDA C_HDMI_SDA ✅ DDC SDA pin correctly connected through U2 ESD protection to the system I2C data signal with appropriate pull-up resistor.
19 +5V D5_0V_HDMI ✅ 5V power pin correctly connected through ferrite bead L7 to the charge pump output of U2 with appropriate decoupling.
20 MTG1 GND_EARTH ✅ Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding.
21 MTG2 GND_EARTH ✅ Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding.
22 MTG3 GND_EARTH ✅ Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding.
23 MTG4 GND_EARTH ✅ Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding.
C161 - 2267-0004 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to main circuit ground (GND). This is the circuit ground side of an EMI suppression capacitor between circuit ground and chassis ground.
2 2 GND_EARTH ✅ Connected to chassis/earth ground (GND_EARTH) from HDMI connector shield. This is the chassis ground side of an EMI suppression capacitor.
C16 - 123-0004415 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to main circuit ground (GND). Component is marked DNI (Do Not Install), so it is electrically absent from the circuit.
2 2 GND_EARTH ✅ Connected to chassis/earth ground (GND_EARTH). Component is marked DNI (Do Not Install), so it is electrically absent from the circuit.
R29 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_CEC ✅ 10K ohm pull-up resistor for HDMI CEC line on the system side of the level translator U2.
2 2 +V1P8S ✅ 10K ohm pull-up resistor for HDMI CEC line on the system side of the level translator U2.
R28 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_DDCCLK ✅ 10K ohm pull-up resistor for HDMI DDC clock line (I2C SCL) on the system side of the level translator U2.
2 2 +V1P8S ✅ 10K ohm pull-up resistor for HDMI DDC clock line (I2C SCL) on the system side of the level translator U2.
R30 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_DDCDAT ✅ 10K ohm pull-up resistor for HDMI DDC data line (I2C SDA) on the system side of the level translator U2.
2 2 +V1P8S ✅ 10K ohm pull-up resistor for HDMI DDC data line (I2C SDA) on the system side of the level translator U2.
U32 - AP2172MPG ✅

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Pin Designator Pin Name Net Correct? Analysis
1 GND GND ✅ Ground pin correctly connected to GND net.
2 IN +USBVCC ✅ Input voltage pin correctly connected to +USBVCC with proper bypass capacitors.
3 EN1 USB_HOST_EN0 ✅ Enable 1 input correctly connected through level shifter U4 from SOC, with DNI pull-down resistor.
4 EN2 USB_HOST_EN1 ✅ Enable 2 input correctly connected through level shifter U4 from SOC, with DNI pull-down resistor.
5 OC2# SOC_USB_HOST_OC1 ✅ Over-current flag 2 output connected to SOC. No visible external pull-up resistor, likely relying on SOC internal pull-up.
6 OUTB USBP2 ✅ Output B correctly connected through ferrite bead L2 to VBUS2 with proper output capacitors.
7 OUTA USBP1 ✅ Output A correctly connected through ferrite bead L1 to VBUS1 with proper output capacitors.
8 OC1# SOC_USB_HOST_OC0 ✅ Over-current flag 1 output connected to SOC. No visible external pull-up resistor, likely relying on SOC internal pull-up.
9 GND_PAD GND ✅ Exposed pad correctly connected to GND for thermal and electrical grounding.
R116 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 USB_HOST_BUFF_ENB ✅ Connected to USB_HOST_BUFF_ENB, which drives the OE (output enable) pin of level translator U4.
2 2 +V1P8A ✅ Connected to +V1P8A supply, providing the pull-up voltage reference for the OE signal.
R117 - 110-0001984 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND, providing the pull-down reference.
2 2 SOC_USB_HOST_EN1 ✅ Connected to SOC_USB_HOST_EN1, providing pull-down functionality to ensure a defined low state when not actively driven by the SOC.
U4 - NTS0102GT ✅

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Pin Designator Pin Name Net Correct? Analysis
1 B2 USB_HOST_EN0 ✅ B2 output translates SOC_USB_HOST_EN0 to USB_HOST_EN0 for USB power switch EN1.
2 GND GND ✅ GND pin correctly connected to ground.
3 VCCA +V1P8A ✅ VCCA supply correctly connected to +V1P8A for SOC-side voltage level.
4 A2 SOC_USB_HOST_EN0 ✅ A2 input receives SOC_USB_HOST_EN0 signal for translation to B-side.
5 A1 SOC_USB_HOST_EN1 ✅ A1 input receives SOC_USB_HOST_EN1 signal for translation to B-side.
6 OE USB_HOST_BUFF_ENB ✅ OE pin pulled high to VCCA through R116 to enable the translator by default.
7 VCCB +USBVCC ✅ VCCB supply correctly connected to +USBVCC for USB-side voltage level.
8 B1 USB_HOST_EN1 ✅ B1 output translates SOC_USB_HOST_EN1 to USB_HOST_EN1 for USB power switch EN2.
U9 - TPD4S012 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 D+ USB_H0 ✅ D+ pin provides ESD protection for USB port A high-speed data line. Connected to USB_H0 net which routes through common mode choke CHOKE4 to USB connector pin 3 (DA+).
2 D- USB_L0 ✅ D- pin provides ESD protection for USB port A high-speed data line. Connected to USB_L0 net which routes through common mode choke CHOKE4 to USB connector pin 2 (DA-).
3 ID ✅ ID pin is left unconnected. This is acceptable per datasheet as ID pin can be left floating if not used in the application.
4 GND GND ✅ GND pin is correctly connected to the ground net, providing the ground reference for the ESD protection device.
5 NC ✅ NC pin is correctly left unconnected as it is not internally connected per the datasheet.
6 VBUS VBUS1 ✅ VBUS pin provides ESD protection for USB port A power line. Connected to VBUS1 net with proper decoupling capacitors and routes to USB connector pin 1 (VBUSA).
U8 - TPD4S012 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 D+ USB_H1 ✅ D+ pin provides ESD protection for USB port B high-speed data line. Connected to USB_H1 net which routes through common mode choke CHOKE3 to USB connector pin 12 (DB+).
2 D- USB_L1 ✅ D- pin provides ESD protection for USB port B high-speed data line. Connected to USB_L1 net which routes through common mode choke CHOKE3 to USB connector pin 11 (DB-).
3 ID ✅ ID pin is left unconnected. This is acceptable per datasheet as ID pin can be left floating if not used in the application.
4 GND GND ✅ GND pin is correctly connected to the ground net, providing the ground reference for the ESD protection device.
5 NC ✅ NC pin is correctly left unconnected as it is not internally connected per the datasheet.
6 VBUS VBUS2 ✅ VBUS pin provides ESD protection for USB port B power line. Connected to VBUS2 net with proper decoupling capacitors and routes to USB connector pin 10 (VBUSB).
U29 - TPD4USB30 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 D1+ USB3_TX0P_C ✅ D1+ pin is connected to USB3_TX0P_C net, which routes to the USB connector's SSTX+ pin. This provides ESD protection for the USB 3.0 transmit positive differential signal.
2 D1- USB3_TX0N_C ✅ D1- pin is connected to USB3_TX0N_C net, which routes to the USB connector's SSTX- pin. This provides ESD protection for the USB 3.0 transmit negative differential signal.
3 GND1 GND ✅ GND1 pin is correctly connected to the GND net, providing ground reference for the ESD protection device.
4 D2+ USB3_RX0P_C ✅ D2+ pin is connected to USB3_RX0P_C net, which routes to the USB connector's SSRX+ pin. This provides ESD protection for the USB 3.0 receive positive differential signal.
5 D2- USB3_RX0N_C ✅ D2- pin is connected to USB3_RX0N_C net, which routes to the USB connector's SSRX- pin. This provides ESD protection for the USB 3.0 receive negative differential signal.
6 NC4 USB3_RX0N_C ✅ NC4 pin is connected to USB3_RX0N_C net (same as D2-). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation.
7 NC3 USB3_RX0P_C ✅ NC3 pin is connected to USB3_RX0P_C net (same as D2+). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation.
8 GND2 GND ✅ GND2 pin is correctly connected to the GND net, providing a second ground reference for the ESD protection device.
9 NC2 USB3_TX0N_C ✅ NC2 pin is connected to USB3_TX0N_C net (same as D1-). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation.
10 NC1 USB3_TX0P_C ✅ NC1 pin is connected to USB3_TX0P_C net (same as D1+). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation.
USB1 - 258-0004503 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VBUSA VBUS1 ✅ VBUSA provides power to USB port A. Connected to VBUS1 net with proper decoupling and power switching through U32.
2 DA- USB_L0 ✅ DA- is the USB 2.0 differential pair negative signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9.
3 DA+ USB_H0 ✅ DA+ is the USB 2.0 differential pair positive signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9.
4 GNDA GND ✅ GNDA is the ground connection for USB port A, correctly connected to the GND net.
5 SSRX- USB3_RX0N_C ✅ SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected through common mode choke CHOKE1 with ESD protection from U29.
6 SSRX+ USB3_RX0P_C ✅ SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected through common mode choke CHOKE1 with ESD protection from U29.
7 GND_DRAIN GND ✅ GND_DRAIN is a drain/shield ground connection, correctly connected to the GND net.
8 SSTX- USB3_TX0N_C ✅ SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C191.
9 SSTX+ USB3_TX0P_C ✅ SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C192.
10 VBUSB VBUS2 ✅ VBUSB provides power to USB port B. Connected to VBUS2 net with proper decoupling and power switching through U32.
11 DB- USB_L1 ✅ DB- is the USB 2.0 differential pair negative signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8.
12 DB+ USB_H1 ✅ DB+ is the USB 2.0 differential pair positive signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8.
13 GNDB GND ✅ GNDB is the ground connection for USB port B, correctly connected to the GND net.
MH1 SHIELD1 GND_EARTH ✅ Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.
MH2 SHIELD2 GND_EARTH ✅ Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.
MH3 SHIELD3 GND_EARTH ✅ Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.
MH4 SHIELD4 GND_EARTH ✅ Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.
C192 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 USB3_TXP0 ✅ Pin 1 is connected to USB3_TXP0, the positive SuperSpeed transmit signal from the SOC before AC coupling.
2 2 USB3_TX0P-R ✅ Pin 2 is connected to USB3_TX0P-R, the AC-coupled positive SuperSpeed transmit signal going to CHOKE2.
C191 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 USB3_TXN0 ✅ Pin 1 is connected to USB3_TXN0, the negative SuperSpeed transmit signal from the SOC before AC coupling.
2 2 USB3_TX0N-R ✅ Pin 2 is connected to USB3_TX0N-R, the AC-coupled negative SuperSpeed transmit signal going to CHOKE2.
CHOKE2 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 USB3_TX0P-R ✅ IN1 is connected to USB3_TX0P-R, the AC-coupled positive SuperSpeed transmit signal from the SOC. This pin correctly receives the positive signal after AC coupling for common mode filtering.
3 IN2 USB3_TX0N-R ✅ IN2 is connected to USB3_TX0N-R, the AC-coupled negative SuperSpeed transmit signal from the SOC. This pin correctly receives the negative signal after AC coupling for common mode filtering.
4 OUT2 USB3_TX0N_C ✅ OUT2 is connected to USB3_TX0N_C, the filtered negative SuperSpeed transmit signal going to the connector. The polarity mapping (IN2→OUT2 for negative) is correct for a common mode choke.
6 OUT1 USB3_TX0P_C ✅ OUT1 is connected to USB3_TX0P_C, the filtered positive SuperSpeed transmit signal going to the connector. The polarity mapping (IN1→OUT1 for positive) is correct for a common mode choke.
CHOKE1 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 USB3_RX0N_C ✅ IN1 is connected to USB3_RX0N_C, the negative SuperSpeed receive signal from the USB connector. This pin correctly receives the negative signal from the connector side for common mode filtering.
3 IN2 USB3_RX0P_C ✅ IN2 is connected to USB3_RX0P_C, the positive SuperSpeed receive signal from the USB connector. This pin correctly receives the positive signal from the connector side for common mode filtering.
4 OUT2 USB3_RXP0 ✅ OUT2 is connected to USB3_RXP0, the filtered positive SuperSpeed receive signal going to the SOC. The polarity mapping (IN2→OUT2 for positive) is correct for a common mode choke.
6 OUT1 USB3_RXN0 ✅ OUT1 is connected to USB3_RXN0, the filtered negative SuperSpeed receive signal going to the SOC. The polarity mapping (IN1→OUT1 for negative) is correct for a common mode choke.
CHOKE4 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 USB_DN0 ✅ IN1 is connected to USB_DN0, which is the D- signal from the SOC for USB port 0. This pin correctly receives the negative differential signal of the USB 2.0 data pair.
3 IN2 USB_DP0 ✅ IN2 is connected to USB_DP0, which is the D+ signal from the SOC for USB port 0. This pin correctly receives the positive differential signal of the USB 2.0 data pair.
4 OUT2 USB_H0 ✅ OUT2 is connected to USB_H0, which routes to the D+ pin of USB connector port A and ESD protection device U9. This pin correctly outputs the positive differential signal.
6 OUT1 USB_L0 ✅ OUT1 is connected to USB_L0, which routes to the D- pin of USB connector port A and ESD protection device U9. This pin correctly outputs the negative differential signal.
CHOKE3 - 3142-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 IN1 USB_DN1 ✅ IN1 is connected to USB_DN1, which is the D- signal from the SOC for USB port 1. This pin correctly receives the negative differential signal of the USB 2.0 data pair.
3 IN2 USB_DP1 ✅ IN2 is connected to USB_DP1, which is the D+ signal from the SOC for USB port 1. This pin correctly receives the positive differential signal of the USB 2.0 data pair.
4 OUT2 USB_H1 ✅ OUT2 is connected to USB_H1, which routes to the D+ pin of USB connector port B and ESD protection device U8. This pin correctly outputs the positive differential signal.
6 OUT1 USB_L1 ✅ OUT1 is connected to USB_L1, which routes to the D- pin of USB connector port B and ESD protection device U8. This pin correctly outputs the negative differential signal.
J10 - 158-0004534 ❌

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Pin Designator Pin Name Net Correct? Analysis
57 57 XDP_H_TDO ❌
XDP test data out signal with unusual 51 ohm connection to +V1P8A power rail. This configuration is highly atypical for a JTAG TDO signal and likely incorrect.
  • Pin 57 is connected to net XDP_H_TDO (from schematic)
  • Resistor R21 (51 ohm, part 110-0002078) connects between +V1P8A and XDP_H_TDO (from schematic)
  • XDP_H_TDO is the test data output signal for the XDP/JTAG debug interface (reasoning)
  • TDO is typically an output signal from the device under test and is driven by the target device being debugged (reasoning)
  • A 51 ohm resistor to power rail acts as a pull-up, but this value is extremely low compared to typical pull-up resistors which range from 1K to 10K ohms (reasoning)
  • When TDO is driven low by the target device, this 51 ohm pull-up would draw approximately 35mA (1.8V / 51Ω), which is unusually high current for a logic signal and could exceed the drive capability of typical JTAG outputs (reasoning)
  • If series termination is intended for signal integrity, the resistor should be placed in series with the signal path (between the driver and load), not connected to the power rail (reasoning)
  • Other XDP/JTAG signals on the connector (TDI on pin 58, TMS on pin 56, TCK on pin 54, TRST on pin 52) do not show similar resistor connections to power, making this connection inconsistent with the rest of the debug interface design (from schematic)
  • Standard JTAG interface design does not typically require strong pull-ups on TDO outputs, as the signal is actively driven by the target device (reasoning)
  • This connection should be reviewed and verified against the system debug interface requirements, as it appears to be either a design error or an undocumented special requirement (reasoning)
1 1 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
2 2 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
13 13 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
14 14 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
25 25 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
26 26 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
37 37 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
38 38 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
49 49 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
50 50 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
59 59 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
60 60 GND ✅ Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals.
3 3 mSATA_TX_P ✅ mSATA differential transmit pair (TX_P and TX_N) for SATA interface on the expansion connector.
5 5 mSATA_TX_N ✅ mSATA differential transmit pair (TX_P and TX_N) for SATA interface on the expansion connector.
4 4 mSATA_RX_P ✅ mSATA differential receive pair (RX_P and RX_N) for SATA interface on the expansion connector.
6 6 mSATA_RX_N ✅ mSATA differential receive pair (RX_P and RX_N) for SATA interface on the expansion connector.
7 7 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
8 8 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
19 19 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
20 20 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
31 31 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
32 32 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
43 43 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
44 44 +5VSB ✅ 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop.
9 9 mPCIE_REFCLK_P ✅ mPCIE differential reference clock pair (REFCLK_P and REFCLK_N) for PCIe interface on the expansion connector.
11 11 mPCIE_REFCLK_N ✅ mPCIE differential reference clock pair (REFCLK_P and REFCLK_N) for PCIe interface on the expansion connector.
10 10 USB_HOST_DP ✅ USB host differential data pair (DP and DN) for USB interface on the expansion connector.
12 12 USB_HOST_DN ✅ USB host differential data pair (DP and DN) for USB interface on the expansion connector.
15 15 mPCIE_TX_P ✅ mPCIE differential transmit pair (TX_P and TX_N) for PCIe interface on the expansion connector.
17 17 mPCIE_TX_N ✅ mPCIE differential transmit pair (TX_P and TX_N) for PCIe interface on the expansion connector.
16 16 mPCIE_RX_N ✅ mPCIE differential receive pair (RX_N and RX_P) for PCIe interface. Note that the polarity appears inverted (pin 16 is RX_N, pin 18 is RX_P), which is explicitly documented as intentional for routing purposes.
18 18 mPCIE_RX_P ✅ mPCIE differential receive pair (RX_N and RX_P) for PCIe interface. Note that the polarity appears inverted (pin 16 is RX_N, pin 18 is RX_P), which is explicitly documented as intentional for routing purposes.
21 21 I2C6_SCL ✅ I2C clock signal (SCL) with 10K pullup resistor to +V1P8S for I2C interface on the expansion connector.
22 22 mPCIE_WAKEB ✅ mPCIE wake signal (active low) for PCIe power management on the expansion connector.
23 23 I2C6_SDA ✅ I2C data signal (SDA) with 10K pullup resistor to +V1P8S for I2C interface on the expansion connector.
24 24 mPCIe_CLKREQ3_B ✅ mPCIE clock request signal (active low) for PCIe power management on the expansion connector.
27 27 EXP_GPIO1 ✅ General purpose I/O expansion pins for the expansion connector.
28 28 EXP_GPIO3 ✅ General purpose I/O expansion pins for the expansion connector.
29 29 EXP_GPIO2 ✅ General purpose I/O expansion pins for the expansion connector.
30 30 EXP_GPIO4 ✅ General purpose I/O expansion pins for the expansion connector.
33 33 XDP_H_OBSDATA_A1 ✅ XDP observation data bus signals (4-bit) for debug interface on the expansion connector.
34 34 XDP_H_OBSDATA_A0 ✅ XDP observation data bus signals (4-bit) for debug interface on the expansion connector.
35 35 XDP_H_OBSDATA_A2 ✅ XDP observation data bus signals (4-bit) for debug interface on the expansion connector.
36 36 XDP_H_OBSDATA_A3 ✅ XDP observation data bus signals (4-bit) for debug interface on the expansion connector.
39 39 XDP_H_PRDYB ✅ XDP ready signal (active low) for debug interface handshaking on the expansion connector.
40 40 XDP_H_PREQB_PB ✅ XDP request signal (active low, push-button) buffered through U1 with 200 ohm pullup to +V1P8A for debug interface on the expansion connector.
41 41 HOOK0 ✅ HOOK0 debug signal connected through 1K resistor to PMC_RSMRST for test/debug access on the expansion connector.
42 42 HOOK1 ✅ HOOK1 debug signal connected through 0 ohm resistor to FP_PWRBTN for test/debug access on the expansion connector.
45 45 HOOK2 ✅ HOOK2 debug signal connected through 1K resistor to PMC_CORE_PWROK for test/debug access on the expansion connector.
46 46 PMC_RSTBTN ✅ PMC reset button signal with 1K pullup to +V1P8S and 0.1uF filter capacitor for the expansion connector.
47 47 HOOK6 ✅ HOOK6 debug signal connected through 1K resistor to PMC_PLTRST_R_V1P8 for test/debug access on the expansion connector.
48 48 ILB_RTC_TESTB ✅ ILB RTC test signal (active low) with 1K pullup to +RTCVCC and 1uF filter capacitor for the expansion connector.
51 51 HOOK4 ✅ HOOK4 debug signal connected through 0 ohm resistor to +3VSB for test/debug access on the expansion connector.
52 52 XDP_H_TRSTB ✅ XDP test reset signal (active low) for JTAG/debug interface on the expansion connector.
53 53 HOOK5 ✅ HOOK5 debug signal connected through 0 ohm resistor to +V1P8S for test/debug access on the expansion connector.
54 54 XDP_H_TCK ✅ XDP test clock signal for JTAG/debug interface on the expansion connector.
55 55 +V1P8A ✅ 1.8V analog power supply pin for the expansion connector with 0.1uF decoupling capacitor.
56 56 XDP_H_TMS ✅ XDP test mode select signal for JTAG/debug interface on the expansion connector.
58 58 XDP_H_TDI ✅ XDP test data in signal for JTAG/debug interface on the expansion connector.
C5 - 0.1uF 10% 25V 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND, providing ground reference for bypass capacitor.
2 2 +V1P8A ✅ Connected to +V1P8A, providing bypass capacitance for U1 power supply.
U1 - SN74AUP1G34 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 NC ✅ No Connect pin, correctly left unconnected.
2 A XDP_H_PREQB_PB ✅ Input pin A connected to XDP_H_PREQB_PB with 200 ohm pull-up resistor to +V1P8A.
3 GND GND ✅ Ground pin correctly connected to GND net.
4 Y XDP_H_PREQB ✅ Output pin Y correctly connected to XDP_H_PREQB net.
5 VCC +V1P8A ✅ VCC power pin correctly connected to +V1P8A with appropriate bypass capacitor C5.
R3 - 200 ohm 1% 1/10W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 XDP_H_PREQB_PB ✅ Connected to XDP_H_PREQB_PB, providing pull-up for buffer input.
2 2 +V1P8A ✅ Connected to +V1P8A power rail, providing pull-up voltage reference.
R13 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 I2C6_SCL ✅ Connected to I2C6_SCL signal line, providing pull-up path to +V1P8S through the 10K resistor.
2 2 +V1P8S ✅ Connected to +V1P8S power rail, providing the pull-up voltage for the I2C6_SCL line.
R14 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 I2C6_SDA ✅ Connected to I2C6_SDA signal line, providing pull-up path to +V1P8S through the 10K resistor.
2 2 +V1P8S ✅ Connected to +V1P8S power rail, providing the pull-up voltage for the I2C6_SDA line.
R15 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 PMC_RSMRST ✅ 1K series resistor connecting PMC_RSMRST signal to HOOK0 pin on expansion connector J10 pin 41. Provides signal protection and current limiting for the expansion interface.
2 2 HOOK0 ✅ 1K series resistor connecting PMC_RSMRST signal to HOOK0 pin on expansion connector J10 pin 41. Provides signal protection and current limiting for the expansion interface.
R16 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 PMC_CORE_PWROK ✅ 1K series resistor connecting PMC_CORE_PWROK signal to HOOK2 pin on expansion connector J10 pin 45. Provides signal protection and current limiting for the expansion interface.
2 2 HOOK2 ✅ 1K series resistor connecting PMC_CORE_PWROK signal to HOOK2 pin on expansion connector J10 pin 45. Provides signal protection and current limiting for the expansion interface.
R17 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 PMC_PLTRST_R_V1P8 ✅ 1K series resistor connecting PMC_PLTRST_R_V1P8 signal to HOOK6 pin on expansion connector J10 pin 47. Provides signal protection and current limiting for the expansion interface.
2 2 HOOK6 ✅ 1K series resistor connecting PMC_PLTRST_R_V1P8 signal to HOOK6 pin on expansion connector J10 pin 47. Provides signal protection and current limiting for the expansion interface.
R18 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +3VSB ✅ 0 ohm jumper connecting +3VSB power supply to HOOK4 pin on expansion connector J10 pin 51. Allows power distribution to expansion connector with option to disconnect if needed.
2 2 HOOK4 ✅ 0 ohm jumper connecting +3VSB power supply to HOOK4 pin on expansion connector J10 pin 51. Allows power distribution to expansion connector with option to disconnect if needed.
R20 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ 0 ohm jumper connecting +V1P8S power supply to HOOK5 pin on expansion connector J10 pin 53. Allows power distribution to expansion connector with option to disconnect if needed.
2 2 HOOK5 ✅ 0 ohm jumper connecting +V1P8S power supply to HOOK5 pin on expansion connector J10 pin 53. Allows power distribution to expansion connector with option to disconnect if needed.
R21 - 110-0002078 ❌

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ❌
R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.
  • Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail (from schematic)
  • Pin 2 of R21 is connected to the XDP_H_TDO net (from schematic)
  • XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface (from schematic)
  • R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package (from schematic)
  • The resistor is configured as a pull-up resistor from the signal line to the power rail (reasoning)
  • TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test (reasoning)
  • When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA (reasoning)
  • 35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device (reasoning)
  • Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption (reasoning)
  • Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value (reasoning)
  • No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value (from schematic)
  • The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application (reasoning)
  • While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values (reasoning)
  • The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value (reasoning)
2 2 XDP_H_TDO ❌
R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.
  • Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail (from schematic)
  • Pin 2 of R21 is connected to the XDP_H_TDO net (from schematic)
  • XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface (from schematic)
  • R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package (from schematic)
  • The resistor is configured as a pull-up resistor from the signal line to the power rail (reasoning)
  • TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test (reasoning)
  • When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA (reasoning)
  • 35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device (reasoning)
  • Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption (reasoning)
  • Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value (reasoning)
  • No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value (from schematic)
  • The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application (reasoning)
  • While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values (reasoning)
  • The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value (reasoning)
U42 - WGI210AT ✅

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Pin Designator Pin Name Net Correct? Analysis
1 LAN_PWR_GOOD $18N3538 ✅ LAN_PWR_GOOD is pulled up to +3VSB_LAN through a 10K resistor, indicating this is a power good output signal.
2 NC_SI_CLK_IN $18N3372 ✅ NC_SI_CLK_IN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal.
3 NC_SI_CRS_DV $18N3374 ✅ NC_SI_CRS_DV is terminated to ground through a 1K resistor, which is appropriate for an unused input signal.
4 JTAG_TDO ✅ JTAG_TDO is left unconnected, which is acceptable for a JTAG output pin when JTAG is not being used.
5 NC_SI_RXD1 $18N3305 ✅ NC_SI_RXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
6 NC_SI_RXD0 $18N3303 ✅ NC_SI_RXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
7 NC_SI_TX_EN $18N3376 ✅ NC_SI_TX_EN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal.
8 NC_SI_TXD1 $18N3301 ✅ NC_SI_TXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
9 NC_SI_TXD0 $18N3299 ✅ NC_SI_TXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
10 VDD3P3_10 +3VSB_LAN ✅ VDD3P3_10 is correctly connected to the +3VSB_LAN power rail.
11 VDD0P9_11 +0V9_LAN ✅ VDD0P9_11 is correctly connected to the +0V9_LAN power rail.
12 NVM_SI $18N2399 ✅ NVM_SI is correctly connected to the SPI flash MOSI line through a 33.2 ohm series resistor for signal integrity.
13 NVM_SK $18N2397 ✅ NVM_SK is correctly connected to the SPI flash clock line through a 33.2 ohm series resistor for signal integrity.
14 NVM_SO $18N3554 ✅ NVM_SO is correctly connected to the SPI flash MISO line through a 33.2 ohm series resistor for signal integrity.
15 NVM_CS_N $18N2395 ✅ NVM_CS_N is correctly connected to the SPI flash chip select line through a 33.2 ohm series resistor for signal integrity.
16 PE_WAKE_N PMC_PCIE_WAKE ✅ PE_WAKE_N is connected to the PCIe wake signal going to the system controller.
17 PE_RST_N PMC_PLTRST_L ✅ PE_RST_N is connected to the platform reset signal from the system controller.
18 JTAG_TMS $18N3293 ✅ JTAG_TMS is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces.
19 JTAG_CLK $18N3295 ✅ JTAG_CLK is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces.
20 PE_TXN PCIE_C_RXP2 ✅ PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
21 PE_TXP PCIE_C_RXN2 ✅ PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
22 NC/INTVCC ✅ NC/INTVCC is left unconnected, which is acceptable as this pin can be either not connected or used for internal VCC depending on configuration.
23 PE_RXN PCIE_C_TXP2 ✅ PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
24 PE_RXP PCIE_C_TXN2 ✅ PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
25 PECLK_N PCIE_CLK-N2 ✅ PECLK_N is correctly connected to the PCIe reference clock negative signal.
26 PECLK_P PCIE_CLK-P2 ✅ PECLK_P is correctly connected to the PCIe reference clock positive signal.
27 VDD3P3_27 +3VSB_LAN ✅ VDD3P3_27 is correctly connected to the +3VSB_LAN power rail.
28 DEV_OFF_N $18N3540 ✅ DEV_OFF_N is pulled up to +3VSB_LAN through a 10K resistor, keeping the device enabled by default.
29 JTAG_TDI $18N3297 ✅ JTAG_TDI is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces.
30 LED1 LAN-LED1 ✅ LED1 is connected to an off-page signal for LED control.
31 LED0 LAN-LED0 ✅ LED0 is correctly connected to the RJ45 connector LED with appropriate filtering.
32 VDD0P9_32 +0V9_LAN ✅ VDD0P9_32 is correctly connected to the +0V9_LAN power rail.
33 LED2 LAN-LED2 ✅ LED2 is correctly connected to the RJ45 connector LED through a current limiting resistor.
34 SMB_CLK LAN-SMB-CLK ✅ SMB_CLK is connected to an off-page SMBus clock signal.
35 SMB_ALRT_N LAN-SMB-ALERT# ✅ SMB_ALRT_N is connected to an off-page SMBus alert signal.
36 SMB_DATA LAN-SMB-DATA ✅ SMB_DATA is connected to an off-page SMBus data signal.
37 CBOT $18N2590 ✅ CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators.
40 CTOP $18N2588 ✅ CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators.
38 VDD0P9_OUT +0V9_LAN ✅ VDD0P9_OUT is connected to the +0V9_LAN rail, indicating the internal 0.9V regulator output is being used.
39 VDD1P5_OUT +1V5_LAN ✅ VDD1P5_OUT is connected to the +1V5_LAN rail, indicating the internal 1.5V regulator output is being used.
41 VDD3P3_41 +3VSB_LAN ✅ VDD3P3_41 is correctly connected to the +3VSB_LAN power rail.
42 VDD0P9_42 +0V9_LAN ✅ VDD0P9_42 is correctly connected to the +0V9_LAN power rail.
43 NC_SI_ARB_IN ✅ NC_SI_ARB_IN is left unconnected, which is acceptable for an unused signal.
44 NC_SI_ARB_OUT ✅ NC_SI_ARB_OUT is left unconnected, which is acceptable for an unused output signal.
45 XTAL2 LAN_XTAL2 ✅ XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors.
46 XTAL1 LAN_XTAL1 ✅ XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors.
47 VDD1P5_47 +1V5_LAN ✅ VDD1P5_47 is correctly connected to the +1V5_LAN power rail.
48 RSET LAN_RSET ✅ RSET is correctly connected to ground through a 4.99K resistor to set the PHY reference current.
49 MDI_MINUS3/SER_N MDI_N3 ✅ MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3.
50 MDI_PLUS3/SER_P MDI_P3 ✅ MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3.
51 VDD3P3_51 +3VSB_LAN ✅ VDD3P3_51 is correctly connected to the +3VSB_LAN power rail.
52 MDI_MINUS2/SET_N MDI_N2 ✅ MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2.
53 MDI_PLUS2 MDI_P2 ✅ MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2.
54 MDI_MINUS1/SRDS_SIG_DET MDI_N1 ✅ MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1.
55 MDI_PLUS1/SFP_I2C_CLK MDI_P1 ✅ MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1.
56 VDD1P5_56 +1V5_LAN ✅ VDD1P5_56 is correctly connected to the +1V5_LAN power rail.
57 MDI_MINUS0/SFP_I2C_DATA MDI_N0 ✅ MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0.
58 MDI_PLUS0/NC MDI_P0 ✅ MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0.
59 VDD0P9_59 +0V9_LAN ✅ VDD0P9_59 is correctly connected to the +0V9_LAN power rail.
60 SDP3 ✅ SDP3 is left unconnected, which is acceptable for an unused software-defined pin.
61 SDP1/PCIE_DIS ✅ SDP1/PCIE_DIS is left unconnected, which is acceptable for an unused software-defined pin.
62 SDP2 ✅ SDP2 is left unconnected, which is acceptable for an unused software-defined pin.
63 SDP0 ✅ SDP0 is left unconnected, which is acceptable for an unused software-defined pin.
64 VDD3P3_64 +3VSB_LAN ✅ VDD3P3_64 is correctly connected to the +3VSB_LAN power rail.
65 GND_PAD GND ✅ GND_PAD is correctly connected to the ground plane.
U43 - 4356-0082 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 CS# $18N2439 ✅ CS# (Chip Select) is correctly connected through series resistor R835 (33.2Ω) to the LAN controller U42 pin 15 (NVM_CS_N).
2 SO $18N3552 ✅ SO (Serial Output) is correctly connected through series resistor R833 (33.2Ω) to the LAN controller U42 pin 14 (NVM_SO).
3 WP# $18N3609 ✅ WP# (Write Protect) is correctly pulled high through R830 (10KΩ) to +3VSB_LAN, disabling hardware write protection as recommended by the datasheet.
4 GND GND ✅ GND is correctly connected to the ground plane.
5 SI $18N2435 ✅ SI (Serial Input) is correctly connected through series resistor R832 (33.2Ω) to the LAN controller U42 pin 12 (NVM_SI). A weak pull-up R848 (33.2KΩ) to +3VSB_LAN ensures a defined state.
6 SCK $18N2437 ✅ SCK (Serial Clock) is correctly connected through series resistor R834 (33.2Ω) to the LAN controller U42 pin 13 (NVM_SK).
7 HOLD# $18N3659 ✅ HOLD# is correctly pulled high through R831 (10KΩ) to +3VSB_LAN, keeping the hold function inactive as recommended by the datasheet.
8 VCC +3VSB_LAN ✅ VCC is correctly connected to +3VSB_LAN, which provides 3.3V power within the specified 2.7V to 3.6V operating range.
R832 - 1120-0003 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N2435 ✅ Series resistor on SI (MOSI) line between LAN controller and flash memory, correctly placed for signal integrity.
R833 - 1120-0003 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N3554 ✅ Series resistor on SO (MISO) line between flash memory and LAN controller, correctly placed for signal integrity.
R834 - 1120-0003 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N2437 ✅ Series resistor on SCK (clock) line between LAN controller and flash memory, correctly placed for signal integrity.
R835 - 1120-0003 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N2439 ✅ Series resistor on CS# (chip select) line between LAN controller and flash memory, correctly placed for signal integrity.
R829 - 1120-0011 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N3609 ✅ DNI pull-down resistor on WP# that would enable hardware write protection if installed. Correctly marked DNI to allow software-controlled write protection.
2 2 GND ✅ DNI pull-down resistor on WP# that would enable hardware write protection if installed. Correctly marked DNI to allow software-controlled write protection.
R830 - 1120-0011 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +3VSB_LAN ✅ Pull-up resistor on WP# that correctly implements the datasheet recommendation to connect WP to VCC.
2 2 $18N3609 ✅ Pull-up resistor on WP# that correctly implements the datasheet recommendation to connect WP to VCC.
R831 - 1120-0011 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +3VSB_LAN ✅ Pull-up resistor on HOLD# that correctly implements the datasheet recommendation to connect HOLD to VCC.
2 2 $18N3659 ✅ Pull-up resistor on HOLD# that correctly implements the datasheet recommendation to connect HOLD to VCC.
R848 - 1120-0359 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +3VSB_LAN ✅ Weak pull-up resistor on SI line that prevents floating when not driven by the controller.
2 2 $18N2435 ✅ Weak pull-up resistor on SI line that prevents floating when not driven by the controller.
R847 - 1120-0032 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N2435 ✅ DNI pull-down resistor on SI that is correctly not installed, as it would create a problematic voltage divider with R848.
2 2 GND ✅ DNI pull-down resistor on SI that is correctly not installed, as it would create a problematic voltage divider with R848.
C253 - 123-0001107 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN_XTAL2 ✅ Load capacitor connected to LAN_XTAL2 net, providing the required load capacitance for the crystal oscillator circuit.
2 2 GND ✅ Ground connection for the load capacitor, correctly connected to GND.
C252 - 123-0001107 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN_XTAL1 ✅ Load capacitor connected to LAN_XTAL1 net, providing the required load capacitance for the crystal oscillator circuit.
2 2 GND ✅ Ground connection for the load capacitor, correctly connected to GND.
X1 - 145-0004792 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN_XTAL2 ✅ Crystal pin connected to XTAL2 of U42 through LAN_XTAL2 net with 27pF load capacitor C253 to ground. This is one of the two active crystal oscillator pins.
2 2 GND ✅ Ground pin of the crystal package, correctly connected to GND for proper operation and EMI reduction.
3 3 LAN_XTAL1 ✅ Crystal pin connected to XTAL1 of U42 through LAN_XTAL1 net with 27pF load capacitor C252 to ground. This is the second active crystal oscillator pin.
4 4 GND ✅ Ground pin of the crystal package, correctly connected to GND for proper operation and EMI reduction.
R843 - 1120-0203 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN-LED1 ✅ Current-limiting resistor for LED1 circuit in the RJ45 connector, providing approximately 4.3mA LED current.
2 2 LINK-LED-N ✅ Current-limiting resistor for LED1 circuit in the RJ45 connector, providing approximately 4.3mA LED current.
R844 - 1120-0203 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN-LED2 ✅ Current-limiting resistor for LED2 circuit in the RJ45 connector, providing approximately 4.3mA LED current.
2 2 1G-LED-N ✅ Current-limiting resistor for LED2 circuit in the RJ45 connector, providing approximately 4.3mA LED current.
C429 - 2220-0039 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LINK-LED-N ✅ EMI filtering capacitor on LINK-LED-N signal to reduce high-frequency noise emissions.
2 2 GND ✅ EMI filtering capacitor on LINK-LED-N signal to reduce high-frequency noise emissions.
C430 - 2220-0039 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 1G-LED-N ✅ EMI filtering capacitor on 1G-LED-N signal to reduce high-frequency noise emissions.
2 2 GND ✅ EMI filtering capacitor on 1G-LED-N signal to reduce high-frequency noise emissions.
C431 - 2220-0039 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 LAN-LED0 ✅ EMI filtering capacitor on LAN-LED0 signal to reduce high-frequency noise emissions.
2 2 GND ✅ EMI filtering capacitor on LAN-LED0 signal to reduce high-frequency noise emissions.
C426 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N3856 ✅ Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression.
2 2 GND ✅ Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression.
C427 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N3856 ✅ Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression.
2 2 GND ✅ Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression.
C428 - 2222-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N3856 ✅ Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, providing low-frequency filtering in parallel combination.
2 2 GND ✅ Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, providing low-frequency filtering in parallel combination.
J11 - RJ45 W XFMR GRN-ORN GRN LEDS ✅

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Pin Designator Pin Name Net Correct? Analysis
1 MD1+ MDI_P0 ✅ MD1+ connects to MDI_P0, the positive differential signal of MDI pair 0 to the LAN controller U42 pin 58.
2 MD1- MDI_N0 ✅ MD1- connects to MDI_N0, the negative differential signal of MDI pair 0 to the LAN controller U42 pin 57.
3 MD2+ MDI_P1 ✅ MD2+ connects to MDI_P1, the positive differential signal of MDI pair 1 to the LAN controller U42 pin 55.
4 MD2- MDI_N1 ✅ MD2- connects to MDI_N1, the negative differential signal of MDI pair 1 to the LAN controller U42 pin 54.
5 CT1 $18N3856 ✅ CT1 is the first center tap connection, properly bypassed to GND through parallel capacitors C426, C427, and C428.
6 CT2 $18N3856 ✅ CT2 is the second center tap connection, properly bypassed to GND through the same parallel capacitors as CT1.
7 MD3+ MDI_P2 ✅ MD3+ connects to MDI_P2, the positive differential signal of MDI pair 2 to the LAN controller U42 pin 53.
8 MD3- MDI_N2 ✅ MD3- connects to MDI_N2, the negative differential signal of MDI pair 2 to the LAN controller U42 pin 52.
9 MD4+ MDI_P3 ✅ MD4+ connects to MDI_P3, the positive differential signal of MDI pair 3 to the LAN controller U42 pin 50.
10 MD4- MDI_N3 ✅ MD4- connects to MDI_N3, the negative differential signal of MDI pair 3 to the LAN controller U42 pin 49.
11 LED2_AC1 LAN-LED0 ✅ LED2_AC1 connects to LAN-LED0 from U42 pin 31, forming one terminal of a bi-color LED with proper EMI filtering via C431.
12 LED2_AD1 1G-LED-N ✅ LED2_AD1 connects through R844 to LAN-LED2 from U42 pin 33, forming the other terminal of the bi-color LED with proper current limiting and EMI filtering.
13 LED1_C LINK-LED-N ✅ LED1_C is the cathode of LED1, connecting through R843 to U42 pin 30 with proper current limiting and EMI filtering.
14 LED1_A +3VSB_LAN ✅ LED1_A is the anode of LED1, correctly connected to +3VSB_LAN to provide power for the LED.
15 SHLD1 GND_EARTH ✅ SHLD1 is correctly connected to GND_EARTH for proper shield grounding and EMI/ESD protection.
16 SHLD2 GND_EARTH ✅ SHLD2 is correctly connected to GND_EARTH for proper shield grounding and EMI/ESD protection.
C425 - 2221-0017 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $18N2588 ✅ Connected to CTOP pin of U42 LAN controller. This capacitor is part of the internal voltage regulator charge pump circuit.
2 2 $18N2590 ✅ Connected to CBOT pin of U42 LAN controller, completing the charge pump capacitor connection.
FB12 - 3044-0010 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +3VSB ✅ Input pin connected to main +3VSB standby power rail. This ferrite bead filters the power supply to the LAN subsystem.
2 2 +3VSB_LAN ✅ Output pin connected to +3VSB_LAN rail that powers the LAN controller and associated circuitry.
C233 - 123-0004408 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pin 1 connects to the main circuit ground (GND). This is correct for a Y-capacitor application providing coupling between circuit ground and chassis ground.
2 2 GND_EARTH ✅ Pin 2 connects to chassis/earth ground (GND_EARTH). This is correct for a Y-capacitor application providing coupling between circuit ground and chassis ground.
U15 - NTS0104GU12 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VCCA +V1P8S ✅ VCCA pin connected to +V1P8S (1.8V supply). This provides the reference voltage for the A-side (lower voltage) of the translator.
2 A1 SIO_UART1_RTSB ✅ A1 pin connected to SIO_UART1_RTSB on the 1.8V side. This is the A-side (lower voltage) channel 1, properly paired with B1 for UART RTS flow control.
3 A2 SIO_UART1_CTSB ✅ A2 pin connected to SIO_UART1_CTSB on the 1.8V side. This is the A-side (lower voltage) channel 2, properly paired with B2 for UART CTS flow control.
4 A3 SIO_UART1_RXD ✅ A3 pin connected to SIO_UART1_RXD on the 1.8V side. This is the A-side (lower voltage) channel 3, properly paired with B3 for UART receive data.
5 A4 SIO_UART1_TXD ✅ A4 pin connected to SIO_UART1_TXD on the 1.8V side. This is the A-side (lower voltage) channel 4, properly paired with B4 for UART transmit data.
6 GND GND ✅ GND pin correctly connected to ground plane.
7 B4 UART1_TXD ✅ B4 pin connected to UART1_TXD on the 3.3V side. This is the B-side (higher voltage) channel 4, properly paired with A4 for UART transmit data.
8 B3 UART1_RXD ✅ B3 pin connected to UART1_RXD on the 3.3V side. This is the B-side (higher voltage) channel 3, properly paired with A3 for UART receive data.
9 B2 UART1_CTSB ✅ B2 pin connected to UART1_CTSB on the 3.3V side. This is the B-side (higher voltage) channel 2, properly paired with A2 for UART CTS flow control.
10 B1 UART1_RTSB ✅ B1 pin connected to UART1_RTSB on the 3.3V side. This is the B-side (higher voltage) channel 1, properly paired with A1 for UART RTS flow control.
11 VCCB +3VSB ✅ VCCB pin connected to +3VSB (3.3V standby supply). This provides the reference voltage for the B-side (higher voltage) of the translator.
12 OE PMC_PLTRST_R_V1P8 ✅ OE pin connected to PMC_PLTRST_R_V1P8, which enables the translator when the platform is out of reset.
U7 - NTS0102GT ✅

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Pin Designator Pin Name Net Correct? Analysis
1 B2 UART2_RXD ✅ B2 pin connected to UART2_RXD on the 3.3V side. This is the B-side (higher voltage) channel 2 of the bidirectional level translator, properly paired with A2.
2 GND GND ✅ GND pin correctly connected to ground plane.
3 VCCA +V1P8S ✅ VCCA pin connected to +V1P8S (1.8V supply). This provides the reference voltage for the A-side (lower voltage) of the translator.
4 A2 SIO_UART2_RXD ✅ A2 pin connected to SIO_UART2_RXD on the 1.8V side. This is the A-side (lower voltage) channel 2, properly paired with B2.
5 A1 SIO_UART2_TXD ✅ A1 pin connected to SIO_UART2_TXD on the 1.8V side. This is the A-side (lower voltage) channel 1, properly paired with B1.
6 OE PMC_PLTRST_R_V1P8 ✅ OE pin connected to PMC_PLTRST_R_V1P8, which enables the translator when the platform is out of reset.
7 VCCB +3VSB ✅ VCCB pin connected to +3VSB (3.3V standby supply). This provides the reference voltage for the B-side (higher voltage) of the translator.
8 B1 UART2_TXD ✅ B1 pin connected to UART2_TXD on the 3.3V side. This is the B-side (higher voltage) channel 1, properly paired with A1.
U10 - NTS0104GU12 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VCCA +V1P8A ✅ VCCA is correctly connected to +V1P8A, providing the 1.8V reference voltage for the A-side of the level translator.
2 A1 SOC_GPIO_S5_2 ✅ A1 is correctly connected to SOC_GPIO_S5_2, which is translated to GPIO_S5_2 on the B-side through B1.
3 A2 SOC_GPIO_S5_1 ✅ A2 is correctly connected to SOC_GPIO_S5_1, which is translated to GPIO_S5_1 on the B-side through B2.
4 A3 SOC_GPIO_S5_0 ✅ A3 is correctly connected to SOC_GPIO_S5_0, which is translated to GPIO_S5_0 on the B-side through B3.
5 A4 ✅ Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators.
7 B4 GND ✅ Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators.
6 GND GND ✅ GND is correctly connected to the ground net.
8 B3 GPIO_S5_0 ✅ B3 is correctly connected to GPIO_S5_0, which is the 3.3V translation of SOC_GPIO_S5_0 from A3.
9 B2 GPIO_S5_1 ✅ B2 is correctly connected to GPIO_S5_1, which is the 3.3V translation of SOC_GPIO_S5_1 from A2.
10 B1 GPIO_S5_2 ✅ B1 is correctly connected to GPIO_S5_2, which is the 3.3V translation of SOC_GPIO_S5_2 from A1.
11 VCCB +PS_3VSB ✅ VCCB is correctly connected to +PS_3VSB, providing the 3.3V reference voltage for the B-side of the level translator.
12 OE PMC_PLTRST_R_V1P8 ✅ OE is correctly connected to PMC_PLTRST_R_V1P8, which enables the level translator when the platform is out of reset.
U17 - NTS0104GU12 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VCCA +V1P8S ✅ VCCA is correctly connected to +V1P8S, providing the 1.8V reference voltage for the A-side of the level translator.
2 A1 I2S_MCLK ✅ A1 is correctly connected to I2S_MCLK, which is translated to I2SMCLK_GPIO on the B-side through B1.
3 A2 SOC_PWM1 ✅ A2 is correctly connected to SOC_PWM1, which is translated to PWM1 on the B-side through B2.
4 A3 SOC_PWM0 ✅ A3 is correctly connected to SOC_PWM0, which is translated to PWM0 on the B-side through B3.
5 A4 ✅ Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators.
7 B4 GND ✅ Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators.
6 GND GND ✅ GND is correctly connected to the ground net.
8 B3 PWM0 ✅ B3 is correctly connected to PWM0, which is the 3.3V translation of SOC_PWM0 from A3.
9 B2 PWM1 ✅ B2 is correctly connected to PWM1, which is the 3.3V translation of SOC_PWM1 from A2.
10 B1 I2SMCLK_GPIO ✅ B1 is correctly connected to I2SMCLK_GPIO, which is the 3.3V translation of I2S_MCLK from A1.
11 VCCB +3VSB ✅ VCCB is correctly connected to +3VSB, providing the 3.3V reference voltage for the B-side of the level translator.
12 OE PMC_PLTRST_R_V1P8 ✅ OE is correctly connected to PMC_PLTRST_R_V1P8, which enables the level translator when the platform is out of reset.
U16 - NTS0104GU12 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VCCA +V1P8S ✅ VCCA is correctly connected to +V1P8S (1.8V supply), providing the A-side voltage reference for the level translator.
2 A1 I2S_DATIN_R ✅ A1 is correctly connected to I2S_DATIN_R, which translates to I2SDI_GPIO on the B-side through B1.
3 A2 I2S_DATOUT_R ✅ A2 is correctly connected to I2S_DATOUT_R, which translates to I2SDO_GPIO on the B-side through B2.
4 A3 I2S_FRM_R ✅ A3 is correctly connected to I2S_FRM_R, which translates to I2SFRM_GPIO on the B-side through B3.
5 A4 I2S_CLK_R ✅ A4 is correctly connected to I2S_CLK_R, which translates to I2SCLK_GPIO on the B-side through B4.
6 GND GND ✅ GND is correctly connected to the ground net.
7 B4 I2SCLK_GPIO ✅ B4 is correctly connected to I2SCLK_GPIO, providing the 3.3V side connection for I2S clock that pairs with A4.
8 B3 I2SFRM_GPIO ✅ B3 is correctly connected to I2SFRM_GPIO, providing the 3.3V side connection for I2S frame sync that pairs with A3.
9 B2 I2SDO_GPIO ✅ B2 is correctly connected to I2SDO_GPIO, providing the 3.3V side connection for I2S data out that pairs with A2.
10 B1 I2SDI_GPIO ✅ B1 is correctly connected to I2SDI_GPIO, providing the 3.3V side connection for I2S data in that pairs with A1.
11 VCCB +3VSB ✅ VCCB is correctly connected to +3VSB (3.3V standby supply), providing the B-side voltage reference for the level translator.
12 OE PMC_PLTRST_R_V1P8 ✅ OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset.
U18 - NTB0104GU12 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VCCA +V1P8A ✅ VCCA is correctly connected to +V1P8A (1.8V supply) to provide the reference voltage for the A-side of the level translator.
2 A1 SOC_SPI_MOSI-R ✅ A1 is correctly connected to SOC_SPI_MOSI-R, which is the SPI MOSI signal from the SOC at 1.8V level.
3 A2 SOC_SPI_CLK-R ✅ A2 is correctly connected to SOC_SPI_CLK-R, which is the SPI clock signal from the SOC at 1.8V level.
4 A3 SOC_SPI_MISO-R ✅ A3 is correctly connected to SOC_SPI_MISO-R, which is the SPI MISO signal from the SOC at 1.8V level.
5 A4 SOC_SPI_CS0B-R ✅ A4 is correctly connected to SOC_SPI_CS0B-R, which is the SPI chip select 0 (active low) signal from the SOC at 1.8V level.
6 GND GND ✅ GND is correctly connected to the ground net.
7 B4 SPI_CS0 ✅ B4 is correctly connected to SPI_CS0, which is the SPI chip select 0 signal at variable voltage level (currently 3.3V).
8 B3 SPI_MISO ✅ B3 is correctly connected to SPI_MISO, which is the SPI MISO signal at variable voltage level (currently 3.3V).
9 B2 SPI_CLK ✅ B2 is correctly connected to SPI_CLK, which is the SPI clock signal at variable voltage level (currently 3.3V).
10 B1 SPI_MOSI ✅ B1 is correctly connected to SPI_MOSI, which is the SPI MOSI signal at variable voltage level (currently 3.3V).
11 VCCB +V_SPI ✅ VCCB is correctly connected to +V_SPI, which is a variable voltage supply (currently 3.3V) that can be configured as either 1.8V or 3.3V via resistor population options.
12 OE DDP_IO3L ✅ OE is correctly connected to DDP_IO3L with a 100K pull-up to +V1P8A, enabling the level translator by default and allowing the DediProg programmer to disable it when needed.
U14 - NTS0104GU12 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VCCA +V1P8S ✅ VCCA is correctly connected to +V1P8S (1.8V supply) to provide the reference voltage for the A-side of the level translator.
2 A1 SOC_SIO_SPI_CLK ✅ A1 is correctly connected to SOC_SIO_SPI_CLK, which is the SPI clock signal from the SOC at 1.8V level.
3 A2 SOC_SIO_SPI_MOSI ✅ A2 is correctly connected to SOC_SIO_SPI_MOSI, which is the SPI MOSI signal from the SOC at 1.8V level.
4 A3 SOC_SIO_SPI_MISO ✅ A3 is correctly connected to SOC_SIO_SPI_MISO, which is the SPI MISO signal from the SOC at 1.8V level.
5 A4 SOC_SIO_SPI_CS1 ✅ A4 is correctly connected to SOC_SIO_SPI_CS1, which is the SPI chip select 1 signal from the SOC at 1.8V level.
6 GND GND ✅ GND is correctly connected to the ground net.
7 B4 SIO_SPI_CS1 ✅ B4 is correctly connected to SIO_SPI_CS1, which is the SPI chip select 1 signal at 3.3V level.
8 B3 SIO_SPI_MISO ✅ B3 is correctly connected to SIO_SPI_MISO, which is the SPI MISO signal at 3.3V level.
9 B2 SIO_SPI_MOSI ✅ B2 is correctly connected to SIO_SPI_MOSI, which is the SPI MOSI signal at 3.3V level.
10 B1 SIO_SPI_CLK ✅ B1 is correctly connected to SIO_SPI_CLK, which is the SPI clock signal at 3.3V level.
11 VCCB +3VSB ✅ VCCB is correctly connected to +3VSB (3.3V standby supply) to provide the reference voltage for the B-side of the level translator.
12 OE PMC_PLTRST_R_V1P8 ✅ OE is correctly connected to PMC_PLTRST_R_V1P8, which is a platform reset signal at 1.8V level that enables the level translator when the platform is out of reset.
U40 - PCA9306DCUT ❌

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Pin Designator Pin Name Net Correct? Analysis
5 SDA2 GPIO_I2C_SDA ❌
SDA2 and SCL2 pins lack required pullup resistors to the high-voltage supply. While external pullups on a board connected to JP1 might be intended, the datasheet explicitly requires pullup resistors for proper I2C operation, and none are visible on this schematic page.
  • Pin 5 (SDA2) is connected to the GPIO_I2C_SDA net (from schematic)
  • Pin 6 (SCL2) is connected to the GPIO_I2C_SCL net (from schematic)
  • GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 pins 15 and 13 respectively, which is a 26-pin expansion header (HDR2X13) (from schematic)
  • No pullup resistors are visible on the GPIO_I2C_SDA or GPIO_I2C_SCL nets on this schematic page (from schematic)
  • Pin 5 is SDA2, the serial data on the high-voltage side (from datasheet PCA9306DCUT, page 4)
  • Pin 6 is SCL2, the serial clock on the high-voltage side (from datasheet PCA9306DCUT, page 4)
  • The datasheet states: 'Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)' (from datasheet PCA9306DCUT, page 10)
  • The datasheet states: 'pullup resistors required to pull SCL2 and SDA2 outputs to VDPU' (from datasheet PCA9306DCUT, page 10)
  • The high-voltage supply (VDPU) should be +3VSB based on the VREF2 connection through R812 (200K resistor) (from schematic)
  • I2C is an open-drain protocol that requires pullup resistors to function - without them, the bus cannot pull high (reasoning)
  • While the design might intend for pullups to be provided on an external board connected to JP1, this creates a hard dependency on external hardware and the I2C bus will not function without it (reasoning)
  • Best practice for I2C interfaces on expansion headers is to include pullups on the main board, possibly with the option to disable them if external pullups are present (reasoning)
  • Recommendation: Add pullup resistors (typically 2.2K to 10K ohms depending on bus capacitance and speed requirements per I2C specification) from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB, or clearly document that external pullups are required (reasoning)
6 SCL2 GPIO_I2C_SCL ❌
SDA2 and SCL2 pins lack required pullup resistors to the high-voltage supply. While external pullups on a board connected to JP1 might be intended, the datasheet explicitly requires pullup resistors for proper I2C operation, and none are visible on this schematic page.
  • Pin 5 (SDA2) is connected to the GPIO_I2C_SDA net (from schematic)
  • Pin 6 (SCL2) is connected to the GPIO_I2C_SCL net (from schematic)
  • GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 pins 15 and 13 respectively, which is a 26-pin expansion header (HDR2X13) (from schematic)
  • No pullup resistors are visible on the GPIO_I2C_SDA or GPIO_I2C_SCL nets on this schematic page (from schematic)
  • Pin 5 is SDA2, the serial data on the high-voltage side (from datasheet PCA9306DCUT, page 4)
  • Pin 6 is SCL2, the serial clock on the high-voltage side (from datasheet PCA9306DCUT, page 4)
  • The datasheet states: 'Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)' (from datasheet PCA9306DCUT, page 10)
  • The datasheet states: 'pullup resistors required to pull SCL2 and SDA2 outputs to VDPU' (from datasheet PCA9306DCUT, page 10)
  • The high-voltage supply (VDPU) should be +3VSB based on the VREF2 connection through R812 (200K resistor) (from schematic)
  • I2C is an open-drain protocol that requires pullup resistors to function - without them, the bus cannot pull high (reasoning)
  • While the design might intend for pullups to be provided on an external board connected to JP1, this creates a hard dependency on external hardware and the I2C bus will not function without it (reasoning)
  • Best practice for I2C interfaces on expansion headers is to include pullups on the main board, possibly with the option to disable them if external pullups are present (reasoning)
  • Recommendation: Add pullup resistors (typically 2.2K to 10K ohms depending on bus capacitance and speed requirements per I2C specification) from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB, or clearly document that external pullups are required (reasoning)
1 GND GND ✅ GND pin correctly connected to system ground.
2 VREF1 +V1P8S ✅ VREF1 pin correctly connected to +V1P8S (1.8V) low-voltage reference supply.
3 SCL1 I2C5_SCL ✅ SCL1 pin correctly connected to I2C5_SCL with appropriate 10K pullup resistor to +V1P8S.
4 SDA1 I2C5_SDA ✅ SDA1 pin correctly connected to I2C5_SDA with appropriate 10K pullup resistor to +V1P8S.
7 VREF2 $20N1576 ✅ VREF2 pin correctly connected through 200K resistor (R812) to +3VSB, establishing the required reference voltage.
8 EN $20N1576 ✅ EN pin correctly tied to VREF2 and pulled up through 200K resistor to +3VSB, enabling the translator.
R818 - 110-0002124 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $20N2079 ✅ R818 is a 0-ohm jumper correctly marked DNI (Do Not Install) for the 3.3V SPI flash configuration. It would connect the 1.8V supply (+V1P8A) to the flash power network if populated, but is left unpopulated because the installed part W25Q64BVSSIG requires 3.3V operation.
2 2 +V1P8A ✅ R818 is a 0-ohm jumper correctly marked DNI (Do Not Install) for the 3.3V SPI flash configuration. It would connect the 1.8V supply (+V1P8A) to the flash power network if populated, but is left unpopulated because the installed part W25Q64BVSSIG requires 3.3V operation.
R152 - 110-0002124 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $20N2079 ✅ R152 is correctly populated to connect +3VSB (3.3V standby supply) to the SPI flash power OR-ing circuit, matching the voltage requirement of the installed W25Q64BVSSIG part.
2 2 +3VSB ✅ R152 is correctly populated to connect +3VSB (3.3V standby supply) to the SPI flash power OR-ing circuit, matching the voltage requirement of the installed W25Q64BVSSIG part.
U3 - W25Q64BVSSIG ✅

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Pin Designator Pin Name Net Correct? Analysis
1 CS# SPI_CS0 ✅ CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pullup resistor to +V_SPI, meeting datasheet recommendations for power-up tracking.
2 SO/IO1 SPI_MISO ✅ SO/IO1 (Serial Data Output) is correctly connected to SPI_MISO through level translator U18, providing the MISO signal for SPI communication.
3 WP#/IO2 SPI_WP ✅ WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pullup resistor to +V_SPI, disabling hardware write protection as recommended for standard SPI operation.
4 GND GND ✅ GND is correctly connected to the ground net.
5 SI/IO0 SPI_MOSI ✅ SI/IO0 (Serial Data Input) is correctly connected to SPI_MOSI through level translator U18, providing the MOSI signal for SPI communication.
6 SCK SPI_CLK ✅ SCK (Serial Clock) is correctly connected to SPI_CLK through level translator U18, providing the clock signal for SPI communication.
7 HOLD#/IO3 SPI_HOLD ✅ HOLD#/IO3 (Hold Input) is correctly connected to SPI_HOLD with a 10K pullup resistor to +V_SPI, disabling the hold function as recommended for standard SPI operation.
8 VCC +V_SPI ✅ VCC is correctly connected to +V_SPI with proper decoupling capacitors. The voltage level after diode drop (approximately 2.9-3.0V from 3.3V source) is within the 2.7-3.6V specification but has limited margin.
R147 - 110-0001859 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A ✅ R147 correctly pulls up the DDP_IO3L signal (connected to level translator U18 OE pin) to +V1P8A, providing a default enabled state for the level translator while allowing external control through the DediProg connector.
2 2 DDP_IO3L ✅ R147 correctly pulls up the DDP_IO3L signal (connected to level translator U18 OE pin) to +V1P8A, providing a default enabled state for the level translator while allowing external control through the DediProg connector.
D8 - BAT754C ✅

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Pin Designator Pin Name Net Correct? Analysis
A1 A1 DDP_VCC ✅ Anode 1 is correctly connected to DDP_VCC from the DediProg programming header J1 pin 1, allowing external programming power to be OR-ed with the internal supply.
A2 A2 $20N2079 ✅ Anode 2 is correctly connected to the internal 3.3V standby supply (+3VSB) through R152, providing the second power source for the OR-ing configuration.
C C +V_SPI ✅ Common cathode is correctly connected to +V_SPI, which powers the SPI flash U3. The OR-ing diode configuration allows the higher voltage source (DDP_VCC or +3VSB) to power the flash.
J1 - 258-0004612 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DDP_VCC ✅ DDP_VCC provides power to the DediProg programmer interface. It is OR'd with +V_SPI through diode D8 and can be sourced from either +3VSB (via R152) or +V1P8A (via R818, DNI).
2 2 GND ✅ Ground connection for the DediProg programmer interface.
3 3 SPI_CS0 ✅ SPI chip select signal for the DediProg programmer interface, connected to U3 SPI flash CS# and level translator U18.
4 4 SPI_CLK ✅ SPI clock signal for the DediProg programmer interface, connected to U3 SPI flash SCK and level translator U18.
5 5 SPI_MISO ✅ SPI MISO (Master In Slave Out) signal for the DediProg programmer interface, connected to U3 SPI flash SO/IO1 and level translator U18.
6 6 SPI_MOSI ✅ SPI MOSI (Master Out Slave In) signal for the DediProg programmer interface, connected to U3 SPI flash SI/IO0 and level translator U18.
7 7 ✅ No connection on pin 7.
8 8 DDP_IO3L ✅ DDP_IO3L controls the output enable of level translator U18, allowing the DediProg to take control of the SPI bus by disabling the SOC connection.
JP1 - 258-0005019 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Ground connections for the expansion header.
2 2 GND ✅ Ground connections for the expansion header.
3 3 +PS_5VSB ✅ 5V standby power supply output for the expansion header.
4 4 +3VSB ✅ 3.3V standby power supply output for the expansion header.
5 5 SIO_SPI_CS1 ✅ SPI chip select 1 signal, level-translated from SOC 1.8V to 3.3V via U14.
6 6 UART1_TXD ✅ UART1 transmit signal, level-translated from SOC 1.8V to 3.3V via U15.
7 7 SIO_SPI_MISO ✅ SPI MISO signal, level-translated from SOC 1.8V to 3.3V via U14.
8 8 UART1_RXD ✅ UART1 receive signal, level-translated from SOC 1.8V to 3.3V via U15.
9 9 SIO_SPI_MOSI ✅ SPI MOSI signal, level-translated from SOC 1.8V to 3.3V via U14.
10 10 UART1_CTSB ✅ UART1 clear-to-send signal, level-translated from SOC 1.8V to 3.3V via U15.
11 11 SIO_SPI_CLK ✅ SPI clock signal, level-translated from SOC 1.8V to 3.3V via U14.
12 12 UART1_RTSB ✅ UART1 request-to-send signal, level-translated from SOC 1.8V to 3.3V via U15.
13 13 GPIO_I2C_SCL ✅ I2C clock signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator).
14 14 I2SCLK_GPIO ✅ I2S clock signal, level-translated from SOC 1.8V to 3.3V via U16.
15 15 GPIO_I2C_SDA ✅ I2C data signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator).
16 16 I2SFRM_GPIO ✅ I2S frame sync signal, level-translated from SOC 1.8V to 3.3V via U16.
17 17 UART2_TXD ✅ UART2 transmit signal, level-translated from SOC 1.8V to 3.3V via U7.
18 18 I2SDO_GPIO ✅ I2S data out signal, level-translated from SOC 1.8V to 3.3V via U16.
19 19 UART2_RXD ✅ UART2 receive signal, level-translated from SOC 1.8V to 3.3V via U7.
20 20 I2SDI_GPIO ✅ I2S data in signal, level-translated from SOC 1.8V to 3.3V via U16.
21 21 GPIO_S5_0 ✅ GPIO S5_0 signal, level-translated from SOC 1.8V to 3.3V via U10.
22 22 PWM0 ✅ PWM0 signal, level-translated from SOC 1.8V to 3.3V via U17.
23 23 GPIO_S5_1 ✅ GPIO S5_1 signal, level-translated from SOC 1.8V to 3.3V via U10.
24 24 PWM1 ✅ PWM1 signal, level-translated from SOC 1.8V to 3.3V via U17.
25 25 GPIO_S5_2 ✅ GPIO S5_2 signal, level-translated from SOC 1.8V to 3.3V via U10.
26 26 I2SMCLK_GPIO ✅ I2S master clock signal, level-translated from SOC 1.8V to 3.3V via U17.
R746 - 1120-0318 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC ✅ R746 is a 470Ω current limiting resistor connected between +VCC and GPIO_LED_CONTROL. This limits the LED current and also dissipates power when Q105 is on.
2 2 GPIO_LED_CONTROL ✅ R746 is a 470Ω current limiting resistor connected between +VCC and GPIO_LED_CONTROL. This limits the LED current and also dissipates power when Q105 is on.
D2 - 4560-0045 ✅

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Pin Designator Pin Name Net Correct? Analysis
A ANODE GPIO_LED_CONTROL ✅ Anode is connected to GPIO_LED_CONTROL net. This connection is correct for the LED in this inverted logic configuration.
C CATHODE GND ✅ Cathode is connected to GND, which is correct for the LED in this configuration.
R706 - 110-0001875 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GPIO_D2_LED_CTRL ✅ R706 is a 10K pull-down resistor connected between GPIO_D2_LED_CTRL and GND. This ensures the MOSFET gate is pulled low when not actively driven.
2 2 GND ✅ R706 is a 10K pull-down resistor connected between GPIO_D2_LED_CTRL and GND. This ensures the MOSFET gate is pulled low when not actively driven.
Q105 - FDN327N ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN GPIO_LED_CONTROL ✅ Drain is connected to GPIO_LED_CONTROL net, which is the switched node for the LED driver circuit. This connection is correct for a low-side switch configuration.
G GATE GPIO_D2_LED_CTRL ✅ Gate is connected to GPIO_D2_LED_CTRL control signal with a 10K pull-down resistor (R706) to ground. This connection is correct for controlling the MOSFET.
S SOURCE GND ✅ Source is connected to GND, which is correct for an N-channel MOSFET in a low-side switch configuration.
C149 - 123-0003258 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GPIO_LED_CONTROL ✅ C149 is a 2.2uF capacitor connected between GPIO_LED_CONTROL and GND. This provides filtering but causes slow LED turn-on time of approximately 5ms.
2 2 GND ✅ C149 is a 2.2uF capacitor connected between GPIO_LED_CONTROL and GND. This provides filtering but causes slow LED turn-on time of approximately 5ms.
R149 - 110-0002058 ❌

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Pin Designator Pin Name Net Correct? Analysis
1 1 FP_PWRBTN ❌
Pull-up resistor connecting FP_PWRBTN signal (pin 1) to +PS_5VSB power rail (pin 2). However, the resistor value is 4.7K ohm, which does not match the 10K value specified by the datasheet recommendation documented in the schematic notes.
  • Pin 1 is connected to the FP_PWRBTN net (from schematic)
  • Pin 2 is connected to the +PS_5VSB net (5V standby power) (from schematic)
  • R149 is specified as 4.7K ohm 1% 1/10W 0402 resistor (Part Number 110-0002058) (from schematic)
  • Schematic text notes near R149 state 'USE 10K PU' and 'DATASHEET SAYS', indicating a datasheet specifies a 10K pull-up resistor should be used (from schematic)
  • The actual resistor value of 4.7K does not match the 10K value indicated by the schematic notes (reasoning)
  • Using +PS_5VSB for the pull-up is correct, as it ensures the power button remains functional even when the main system power is off (reasoning)
  • A 4.7K pull-up will draw approximately 1.06mA when the button is pressed (5V / 4.7K), while a 10K pull-up would draw approximately 0.5mA (reasoning)
  • The lower resistance provides faster rise times and better noise immunity, but may violate input current specifications or power consumption requirements of the receiving component (reasoning)
  • Without documentation explaining the intentional deviation from the datasheet recommendation, this represents a specification violation (reasoning)
  • Recommendation: Change R149 to 10K ohm to match the datasheet requirement noted on the schematic, or add documentation explaining why 4.7K was intentionally chosen and validated (reasoning)
2 2 +PS_5VSB ❌
Pull-up resistor connecting FP_PWRBTN signal (pin 1) to +PS_5VSB power rail (pin 2). However, the resistor value is 4.7K ohm, which does not match the 10K value specified by the datasheet recommendation documented in the schematic notes.
  • Pin 1 is connected to the FP_PWRBTN net (from schematic)
  • Pin 2 is connected to the +PS_5VSB net (5V standby power) (from schematic)
  • R149 is specified as 4.7K ohm 1% 1/10W 0402 resistor (Part Number 110-0002058) (from schematic)
  • Schematic text notes near R149 state 'USE 10K PU' and 'DATASHEET SAYS', indicating a datasheet specifies a 10K pull-up resistor should be used (from schematic)
  • The actual resistor value of 4.7K does not match the 10K value indicated by the schematic notes (reasoning)
  • Using +PS_5VSB for the pull-up is correct, as it ensures the power button remains functional even when the main system power is off (reasoning)
  • A 4.7K pull-up will draw approximately 1.06mA when the button is pressed (5V / 4.7K), while a 10K pull-up would draw approximately 0.5mA (reasoning)
  • The lower resistance provides faster rise times and better noise immunity, but may violate input current specifications or power consumption requirements of the receiving component (reasoning)
  • Without documentation explaining the intentional deviation from the datasheet recommendation, this represents a specification violation (reasoning)
  • Recommendation: Change R149 to 10K ohm to match the datasheet requirement noted on the schematic, or add documentation explaining why 4.7K was intentionally chosen and validated (reasoning)
C154 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Decoupling capacitor ground connection, providing the return path for filtering and debouncing the FP_PWRBTN signal.
2 2 FP_PWRBTN ✅ Decoupling capacitor signal pin connected to FP_PWRBTN net, providing filtering and debouncing for the power button signal.
D9 - D5V0L1B2LP-7B ✅

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Pin Designator Pin Name Net Correct? Analysis
N N GND ✅ TVS diode terminal connected to GND. Provides the ground reference for bidirectional ESD protection.
P P FP_PWRBTN ✅ TVS diode terminal connected to FP_PWRBTN signal. Provides bidirectional ESD protection for the power button input.
J5 - 258-0002513 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 FP_PWRBTN ✅ Header pin connected to FP_PWRBTN signal. Provides connection point for external power button.
2 2 GND ✅ Header pin connected to GND. Provides ground return for external power button connection.
SW1 - 3770-0026 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 FP_PWRBTN ✅ Switch signal pin connected to FP_PWRBTN net. When button is pressed, this pin connects to pin 2 (GND), pulling the power button signal low.
2 2 GND ✅ Switch return pin connected to GND. Provides the ground reference for the power button when pressed.
3 GND1 GND_EARTH ✅ Shield/mounting pins (GND1 and GND2) connected to GND_EARTH. Provides chassis ground connection for EMI/ESD protection.
4 GND2 GND_EARTH ✅ Shield/mounting pins (GND1 and GND2) connected to GND_EARTH. Provides chassis ground connection for EMI/ESD protection.
D1 - 4560-0045 ✅

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Pin Designator Pin Name Net Correct? Analysis
A ANODE +PS_5VSB ✅ Anode is correctly connected to +PS_5VSB to power the adaptor power indicator LED.
C CATHODE PWR_LEDR ✅ Cathode is correctly connected through current-limiting resistor R148 to ground, completing the LED circuit.
Q9 - DIODE_ARRAY_75V_0.3A_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 A1 $22N1417 ✅ Anode A1 correctly connected to intermediate node $22N1417 from first charge pump stage.
2 A2 +10V ✅ Anode A2 correctly connected to +10V output of charge pump circuit.
3 C $22N1467 ✅ Common cathode correctly connected to $22N1467 node with capacitor C283 to CLK signal.
L3 - IND_2.2uH_20%_10A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 PS3VSB_PHASE ✅ Inductor input correctly connected to PS3VSB_PHASE switch node from U13 SW pins.
2 2 +PS_3VSB ✅ Inductor output correctly connected to +PS_3VSB output rail with output capacitors.
Q2 - DIODE_ARRAY_75V_0.3A_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 A1 +PS_5VSB ✅ Anode A1 correctly connected to +PS_5VSB input for first stage of charge pump circuit.
2 A2 $22N1417 ✅ Anode A2 correctly connected to intermediate node $22N1417 between charge pump stages.
3 C $22N1419 ✅ Common cathode correctly connected to $22N1419 node with capacitor C72 to CLK signal.
U13 - REG_LDO_BUCK_24V ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VIN PS5VSB_VIN ✅ VIN pin correctly connected to PS5VSB_VIN input rail with multiple input decoupling capacitors (22µF and 0.1µF) and ferrite beads to +PS_5VSB source.
2 PGND GND ✅ PGND pin correctly connected to GND plane for power ground return.
3 N/C ✅ N/C pin correctly left unconnected per datasheet.
4 PG +PS_3VSB_PG ✅ PG pin correctly configured as open-drain output with 100kΩ pull-up resistor to PS3_VCC, connected to power good monitoring circuit.
5 CLK $22N1411 ✅ CLK pin correctly connected to external charge pump circuit through capacitors C72 and C283 with diode networks Q2 and Q9 to generate +10V output.
6 LDO PS3_LDO ✅ LDO pin correctly connected to 10µF decoupling capacitor C95 for internal 3.3V linear regulator output.
7 VOUT +PS_3VSB ✅ VOUT pin correctly connected to +PS_3VSB output rail through inductor L3, with multiple output capacitors for 3.3V/6A output.
8 SW1 PS3VSB_PHASE ✅ SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit.
9 SW2 PS3VSB_PHASE ✅ SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit.
15 SW3 PS3VSB_PHASE ✅ SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit.
16 SW4 PS3VSB_PHASE ✅ SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit.
10 BST PS3_BST ✅ BST pin connected to bootstrap circuit with series resistor R291 (4.7Ω) and capacitor C306 (0.1µF) to SW node. The series resistor is non-standard but may be intentional for current limiting or damping.
11 VCC PS3_VCC ✅ VCC pin correctly connected to 1µF decoupling capacitor C97 for internal 5V LDO output that powers driver and control circuits.
12 ENLDO ✅ ENLDO pin correctly left floating, which enables the LDO and VCC per internal pull-up.
13 EN PS3_EN ✅ EN pin connected with 499kΩ pull-up resistor to PS5VSB_VIN for automatic startup. Recommended 10nF noise filter capacitor C85 is marked DNI, which may increase noise susceptibility.
14 AGND GND ✅ AGND pin correctly connected to GND plane for analog ground reference.
U35 - PWR_CTRL_EMB_PROC ❌

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Pin Designator Pin Name Net Correct? Analysis
4 SLP_S5# SLP_S4_L ❌
Pin 4 (SLP_S5#) is connected to net SLP_S4_L. This represents a mismatch between the pin name (indicating S5 sleep state) and the connected signal (indicating S4 sleep state). While this could be intentional in systems that do not distinguish between S4 and S5 states, it should be verified against system requirements and the NCT3012S-X datasheet.
  • Pin 4 is labeled SLP_S5# on component U35 (from schematic)
  • Pin 4 is connected to net SLP_S4_L (from schematic)
  • Component U35 has a DeepS5_Sel pin (pin 1), indicating the chip has specific S5 state handling functionality (from schematic)
  • In ACPI specifications, S4 (Suspend to Disk/Hibernate) and S5 (Soft Off) are different power states with different system behaviors (reasoning)
  • The pin name SLP_S5# explicitly indicates this pin expects an S5 sleep state signal (reasoning)
  • The net name SLP_S4_L indicates this is an S4 sleep state signal (reasoning)
  • Both signals use active-low polarity (# and _L suffixes), so polarity is consistent (reasoning)
  • No SLP_S5# or SLP_S5_L net is visible in the schematic, suggesting either the S5 signal does not exist in this design or there is a naming/connection error (from schematic)
  • Some embedded systems may intentionally use S4 signals to control S5 behavior if they do not distinguish between these states (reasoning)
  • Without the NCT3012S-X datasheet, it cannot be definitively determined whether the chip accepts S4 signals on the SLP_S5# pin (reasoning)
  • Given the explicit pin naming and the presence of S5-specific functionality (DeepS5_Sel), this connection should be verified to ensure correct power state management (reasoning)
  • If this is an error, pin 4 should be connected to an SLP_S5# signal; if intentional, this design decision should be documented (reasoning)
1 DeepS5_Sel S5_SEL ✅ DeepS5_Sel configuration pin with 2.2K pull-up to +PS_5VSB. This pin likely selects the deep S5 mode behavior.
2 VSB +PS_5VSB ✅ VSB power supply pin correctly connected to +PS_5VSB rail with adequate decoupling capacitors nearby.
3 PS_IN# PB_RES ✅ PS_IN# (power switch input) connected to PB_RES through R308 (33 ohm series resistor) for protection and debouncing.
5 SDA DDR_SMB_DATA ✅ SDA pin connected to DDR_SMB_DATA for I2C/SMBus communication, likely for DDR memory or system management.
6 SCLK DDR_SMB_CLK ✅ SCLK pin connected to DDR_SMB_CLK for I2C/SMBus clock signal, pairing with the SDA line.
7 PS_OUT# PS_OUT_L ✅ PS_OUT# output pin connected to PS_OUT_L with a DNI pull-up resistor (R289). The absence of the pull-up may be correct if the output is push-pull.
8 SYS5VSB_OFF 5VSB_CTRL ✅ SYS5VSB_OFF output controls the 5VSB rail through Q10 gate and has proper pull-up through R288. Text notes indicate this signal controls EuP mode.
9 GND GND ✅ GND pin correctly connected to the ground net.
Q103 - SISA18ADN-T1-GE3 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 S1 +5VSB ✅ Source pins correctly connected to +5VSB output rail. All three source pins are paralleled for lower resistance and better current handling capability.
2 S2 +5VSB ✅ Source pins correctly connected to +5VSB output rail. All three source pins are paralleled for lower resistance and better current handling capability.
3 S3 +5VSB ✅ Source pins correctly connected to +5VSB output rail. All three source pins are paralleled for lower resistance and better current handling capability.
4 G 5VSB_LSENB ✅ Gate pin correctly connected to control signal 5VSB_LSENB with appropriate gate drive circuit providing +10V when on and 0V when off.
5 D1 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability.
6 D2 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability.
7 D3 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability.
8 D4 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability.
Q104 - SISA18ADN-T1-GE3 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 S1 +3VSB ✅ Source pins correctly connected to +3VSB output rail. All three source pins are paralleled and connected to the switched output that supplies downstream loads including Q6 and Q13.
2 S2 +3VSB ✅ Source pins correctly connected to +3VSB output rail. All three source pins are paralleled and connected to the switched output that supplies downstream loads including Q6 and Q13.
3 S3 +3VSB ✅ Source pins correctly connected to +3VSB output rail. All three source pins are paralleled and connected to the switched output that supplies downstream loads including Q6 and Q13.
4 G +3VSB_EN ✅ Gate pin correctly connected to +3VSB_EN control signal with proper high-side drive circuit. The gate is pulled up to +10V through R322 (100K) when enabled, providing VGS of approximately 6.7V, and pulled down through Q11 when disabled.
5 D1 +PS_3VSB ✅ Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch.
6 D2 +PS_3VSB ✅ Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch.
7 D3 +PS_3VSB ✅ Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch.
8 D4 +PS_3VSB ✅ Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch.
D13 - 4.3V Zener ✅

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Pin Designator Pin Name Net Correct? Analysis
A ANODE GND ✅ Anode correctly connected to GND, establishing the reference for the 4.3V zener clamp voltage on the cathode.
C CATHODE $22N2300 ✅ Cathode correctly connected to $22N2300, which is the gate control voltage for Q106. The zener clamps this voltage at 4.3V to create the protection threshold.
U36 - MOSFET_30V_15A_8-SOIC ✅

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Pin Designator Pin Name Net Correct? Analysis
1 S1 $22N1502 ✅ Source pins correctly connected to $22N1502, which receives input power from DC_IN_1 through ferrite beads L12 and L13. This is the correct configuration for a P-channel MOSFET high-side switch where current flows from source to drain.
2 S2 $22N1502 ✅ Source pins correctly connected to $22N1502, which receives input power from DC_IN_1 through ferrite beads L12 and L13. This is the correct configuration for a P-channel MOSFET high-side switch where current flows from source to drain.
3 S3 $22N1502 ✅ Source pins correctly connected to $22N1502, which receives input power from DC_IN_1 through ferrite beads L12 and L13. This is the correct configuration for a P-channel MOSFET high-side switch where current flows from source to drain.
4 G DC_GATE_ENB ✅ Gate pin correctly connected to DC_GATE_ENB, which is the control signal from the protection circuit. When DC_GATE_ENB is pulled low by R309, U36 turns on; when Q106 pulls it high during overvoltage, U36 turns off.
5 D1 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side.
6 D2 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side.
7 D3 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side.
8 D4 +PS_5VSB ✅ Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side.
Q106 - BSS84 ✅

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Pin Designator Pin Name Net Correct? Analysis
D D DC_GATE_ENB ✅ Drain pin correctly connected to DC_GATE_ENB, which is the gate control signal for U36. When Q106 turns on, it pulls DC_GATE_ENB toward $22N1502, reducing VGS of U36 and turning it off.
G G $22N2300 ✅ Gate pin correctly connected to $22N2300, which is the control voltage from the zener clamp circuit (R855 and D13). When $22N1502 exceeds ~5.8V, the gate voltage becomes sufficiently negative to turn on Q106.
S S $22N1502 ✅ Source pin correctly connected to $22N1502, which serves as the reference voltage for Q106. This is the higher potential node in normal operation, which is correct for a P-channel MOSFET.
Q6 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN +3VSB ✅ Drain pin correctly connected to +3VSB input rail. This is the input side of the high-side N-channel load switch.
G GATE SYS_EN ✅ Gate pin correctly connected to SYS_EN control signal. The gate drive voltage of +10V provides sufficient VGS for proper MOSFET operation.
S SOURCE +VCC3 ✅ Source pin correctly connected to +VCC3 output rail. This is the output side of the high-side N-channel load switch.
Q13 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN +5VSB ✅ Drain pin correctly connected to +5VSB input rail. This is the input side of the high-side N-channel load switch.
G GATE SYS_EN ✅ Gate pin correctly connected to SYS_EN control signal. The gate drive voltage of +10V provides sufficient VGS for proper MOSFET operation.
S SOURCE +VCC ✅ Source pin correctly connected to +VCC output rail. This is the output side of the high-side N-channel load switch.
Q12 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN SYS_EN ✅ Drain is connected to SYS_EN net, which controls the gates of Q13 and Q6 power MOSFETs. When Q12 is on, it pulls SYS_EN low; when off, R340 pulls it high to +10V.
G GATE SYS_EN_GATE ✅ Gate is connected to SYS_EN_GATE net, which is the output of Q7. This forms the second stage of an inverter chain that level-shifts and inverts the SLP_S3_L signal.
S SOURCE GND ✅ Source is connected to GND, which is correct for an N-channel MOSFET in a low-side switching configuration.
Q7 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN SYS_EN_GATE ✅ Drain is connected to SYS_EN_GATE net, which serves as the output of this inverter stage. When Q7 turns on, it pulls SYS_EN_GATE low; when off, R142 pulls it high to +10V.
G GATE SLP_S3_L ✅ Gate is connected to SLP_S3_L signal, which is an active-low sleep control signal. This controls when Q7 turns on to pull down SYS_EN_GATE.
S SOURCE GND ✅ Source is connected to GND, which is correct for an N-channel MOSFET in a low-side switching configuration.
Q10 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN S5_ENBL ✅ Drain is correctly connected to S5_ENBL, which is pulled up to +V1P8A through R133 (10K) and drives the base of Q4.
G GATE 5VSB_CTRL ✅ Gate is correctly connected to 5VSB_CTRL from U35 pin 8, providing adequate gate drive voltage.
S SOURCE GND ✅ Source is correctly connected to GND, providing the reference for the N-channel MOSFET low-side switch.
Q4 - XSTR_NPN_40V_200mA_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
B BASE S5_ENBL ✅ Base is correctly connected to S5_ENBL, which is controlled by Q10 and pulled up through R133.
C COLLECTOR +3VSB_EN_L ✅ Collector is correctly connected to +3VSB_EN_L, which is pulled up through R321 and drives Q11 gate.
E EMITTER GND ✅ Emitter is correctly connected to GND, providing the reference for the NPN transistor common-emitter configuration.
Q14 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN 5VSB_LSENB ✅ Drain is correctly connected to 5VSB_LSENB, which is pulled up to +10V through R324 and controls Q103 gate.
G GATE 5VSB_GATE ✅ Gate is correctly connected to 5VSB_GATE, which is derived from 5VSB_CTRL through R323 and filtered by C340.
S SOURCE GND ✅ Source is correctly connected to GND, providing the reference for the N-channel MOSFET low-side switch.
Q11 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN +3VSB_EN ✅ Drain is correctly connected to +3VSB_EN, which is pulled up to +10V through R322 and controls Q104 gate.
G GATE +3VSB_EN_L ✅ Gate is correctly connected to +3VSB_EN_L from Q4 collector, providing adequate gate drive voltage.
S SOURCE GND ✅ Source is correctly connected to GND, providing the reference for the N-channel MOSFET low-side switch.
D6 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +PS_3VSB_PG ✅ Cathode 1 connected to +PS_3VSB_PG (power good signal from U13 pin 4). This diode clamps +3VSB_EN low when the power good signal is asserted low.
2 2 +3VSB_EN ✅ Common anode connected to +3VSB_EN (gate control signal for Q104). This is the output node of the diode OR circuit that controls the 3VSB power switch based on power good and reset signals.
3 3 PMC_RSMRST ✅ Cathode 2 connected to PMC_RSMRST (resume reset signal from platform management controller). This diode clamps +3VSB_EN low when reset is asserted.
J9 - JACK_PWR_2.1MM_RAPC712 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DC_IN_1 ✅ Center pin correctly connected to DC_IN_1 net, serving as the positive DC power input. The connection includes protection circuitry that disconnects the input when voltage exceeds 5.8V.
2 2 GND ✅ Sleeve pin correctly connected to GND net, serving as the ground return path for the DC power input.
3 3 GND ✅ Switch contact pin connected to GND, which disables the plug detection functionality. While electrically safe, this connection does not utilize the jack's switched contact feature.
FB11 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +PS_5VSB ✅ Pin 1 connects to +PS_5VSB, paralleled with FB1 pin 1 for increased current capacity.
2 2 PS5VSB_VIN ✅ Pin 2 connects to PS5VSB_VIN, paralleled with FB1 pin 2 for increased current capacity.
FB1 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +PS_5VSB ✅ Pin 1 connects to +PS_5VSB, the filtered 5V standby rail output from power switching MOSFETs Q103 and U36.
2 2 PS5VSB_VIN ✅ Pin 2 connects to PS5VSB_VIN, the input to the 3.3V buck regulator U13 and associated input capacitors.
L13 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $22N1502 ✅ Pin 1 connects to $22N1502, paralleled with L12 pin 1 for increased current capacity.
2 2 DC_IN_1 ✅ Pin 2 connects to DC_IN_1, paralleled with L12 pin 2 for increased current capacity.
L12 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $22N1502 ✅ Pin 1 connects to $22N1502, the source pins of P-channel MOSFET U36 and the filtered DC input node.
2 2 DC_IN_1 ✅ Pin 2 connects to DC_IN_1, the 5V DC input from power jack J9.
U25 - NCP81109GMNTXG ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VRHOT VR_HOT_L ✅ VRHOT pin connected to VR_HOT_L net for thermal alert output.
2 SDIO $23N2429 ✅ SDIO pin connected to SVID data line through 16.9Ω series resistor R80.
3 ALERT $23N2431 ✅ ALERT pin connected to SVID alert line through 0Ω resistor R62.
4 SCLK $23N2430 ✅ SCLK pin connected to SVID clock line through 20.0Ω series resistor R81.
5 GND AGND-VCORE ✅ Analog ground pins (GND, GND1, GND_PAD) connected to AGND-VCORE net, which connects to main GND through 0Ω resistor R37.
32 GND1 AGND-VCORE ✅ Analog ground pins (GND, GND1, GND_PAD) connected to AGND-VCORE net, which connects to main GND through 0Ω resistor R37.
49 GND_PAD AGND-VCORE ✅ Analog ground pins (GND, GND1, GND_PAD) connected to AGND-VCORE net, which connects to main GND through 0Ω resistor R37.
6 VR_RDY $23N3753 ✅ VR_RDY pin connected to power good output signal VCORE_PG through 0Ω resistor R79.
7 VIN1 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
11 VIN2 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
12 VIN3 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
13 VIN4 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
14 VIN5 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
15 VIN6 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
16 VIN7 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
17 VIN8 +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
50 VIN_PAD +5VSB_SW ✅ Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling.
8 BST $23N3711 ✅ BST pin connected to bootstrap circuit with R154 (2.20Ω) and C50 (0.22µF) to SW1.
9 GH ✅ GH pin (high-side gate driver output) is not connected. This is unusual but may be correct for an integrated power stage with internal MOSFETs.
10 SW1 $23N3731 ✅ SW1 pin connected to bootstrap circuit but not to main VCORE-SW net. This separation from SW2-SW7 is unusual and should be verified.
18 SW2 VCORE-SW ✅ Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18.
25 SW3 VCORE-SW ✅ Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18.
26 SW4 VCORE-SW ✅ Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18.
27 SW5 VCORE-SW ✅ Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18.
28 SW6 VCORE-SW ✅ Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18.
29 SW7 VCORE-SW ✅ Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18.
51 SW_PAD VCORE-SW ✅ Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18.
19 PGND1 GND ✅ Power ground pins (PGND1-PGND6) all connected to main GND net.
20 PGND2 GND ✅ Power ground pins (PGND1-PGND6) all connected to main GND net.
21 PGND3 GND ✅ Power ground pins (PGND1-PGND6) all connected to main GND net.
22 PGND4 GND ✅ Power ground pins (PGND1-PGND6) all connected to main GND net.
23 PGND5 GND ✅ Power ground pins (PGND1-PGND6) all connected to main GND net.
24 PGND6 GND ✅ Power ground pins (PGND1-PGND6) all connected to main GND net.
30 GL ✅ GL pin (low-side gate driver output) is not connected. This is unusual but may be correct for an integrated power stage with internal MOSFETs.
31 VBOOT $23N3477 ✅ VBOOT pin connected to voltage divider R70 (88.7kΩ) to set boot voltage. Text note indicates VBOOT = 1.1V.
33 VCCP $23N3625 ✅ VCCP pin connected to charge pump supply through R845 (1.00Ω) from +5VSB with 4.7µF decoupling capacitor C48.
34 TSENSE $23N3665 ✅ TSENSE pin connected to thermistor divider network with TH2 (100kΩ@25C) and R131 (14.0kΩ) for temperature sensing.
35 IMAX $23N3681 ✅ IMAX pin connected to resistor divider R105 (44.2kΩ) to set maximum current limit. Text note indicates IMAX = 14A.
36 IOUT $23N3683 ✅ IOUT pin connected to resistor divider R146 (16.5kΩ) and filter capacitor C47 (470pF) for output current reporting.
37 ILIM VCORE-ILIM ✅ ILIM pin connected to current loop compensation network through R95 (15.0kΩ).
38 CSCOMP VCORE-CSCOMP ✅ CSCOMP pin connected to current sense compensation network with capacitors C39 (470pF), C40 (2200pF), resistors R95, R96, and thermistor TH1.
39 CSSUM VCORE-CSSUM ✅ CSSUM pin connected to current sense summing network with capacitors C39, C40 and resistors R106, R107 for DCR current sensing.
40 CSREF VCORE-CSREF ✅ CSREF pin connected to current sense reference network with capacitor C45 (1000pF) and resistor R108 (10.0Ω).
41 FREQ $23N2930 ✅ FREQ pin connected to frequency setting resistor R93 (18.7kΩ). Text note indicates FSW = 650kHz.
42 COMP VCORE-COMP ✅ COMP pin connected to voltage loop compensation network with capacitors C35 (47pF), C37 (2200pF) and resistor R88 (3.01kΩ).
43 FB VCORE-FB ✅ FB pin connected to feedback network with resistors R88, R89 and capacitors C35, C36 for voltage regulation.
44 DIFFOUT VCORE-DIFFOUT ✅ DIFFOUT pin connected to differential amplifier output network with resistors R89 (1.00kΩ) and R90 (47Ω).
45 VSN VR-VCORE-VSN ✅ VSN pin connected to negative remote sense input through R65 (10.0Ω) for differential voltage sensing.
46 VSP VR-VCORE-VSP ✅ VSP pin connected to positive remote sense input through R92 (100Ω) and R63 (0Ω) for differential voltage sensing.
47 VCC $23N3860 ✅ VCC pin connected to internal supply through R166 (2.20Ω) from +5VSB with 1.0µF decoupling capacitor C24.
48 EN $23N5607 ✅ EN pin connected to enable circuit with pull-up to +VCC through R849 (0Ω) and pull-down R851 (10.0kΩ) to GND.
L8 - 3120-0183 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of the input filter inductor.
2 2 +5VSB_SW ✅ Pin 2 connects to the +5VSB_SW filtered supply rail that powers the U25 controller. This is the correct connection for the output side of the input filter inductor.
L18 - 3120-0266 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-SW ✅ Pin 1 connects to the VCORE-SW switching node from the U25 multiphase buck controller. This is the correct connection for the input side of the output filter inductor.
2 2 +VCORE ✅ Pin 2 connects to the +VCORE output rail with appropriate output capacitors and load connections. This is the correct connection for the output side of the filter inductor.
R88 - 1120-0032 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N2824 ✅ R88 forms part of a Type III compensation network, creating a pole-zero pair with C37 between the COMP and FB pins of the voltage regulator.
2 2 VCORE-FB ✅ R88 forms part of a Type III compensation network, creating a pole-zero pair with C37 between the COMP and FB pins of the voltage regulator.
R89 - 1120-0010 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-FB ✅ R89 provides a DC feedback path between the FB and DIFFOUT pins, part of the differential amplifier network for remote sensing.
2 2 VCORE-DIFFOUT ✅ R89 provides a DC feedback path between the FB and DIFFOUT pins, part of the differential amplifier network for remote sensing.
R90 - 1121-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N2818 ✅ R90 forms an RC filter with C36 in the DIFFOUT network, providing damping and filtering for the differential output path.
2 2 VCORE-DIFFOUT ✅ R90 forms an RC filter with C36 in the DIFFOUT network, providing damping and filtering for the differential output path.
C35 - 2220-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-COMP ✅ C35 is the direct compensation capacitor between COMP and FB pins, providing the high-frequency pole in the Type III compensation network.
2 2 VCORE-FB ✅ C35 is the direct compensation capacitor between COMP and FB pins, providing the high-frequency pole in the Type III compensation network.
C36 - 2220-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-FB ✅ C36 forms an RC filter with R90 in the DIFFOUT network, connecting between FB and the filtered node feeding DIFFOUT.
2 2 $23N2818 ✅ C36 forms an RC filter with R90 in the DIFFOUT network, connecting between FB and the filtered node feeding DIFFOUT.
C37 - 2221-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-COMP ✅ C37 forms part of the Type III compensation network, creating a pole-zero pair with R88 to provide phase boost in the voltage loop.
2 2 $23N2824 ✅ C37 forms part of the Type III compensation network, creating a pole-zero pair with R88 to provide phase boost in the voltage loop.
R108 - 1120-0022 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-CSREF ✅ Connected to VCORE-CSREF (U25 pin 40). This is the current sense reference input.
2 2 $23N3208 ✅ Connected to $23N3208, which connects to +VCORE through SP4. This provides the current sense reference from the output voltage.
C39 - 2220-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-CSCOMP ✅ Connected to VCORE-CSCOMP (U25 pin 38). This is one side of the current loop compensation capacitor.
2 2 VCORE-CSSUM ✅ Connected to VCORE-CSSUM (U25 pin 39). This completes the compensation capacitor between CSCOMP and CSSUM.
C45 - 2220-0035 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-CSREF ✅ Connected to VCORE-CSREF (U25 pin 40). This provides filtering for the current sense reference.
2 2 GND ✅ Connected to GND. This completes the filter capacitor for CSREF.
R107 - 1130-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-CSSUM ✅ Connected to VCORE-CSSUM (U25 pin 39). This is the current sense sum input.
2 2 $23N3209 ✅ Connected to $23N3209, which connects to VCORE-SW through SP3. This senses current from the switch node.
TH1 - 3880-0004 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-CSCOMP ✅ Connected to VCORE-CSCOMP (U25 pin 38). This is one side of the temperature compensation thermistor.
2 2 $23N3115 ✅ Connected to intermediate node $23N3115, which connects to R96 and R106. This completes the temperature compensation network.
C40 - 2221-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-CSCOMP ✅ Connected to VCORE-CSCOMP (U25 pin 38). This is one side of the current loop compensation capacitor.
2 2 VCORE-CSSUM ✅ Connected to VCORE-CSSUM (U25 pin 39). This completes the compensation capacitor between CSCOMP and CSSUM.
R95 - 1120-0029 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-ILIM ✅ Connected to VCORE-ILIM (U25 pin 37). This pin sets the current limit threshold for the DC-DC converter.
2 2 VCORE-CSCOMP ✅ Connected to VCORE-CSCOMP (U25 pin 38). This pin provides current sense compensation.
R106 - 1120-0037 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3115 ✅ Connected to intermediate node $23N3115, which connects to R96 and TH1. This is part of the resistor divider network.
2 2 VCORE-CSSUM ✅ Connected to VCORE-CSSUM (U25 pin 39). This completes the resistor divider for current sensing.
R96 - 1120-0282 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-CSCOMP ✅ Connected to VCORE-CSCOMP (U25 pin 38). This is part of the current sense compensation network.
2 2 $23N3115 ✅ Connected to intermediate node $23N3115, which connects to R106 and TH1. This forms part of the resistor divider network.
C46 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3665 ✅ Filter capacitor positive terminal connected to the TSENSE input of U25, providing noise filtering for the temperature sensing circuit.
2 2 AGND-VCORE ✅ Filter capacitor ground terminal connected to AGND-VCORE, the analog ground reference for the voltage regulator.
R131 - 1120-0055 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3662 ✅ 14.0K resistor in parallel with thermistor TH2, limiting the maximum resistance seen by the TSENSE input and providing a defined voltage range.
2 2 GND ✅ 14.0K resistor in parallel with thermistor TH2, limiting the maximum resistance seen by the TSENSE input and providing a defined voltage range.
R78 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3665 ✅ 0Ω jumper connecting the TSENSE pin of U25 to the thermistor temperature sensing network. This allows for easy disconnection if needed.
2 2 $23N3662 ✅ 0Ω jumper connecting the TSENSE pin of U25 to the thermistor temperature sensing network. This allows for easy disconnection if needed.
TH2 - 3880-0004 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3662 ✅ Thermistor pin connected to the temperature sensing voltage divider node. This pin connects through R78 to the TSENSE input of U25.
2 2 GND ✅ Thermistor pin connected to ground, completing the temperature sensing voltage divider.
R80 - 1120-0329 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SVID_DATA-R ✅ Connected to SVID_DATA-R signal line. This is the external side of the series resistor for the SVID data interface.
2 2 $23N2429 ✅ Connected to U25 pin 2 (SDIO) through net $23N2429. This is the controller side of the series resistor.
R81 - 1120-0099 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SVID_CLK-R ✅ Connected to SVID_CLK-R signal line. This is the external side of the series resistor for the SVID clock interface.
2 2 $23N2430 ✅ Connected to U25 pin 4 (SCLK) through net $23N2430. This is the controller side of the series resistor.
R62 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 SVID_ALERT-R ✅ Connected to SVID_ALERT-R signal line. This is the external side of the 0Ω jumper for the SVID alert interface.
2 2 $23N2431 ✅ Connected to U25 pin 3 (ALERT) through net $23N2431. This is the controller side of the 0Ω jumper.
R85 - 1120-0330 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ✅ Connected to +V1P0S supply. This resistor is marked DNI and is electrically absent.
2 2 SVID_DATA-R ✅ Connected to SVID_DATA-R signal line. This resistor is marked DNI and is electrically absent.
R86 - 1120-0330 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ✅ Connected to +V1P0S supply. This resistor is marked DNI and is electrically absent.
2 2 SVID_ALERT-R ✅ Connected to SVID_ALERT-R signal line. This resistor is marked DNI and is electrically absent.
R87 - 1120-0330 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ✅ Connected to +V1P0S supply. This resistor is marked DNI and is electrically absent.
2 2 SVID_CLK-R ✅ Connected to SVID_CLK-R signal line. This resistor is marked DNI and is electrically absent.
R65 - 1120-0022 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N2860 ✅ Connected to intermediate node $23N2860, which combines local and remote sense signals for the negative path.
2 2 VR-VCORE-VSN ✅ Connected to VR-VCORE-VSN (U25 pin 45), providing the negative differential sense input. The 10Ω value creates an asymmetry with the positive path but may be intentional for filtering or current limiting.
C38 - 2221-0004 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N2860 ✅ Would connect to intermediate node $23N2860 if installed, but component is marked DNI (Do Not Install).
2 2 VR-VCORE-VSN ✅ Would connect to VR-VCORE-VSN if installed, forming a filter with R65, but component is marked DNI.
R63 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCC_SENSE ✅ Connected to VCC_SENSE for remote voltage sensing of the positive output.
2 2 VR-VCORE-VSP ✅ Connected to VR-VCORE-VSP, providing remote sense input to U25 pin 46 (VSP).
R91 - 1120-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND as part of the local voltage sense path for the negative side of the differential sense circuit.
2 2 $23N2860 ✅ Connected to intermediate node $23N2860, which connects to VSS_SENSE through R64 and to VSN through R65.
R64 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VSS_SENSE ✅ Connected to VSS_SENSE for remote voltage sensing of the negative output (ground).
2 2 $23N2860 ✅ Connected to intermediate node $23N2860, which connects to VSN through R65.
C34 - 2221-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VR-VCORE-VSP ✅ Would connect to VR-VCORE-VSP if installed, but component is marked DNI (Do Not Install).
2 2 VR-VCORE-VSN ✅ Would connect to VR-VCORE-VSN if installed, forming a differential filter capacitor between VSP and VSN, but component is marked DNI.
R92 - 1120-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCORE ✅ Connected to +VCORE output as part of the local voltage sense path for the positive side of the differential sense circuit.
2 2 VR-VCORE-VSP ✅ Connected to VR-VCORE-VSP, which connects to U25 pin 46 (VSP) and to VCC_SENSE through R63.
D4 - BAT54A-S ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE_PG ✅ Cathode 1 connected to VCORE_PG power good signal. This pin receives the VCORE power good signal and forms one input of the OR-ing diode configuration.
2 2 VGFX_PG ✅ Cathode 2 connected to VGFX_PG power good signal. This pin receives the VGFX power good signal and forms the second input of the OR-ing diode configuration.
3 3 VCORE_GFX_PG ✅ Common anode connected to VCORE_GFX_PG combined power good output. This pin outputs the OR'd result of the two input power good signals.
R167 - 1120-0052 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC3 ✅ Connected to +VCC3 supply rail. Provides pull-up voltage for VCORE_PG signal.
2 2 VCORE_PG ✅ Connected to VCORE_PG power good signal. Provides weak pull-up to ensure signal is high when not actively driven low.
R94 - 110-0001923 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE_GFX_PG ✅ Connected to VCORE_GFX_PG combined power good output. Provides pull-up for the OR'd power good signal.
2 2 +VCC3 ✅ Connected to +VCC3 supply rail. Provides pull-up voltage for VCORE_GFX_PG signal.
C25 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE_PG ✅ Connected to VCORE_PG signal for filtering and decoupling.
2 2 GND ✅ Connected to GND for signal filtering return path.
C65 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND for signal filtering return path.
2 2 VCORE_GFX_PG ✅ Connected to VCORE_GFX_PG combined power good signal for filtering and decoupling.
R849 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC ✅ Connected to +VCC power rail to provide enable signal source.
2 2 $23N5607 ✅ Connected to U25 EN pin through net $23N5607, providing enable control.
R851 - 1120-0011 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N5607 ✅ Connected to U25 EN pin through net $23N5607, providing pull-down function.
2 2 GND ✅ Connected to GND, completing the pull-down path.
C433 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N5607 ✅ Connected to U25 EN pin through net $23N5607, providing filtering.
2 2 GND ✅ Connected to GND, completing the bypass path.
C50 - 2222-0008 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3733 ✅ Connected to R154 pin 2, forming the positive terminal of the bootstrap capacitor that charges through R154 from the BST pin.
2 2 $23N3731 ✅ Connected to U25 pin 10 (SW1), referencing the bootstrap capacitor to the switch node as required for proper high-side gate driver operation.
R154 - 1130-0234 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3711 ✅ Connected to U25 pin 8 (BST) as part of the bootstrap circuit for the high-side gate driver.
2 2 $23N3733 ✅ Connected to C50 pin 1, forming the intermediate node in the bootstrap circuit between the BST pin and the bootstrap capacitor.
R79 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE_PG ✅ Connected to VCORE_PG signal, which is the system power good signal that is OR-ed with other power good signals through D4.
2 2 $23N3753 ✅ Connected to U25 pin 6 (VR_RDY), which is the voltage regulator ready output signal indicating the regulator has reached regulation.
R166 - 1130-0234 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Connected to +5VSB power rail, providing input to series resistor feeding U25 VCC pin.
2 2 $23N3860 ✅ Connected to U25 pin 47 (VCC) through net $23N3860, with C24 providing decoupling to AGND-VCORE.
C24 - 2222-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3860 ✅ Connected to U25 VCC supply net $23N3860 for decoupling.
2 2 AGND-VCORE ✅ Connected to AGND-VCORE, providing decoupling return path through analog ground.
C48 - 2232-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3625 ✅ Connected to U25 VCCP supply net $23N3625 for decoupling.
2 2 GND ✅ Connected to GND, providing decoupling return path through main ground.
R845 - 1130-0193 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Connected to +5VSB power rail, providing input to series resistor feeding U25 VCCP pin.
2 2 $23N3625 ✅ Connected to U25 pin 33 (VCCP) through net $23N3625, with C48 providing decoupling to GND.
R70 - 1120-0289 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3477 ✅ Connected to U25 VBOOT pin (pin 31) for configuration. Text note indicates VBOOT should be 1.1V and sets I2C address to 0x0.
2 2 AGND-VCORE ✅ Connected to AGND-VCORE (analog ground), completing the VBOOT configuration resistor divider.
R93 - 1120-0351 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N2930 ✅ Connected to U25 FREQ pin (pin 41) to set switching frequency. Text note indicates target frequency of 650kHz.
2 2 AGND-VCORE ✅ Connected to AGND-VCORE (analog ground), completing the frequency-setting resistor divider.
R146 - 1120-0338 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3683 ✅ Connected to U25 pin 36 (IOUT) for current monitoring. Forms an RC filter with C47 to filter the current output signal.
2 2 AGND-VCORE ✅ Connected to AGND-VCORE, providing the return path for the current monitoring circuit.
C47 - 2220-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3683 ✅ Connected to U25 pin 36 (IOUT) along with R146. Forms an RC filter to reduce noise on the current monitoring output.
2 2 AGND-VCORE ✅ Connected to AGND-VCORE, providing the AC return path for the filter capacitor.
R105 - 1120-0115 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3681 ✅ Connected to U25 pin 35 (IMAX) to set the maximum current limit. A text note indicates the target is 14A.
2 2 AGND-VCORE ✅ Connected to AGND-VCORE, providing the return path for the current limit setting circuit.
C52 - 2240-0005 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $23N3990 ✅ Connected to intermediate node $23N3990 of the RC snubber. Forms the capacitive element that works with R168 to dampen switching node ringing.
2 2 GND ✅ Connected to GND. Completes the snubber circuit path from the switching node to ground.
R168 - 1141-0026 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE-SW ✅ Connected to VCORE-SW switching node. This is the input side of an RC snubber circuit used to dampen ringing and reduce EMI on the switching node.
2 2 $23N3990 ✅ Connected to intermediate node $23N3990 between the snubber resistor and capacitor. Forms the RC junction of the snubber network.
U26 - NCP81109GMNTXG ❌

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Pin Designator Pin Name Net Correct? Analysis
10 SW1 $24N3595 ❌
SW1 is connected only to the bootstrap capacitor return ($24N3595) and is isolated from the main switch node (VGFX-SW). This appears incorrect as phase 1 should be connected to the output if it is intended to be active.
  • Pin 10 (SW1) is connected to net $24N3595 (from schematic)
  • Net $24N3595 connects only to bootstrap capacitor C186 pin 2 and pin 10 (SW1) (from schematic)
  • Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW (from schematic)
  • Net VGFX-SW connects to inductor L4 pin 1, which connects to output +VGFX (from schematic)
  • There is no connection between net $24N3595 (SW1) and net VGFX-SW (from schematic)
  • Bootstrap circuit is present: pin 8 (BST) -> $24N3593 -> R228 -> $24N3596 -> C186 -> $24N3595 -> pin 10 (SW1) (from schematic)
  • Pin 7 (VIN1) is connected to +5VSB_SW, indicating phase 1 is powered (from schematic)
  • The presence of a populated bootstrap circuit (R228, C186) suggests phase 1 was intended to be active (reasoning)
  • In a multiphase buck converter, all active switch nodes should be connected to share load current through their respective inductors to the common output (reasoning)
  • Only one inductor (L4) is present, connecting VGFX-SW to +VGFX, suggesting all active phases should connect to VGFX-SW (reasoning)
  • If phase 1 were intentionally disabled, the bootstrap circuit components would typically be unpopulated (reasoning)
  • The isolation of SW1 from VGFX-SW while maintaining the bootstrap circuit and VIN1 connection is inconsistent and likely a design error (reasoning)
  • SW1 should be connected to VGFX-SW to enable phase 1 to contribute to the output (reasoning)
1 VRHOT VR_HOT_L ✅ VRHOT is a thermal alert output connected to the system-level VR_HOT_L signal for thermal monitoring.
2 SDIO $24N3490 ✅ SDIO is the SVID data line with proper series termination (16.9Ω) and pull-up resistor (69.8Ω) to +V1P0S for bidirectional communication.
3 ALERT $24N3492 ✅ ALERT is the SVID alert output with 0Ω series resistor and DNI pull-up, properly configured for open-drain signaling.
4 SCLK $24N3491 ✅ SCLK is the SVID clock line with proper series termination (20.0Ω) and pull-up resistor (69.8Ω) to +V1P0S.
5 GND AGND-VGFX ✅ GND is the analog ground pin properly connected to AGND-VGFX, which is tied to system GND through a 0Ω jumper for star grounding.
6 VR_RDY $24N3598 ✅ VR_RDY is the power good output with 0Ω series resistor, pull-up to +VCC3 (1.91kΩ), and bypass capacitor, properly configured for system power sequencing.
7 VIN1 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
11 VIN2 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
12 VIN3 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
13 VIN4 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
14 VIN5 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
15 VIN6 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
16 VIN7 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
17 VIN8 +5VSB_SW ✅ VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply.
8 BST $24N3593 ✅ BST is the bootstrap pin with proper bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) connected to SW1 for high-side gate driver supply.
9 GH ✅ GH is the high-side gate driver output with no visible external connection. This may indicate integrated MOSFETs, internal connections, or connections on another schematic page.
18 SW2 VGFX-SW ✅ SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present.
25 SW3 VGFX-SW ✅ SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present.
26 SW4 VGFX-SW ✅ SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present.
27 SW5 VGFX-SW ✅ SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present.
28 SW6 VGFX-SW ✅ SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present.
29 SW7 VGFX-SW ✅ SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present.
19 PGND1 GND ✅ PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path.
20 PGND2 GND ✅ PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path.
21 PGND3 GND ✅ PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path.
22 PGND4 GND ✅ PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path.
23 PGND5 GND ✅ PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path.
24 PGND6 GND ✅ PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path.
30 GL ✅ GL is the low-side gate driver output with no visible external connection. This may indicate integrated MOSFETs, internal connections, or connections on another schematic page.
31 VBOOT $24N3564 ✅ VBOOT is the bootstrap voltage sense pin with 100kΩ pull-down to AGND-VGFX for monitoring bootstrap voltage level.
32 GND1 AGND-VGFX ✅ GND1 is an analog ground pin properly connected to AGND-VGFX for star grounding topology.
33 VCCP $24N3578 ✅ VCCP is the internal charge pump/LDO supply pin with proper input from +5VSB through 1Ω current limiting resistor and 4.7µF decoupling capacitor.
34 TSENSE $24N3584 ✅ TSENSE is the temperature sense input with proper thermistor network (TH4 100kΩ@25C, R226 14.0kΩ) and bypass capacitor for thermal monitoring and protection.
35 IMAX $24N3588 ✅ IMAX sets the maximum current limit to 14A per phase using R207 (44.2kΩ) to AGND-VGFX, as indicated by nearby text note.
36 IOUT $24N3589 ✅ IOUT is the output current reporting pin with proper RC filter (R227 16.5kΩ, C184 470pF) to AGND-VGFX for current telemetry.
37 ILIM VGFX-ILIM ✅ ILIM is the current limit threshold pin connected through R204 (15.0kΩ) to VGFX-CSCOMP for current loop compensation and limiting.
38 CSCOMP VGFX-CSCOMP ✅ CSCOMP is the current sense compensation pin with proper compensation network including capacitors (C113 470pF, C166 2200pF), resistors (R205 75.0kΩ, R204 15.0kΩ), and thermistor (TH3) for temperature-compensated current sensing.
39 CSSUM VGFX-CSSUM ✅ CSSUM is the current sense sum input with resistor network (R224 100kΩ, R223 165kΩ) for DCR current sensing from the switch node through SP2.
40 CSREF VGFX-CSREF ✅ CSREF is the current sense reference pin connected through R225 (10.0Ω) to output voltage via SP1, with C167 (1000pF) bypass, implementing DCR current sensing reference.
41 FREQ $24N3542 ✅ FREQ sets the switching frequency to 650kHz using R203 (18.7kΩ) to AGND-VGFX, as confirmed by nearby text note.
42 COMP VGFX-COMP ✅ COMP is the voltage loop compensation pin with Type III compensation network (C62 47pF, C64 2200pF, R198 3.01kΩ) for stable voltage regulation.
43 FB VGFX-FB ✅ FB is the feedback input with resistor divider (R198 3.01kΩ, R199 1.00kΩ) and compensation capacitors (C62 47pF, C63 220pF) setting the output voltage regulation point.
44 DIFFOUT VGFX-DIFFOUT ✅ DIFFOUT is the differential amplifier output connected through resistors (R199 1.00kΩ, R200 47Ω) to FB and compensation network for remote voltage sensing.
45 VSN VR-VGFX-VSN ✅ VSN is the negative remote sense input connected through R169 (10.0Ω) to a ground reference divider (R201 100Ω, R69 0Ω) for differential voltage sensing.
46 VSP VR-VGFX-VSP ✅ VSP is the positive remote sense input connected through R202 (100Ω) to +VGFX and through R68 (0Ω) to VCCGT_SENSE for remote voltage regulation at the load.
47 VCC $24N3610 ✅ VCC is the main supply input with proper input filtering through R229 (2.20Ω) from +5VSB and C53 (1.0µF) decoupling to AGND-VGFX.
48 EN $24N6011 ✅ EN is the enable input with proper configuration: 0Ω jumper from +VCC for enable, 10kΩ pull-down, and 0.1µF bypass capacitor.
49 GND_PAD AGND-VGFX ✅ GND_PAD is the exposed thermal/ground pad properly connected to AGND-VGFX for thermal dissipation and electrical grounding.
50 VIN_PAD +5VSB_SW ✅ VIN_PAD is the exposed input voltage pad properly connected to +5VSB_SW for additional input current capability and thermal management.
51 SW_PAD VGFX-SW ✅ SW_PAD is the exposed switch node pad properly connected to VGFX-SW for additional current capability and thermal management of the switch nodes.
C76 - 123-0005035 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 P +VGFX ✅ Positive terminal connected to +VGFX output rail. Polarity is correct for a bulk output capacitor.
2 N GND ✅ Negative terminal connected to GND. Polarity is correct, but the 2V voltage rating is marginal for this application and provides minimal safety margin.
C77 - 123-0005035 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 P +VGFX ✅ Positive terminal connected to +VGFX output rail. Polarity is correct for a bulk output capacitor.
2 N GND ✅ Negative terminal connected to GND. Polarity is correct, but the 2V voltage rating is marginal for this application and provides minimal safety margin.
SP1 - 999-0000005 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VGFX ✅ Connected to +VGFX output rail. This provides the output voltage reference for DCR current sensing.
2 2 $24N3559 ✅ Connected to $24N3559, which connects through R225 (10Ω) to VGFX-CSREF pin of the controller. This forms the reference path for DCR current sensing.
SP2 - 999-0000005 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-SW ✅ Connected to VGFX-SW switching node. This provides the switching node voltage reference for DCR current sensing.
2 2 $24N3558 ✅ Connected to $24N3558, which connects through R224 (100kΩ) to VGFX-CSSUM pin of the controller. This forms the sum path for DCR current sensing.
L4 - 3120-0266 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-SW ✅ Pin 1 connects to the switching node VGFX-SW from the multiphase buck controller U26. This is the standard input connection for a buck converter output inductor.
2 2 +VGFX ✅ Pin 2 connects to the output rail +VGFX and is filtered by multiple output capacitors. The inductor is rated for 17.5A, but a text note indicates IMAX = 24A, which may exceed the inductor's rating depending on whether 17.5A refers to saturation current or thermal rating.
R198 - 1120-0032 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3524 ✅ Connected to internal node $24N3524, which connects to C64 pin 2, forming a series RC network with C64 from COMP to FB.
2 2 VGFX-FB ✅ Connected to VGFX-FB feedback net, which connects to U26 pin 43 (FB), completing the compensation network.
R199 - 1120-0010 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-FB ✅ Connected to VGFX-FB feedback net, forming part of the differential sensing network between FB and DIFFOUT.
2 2 VGFX-DIFFOUT ✅ Connected to VGFX-DIFFOUT net, which connects to U26 pin 44 (DIFFOUT), completing the differential sensing path.
R200 - 1121-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3522 ✅ Connected to internal node $24N3522, which connects to C63 pin 2, forming a series RC network in the differential path.
2 2 VGFX-DIFFOUT ✅ Connected to VGFX-DIFFOUT net, completing the differential sensing network to U26 pin 44.
C62 - 2220-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-COMP ✅ Connected to VGFX-COMP compensation pin, providing direct high-frequency feedback path.
2 2 VGFX-FB ✅ Connected to VGFX-FB feedback net, completing the high-frequency compensation path.
C63 - 2220-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-FB ✅ Connected to VGFX-FB feedback net, forming part of the differential sensing filter network.
2 2 $24N3522 ✅ Connected to internal node $24N3522, which connects to R200 pin 1, forming a series RC network.
C64 - 2221-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-COMP ✅ Connected to VGFX-COMP compensation pin, forming the main compensation capacitor.
2 2 $24N3524 ✅ Connected to internal node $24N3524, which connects to R198 pin 1, forming a series RC compensation network.
R225 - 1120-0022 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-CSREF ✅ Connected to VGFX-CSREF pin of the controller for current sense reference.
2 2 $24N3559 ✅ Connected through net $24N3559 and short SP1 to the output voltage +VGFX, providing a reference for DCR current sensing.
C113 - 2220-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-CSCOMP ✅ Connected to VGFX-CSCOMP for current loop compensation.
2 2 VGFX-CSSUM ✅ Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C166.
R205 - 1120-0282 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-CSCOMP ✅ Connected to VGFX-CSCOMP for current sense compensation.
2 2 $24N3557 ✅ Connected to intermediate node $24N3557, forming a parallel path with thermistor TH3 for temperature compensation.
C166 - 2221-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-CSCOMP ✅ Connected to VGFX-CSCOMP for current loop compensation.
2 2 VGFX-CSSUM ✅ Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C113.
C167 - 2220-0035 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-CSREF ✅ Connected to VGFX-CSREF for filtering the current sense reference.
2 2 GND ✅ Connected to GND to provide AC filtering for the CSREF pin.
R224 - 1130-0002 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-CSSUM ✅ Connected to VGFX-CSSUM pin of the controller U26 for current sensing.
2 2 $24N3558 ✅ Connected through net $24N3558 and short SP2 to the switching node VGFX-SW for DCR current sensing.
R204 - 1120-0029 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-ILIM ✅ Connected to VGFX-ILIM pin of the controller for current limit setting.
2 2 VGFX-CSCOMP ✅ Connected to VGFX-CSCOMP to link the current limit setting to the compensation network.
TH3 - 3880-0004 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-CSCOMP ✅ Connected to VGFX-CSCOMP (U26 pin 38). Part of current loop compensation network, in parallel with R205 (75K) to provide temperature-dependent compensation.
2 2 $24N3557 ✅ Connected to $24N3557, which is the junction between R205 and R223 in the current sense compensation network.
R223 - 1120-0037 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3557 ✅ Connected to the intermediate node $24N3557 which links to the CSCOMP compensation network.
2 2 VGFX-CSSUM ✅ Connected to VGFX-CSSUM to provide feedback from the current sense sum to the compensation network.
C168 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3584 ✅ Connected to $24N3584 (U26 pin 34 TSENSE), providing filtering for the temperature sense signal.
2 2 AGND-VGFX ✅ Connected to AGND-VGFX (analog ground), providing proper ground reference for filtering.
R178 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3584 ✅ Connected to $24N3584, which connects to U26 pin 34 (TSENSE) and C168 for filtering.
2 2 $24N3583 ✅ Connected to $24N3583, which connects to the TH4/R226 voltage divider network.
TH4 - 3880-0004 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3583 ✅ Connected to $24N3583, which connects through R178 (0 ohm) to U26 pin 34 (TSENSE). Forms voltage divider with R226 (14K) for temperature sensing.
2 2 GND ✅ Connected to GND, completing the voltage divider circuit for temperature sensing.
R226 - 1120-0055 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3583 ✅ Connected to $24N3583, forming the lower part of the voltage divider with TH4 for temperature sensing.
2 2 GND ✅ Connected to GND, completing the voltage divider to ground.
R195 - 1120-0330 ❌

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ❌
Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).
  • Pin 1 is connected to +V1P0S (1.0V standby supply rail) (from schematic)
  • Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) (from schematic)
  • This resistor forms a pull-up for the SVID data line (reasoning)
  • SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines (reasoning)
  • Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ (reasoning)
  • The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) (reasoning)
  • The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up (reasoning)
  • The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity (reasoning)
2 2 SVID_DATA-R ❌
Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).
  • Pin 1 is connected to +V1P0S (1.0V standby supply rail) (from schematic)
  • Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) (from schematic)
  • This resistor forms a pull-up for the SVID data line (reasoning)
  • SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines (reasoning)
  • Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ (reasoning)
  • The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) (reasoning)
  • The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up (reasoning)
  • The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity (reasoning)
R196 - 1120-0330 ❌

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ❌
Pull-up resistor for SVID alert line, marked DNI (Do Not Install). Without this pull-up, the ALERT line will float when not actively driven, which may cause issues since R67 connects this signal to U26 pin 3 (ALERT).
  • Pin 1 would connect to +V1P0S (1.0V standby supply rail) if populated (from schematic)
  • Pin 2 would connect to SVID_ALERT-R if populated (from schematic)
  • This component is marked DNI (Do Not Install) and is electrically absent from the circuit (from schematic)
  • R67 (0Ω jumper) connects SVID_ALERT-R through to U26 pin 3 (ALERT), indicating the alert signal path is intended to be active (from schematic)
  • SVID alert lines typically require pull-up resistors similar to data and clock lines, as they use open-drain outputs (reasoning)
  • Without a pull-up resistor, the ALERT line will float when not actively driven, which can cause undefined logic levels and potential noise sensitivity (reasoning)
  • If the alert function is intended to be used (suggested by R67 being populated), R196 should be populated with a pull-up resistor in the 1kΩ to 10kΩ range (reasoning)
  • If the alert function is not used, the DNI status may be acceptable, though best practice would be to leave the pin unconnected or ensure it has a defined state (reasoning)
2 2 SVID_ALERT-R ❌
Pull-up resistor for SVID alert line, marked DNI (Do Not Install). Without this pull-up, the ALERT line will float when not actively driven, which may cause issues since R67 connects this signal to U26 pin 3 (ALERT).
  • Pin 1 would connect to +V1P0S (1.0V standby supply rail) if populated (from schematic)
  • Pin 2 would connect to SVID_ALERT-R if populated (from schematic)
  • This component is marked DNI (Do Not Install) and is electrically absent from the circuit (from schematic)
  • R67 (0Ω jumper) connects SVID_ALERT-R through to U26 pin 3 (ALERT), indicating the alert signal path is intended to be active (from schematic)
  • SVID alert lines typically require pull-up resistors similar to data and clock lines, as they use open-drain outputs (reasoning)
  • Without a pull-up resistor, the ALERT line will float when not actively driven, which can cause undefined logic levels and potential noise sensitivity (reasoning)
  • If the alert function is intended to be used (suggested by R67 being populated), R196 should be populated with a pull-up resistor in the 1kΩ to 10kΩ range (reasoning)
  • If the alert function is not used, the DNI status may be acceptable, though best practice would be to leave the pin unconnected or ensure it has a defined state (reasoning)
R197 - 1120-0330 ❌

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0S ❌
Pull-up resistor for SVID clock line connecting +V1P0S to SVID_CLK-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).
  • Pin 1 is connected to +V1P0S (1.0V standby supply rail) (from schematic)
  • Pin 2 is connected to SVID_CLK-R, which connects through series resistor R194 to U26 pin 4 (SCLK) (from schematic)
  • This resistor forms a pull-up for the SVID clock line (reasoning)
  • SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines (reasoning)
  • Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ (reasoning)
  • The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) (reasoning)
  • The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up (reasoning)
  • The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity (reasoning)
2 2 SVID_CLK-R ❌
Pull-up resistor for SVID clock line connecting +V1P0S to SVID_CLK-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).
  • Pin 1 is connected to +V1P0S (1.0V standby supply rail) (from schematic)
  • Pin 2 is connected to SVID_CLK-R, which connects through series resistor R194 to U26 pin 4 (SCLK) (from schematic)
  • This resistor forms a pull-up for the SVID clock line (reasoning)
  • SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines (reasoning)
  • Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ (reasoning)
  • The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) (reasoning)
  • The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up (reasoning)
  • The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity (reasoning)
C61 - 2221-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VR-VGFX-VSP ✅ Connected to VR-VGFX-VSP net. Component is DNI (Do Not Install), so it does not affect the circuit electrically.
2 2 VR-VGFX-VSN ✅ Connected to VR-VGFX-VSN net. Component is DNI, so it does not load the circuit.
C104 - 2221-0004 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3528 ✅ Connected to internal node $24N3528. Component is DNI, so it does not affect the circuit.
2 2 VR-VGFX-VSN ✅ Connected to VR-VGFX-VSN net. Component is DNI, so it does not load the circuit.
R68 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCCGT_SENSE ✅ 0Ω jumper connects VCCGT_SENSE to VSP sense input. Creates imbalanced differential pair with VSN path which has 10Ω (R169).
2 2 VR-VGFX-VSP ✅ 0Ω jumper connects VCCGT_SENSE to VSP sense input. Creates imbalanced differential pair with VSN path which has 10Ω (R169).
R69 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ 0Ω jumper connects GND to intermediate node $24N3528. In parallel with R201 (100Ω), providing the dominant low-resistance path.
2 2 $24N3528 ✅ 0Ω jumper connects GND to intermediate node $24N3528. In parallel with R201 (100Ω), providing the dominant low-resistance path.
R201 - 1120-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ 100Ω resistor connects GND to intermediate node $24N3528. In parallel with R69 (0Ω) which dominates, making this resistor's contribution minimal.
2 2 $24N3528 ✅ 100Ω resistor connects GND to intermediate node $24N3528. In parallel with R69 (0Ω) which dominates, making this resistor's contribution minimal.
R202 - 1120-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VGFX ✅ 100Ω resistor connects +VGFX to VSP sense input. In parallel with R68 (0Ω) which dominates the connection, making this resistor's contribution minimal.
2 2 VR-VGFX-VSP ✅ 100Ω resistor connects +VGFX to VSP sense input. In parallel with R68 (0Ω) which dominates the connection, making this resistor's contribution minimal.
R169 - 1120-0022 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3528 ✅ 10Ω resistor in VSN path creates imbalanced differential pair with VSP path (0Ω through R68). May be intentional for filtering or current limiting.
2 2 VR-VGFX-VSN ✅ 10Ω resistor in VSN path creates imbalanced differential pair with VSP path (0Ω through R68). May be intentional for filtering or current limiting.
R850 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC ✅ Connected to +VCC power rail. This pin sources the enable signal when the jumper is populated.
2 2 $24N6011 ✅ Connected to net $24N6011, which drives the enable pin of U26. This forms part of the enable circuit.
R852 - 1120-0011 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N6011 ✅ Connected to net $24N6011, providing a pull-down path for the enable circuit.
2 2 GND ✅ Connected to GND, completing the pull-down path for the enable circuit.
C434 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N6011 ✅ Connected to net $24N6011, providing decoupling and filtering for the enable signal.
2 2 GND ✅ Connected to GND, completing the decoupling path for the enable signal.
C60 - 2222-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX_PG ✅ Connected to VGFX_PG net to provide signal filtering and noise suppression.
2 2 GND ✅ Connected to GND to complete the filtering path for the power good signal.
R184 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX_PG ✅ Connected to VGFX_PG net, which is the conditioned power good signal with pull-up and filtering.
2 2 $24N3598 ✅ Connected to U26 pin 6 (VR_RDY), the voltage regulator power ready output signal.
R230 - 1120-0052 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC3 ✅ Connected to +VCC3 power rail to provide pull-up voltage source for the power good signal.
2 2 VGFX_PG ✅ Connected to VGFX_PG net, providing pull-up function for the power good signal.
R228 - 1130-0234 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3593 ✅ Connected to the BST (bootstrap) pin of U26 (NCP81109GMNTXG voltage regulator). This is the input side of the bootstrap charging resistor.
2 2 $24N3596 ✅ Connected to the bootstrap capacitor C186 pin 1. This is the output side of the bootstrap charging resistor.
C186 - 2222-0008 ❌

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Pin Designator Pin Name Net Correct? Analysis
2 2 $24N3595 ❌
Connected to SW1 (U26 pin 10), but should be connected to VGFX-SW (the main switching node). The bootstrap capacitor must reference the actual switching node where the inductor connects for proper gate driver operation.
  • Pin 2 is connected to net $24N3595 (from schematic)
  • Net $24N3595 connects only to U26 pin 10 (SW1) (from schematic)
  • The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) (from schematic)
  • The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node where power conversion occurs (from schematic)
  • Net $24N3595 (SW1) is isolated from VGFX-SW and has no other connections besides U26 pin 10 and C186 pin 2 (from schematic)
  • In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET (reasoning)
  • The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects to extract power (reasoning)
  • The bootstrap capacitor charges when the low-side FET is on (switching node is low) and provides voltage to drive the high-side FET gate when it turns on (reasoning)
  • For the bootstrap circuit to function, the capacitor must be referenced to the actual switching node voltage, not to an isolated pin (reasoning)
  • Since the inductor L4 connects to VGFX-SW, this is the actual switching node, and the bootstrap capacitor should be connected between BST and VGFX-SW (reasoning)
  • The current configuration with C186 pin 2 connected to the isolated SW1 pin will not provide proper bootstrap voltage for the gate driver, as SW1 does not follow the switching node voltage (reasoning)
  • Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit (reasoning)
1 1 $24N3596 ✅ Connected to R228 pin 2, forming the intermediate node in the bootstrap charging circuit between the BST pin and the bootstrap capacitor.
R846 - 1130-0193 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Connected to +5VSB supply rail. This pin incorrectly attempts to supply power to the VCCP pin of U26, which is an internal LDO output that should not be externally driven.
2 2 $24N3578 ✅ Connected to net $24N3578, which feeds the VCCP pin (pin 33) of U26. This connection is incorrect as VCCP is an internal LDO output that should not be driven from an external source.
R229 - 1130-0234 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Connected to +5VSB supply rail. This pin sources power for the VCC bias supply of U26 through the 2.2 ohm current-limiting resistor.
2 2 $24N3610 ✅ Connected to net $24N3610, which supplies U26 pin 47 (VCC) and is bypassed by C53. This provides the bias supply voltage for the controller IC.
C185 - 2232-0016 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3578 ✅ Connected to net $24N3578, which is the VCCP charge pump supply for U26 after current limiting by R846. This pin provides bypass capacitance for the charge pump supply.
2 2 GND ✅ Connected to GND power ground. This provides the return path for the VCCP bypass capacitor, referenced to power ground to keep charge pump switching currents separate from the analog ground.
C53 - 2222-0014 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3610 ✅ Connected to net $24N3610, which is the VCC supply for U26 after current limiting by R229. This pin provides bypass capacitance for the controller bias supply.
2 2 AGND-VGFX ✅ Connected to AGND-VGFX analog ground. This provides the return path for the VCC bypass capacitor, correctly referenced to the analog ground plane.
R203 - 1120-0351 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3542 ✅ Pin 1 connects to the FREQ pin (pin 41) of U26 (NCP81109GMNTXG) to set the switching frequency. A nearby text note indicates the target frequency is 650 kHz.
2 2 AGND-VGFX ✅ Pin 2 connects to AGND-VGFX, which is the analog ground reference for the VGFX voltage regulator circuit.
R227 - 1120-0338 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3589 ✅ Connected to U26 pin 36 (IOUT) for current monitoring. Forms part of the current sense output circuit with C184.
2 2 AGND-VGFX ✅ Connected to AGND-VGFX, the analog ground reference for the voltage regulator.
C184 - 2220-0025 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3589 ✅ Connected to U26 pin 36 (IOUT) for filtering the current monitoring signal. Works in conjunction with R227.
2 2 AGND-VGFX ✅ Connected to AGND-VGFX, the analog ground reference for the voltage regulator.
R207 - 1120-0115 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3588 ✅ Connected to U26 pin 35 (IMAX) to set the maximum current limit. A nearby text note indicates the target is 14A.
2 2 AGND-VGFX ✅ Connected to AGND-VGFX, the analog ground reference for the voltage regulator.
C187 - 2240-0005 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $24N3623 ✅ Connected to intermediate node of RC snubber circuit from R231 pin 2. Forms the capacitive element of the snubber to ground.
2 2 GND ✅ Connected to GND. Completes the RC snubber circuit path from the switching node to ground.
R231 - 1141-0026 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VGFX-SW ✅ Connected to VGFX-SW switching node. Forms the series element of an RC snubber circuit to dampen high-frequency ringing on the switching node.
2 2 $24N3623 ✅ Connected to intermediate node of RC snubber circuit, connecting to C187 pin 1. This forms the junction between the resistor and capacitor in the snubber.
R66 - 1121-0001 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to main power ground (GND). This is the expected connection for one side of the ground jumper.
2 2 AGND-VGFX ✅ Connected to analog ground (AGND-VGFX). This is the expected connection for the other side of the ground jumper.
U41 - RT8207 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VTTGND GND ✅ VTTGND is correctly connected to GND for the VTT LDO power ground.
2 VTTSNS +VDIMM_VTT ✅ VTTSNS is correctly connected to +VDIMM_VTT for remote voltage sensing at the output capacitors.
3 GND GND ✅ GND is correctly connected to system ground for analog ground reference.
4 MODE GND ✅ MODE is connected to GND, which is a typical configuration for mode selection pins.
5 VTTREF $25N769 ✅ VTTREF is correctly connected to a bypass capacitor (C342, 0.22µF) to GND for stable buffered reference operation.
6 DEM $25N1291 ✅ DEM is connected to a 10K pull-up resistor to +5VSB, likely for diode emulation mode control.
8 VDDQ +VDIMM ✅ VDDQ is correctly connected to the +VDIMM output rail for reference input and feedback.
9 FB $25N987 ✅ FB is correctly connected to a resistive voltage divider (R814/R815) for adjustable output voltage setting at 1.35V (DDR3L).
10 S3 EN_VTT ✅ S3 is correctly connected to EN_VTT (derived from SLP_S3_L) for VTT output state control.
11 S5 EN_VDDQ ✅ S5 is correctly connected to EN_VDDQ (derived from SLP_S4_L) for overall power state control.
12 TON $25N1081 ✅ TON is correctly connected to +5VSB through R816 (464K) to set the switching frequency. However, there is a significant discrepancy between the actual resistor value and the schematic design note which specifies 806K for 285kHz operation, resulting in approximately 504kHz actual switching frequency instead of the intended 285kHz.
13 PGOOD DRAM_PWROK ✅ PGOOD is correctly connected as an open-drain output to DRAM_PWROK with an external pull-up resistor.
14 VDD $25N1195 ✅ VDD is correctly connected to a filtered analog supply with 2.2Ω resistor from +5VSB and 1µF bypass capacitor.
15 VDDP +5VSB ✅ VDDP is correctly connected to +5VSB as the main supply for gate drivers.
16 CS $25N1238 ✅ CS is correctly connected to VDD through a 3.83K resistor for current limit threshold setting.
18 PGND GND ✅ PGND is correctly connected to system ground for low-side MOSFET power ground.
19 LGATE $25N901 ✅ LGATE is correctly connected to the low-side MOSFET gate (Q102 pin 8).
20 PHASE DDR_PHASE ✅ PHASE is correctly connected to the switch node (Q102 pin 9) and output inductor (L11).
21 UGATE $25N897 ✅ UGATE is correctly connected to the high-side MOSFET gate (Q102 pin 1).
22 BOOT $25N771 ✅ BOOT is connected to a bootstrap network with C309 (0.1µF) and R298 (4.7Ω). The bootstrap capacitor is significantly smaller than the 1µF recommended by the datasheet, which may cause insufficient gate drive voltage.
23 VLDOIN +VDIMM ✅ VLDOIN is correctly connected to +VDIMM for tracking discharge mode operation.
24 VTT +VDIMM_VTT ✅ VTT is correctly connected to +VDIMM_VTT output with appropriate output capacitors (20µF total).
25 GND_PAD GND ✅ GND_PAD is correctly connected to system ground for thermal dissipation.
Q102 - FDMS3604S ✅

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Pin Designator Pin Name Net Correct? Analysis
1 Q1G $25N897 ✅ Q1G (high-side gate) is correctly connected to the controller's UGATE output (U41 pin 21) to drive the control MOSFET.
2 VIN_A DDR3L_VIN ✅ VIN_A, VIN_B, VIN_C (drain pins of Q1) are correctly connected to the DDR3L_VIN input rail with appropriate input decoupling capacitors.
3 VIN_B DDR3L_VIN ✅ VIN_A, VIN_B, VIN_C (drain pins of Q1) are correctly connected to the DDR3L_VIN input rail with appropriate input decoupling capacitors.
4 VIN_C DDR3L_VIN ✅ VIN_A, VIN_B, VIN_C (drain pins of Q1) are correctly connected to the DDR3L_VIN input rail with appropriate input decoupling capacitors.
5 PGND_A GND ✅ PGND_A, PGND_B, PGND_C (source pins of Q2) are correctly connected to GND for the synchronous MOSFET return path.
6 PGND_B GND ✅ PGND_A, PGND_B, PGND_C (source pins of Q2) are correctly connected to GND for the synchronous MOSFET return path.
7 PGND_C GND ✅ PGND_A, PGND_B, PGND_C (source pins of Q2) are correctly connected to GND for the synchronous MOSFET return path.
8 Q2G $25N901 ✅ Q2G (low-side gate) is correctly connected to the controller's LGATE output (U41 pin 19) to drive the synchronous MOSFET.
9 PHASE DDR_PHASE ✅ PHASE (switch node) is correctly connected to the output inductor L11 and controller PHASE pin for current sensing in the synchronous buck converter.
L6 - 126-0004457 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Pin 1 is correctly connected to the +5VSB standby power rail, serving as the input to the ferrite bead filter in parallel with L5.
2 2 DDR3L_VIN ✅ Pin 2 is correctly connected to the DDR3L_VIN net, providing filtered power to the DDR memory power supply input in parallel with L5.
L5 - 126-0004457 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Pin 1 is correctly connected to the +5VSB standby power rail, serving as the input to the ferrite bead filter.
2 2 DDR3L_VIN ✅ Pin 2 is correctly connected to the DDR3L_VIN net, providing filtered power to the DDR memory power supply input.
L11 - 125-0004454 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DDR_PHASE ✅ Pin 1 connects to the switching node DDR_PHASE from the RT8207 controller and FDMS3604S MOSFETs. This is the correct connection for the input side of the output filter inductor in this synchronous buck converter.
2 2 +VDIMM ✅ Pin 2 connects to the +VDIMM output rail. This is the correct connection for the output side of the filter inductor, providing filtered DC power to the DDR memory voltage rail.
R814 - 1120-0187 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM ✅ Upper resistor in feedback voltage divider, connected to +VDIMM output rail. Forms part of the feedback network for U41 (RT8207) VDDQ regulator.
2 2 $25N987 ✅ Feedback divider node connected to U41 pin 9 (FB) through net $25N987. Forms the center tap of the voltage divider with R815.
C382 - 2220-0047 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VDIMM ✅ AC compensation capacitor connected to +VDIMM output rail. Forms high-frequency compensation network in parallel with R814.
2 2 $25N987 ✅ Feedback node connection providing AC compensation. Connected to U41 pin 9 (FB) through net $25N987.
R815 - 1120-0011 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $25N987 ✅ Lower resistor in feedback voltage divider, connected to feedback node $25N987. Completes the voltage divider with R814 to set output voltage.
2 2 GND ✅ Ground connection for feedback voltage divider. Completes the divider path from +VDIMM through R814, R815 to ground.
R817 - 1120-0267 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $25N1195 ✅ Connected to VDD supply pin of U41 through net $25N1195. VDD is supplied from +5VSB through R813 (2.2 ohm) and bypassed by C380 (1uF).
2 2 $25N1238 ✅ Connected to CS (current sense) pin of U41 through net $25N1238. This connection, along with pin 1 to VDD, forms a resistor divider or reference circuit for overcurrent protection.
C309 - 123-0001056 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 DDR_PHASE ✅ Connected to the switching node (DDR_PHASE) of the buck converter, which includes the PHASE output of controller U41 and the PHASE pin of MOSFET Q102. This is the correct connection for one side of the bootstrap capacitor.
2 2 DDR_BST ✅ Connected to intermediate node DDR_BST, which connects through R298 to the BOOT pin of U41. This forms a bootstrap circuit with series damping resistor, which is a valid configuration.
R298 - 110-0004467 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $25N771 ✅ Connected to the BOOT pin of the RT8207 controller (U41 pin 22) via net $25N771. This is the correct connection for the bootstrap circuit series resistor.
2 2 DDR_BST ✅ Connected to intermediate node DDR_BST, which connects to bootstrap capacitor C309. This completes the bootstrap circuit with series damping resistor configuration.
R813 - 110-0004466 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 $25N1195 ✅ Pin 1 connects to net $25N1195, which supplies the VDD pin (pin 14) of U41 (RT8207 DDR power controller). This net is decoupled by C380 (1uF) and also connects to the current sense divider network through R817.
2 2 +5VSB ✅ Pin 2 connects to the +5VSB power rail, which is the standby 5V supply. This rail also directly supplies U41 pin 15 (VDDP) and other circuit elements through ferrite beads L5 and L6.
R816 - 1120-0149 ❌

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Pin Designator Pin Name Net Correct? Analysis
2 2 $25N1081 ❌
Connected to U41 pin 12 (TON) to set the switching frequency. However, the resistor value is 464K, which results in approximately 504 kHz switching frequency, not the specified 285 kHz that requires 806K per the design note.
  • Pin 2 is connected to net $25N1081 (from schematic)
  • Net $25N1081 connects to U41 pin 12 (TON) and C378 pin 2 (DNI) (from schematic)
  • C378 is marked DNI (Do Not Install), so it is electrically absent and does not affect the circuit (from schematic)
  • R816 has a value of 464K ohms per part number 1120-0149 (from schematic)
  • The design note states 'Rton=806K , F=285KHz' as the intended design specification (from schematic)
  • The design note provides the formula F= (Vin - 0.5) / 3.85pVinRton for calculating switching frequency (from schematic)
  • Using the formula with Vin=5V and Rton=806K: F = (5-0.5)/(3.85e-125806000) = 290 kHz, approximately matching the specified 285 kHz (reasoning)
  • Using the formula with Vin=5V and the actual Rton=464K: F = (5-0.5)/(3.85e-125464000) = 504 kHz (reasoning)
  • The actual resistor value of 464K results in a switching frequency of approximately 504 kHz, which is 77% higher than the specified 285 kHz (reasoning)
  • No other resistors are connected in parallel or series with R816 on the TON pin that would modify the effective resistance (from schematic)
  • The resistor value should be changed to approximately 806K to meet the design specification of 285 kHz switching frequency (reasoning)
1 1 +5VSB ✅ Connected to +5VSB power rail, providing the reference voltage for the TON timing resistor. This connection is correct.
U21 - LDO_ULD_3A_SO8 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 PGOOD +V1P8S_PGD ✅ PGOOD pin is correctly connected to +V1P8S_PGD net with pull-up resistor R23 (4.7K) to +V1P8S output.
2 EN +V1P8S_EN ✅ EN pin is correctly connected to +V1P8S_EN net through 0 ohm resistor R22 from 1P8V_EN signal.
3 VIN +PS_3VSB ✅ VIN pin is correctly connected to +PS_3VSB input supply with adequate input capacitance.
4 VDD +PS_3VSB ✅ VDD pin is correctly connected to +PS_3VSB input supply, same as VIN.
5 NC ✅ NC pin is correctly left unconnected as specified.
6 VOUT +V1P8S ✅ VOUT pin is correctly connected to +V1P8S output rail with adequate output capacitance.
7 ADJ +V1P8S_FB ✅ ADJ pin is correctly connected to feedback divider network (R24=12.1K to output, R25=9.53K to ground) setting output to approximately 1.816V.
8 GND1 GND ✅ GND1 and GND2 pins are both correctly connected to ground plane.
9 GND2 GND ✅ GND1 and GND2 pins are both correctly connected to ground plane.
R24 - 110-0002560 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Upper feedback resistor (R1) correctly connects output +V1P8S to feedback pin +V1P8S_FB with 12.1K ohm value.
2 2 +V1P8S_FB ✅ Upper feedback resistor (R1) correctly connects output +V1P8S to feedback pin +V1P8S_FB with 12.1K ohm value.
R23 - 110-0002058 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8S ✅ Pull-up resistor correctly connects power good signal +V1P8S_PGD to output rail +V1P8S with 4.7K ohm value.
2 2 +V1P8S_PGD ✅ Pull-up resistor correctly connects power good signal +V1P8S_PGD to output rail +V1P8S with 4.7K ohm value.
R25 - 110-0004490 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Lower feedback resistor (R2) correctly connects feedback pin +V1P8S_FB to ground with 9.53K ohm value.
2 2 +V1P8S_FB ✅ Lower feedback resistor (R2) correctly connects feedback pin +V1P8S_FB to ground with 9.53K ohm value.
R22 - 110-0001853 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V_EN ✅ Zero ohm resistor correctly passes enable signal from 1P8V_EN to +V1P8S_EN for U21 enable control.
2 2 +V1P8S_EN ✅ Zero ohm resistor correctly passes enable signal from 1P8V_EN to +V1P8S_EN for U21 enable control.
R134 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 V1P0S_PG ✅ 1kΩ resistor connecting V1P0S_PG to 1P35V_EN (gate of Q5). Provides current limiting for gate drive and creates ~100μs time constant with C105 for controlled turn-on of the +V1P35S rail.
2 2 1P35V_EN ✅ 1kΩ resistor connecting V1P0S_PG to 1P35V_EN (gate of Q5). Provides current limiting for gate drive and creates ~100μs time constant with C105 for controlled turn-on of the +V1P35S rail.
R120 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P35S ✅ 10kΩ resistor connecting +V1P35S to 1P35V_PWG (base of Q3 transistor 1). Provides base drive for power sequencing logic that controls the 1.8V regulator enable.
2 2 1P35V_PWG ✅ 10kΩ resistor connecting +V1P35S to 1P35V_PWG (base of Q3 transistor 1). Provides base drive for power sequencing logic that controls the 1.8V regulator enable.
R126 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ 4.7kΩ pull-up resistor connecting +5VSB to 1P5V_EN_B. Pulls up the collector of Q3 transistor 1 and provides base drive for Q3 transistor 2 in the cascaded power sequencing circuit.
2 2 1P5V_EN_B ✅ 4.7kΩ pull-up resistor connecting +5VSB to 1P5V_EN_B. Pulls up the collector of Q3 transistor 1 and provides base drive for Q3 transistor 2 in the cascaded power sequencing circuit.
R125 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC ✅ 4.7kΩ pull-up resistor connecting +VCC to 1P8V_EN. Pulls up the collector of Q3 transistor 2 to enable the 1.8V regulator (U21) as part of the power sequencing logic.
2 2 1P8V_EN ✅ 4.7kΩ pull-up resistor connecting +VCC to 1P8V_EN. Pulls up the collector of Q3 transistor 2 to enable the 1.8V regulator (U21) as part of the power sequencing logic.
Q3 - XSTR_NPN_DUAL_40V_SOT-363 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 E1 GND ✅ Emitter 1 is correctly connected to GND for NPN transistor operation.
2 B1 1P35V_PWG ✅ Base 1 is correctly driven from +V1P35S through R120 (10kΩ) to sense when the 1.35V rail is present.
3 C2 1P8V_EN ✅ Collector 2 is correctly connected to 1P8V_EN, which is pulled up through R125 (4.7kΩ) to +VCC.
4 E2 GND ✅ Emitter 2 is correctly connected to GND for NPN transistor operation.
5 B2 1P5V_EN_B ✅ Base 2 is correctly connected to 1P5V_EN_B, which is the same net as Collector 1 (pin 6), creating a cascaded transistor configuration.
6 C1 1P5V_EN_B ✅ Collector 1 is correctly connected to 1P5V_EN_B, which is pulled up through R126 (4.7kΩ) to +5VSB and also drives Base 2 (pin 5).
Q5 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

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Pin Designator Pin Name Net Correct? Analysis
D DRAIN +VDIMM ✅ Drain is correctly connected to +VDIMM input power rail for high-side switch configuration.
G GATE 1P35V_EN ✅ Gate is driven from V1P0S_PG through R134 (1kΩ). Gate drive voltage may be marginal if +VCC is 3.3V, resulting in VGS ≈ 1.95V, which is below the 2V design guideline noted on the schematic but within the VGS(th) range of 1.0-2.5V.
S SOURCE +V1P35S ✅ Source is correctly connected to +V1P35S output rail for high-side switch configuration.
U38 - LDO_ULD_5A_SO8 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 GND GND ✅ Ground pin correctly connected to GND net.
2 FB FB_V1P0S ✅ Feedback pin connected to resistor divider network (R135 and R136). The divider is correctly configured but sets output to 1.025V. Based on schematic notes indicating combined load requirements of 1.3A at 1.05V and 3.6A at 1.0V, and the note 'Combine +V1P0S and +V1P05S', the output voltage may be insufficient for loads requiring 1.05V. The root cause is the incorrect value of R136.
3 VOUT-2 +V1P0S ✅ Output pins correctly connected to +V1P0S rail with appropriate decoupling capacitors.
4 VOUT-1 +V1P0S ✅ Output pins correctly connected to +V1P0S rail with appropriate decoupling capacitors.
5 VIN-2 +VDIMM ✅ Input voltage pins correctly connected to +VDIMM supply rail.
9 VIN-1 +VDIMM ✅ Input voltage pins correctly connected to +VDIMM supply rail.
6 VCNTL VCNTL_V1P0S ✅ Voltage control pin connected to RC network with 10 ohm resistor to +VCC and 1uF capacitor to ground.
7 POK V1P0S_PG ✅ Power good output pin correctly connected with 10K pull-up resistor and used for downstream power sequencing.
8 EN 1P0V_EN ✅ Enable pin correctly connected to power sequencing signal through 0-ohm jumper resistor.
R136 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 FB_V1P0S ✅ Upper feedback resistor (R1) in voltage divider. Current value of 40.2K results in 1.025V output. Based on schematic notes indicating combined load requirements (1.3A at 1.05V and 3.6A at 1.0V) and the note 'Combine +V1P0S and +V1P05S', the resistor value should be approximately 44.2K to achieve 1.05V output and properly supply all loads.
2 2 +V1P0S ✅ Upper feedback resistor (R1) in voltage divider. Current value of 40.2K results in 1.025V output. Based on schematic notes indicating combined load requirements (1.3A at 1.05V and 3.6A at 1.0V) and the note 'Combine +V1P0S and +V1P05S', the resistor value should be approximately 44.2K to achieve 1.05V output and properly supply all loads.
R135 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Lower feedback resistor (R2) in voltage divider, correctly connected between FB pin and ground to set output voltage.
2 2 FB_V1P0S ✅ Lower feedback resistor (R2) in voltage divider, correctly connected between FB pin and ground to set output voltage.
R306 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCORE_GFX_PG ✅ Zero-ohm jumper resistor implementing power sequencing by connecting graphics core power good to regulator enable.
2 2 1P0V_EN ✅ Zero-ohm jumper resistor implementing power sequencing by connecting graphics core power good to regulator enable.
R319 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 V1P0S_PG ✅ Pull-up resistor for power good signal, correctly connected between V1P0S_PG and +VCC.
2 2 +VCC ✅ Pull-up resistor for power good signal, correctly connected between V1P0S_PG and +VCC.
R320 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 VCNTL_V1P0S ✅ Control resistor forming RC network with C117 for VCNTL pin, connected between +VCC and VCNTL_V1P0S.
2 2 +VCC ✅ Control resistor forming RC network with C117 for VCNTL pin, connected between +VCC and VCNTL_V1P0S.
U20 - NCP606 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 VIN1 +PS_3VSB ✅ VIN1 and VIN2 are both correctly connected to +PS_3VSB input supply. Both pins must be connected together externally per datasheet requirements for full output current range operation.
6 VIN2 +PS_3VSB ✅ VIN1 and VIN2 are both correctly connected to +PS_3VSB input supply. Both pins must be connected together externally per datasheet requirements for full output current range operation.
2 GND GND ✅ GND and GND_PAD are both correctly connected to the GND net. The exposed pad connection to ground provides thermal relief as required.
7 GND_PAD GND ✅ GND and GND_PAD are both correctly connected to the GND net. The exposed pad connection to ground provides thermal relief as required.
3 EN +V1P8A_EN ✅ EN pin is correctly connected to +V1P8A_EN which implements power sequencing. The enable signal is derived from U24's power good output through R151, ensuring U24 (1.0V regulator) is stable before U20 (1.8V regulator) enables.
4 VOUT +V1P8A ✅ VOUT pin is correctly connected to +V1P8A output net with adequate decoupling. Output capacitor C151 (10uF) exceeds the 1.0 µF minimum requirement.
5 SENSE/ADJ +V1P8A_FB ✅ SENSE/ADJ pin is correctly connected to feedback divider network formed by R150 (12.1K) and R153 (27.4K). The calculated output voltage is approximately 1.802V, matching the intended 1.8V output.
R151 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0A_PWRGD ✅ R151 (0 ohm jumper) correctly implements power sequencing by connecting the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN).
2 2 +V1P8A_EN ✅ R151 (0 ohm jumper) correctly implements power sequencing by connecting the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN).
R153 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A_FB ✅ R153 (27.4K ohm) is correctly configured as R2 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and ground.
2 2 GND ✅ R153 (27.4K ohm) is correctly configured as R2 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and ground.
R150 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P8A_FB ✅ R150 (12.1K ohm) is correctly configured as R1 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and output (+V1P8A).
2 2 +V1P8A ✅ R150 (12.1K ohm) is correctly configured as R1 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and output (+V1P8A).
R34 - 6.04K ohm 1% 1/16W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0A_FB ✅ Upper resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and VOUT (pin 2) to set output voltage to 1.0V.
2 2 +V1P0A ✅ Upper resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and VOUT (pin 2) to set output voltage to 1.0V.
R35 - 23.7K ohm 1% 1/4W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0A_FB ✅ Lower resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and GND (pin 2) to set output voltage to 1.0V.
2 2 GND ✅ Lower resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and GND (pin 2) to set output voltage to 1.0V.
R32 - 4.7K ohm 1% 1/10W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +5VSB ✅ Enable pull-up resistor, correctly connected between +5VSB (pin 1) and EN pin of U24 (pin 2) to enable the regulator when +5VSB is present.
2 2 +V1P0A_ENABLE ✅ Enable pull-up resistor, correctly connected between +5VSB (pin 1) and EN pin of U24 (pin 2) to enable the regulator when +5VSB is present.
R33 - 4.7K ohm 1% 1/10W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +PS_3VSB ✅ Power good pull-up resistor, correctly connected between +PS_3VSB (pin 1) and PGOOD pin of U24 (pin 2) to provide proper logic levels for open-drain output.
2 2 +V1P0A_PWRGD ✅ Power good pull-up resistor, correctly connected between +PS_3VSB (pin 1) and PGOOD pin of U24 (pin 2) to provide proper logic levels for open-drain output.
U24 - LDO_ULD_3A_SO8 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 PGOOD +V1P0A_PWRGD ✅ PGOOD pin correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB. Used for power sequencing to enable downstream regulator U20.
2 EN +V1P0A_ENABLE ✅ EN pin correctly connected to +V1P0A_ENABLE with pull-up resistor R32 to +5VSB and bypass capacitor C20 to ground. Enable threshold requirement >1.1V is met.
3 VIN +PS_3VSB ✅ VIN pin correctly connected to +PS_3VSB (3.3V standby rail) with appropriate input bypass capacitors nearby.
4 VDD +PS_3VSB ✅ VDD pin correctly connected to +PS_3VSB, same as VIN. This is typical for LDOs with separate VIN and VDD pins.
5 NC ✅ NC pin has no connection, which is correct for a no-connect pin.
6 VOUT +V1P0A ✅ VOUT pin correctly connected to +V1P0A output rail with appropriate output capacitors C21 (22uF) and C22 (0.1uF) for stability.
7 ADJ +V1P0A_FB ✅ ADJ pin correctly connected to feedback divider network formed by R34 (6.04K) and R35 (23.7K), which sets output voltage to 1.0V per formula Vout=0.8(1+R1/R2).
8 GND1 GND ✅ GND1 and GND2 pins both correctly connected to GND. Dual ground pins are typical for power devices to handle high currents.
9 GND2 GND ✅ GND1 and GND2 pins both correctly connected to GND. Dual ground pins are typical for power devices to handle high currents.
R61 - 20K ohm 1% 1/10W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC3 ✅ Pull-up resistor from SYS_PWRGD to +VCC3, providing pull-up for the output signal.
2 2 SYS_PWRGD ✅ Pull-up resistor from SYS_PWRGD to +VCC3, providing pull-up for the output signal.
Q1 - XSTR_NPN_DUAL_40V_SOT-363 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 E1 GND ✅ Emitter of transistor 1 (E1) correctly connected to ground.
2 B1 PSGOOD ✅ Base of transistor 1 (B1) connected to PSGOOD signal, which is driven by a wired-AND gate through D11 and pulled up through R206.
3 C2 SYS_PWRGD ✅ Collector of transistor 2 (C2) connected to SYS_PWRGD output, pulled up through R61 to +VCC3.
4 E2 GND ✅ Emitter of transistor 2 (E2) correctly connected to ground.
5 B2 PSPUP ✅ Base of transistor 2 (B2) connected to PSPUP, which is driven by the collector of transistor 1 and pulled up through R60.
6 C1 PSPUP ✅ Collector of transistor 1 (C1) connected to PSPUP, which drives the base of transistor 2 and is pulled up through R60.
R60 - 20K ohm 1% 1/10W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +PS_3VSB ✅ Pull-up resistor from PSPUP to +PS_3VSB, providing pull-up for the intermediate signal between the two transistors in Q1.
2 2 PSPUP ✅ Pull-up resistor from PSPUP to +PS_3VSB, providing pull-up for the intermediate signal between the two transistors in Q1.
D11 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +V1P0A_PWRGD ✅ Anode 1 connected to +V1P0A_PWRGD power good signal.
2 2 SLP_S3_L ✅ Anode 2 connected to SLP_S3_L sleep signal.
3 3 PSGOOD ✅ Common cathode connected to PSGOOD, forming a wired-AND gate with the two input signals.
R206 - 200K ohm 1% 1/10W 0402 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 PSGOOD ✅ Pull-up resistor from PSGOOD to +V1P8S, providing both pull-up function and RC delay with C44.
2 2 +V1P8S ✅ Pull-up resistor from PSGOOD to +V1P8S, providing both pull-up function and RC delay with C44.
FB7 - 110-0002124 ✅

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Pin Designator Pin Name Net Correct? Analysis
1 1 +VCC3 ✅ Input pin connected to +VCC3 power rail. This pin receives 3.3V power that will be passed through to the CPU supply rail.
2 2 +VCC3S ✅ Output pin connected to +VCC3S power rail that supplies the CPU. The rail is decoupled by C247 and carries approximately 43mA according to schematic notes.
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# DRCY Connections Checker Review DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 400 component(s) to review, and found 12 potential issue(s) in 15 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary><b>Component Details</b></summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AK12 | DDI0_RCOMP_P | DDI_RCOMP_N | ❌ | <details><summary>DDI0 RCOMP pins are swapped. AK13 (negative RCOMP) is connected to DDI_RCOMP_P, and AK12 (positive RCOMP) is connected to DDI_RCOMP_N.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,31.55,45.57,39.05" aspect-ratio="1.29" } <ul><li>Pin AK13 has the name D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating negative/complement signal <em>(from schematic)</em></li><li>Pin AK12 has the name DDI0_RCOMP_P with _P suffix indicating positive signal <em>(from schematic)</em></li><li>Pin AK13 is connected to net DDI_RCOMP_P (positive net name) <em>(from schematic)</em></li><li>Pin AK12 is connected to net DDI_RCOMP_N (negative net name) <em>(from schematic)</em></li><li>The overline notation in pin names is a standard convention to indicate active-low or complement signals <em>(reasoning)</em></li><li>A 402 ohm resistor (R217) is connected between DDI_RCOMP_N and DDI_RCOMP_P <em>(from schematic)</em></li><li>The RCOMP pins require an external resistor for display port compensation per Intel Atom E3800 design guidelines <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>The polarity of the RCOMP connections is reversed - the negative pin is connected to the positive net and vice versa <em>(reasoning)</em></li><li>The connections should be corrected: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P <em>(reasoning)</em></li></ul></details> | | AK13 | ~DDI0_RCOMP | DDI_RCOMP_P | ❌ | <details><summary>DDI0 RCOMP pins are swapped. AK13 (negative RCOMP) is connected to DDI_RCOMP_P, and AK12 (positive RCOMP) is connected to DDI_RCOMP_N.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,38.46" aspect-ratio="1.29" } <ul><li>Pin AK13 has the name D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating negative/complement signal <em>(from schematic)</em></li><li>Pin AK12 has the name DDI0_RCOMP_P with _P suffix indicating positive signal <em>(from schematic)</em></li><li>Pin AK13 is connected to net DDI_RCOMP_P (positive net name) <em>(from schematic)</em></li><li>Pin AK12 is connected to net DDI_RCOMP_N (negative net name) <em>(from schematic)</em></li><li>The overline notation in pin names is a standard convention to indicate active-low or complement signals <em>(reasoning)</em></li><li>A 402 ohm resistor (R217) is connected between DDI_RCOMP_N and DDI_RCOMP_P <em>(from schematic)</em></li><li>The RCOMP pins require an external resistor for display port compensation per Intel Atom E3800 design guidelines <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>The polarity of the RCOMP connections is reversed - the negative pin is connected to the positive net and vice versa <em>(reasoning)</em></li><li>The connections should be corrected: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P <em>(reasoning)</em></li></ul></details> | | A29 | RESERVED_A29 | GPIO_NC13 | ✅ | RESERVED_A29 pin connected to GPIO_NC13 with 10K pull-down resistor R102. | | B26 | DDI0_BKLTCTL | | ✅ | DDI0_BKLTCTL pin for backlight control, connection not shown in this schematic section. | | B28 | DDI0_VDDEN | | ✅ | DDI0_VDDEN signal is not connected, which is acceptable for HDMI mode operation. | | B30 | GPIO_S0_NC12 | $3N566 | ✅ | GPIO_S0_NC12 connected to test point TP15 which is marked DNI, leaving the pin effectively floating. | | C26 | DDI0_DDCDATA | HDMI_DDCDAT | ✅ | DDI0_DDCDATA connected to HDMI_DDCDAT for HDMI monitor communication via DDC. | | C27 | DDI0_BKLTEN | | ✅ | DDI0_BKLTEN signal is not connected, which is acceptable for HDMI mode operation. | | C28 | DDI0_DDCCLK | HDMI_DDCCLK | ✅ | DDI0_DDCCLK connected to HDMI_DDCCLK for HDMI monitor communication via DDC. | | C29 | RESERVED_C29 | | ✅ | Reserved pins with no connections, which is standard practice. | | C30 | RESERVED_C30 | | ✅ | Reserved pins with no connections, which is standard practice. | | D27 | DDI0_HPD | HDMI_HPD_B | ✅ | DDI0_HPD connected to HDMI_HPD_B, which is the inverted hot plug detect signal from U39. | | D28 | RESERVED_D28 | | ✅ | Reserved pins with no connections, which is standard practice. | | D32 | RESERVED_D32 | | ✅ | Reserved pins with no connections, which is standard practice. | | D34 | RESERVED_D34 | | ✅ | Reserved pins with no connections, which is standard practice. | | F28 | RESERVED_F28 | | ✅ | Reserved pins with no connections, which is standard practice. | | F32 | RESERVED_F32 | | ✅ | Reserved pins with no connections, which is standard practice. | | F34 | RESERVED_F34 | | ✅ | Reserved pins with no connections, which is standard practice. | | G30 | DDI1_DDCCLK | GND | ✅ | DDI1_DDCCLK grounded, indicating DDI1 port is disabled. | | J28 | RESERVED_J28 | | ✅ | DDI1_BKLTEN is not connected and J28, J34 are reserved pins, all consistent with DDI1 being disabled. | | J30 | DDI1_BKLTEN | | ✅ | DDI1_BKLTEN is not connected and J28, J34 are reserved pins, all consistent with DDI1 being disabled. | | J34 | RESERVED_J34 | | ✅ | DDI1_BKLTEN is not connected and J28, J34 are reserved pins, all consistent with DDI1 being disabled. | | K28 | RESERVED_K28 | | ✅ | DDI1_HPD is connected to GND to disable the port, and K28, K34 are reserved pins. | | K34 | RESERVED_K34 | | ✅ | DDI1_HPD is connected to GND to disable the port, and K28, K34 are reserved pins. | | K30 | DDI1_HPD | GND | ✅ | DDI1_HPD grounded, indicating DDI1 port is disabled. | | M30 | DDI1_BKLTCTL | | ✅ | DDI1_BKLTCTL is not connected, consistent with DDI1 being disabled. | | M32 | RESERVED_M32 | | ✅ | Reserved pin with no connection, which is standard practice. | | N30 | DDI1_VDDEN | | ✅ | DDI1_VDDEN is not connected, consistent with DDI1 being disabled. | | N32 | RESERVED_N32 | | ✅ | Reserved pin with no connection, which is standard practice. | | P14 | RESERVED_P14 | MCSI_RCOMP | ✅ | RESERVED_P14 connected to MCSI_RCOMP with 150 ohm termination resistor R213. | | P30 | DDI1_DDCDATA | DDI1_DDCDAT | ✅ | DDI1_DDCDATA connected to DDI1_DDCDAT with 2.2K pull-down resistor R257, though DDI1 is otherwise disabled. | | R1 | RESERVED_R1 | | ✅ | Reserved pins with no connections, which is standard practice. | | R3 | RESERVED_R3 | | ✅ | Reserved pins with no connections, which is standard practice. | | T2 | RESERVED_T2 | | ✅ | Reserved pins with no connections, which is standard practice. | | T3 | RESERVED_T3 | | ✅ | Reserved pins with no connections, which is standard practice. | | T4 | RESERVED_T4 | | ✅ | Reserved pins with no connections, which is standard practice. | | T6 | RESERVED_T6 | | ✅ | Reserved pins with no connections, which is standard practice. | | T7 | RESERVED_T7 | | ✅ | Reserved pins with no connections, which is standard practice. | | T9 | RESERVED_T9 | | ✅ | Reserved pins with no connections, which is standard practice. | | T10 | RESERVED_T10 | | ✅ | Reserved pins with no connections, which is standard practice. | | T12 | RESERVED_T12 | | ✅ | Reserved pins with no connections, which is standard practice. | | T13 | RESERVED_T13 | | ✅ | Reserved pins with no connections, which is standard practice. | | T14 | RESERVED_T14 | | ✅ | Reserved pins with no connections, which is standard practice. | | V2 | RESERVED_V2 | | ✅ | Reserved pins with no connections, which is standard practice. | | V3 | RESERVED_V3 | | ✅ | Reserved pins with no connections, which is standard practice. | | V4 | RESERVED_V4 | | ✅ | Reserved pins with no connections, which is standard practice. | | V6 | RESERVED_V6 | | ✅ | Reserved pins with no connections, which is standard practice. | | V9 | RESERVED_V9 | | ✅ | Reserved pins with no connections, which is standard practice. | | V10 | RESERVED_V10 | | ✅ | Reserved pins with no connections, which is standard practice. | | V13 | RESERVED_V13 | | ✅ | Reserved pins with no connections, which is standard practice. | | V14 | RESERVED_V14 | | ✅ | Reserved pins with no connections, which is standard practice. | | W1 | RESERVED_W1 | | ✅ | Reserved pins with no connections, which is standard practice. | | W3 | RESERVED_W3 | | ✅ | Reserved pins with no connections, which is standard practice. | | Y2 | RESERVED_Y2 | | ✅ | Reserved pins with no connections, which is standard practice. | | Y3 | RESERVED_Y3 | | ✅ | Reserved pins with no connections, which is standard practice. | | Y4 | RESERVED_Y4 | | ✅ | Reserved pins with no connections, which is standard practice. | | Y6 | RESERVED_Y6 | | ✅ | Reserved pins with no connections, which is standard practice. | | Y12 | RESERVED_Y12 | | ✅ | Reserved pins with no connections, which is standard practice. | | Y13 | RESERVED_Y13 | | ✅ | Reserved pins with no connections, which is standard practice. | | BA1 | VGA_GREEN | | ✅ | VGA_GREEN analog output is not connected, consistent with VGA interface not being fully implemented. | | AB2 | RESERVED_AB2 | | ✅ | Reserved pins with no connections, which is standard practice. | | AB3 | RESERVED_AB3 | | ✅ | Reserved pins with no connections, which is standard practice. | | AB7 | RESERVED_AB7 | | ✅ | Reserved pins with no connections, which is standard practice. | | AB9 | RESERVED_AB9 | | ✅ | Reserved pins with no connections, which is standard practice. | | AB12 | RESERVED_AB12 | | ✅ | Reserved pins with no connections, which is standard practice. | | AB13 | RESERVED_AB13 | | ✅ | Reserved pins with no connections, which is standard practice. | | AB14 | RESERVED_AB14 | | ✅ | Reserved pins with no connections, which is standard practice. | | BA3 | VGA_RED | | ✅ | VGA_RED analog output is not connected, consistent with VGA interface not being fully implemented. | | AC1 | DDI1_TXN_3 | | ✅ | DDI1_TXN_3 and DDI1_TXP_3 differential transmit lane 3 signals are not connected, consistent with DDI1 port being intentionally disabled. | | AC3 | DDI1_TXP_3 | | ✅ | DDI1_TXN_3 and DDI1_TXP_3 differential transmit lane 3 signals are not connected, consistent with DDI1 port being intentionally disabled. | | BC1 | VGA_DDCCLK | CRT_CLK | ✅ | VGA_DDCCLK connected to CRT_CLK with 150 ohm series termination resistor R39. | | AD2 | DDI1_TXN_2 | | ✅ | DDI1_TXN_2 and DDI1_TXP_2 differential transmit lane 2 signals are not connected, consistent with DDI1 port being disabled. | | AD3 | DDI1_TXP_2 | | ✅ | DDI1_TXN_2 and DDI1_TXP_2 differential transmit lane 2 signals are not connected, consistent with DDI1 port being disabled. | | BC2 | VGA_DDCDATA | CRT_DAT | ✅ | VGA_DDCDATA connected to CRT_DAT with 150 ohm series termination resistor R38. | | AD4 | RESERVED_AD4 | | ✅ | Reserved pins with no connections, which is standard practice. | | AD6 | RESERVED_AD6 | | ✅ | Reserved pins with no connections, which is standard practice. | | BD2 | VGA_HSYNC | | ✅ | VGA_HSYNC signal is not connected, consistent with VGA interface not being fully implemented. | | AF2 | DDI1_TXN_1 | | ✅ | DDI1_TXN_1 and DDI1_TXP_1 differential transmit lane 1 signals are not connected, consistent with DDI1 port being disabled. | | AF3 | DDI1_TXP_1 | | ✅ | DDI1_TXN_1 and DDI1_TXP_1 differential transmit lane 1 signals are not connected, consistent with DDI1 port being disabled. | | AF13 | RESERVED_AF13 | | ✅ | Reserved pins with no connections, which is standard practice. | | AF14 | RESERVED_AF14 | | ✅ | Reserved pins with no connections, which is standard practice. | | AH13 | RESERVED_AH13 | | ✅ | Reserved pins with no connections, which is standard practice. | | AH14 | RESERVED_AH14 | | ✅ | Reserved pins with no connections, which is standard practice. | | AG1 | DDI1_TXN_0 | | ✅ | DDI1_TXN_0 and DDI1_TXP_0 differential transmit lane 0 signals are not connected, consistent with DDI1 port being disabled. | | AG3 | DDI1_TXP_0 | | ✅ | DDI1_TXN_0 and DDI1_TXP_0 differential transmit lane 0 signals are not connected, consistent with DDI1 port being disabled. | | BF2 | VGA_VSYNC | | ✅ | VGA_VSYNC signal is not connected, consistent with VGA interface not being fully implemented. | | AH2 | RESERVED_VSS3 | $3N554 | ✅ | RESERVED_VSS3 pin correctly connected to ground through 0 ohm resistor R43. | | AH3 | RESERVED_VSS2 | $3N552 | ✅ | RESERVED_VSS2 pin correctly connected to ground through 0 ohm resistor R46. | | AK2 | DDI1_AUXN | | ✅ | DDI1_AUXN and DDI1_AUXP auxiliary channel differential pair is not connected, consistent with DDI1 port being disabled. | | AK3 | DDI1_AUXP | | ✅ | DDI1_AUXN and DDI1_AUXP auxiliary channel differential pair is not connected, consistent with DDI1 port being disabled. | | AL1 | DDI0_AUXN | | ✅ | DDI0_AUXN and DDI0_AUXP auxiliary channel is not connected, which is correct for HDMI mode operation. | | AL3 | DDI0_AUXP | | ✅ | DDI0_AUXN and DDI0_AUXP auxiliary channel is not connected, which is correct for HDMI mode operation. | | AM2 | RESERVED_VSS1 | $3N589 | ✅ | RESERVED_VSS1 pin correctly connected to ground through 0 ohm resistor R41. | | AM3 | RESERVED_VSS0 | $3N579 | ✅ | RESERVED_VSS0 pin correctly connected to ground through 0 ohm resistor R42. | | AM13 | RESERVED_AM13 | | ✅ | Reserved pins with no connections, which is standard practice. | | AM14 | RESERVED_AM14 | | ✅ | Reserved pins with no connections, which is standard practice. | | AP2 | DDI0_TXN_3 | HDMI_CLK_DN | ✅ | DDI0_TXN_3 connected to HDMI_CLK_DN, providing the negative differential clock signal for HDMI interface. | | AP3 | DDI0_TXP_3 | HDMI_CLK_DP | ✅ | DDI0_TXP_3 connected to HDMI_CLK_DP, providing the positive differential clock signal for HDMI interface. | | AR1 | DDI0_TXN_2 | HDMI_TX0_DN | ✅ | DDI0_TXN_2 connected to HDMI_TX0_DN, providing negative differential data signal for HDMI data lane 0. | | AR3 | DDI0_TXP_2 | HDMI_TX0_DP | ✅ | DDI0_TXP_2 connected to HDMI_TX0_DP, providing positive differential data signal for HDMI data lane 0. | | AT2 | DDI0_TXP_1 | HDMI_TX1_DP | ✅ | DDI0_TXP_1 connected to HDMI_TX1_DP, providing positive differential data signal for HDMI data lane 1. | | AT3 | DDI0_TXN_1 | HDMI_TX1_DN | ✅ | DDI0_TXN_1 connected to HDMI_TX1_DN, providing negative differential data signal for HDMI data lane 1. | | AV2 | DDI0_TXN_0 | HDMI_TX2_DN | ✅ | DDI0_TXN_0 connected to HDMI_TX2_DN, providing negative differential data signal for HDMI data lane 2. | | AV3 | DDI0_TXP_0 | HDMI_TX2_DP | ✅ | DDI0_TXP_0 connected to HDMI_TX2_DP, providing positive differential data signal for HDMI data lane 2. | | AW1 | VGA_IREF | $3N548 | ✅ | VGA_IREF connected to 357 ohm reference resistor R40 to set VGA DAC output current. | | AY2 | VGA_BLUE | | ✅ | VGA_BLUE analog output is not connected, consistent with VGA interface not being fully implemented. | | AY3 | VGA_IRTN | GND | ✅ | VGA_IRTN connected to ground, providing the return path for VGA DAC reference current. | </details> <details> <summary><b>U39</b> - SN74LVC1G14DCKR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf?ts=1753365169590&ref_url=https%25253A%25252F%25252Fwww.ti.com%25252Fproduct%25252FSN74LVC1G14) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/SN74LVC1G14DCKR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin is left unconnected, which is acceptable per datasheet. | | 2 | A | HDMI_HPD | ✅ | Input pin A receives HDMI_HPD signal for Schmitt-trigger noise filtering before inversion. | | 3 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 4 | Y | HDMI_HPD_B | ✅ | Output pin Y provides inverted HDMI_HPD signal as HDMI_HPD_B to CPU DDI0_HPD input. | | 5 | VCC | +V1P8S | ✅ | Power pin correctly supplied by +V1P8S (1.8V) with proper decoupling capacitor. | </details> <details> <summary><b>R40</b> - 110-0004695 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004695) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N548 | ✅ | 357Ω reference resistor connected between VGA_IREF (CPU1 pin AW1) and GND. Sets the VGA DAC reference current for analog video output. | | 2 | 2 | GND | ✅ | 357Ω reference resistor connected between VGA_IREF (CPU1 pin AW1) and GND. Sets the VGA DAC reference current for analog video output. | </details> <details> <summary><b>R38</b> - 110-0002631 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_DAT | ✅ | R38 is connected as a 150Ω pull-down resistor on the VGA DDC data line (CRT_DAT). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors. | | 2 | 2 | GND | ✅ | R38 is connected as a 150Ω pull-down resistor on the VGA DDC data line (CRT_DAT). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors. | </details> <details> <summary><b>R39</b> - 110-0002631 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_CLK | ✅ | R39 is connected as a 150Ω pull-down resistor on the VGA DDC clock line (CRT_CLK). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors. | | 2 | 2 | GND | ✅ | R39 is connected as a 150Ω pull-down resistor on the VGA DDC clock line (CRT_CLK). DDC is an I2C-based protocol that requires pull-up resistors for proper operation, not pull-down resistors. | </details> <details> <summary><b>R217</b> - 402 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI_RCOMP_N | ✅ | This 402Ω resistor is correctly connected between the two DDI0 RCOMP pins of the CPU (AK12 and AK13) through nets DDI_RCOMP_N and DDI_RCOMP_P. However, the net names are swapped relative to the CPU pin designations - DDI_RCOMP_N connects to CPU pin AK12 (DDI0_RCOMP_P) and DDI_RCOMP_P connects to CPU pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅). Since this is a non-polarized resistor, the swap does not affect electrical functionality. The root cause of the naming inconsistency is at the CPU pin connections. | | 2 | 2 | DDI_RCOMP_P | ✅ | This 402Ω resistor is correctly connected between the two DDI0 RCOMP pins of the CPU (AK12 and AK13) through nets DDI_RCOMP_N and DDI_RCOMP_P. However, the net names are swapped relative to the CPU pin designations - DDI_RCOMP_N connects to CPU pin AK12 (DDI0_RCOMP_P) and DDI_RCOMP_P connects to CPU pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅). Since this is a non-polarized resistor, the swap does not affect electrical functionality. The root cause of the naming inconsistency is at the CPU pin connections. | </details> <details> <summary><b>R213</b> - 150 ohm 1% 1/16W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCSI_RCOMP | ✅ | Connected to CPU1 pin P14 (MCSI_RCOMP) to provide compensation resistance for the MCSI interface on Bay Trail-I variant. | | 2 | 2 | GND | ✅ | Connected to ground to complete the MCSI compensation network. | </details> <details> <summary><b>R257</b> - 2.2K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI1_DDCDAT | ✅ | Pull-down resistor on DDI1_DDCDAT signal. This is part of intentionally disabling the DDI1 (Display Port 1) interface. | | 2 | 2 | GND | ✅ | Connected to ground as part of pull-down configuration. | </details> <details> <summary><b>R102</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the pull-down resistor. | | 2 | 2 | GPIO_NC13 | ✅ | Connected to GPIO_NC13, pulling this GPIO signal to ground through 10K resistance. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C24 | ~PROCHOT | VR_HOT_L | ✅ | PROCHOT thermal management signal, correctly connected with current limiting resistor to voltage rail. | | N34 | RESERVED_N34 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | P34 | RESERVED_P34 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | BA12 | SATA_GP0 | SATA_GP0 | ✅ | SATA general purpose signal 0, correctly connected with pull-down resistor. | | BA16 | SATA_RXN_1 | SATA1_RXN | ✅ | SATA port 1 receive negative signal, correctly connected through AC coupling capacitor to mSATA interface. | | BA18 | SD2_CLK | | ✅ | SD2 clock signal, not connected. This is acceptable if SD2 interface is not used. | | BA20 | SD2_D2 | | ✅ | SD2 data bit 2 signal, not connected. This is acceptable if SD2 interface is not used. | | BA24 | ~MMC1_RST | | ✅ | MMC1 reset signal, not connected. This is acceptable if MMC1 interface is not used. | | BA26 | SD3_D3 | SD3_D3 | ✅ | SD3 data bit 3 signal, connected to SD3_D3 for SD card interface. | | BA30 | LPE_I2S2_FRM | LPE_I2S_FRM | ✅ | I2S frame sync signal, correctly connected with pull-up resistor. | | BB3 | RESERVED_BB3 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | BB4 | RESERVED_BB4 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | BB5 | RESERVED_VSS6 | RESERVED_VSS6 | ✅ | Reserved VSS pin, correctly connected to ground through 0 ohm resistor. | | BB7 | RESERVED_VSS7 | RESERVED_VSS7 | ✅ | Reserved VSS pin, correctly connected to ground through 0 ohm resistor. | | BB10 | RESERVED_VSS4 | ICLK_SATA_TERMP | ✅ | SATA clock termination positive pin, correctly connected to ground through 0 ohm resistor. | | BC10 | RESERVED_VSS5 | ICLK_SATA_TERMN | ✅ | SATA clock termination negative pin, correctly connected to ground through 0 ohm resistor. | | BC18 | SD2_CMD | | ✅ | SD2 command signal, not connected. This is acceptable if SD2 interface is not used. | | BC24 | SD3_CD# | SD3_CD# | ✅ | SD3 card detect signal, connected through 0 ohm resistor to SD3_WP. This is an intentional design decision for Bay Trail-I variant. | | BC30 | LPE_I2S2_DATAOUT | LPE_I2S_DATOUT | ✅ | I2S data output signal, connected with series resistor and optional pull-down for hardware strapping. | | BD5 | SD3_WP_BD5 | SD3_WP | ✅ | SD3 write protect signal, connected through 0 ohm resistor to SD3_CD#. This is an intentional design decision for Bay Trail-I variant. | | BD7 | ~PCIE_CLKREQ_1 | CLKREQ1_B | ✅ | PCIe clock request 1 signal, correctly connected with pull-up resistor. | | BD10 | SATA_TXP1 | SATA1_TXP | ✅ | SATA port 1 transmit positive signal, correctly connected through AC coupling capacitor to mSATA interface. | | BD18 | ~SD2_D3_CD | | ✅ | SD2 data bit 3 / card detect signal, not connected. This is acceptable if SD2 interface is not used. | | BD20 | SD2_D1 | | ✅ | SD2 data bit 1 signal, not connected. This is acceptable if SD2 interface is not used. | | BD22 | ~SD3_PWREN | /SD3+PWREN | ✅ | SD3 power enable signal, connected to test point for monitoring. | | BD26 | SD3_D1 | SD3_D1 | ✅ | SD3 data bit 1 signal, connected to SD3_D1 for SD card interface. | | BD28 | LPE_I2S2_DATAIN | LPE_I2S_DATIN | ✅ | I2S data input signal, connected to LPE_I2S_DATIN for audio input. | | BE3 | ~PCIE_CLKREQ_3 | mPCIe_CLKREQ3_B | ✅ | PCIe clock request 3 signal, correctly connected with pull-up resistor for mini PCIe interface. | | BF6 | SATA_TXP_0 | SATA0_TXP | ✅ | SATA port 0 transmit positive signal, correctly connected through AC coupling capacitor to SATA connector. | | BF10 | SATA_TXN_1 | SATA1_TXN | ✅ | SATA port 1 transmit negative signal, correctly connected through AC coupling capacitor to mSATA interface. | | BF20 | HDA_LPE_RCOMP | HDA_RCOMP | ✅ | HD Audio / Low Power Engine compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | BF22 | SD3_1P8EN | SD3_1P8EN | ✅ | SD3 1.8V enable signal, connected to test point for monitoring. | | BF26 | SD3_RCOMP | SD3_RCOMP | ✅ | SD3 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | BF28 | LPE_I2S2_CLK | LPE_I2S_CLK | ✅ | I2S clock signal, connected with pull-up resistor and series resistor for hardware strapping. | | BG3 | ~PCIE_CLKREQ_0 | CLKREQ0_B | ✅ | PCIe clock request 0 signal, correctly connected with pull-up resistor. | | BG5 | ~PCIE_CLKREQ_2 | LAN_CLKREQ2_B | ✅ | PCIe clock request 2 signal, correctly connected with pull-up resistor for LAN interface. | | BG7 | SATA_TXN_0 | SATA0_TXN | ✅ | SATA port 0 transmit negative signal, correctly connected through AC coupling capacitor to SATA connector. | | BG18 | GPIO_S0_SC_15 | | ✅ | GPIO signal, not connected. This is acceptable if this GPIO is not used. | | BG19 | HDA_SDI0 | | ✅ | HD Audio SDI0 signal, not connected. This is acceptable if HD Audio interface is not used. | | BG20 | HDA_SDO | | ✅ | HD Audio SDO signal, not connected. This is acceptable if HD Audio interface is not used. | | BG21 | HDA_SDI1 | | ✅ | HD Audio SDI1 signal, not connected. This is acceptable if HD Audio interface is not used. | | BG22 | ~HDA_RST | | ✅ | HD Audio reset signal, not connected. This is acceptable if HD Audio interface is not used. | | BH18 | GPIO_S0_SC_14 | | ✅ | GPIO signal, not connected. This is acceptable if this GPIO is not used. | | BH20 | HDA_SYNC | | ✅ | HD Audio sync signal, not connected. This is acceptable if HD Audio interface is not used. | | AK7 | RESERVED_AK7 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | AK9 | RESERVED_AK9 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | BJ21 | HDA_CLK | | ✅ | HD Audio clock signal, not connected. This is acceptable if HD Audio interface is not used. | | AP4 | PCIE_TXN_3 | mPCIE_TX_N | ✅ | PCIe port 3 transmit negative signal, connected to mPCIE_TX_N for mini PCIe interface. | | AP6 | PCIE_TXP_3 | mPCIE_TX_P | ✅ | PCIe port 3 transmit positive signal, connected to mPCIE_TX_P for mini PCIe interface. | | AP7 | PCIE_RXN_3 | mPCIE_RX_N | ✅ | PCIe port 3 receive negative signal, connected to mPCIE_RX_N for mini PCIe interface. | | AP9 | PCIE_RXP_3 | mPCIE_RX_P | ✅ | PCIe port 3 receive positive signal, connected to mPCIE_RX_P for mini PCIe interface. | | AP10 | PCIE_RXN_2 | PCIE_RXN2 | ✅ | PCIe port 2 receive negative signal, connected to PCIE_RXN2 for LAN interface. | | AP12 | PCIE_RXP_2 | PCIE_RXP2 | ✅ | PCIe port 2 receive positive signal, connected to PCIE_RXP2 for LAN interface. | | AP13 | PCIE_RCOMP_N_AP13_AP13 | PCIE_RCOMP_N | ✅ | PCIe compensation resistor negative pin, correctly connected to PCIE_RCOMP_N with 402 ohm resistor to PCIE_RCOMP_P. | | AP14 | PCIE_RCOMP_P_AP14_AP14 | PCIE_RCOMP_P | ✅ | PCIe compensation resistor positive pin, correctly connected to PCIE_RCOMP_P with 402 ohm resistor to PCIE_RCOMP_N. | | AT6 | PCIE_TXN_2 | PCIE_TXN2 | ✅ | PCIe port 2 transmit negative signal, connected to PCIE_TXN2 for LAN interface. | | AT7 | PCIE_TXP_2 | PCIE_TXP2 | ✅ | PCIe port 2 transmit positive signal, connected to PCIE_TXP2 for LAN interface. | | AT9 | PCIE_RXN_1 | | ✅ | PCIe port 1 receive negative signal, not connected. This is acceptable if PCIe port 1 is not used. | | AT10 | PCIE_RXP_1 | | ✅ | PCIe port 1 receive positive signal, not connected. This is acceptable if PCIe port 1 is not used. | | AT13 | PCIE_RXN_0 | | ✅ | PCIe port 0 receive negative signal, not connected. This is acceptable if PCIe port 0 is not used. | | AT14 | PCIE_RXP_0 | | ✅ | PCIe port 0 receive positive signal, not connected. This is acceptable if PCIe port 0 is not used. | | AT18 | SATA_RCOMP_N_AT18 | SATA_RCOMP_N | ✅ | SATA compensation resistor negative pin, correctly connected to SATA_RCOMP_N with 402 ohm resistor to SATA_RCOMP_P. | | AT20 | MMC1_D3 | | ✅ | MMC1 data bit 3 signal, not connected. This is acceptable if MMC1 interface is not used. | | AT22 | MMC1_CLK | | ✅ | MMC1 clock signal, not connected. This is acceptable if MMC1 interface is not used. | | AT26 | MMC1_D6 | | ✅ | MMC1 data bit 6 signal, not connected. This is acceptable if MMC1 interface is not used. | | AT28 | SD3_D0 | SD3_D0 | ✅ | SD3 data bit 0 signal, connected to SD3_D0 for SD card interface. | | AU16 | SATA_RXP_0 | SATA0_RXP | ✅ | SATA port 0 receive positive signal, correctly connected through AC coupling capacitor to SATA connector. | | AU18 | SATA_RCOMP_P_AU18 | SATA_RCOMP_P | ✅ | SATA compensation resistor positive pin, correctly connected to SATA_RCOMP_P with 402 ohm resistor to SATA_RCOMP_N. | | AU20 | MMC1_D7 | | ✅ | MMC1 data bit 7 signal, not connected. This is acceptable if MMC1 interface is not used. | | AU22 | MMC1_D1 | | ✅ | MMC1 data bit 1 signal, not connected. This is acceptable if MMC1 interface is not used. | | AU26 | MMC1_D5 | | ✅ | MMC1 data bit 5 signal, not connected. This is acceptable if MMC1 interface is not used. | | AU28 | SD3_D2 | SD3_D2 | ✅ | SD3 data bit 2 signal, connected to SD3_D2 for SD card interface. | | AV4 | PCIE_TXN_1 | | ✅ | PCIe port 1 transmit negative signal, not connected. This is acceptable if PCIe port 1 is not used. | | AV6 | PCIE_TXP_1 | | ✅ | PCIe port 1 transmit positive signal, not connected. This is acceptable if PCIe port 1 is not used. | | AV9 | RESERVED_AV9 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | AV10 | RESERVED_AV10 | | ✅ | Reserved pin, not connected. This is correct as the datasheet indicates this pin is reserved. | | AV16 | SATA_RXN_0 | SATA0_RXN | ✅ | SATA port 0 receive negative signal, correctly connected through AC coupling capacitor to SATA connector. | | AV20 | MMC1_D0 | | ✅ | MMC1 data bit 0 signal, not connected. This is acceptable if MMC1 interface is not used. | | AV22 | MMC1_D2 | | ✅ | MMC1 data bit 2 signal, not connected. This is acceptable if MMC1 interface is not used. | | AV26 | MMC1_CMD | | ✅ | MMC1 command signal, not connected. This is acceptable if MMC1 interface is not used. | | AV28 | SD3_CMD | SD3_CMD | ✅ | SD3 command signal, connected to SD3_CMD for SD card interface. | | AY6 | PCIE_TXN_0 | | ✅ | PCIe port 0 transmit negative signal, not connected. This is acceptable if PCIe port 0 is not used. | | AY7 | PCIE_TXP_0 | | ✅ | PCIe port 0 transmit positive signal, not connected. This is acceptable if PCIe port 0 is not used. | | AY12 | ~SATA_LED | SATA_LED_B | ✅ | SATA LED signal, correctly connected through current limiting resistor to LED indicator with jumper. | | AY14 | SATA_GP1 | SATA_GP1 | ✅ | SATA general purpose signal 1, correctly connected with pull-down resistor. | | AY16 | SATA_RXP_1 | SATA1_RXP | ✅ | SATA port 1 receive positive signal, correctly connected through AC coupling capacitor to mSATA interface. | | AY18 | MMC1_RCOMP | MMC1_RCOMP | ✅ | MMC1 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | AY20 | SD2_D0 | | ✅ | SD2 data bit 0 signal, not connected. This is acceptable if SD2 interface is not used. | | AY24 | MMC1_D4 | | ✅ | MMC1 data bit 4 signal, not connected. This is acceptable if MMC1 interface is not used. | | AY26 | SD3_CLK | SD3_CLK | ✅ | SD3 clock signal, connected to SD3_CLK for SD card interface. | </details> <details> <summary><b>J3</b> - HDR_7POS_SER_GOLD_SATA_R/A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-67490-001.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0003610) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins for SATA differential signal pairs. These pins provide ground reference for the high-speed SATA signals. | | 4 | 4 | GND | ✅ | Ground pins for SATA differential signal pairs. These pins provide ground reference for the high-speed SATA signals. | | 7 | 7 | GND | ✅ | Ground pins for SATA differential signal pairs. These pins provide ground reference for the high-speed SATA signals. | | 2 | 2 | SATA0_TXP_C | ✅ | SATA transmit positive signal (A+). Connected to CPU SATA0_TXP through AC coupling capacitor C10. | | 3 | 3 | SATA0_TXN_C | ✅ | SATA transmit negative signal (A-). Connected to CPU SATA0_TXN through AC coupling capacitor C11. | | 5 | 5 | SATA0_RXN_C | ✅ | SATA receive negative signal (B-). Connected to CPU SATA0_RXN through AC coupling capacitor C12. | | 6 | 6 | SATA0_RXP_C | ✅ | SATA receive positive signal (B+). Connected to CPU SATA0_RXP through AC coupling capacitor C13. | | 8 | MH1 | GND_EARTH | ✅ | Mounting holes connected to chassis ground (GND_EARTH) for EMI shielding. This provides proper separation between signal ground and chassis ground. | | 9 | MH2 | GND_EARTH | ✅ | Mounting holes connected to chassis ground (GND_EARTH) for EMI shielding. This provides proper separation between signal ground and chassis ground. | </details> <details> <summary><b>J6</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Supply voltage (+V1P8S, 1.8V) for SATA activity LED circuit. This pin provides power to the LED when connected. | | 2 | 2 | SATA_LED_R | ✅ | LED cathode connection (SATA_LED_R). Connects through current-limiting resistor R179 to CPU SATA LED output. | </details> <details> <summary><b>C177</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_N | ✅ | Connected to mSATA_RX_N net, providing AC coupling for SATA1 receive negative differential signal from mSATA interface to CPU. | | 2 | 2 | SATA1_RXN | ✅ | Connected to SATA1_RXN net, which connects to CPU1 pin BA16 (SATA_RXN_1), completing the AC coupling path for the negative differential receive signal. | </details> <details> <summary><b>C178</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_P | ✅ | Connected to mSATA_RX_P net, providing AC coupling for SATA1 receive positive differential signal from mSATA interface to CPU. | | 2 | 2 | SATA1_RXP | ✅ | Connected to SATA1_RXP net, which connects to CPU1 pin AY16 (SATA_RXP_1), completing the AC coupling path for the positive differential receive signal. | </details> <details> <summary><b>C179</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_P | ✅ | Connected to mSATA_TX_P net, providing AC coupling for SATA1 transmit positive differential signal from CPU to mSATA interface. | | 2 | 2 | SATA1_TXP | ✅ | Connected to SATA1_TXP net, which connects to CPU1 pin BD10 (SATA_TXP1), completing the AC coupling path for the positive differential transmit signal. | </details> <details> <summary><b>C180</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_N | ✅ | Connected to mSATA_TX_N net, providing AC coupling for SATA1 transmit negative differential signal from CPU to mSATA interface. | | 2 | 2 | SATA1_TXN | ✅ | Connected to SATA1_TXN net, which connects to CPU1 pin BF10 (SATA_TXN_1), completing the AC coupling path for the negative differential transmit signal. | </details> <details> <summary><b>R218</b> - 110-0004476 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PCIE_RCOMP_P | ✅ | R218 is a 402 ohm RCOMP resistor connected between the CPU's PCIe compensation pins PCIE_RCOMP_P (pin AP14) and PCIE_RCOMP_N (pin AP13). This resistor is used for impedance calibration of the PCIe interface. | | 2 | 2 | PCIE_RCOMP_N | ✅ | R218 is a 402 ohm RCOMP resistor connected between the CPU's PCIe compensation pins PCIE_RCOMP_P (pin AP14) and PCIE_RCOMP_N (pin AP13). This resistor is used for impedance calibration of the PCIe interface. | </details> <details> <summary><b>R242</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDA_RCOMP | ✅ | Pin 1 is connected to HDA_RCOMP, which connects to CPU1 pin BF20 to set the output driver impedance for the HDA interface. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, providing the ground reference for the HDA_RCOMP resistor. | </details> <details> <summary><b>R240</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for the MMC1_RCOMP resistor. | | 2 | 2 | MMC1_RCOMP | ✅ | Pin 2 is connected to MMC1_RCOMP, which connects to CPU1 pin AY18 to set the output driver impedance for the MMC1 interface. | </details> <details> <summary><b>R258</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for the SD3_RCOMP resistor. | | 2 | 2 | SD3_RCOMP | ✅ | Pin 2 is connected to SD3_RCOMP, which connects to CPU1 pin BF26 to set the output driver impedance for the SD3 interface. | </details> <details> <summary><b>R189</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pull-down resistor connection to GND for hardware strap GPIO_S0_SC_56. Component is DNI (Do Not Install) for field configuration. | | 2 | 2 | GPIO_S0_SC_56 | ✅ | Connected to GPIO_S0_SC_56 hardware strap signal, shared with R219 pin 2. Component is DNI for field configuration. | </details> <details> <summary><b>R219</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor connection to +V1P8S for hardware strap GPIO_S0_SC_56. Component is DNI (Do Not Install) for field configuration. | | 2 | 2 | GPIO_S0_SC_56 | ✅ | Connected to GPIO_S0_SC_56 hardware strap signal, shared with R189 pin 2. Component is DNI for field configuration. | </details> <details> <summary><b>R234</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP3 | ✅ | 1K pull-down resistor connecting BOM_OP3 to GND, setting hardware ID bit 3 to logic 0. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | GND | ✅ | 1K pull-down resistor connecting BOM_OP3 to GND, setting hardware ID bit 3 to logic 0. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R208</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP2 | ✅ | 1K pull-down resistor connecting BOM_OP2 to GND, setting hardware ID bit 2 to logic 0. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | GND | ✅ | 1K pull-down resistor connecting BOM_OP2 to GND, setting hardware ID bit 2 to logic 0. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R233</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP1 | ✅ | 1K pull-down resistor marked DNI on BOM_OP1, allowing the net to be pulled high by R211. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | GND | ✅ | 1K pull-down resistor marked DNI on BOM_OP1, allowing the net to be pulled high by R211. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R401</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP4 | ✅ | 1K pull-down resistor marked DNI on BOM_OP4, allowing the net to be pulled high by R400. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | GND | ✅ | 1K pull-down resistor marked DNI on BOM_OP4, allowing the net to be pulled high by R400. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R209</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor marked DNI on BOM_OP2, allowing the net to be pulled low by R208. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | BOM_OP2 | ✅ | 10K pull-up resistor marked DNI on BOM_OP2, allowing the net to be pulled low by R208. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R210</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor marked DNI on BOM_OP3, allowing the net to be pulled low by R234. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | BOM_OP3 | ✅ | 10K pull-up resistor marked DNI on BOM_OP3, allowing the net to be pulled low by R234. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R211</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor connecting BOM_OP1 to +V1P8A, setting hardware ID bit 1 to logic 1. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | BOM_OP1 | ✅ | 10K pull-up resistor connecting BOM_OP1 to +V1P8A, setting hardware ID bit 1 to logic 1. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R400</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor connecting BOM_OP4 to +V1P8A, setting hardware ID bit 4 to logic 1. Part of a hardware identification circuit that reads '1001'. | | 2 | 2 | BOM_OP4 | ✅ | 10K pull-up resistor connecting BOM_OP4 to +V1P8A, setting hardware ID bit 4 to logic 1. Part of a hardware identification circuit that reads '1001'. | </details> <details> <summary><b>R191</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ0_B | ✅ | Connected to CLKREQ0_B signal, which goes to CPU1 pin BG3 (PCIE_CLKREQ_0). This is the pull-down side of the pull-up resistor. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ0 signal. | </details> <details> <summary><b>R190</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ1_B | ✅ | Connected to CLKREQ1_B signal, which goes to CPU1 pin BD7 (PCIE_CLKREQ_1). This is the pull-down side of the pull-up resistor. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ1 signal. | </details> <details> <summary><b>R71</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_CLKREQ2_B | ✅ | Connected to LAN_CLKREQ2_B signal, which goes to CPU1 pin BG5 (PCIE_CLKREQ_2). This is the pull-down side of the pull-up resistor for the LAN interface. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ2 signal. | </details> <details> <summary><b>R2</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mPCIe_CLKREQ3_B | ✅ | Connected to mPCIe_CLKREQ3_B signal, which goes to CPU1 pin BE3 (PCIE_CLKREQ_3). This is the pull-down side of the pull-up resistor for the mPCIe card slot. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for the CLKREQ3 signal. | </details> <details> <summary><b>R260</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_DATOUT | ✅ | Pin 1 connects to LPE_I2S_DATOUT net. This resistor is marked DNI (Do Not Install) and is electrically absent from the circuit. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This resistor is marked DNI (Do Not Install) and is electrically absent from the circuit. | </details> <details> <summary><b>R268</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_FRM | ✅ | Pin 1 connects to LPE_I2S_FRM net, which is also known as GPIO_S0_SC63 and serves as a hardware strap for BIOS Boot Selection. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S supply, providing the pull-up voltage for the hardware strap. | </details> <details> <summary><b>R259</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_10_UNLOCK | ✅ | Pin 1 connects to GPIO_S5_10_UNLOCK net. This pin is one end of a series resistor used to control the hardware strap value of the LPE_I2S_DATOUT signal. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | Pin 2 connects to LPE_I2S_DATOUT net, which is also known as GPIO_S0_SC65 and serves as a hardware strap for Security Flash Descriptors configuration. | </details> <details> <summary><b>R72</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS6 | ✅ | Pin 1 connects to RESERVED_VSS6, which connects to CPU1 pin BB5 (RESERVED_VSS6). This is part of grounding a reserved CPU pin. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This completes the connection to ground a reserved CPU pin through a 0-ohm resistor. | </details> <details> <summary><b>R73</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This is one side of a 0-ohm resistor used to ground a reserved CPU pin. | | 2 | 2 | ICLK_SATA_TERMP | ✅ | Pin 2 connects to ICLK_SATA_TERMP, which connects to CPU1 pin BB10 (RESERVED_VSS4). This grounds a reserved CPU pin. | </details> <details> <summary><b>R74</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This is one side of a 0-ohm resistor used to ground a reserved CPU pin. | | 2 | 2 | ICLK_SATA_TERMN | ✅ | Pin 2 connects to ICLK_SATA_TERMN, which connects to CPU1 pin BC10 (RESERVED_VSS5). This grounds a reserved CPU pin. | </details> <details> <summary><b>R192</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS7 | ✅ | Pin 1 connects to RESERVED_VSS7, which connects to CPU1 pin BB7 (RESERVED_VSS7). This is part of grounding a reserved CPU pin. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This completes the connection to ground a reserved CPU pin through a 0-ohm resistor. | </details> <details> <summary><b>R354</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SD3_WP | ✅ | 0 ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect) signals. This unusual configuration may be intentional due to Bay Trail-I processor-specific requirements. | | 2 | 2 | SD3_CD# | ✅ | 0 ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect) signals. This unusual configuration may be intentional due to Bay Trail-I processor-specific requirements. | </details> <details> <summary><b>R255</b> - 110-0004474 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004474) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR_HOT_L | ✅ | Pin 1 connects to VR_HOT_L net, which is the PROCHOT (processor hot) signal from CPU1 pin C24. This is an active-low thermal management signal. | | 2 | 2 | +V1P0S | ✅ | Pin 2 connects to +V1P0S (1.0V supply), providing a pull-up for the PROCHOT signal. The 73.2 ohm value is unusually low for a typical pull-up but appears intentional. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A9 | ILB_RTC_X2 | BRTCX2 | ✅ | ILB_RTC_X2 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor. | | A13 | GPIO_S5_9 | SOC_USB_HOST_EN1 | ✅ | GPIO_S5_9 is routed off-page as SOC_USB_HOST_EN1, likely used for USB host port enable control. | | A17 | GPIO_S5_3 | mPCIE_WAKEB | ✅ | GPIO_S5_3 is correctly configured as mPCIE wake input with optional pull-up resistor. | | A21 | PCU_SPI_MOSI | SOC_SPI_MOSI | ✅ | PCU_SPI_MOSI is correctly connected through series resistor to the SPI flash interface. | | A25 | SVID_DATA | SVID_DATA | ✅ | SVID_DATA is correctly connected through series resistor for voltage regulator communication. | | B7 | PMC_CORE_PWROK | PMC_CORE_PWROK | ✅ | PMC_CORE_PWROK is correctly connected to system power good signal through series resistor. | | B8 | ILB_RTC_EXTPAD | BVCCRTC_EXTPAD | ✅ | ILB_RTC_EXTPAD is correctly connected to decoupling capacitor for RTC battery backup. | | B10 | ~PMC_RSMRST | PMC_RSMRST | ✅ | PMC_RSMRST is correctly connected with pull-up, pull-down, and RC filtering for resume reset control. | | B14 | GPIO_S5_6 | BOM_OP2 | ✅ | GPIO_S5_6 routes off-page as BOM_OP2, likely used for board option configuration. | | B16 | GPIO_S5_1 | SOC_GPIO_S5_1 | ✅ | GPIO_S5_1 routes off-page as SOC_GPIO_S5_1 for general purpose I/O. | | B18 | GPIO_S5_0 | SOC_GPIO_S5_0 | ✅ | GPIO_S5_0 routes off-page as SOC_GPIO_S5_0 for general purpose I/O. | | B22 | PCU_SPI_MISO | SOC_SPI_MISO | ✅ | PCU_SPI_MISO is correctly connected through series resistor to the SPI flash interface. | | B24 | ~SVID_ALERT | SVID_ALERT | ✅ | SVID_ALERT is correctly connected through series resistor with pull-up for voltage regulator alert signaling. | | C9 | ILB_RTC_X1 | BRTCX1 | ✅ | ILB_RTC_X1 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor. | | C11 | ~ILB_RTC_TEST | ILB_RTC_TESTB | ✅ | ILB_RTC_TEST routes off-page for RTC test mode control. | | C12 | ~ILB_RTC_RST | RTCRST_L | ✅ | ILB_RTC_RST is correctly connected with pull-up resistor and decoupling capacitor for RTC reset control. | | C13 | GPIO_S5_8 | SOC_USB_HOST_EN0 | ✅ | GPIO_S5_8 routes off-page as SOC_USB_HOST_EN0, likely used for USB host port enable control. | | C15 | GPIO_S5_7 | BOM_OP3 | ✅ | GPIO_S5_7 routes off-page as BOM_OP3, likely used for board option configuration. | | C16 | GPIO_S5_5 | BOM_OP1 | ✅ | GPIO_S5_5 routes off-page as BOM_OP1, likely used for board option configuration. | | C17 | GPIO_S5_4 | BOM_OP4 | ✅ | GPIO_S5_4 routes off-page as BOM_OP4, likely used for board option configuration. | | C18 | GPIO_S5_2 | SOC_GPIO_S5_2 | ✅ | GPIO_S5_2 routes off-page as SOC_GPIO_S5_2 for general purpose I/O. | | C19 | GPIO_S5_10 | GPIO_S5_10_UNLOCK | ✅ | GPIO_S5_10 routes off-page as GPIO_S5_10_UNLOCK for general purpose I/O. | | C21 | ~PCU_SPI_CS_11 | SOC_SPI_CS1B | ✅ | PCU_SPI_CS_11 is connected through DNI series resistor, indicating SPI chip select 1 is not used. | | C22 | PCU_SPI_CLK | SOC_SPI_CLK | ✅ | PCU_SPI_CLK is correctly connected through series resistor with optional capacitor for SPI clock signal. | | C23 | ~PCU_SPI_CS_00 | SOC_SPI_CS0B | ✅ | PCU_SPI_CS_00 is correctly connected through series resistor to the SPI flash chip select. | | C25 | SVID_CLK | SVID_CLK-R | ✅ | SVID_CLK routes off-page for Serial VID clock signal to voltage regulator. | | D14 | TAP_TCK | XDP_H_TCK | ✅ | TAP_TCK is correctly connected with pull-down resistor for JTAG test clock. | | D18 | ~TAP_PRDY | XDP_H_PRDYB | ✅ | TAP_PRDY routes off-page for JTAG probe ready signal. | | D20 | PMC_ACPRESENT | PMC_ACPRESENT | ✅ | PMC_ACPRESENT is correctly connected with pull-up resistor for AC power present indication. | | D22 | ~PMC_SLP_S3 | PMC_SLP_S3_L | ✅ | PMC_SLP_S3 is correctly connected to level shifter for sleep state S3 indication. | | D26 | PMC_SUSPWRDNACK | SUSPWRDNACK | ✅ | PMC_SUSPWRDNACK is correctly connected with pull-up resistor and test point for suspend power down acknowledge. | | F12 | TAP_TDI | XDP_H_TDI | ✅ | TAP_TDI is correctly connected with pull-up resistor for JTAG test data input. | | F14 | TAP_TMS | XDP_H_TMS | ✅ | TAP_TMS is correctly connected with pull-up resistor for JTAG test mode select. | | F16 | ~TAP_PREQ | XDP_H_PREQB | ✅ | TAP_PREQ routes off-page for JTAG probe request signal. | | F18 | ~PMC_SLP_S0IX | PMC_SLP_S0IX | ✅ | PMC_SLP_S0IX is connected to test point only for sleep state S0IX indication. | | F20 | ~PMC_PLTRST | PMC_PLTRST_R_V1P8 | ✅ | PMC_PLTRST is correctly connected to level shifter for platform reset signal translation. | | F22 | ~PMC_SLP_S4 | PMC_SLP_S4_L | ✅ | PMC_SLP_S4 is correctly connected to level shifter for sleep state S4 indication. | | F26 | ~PMC_WAKE_PCIE_0 | PMC_PCIE_WAKE_R | ✅ | PMC_WAKE_PCIE_0 is correctly connected with diode OR logic and pull-up for PCIe wake signaling. | | G12 | ~TAP_TRST | XDP_H_TRSTB | ✅ | TAP_TRST is correctly connected with pull-down resistor for JTAG test reset. | | G16 | TAP_TDO | XDP_H_TDO | ✅ | TAP_TDO routes off-page for JTAG test data output. | | G18 | ~PMC_SUS_STAT | LPCPD_L | ✅ | PMC_SUS_STAT is connected to test point only for suspend status monitoring. | | G24 | PMC_SUSCLK0_G24 | PMC_SUSCLK0 | ✅ | PMC_SUSCLK0 is correctly connected to level shifter with optional pull-up for suspend clock output. | | J18 | GPIO_S5_25 | XDP_H_OBSDATA_A2 | ✅ | GPIO_S5_25 routes off-page as XDP_H_OBSDATA_A2 for debug observation data. | | J20 | GPIO_S5_14 | GPIO_S514_J20 | ✅ | GPIO_S5_14 is correctly connected with pull-up resistor for general purpose I/O. | | J24 | GPIO_S5_17 | GPIO_S5_17 | ✅ | GPIO_S5_17 is correctly connected to jumper header with pull-up for user-configurable option. | | J26 | ~PMC_PWRBTN | PMC_PWRBTN | ✅ | PMC_PWRBTN is connected to power button logic with diode OR and optional pull-up. | | K18 | GPIO_S5_27 | EXP_GPIO1 | ✅ | GPIO_S5_27 routes off-page as EXP_GPIO1 for expansion bus GPIO. | | K20 | GPIO_S5_28 | EXP_GPIO2 | ✅ | GPIO_S5_28 routes off-page as EXP_GPIO2 for expansion bus GPIO. | | K24 | GPIO_S5_22 | GPIO_D2_LED_CTRL | ✅ | GPIO_S5_22 routes off-page as GPIO_D2_LED_CTRL, likely used for LED control. | | K26 | ~PMC_BATLOW | PMC_BATLOW | ✅ | PMC_BATLOW is correctly connected with pull-up resistor for battery low indication. | | M18 | GPIO_S5_26 | XDP_H_OBSDATA_A3 | ✅ | GPIO_S5_26 routes off-page as XDP_H_OBSDATA_A3 for debug observation data. | | M20 | GPIO_S5_24 | XDP_H_OBSDATA_A1 | ✅ | GPIO_S5_24 routes off-page as XDP_H_OBSDATA_A1 for debug observation data. | | M22 | GPIO_S5_29 | EXP_GPIO3 | ✅ | GPIO_S5_29 routes off-page as EXP_GPIO3 for expansion bus GPIO. | | M24 | GPIO_S5_30 | EXP_GPIO4 | ✅ | GPIO_S5_30 routes off-page as EXP_GPIO4 for expansion bus GPIO. | | N24 | GPIO_S5_23 | XDP_H_OBSDATA_A0 | ✅ | GPIO_S5_23 routes off-page as XDP_H_OBSDATA_A0 for debug observation data. | | N26 | GPIO_RCOMP | GPIO_RCOMP | ✅ | GPIO_RCOMP is correctly connected to 49.9 ohm compensation resistor to ground. | | BA28 | SIO_SPI_MISO | SOC_SIO_SPI_MISO | ✅ | SIO_SPI_MISO routes off-page for Serial I/O SPI master in slave out. | | BA34 | ~SIO_UART1_RTS | SIO_UART1_RTSB | ✅ | SIO_UART1_RTS routes off-page for UART1 request to send flow control. | | AD9 | RESERVED_AD9 | | ✅ | RESERVED_AD9 is correctly left unconnected as specified. | | AD10 | RESERVED_AD10 | | ✅ | RESERVED_AD10 is correctly left unconnected as specified. | | AD12 | RESERVED_AD12 | | ✅ | RESERVED_AD12 is correctly left unconnected as specified. | | AD13 | ICLK_RCOMP | ICLK_RCOMP | ✅ | ICLK_RCOMP is correctly connected to 47.5 ohm compensation resistor to ground. | | AD14 | ICLK_ICOMP | ICLK_ICOMP | ✅ | ICLK_ICOMP is correctly connected to 4.02K ohm compensation resistor to ground. | | BD32 | ~SIO_UART2_RTS | | ✅ | SIO_UART2_RTS is not connected, indicating UART2 flow control is not used. | | BD34 | SIO_UART2_TXD | SIO_UART2_TXD | ✅ | SIO_UART2_TXD routes off-page for UART2 transmit data. | | AF4 | PCIE_CLKP_00 | | ✅ | PCIE_CLKP_00 is not connected, indicating PCIe port 0 is not used. | | AF6 | PCIE_CLKN_00 | | ✅ | PCIE_CLKN_00 is not connected, indicating PCIe port 0 is not used. | | AF7 | PCIE_CLKP_11 | | ✅ | PCIE_CLKP_11 is not connected, indicating PCIe port 1 is not used. | | AF9 | PCIE_CLKN_11 | | ✅ | PCIE_CLKN_11 is not connected, indicating PCIe port 1 is not used. | | BF32 | ~SIO_UART2_CTS | | ✅ | SIO_UART2_CTS is not connected, indicating UART2 flow control is not used. | | BF34 | SIO_UART2_RXD | SIO_UART2_RXD | ✅ | SIO_UART2_RXD routes off-page for UART2 receive data. | | BG9 | ~PMC_RSTBTN | PMC_RSTBTN | ✅ | PMC_RSTBTN routes off-page for reset button input. | | AH10 | ICLK_OSCOUT | XTAL25_OUT | ✅ | ICLK_OSCOUT (AH10) and ICLK_OSCIN (AH12) are correctly connected to a 25MHz crystal with appropriate load capacitors and feedback resistor. | | AH12 | ICLK_OSCIN | XTAL25_IN | ✅ | ICLK_OSCOUT (AH10) and ICLK_OSCIN (AH12) are correctly connected to a 25MHz crystal with appropriate load capacitors and feedback resistor. | | BH4 | PMC_PLT_CLK_22 | | ✅ | PMC_PLT_CLK_22 is not connected, indicating platform clock 2 is not used. | | BH5 | PMC_PLT_CLK_11 | | ✅ | PMC_PLT_CLK_11 is not connected, indicating platform clock 1 is not used. | | BH6 | PMC_PLT_CLK_44 | | ✅ | PMC_PLT_CLK_44 is not connected, indicating platform clock 4 is not used. | | BH7 | PMC_PLT_CLK_00 | | ✅ | PMC_PLT_CLK_00 is not connected, indicating platform clock 0 is not used. | | BH8 | PMC_PLT_CLK_33 | I2S_MCLK | ✅ | PMC_PLT_CLK_33 routes off-page as I2S_MCLK to provide master clock for I2S audio interface. | | AK4 | PCIE_CLKN_22 | PCIE_CLK-N2 | ✅ | PCIE_CLKN_22 routes off-page to provide PCIe reference clock for port 2. | | AK6 | PCIE_CLKP_22 | PCIE_CLK-P2 | ✅ | PCIE_CLKP_22 routes off-page to provide PCIe reference clock for port 2. | | BJ9 | PMC_PLT_CLK_55 | | ✅ | PMC_PLT_CLK_55 is not connected, indicating platform clock 5 is not used. | | AM4 | PCIE_CLKN_33 | mPCIE_REFCLK_N | ✅ | PCIE_CLKN_33 routes off-page to provide PCIe reference clock for mPCIE slot. | | AM6 | PCIE_CLKP_33 | mPCIE_REFCLK_P | ✅ | PCIE_CLKP_33 routes off-page to provide PCIe reference clock for mPCIE slot. | | AM9 | RESERVED_AM9 | | ✅ | RESERVED_AM9 is correctly left unconnected as specified. | | AM10 | RESERVED_AM10 | | ✅ | RESERVED_AM10 is correctly left unconnected as specified. | | AT32 | SIO_PWM_11 | SOC_PWM1 | ✅ | SIO_PWM_11 routes off-page, likely used for PWM control function. | | AT34 | RESERVED | | ✅ | RESERVED pin is correctly left unconnected as specified. | | AU32 | SIO_PWM_00 | SOC_PWM0 | ✅ | SIO_PWM_00 routes off-page, likely used for PWM control function. | | AU34 | SIO_UART1_RXD | SIO_UART1_RXD | ✅ | SIO_UART1_RXD routes off-page for UART1 receive data. | | AV32 | ~SIO_SPI_CS | SOC_SIO_SPI_CS1 | ✅ | SIO_SPI_CS routes off-page for Serial I/O SPI chip select. | | AV34 | SIO_UART1_TXD | SIO_UART1_TXD | ✅ | SIO_UART1_TXD routes off-page for UART1 transmit data. | | AY28 | SIO_SPI_MOSI | SOC_SIO_SPI_MOSI | ✅ | SIO_SPI_MOSI routes off-page for Serial I/O SPI master out slave in. | | AY30 | SIO_SPI_CLK | SOC_SIO_SPI_CLK | ✅ | SIO_SPI_CLK routes off-page for Serial I/O SPI clock. | | AY34 | ~SIO_UART1_CTS | SIO_UART1_CTSB | ✅ | SIO_UART1_CTS routes off-page for UART1 clear to send flow control. | </details> <details> <summary><b>U19</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA supply pin correctly connected to +V1P8A (1.8V) rail, providing power for the A-side of the level shifter. | | 2 | A1 | PMC_PLTRST_R_V1P8 | ✅ | A1 pin correctly connected to PMC_PLTRST_R_V1P8 from CPU1 pin F20, translating the platform reset signal from 1.8V to 3.3V. | | 3 | A2 | PMC_SUSCLK0 | ✅ | A2 pin correctly connected to PMC_SUSCLK0 from CPU1 pin G24, translating the suspend clock signal from 1.8V to 3.3V. | | 4 | A3 | PMC_SLP_S4_L | ✅ | A3 pin correctly connected to PMC_SLP_S4_L from CPU1 pin F22, translating the S4 sleep state signal from 1.8V to 3.3V. | | 5 | A4 | PMC_SLP_S3_L | ✅ | A4 pin correctly connected to PMC_SLP_S3_L from CPU1 pin D22, translating the S3 sleep state signal from 1.8V to 3.3V. | | 6 | GND | GND | ✅ | GND pin correctly connected to the ground net. | | 7 | B4 | SLP_S3_L | ✅ | B4 pin correctly connected to SLP_S3_L, the 3.3V side of the S3 sleep state signal, pairing with A4. | | 8 | B3 | SLP_S4_L | ✅ | B3 pin correctly connected to SLP_S4_L, the 3.3V side of the S4 sleep state signal, pairing with A3. | | 9 | B2 | SUSCLK_3P3 | ✅ | B2 pin correctly connected to SUSCLK_3P3, the 3.3V side of the suspend clock signal, pairing with A2. | | 10 | B1 | PMC_PLTRST_L | ✅ | B1 pin correctly connected to PMC_PLTRST_L, the 3.3V side of the platform reset signal, pairing with A1. | | 11 | VCCB | PWR_BUF1 | ✅ | VCCB supply pin correctly connected to PWR_BUF1, which is connected through R26 (0-ohm) to +3VSB, providing 3.3V standby power for the B-side. | | 12 | OE | PMC_OE | ✅ | OE pin correctly connected to PMC_OE with a 2.2K pull-up resistor (R57) to +V1P8A, enabling the level shifter. | </details> <details> <summary><b>Y1</b> - 145-0004789 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/145-0004789) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BRTCX2 | ✅ | Crystal pin connected to CPU RTC oscillator pin X2 with proper load capacitor and feedback resistor. | | 2 | 2 | BRTCX1 | ✅ | Crystal pin connected to CPU RTC oscillator pin X1 with proper load capacitor and feedback resistor. | </details> <details> <summary><b>D5</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | +PS_3VSB | ✅ | Anode 1 connected to 3.3V standby rail for primary RTC power through OR-ing diode. | | A2 | A2 | +VBAT_R | ✅ | Anode 2 connected to battery voltage for backup RTC power through OR-ing diode. | | C | C | +RTCVCC | ✅ | Common cathode output providing OR-ed power to RTC circuit from either main power or battery. | </details> <details> <summary><b>BH1</b> - 353-0003073 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/353-0003073) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +VBAT | ✅ | Positive battery terminal connected to +VBAT net through current limiting resistor to OR-ing diode for RTC backup power. | | 2 | P2 | +VBAT | ✅ | Redundant positive battery terminal connected to +VBAT net, same as pin 1. | | 3 | N | GND | ✅ | Negative battery terminal correctly connected to ground. | </details> <details> <summary><b>Y2</b> - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XTAL25_IN | ✅ | Crystal input pin correctly connected to CPU oscillator input (ICLK_OSCIN) through net XTAL25_IN with proper load capacitor C175 (27pF) to ground and feedback resistor R188 (1M) to pin 3. | | 2 | 2 | GND | ✅ | Ground pin correctly connected to GND net, standard for 4-pin crystal packages. | | 3 | 3 | XTAL25_OUT | ✅ | Crystal output pin correctly connected to CPU oscillator output (ICLK_OSCOUT) through net XTAL25_OUT with proper load capacitor C176 (27pF) to ground. | | 4 | 4 | GND | ✅ | Ground pin correctly connected to GND net, standard for 4-pin crystal packages. | </details> <details> <summary><b>D3</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE | ✅ | Both anode pins are connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27 (2.2K). This parallels the two diodes in the package. | | 2 | 2 | PMC_PCIE_WAKE | ✅ | Both anode pins are connected together to PMC_PCIE_WAKE net, which is pulled up to +3VSB through R27 (2.2K). This parallels the two diodes in the package. | | 3 | 3 | PMC_PCIE_WAKE_R | ✅ | Cathode pin connected to PMC_PCIE_WAKE_R net, which connects to CPU1 pin F26 and is pulled up to +V1P8A through R253 (1K). This creates a unidirectional level shifter allowing the CPU to pull the wake signal low while protecting it from the higher +3VSB voltage. | </details> <details> <summary><b>D10</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | 3VSB_OK | ✅ | Anode 1 connected to 3VSB_OK net, which is pulled up to +3VSB through R162 (1K). This allows the power supply good signal to control PS_OUT_L. | | A2 | A2 | PMC_PWRBTN | ✅ | Anode 2 connected to PMC_PWRBTN net, which connects to CPU1 pin J26 (active-low power button signal). This allows the power button to control PS_OUT_L. | | C | C | PS_OUT_L | ✅ | Common cathode connected to PS_OUT_L net. This output is pulled low when either 3VSB_OK or PMC_PWRBTN goes low, implementing an OR gate for power control. | </details> <details> <summary><b>J7</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_17 | ✅ | Connected to GPIO_S5_17 from the CPU, serving as the signal pin of the jumper header. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the jumper. | </details> <details> <summary><b>R183</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S supply rail, providing the pull-up voltage source. | | 2 | 2 | GPIO_S5_17 | ✅ | Connected to GPIO_S5_17, completing the pull-up resistor circuit. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A7 | USB_HSIC_RCOMP | USB_HSIC0_RCOMP | ✅ | USB_HSIC_RCOMP is correctly connected to a 45.3 ohm resistor to ground for USB HSIC impedance calibration. | | B4 | USB_HSIC0_DATA | | ✅ | USB_HSIC0_DATA and USB_HSIC0_STROBE are not connected, indicating USB HSIC port 0 is not used in this design. | | B5 | USB_HSIC0_STROBE | | ✅ | USB_HSIC0_DATA and USB_HSIC0_STROBE are not connected, indicating USB HSIC port 0 is not used in this design. | | B12 | GPIO_S5_43 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | G2 | GPIO_S5_31 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | H3 | GPIO_S5_42 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | J3 | GPIO_S5_40 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | K2 | GPIO_S5_34 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | K3 | GPIO_S5_35 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | L1 | GPIO_S5_33 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | L3 | GPIO_S5_39 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | M2 | GPIO_S5_36 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | M3 | GPIO_S5_32 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | N3 | GPIO_S5_37 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | P2 | GPIO_S5_38 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | P3 | GPIO_S5_41 | | ✅ | GPIO_S5 pins are not connected, indicating these S5 power domain GPIOs are not used in this design. | | B20 | ~USB_OC_11 | SOC_USB_HOST_OC1 | ✅ | USB_OC[1]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection. | | C7 | USB_RCOMPI | USB_RCOMP | ✅ | USB_RCOMPI and USB_RCOMPO are correctly connected together to a 45.3 ohm resistor to ground for USB 2.0 impedance calibration. | | D6 | USB_RCOMPO | USB_RCOMP | ✅ | USB_RCOMPI and USB_RCOMPO are correctly connected together to a 45.3 ohm resistor to ground for USB 2.0 impedance calibration. | | C20 | ~USB_OC_00 | SOC_USB_HOST_OC0 | ✅ | USB_OC[0]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection. | | D2 | USB_HSIC1_STROBE | | ✅ | USB_HSIC1_STROBE and USB_HSIC1_DATA are not connected, indicating USB HSIC port 1 is not used in this design. | | E2 | USB_HSIC1_DATA | | ✅ | USB_HSIC1_STROBE and USB_HSIC1_DATA are not connected, indicating USB HSIC port 1 is not used in this design. | | D4 | USB3_RXP0 | USB3_RXP0 | ✅ | USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation. | | E3 | USB3_RXN0 | USB3_RXN0 | ✅ | USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation. | | K6 | USB3_TXP0 | USB3_TXP0 | ✅ | USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation. | | K7 | USB3_TXN0 | USB3_TXN0 | ✅ | USB 3.0 differential pairs (USB3_RXP0, USB3_RXN0, USB3_TXP0, USB3_TXN0) are connected to their respective nets for USB 3.0 port 0 operation. | | D10 | ICLK_USB_TERM_1 | ICLK_USB_TERM_0 | ✅ | ICLK_USB_TERM_1 and ICLK_USB_TERMN are correctly connected to 1K ohm resistors to ground for USB clock termination. | | F10 | ICLK_USB_TERMN | ICLK_USB_TERM_1 | ✅ | ICLK_USB_TERM_1 and ICLK_USB_TERMN are correctly connected to 1K ohm resistors to ground for USB clock termination. | | G14 | USB_DN1 | USB_DN1 | ✅ | USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets. | | J14 | USB_DP1 | USB_DP1 | ✅ | USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets. | | K16 | USB_DN0 | USB_DN0 | ✅ | USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets. | | M16 | USB_DP0 | USB_DP0 | ✅ | USB 2.0 differential pairs for port 0 and port 1 (USB_DN0, USB_DP0, USB_DN1, USB_DP1) are connected to their respective nets. | | H4 | RESERVED_H4 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | H5 | RESERVED_H5 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | H7 | RESERVED_H7 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | H8 | RESERVED_H8 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | M10 | RESERVED_M10 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | M4 | RESERVED_M4 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | M6 | RESERVED_M6 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | M7 | RESERVED_M7 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | M9 | RESERVED_M9 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | P10 | RESERVED_P10 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | P12 | RESERVED_P12 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | P6 | RESERVED_P6 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | P7 | RESERVED_P7 | | ✅ | Reserved pins are correctly left unconnected as per datasheet requirements. | | H10 | USB_DN3 | | ✅ | USB_DN3 and USB_DP3 are not connected, indicating USB port 3 is not used in this design. | | K10 | USB_DP3 | | ✅ | USB_DN3 and USB_DP3 are not connected, indicating USB port 3 is not used in this design. | | J12 | USB_DN2 | USB_HOST_DN | ✅ | USB 2.0 differential pair for port 2 (USB_DN2, USB_DP2) is connected to USB_HOST_DN and USB_HOST_DP nets. | | K12 | USB_DP2 | USB_HOST_DP | ✅ | USB 2.0 differential pair for port 2 (USB_DN2, USB_DP2) is connected to USB_HOST_DN and USB_HOST_DP nets. | | M12 | USB3_REXT0 | USB3_REXT0 | ✅ | USB3_REXT0 is correctly connected to a 1.24K ohm resistor to ground for USB 3.0 impedance calibration. | | M13 | USB_PLL_MON | USB_PLL_MON | ✅ | USB_PLL_MON is correctly connected to a test point for USB PLL monitoring and debug. | | BC12 | GPIO_S0_SC_56 | GPIO_S0_SC_56 | ✅ | GPIO_S0_SC_56 is connected to net GPIO_S0_SC_56 for GPIO functionality. | | BC14 | GPIO_S0_SC_58 | HDMI_CEC | ✅ | GPIO_S0_SC_58 is connected to net HDMI_CEC for HDMI Consumer Electronics Control functionality. | | BC16 | GPIO_S0_SC_61 | PCU_UART3_RXD | ✅ | GPIO_S0_SC_61 is correctly configured as UART3 receive and connected to level shifter U6 for debug serial input. | | BD12 | GPIO_S0_SC_55 | GPIO_S0_SC_55 | ✅ | GPIO_S0_SC_55 is correctly connected to a test point for GPIO monitoring. | | BD14 | GPIO_S0_SC_57 | PCU_UART3_TXD | ✅ | GPIO_S0_SC_57 is correctly configured as UART3 transmit and connected to level shifter U6 for debug serial output. | | BD16 | GPIO_S0_SC_60 | | ✅ | GPIO_S0_SC_60 is not connected, indicating this GPIO is not used in this design. | | BF14 | GPIO_S0_SC_59 | | ✅ | GPIO_S0_SC_59 is not connected, indicating this GPIO is not used in this design. | | BF18 | LPC_RCOMP | LPC_RCOMP | ✅ | LPC_RCOMP is correctly connected to a 49.9 ohm resistor to ground for LPC bus impedance calibration. | | BF27 | SIO_I2C4_DATA | | ✅ | SIO_I2C4_DATA and SIO_I2C4_CLK are not connected, indicating I2C4 interface is not used in this design. | | BG27 | SIO_I2C4_CLK | | ✅ | SIO_I2C4_DATA and SIO_I2C4_CLK are not connected, indicating I2C4 interface is not used in this design. | | BG11 | ~PCU_SMB_ALERT | PCU_SMB_ALERT | ✅ | PCU_SMB_ALERT# is correctly connected with a 10K pull-up to +V1P8S and routed through a 0 ohm resistor to LAN-SMB-ALERT#. | | BG12 | PCU_SMB_DATA | PCU_SMB_DATA | ✅ | PCU_SMB_DATA is correctly connected with a 2.2K pull-up to +V1P8S and routed to level shifter U5 for SMBus data signal. | | BG13 | ILB_LPC_SERIRQ | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BG14 | ILB_LPC_AD_33 | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BG15 | ILB_LPC_CLK_00 | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BG16 | ~ILB_LPC_CLKRUN | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BG17 | ~ILB_LPC_FRAME | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BH14 | ILB_LPC_CLK_11 | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BH16 | ILB_LPC_AD_00 | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BJ13 | ILB_LPC_AD_22 | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BJ17 | ILB_LPC_AD_11 | | ✅ | LPC interface pins are not connected, indicating the LPC bus is not used in this design. | | BG23 | SIO_I2C0_CLK | | ✅ | SIO_I2C0_CLK and SIO_I2C0_DATA are not connected, indicating I2C0 interface is not used in this design. | | BH22 | SIO_I2C0_DATA | | ✅ | SIO_I2C0_CLK and SIO_I2C0_DATA are not connected, indicating I2C0 interface is not used in this design. | | BG24 | SIO_I2C1_DATA | SIO_I2C1_SDA | ✅ | SIO_I2C1_DATA and SIO_I2C1_CLK are correctly connected to test points TP6 and TP5 for I2C monitoring. | | BH24 | SIO_I2C1_CLK | SIO_I2C1_SCL | ✅ | SIO_I2C1_DATA and SIO_I2C1_CLK are correctly connected to test points TP6 and TP5 for I2C monitoring. | | BG25 | SIO_I2C2_DATA | | ✅ | SIO_I2C2_DATA and SIO_I2C2_CLK are not connected, indicating I2C2 interface is not used in this design. | | BJ25 | SIO_I2C2_CLK | | ✅ | SIO_I2C2_DATA and SIO_I2C2_CLK are not connected, indicating I2C2 interface is not used in this design. | | BG26 | SIO_I2C3_DATA | | ✅ | SIO_I2C3_DATA and SIO_I2C3_CLK are not connected, indicating I2C3 interface is not used in this design. | | BH26 | SIO_I2C3_CLK | | ✅ | SIO_I2C3_DATA and SIO_I2C3_CLK are not connected, indicating I2C3 interface is not used in this design. | | BG28 | SIO_I2C5_CLK | SI0_I2C5_SCL | ✅ | SIO_I2C5_CLK and SIO_I2C5_DATA are correctly connected with 22 ohm series resistors to I2C5_SCL and I2C5_SDA nets. | | BH28 | SIO_I2C5_DATA | SI0_I2C5_SDA | ✅ | SIO_I2C5_CLK and SIO_I2C5_DATA are correctly connected with 22 ohm series resistors to I2C5_SCL and I2C5_SDA nets. | | BG29 | SIO_I2C6_CLK | SI0_I2C6_SCL | ✅ | SIO_I2C6_CLK and SIO_I2C6_DATA are correctly connected with 22 ohm series resistors to I2C6_SCL and I2C6_SDA nets. | | BJ29 | SIO_I2C6_DATA | SI0_I2C6_SDA | ✅ | SIO_I2C6_CLK and SIO_I2C6_DATA are correctly connected with 22 ohm series resistors to I2C6_SCL and I2C6_SDA nets. | | BG30 | GPIO_S0_SC_093 | TP10_NET | ✅ | GPIO_S0_SC_093 and GPIO_S0_SC_092 are intentionally grounded through 0 ohm resistors with test points, as indicated by schematic notes. | | BH30 | GPIO_S0_SC_092 | TP9_NET | ✅ | GPIO_S0_SC_093 and GPIO_S0_SC_092 are intentionally grounded through 0 ohm resistors with test points, as indicated by schematic notes. | | BH10 | PCU_SMB_CLK | PCU_SMB_CLK | ✅ | PCU_SMB_CLK is correctly connected with a 2.2K pull-up to +V1P8S and routed to level shifter U5 for SMBus clock signal. | | BH12 | ILB_8254_SPKR | ILB_8254_SPKR | ✅ | ILB_8254_SPKR is connected to net ILB_8254_SPKR for PC speaker output functionality. | </details> <details> <summary><b>R48</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF2_PWR | ✅ | Connected to BUF2_PWR, which supplies power to the high-voltage side of level shifter U5. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 (3.3V supply), providing power through the 0 ohm resistor to BUF2_PWR. | </details> <details> <summary><b>R44</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_CLK | ✅ | Connected to DDR_SMB_CLK, providing pull-up for the SMBus clock line on the 3.3V side. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 (3.3V supply), providing the pull-up voltage for DDR_SMB_CLK. | </details> <details> <summary><b>R47</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_DATA | ✅ | Connected to DDR_SMB_DATA, providing pull-up for the SMBus data line on the 3.3V side. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 (3.3V supply), providing the pull-up voltage for DDR_SMB_DATA. | </details> <details> <summary><b>R45</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_CLK. | | 2 | 2 | PCU_SMB_CLK | ✅ | Connected to PCU_SMB_CLK, providing pull-up for the SMBus clock line on the 1.8V side. | </details> <details> <summary><b>R177</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_DATA. | | 2 | 2 | PCU_SMB_DATA | ✅ | Connected to PCU_SMB_DATA, providing pull-up for the SMBus data line on the 1.8V side. | </details> <details> <summary><b>R49</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_BUFF_ENB. | | 2 | 2 | PCU_SMB_BUFF_ENB | ✅ | Connected to PCU_SMB_BUFF_ENB, providing pull-up to enable the level shifter U5 by default. | </details> <details> <summary><b>R75</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S (1.8V supply), providing the pull-up voltage for PCU_SMB_ALERT. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Connected to PCU_SMB_ALERT, providing pull-up for the SMBus alert signal. | </details> <details> <summary><b>R840</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_DATA | ✅ | Connected to DDR_SMB_DATA, allowing the SMBus data line to be shared with LAN interface. | | 2 | 2 | LAN-SMB-DATA | ✅ | Connected to LAN-SMB-DATA, extending the SMBus data line to the LAN interface. | </details> <details> <summary><b>R841</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_CLK | ✅ | Connected to DDR_SMB_CLK, allowing the SMBus clock line to be shared with LAN interface. | | 2 | 2 | LAN-SMB-CLK | ✅ | Connected to LAN-SMB-CLK, extending the SMBus clock line to the LAN interface. | </details> <details> <summary><b>R842</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-SMB-ALERT# | ✅ | Connected to LAN-SMB-ALERT#, extending the SMBus alert line to the LAN interface. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Connected to PCU_SMB_ALERT, allowing the SMBus alert line to be shared with LAN interface. | </details> <details> <summary><b>U5</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DDR_SMB_CLK | ✅ | B2 pin correctly connected to DDR_SMB_CLK for 3.3V side clock signal translation. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V) for A-side voltage reference. | | 4 | A2 | PCU_SMB_CLK | ✅ | A2 pin correctly connected to PCU_SMB_CLK for 1.8V side clock signal translation. | | 5 | A1 | PCU_SMB_DATA | ✅ | A1 pin correctly connected to PCU_SMB_DATA for 1.8V side data signal translation. | | 6 | OE | PCU_SMB_BUFF_ENB | ✅ | OE pin connected to PCU_SMB_BUFF_ENB with pull-up to +V1P8S, keeping the level shifter enabled. | | 7 | VCCB | BUF2_PWR | ✅ | VCCB pin correctly connected to BUF2_PWR (3.3V via R48) for B-side voltage reference. | | 8 | B1 | DDR_SMB_DATA | ✅ | B1 pin correctly connected to DDR_SMB_DATA for 3.3V side data signal translation. | </details> <details> <summary><b>J4</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004869) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 correctly connected to GND for the debug serial connector ground reference. | | 2 | 2 | | ✅ | Pins 2, 3, and 6 are not connected, which is appropriate for a minimal 3-wire UART interface (GND, TX, RX). | | 3 | 3 | | ✅ | Pins 2, 3, and 6 are not connected, which is appropriate for a minimal 3-wire UART interface (GND, TX, RX). | | 6 | 6 | | ✅ | Pins 2, 3, and 6 are not connected, which is appropriate for a minimal 3-wire UART interface (GND, TX, RX). | | 4 | 4 | DBG_UART3_RXD | ✅ | Pin 4 correctly connected to DBG_UART3_RXD, which is the receive input to the board from the external serial cable. | | 5 | 5 | DBG_UART3_TXD_R | ✅ | Pin 5 correctly connected to DBG_UART3_TXD_R, which is the transmit output from the board to the external serial cable. | </details> <details> <summary><b>R51</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF3_PWR | ✅ | 0-ohm resistor correctly connecting +3VSB to BUF3_PWR, providing 3.3V standby power to the level translator's B-side. | | 2 | 2 | +3VSB | ✅ | 0-ohm resistor correctly connecting +3VSB to BUF3_PWR, providing 3.3V standby power to the level translator's B-side. | </details> <details> <summary><b>R819</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002000) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DBG_UART3_TXD | ✅ | 330-ohm series resistor correctly placed in the UART transmit path for protection against shorts and ESD events. | | 2 | 2 | DBG_UART3_TXD_R | ✅ | 330-ohm series resistor correctly placed in the UART transmit path for protection against shorts and ESD events. | </details> <details> <summary><b>R50</b> ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001859) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ❌ | <details><summary>R50 is a 100K pull-down resistor on the UART RX line. This is incorrect - UART signals should idle high (mark state), so this should be a pull-up resistor to +3VSB or BUF3_PWR instead of a pull-down to GND.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="27eb0188bc47cc9ba6f9" diff-visibility="full" variant="default" view-coords="78.29,43.02,85.79,50.52" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net GND <em>(from schematic)</em></li><li>Pin 2 is connected to net DBG_UART3_RXD <em>(from schematic)</em></li><li>R50 is a 100K-ohm resistor (part number 110-0001859) configured as a pull-down <em>(from schematic)</em></li><li>DBG_UART3_RXD connects to U6 pin 8 (B1) and J4 pin 4 <em>(from schematic)</em></li><li>In UART protocol, the idle state is logic high (mark state), and the start bit is logic low <em>(reasoning)</em></li><li>When no cable is connected to the debug port, the RX line should be pulled high to indicate the proper idle state <em>(reasoning)</em></li><li>A pull-down resistor causes the line to be low when nothing is connected, which violates the UART idle state requirement <em>(reasoning)</em></li><li>A low RX line when disconnected could be interpreted by the UART receiver as a continuous start bit or break condition, potentially causing spurious interrupts or errors <em>(reasoning)</em></li><li>When a cable is connected and transmitting logic high, the pull-down resistor fights against the external device&#x27;s driver, though the 100K value is weak enough that this may not cause immediate functional problems <em>(reasoning)</em></li><li>R50 should be changed to a pull-up resistor to +3VSB or BUF3_PWR (3.3V) instead of a pull-down to GND to maintain the correct UART idle state <em>(reasoning)</em></li><li>The 100K ohm value is appropriate for a UART pull resistor, but the polarity is incorrect <em>(reasoning)</em></li></ul></details> | | 2 | 2 | DBG_UART3_RXD | ❌ | <details><summary>R50 is a 100K pull-down resistor on the UART RX line. This is incorrect - UART signals should idle high (mark state), so this should be a pull-up resistor to +3VSB or BUF3_PWR instead of a pull-down to GND.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="27eb0188bc47cc9ba6f9" diff-visibility="full" variant="default" view-coords="78.29,41.25,85.79,48.75" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net GND <em>(from schematic)</em></li><li>Pin 2 is connected to net DBG_UART3_RXD <em>(from schematic)</em></li><li>R50 is a 100K-ohm resistor (part number 110-0001859) configured as a pull-down <em>(from schematic)</em></li><li>DBG_UART3_RXD connects to U6 pin 8 (B1) and J4 pin 4 <em>(from schematic)</em></li><li>In UART protocol, the idle state is logic high (mark state), and the start bit is logic low <em>(reasoning)</em></li><li>When no cable is connected to the debug port, the RX line should be pulled high to indicate the proper idle state <em>(reasoning)</em></li><li>A pull-down resistor causes the line to be low when nothing is connected, which violates the UART idle state requirement <em>(reasoning)</em></li><li>A low RX line when disconnected could be interpreted by the UART receiver as a continuous start bit or break condition, potentially causing spurious interrupts or errors <em>(reasoning)</em></li><li>When a cable is connected and transmitting logic high, the pull-down resistor fights against the external device&#x27;s driver, though the 100K value is weak enough that this may not cause immediate functional problems <em>(reasoning)</em></li><li>R50 should be changed to a pull-up resistor to +3VSB or BUF3_PWR (3.3V) instead of a pull-down to GND to maintain the correct UART idle state <em>(reasoning)</em></li><li>The 100K ohm value is appropriate for a UART pull resistor, but the polarity is incorrect <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R52</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LSENB | ✅ | 2.2K-ohm pull-up resistor on LSENB signal to +V1P8S, keeping the level translator's OE pin high by default to enable the buffer. | | 2 | 2 | +V1P8S | ✅ | 2.2K-ohm pull-up resistor on LSENB signal to +V1P8S, keeping the level translator's OE pin high by default to enable the buffer. | </details> <details> <summary><b>U6</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DBG_UART3_TXD | ✅ | B2 pin correctly connected to DBG_UART3_TXD, which routes through series resistor R819 to connector J4 pin 5. This translates the CPU's 1.8V UART TX signal to 3.3V for the external debug connector. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply), providing reference voltage for the A-side (CPU side) of the level translator. | | 4 | A2 | PCU_UART3_TXD | ✅ | A2 pin correctly connected to PCU_UART3_TXD from CPU GPIO_S0_SC_57. This is the low-voltage side of the UART transmit path. | | 5 | A1 | PCU_UART3_RXD | ✅ | A1 pin correctly connected to PCU_UART3_RXD from CPU GPIO_S0_SC_61. This is the low-voltage side of the UART receive path. | | 6 | OE | LSENB | ✅ | OE pin connected to LSENB with 2.2K pull-up to +V1P8S. The signal name suggests active-low enable, but the pull-up configuration indicates active-high operation, which would keep the buffer enabled by default. Without datasheet confirmation, this appears correct assuming typical active-high OE behavior. | | 7 | VCCB | BUF3_PWR | ✅ | VCCB pin correctly connected to BUF3_PWR, which is tied to +3VSB (3.3V standby) through 0-ohm resistor R51. This provides the reference voltage for the B-side (connector side) of the level translator. | | 8 | B1 | DBG_UART3_RXD | ✅ | B1 pin correctly connected to DBG_UART3_RXD, which routes to connector J4 pin 4 and has a 100K pull-down resistor R50. This translates the external 3.3V UART RX signal to 1.8V for the CPU. | </details> <details> <summary><b>R269</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SDA | ✅ | 22 ohm series resistor on I2C5 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line. | | 2 | 2 | I2C5_SDA | ✅ | 22 ohm series resistor on I2C5 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line. | </details> <details> <summary><b>R12</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SCL | ✅ | 22 ohm series resistor on I2C6 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line. | | 2 | 2 | I2C6_SCL | ✅ | 22 ohm series resistor on I2C6 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line. | </details> <details> <summary><b>R11</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SDA | ✅ | 22 ohm series resistor on I2C6 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line. | | 2 | 2 | I2C6_SDA | ✅ | 22 ohm series resistor on I2C6 SDA line between SoC and external bus. This provides signal damping and protection for the I2C data line. | </details> <details> <summary><b>R270</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SCL | ✅ | 22 ohm series resistor on I2C5 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line. | | 2 | 2 | I2C5_SCL | ✅ | 22 ohm series resistor on I2C5 SCL line between SoC and external bus. This provides signal damping and protection for the I2C clock line. | </details> <details> <summary><b>R84</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pull-up resistor connection to +V1P8A power rail for USB overcurrent signal SOC_USB_HOST_OC0. | | 2 | 2 | SOC_USB_HOST_OC0 | ✅ | Connected to SOC_USB_HOST_OC0, an active-low USB overcurrent signal from CPU1 pin C20. | </details> <details> <summary><b>R97</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pull-up resistor connection to +V1P8A power rail for USB overcurrent signal SOC_USB_HOST_OC1. | | 2 | 2 | SOC_USB_HOST_OC1 | ✅ | Connected to SOC_USB_HOST_OC1, an active-low USB overcurrent signal from CPU1 pin B20. | </details> <details> <summary><b>TP16</b> - 999-0000002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/999-0000002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP10_NET | ✅ | DNI test point on net TP10_NET providing access to GPIO_S0_SC_093 signal for testing and debugging. | </details> <details> <summary><b>R243</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP9_NET | ✅ | 0-ohm resistor connecting GPIO_S0_SC_092 (CPU1 pin BH30) to ground through TP9_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'. | | 2 | 2 | GND | ✅ | 0-ohm resistor connecting GPIO_S0_SC_092 (CPU1 pin BH30) to ground through TP9_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'. | </details> <details> <summary><b>TP13</b> - 999-0000002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/999-0000002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP9_NET | ✅ | DNI test point on net TP9_NET providing access to GPIO_S0_SC_092 signal for testing and debugging. | </details> <details> <summary><b>R261</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP10_NET | ✅ | 0-ohm resistor connecting GPIO_S0_SC_093 (CPU1 pin BG30) to ground through TP10_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'. | | 2 | 2 | GND | ✅ | 0-ohm resistor connecting GPIO_S0_SC_093 (CPU1 pin BG30) to ground through TP10_NET. This is an intentional configuration option as indicated by nearby schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A48 | DRAM_VDD_S4 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | AK38 | DRAM_VDD_S4_AK38 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | AM38 | DRAM_VDD_S4_AM38 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | AV41 | DRAM_VDD_S4_AV41 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | AV42 | DRAM_VDD_S4_AV42 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | BB46 | DRAM_VDD_S4_BB46 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | BD49 | DRAM_VDD_S4_BD49 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | BD52 | DRAM_VDD_S4_BD52 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | BD53 | DRAM_VDD_S4_BD53 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | BF44 | DRAM_VDD_S4_BF44 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | BG51 | DRAM_VDD_S4_BG51 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | BJ48 | DRAM_VDD_S4_BJ48 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | C51 | DRAM_VDD_S4_C51 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | D44 | DRAM_VDD_S4_D44 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | F49 | DRAM_VDD_S4_F49 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | F52 | DRAM_VDD_S4_F52 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | F53 | DRAM_VDD_S4_F53 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | H46 | DRAM_VDD_S4_H46 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | M41 | DRAM_VDD_S4_M41 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | M42 | DRAM_VDD_S4_M42 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | V38 | DRAM_VDD_S4_V38 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | Y38 | DRAM_VDD_S4_Y38 | +VDIMM | ✅ | DRAM_VDD_S4 pins supply 1.35V power to the DDR3L memory interface. These pins are correctly connected to the +VDIMM rail with appropriate decoupling capacitors. | | N28 | CORE_VSS_SENSE_N28 | VSS_SENSE | ✅ | CORE_VSS_SENSE is a ground sense pin for voltage regulation feedback. It is connected to the VSS_SENSE net for remote ground sensing. | | P28 | CORE_VCC_SENSE_P28 | VCC_SENSE | ✅ | CORE_VCC_SENSE is a voltage sense pin for SVID regulation feedback. It is connected to the VCC_SENSE net for remote sensing of the core voltage. | | AA22 | TP2_CORE_VCC_S0IX | $9N615 | ✅ | TP2_CORE_VCC_S0IX is a test point pin for monitoring core voltage. It is connected to test point TP2 which is marked DNI. | | AA24 | UNCORE_VNN_S3_AA24 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AC22 | UNCORE_VNN_S3_AC22 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AC24 | UNCORE_VNN_S3_AC24 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AD22 | UNCORE_VNN_S3_AD22 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AD24 | UNCORE_VNN_S3_AD24 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AF22 | UNCORE_VNN_S3_AF22 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AF24 | UNCORE_VNN_S3_AF24 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AG22 | UNCORE_VNN_S3_AG22 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AG24 | UNCORE_VNN_S3_AG24 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AJ22 | UNCORE_VNN_S3_AJ22 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AJ24 | UNCORE_VNN_S3_AJ24 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AK22 | UNCORE_VNN_S3_AK22 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AK24 | UNCORE_VNN_S3_AK24 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AK25 | UNCORE_VNN_S3_AK25 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AK27 | UNCORE_VNN_S3_AK27 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AK29 | UNCORE_VNN_S3_AK29 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AK30 | UNCORE_VNN_S3_AK30 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AK32 | UNCORE_VNN_S3_AK32 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AM22 | UNCORE_VNN_S3_AM22 | +VGFX | ✅ | UNCORE_VNN_S3 pins supply voltage to the uncore logic including graphics. These pins are correctly connected to the +VGFX rail with adequate decoupling. | | AA27 | CORE_VCC_S0IX_AA27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AA29 | CORE_VCC_S0IX_AA29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AA30 | CORE_VCC_S0IX_AA30 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AC27 | CORE_VCC_S0IX_AC27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AC29 | CORE_VCC_S0IX_AC29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AC30 | CORE_VCC_S0IX_AC30 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AD27 | CORE_VCC_S0IX_AD27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AD29 | CORE_VCC_S0IX_AD29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AD30 | CORE_VCC_S0IX_AD30 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AF27 | CORE_VCC_S0IX_AF27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AF29 | CORE_VCC_S0IX_AF29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AG27 | CORE_VCC_S0IX_AG27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AG29 | CORE_VCC_S0IX_AG29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | AG30 | CORE_VCC_S0IX_AG30 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | P26 | CORE_VCC_S0IX_P26 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | P27 | CORE_VCC_S0IX_P27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | U27 | CORE_VCC_S0IX_U27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | U29 | CORE_VCC_S0IX_U29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | V27 | CORE_VCC_S0IX_V27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | V29 | CORE_VCC_S0IX_V29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | V30 | CORE_VCC_S0IX_V30 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | Y27 | CORE_VCC_S0IX_Y27 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | Y29 | CORE_VCC_S0IX_Y29 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | Y30 | CORE_VCC_S0IX_Y30 | +VCORE | ✅ | CORE_VCC_S0IX pins supply voltage to the processor cores. These pins are correctly connected to the +VCORE rail with extensive decoupling. | | BB8 | UNCORE_VNN_SENSE | VCCGT_SENSE | ✅ | UNCORE_VNN_SENSE is a voltage sense pin for SVID regulation feedback. It is connected to the VCCGT_SENSE net for remote sensing of the uncore voltage. | | AD38 | DRAM_VDD_S4_AD38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 clock power pins supply power to the DDR3L clock circuits. These pins are correctly connected to DRAM_VDD_CLK, which is filtered from +VDIMM through a 0-ohm jumper. | | AF38 | DRAM_VDD_S4_AF38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 clock power pins supply power to the DDR3L clock circuits. These pins are correctly connected to DRAM_VDD_CLK, which is filtered from +VDIMM through a 0-ohm jumper. | | AF30 | TP_CORE_V1P05_S4 | $9N613 | ✅ | TP_CORE_V1P05_S4 is a test point pin for monitoring 1.05V core rail. It is connected to test point TP1 which is marked DNI. | </details> <details> <summary><b>R275</b> - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM, the main DRAM voltage supply rail. This is the source side of the 0-ohm jumper. | | 2 | 2 | DRAM_VDD_CLK | ✅ | Connected to DRAM_VDD_CLK, a separate DRAM voltage rail for clock circuitry. This is the load side of the 0-ohm jumper. | </details> <details> <summary><b>C292</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Standard ground connection for decoupling capacitor. | | 2 | 2 | DRAM_VDD_CLK | ✅ | Connected to DRAM_VDD_CLK. Provides bulk decoupling for the DRAM clock voltage rail. | </details> <details> <summary><b>C291</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Standard ground connection for decoupling capacitor. | | 2 | 2 | DRAM_VDD_CLK | ✅ | Connected to DRAM_VDD_CLK. Provides high-frequency decoupling for the DRAM clock voltage rail. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AC32 | CORE_V1P05_S3_AC32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,41.55,44.21,49.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | Y32 | CORE_V1P05_S3_Y32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,42.13,44.21,49.63" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | AA33 | CORE_V1P05_S3_AA33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,33.31,44.21,40.81" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | AF33 | CORE_V1P05_S3_AF33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,28.61,61.48,36.11" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | AG33 | CORE_V1P05_S3_AG33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.20,61.48,36.70" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | AG35 | CORE_V1P05_S3_AG35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.79,61.48,37.29" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | U33 | CORE_V1P05_S3_U33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.37,61.48,37.87" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | U35 | CORE_V1P05_S3_U35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.96,61.48,38.46" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | V33 | CORE_V1P05_S3_V33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,31.55,61.48,39.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V <em>(reasoning)</em></li><li>The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) <em>(from schematic)</em></li><li>Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail <em>(reasoning)</em></li><li>Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead <em>(from schematic)</em></li><li>Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) <em>(reasoning)</em></li><li>The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions <em>(reasoning)</em></li><li>Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error <em>(from schematic)</em></li></ul></details> | | A3 | VSS_A3_A3 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | A5 | VSS_A5_A5 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | A6 | VSS_A6_A6 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | A49 | VSS_A49_A49 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | A51 | VSS_A51_A51 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | A52 | VSS_A52_A52 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | AN16 | VSSA_AN16 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | B2 | VSS_B2_B2 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | B52 | VSS_B52_B52 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | B53 | VSS_B53_B53 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BE1 | VSS_BE1_BE1 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BE53 | VSS_BE53_BE53 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BG1 | VSS_BG1_BG1 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BG53 | VSS_BG53_BG53 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BH1 | VSS_BH1_BH1 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BH2 | VSS_BH2_BH2 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BH52 | VSS_BH52_BH52 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BH53 | VSS_BH53_BH53 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BJ2 | VSS_BJ2_BJ2 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BJ3 | VSS_BJ3_BJ3 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BJ5 | VSS_BJ5_BJ5 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BJ49 | VSS_BJ49_BJ49 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BJ51 | VSS_BJ51_BJ51 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | BJ52 | VSS_BJ52_BJ52 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | C1 | VSS_C1_C1 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | C53 | VSS_C53_C53 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | E1 | VSS_E1_E1 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | E53 | VSS_E53_E53 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | U16 | USB_VSSA_U16 | GND | ✅ | Ground pins correctly connected to GND net. All VSS and USB_VSSA pins provide ground reference for the SoC. | | B6 | UNCORE_V1P0_G3_B6 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided. | | C5 | UNCORE_V1P0_G3_C5 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided. | | U22 | UNCORE_V1P0_G3_U22 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided. | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided. | | C3 | USB3_V1P0_G3_C3 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided. | | Y19 | USB3_V1P0_G3_Y19 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 pins correctly connected to +V1P0A rail (1.0V always-on supply). Adequate decoupling provided. | | F1 | RESERVED_F1 | $10N1595 | ✅ | RESERVED_F1 pin connected to test point TP4 on net $10N1595. Connection to test point is acceptable for reserved pin. | | M14 | USB_V1P0_S3_M14 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S rail. Powers USB digital logic with adequate decoupling. | | U18 | USB_V1P0_S3_U18 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S rail. Powers USB digital logic with adequate decoupling. | | U19 | USB_V1P0_S3_U19 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S rail. Powers USB digital logic with adequate decoupling. | | N18 | USB_V3P3_G3_N18 | +3VSB | ✅ | USB_V3P3_G3 and PCU_V3P3_G3 pins correctly connected to +3VSB rail (3.3V standby supply). Adequate decoupling provided. | | P18 | USB_V3P3_G3_P18 | +3VSB | ✅ | USB_V3P3_G3 and PCU_V3P3_G3 pins correctly connected to +3VSB rail (3.3V standby supply). Adequate decoupling provided. | | N22 | PCU_V3P3_G3_N22 | +3VSB | ✅ | USB_V3P3_G3 and PCU_V3P3_G3 pins correctly connected to +3VSB rail (3.3V standby supply). Adequate decoupling provided. | | N20 | USB_V1P8_G3_N20 | +V1P8A | ✅ | USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided. | | U24 | UNCORE_V1P8_G3_U24 | +V1P8A | ✅ | USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided. | | U25 | PMU_V1P8_G3_U25 | +V1P8A | ✅ | USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided. | | V25 | PCU_V1P8_G3_V25 | +V1P8A | ✅ | USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided. | | AA18 | UNCORE_V1P8_G3_AA18 | +V1P8A | ✅ | USB_V1P8_G3, UNCORE_V1P8_G3, PMU_V1P8_G3, and PCU_V1P8_G3 pins correctly connected to +V1P8A rail (1.8V always-on supply). Proper decoupling provided. | | P22 | RTC_VCC_P22 | +RTCVCC | ✅ | RTC_VCC pin correctly connected to +RTCVCC rail (RTC battery backup supply). Proper decoupling provided. | | V18 | USB_HSIC_V1P24_G3_V18 | +V1P0A | ✅ | USB_HSIC_V1P24_G3 pin connected to +V1P0A rail (1.0V instead of 1.24V). This is correct per datasheet guidance when USB HSIC is not used. | | V32 | SVID_V1P0_S3_V32 | +V1P0S | ✅ | SVID_V1P0_S3 pin correctly connected to +V1P0S rail. Powers SVID interface logic with proper decoupling. | | AD16 | VSS_AD16 | VCC_VSS_V1P2 | ✅ | VSS pins connected to VCC_VSS_V1P2 net which connects to GND via 0-ohm resistor R216. This configuration is correct for designs where MIPI CSI is not used. | | AD18 | VSS_AD18 | VCC_VSS_V1P2 | ✅ | VSS pins connected to VCC_VSS_V1P2 net which connects to GND via 0-ohm resistor R216. This configuration is correct for designs where MIPI CSI is not used. | | AD35 | DRAM_V1P0_S0IX_AD35 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | AF35 | DRAM_V1P0_S0IX_AF35 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | AF36 | DRAM_V1P0_S0IX_AF36 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | AJ36 | DRAM_V1P0_S0IX_AJ36 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | AK35 | DRAM_V1P0_S0IX_AK35 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | AK36 | DRAM_V1P0_S0IX_AK36 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | Y35 | DRAM_V1P0_S0IX_Y35 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | Y36 | DRAM_V1P0_S0IX_Y36 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | AA36 | DRAM_V1P0_S0IX_AA36 | VCC_DRAM | ✅ | DRAM power pins correctly connected to VCC_DRAM net, which is fed from +V1P0S via 0-ohm jumper R265. Adequate decoupling provided. | | BD1 | VGA_V1P35_S3_F1_BD1 | VCC_CRT_V1P35 | ✅ | VGA_V1P35_S3_F1 pin correctly connected to VCC_CRT_V1P35 rail, fed from +V1P35S through ferrite FB4. Powers VGA CRT interface. | | AF16 | UNCORE_V1P0_S3_AF16 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling. | | AF18 | UNCORE_V1P0_S3_AF18 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling. | | G1 | UNCORE_V1P0_S3_G1 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling. | | Y18 | UNCORE_V1P0_S3_Y18 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These pins power uncore logic in S3 state with proper decoupling. | | AF19 | UNCORE_V1P35_S0IX_F6 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided. | | AG19 | UNCORE_V1P35_S0IX_F1_AG19 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided. | | AG32 | UNCORE_V1P35_S0IX_F2_AG32 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided. | | U36 | UNCORE_V1P35_S0IX_F4_U36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided. | | V36 | UNCORE_V1P35_S0IX_F3_V36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided. | | AA25 | UNCORE_V1P35_S0IX_F5_AA25 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided. | | AD36 | DRAM_V1P35_S0IX_F1_AD36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35 and DRAM_V1P35 pins correctly connected to VCC_UNCORE_V1P35 rail, fed from +V1P35S through ferrite FB3. Proper filtering and decoupling provided. | | AF21 | UNCORE_V1P0_S0IX_AF21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic. | | AG21 | UNCORE_V1P0_S0IX_AG21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic. | | V24 | UNCORE_V1P0_S0IX_V24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic. | | Y22 | UNCORE_V1P0_S0IX_Y22 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic. | | Y24 | UNCORE_V1P0_S0IX_Y24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic. | | AN29 | UNCORE_V1P0_S0IX_AN29 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic. | | AN30 | UNCORE_V1P0_S0IX_AN30 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, fed from +V1P0S through 0-ohm jumper R222. Powers visual/graphics uncore logic. | | AJ18 | DDI_V1P0_S0IX_AJ18 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling. | | AK19 | DDI_V1P0_S0IX_AK19 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling. | | AK21 | DDI_V1P0_S0IX_AK21 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling. | | AM16 | DDI_V1P0_S0IX_AM16 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These pins power the display interface logic with proper decoupling. | | AJ19 | ICLK_V1P35_S3_F1_AJ19 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail, fed from +V1P35S through ferrite FB5. Powers integrated clock logic. | | AG18 | ICLK_V1P35_S3_F2 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail, fed from +V1P35S through ferrite FB5. Powers integrated clock logic. | | BJ6 | VGA_V1P0_S3_BJ6 | +V1P0S | ✅ | VGA_V1P0_S3 pin correctly connected to +V1P0S rail. Powers VGA digital logic with proper decoupling. | | AK18 | PCIE_V1P0_S3_AK18 | +V1P0S | ✅ | PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling. | | AM18 | PCIE_V1P0_S3_AM18 | +V1P0S | ✅ | PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling. | | AM21 | PCIE_V1P0_S3_AM21 | +V1P0S | ✅ | PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling. | | AN18 | PCIE_SATA_V1P0_S3_AN18 | +V1P0S | ✅ | PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling. | | AN19 | SATA_V1P0_S3_AN19 | +V1P0S | ✅ | PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling. | | AN21 | PCIE_V1P0_S3_AN21 | +V1P0S | ✅ | PCIE and SATA power pins correctly connected to +V1P0S rail. These pins power PCIe and SATA interfaces with adequate decoupling. | | AM27 | LPC_V1P8V3P3_S3_AM27 | +VCC3S | ✅ | LPC, SD, and VGA 1.8V/3.3V power pins correctly connected to +VCC3S rail (3.3V supply). Proper decoupling provided. | | AN27 | SD3_V1P8V3P3_S3_AN27 | +VCC3S | ✅ | LPC, SD, and VGA 1.8V/3.3V power pins correctly connected to +VCC3S rail (3.3V supply). Proper decoupling provided. | | AN24 | VGA_V3P3_S3_AN24 | +VCC3S | ✅ | LPC, SD, and VGA 1.8V/3.3V power pins correctly connected to +VCC3S rail (3.3V supply). Proper decoupling provided. | | AM30 | UNCORE_V1P8_S3_AM30 | +V1P8S | ✅ | UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided. | | AN32 | UNCORE_V1P8_S3_AN32 | +V1P8S | ✅ | UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided. | | U38 | UNCORE_V1P8_S3_U38 | +V1P8S | ✅ | UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided. | | AM32 | HDA_LPE_V1P5V1P8_S3_AM32 | +V1P8S | ✅ | UNCORE_V1P8_S3 and HDA_LPE_V1P5V1P8_S3 pins correctly connected to +V1P8S rail (1.8V supply). Adequate decoupling provided. | | AN25 | GPIO_V1P0_S3_AN25 | +V1P0S | ✅ | GPIO_V1P0_S3 pin correctly connected to +V1P0S rail. Powers GPIO logic with proper decoupling. | </details> <details> <summary><b>FB4</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Output pin connected to VCC_CRT_V1P35, which powers the VGA/CRT interface. The ferrite provides filtering for this power domain. | </details> <details> <summary><b>FB3</b> - FERRITE_600OHM_1.3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0001423) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply. | | 2 | 2 | VCC_UNCORE_V1P35 | ✅ | Output pin connected to VCC_UNCORE_V1P35, which powers multiple CPU UNCORE and DRAM voltage pins. The ferrite provides filtering for this power domain. | </details> <details> <summary><b>FB5</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Output pin connected to VCC_ICLK_V1P35, which powers the internal clock circuitry. The ferrite provides filtering for this power domain. | </details> <details> <summary><b>R222</b> - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S power rail, which supplies multiple 1.0V power domains for the Intel Atom E3825 CPU including core, peripherals, and I/O interfaces. | | 2 | 2 | VCC_VIS_V1P0 | ✅ | Connected to VCC_VIS_V1P0 power rail, which supplies the CPU's graphics/VIS (Visual Intelligence) uncore domain during S0ix low-power state. | </details> <details> <summary><b>R265</b> - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S power rail, which supplies multiple 1.0V power domains for the CPU. | | 2 | 2 | VCC_DRAM | ✅ | Connected to VCC_DRAM power rail, which supplies the CPU's DRAM interface power pins in S0ix state. | </details> <details> <summary><b>R216</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VSS_V1P2 | ✅ | Connected to VCC_VSS_V1P2 net, which connects to CPU VSS pins AD16 and AD18. This net is grounded through the 0-ohm resistor when MIPI CSI is not used. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground connection for the CPU VSS pins through the 0-ohm resistor. | </details> <details> <summary><b>D7</b> - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N is correctly connected to GND, serving as the reference terminal for this bidirectional TVS diode. | | P | P | +5VSB | ✅ | Pin P is correctly connected to the +5VSB rail, serving as the protected line terminal of this bidirectional TVS diode for ESD protection. | </details> <details> <summary><b>J8</b> - 3430-0212 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3430-0212) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is correctly connected to the +5VSB power rail, serving as the power input/output terminal for this 2x1 vertical header connector. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND, serving as the ground return terminal for this connector. | </details> <details> <summary><b>J2</b> - 258-0004524 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004524) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to +5VSB but the component is marked DNI (Do Not Install), so it is electrically absent from the circuit. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND but the component is marked DNI (Do Not Install), so it is electrically absent from the circuit. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A11 | VSS1 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A15 | VSS2 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A19 | VSS3 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A23 | VSS4 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A27 | VSS5 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A31 | VSS6 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A35 | VSS7 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A39 | VSS8 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A43 | VSS9 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | A47 | VSS10 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA1 | VSS11 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA3 | VSS15 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA16 | VSS12 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA19 | VSS13 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA21 | VSS14 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA32 | VSS16 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA35 | VSS17 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA38 | VSS18 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AA53 | VSS19 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB4 | VSS21 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB6 | VSS28 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB10 | VSS20 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB41 | VSS22 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB45 | VSS23 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB47 | VSS24 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB48 | VSS25 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB50 | VSS26 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AB51 | VSS27 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC16 | VSS29 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC18 | VSS30 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC19 | VSS31 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC21 | VSS32 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC25 | VSS33 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC33 | VSS34 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC35 | VSS35 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC36 | VSS36 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AC38 | VSS37 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AD7 | VSS44 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AD19 | VSS38 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AD21 | VSS39 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AD25 | VSS40 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AD32 | VSS41 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AD33 | VSS42 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AD47 | VSS43 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE1 | VSS45 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE3 | VSS49 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE4 | VSS50 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE6 | VSS60 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE8 | VSS61 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE9 | VSS62 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE11 | VSS46 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE12 | VSS47 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE14 | VSS48 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE40 | VSS51 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE42 | VSS52 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE43 | VSS53 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE45 | VSS54 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE46 | VSS55 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE48 | VSS56 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE50 | VSS57 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE51 | VSS58 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AE53 | VSS59 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AF10 | VSS63 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AF12 | VSS64 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AF25 | VSS65 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AF32 | VSS66 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AF47 | VSS67 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AG16 | VSS68 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AG25 | VSS69 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AG36 | VSS70 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AG38 | VSS71 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH4 | VSS72 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH6 | VSS110 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH7 | VSS75 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH9 | VSS76 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH41 | VSS73 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH45 | VSS74 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH47 | VSS106 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH48 | VSS107 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH50 | VSS108 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AH51 | VSS109 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ1 | VSS77 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ3 | VSS83 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ16 | VSS78 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ21 | VSS79 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ25 | VSS80 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ27 | VSS81 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ29 | VSS82 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ30 | VSS84 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ32 | VSS85 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ33 | VSS86 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ35 | VSS87 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ38 | VSS88 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AJ53 | VSS89 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AK10 | VSS90 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AK14 | VSS91 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AK16 | VSS92 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AK33 | VSS93 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AK41 | VSS94 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AK44 | VSS95 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM7 | VSS113 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM12 | VSS96 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM19 | VSS97 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM24 | VSS98 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM25 | VSS99 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM29 | VSS100 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM33 | VSS101 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM35 | VSS102 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM36 | VSS103 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM40 | VSS104 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM44 | VSS111 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AM51 | VSS112 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN1 | VSS114 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN3 | VSS119 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN5 | VSS131 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN6 | VSS134 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN8 | VSS135 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN9 | VSS136 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN11 | VSS115 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN12 | VSS116 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN14 | VSS117 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN22 | VSS118 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN33 | VSS120 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN35 | VSS121 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN36 | VSS122 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN38 | VSS123 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN40 | VSS124 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN42 | VSS125 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN43 | VSS126 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN45 | VSS127 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN46 | VSS128 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN48 | VSS129 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN49 | VSS130 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN51 | VSS132 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AN53 | VSS133 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AP40 | VSS137 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT4 | VSS146 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT12 | VSS138 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT16 | VSS139 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT19 | VSS140 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT24 | VSS141 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT27 | VSS142 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT30 | VSS143 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT35 | VSS144 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT38 | VSS145 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT47 | VSS147 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AT52 | VSS148 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AU1 | VSS149 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AU3 | VSS151 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AU24 | VSS150 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AU30 | VSS152 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AU38 | VSS153 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AU51 | VSS154 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV7 | VSS167 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV12 | VSS155 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV13 | VSS156 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV14 | VSS157 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV18 | VSS158 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV19 | VSS159 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV24 | VSS160 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV27 | VSS161 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV30 | VSS162 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV35 | VSS163 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV38 | VSS164 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV47 | VSS165 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AV51 | VSS166 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AW3 | VSS171 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AW13 | VSS168 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AW19 | VSS169 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AW27 | VSS170 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AW35 | VSS172 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AY4 | VSS177 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AY9 | VSS179 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AY10 | VSS173 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AY22 | VSS174 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AY32 | VSS175 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AY36 | VSS176 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | AY50 | VSS178 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA14 | VSS180 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA19 | VSS181 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA22 | VSS182 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA27 | VSS183 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA32 | VSS184 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA35 | VSS185 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA40 | VSS186 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BA53 | VSS187 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BB19 | VSS188 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BB27 | VSS189 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BB35 | VSS190 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BC20 | VSS191 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BC22 | VSS192 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BC26 | VSS193 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BC28 | VSS194 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BC32 | VSS195 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BC34 | VSS196 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BC42 | VSS197 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BD19 | VSS198 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BD24 | VSS199 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BD27 | VSS200 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BD30 | VSS201 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BD35 | VSS202 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BE2 | VSS204 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BE8 | VSS206 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BE19 | VSS203 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BE35 | VSS205 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BF4 | VSS213 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BF12 | VSS207 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BF16 | VSS208 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BF24 | VSS209 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BF30 | VSS211 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BF36 | VSS212 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BF38 | VSS210 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BG31 | VSS214 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BG34 | VSS215 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BG39 | VSS216 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BG42 | VSS217 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BG45 | VSS218 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BG49 | VSS219 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ7 | VSS230 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ11 | VSS220 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ15 | VSS221 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ19 | VSS222 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ23 | VSS223 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ27 | VSS224 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ31 | VSS225 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ35 | VSS226 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ39 | VSS227 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ43 | VSS228 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | BJ47 | VSS229 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | C14 | VSS231 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | C31 | VSS232 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | C34 | VSS233 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | C39 | VSS234 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | C42 | VSS235 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | C45 | VSS236 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | C49 | VSS237 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | D12 | VSS238 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | D16 | VSS239 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | D24 | VSS240 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | D30 | VSS241 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | D36 | VSS242 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | D38 | VSS243 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | E8 | VSS246 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | E19 | VSS244 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | E35 | VSS245 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F2 | VSS248 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F5 | VSS253 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F7 | VSS254 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F19 | VSS247 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F24 | VSS249 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F27 | VSS250 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F30 | VSS251 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | F35 | VSS252 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G10 | VSS255 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G20 | VSS256 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G22 | VSS257 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G26 | VSS258 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G28 | VSS259 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G32 | VSS260 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G34 | VSS261 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | G42 | VSS262 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | H19 | VSS263 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | H27 | VSS264 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | H35 | VSS265 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J1 | VSS266 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J16 | VSS267 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J19 | VSS268 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J22 | VSS269 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J27 | VSS270 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J32 | VSS271 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J35 | VSS272 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J40 | VSS273 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | J53 | VSS274 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | K4 | VSS279 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | K9 | VSS281 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | K14 | VSS275 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | K22 | VSS276 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | K32 | VSS277 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | K36 | VSS278 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | K50 | VSS280 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | L13 | VSS282 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | L19 | VSS283 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | L27 | VSS284 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | L35 | VSS285 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M19 | VSS286 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M26 | VSS287 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M27 | VSS288 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M28 | VSS105 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M34 | VSS289 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M35 | VSS290 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M38 | VSS291 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M47 | VSS292 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | M51 | VSS293 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | N1 | VSS294 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | N16 | VSS295 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | N38 | VSS296 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | N51 | VSS297 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P4 | VSS306 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P9 | VSS309 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P13 | VSS298 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P16 | VSS299 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P19 | VSS300 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P20 | VSS301 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P24 | VSS302 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P32 | VSS303 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P35 | VSS304 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P38 | VSS305 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P47 | VSS307 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | P52 | VSS308 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | T40 | VSS310 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U1 | VSS311 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U3 | VSS316 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U5 | VSS326 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U6 | VSS329 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U8 | VSS330 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U9 | VSS331 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U11 | VSS312 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U12 | VSS313 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U14 | VSS314 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U21 | VSS315 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U30 | VSS317 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U32 | VSS318 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U40 | VSS319 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U42 | VSS320 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U43 | VSS321 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U45 | VSS322 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U46 | VSS323 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U48 | VSS324 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U49 | VSS325 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U51 | VSS327 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | U53 | VSS328 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V7 | VSS340 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V12 | VSS332 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V16 | VSS333 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V19 | VSS334 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V21 | VSS335 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V35 | VSS336 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V40 | VSS337 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V44 | VSS338 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | V51 | VSS339 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y7 | VSS349 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y9 | VSS350 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y10 | VSS341 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y14 | VSS342 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y16 | VSS343 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y21 | VSS344 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y25 | VSS345 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y33 | VSS346 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y41 | VSS347 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | | Y44 | VSS348 | GND | ✅ | All VSS ground pins on this schematic page are correctly connected to the GND net. These 350 pins represent the complete set of ground connections for the Intel Atom E3825 SoC shown on this page. | </details> <details> <summary><b>MEM2</b> - MICRON MT41K256M16HA ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | VDDQ1 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | A2 | DQU5 | M_DATA_A15 | ✅ | DQ13 data pin correctly connected to M_DATA_A15 for upper byte data bit 5. | | A3 | DQU7 | M_DATA_A14 | ✅ | DQ15 data pin correctly connected to M_DATA_A14 for upper byte data bit 7. | | A7 | DQU4 | M_DATA_A13 | ✅ | DQ12 data pin correctly connected to M_DATA_A13 for upper byte data bit 4. | | A8 | VDDQ5 | +VDIMM | ✅ | VDDQ5 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | A9 | VSS9 | GND | ✅ | VSS9 ground pin correctly connected to GND. | | B1 | VSSQ1 | GND | ✅ | VSSQ1 DQ ground pin correctly connected to GND for isolated noise immunity. | | B2 | VDD8 | +VDIMM | ✅ | VDD8 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | B3 | VSS6 | GND | ✅ | VSS6 ground pin correctly connected to GND. | | B7 | /DQSU | M_DQS_A_N1 | ✅ | Upper byte data strobe complement correctly connected to M_DQS_A_N1 for differential signaling. | | B8 | DQU6 | M_DATA_A12 | ✅ | DQ14 data pin correctly connected to M_DATA_A12 for upper byte data bit 6. | | B9 | VSSQ7 | GND | ✅ | VSSQ7 DQ ground pin correctly connected to GND for isolated noise immunity. | | C1 | VDDQ2 | +VDIMM | ✅ | VDDQ2 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | C2 | DQU3 | M_DATA_A11 | ✅ | DQ11 data pin correctly connected to M_DATA_A11 for upper byte data bit 3. | | C3 | DQU1 | M_DATA_A10 | ✅ | DQ9 data pin correctly connected to M_DATA_A10 for upper byte data bit 1. | | C7 | DQSU | M_DQS_A_P1 | ✅ | Upper byte data strobe correctly connected to M_DQS_A_P1 for differential signaling. | | C8 | DQU2 | M_DATA_A8 | ✅ | DQ10 data pin correctly connected to M_DATA_A8 for upper byte data bit 2. | | C9 | VDDQ6 | +VDIMM | ✅ | VDDQ6 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | D1 | VSSQ2 | GND | ✅ | VSSQ2 DQ ground pin correctly connected to GND for isolated noise immunity. | | D2 | VDDQ9 | +VDIMM | ✅ | VDDQ9 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | D3 | DMU | M_DM_A1 | ✅ | Upper byte data mask pin correctly connected to M_DM_A1 for write data masking. | | D7 | DQU0 | M_DATA_A9 | ✅ | DQ8 data pin correctly connected to M_DATA_A9 for upper byte data bit 0. | | D8 | VSSQ5 | GND | ✅ | VSSQ5 DQ ground pin correctly connected to GND for isolated noise immunity. | | D9 | VDD4 | +VDIMM | ✅ | VDD4 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | E1 | VSS1 | GND | ✅ | VSS1 ground pin correctly connected to GND. | | E2 | VSSQ4 | GND | ✅ | VSSQ4 DQ ground pin correctly connected to GND for isolated noise immunity. | | E3 | DQL0 | M_DATA_A0 | ✅ | DQ0 data pin correctly connected to M_DATA_A0 for lower byte data bit 0. | | E7 | DML | M_DM_A0 | ✅ | Lower byte data mask pin correctly connected to M_DM_A0 for write data masking. | | E8 | VSSQ6 | GND | ✅ | VSSQ6 DQ ground pin correctly connected to GND for isolated noise immunity. | | E9 | VDDQ7 | +VDIMM | ✅ | VDDQ7 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | F1 | VDDQ3 | +VDIMM | ✅ | VDDQ3 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | F2 | DQL2 | M_DATA_A2 | ✅ | DQ2 data pin correctly connected to M_DATA_A2 for lower byte data bit 2. | | F3 | DQSL | M_DQS_A_P0 | ✅ | Lower byte data strobe correctly connected to M_DQS_A_P0 for differential signaling. | | F7 | DQL1 | M_DATA_A1 | ✅ | DQ1 data pin correctly connected to M_DATA_A1 for lower byte data bit 1. | | F8 | DQL3 | M_DATA_A3 | ✅ | DQ3 data pin correctly connected to M_DATA_A3 for lower byte data bit 3. | | F9 | VSSQ8 | GND | ✅ | VSSQ8 DQ ground pin correctly connected to GND for isolated noise immunity. | | G1 | VSSQ3 | GND | ✅ | VSSQ3 DQ ground pin correctly connected to GND for isolated noise immunity. | | G2 | DQL6 | M_DATA_A6 | ✅ | DQ6 data pin correctly connected to M_DATA_A6 for lower byte data bit 6. | | G3 | /DQSL | M_DQS_A_N0 | ✅ | Lower byte data strobe complement correctly connected to M_DQS_A_N0 for differential signaling. | | G7 | VDD1 | +VDIMM | ✅ | VDD1 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | G8 | VSS7 | GND | ✅ | VSS7 ground pin correctly connected to GND. | | G9 | VSSQ9 | GND | ✅ | VSSQ9 DQ ground pin correctly connected to GND for isolated noise immunity. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ reference voltage correctly connected to SM_VREF_DQ1_A with proper voltage divider generating VDDQ/2. | | H2 | VDDQ4 | +VDIMM | ✅ | VDDQ4 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | H3 | DQL4 | M_DATA_A4 | ✅ | DQ4 data pin correctly connected to M_DATA_A4 for lower byte data bit 4. | | H7 | DQL7 | M_DATA_A7 | ✅ | DQ7 data pin correctly connected to M_DATA_A7 for lower byte data bit 7. | | H8 | DQL5 | M_DATA_A5 | ✅ | DQ5 data pin correctly connected to M_DATA_A5 for lower byte data bit 5. | | H9 | VDDQ8 | +VDIMM | ✅ | VDDQ8 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | J1 | NC1__ODT1_ | | ✅ | NC1 (ODT1) no-connect pin correctly left unconnected per datasheet. | | J2 | VSS5 | GND | ✅ | VSS5 ground pin correctly connected to GND. | | J3 | /RAS | M_RAS_A_L | ✅ | Row address strobe command input correctly connected to M_RAS_A_L, shared with MEM3. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock input positive correctly connected to M_CLK_A_P0, shared with MEM3. | | J8 | VSS8 | GND | ✅ | VSS8 ground pin correctly connected to GND. | | J9 | NC3__CKE1_ | | ✅ | NC3 (CKE1) no-connect pin correctly left unconnected per datasheet. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination enable correctly connected to M_ODT_A0, shared with MEM3. | | K2 | VDD9 | +VDIMM | ✅ | VDD9 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | K3 | /CAS | M_CAS_A_L | ✅ | Column address strobe command input correctly connected to M_CAS_A_L, shared with MEM3. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock input complement correctly connected to M_CLK_A_N0, shared with MEM3. | | K8 | VDD2 | +VDIMM | ✅ | VDD2 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable correctly connected to M_CKE_A0, shared with MEM3. | | L1 | NC2__/CS1_ | | ✅ | NC2 (CS1) no-connect pin correctly left unconnected per datasheet. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select command input correctly connected to M_CS_A_L0, shared with MEM3. | | L3 | /WE | M_WE_A_L | ✅ | Write enable command input correctly connected to M_WE_A_L, shared with MEM3. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address A10 with auto-precharge function correctly connected to M_MA_A10, shared with MEM3. | | L8 | ZQ | M_ZQ1 | ✅ | ZQ calibration pin correctly connected to M_ZQ1 with 240 ohm resistor to ground. | | L9 | NC4__ZQ1_ | | ✅ | NC4 (ZQ1) no-connect pin correctly left unconnected per datasheet. | | M1 | VSS2 | GND | ✅ | VSS2 ground pin correctly connected to GND. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address BA0 correctly connected to M_BS_A0, shared with MEM3. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address BA2 correctly connected to M_BS_A2, shared with MEM3. | | M7 | NC5 | | ✅ | NC5 no-connect pin correctly left unconnected per datasheet. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA reference voltage correctly connected to SM_VREF_CA1_A with proper voltage divider generating VDDQ/2. | | M9 | VSS10 | GND | ✅ | VSS10 ground pin correctly connected to GND. | | N1 | VDD6 | +VDIMM | ✅ | VDD6 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | N2 | A3 | M_MA_A3 | ✅ | Address A3 correctly connected to M_MA_A3, shared with MEM3. | | N3 | A0 | M_MA_A0 | ✅ | Address A0 correctly connected to M_MA_A0, shared with MEM3. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address A12 with burst chop function correctly connected to M_MA_A12, shared with MEM3. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address BA1 correctly connected to M_BS_A1, shared with MEM3. | | N9 | VDD3 | +VDIMM | ✅ | VDD3 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | P1 | VSS3 | GND | ✅ | VSS3 ground pin correctly connected to GND. | | P2 | A5 | M_MA_A5 | ✅ | Address A5 correctly connected to M_MA_A5, shared with MEM3. | | P3 | A2 | M_MA_A2 | ✅ | Address A2 correctly connected to M_MA_A2, shared with MEM3. | | P7 | A1 | M_MA_A1 | ✅ | Address A1 correctly connected to M_MA_A1, shared with MEM3. | | P8 | A4 | M_MA_A4 | ✅ | Address A4 correctly connected to M_MA_A4, shared with MEM3. | | P9 | VSS11 | GND | ✅ | VSS11 ground pin correctly connected to GND. | | R1 | VDD7 | +VDIMM | ✅ | VDD7 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | R2 | A7 | M_MA_A7 | ✅ | Address A7 correctly connected to M_MA_A7, shared with MEM3. | | R3 | A9 | M_MA_A9 | ✅ | Address A9 correctly connected to M_MA_A9, shared with MEM3. | | R7 | A11 | M_MA_A11 | ✅ | Address A11 correctly connected to M_MA_A11, shared with MEM3. | | R8 | A6 | M_MA_A6 | ✅ | Address A6 correctly connected to M_MA_A6, shared with MEM3. | | R9 | VDD5 | +VDIMM | ✅ | VDD5 power supply pin correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | T1 | VSS4 | GND | ✅ | VSS4 ground pin correctly connected to GND. | | T2 | /RESET | M_A_RST_L | ✅ | Active-low reset input correctly connected to M_A_RST_L, shared with MEM3. | | T3 | A13 | M_MA_A13 | ✅ | Address A13 correctly connected to M_MA_A13, shared with MEM3. | | T7 | A14 | M_MA_A14 | ✅ | Address A14 correctly connected to M_MA_A14, shared with MEM3. | | T8 | A8 | M_MA_A8 | ✅ | Address A8 correctly connected to M_MA_A8, shared with MEM3. | | T9 | VSS12 | GND | ✅ | VSS12 ground pin correctly connected to GND. | </details> <details> <summary><b>MEM3</b> - MICRON MT41K256M16HA ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | C1 | VDDQ2 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | F1 | VDDQ3 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | H2 | VDDQ4 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | A8 | VDDQ5 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | C9 | VDDQ6 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | D2 | VDDQ9 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | E9 | VDDQ7 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | H9 | VDDQ8 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | D9 | VDD4 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | B1 | VSSQ1 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | D1 | VSSQ2 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | G1 | VSSQ3 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | E2 | VSSQ4 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | D8 | VSSQ5 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | E8 | VSSQ6 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | B9 | VSSQ7 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | F9 | VSSQ8 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | G9 | VSSQ9 | GND | ✅ | VSSQ DQ ground pins correctly connected to GND for isolated noise immunity. | | B2 | VDD8 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | K2 | VDD9 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | G7 | VDD1 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | K8 | VDD2 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | N1 | VDD6 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | N9 | VDD3 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | R1 | VDD7 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | R9 | VDD5 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail for 1.35V DDR3L operation. | | C7 | DQSU | M_DQS_A_P3 | ✅ | Upper byte data strobe differential pair correctly connected to M_DQS_A_P3 and M_DQS_A_N3. | | B7 | /DQSU | M_DQS_A_N3 | ✅ | Upper byte data strobe differential pair correctly connected to M_DQS_A_P3 and M_DQS_A_N3. | | D3 | DMU | M_DM_A3 | ✅ | Upper byte data mask pin correctly connected to M_DM_A3 for write data masking. | | D7 | DQU0 | M_DATA_A29 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | C3 | DQU1 | M_DATA_A26 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | C8 | DQU2 | M_DATA_A28 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | C2 | DQU3 | M_DATA_A27 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | A7 | DQU4 | M_DATA_A25 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | A2 | DQU5 | M_DATA_A30 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | B8 | DQU6 | M_DATA_A24 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | A3 | DQU7 | M_DATA_A31 | ✅ | Upper byte data pins (DQ8-DQ15) correctly connected to M_DATA_A24 through M_DATA_A31 for bits 24-31 of 32-bit data bus. | | E1 | VSS1 | GND | ✅ | VSS ground pins correctly connected to GND. | | M1 | VSS2 | GND | ✅ | VSS ground pins correctly connected to GND. | | P1 | VSS3 | GND | ✅ | VSS ground pins correctly connected to GND. | | T1 | VSS4 | GND | ✅ | VSS ground pins correctly connected to GND. | | J2 | VSS5 | GND | ✅ | VSS ground pins correctly connected to GND. | | B3 | VSS6 | GND | ✅ | VSS ground pins correctly connected to GND. | | G8 | VSS7 | GND | ✅ | VSS ground pins correctly connected to GND. | | J8 | VSS8 | GND | ✅ | VSS ground pins correctly connected to GND. | | A9 | VSS9 | GND | ✅ | VSS ground pins correctly connected to GND. | | M9 | VSS10 | GND | ✅ | VSS ground pins correctly connected to GND. | | P9 | VSS11 | GND | ✅ | VSS ground pins correctly connected to GND. | | T9 | VSS12 | GND | ✅ | VSS ground pins correctly connected to GND. | | E3 | DQL0 | M_DATA_A16 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | F7 | DQL1 | M_DATA_A17 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | F2 | DQL2 | M_DATA_A18 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | F8 | DQL3 | M_DATA_A19 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | H3 | DQL4 | M_DATA_A20 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | H8 | DQL5 | M_DATA_A21 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | G2 | DQL6 | M_DATA_A22 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | H7 | DQL7 | M_DATA_A23 | ✅ | Lower byte data pins (DQ0-DQ7) correctly connected to M_DATA_A16 through M_DATA_A23 for bits 16-23 of 32-bit data bus. | | E7 | DML | M_DM_A2 | ✅ | Lower byte data mask pin correctly connected to M_DM_A2 for write data masking. | | F3 | DQSL | M_DQS_A_P2 | ✅ | Lower byte data strobe differential pair correctly connected to M_DQS_A_P2 and M_DQS_A_N2. | | G3 | /DQSL | M_DQS_A_N2 | ✅ | Lower byte data strobe differential pair correctly connected to M_DQS_A_P2 and M_DQS_A_N2. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ reference voltage correctly connected to SM_VREF_DQ1_A with proper voltage divider generating VDDQ/2, shared with MEM2. | | J1 | NC1__ODT1_ | | ✅ | No-connect pins correctly left unconnected per datasheet. | | L1 | NC2__/CS1_ | | ✅ | No-connect pins correctly left unconnected per datasheet. | | J9 | NC3__CKE1_ | | ✅ | No-connect pins correctly left unconnected per datasheet. | | L9 | NC4__ZQ1_ | | ✅ | No-connect pins correctly left unconnected per datasheet. | | M7 | NC5 | | ✅ | No-connect pins correctly left unconnected per datasheet. | | J3 | /RAS | M_RAS_A_L | ✅ | Command inputs (RAS, CAS, WE) correctly connected to shared command bus with MEM2. | | K3 | /CAS | M_CAS_A_L | ✅ | Command inputs (RAS, CAS, WE) correctly connected to shared command bus with MEM2. | | L3 | /WE | M_WE_A_L | ✅ | Command inputs (RAS, CAS, WE) correctly connected to shared command bus with MEM2. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock inputs correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock inputs correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination enable correctly connected to M_ODT_A0, shared with MEM2. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable correctly connected to M_CKE_A0, shared with MEM2. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select command input correctly connected to M_CS_A_L0, shared with MEM2. | | L8 | ZQ | M_ZQ2 | ✅ | ZQ calibration pin correctly connected to M_ZQ2 with 240 ohm resistor to ground. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address inputs correctly connected to shared bank address bus with MEM2. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address inputs correctly connected to shared bank address bus with MEM2. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address inputs correctly connected to shared bank address bus with MEM2. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA reference voltage correctly connected to SM_VREF_CA1_A with proper voltage divider generating VDDQ/2, shared with MEM2. | | N3 | A0 | M_MA_A0 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | P7 | A1 | M_MA_A1 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | P3 | A2 | M_MA_A2 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | N2 | A3 | M_MA_A3 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | P8 | A4 | M_MA_A4 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | P2 | A5 | M_MA_A5 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | R8 | A6 | M_MA_A6 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | R2 | A7 | M_MA_A7 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | T8 | A8 | M_MA_A8 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | R3 | A9 | M_MA_A9 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | R7 | A11 | M_MA_A11 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | T3 | A13 | M_MA_A13 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | T7 | A14 | M_MA_A14 | ✅ | Address inputs A0-A14 correctly connected to shared address bus with MEM2. | | T2 | /RESET | M_A_RST_L | ✅ | Active-low reset input correctly connected to M_A_RST_L, shared with MEM2. | </details> <details> <summary><b>C124</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A to provide AC decoupling for the DDR3 VREFDQ reference voltage. | | 2 | 2 | GND | ✅ | Connected to GND to complete the decoupling path for the reference voltage. | </details> <details> <summary><b>R310</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM to form the upper leg of a voltage divider for DDR3 VREFDQ reference voltage generation. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A reference voltage net, providing the midpoint of the voltage divider. | </details> <details> <summary><b>C329</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A to provide additional AC decoupling for the DDR3 VREFDQ reference voltage. | | 2 | 2 | GND | ✅ | Connected to GND to complete the decoupling path for the reference voltage. | </details> <details> <summary><b>R325</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND to form the lower leg of the voltage divider for DDR3 VREFDQ reference voltage generation. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A reference voltage net, providing the midpoint of the voltage divider. | </details> <details> <summary><b>R327</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ2 | ✅ | Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM3 via net M_ZQ2. This provides the reference impedance for the memory's output driver calibration. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit. | </details> <details> <summary><b>R140</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ1 | ✅ | Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM2 via net M_ZQ1. This provides the reference impedance for the memory's output driver calibration. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit. | </details> <details> <summary><b>C374</b> - 10pF 5% 50V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. However, C374 is marked DNI (Do Not Install), so this connection is not electrically present in the final circuit. | | 2 | 2 | M_A_RST_L | ✅ | Connected to M_A_RST_L, the reset signal net for the memory devices. However, C374 is marked DNI (Do Not Install), so this connection is not electrically present in the final circuit. | </details> <details> <summary><b>R353</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_A_DRAMRST_L | ✅ | Connected to M_A_DRAMRST_L net, which is the source of the DRAM reset signal. This pin serves as the input side of the 0-ohm series resistor. | | 2 | 2 | M_A_RST_L | ✅ | Connected to M_A_RST_L net, which connects to the /RESET pins of memory devices MEM2 and MEM3. This pin serves as the output side of the 0-ohm series resistor. | </details> <details> <summary><b>C287</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor negative terminal correctly connected to GND. | | 2 | 2 | +VCC3 | ✅ | Decoupling capacitor positive terminal correctly connected to +VCC3 power rail. | </details> <details> <summary><b>U33</b> - M24C02-WMN6TP-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/M24C02-WMN6TP-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E0 | DDR_E0 | ✅ | E0 address input pin connected to DDR_E0 net. Pin is floating because pull-down resistor R118 is DNI. | | 2 | E1 | DDR_E1 | ✅ | E1 address input pin connected to DDR_E1 net. Pin is floating because pull-down resistor R123 is DNI. | | 3 | E2 | GND | ✅ | E2 address input pin correctly connected to GND to set address bit to 0. | | 4 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA pin correctly connected to DDR_SMB_DATA for I2C data communication. | | 6 | SCL | DDR_SMB_CLK | ✅ | SCL pin correctly connected to DDR_SMB_CLK for I2C clock communication. | | 7 | ~WC | DDR_WP_A | ✅ | Write Control pin connected to DDR_WP_A net. Pin is floating because both configuration resistors R121 and R122 are DNI. | | 8 | VCC | +VCC3 | ✅ | VCC power pin correctly connected to +VCC3 with decoupling capacitor C287. | </details> <details> <summary><b>C145</b> - 123-0004765 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | | 2 | 2 | GND | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | </details> <details> <summary><b>C146</b> - 123-0004765 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | | 2 | 2 | GND | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | </details> <details> <summary><b>C369</b> - 123-0004765 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | | 2 | 2 | GND | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | </details> <details> <summary><b>C370</b> - 123-0004765 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | | 2 | 2 | GND | ✅ | Decoupling capacitor for +VDIMM_VTT rail. Pin 1 connects to +VDIMM_VTT and pin 2 connects to GND. | </details> <details> <summary><b>C331</b> - 3.3pF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_CLK_A_N0 | ✅ | C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization. | | 2 | 2 | M_CLK_A_P0 | ✅ | C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization. | </details> <details> <summary><b>FL1</b> - 3750-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3750-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CH1-IN | SD3_CD# | ✅ | CH1-IN is connected to SD3_CD# (card detect signal) which has a 100K pull-up to +V1P8S via R182. This channel filters the card detect signal before it goes to the microSD connector. | | 2 | CH2-IN | SD3_D2 | ✅ | CH2-IN is connected to SD3_D2 (data line 2) which has a 100K pull-up to +VCC3 via R174. This channel filters the data line before it goes to the microSD connector. | | 3 | CH3-IN | SD3_D3 | ✅ | CH3-IN is connected to SD3_D3 (data line 3) which has a 100K pull-up to +VCC3 via R180. This channel filters the data line before it goes to the microSD connector. | | 4 | CH4-IN | SD3_CMD | ✅ | CH4-IN is connected to SD3_CMD (command line) which has a 100K pull-up to +VCC3 via R173. This channel filters the command line before it goes to the microSD connector. | | 5 | CH5-IN | SD3_CLK | ✅ | CH5-IN is connected to SD3_CLK (clock line) which has a 100K pull-up to +VCC3 via R157. This channel filters the clock line before it goes to the microSD connector. | | 6 | CH6-IN | SD3_D0 | ✅ | CH6-IN is connected to SD3_D0 (data line 0) which has a 100K pull-up to +VCC3 via R156. This channel filters the data line before it goes to the microSD connector. | | 7 | CH7-IN | SD3_D1 | ✅ | CH7-IN is connected to SD3_D1 (data line 1) which has a 100K pull-up to +VCC3 via R155. This channel filters the data line before it goes to the microSD connector. | | 8 | CH8-IN | | ✅ | CH8-IN is unconnected. Channel 8 is unused in this design. | | 9 | CH8-OUT | | ✅ | CH8-OUT is unconnected. Channel 8 is unused in this design. | | 10 | CH7-OUT | SD3_D1_R | ✅ | CH7-OUT is connected to SD3_D1_R which goes to P2 pin 8 (DAT1). This is the filtered output for data line 1. | | 11 | CH6-OUT | SD3_D0_R | ✅ | CH6-OUT is connected to SD3_D0_R which goes to P2 pin 7 (DAT0). This is the filtered output for data line 0. | | 12 | CH5-OUT | SD3_CLK_R | ✅ | CH5-OUT is connected to SD3_CLK_R which goes to P2 pin 5 (CLOCK). This is the filtered output for the clock line. | | 13 | CH4-OUT | SD3_CMD_R | ✅ | CH4-OUT is connected to SD3_CMD_R which goes to P2 pin 3 (CMD). This is the filtered output for the command line. | | 14 | CH3-OUT | SD3_D3_R | ✅ | CH3-OUT is connected to SD3_D3_R which goes to P2 pin 2 (CD/DAT3). This is the filtered output for data line 3. | | 15 | CH2-OUT | SD3_D2_R | ✅ | CH2-OUT is connected to SD3_D2_R which goes to P2 pin 1 (DAT2). This is the filtered output for data line 2. | | 16 | CH1-OUT | SD3_CD_R | ✅ | CH1-OUT is connected to SD3_CD_R which goes to P2 pin 10 (CD). This is the filtered output for the card detect signal. | | 17 | GND_PAD | GND | ✅ | GND_PAD is connected to GND. This provides the ground reference for the passive filter. | </details> <details> <summary><b>P2</b> - 158-0001269 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/158-0001269) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | SD3_D2_R | ✅ | DAT2 is connected to SD3_D2_R, the filtered data line 2 from FL1 channel 2. This is correct for the microSD interface. | | 2 | CD/DAT3 | SD3_D3_R | ✅ | CD/DAT3 is connected to SD3_D3_R, the filtered data line 3 from FL1 channel 3. This is correct for the microSD interface. | | 3 | CMD | SD3_CMD_R | ✅ | CMD is connected to SD3_CMD_R, the filtered command line from FL1 channel 4. This is correct for the microSD interface. | | 4 | VDD | +VCC3 | ✅ | VDD is connected to +VCC3 with decoupling capacitors C162 and C159 (both 10uF). This provides proper power to the microSD card. | | 5 | CLOCK | SD3_CLK_R | ✅ | CLOCK is connected to SD3_CLK_R, the filtered clock line from FL1 channel 5. This is correct for the microSD interface. | | 6 | VSS | GND | ✅ | VSS is connected to GND. This provides the ground reference for the microSD card. | | 7 | DAT0 | SD3_D0_R | ✅ | DAT0 is connected to SD3_D0_R, the filtered data line 0 from FL1 channel 6. This is correct for the microSD interface. | | 8 | DAT1 | SD3_D1_R | ✅ | DAT1 is connected to SD3_D1_R, the filtered data line 1 from FL1 channel 7. This is correct for the microSD interface. | | 9 | GND | GND | ✅ | GND is connected to GND. This provides an additional ground connection for the microSD card. | | 10 | CD | SD3_CD_R | ✅ | CD is connected to SD3_CD_R, the filtered card detect signal from FL1 channel 1. The card detect has a pull-up to +V1P8S (1.8V) instead of +VCC3 (3.3V), which is likely intentional for host controller I/O compatibility. | | 11 | GND3 | FGND-uSD | ✅ | GND3 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection. | | 12 | GND4 | FGND-uSD | ✅ | GND4 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection. | | 13 | GND5 | FGND-uSD-Front | ✅ | GND5 is connected to FGND-uSD-Front. This is a frame ground connection for EMI/ESD protection. | | 14 | GND6 | FGND-uSD-Front | ✅ | GND6 is connected to FGND-uSD-Front. This is a frame ground connection for EMI/ESD protection. | | 15 | GND7 | FGND-uSD | ✅ | GND7 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection. | | 16 | GND8 | FGND-uSD | ✅ | GND8 is connected to FGND-uSD. This is a frame ground connection for EMI/ESD protection. | </details> <details> <summary><b>R171</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 2.2K pullup resistor correctly connected between +V1P8S and HPD_ENB (U2 CT_HPD control pin). | | 2 | 2 | HPD_ENB | ✅ | 2.2K pullup resistor correctly connected between +V1P8S and HPD_ENB (U2 CT_HPD control pin). | </details> <details> <summary><b>R172</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 2.2K pullup resistor correctly connected between +V1P8S and LS_OE (U2 level shifter enable pin). | | 2 | 2 | LS_OE | ✅ | 2.2K pullup resistor correctly connected between +V1P8S and LS_OE (U2 level shifter enable pin). | </details> <details> <summary><b>C17</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0.1µF decoupling capacitor correctly connected between GND and +V1P8S (U2 VCCA supply). | | 2 | 2 | +V1P8S | ✅ | 0.1µF decoupling capacitor correctly connected between GND and +V1P8S (U2 VCCA supply). | </details> <details> <summary><b>C155</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0.1µF decoupling capacitor correctly connected between GND and +5VSB (U2 VCC5V supply). | | 2 | 2 | +5VSB | ✅ | 0.1µF decoupling capacitor correctly connected between GND and +5VSB (U2 VCC5V supply). | </details> <details> <summary><b>C157</b> - 123-0001144 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001144) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +HDMI_CRT_VCC | ✅ | 4.7µF decoupling capacitor correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and GND. | | 2 | 2 | GND | ✅ | 4.7µF decoupling capacitor correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and GND. | </details> <details> <summary><b>L7</b> - 126-0001418 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/ferriteBeadInductortypefilter/ENFA0003_PDF_FERRITEBEADINDUCTORTYPEFILTER?lastModifiedDatetime=20250707190934) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0001418) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +HDMI_CRT_VCC | ✅ | Ferrite bead correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and D5_0V_HDMI (HDMI connector +5V) for EMI filtering. | | 2 | P2 | D5_0V_HDMI | ✅ | Ferrite bead correctly connected between +HDMI_CRT_VCC (U2 5V_OUT) and D5_0V_HDMI (HDMI connector +5V) for EMI filtering. | </details> <details> <summary><b>U2</b> - TPD12S016PW ❌</summary> DRCY flagged 3 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004333) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 15 | CLK- | HDMI_OUT_CLK_DN | ❌ | <details><summary>CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,58.30,53.07,65.80" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN <em>(from schematic)</em></li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP <em>(from schematic)</em></li><li>Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) <em>(from schematic)</em></li><li>The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 16 | CLK+ | HDMI_OUT_CLK_DP | ❌ | <details><summary>CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,58.89,53.07,66.39" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN <em>(from schematic)</em></li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP <em>(from schematic)</em></li><li>Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) <em>(from schematic)</em></li><li>The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 17 | D0- | HDMI_OUT_TX0_DN | ❌ | <details><summary>D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,59.48,53.07,66.98" aspect-ratio="1.29" } <ul><li>Pin 17 is connected to net HDMI_OUT_TX0_DN <em>(from schematic)</em></li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP <em>(from schematic)</em></li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN <em>(from schematic)</em></li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP <em>(from schematic)</em></li><li>Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 18 | D0+ | HDMI_OUT_TX0_DP | ❌ | <details><summary>D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,60.07,53.07,67.57" aspect-ratio="1.29" } <ul><li>Pin 17 is connected to net HDMI_OUT_TX0_DN <em>(from schematic)</em></li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP <em>(from schematic)</em></li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN <em>(from schematic)</em></li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP <em>(from schematic)</em></li><li>Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 22 | D2- | HDMI_OUT_TX2_DN | ❌ | <details><summary>D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,61.83,53.07,69.33" aspect-ratio="1.29" } <ul><li>Pin 17 is connected to net HDMI_OUT_TX0_DN <em>(from schematic)</em></li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP <em>(from schematic)</em></li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN <em>(from schematic)</em></li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP <em>(from schematic)</em></li><li>Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 23 | D2+ | HDMI_OUT_TX2_DP | ❌ | <details><summary>D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,62.42,53.07,69.92" aspect-ratio="1.29" } <ul><li>Pin 17 is connected to net HDMI_OUT_TX0_DN <em>(from schematic)</em></li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP <em>(from schematic)</em></li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN <em>(from schematic)</em></li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP <em>(from schematic)</em></li><li>Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 20 | D1- | HDMI_OUT_TX1_DN | ❌ | <details><summary>D1+ and D1- pins are swapped. Pin 20 should be D1+ but is connected to HDMI_OUT_TX1_DN, and pin 21 should be D1- but is connected to HDMI_OUT_TX1_DP.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,60.66,53.07,68.16" aspect-ratio="1.29" } <ul><li>Pin 20 is connected to net HDMI_OUT_TX1_DN <em>(from schematic)</em></li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP <em>(from schematic)</em></li><li>Pin 20 should be D1+ (HDMI TMDS data channel 1 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 21 should be D1- (HDMI TMDS data channel 1 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pin 20 labeled as D1- and pin 21 labeled as D1+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The D1 data channel signals are inverted due to the pin swap, which will prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 21 | D1+ | HDMI_OUT_TX1_DP | ❌ | <details><summary>D1+ and D1- pins are swapped. Pin 20 should be D1+ but is connected to HDMI_OUT_TX1_DN, and pin 21 should be D1- but is connected to HDMI_OUT_TX1_DP.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,61.24,53.07,68.74" aspect-ratio="1.29" } <ul><li>Pin 20 is connected to net HDMI_OUT_TX1_DN <em>(from schematic)</em></li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP <em>(from schematic)</em></li><li>Pin 20 should be D1+ (HDMI TMDS data channel 1 positive) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>Pin 21 should be D1- (HDMI TMDS data channel 1 negative) per the datasheet for PW package <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</em></li><li>The schematic symbol has pin 20 labeled as D1- and pin 21 labeled as D1+, which is opposite to the datasheet <em>(from schematic)</em></li><li>The D1 data channel signals are inverted due to the pin swap, which will prevent proper HDMI operation <em>(reasoning)</em></li><li>The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout <em>(reasoning)</em></li></ul></details> | | 1 | CEC_A | HDMI_CEC | ✅ | CEC_A pin correctly connected to HDMI_CEC net with 10K pullup resistor R29 to +V1P8S. | | 2 | SCL_A | HDMI_DDCCLK | ✅ | SCL_A pin correctly connected to HDMI_DDCCLK net with 10K pullup resistor R28 to +V1P8S. | | 3 | SDA_A | HDMI_DDCDAT | ✅ | SDA_A pin correctly connected to HDMI_DDCDAT net with 10K pullup resistor R30 to +V1P8S. | | 4 | HPD_A | HDMI_HPD | ✅ | HPD_A pin correctly connected to HDMI_HPD net for hot plug detect output to HDMI controller. | | 5 | LS_OE | LS_OE | ✅ | LS_OE pin correctly connected to LS_OE net with 2.2K pullup resistor R172 to +V1P8S for level shifter enable control. | | 6 | GND1 | GND | ✅ | Ground pins correctly connected to GND net. | | 14 | GND2 | GND | ✅ | Ground pins correctly connected to GND net. | | 19 | GND3 | GND | ✅ | Ground pins correctly connected to GND net. | | 7 | CEC_B | C_HDMI_CEC | ✅ | CEC_B pin correctly connected to C_HDMI_CEC net for HDMI connector side CEC signal. | | 8 | SCL_B | C_HDMI_SCL | ✅ | SCL_B pin correctly connected to C_HDMI_SCL net for HDMI connector side SCL signal. | | 9 | SDA_B | C_HDMI_SDA | ✅ | SDA_B pin correctly connected to C_HDMI_SDA net for HDMI connector side SDA signal. | | 10 | HPD_B | C_HDMI_HPD | ✅ | HPD_B pin correctly connected to C_HDMI_HPD net for hot plug detect input from HDMI connector. | | 11 | VCC5V | +5VSB | ✅ | VCC5V pin correctly connected to +5VSB net with 0.1uF decoupling capacitor C155. | | 12 | CT_HPD | HPD_ENB | ✅ | CT_HPD pin correctly connected to HPD_ENB net with 2.2K pullup resistor R171 to +V1P8S for load switch and HPD control. | | 13 | 5V_OUT | +HDMI_CRT_VCC | ✅ | 5V_OUT pin correctly connected to +HDMI_CRT_VCC net with 4.7uF decoupling capacitor C157 and ferrite bead L7 to HDMI connector. | | 24 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S net with 0.1uF decoupling capacitor C17. | </details> <details> <summary><b>L14</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_CLK_C_DN | ✅ | IN1 pin connects to HDMI_CLK_C_DN through AC coupling capacitor C401, providing common mode filtering for the negative clock signal. | | 3 | IN2 | HDMI_CLK_C_DP | ✅ | IN2 pin connects to HDMI_CLK_C_DP through AC coupling capacitor C400, providing common mode filtering for the positive clock signal. | | 4 | OUT2 | HDMI_OUT_CLK_DP | ✅ | OUT2 pin connects to HDMI_OUT_CLK_DP, outputting the filtered positive clock signal to U2 and then to the HDMI connector. | | 6 | OUT1 | HDMI_OUT_CLK_DN | ✅ | OUT1 pin connects to HDMI_OUT_CLK_DN, outputting the filtered negative clock signal to U2 and then to the HDMI connector. | </details> <details> <summary><b>L17</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX2_C_DN | ✅ | IN1 pin connects to HDMI_TX2_C_DN through AC coupling capacitor C407, providing common mode filtering for the negative data signal of channel 2. | | 3 | IN2 | HDMI_TX2_C_DP | ✅ | IN2 pin connects to HDMI_TX2_C_DP through AC coupling capacitor C406, providing common mode filtering for the positive data signal of channel 2. | | 4 | OUT2 | HDMI_OUT_TX2_DP | ✅ | OUT2 pin connects to HDMI_OUT_TX2_DP, outputting the filtered positive data signal to U2 and then to the HDMI connector. | | 6 | OUT1 | HDMI_OUT_TX2_DN | ✅ | OUT1 pin connects to HDMI_OUT_TX2_DN, outputting the filtered negative data signal to U2 and then to the HDMI connector. | </details> <details> <summary><b>L16</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX1_C_DN | ✅ | IN1 pin connects to HDMI_TX1_C_DN through AC coupling capacitor C405, providing common mode filtering for the negative data signal of channel 1. | | 3 | IN2 | HDMI_TX1_C_DP | ✅ | IN2 pin connects to HDMI_TX1_C_DP through AC coupling capacitor C404, providing common mode filtering for the positive data signal of channel 1. | | 4 | OUT2 | HDMI_OUT_TX1_DP | ✅ | OUT2 pin connects to HDMI_OUT_TX1_DP, outputting the filtered positive data signal to U2 and then to the HDMI connector. | | 6 | OUT1 | HDMI_OUT_TX1_DN | ✅ | OUT1 pin connects to HDMI_OUT_TX1_DN, outputting the filtered negative data signal to U2 and then to the HDMI connector. | </details> <details> <summary><b>L15</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX0_C_DN | ✅ | IN1 pin connects to HDMI_TX0_C_DN through AC coupling capacitor C403, providing common mode filtering for the negative data signal of channel 0. | | 3 | IN2 | HDMI_TX0_C_DP | ✅ | IN2 pin connects to HDMI_TX0_C_DP through AC coupling capacitor C402, providing common mode filtering for the positive data signal of channel 0. | | 4 | OUT2 | HDMI_OUT_TX0_DP | ✅ | OUT2 pin connects to HDMI_OUT_TX0_DP, outputting the filtered positive data signal to U2 and then to the HDMI connector. | | 6 | OUT1 | HDMI_OUT_TX0_DN | ✅ | OUT1 pin connects to HDMI_OUT_TX0_DN, outputting the filtered negative data signal to U2 and then to the HDMI connector. | </details> <details> <summary><b>R801</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DN | ✅ | Connected to HDMI_TX2_C_DN, providing DC bias path for AC-coupled HDMI data signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>R802</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DP | ✅ | Connected to HDMI_TX2_C_DP, providing DC bias path for AC-coupled HDMI data signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>R803</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DN | ✅ | Connected to HDMI_TX1_C_DN, providing DC bias path for AC-coupled HDMI data signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>R804</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DP | ✅ | Connected to HDMI_TX1_C_DP, providing DC bias path for AC-coupled HDMI data signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>R805</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DN | ✅ | Connected to HDMI_TX0_C_DN, providing DC bias path for AC-coupled HDMI data signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>R806</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DP | ✅ | Connected to HDMI_TX0_C_DP, providing DC bias path for AC-coupled HDMI data signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>R807</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CLK_C_DP | ✅ | Connected to HDMI_CLK_C_DP, providing DC bias path for AC-coupled HDMI clock signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>R808</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CLK_C_DN | ✅ | Connected to HDMI_CLK_C_DN, providing DC bias path for AC-coupled HDMI clock signal. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switchably connected to ground through Q101. | </details> <details> <summary><b>Q101</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | HDMI_TERM | ✅ | Drain connects to HDMI_TERM net, which is the common termination point for eight 619Ω resistors (R801-R808) connected to HDMI differential signal lines. When Q101 is on, it pulls HDMI_TERM to ground, providing a DC bias path for AC-coupled HDMI signals. | | G | GATE | $15N747 | ✅ | Gate connects to net $15N747, which is driven by +VCC3 through 0Ω resistor R809. This keeps Q101 always on, continuously pulling HDMI_TERM to ground. | | S | SOURCE | GND | ✅ | Source connects to GND, providing the return path for drain current when Q101 is on. | </details> <details> <summary><b>R809</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $15N747 | ✅ | Connects to gate of Q101 via net $15N747. | | 2 | 2 | +VCC3 | ✅ | Connects to +VCC3 supply, providing gate drive voltage to Q101 through the 0Ω resistor. | </details> <details> <summary><b>P1</b> - 158-0004513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/158-0004513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | HPLG | C_HDMI_HPD | ✅ | Hot Plug Detect (HPLG) pin correctly connected to the HPD signal path through U2 (TPD12S016PW) ESD protection device. | | 2 | NC | | ✅ | No Connect (NC) pin is correctly left unconnected. | | 3 | DAT2+ | HDMI_OUT_TX2_DP | ✅ | TMDS Data2+ pin correctly connected through common mode choke L17 and AC coupling capacitor C406 to the HDMI transmitter. | | 4 | DAT2_S | GND | ✅ | TMDS Data2 shield pin correctly connected to ground for EMI shielding. | | 5 | DAT2- | HDMI_OUT_TX2_DN | ✅ | TMDS Data2- pin correctly connected through common mode choke L17 and AC coupling capacitor C407 to the HDMI transmitter. | | 6 | DAT1+ | HDMI_OUT_TX1_DP | ✅ | TMDS Data1+ pin correctly connected through common mode choke L16 and AC coupling capacitor C404 to the HDMI transmitter. | | 7 | DAT1_S | GND | ✅ | TMDS Data1 shield pin correctly connected to ground for EMI shielding. | | 8 | DAT1- | HDMI_OUT_TX1_DN | ✅ | TMDS Data1- pin correctly connected through common mode choke L16 and AC coupling capacitor C405 to the HDMI transmitter. | | 9 | DAT0+ | HDMI_OUT_TX0_DP | ✅ | TMDS Data0+ pin correctly connected through common mode choke L15 and AC coupling capacitor C402 to the HDMI transmitter. | | 10 | DAT0_S | GND | ✅ | TMDS Data0 shield pin correctly connected to ground for EMI shielding. | | 11 | DAT0- | HDMI_OUT_TX0_DN | ✅ | TMDS Data0- pin correctly connected through common mode choke L15 and AC coupling capacitor C403 to the HDMI transmitter. | | 12 | CLK+ | HDMI_OUT_CLK_DP | ✅ | TMDS Clock+ pin correctly connected through common mode choke L14 and AC coupling capacitor C400 to the HDMI transmitter. | | 13 | CLK_S | GND | ✅ | TMDS Clock shield pin correctly connected to ground for EMI shielding. | | 14 | CLK- | HDMI_OUT_CLK_DN | ✅ | TMDS Clock- pin correctly connected through common mode choke L14 and AC coupling capacitor C401 to the HDMI transmitter. | | 15 | CEC | C_HDMI_CEC | ✅ | CEC pin correctly connected through U2 ESD protection to the system CEC signal with appropriate pull-up resistor. | | 16 | DDC/CEC_GND | GND | ✅ | DDC/CEC ground pin correctly connected to system ground. | | 17 | SCL | C_HDMI_SCL | ✅ | DDC SCL pin correctly connected through U2 ESD protection to the system I2C clock signal with appropriate pull-up resistor. | | 18 | SDA | C_HDMI_SDA | ✅ | DDC SDA pin correctly connected through U2 ESD protection to the system I2C data signal with appropriate pull-up resistor. | | 19 | +5V | D5_0V_HDMI | ✅ | 5V power pin correctly connected through ferrite bead L7 to the charge pump output of U2 with appropriate decoupling. | | 20 | MTG1 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding. | | 21 | MTG2 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding. | | 22 | MTG3 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding. | | 23 | MTG4 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground for mechanical stability and EMI shielding. | </details> <details> <summary><b>C161</b> - 2267-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2267-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to main circuit ground (GND). This is the circuit ground side of an EMI suppression capacitor between circuit ground and chassis ground. | | 2 | 2 | GND_EARTH | ✅ | Connected to chassis/earth ground (GND_EARTH) from HDMI connector shield. This is the chassis ground side of an EMI suppression capacitor. | </details> <details> <summary><b>C16</b> - 123-0004415 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0004415) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to main circuit ground (GND). Component is marked DNI (Do Not Install), so it is electrically absent from the circuit. | | 2 | 2 | GND_EARTH | ✅ | Connected to chassis/earth ground (GND_EARTH). Component is marked DNI (Do Not Install), so it is electrically absent from the circuit. | </details> <details> <summary><b>R29</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CEC | ✅ | 10K ohm pull-up resistor for HDMI CEC line on the system side of the level translator U2. | | 2 | 2 | +V1P8S | ✅ | 10K ohm pull-up resistor for HDMI CEC line on the system side of the level translator U2. | </details> <details> <summary><b>R28</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCCLK | ✅ | 10K ohm pull-up resistor for HDMI DDC clock line (I2C SCL) on the system side of the level translator U2. | | 2 | 2 | +V1P8S | ✅ | 10K ohm pull-up resistor for HDMI DDC clock line (I2C SCL) on the system side of the level translator U2. | </details> <details> <summary><b>R30</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCDAT | ✅ | 10K ohm pull-up resistor for HDMI DDC data line (I2C SDA) on the system side of the level translator U2. | | 2 | 2 | +V1P8S | ✅ | 10K ohm pull-up resistor for HDMI DDC data line (I2C SDA) on the system side of the level translator U2. | </details> <details> <summary><b>U32</b> - AP2172MPG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP2162_72.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/AP2172MPG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | IN | +USBVCC | ✅ | Input voltage pin correctly connected to +USBVCC with proper bypass capacitors. | | 3 | EN1 | USB_HOST_EN0 | ✅ | Enable 1 input correctly connected through level shifter U4 from SOC, with DNI pull-down resistor. | | 4 | EN2 | USB_HOST_EN1 | ✅ | Enable 2 input correctly connected through level shifter U4 from SOC, with DNI pull-down resistor. | | 5 | OC2# | SOC_USB_HOST_OC1 | ✅ | Over-current flag 2 output connected to SOC. No visible external pull-up resistor, likely relying on SOC internal pull-up. | | 6 | OUTB | USBP2 | ✅ | Output B correctly connected through ferrite bead L2 to VBUS2 with proper output capacitors. | | 7 | OUTA | USBP1 | ✅ | Output A correctly connected through ferrite bead L1 to VBUS1 with proper output capacitors. | | 8 | OC1# | SOC_USB_HOST_OC0 | ✅ | Over-current flag 1 output connected to SOC. No visible external pull-up resistor, likely relying on SOC internal pull-up. | | 9 | GND_PAD | GND | ✅ | Exposed pad correctly connected to GND for thermal and electrical grounding. | </details> <details> <summary><b>R116</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB_HOST_BUFF_ENB | ✅ | Connected to USB_HOST_BUFF_ENB, which drives the OE (output enable) pin of level translator U4. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A supply, providing the pull-up voltage reference for the OE signal. | </details> <details> <summary><b>R117</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the pull-down reference. | | 2 | 2 | SOC_USB_HOST_EN1 | ✅ | Connected to SOC_USB_HOST_EN1, providing pull-down functionality to ensure a defined low state when not actively driven by the SOC. | </details> <details> <summary><b>U4</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | USB_HOST_EN0 | ✅ | B2 output translates SOC_USB_HOST_EN0 to USB_HOST_EN0 for USB power switch EN1. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground. | | 3 | VCCA | +V1P8A | ✅ | VCCA supply correctly connected to +V1P8A for SOC-side voltage level. | | 4 | A2 | SOC_USB_HOST_EN0 | ✅ | A2 input receives SOC_USB_HOST_EN0 signal for translation to B-side. | | 5 | A1 | SOC_USB_HOST_EN1 | ✅ | A1 input receives SOC_USB_HOST_EN1 signal for translation to B-side. | | 6 | OE | USB_HOST_BUFF_ENB | ✅ | OE pin pulled high to VCCA through R116 to enable the translator by default. | | 7 | VCCB | +USBVCC | ✅ | VCCB supply correctly connected to +USBVCC for USB-side voltage level. | | 8 | B1 | USB_HOST_EN1 | ✅ | B1 output translates SOC_USB_HOST_EN1 to USB_HOST_EN1 for USB power switch EN2. | </details> <details> <summary><b>U9</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H0 | ✅ | D+ pin provides ESD protection for USB port A high-speed data line. Connected to USB_H0 net which routes through common mode choke CHOKE4 to USB connector pin 3 (DA+). | | 2 | D- | USB_L0 | ✅ | D- pin provides ESD protection for USB port A high-speed data line. Connected to USB_L0 net which routes through common mode choke CHOKE4 to USB connector pin 2 (DA-). | | 3 | ID | | ✅ | ID pin is left unconnected. This is acceptable per datasheet as ID pin can be left floating if not used in the application. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the ESD protection device. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as it is not internally connected per the datasheet. | | 6 | VBUS | VBUS1 | ✅ | VBUS pin provides ESD protection for USB port A power line. Connected to VBUS1 net with proper decoupling capacitors and routes to USB connector pin 1 (VBUSA). | </details> <details> <summary><b>U8</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H1 | ✅ | D+ pin provides ESD protection for USB port B high-speed data line. Connected to USB_H1 net which routes through common mode choke CHOKE3 to USB connector pin 12 (DB+). | | 2 | D- | USB_L1 | ✅ | D- pin provides ESD protection for USB port B high-speed data line. Connected to USB_L1 net which routes through common mode choke CHOKE3 to USB connector pin 11 (DB-). | | 3 | ID | | ✅ | ID pin is left unconnected. This is acceptable per datasheet as ID pin can be left floating if not used in the application. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the ESD protection device. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as it is not internally connected per the datasheet. | | 6 | VBUS | VBUS2 | ✅ | VBUS pin provides ESD protection for USB port B power line. Connected to VBUS2 net with proper decoupling capacitors and routes to USB connector pin 10 (VBUSB). | </details> <details> <summary><b>U29</b> - TPD4USB30 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/TPD4USB30) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D1+ | USB3_TX0P_C | ✅ | D1+ pin is connected to USB3_TX0P_C net, which routes to the USB connector's SSTX+ pin. This provides ESD protection for the USB 3.0 transmit positive differential signal. | | 2 | D1- | USB3_TX0N_C | ✅ | D1- pin is connected to USB3_TX0N_C net, which routes to the USB connector's SSTX- pin. This provides ESD protection for the USB 3.0 transmit negative differential signal. | | 3 | GND1 | GND | ✅ | GND1 pin is correctly connected to the GND net, providing ground reference for the ESD protection device. | | 4 | D2+ | USB3_RX0P_C | ✅ | D2+ pin is connected to USB3_RX0P_C net, which routes to the USB connector's SSRX+ pin. This provides ESD protection for the USB 3.0 receive positive differential signal. | | 5 | D2- | USB3_RX0N_C | ✅ | D2- pin is connected to USB3_RX0N_C net, which routes to the USB connector's SSRX- pin. This provides ESD protection for the USB 3.0 receive negative differential signal. | | 6 | NC4 | USB3_RX0N_C | ✅ | NC4 pin is connected to USB3_RX0N_C net (same as D2-). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation. | | 7 | NC3 | USB3_RX0P_C | ✅ | NC3 pin is connected to USB3_RX0P_C net (same as D2+). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation. | | 8 | GND2 | GND | ✅ | GND2 pin is correctly connected to the GND net, providing a second ground reference for the ESD protection device. | | 9 | NC2 | USB3_TX0N_C | ✅ | NC2 pin is connected to USB3_TX0N_C net (same as D1-). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation. | | 10 | NC1 | USB3_TX0P_C | ✅ | NC1 pin is connected to USB3_TX0P_C net (same as D1+). The 'NC' designation typically means 'No Connect', but this pin is connected to a signal net, which may be incorrect without datasheet confirmation. | </details> <details> <summary><b>USB1</b> - 258-0004503 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004503) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUSA | VBUS1 | ✅ | VBUSA provides power to USB port A. Connected to VBUS1 net with proper decoupling and power switching through U32. | | 2 | DA- | USB_L0 | ✅ | DA- is the USB 2.0 differential pair negative signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9. | | 3 | DA+ | USB_H0 | ✅ | DA+ is the USB 2.0 differential pair positive signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9. | | 4 | GNDA | GND | ✅ | GNDA is the ground connection for USB port A, correctly connected to the GND net. | | 5 | SSRX- | USB3_RX0N_C | ✅ | SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected through common mode choke CHOKE1 with ESD protection from U29. | | 6 | SSRX+ | USB3_RX0P_C | ✅ | SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected through common mode choke CHOKE1 with ESD protection from U29. | | 7 | GND_DRAIN | GND | ✅ | GND_DRAIN is a drain/shield ground connection, correctly connected to the GND net. | | 8 | SSTX- | USB3_TX0N_C | ✅ | SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C191. | | 9 | SSTX+ | USB3_TX0P_C | ✅ | SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C192. | | 10 | VBUSB | VBUS2 | ✅ | VBUSB provides power to USB port B. Connected to VBUS2 net with proper decoupling and power switching through U32. | | 11 | DB- | USB_L1 | ✅ | DB- is the USB 2.0 differential pair negative signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8. | | 12 | DB+ | USB_H1 | ✅ | DB+ is the USB 2.0 differential pair positive signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8. | | 13 | GNDB | GND | ✅ | GNDB is the ground connection for USB port B, correctly connected to the GND net. | | MH1 | SHIELD1 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | | MH2 | SHIELD2 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | | MH3 | SHIELD3 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | | MH4 | SHIELD4 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | </details> <details> <summary><b>C192</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXP0 | ✅ | Pin 1 is connected to USB3_TXP0, the positive SuperSpeed transmit signal from the SOC before AC coupling. | | 2 | 2 | USB3_TX0P-R | ✅ | Pin 2 is connected to USB3_TX0P-R, the AC-coupled positive SuperSpeed transmit signal going to CHOKE2. | </details> <details> <summary><b>C191</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXN0 | ✅ | Pin 1 is connected to USB3_TXN0, the negative SuperSpeed transmit signal from the SOC before AC coupling. | | 2 | 2 | USB3_TX0N-R | ✅ | Pin 2 is connected to USB3_TX0N-R, the AC-coupled negative SuperSpeed transmit signal going to CHOKE2. | </details> <details> <summary><b>CHOKE2</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_TX0P-R | ✅ | IN1 is connected to USB3_TX0P-R, the AC-coupled positive SuperSpeed transmit signal from the SOC. This pin correctly receives the positive signal after AC coupling for common mode filtering. | | 3 | IN2 | USB3_TX0N-R | ✅ | IN2 is connected to USB3_TX0N-R, the AC-coupled negative SuperSpeed transmit signal from the SOC. This pin correctly receives the negative signal after AC coupling for common mode filtering. | | 4 | OUT2 | USB3_TX0N_C | ✅ | OUT2 is connected to USB3_TX0N_C, the filtered negative SuperSpeed transmit signal going to the connector. The polarity mapping (IN2→OUT2 for negative) is correct for a common mode choke. | | 6 | OUT1 | USB3_TX0P_C | ✅ | OUT1 is connected to USB3_TX0P_C, the filtered positive SuperSpeed transmit signal going to the connector. The polarity mapping (IN1→OUT1 for positive) is correct for a common mode choke. | </details> <details> <summary><b>CHOKE1</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_RX0N_C | ✅ | IN1 is connected to USB3_RX0N_C, the negative SuperSpeed receive signal from the USB connector. This pin correctly receives the negative signal from the connector side for common mode filtering. | | 3 | IN2 | USB3_RX0P_C | ✅ | IN2 is connected to USB3_RX0P_C, the positive SuperSpeed receive signal from the USB connector. This pin correctly receives the positive signal from the connector side for common mode filtering. | | 4 | OUT2 | USB3_RXP0 | ✅ | OUT2 is connected to USB3_RXP0, the filtered positive SuperSpeed receive signal going to the SOC. The polarity mapping (IN2→OUT2 for positive) is correct for a common mode choke. | | 6 | OUT1 | USB3_RXN0 | ✅ | OUT1 is connected to USB3_RXN0, the filtered negative SuperSpeed receive signal going to the SOC. The polarity mapping (IN1→OUT1 for negative) is correct for a common mode choke. | </details> <details> <summary><b>CHOKE4</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN0 | ✅ | IN1 is connected to USB_DN0, which is the D- signal from the SOC for USB port 0. This pin correctly receives the negative differential signal of the USB 2.0 data pair. | | 3 | IN2 | USB_DP0 | ✅ | IN2 is connected to USB_DP0, which is the D+ signal from the SOC for USB port 0. This pin correctly receives the positive differential signal of the USB 2.0 data pair. | | 4 | OUT2 | USB_H0 | ✅ | OUT2 is connected to USB_H0, which routes to the D+ pin of USB connector port A and ESD protection device U9. This pin correctly outputs the positive differential signal. | | 6 | OUT1 | USB_L0 | ✅ | OUT1 is connected to USB_L0, which routes to the D- pin of USB connector port A and ESD protection device U9. This pin correctly outputs the negative differential signal. | </details> <details> <summary><b>CHOKE3</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN1 | ✅ | IN1 is connected to USB_DN1, which is the D- signal from the SOC for USB port 1. This pin correctly receives the negative differential signal of the USB 2.0 data pair. | | 3 | IN2 | USB_DP1 | ✅ | IN2 is connected to USB_DP1, which is the D+ signal from the SOC for USB port 1. This pin correctly receives the positive differential signal of the USB 2.0 data pair. | | 4 | OUT2 | USB_H1 | ✅ | OUT2 is connected to USB_H1, which routes to the D+ pin of USB connector port B and ESD protection device U8. This pin correctly outputs the positive differential signal. | | 6 | OUT1 | USB_L1 | ✅ | OUT1 is connected to USB_L1, which routes to the D- pin of USB connector port B and ESD protection device U8. This pin correctly outputs the negative differential signal. | </details> <details> <summary><b>J10</b> - 158-0004534 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/158-0004534) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 57 | 57 | XDP_H_TDO | ❌ | <details><summary>XDP test data out signal with unusual 51 ohm connection to +V1P8A power rail. This configuration is highly atypical for a JTAG TDO signal and likely incorrect.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="3a073003e5413b0412d7" diff-visibility="full" variant="default" view-coords="42.16,50.37,49.66,57.87" aspect-ratio="1.29" } <ul><li>Pin 57 is connected to net XDP_H_TDO <em>(from schematic)</em></li><li>Resistor R21 (51 ohm, part 110-0002078) connects between +V1P8A and XDP_H_TDO <em>(from schematic)</em></li><li>XDP_H_TDO is the test data output signal for the XDP/JTAG debug interface <em>(reasoning)</em></li><li>TDO is typically an output signal from the device under test and is driven by the target device being debugged <em>(reasoning)</em></li><li>A 51 ohm resistor to power rail acts as a pull-up, but this value is extremely low compared to typical pull-up resistors which range from 1K to 10K ohms <em>(reasoning)</em></li><li>When TDO is driven low by the target device, this 51 ohm pull-up would draw approximately 35mA (1.8V / 51Ω), which is unusually high current for a logic signal and could exceed the drive capability of typical JTAG outputs <em>(reasoning)</em></li><li>If series termination is intended for signal integrity, the resistor should be placed in series with the signal path (between the driver and load), not connected to the power rail <em>(reasoning)</em></li><li>Other XDP/JTAG signals on the connector (TDI on pin 58, TMS on pin 56, TCK on pin 54, TRST on pin 52) do not show similar resistor connections to power, making this connection inconsistent with the rest of the debug interface design <em>(from schematic)</em></li><li>Standard JTAG interface design does not typically require strong pull-ups on TDO outputs, as the signal is actively driven by the target device <em>(reasoning)</em></li><li>This connection should be reviewed and verified against the system debug interface requirements, as it appears to be either a design error or an undocumented special requirement <em>(reasoning)</em></li></ul></details> | | 1 | 1 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 2 | 2 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 13 | 13 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 14 | 14 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 25 | 25 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 26 | 26 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 37 | 37 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 38 | 38 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 49 | 49 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 50 | 50 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 59 | 59 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 60 | 60 | GND | ✅ | Ground pins providing multiple ground connections for the expansion connector. Multiple ground pins reduce inductance and improve signal integrity for high-speed signals. | | 3 | 3 | mSATA_TX_P | ✅ | mSATA differential transmit pair (TX_P and TX_N) for SATA interface on the expansion connector. | | 5 | 5 | mSATA_TX_N | ✅ | mSATA differential transmit pair (TX_P and TX_N) for SATA interface on the expansion connector. | | 4 | 4 | mSATA_RX_P | ✅ | mSATA differential receive pair (RX_P and RX_N) for SATA interface on the expansion connector. | | 6 | 6 | mSATA_RX_N | ✅ | mSATA differential receive pair (RX_P and RX_N) for SATA interface on the expansion connector. | | 7 | 7 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 8 | 8 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 19 | 19 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 20 | 20 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 31 | 31 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 32 | 32 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 43 | 43 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 44 | 44 | +5VSB | ✅ | 5V standby power supply pins providing multiple power connections for the expansion connector. Multiple power pins reduce inductance and voltage drop. | | 9 | 9 | mPCIE_REFCLK_P | ✅ | mPCIE differential reference clock pair (REFCLK_P and REFCLK_N) for PCIe interface on the expansion connector. | | 11 | 11 | mPCIE_REFCLK_N | ✅ | mPCIE differential reference clock pair (REFCLK_P and REFCLK_N) for PCIe interface on the expansion connector. | | 10 | 10 | USB_HOST_DP | ✅ | USB host differential data pair (DP and DN) for USB interface on the expansion connector. | | 12 | 12 | USB_HOST_DN | ✅ | USB host differential data pair (DP and DN) for USB interface on the expansion connector. | | 15 | 15 | mPCIE_TX_P | ✅ | mPCIE differential transmit pair (TX_P and TX_N) for PCIe interface on the expansion connector. | | 17 | 17 | mPCIE_TX_N | ✅ | mPCIE differential transmit pair (TX_P and TX_N) for PCIe interface on the expansion connector. | | 16 | 16 | mPCIE_RX_N | ✅ | mPCIE differential receive pair (RX_N and RX_P) for PCIe interface. Note that the polarity appears inverted (pin 16 is RX_N, pin 18 is RX_P), which is explicitly documented as intentional for routing purposes. | | 18 | 18 | mPCIE_RX_P | ✅ | mPCIE differential receive pair (RX_N and RX_P) for PCIe interface. Note that the polarity appears inverted (pin 16 is RX_N, pin 18 is RX_P), which is explicitly documented as intentional for routing purposes. | | 21 | 21 | I2C6_SCL | ✅ | I2C clock signal (SCL) with 10K pullup resistor to +V1P8S for I2C interface on the expansion connector. | | 22 | 22 | mPCIE_WAKEB | ✅ | mPCIE wake signal (active low) for PCIe power management on the expansion connector. | | 23 | 23 | I2C6_SDA | ✅ | I2C data signal (SDA) with 10K pullup resistor to +V1P8S for I2C interface on the expansion connector. | | 24 | 24 | mPCIe_CLKREQ3_B | ✅ | mPCIE clock request signal (active low) for PCIe power management on the expansion connector. | | 27 | 27 | EXP_GPIO1 | ✅ | General purpose I/O expansion pins for the expansion connector. | | 28 | 28 | EXP_GPIO3 | ✅ | General purpose I/O expansion pins for the expansion connector. | | 29 | 29 | EXP_GPIO2 | ✅ | General purpose I/O expansion pins for the expansion connector. | | 30 | 30 | EXP_GPIO4 | ✅ | General purpose I/O expansion pins for the expansion connector. | | 33 | 33 | XDP_H_OBSDATA_A1 | ✅ | XDP observation data bus signals (4-bit) for debug interface on the expansion connector. | | 34 | 34 | XDP_H_OBSDATA_A0 | ✅ | XDP observation data bus signals (4-bit) for debug interface on the expansion connector. | | 35 | 35 | XDP_H_OBSDATA_A2 | ✅ | XDP observation data bus signals (4-bit) for debug interface on the expansion connector. | | 36 | 36 | XDP_H_OBSDATA_A3 | ✅ | XDP observation data bus signals (4-bit) for debug interface on the expansion connector. | | 39 | 39 | XDP_H_PRDYB | ✅ | XDP ready signal (active low) for debug interface handshaking on the expansion connector. | | 40 | 40 | XDP_H_PREQB_PB | ✅ | XDP request signal (active low, push-button) buffered through U1 with 200 ohm pullup to +V1P8A for debug interface on the expansion connector. | | 41 | 41 | HOOK0 | ✅ | HOOK0 debug signal connected through 1K resistor to PMC_RSMRST for test/debug access on the expansion connector. | | 42 | 42 | HOOK1 | ✅ | HOOK1 debug signal connected through 0 ohm resistor to FP_PWRBTN for test/debug access on the expansion connector. | | 45 | 45 | HOOK2 | ✅ | HOOK2 debug signal connected through 1K resistor to PMC_CORE_PWROK for test/debug access on the expansion connector. | | 46 | 46 | PMC_RSTBTN | ✅ | PMC reset button signal with 1K pullup to +V1P8S and 0.1uF filter capacitor for the expansion connector. | | 47 | 47 | HOOK6 | ✅ | HOOK6 debug signal connected through 1K resistor to PMC_PLTRST_R_V1P8 for test/debug access on the expansion connector. | | 48 | 48 | ILB_RTC_TESTB | ✅ | ILB RTC test signal (active low) with 1K pullup to +RTCVCC and 1uF filter capacitor for the expansion connector. | | 51 | 51 | HOOK4 | ✅ | HOOK4 debug signal connected through 0 ohm resistor to +3VSB for test/debug access on the expansion connector. | | 52 | 52 | XDP_H_TRSTB | ✅ | XDP test reset signal (active low) for JTAG/debug interface on the expansion connector. | | 53 | 53 | HOOK5 | ✅ | HOOK5 debug signal connected through 0 ohm resistor to +V1P8S for test/debug access on the expansion connector. | | 54 | 54 | XDP_H_TCK | ✅ | XDP test clock signal for JTAG/debug interface on the expansion connector. | | 55 | 55 | +V1P8A | ✅ | 1.8V analog power supply pin for the expansion connector with 0.1uF decoupling capacitor. | | 56 | 56 | XDP_H_TMS | ✅ | XDP test mode select signal for JTAG/debug interface on the expansion connector. | | 58 | 58 | XDP_H_TDI | ✅ | XDP test data in signal for JTAG/debug interface on the expansion connector. | </details> <details> <summary><b>C5</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing ground reference for bypass capacitor. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A, providing bypass capacitance for U1 power supply. | </details> <details> <summary><b>U1</b> - SN74AUP1G34 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](http://www.ti.com/lit/gpn/SN74AUP1G34) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/SN74AUP1G34) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | No Connect pin, correctly left unconnected. | | 2 | A | XDP_H_PREQB_PB | ✅ | Input pin A connected to XDP_H_PREQB_PB with 200 ohm pull-up resistor to +V1P8A. | | 3 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 4 | Y | XDP_H_PREQB | ✅ | Output pin Y correctly connected to XDP_H_PREQB net. | | 5 | VCC | +V1P8A | ✅ | VCC power pin correctly connected to +V1P8A with appropriate bypass capacitor C5. | </details> <details> <summary><b>R3</b> - 200 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XDP_H_PREQB_PB | ✅ | Connected to XDP_H_PREQB_PB, providing pull-up for buffer input. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A power rail, providing pull-up voltage reference. | </details> <details> <summary><b>R13</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SCL | ✅ | Connected to I2C6_SCL signal line, providing pull-up path to +V1P8S through the 10K resistor. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing the pull-up voltage for the I2C6_SCL line. | </details> <details> <summary><b>R14</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SDA | ✅ | Connected to I2C6_SDA signal line, providing pull-up path to +V1P8S through the 10K resistor. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing the pull-up voltage for the I2C6_SDA line. | </details> <details> <summary><b>R15</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSMRST | ✅ | 1K series resistor connecting PMC_RSMRST signal to HOOK0 pin on expansion connector J10 pin 41. Provides signal protection and current limiting for the expansion interface. | | 2 | 2 | HOOK0 | ✅ | 1K series resistor connecting PMC_RSMRST signal to HOOK0 pin on expansion connector J10 pin 41. Provides signal protection and current limiting for the expansion interface. | </details> <details> <summary><b>R16</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_CORE_PWROK | ✅ | 1K series resistor connecting PMC_CORE_PWROK signal to HOOK2 pin on expansion connector J10 pin 45. Provides signal protection and current limiting for the expansion interface. | | 2 | 2 | HOOK2 | ✅ | 1K series resistor connecting PMC_CORE_PWROK signal to HOOK2 pin on expansion connector J10 pin 45. Provides signal protection and current limiting for the expansion interface. | </details> <details> <summary><b>R17</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PLTRST_R_V1P8 | ✅ | 1K series resistor connecting PMC_PLTRST_R_V1P8 signal to HOOK6 pin on expansion connector J10 pin 47. Provides signal protection and current limiting for the expansion interface. | | 2 | 2 | HOOK6 | ✅ | 1K series resistor connecting PMC_PLTRST_R_V1P8 signal to HOOK6 pin on expansion connector J10 pin 47. Provides signal protection and current limiting for the expansion interface. | </details> <details> <summary><b>R18</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB | ✅ | 0 ohm jumper connecting +3VSB power supply to HOOK4 pin on expansion connector J10 pin 51. Allows power distribution to expansion connector with option to disconnect if needed. | | 2 | 2 | HOOK4 | ✅ | 0 ohm jumper connecting +3VSB power supply to HOOK4 pin on expansion connector J10 pin 51. Allows power distribution to expansion connector with option to disconnect if needed. | </details> <details> <summary><b>R20</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 0 ohm jumper connecting +V1P8S power supply to HOOK5 pin on expansion connector J10 pin 53. Allows power distribution to expansion connector with option to disconnect if needed. | | 2 | 2 | HOOK5 | ✅ | 0 ohm jumper connecting +V1P8S power supply to HOOK5 pin on expansion connector J10 pin 53. Allows power distribution to expansion connector with option to disconnect if needed. | </details> <details> <summary><b>R21</b> - 110-0002078 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002078) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ❌ | <details><summary>R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="3a073003e5413b0412d7" diff-visibility="full" variant="default" view-coords="33.07,50.37,40.57,57.87" aspect-ratio="1.29" } <ul><li>Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail <em>(from schematic)</em></li><li>Pin 2 of R21 is connected to the XDP_H_TDO net <em>(from schematic)</em></li><li>XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface <em>(from schematic)</em></li><li>R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package <em>(from schematic)</em></li><li>The resistor is configured as a pull-up resistor from the signal line to the power rail <em>(reasoning)</em></li><li>TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test <em>(reasoning)</em></li><li>When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA <em>(reasoning)</em></li><li>35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device <em>(reasoning)</em></li><li>Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption <em>(reasoning)</em></li><li>Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value <em>(reasoning)</em></li><li>No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value <em>(from schematic)</em></li><li>The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application <em>(reasoning)</em></li><li>While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values <em>(reasoning)</em></li><li>The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value <em>(reasoning)</em></li></ul></details> | | 2 | 2 | XDP_H_TDO | ❌ | <details><summary>R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="3a073003e5413b0412d7" diff-visibility="full" variant="default" view-coords="34.44,50.37,41.94,57.87" aspect-ratio="1.29" } <ul><li>Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail <em>(from schematic)</em></li><li>Pin 2 of R21 is connected to the XDP_H_TDO net <em>(from schematic)</em></li><li>XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface <em>(from schematic)</em></li><li>R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package <em>(from schematic)</em></li><li>The resistor is configured as a pull-up resistor from the signal line to the power rail <em>(reasoning)</em></li><li>TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test <em>(reasoning)</em></li><li>When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA <em>(reasoning)</em></li><li>35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device <em>(reasoning)</em></li><li>Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption <em>(reasoning)</em></li><li>Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value <em>(reasoning)</em></li><li>No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value <em>(from schematic)</em></li><li>The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application <em>(reasoning)</em></li><li>While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values <em>(reasoning)</em></li><li>The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>U42</b> - WGI210AT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4300-0071) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | LAN_PWR_GOOD | $18N3538 | ✅ | LAN_PWR_GOOD is pulled up to +3VSB_LAN through a 10K resistor, indicating this is a power good output signal. | | 2 | NC_SI_CLK_IN | $18N3372 | ✅ | NC_SI_CLK_IN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal. | | 3 | NC_SI_CRS_DV | $18N3374 | ✅ | NC_SI_CRS_DV is terminated to ground through a 1K resistor, which is appropriate for an unused input signal. | | 4 | JTAG_TDO | | ✅ | JTAG_TDO is left unconnected, which is acceptable for a JTAG output pin when JTAG is not being used. | | 5 | NC_SI_RXD1 | $18N3305 | ✅ | NC_SI_RXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 6 | NC_SI_RXD0 | $18N3303 | ✅ | NC_SI_RXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 7 | NC_SI_TX_EN | $18N3376 | ✅ | NC_SI_TX_EN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal. | | 8 | NC_SI_TXD1 | $18N3301 | ✅ | NC_SI_TXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 9 | NC_SI_TXD0 | $18N3299 | ✅ | NC_SI_TXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 10 | VDD3P3_10 | +3VSB_LAN | ✅ | VDD3P3_10 is correctly connected to the +3VSB_LAN power rail. | | 11 | VDD0P9_11 | +0V9_LAN | ✅ | VDD0P9_11 is correctly connected to the +0V9_LAN power rail. | | 12 | NVM_SI | $18N2399 | ✅ | NVM_SI is correctly connected to the SPI flash MOSI line through a 33.2 ohm series resistor for signal integrity. | | 13 | NVM_SK | $18N2397 | ✅ | NVM_SK is correctly connected to the SPI flash clock line through a 33.2 ohm series resistor for signal integrity. | | 14 | NVM_SO | $18N3554 | ✅ | NVM_SO is correctly connected to the SPI flash MISO line through a 33.2 ohm series resistor for signal integrity. | | 15 | NVM_CS_N | $18N2395 | ✅ | NVM_CS_N is correctly connected to the SPI flash chip select line through a 33.2 ohm series resistor for signal integrity. | | 16 | PE_WAKE_N | PMC_PCIE_WAKE | ✅ | PE_WAKE_N is connected to the PCIe wake signal going to the system controller. | | 17 | PE_RST_N | PMC_PLTRST_L | ✅ | PE_RST_N is connected to the platform reset signal from the system controller. | | 18 | JTAG_TMS | $18N3293 | ✅ | JTAG_TMS is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces. | | 19 | JTAG_CLK | $18N3295 | ✅ | JTAG_CLK is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces. | | 20 | PE_TXN | PCIE_C_RXP2 | ✅ | PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 21 | PE_TXP | PCIE_C_RXN2 | ✅ | PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 22 | NC/INTVCC | | ✅ | NC/INTVCC is left unconnected, which is acceptable as this pin can be either not connected or used for internal VCC depending on configuration. | | 23 | PE_RXN | PCIE_C_TXP2 | ✅ | PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 24 | PE_RXP | PCIE_C_TXN2 | ✅ | PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 25 | PECLK_N | PCIE_CLK-N2 | ✅ | PECLK_N is correctly connected to the PCIe reference clock negative signal. | | 26 | PECLK_P | PCIE_CLK-P2 | ✅ | PECLK_P is correctly connected to the PCIe reference clock positive signal. | | 27 | VDD3P3_27 | +3VSB_LAN | ✅ | VDD3P3_27 is correctly connected to the +3VSB_LAN power rail. | | 28 | DEV_OFF_N | $18N3540 | ✅ | DEV_OFF_N is pulled up to +3VSB_LAN through a 10K resistor, keeping the device enabled by default. | | 29 | JTAG_TDI | $18N3297 | ✅ | JTAG_TDI is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces. | | 30 | LED1 | LAN-LED1 | ✅ | LED1 is connected to an off-page signal for LED control. | | 31 | LED0 | LAN-LED0 | ✅ | LED0 is correctly connected to the RJ45 connector LED with appropriate filtering. | | 32 | VDD0P9_32 | +0V9_LAN | ✅ | VDD0P9_32 is correctly connected to the +0V9_LAN power rail. | | 33 | LED2 | LAN-LED2 | ✅ | LED2 is correctly connected to the RJ45 connector LED through a current limiting resistor. | | 34 | SMB_CLK | LAN-SMB-CLK | ✅ | SMB_CLK is connected to an off-page SMBus clock signal. | | 35 | SMB_ALRT_N | LAN-SMB-ALERT# | ✅ | SMB_ALRT_N is connected to an off-page SMBus alert signal. | | 36 | SMB_DATA | LAN-SMB-DATA | ✅ | SMB_DATA is connected to an off-page SMBus data signal. | | 37 | CBOT | $18N2590 | ✅ | CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators. | | 40 | CTOP | $18N2588 | ✅ | CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators. | | 38 | VDD0P9_OUT | +0V9_LAN | ✅ | VDD0P9_OUT is connected to the +0V9_LAN rail, indicating the internal 0.9V regulator output is being used. | | 39 | VDD1P5_OUT | +1V5_LAN | ✅ | VDD1P5_OUT is connected to the +1V5_LAN rail, indicating the internal 1.5V regulator output is being used. | | 41 | VDD3P3_41 | +3VSB_LAN | ✅ | VDD3P3_41 is correctly connected to the +3VSB_LAN power rail. | | 42 | VDD0P9_42 | +0V9_LAN | ✅ | VDD0P9_42 is correctly connected to the +0V9_LAN power rail. | | 43 | NC_SI_ARB_IN | | ✅ | NC_SI_ARB_IN is left unconnected, which is acceptable for an unused signal. | | 44 | NC_SI_ARB_OUT | | ✅ | NC_SI_ARB_OUT is left unconnected, which is acceptable for an unused output signal. | | 45 | XTAL2 | LAN_XTAL2 | ✅ | XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors. | | 46 | XTAL1 | LAN_XTAL1 | ✅ | XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors. | | 47 | VDD1P5_47 | +1V5_LAN | ✅ | VDD1P5_47 is correctly connected to the +1V5_LAN power rail. | | 48 | RSET | LAN_RSET | ✅ | RSET is correctly connected to ground through a 4.99K resistor to set the PHY reference current. | | 49 | MDI_MINUS3/SER_N | MDI_N3 | ✅ | MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3. | | 50 | MDI_PLUS3/SER_P | MDI_P3 | ✅ | MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3. | | 51 | VDD3P3_51 | +3VSB_LAN | ✅ | VDD3P3_51 is correctly connected to the +3VSB_LAN power rail. | | 52 | MDI_MINUS2/SET_N | MDI_N2 | ✅ | MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2. | | 53 | MDI_PLUS2 | MDI_P2 | ✅ | MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2. | | 54 | MDI_MINUS1/SRDS_SIG_DET | MDI_N1 | ✅ | MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1. | | 55 | MDI_PLUS1/SFP_I2C_CLK | MDI_P1 | ✅ | MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1. | | 56 | VDD1P5_56 | +1V5_LAN | ✅ | VDD1P5_56 is correctly connected to the +1V5_LAN power rail. | | 57 | MDI_MINUS0/SFP_I2C_DATA | MDI_N0 | ✅ | MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0. | | 58 | MDI_PLUS0/NC | MDI_P0 | ✅ | MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0. | | 59 | VDD0P9_59 | +0V9_LAN | ✅ | VDD0P9_59 is correctly connected to the +0V9_LAN power rail. | | 60 | SDP3 | | ✅ | SDP3 is left unconnected, which is acceptable for an unused software-defined pin. | | 61 | SDP1/PCIE_DIS | | ✅ | SDP1/PCIE_DIS is left unconnected, which is acceptable for an unused software-defined pin. | | 62 | SDP2 | | ✅ | SDP2 is left unconnected, which is acceptable for an unused software-defined pin. | | 63 | SDP0 | | ✅ | SDP0 is left unconnected, which is acceptable for an unused software-defined pin. | | 64 | VDD3P3_64 | +3VSB_LAN | ✅ | VDD3P3_64 is correctly connected to the +3VSB_LAN power rail. | | 65 | GND_PAD | GND | ✅ | GND_PAD is correctly connected to the ground plane. | </details> <details> <summary><b>U43</b> - 4356-0082 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25df081a-datasheet?language=en) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4356-0082) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | $18N2439 | ✅ | CS# (Chip Select) is correctly connected through series resistor R835 (33.2Ω) to the LAN controller U42 pin 15 (NVM_CS_N). | | 2 | SO | $18N3552 | ✅ | SO (Serial Output) is correctly connected through series resistor R833 (33.2Ω) to the LAN controller U42 pin 14 (NVM_SO). | | 3 | WP# | $18N3609 | ✅ | WP# (Write Protect) is correctly pulled high through R830 (10KΩ) to +3VSB_LAN, disabling hardware write protection as recommended by the datasheet. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 5 | SI | $18N2435 | ✅ | SI (Serial Input) is correctly connected through series resistor R832 (33.2Ω) to the LAN controller U42 pin 12 (NVM_SI). A weak pull-up R848 (33.2KΩ) to +3VSB_LAN ensures a defined state. | | 6 | SCK | $18N2437 | ✅ | SCK (Serial Clock) is correctly connected through series resistor R834 (33.2Ω) to the LAN controller U42 pin 13 (NVM_SK). | | 7 | HOLD# | $18N3659 | ✅ | HOLD# is correctly pulled high through R831 (10KΩ) to +3VSB_LAN, keeping the hold function inactive as recommended by the datasheet. | | 8 | VCC | +3VSB_LAN | ✅ | VCC is correctly connected to +3VSB_LAN, which provides 3.3V power within the specified 2.7V to 3.6V operating range. | </details> <details> <summary><b>R832</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2435 | ✅ | Series resistor on SI (MOSI) line between LAN controller and flash memory, correctly placed for signal integrity. | </details> <details> <summary><b>R833</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3554 | ✅ | Series resistor on SO (MISO) line between flash memory and LAN controller, correctly placed for signal integrity. | </details> <details> <summary><b>R834</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2437 | ✅ | Series resistor on SCK (clock) line between LAN controller and flash memory, correctly placed for signal integrity. | </details> <details> <summary><b>R835</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2439 | ✅ | Series resistor on CS# (chip select) line between LAN controller and flash memory, correctly placed for signal integrity. | </details> <details> <summary><b>R829</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3609 | ✅ | DNI pull-down resistor on WP# that would enable hardware write protection if installed. Correctly marked DNI to allow software-controlled write protection. | | 2 | 2 | GND | ✅ | DNI pull-down resistor on WP# that would enable hardware write protection if installed. Correctly marked DNI to allow software-controlled write protection. | </details> <details> <summary><b>R830</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor on WP# that correctly implements the datasheet recommendation to connect WP to VCC. | | 2 | 2 | $18N3609 | ✅ | Pull-up resistor on WP# that correctly implements the datasheet recommendation to connect WP to VCC. | </details> <details> <summary><b>R831</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor on HOLD# that correctly implements the datasheet recommendation to connect HOLD to VCC. | | 2 | 2 | $18N3659 | ✅ | Pull-up resistor on HOLD# that correctly implements the datasheet recommendation to connect HOLD to VCC. | </details> <details> <summary><b>R848</b> - 1120-0359 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0359) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Weak pull-up resistor on SI line that prevents floating when not driven by the controller. | | 2 | 2 | $18N2435 | ✅ | Weak pull-up resistor on SI line that prevents floating when not driven by the controller. | </details> <details> <summary><b>R847</b> - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0032) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2435 | ✅ | DNI pull-down resistor on SI that is correctly not installed, as it would create a problematic voltage divider with R848. | | 2 | 2 | GND | ✅ | DNI pull-down resistor on SI that is correctly not installed, as it would create a problematic voltage divider with R848. | </details> <details> <summary><b>C253</b> - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Load capacitor connected to LAN_XTAL2 net, providing the required load capacitance for the crystal oscillator circuit. | | 2 | 2 | GND | ✅ | Ground connection for the load capacitor, correctly connected to GND. | </details> <details> <summary><b>C252</b> - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL1 | ✅ | Load capacitor connected to LAN_XTAL1 net, providing the required load capacitance for the crystal oscillator circuit. | | 2 | 2 | GND | ✅ | Ground connection for the load capacitor, correctly connected to GND. | </details> <details> <summary><b>X1</b> - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Crystal pin connected to XTAL2 of U42 through LAN_XTAL2 net with 27pF load capacitor C253 to ground. This is one of the two active crystal oscillator pins. | | 2 | 2 | GND | ✅ | Ground pin of the crystal package, correctly connected to GND for proper operation and EMI reduction. | | 3 | 3 | LAN_XTAL1 | ✅ | Crystal pin connected to XTAL1 of U42 through LAN_XTAL1 net with 27pF load capacitor C252 to ground. This is the second active crystal oscillator pin. | | 4 | 4 | GND | ✅ | Ground pin of the crystal package, correctly connected to GND for proper operation and EMI reduction. | </details> <details> <summary><b>R843</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED1 | ✅ | Current-limiting resistor for LED1 circuit in the RJ45 connector, providing approximately 4.3mA LED current. | | 2 | 2 | LINK-LED-N | ✅ | Current-limiting resistor for LED1 circuit in the RJ45 connector, providing approximately 4.3mA LED current. | </details> <details> <summary><b>R844</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED2 | ✅ | Current-limiting resistor for LED2 circuit in the RJ45 connector, providing approximately 4.3mA LED current. | | 2 | 2 | 1G-LED-N | ✅ | Current-limiting resistor for LED2 circuit in the RJ45 connector, providing approximately 4.3mA LED current. | </details> <details> <summary><b>C429</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LINK-LED-N | ✅ | EMI filtering capacitor on LINK-LED-N signal to reduce high-frequency noise emissions. | | 2 | 2 | GND | ✅ | EMI filtering capacitor on LINK-LED-N signal to reduce high-frequency noise emissions. | </details> <details> <summary><b>C430</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1G-LED-N | ✅ | EMI filtering capacitor on 1G-LED-N signal to reduce high-frequency noise emissions. | | 2 | 2 | GND | ✅ | EMI filtering capacitor on 1G-LED-N signal to reduce high-frequency noise emissions. | </details> <details> <summary><b>C431</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED0 | ✅ | EMI filtering capacitor on LAN-LED0 signal to reduce high-frequency noise emissions. | | 2 | 2 | GND | ✅ | EMI filtering capacitor on LAN-LED0 signal to reduce high-frequency noise emissions. | </details> <details> <summary><b>C426</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression. | | 2 | 2 | GND | ✅ | Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression. | </details> <details> <summary><b>C427</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression. | | 2 | 2 | GND | ✅ | Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, part of parallel combination for broadband noise suppression. | </details> <details> <summary><b>C428</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, providing low-frequency filtering in parallel combination. | | 2 | 2 | GND | ✅ | Center tap decoupling capacitor for Ethernet magnetics common-mode filtering, providing low-frequency filtering in parallel combination. | </details> <details> <summary><b>J11</b> - RJ45 W XFMR GRN-ORN GRN LEDS ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3362-0042) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | MD1+ | MDI_P0 | ✅ | MD1+ connects to MDI_P0, the positive differential signal of MDI pair 0 to the LAN controller U42 pin 58. | | 2 | MD1- | MDI_N0 | ✅ | MD1- connects to MDI_N0, the negative differential signal of MDI pair 0 to the LAN controller U42 pin 57. | | 3 | MD2+ | MDI_P1 | ✅ | MD2+ connects to MDI_P1, the positive differential signal of MDI pair 1 to the LAN controller U42 pin 55. | | 4 | MD2- | MDI_N1 | ✅ | MD2- connects to MDI_N1, the negative differential signal of MDI pair 1 to the LAN controller U42 pin 54. | | 5 | CT1 | $18N3856 | ✅ | CT1 is the first center tap connection, properly bypassed to GND through parallel capacitors C426, C427, and C428. | | 6 | CT2 | $18N3856 | ✅ | CT2 is the second center tap connection, properly bypassed to GND through the same parallel capacitors as CT1. | | 7 | MD3+ | MDI_P2 | ✅ | MD3+ connects to MDI_P2, the positive differential signal of MDI pair 2 to the LAN controller U42 pin 53. | | 8 | MD3- | MDI_N2 | ✅ | MD3- connects to MDI_N2, the negative differential signal of MDI pair 2 to the LAN controller U42 pin 52. | | 9 | MD4+ | MDI_P3 | ✅ | MD4+ connects to MDI_P3, the positive differential signal of MDI pair 3 to the LAN controller U42 pin 50. | | 10 | MD4- | MDI_N3 | ✅ | MD4- connects to MDI_N3, the negative differential signal of MDI pair 3 to the LAN controller U42 pin 49. | | 11 | LED2_AC1 | LAN-LED0 | ✅ | LED2_AC1 connects to LAN-LED0 from U42 pin 31, forming one terminal of a bi-color LED with proper EMI filtering via C431. | | 12 | LED2_AD1 | 1G-LED-N | ✅ | LED2_AD1 connects through R844 to LAN-LED2 from U42 pin 33, forming the other terminal of the bi-color LED with proper current limiting and EMI filtering. | | 13 | LED1_C | LINK-LED-N | ✅ | LED1_C is the cathode of LED1, connecting through R843 to U42 pin 30 with proper current limiting and EMI filtering. | | 14 | LED1_A | +3VSB_LAN | ✅ | LED1_A is the anode of LED1, correctly connected to +3VSB_LAN to provide power for the LED. | | 15 | SHLD1 | GND_EARTH | ✅ | SHLD1 is correctly connected to GND_EARTH for proper shield grounding and EMI/ESD protection. | | 16 | SHLD2 | GND_EARTH | ✅ | SHLD2 is correctly connected to GND_EARTH for proper shield grounding and EMI/ESD protection. | </details> <details> <summary><b>C425</b> - 2221-0017 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0017) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2588 | ✅ | Connected to CTOP pin of U42 LAN controller. This capacitor is part of the internal voltage regulator charge pump circuit. | | 2 | 2 | $18N2590 | ✅ | Connected to CBOT pin of U42 LAN controller, completing the charge pump capacitor connection. | </details> <details> <summary><b>FB12</b> - 3044-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3044-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB | ✅ | Input pin connected to main +3VSB standby power rail. This ferrite bead filters the power supply to the LAN subsystem. | | 2 | 2 | +3VSB_LAN | ✅ | Output pin connected to +3VSB_LAN rail that powers the LAN controller and associated circuitry. | </details> <details> <summary><b>C233</b> - 123-0004408 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0004408) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to the main circuit ground (GND). This is correct for a Y-capacitor application providing coupling between circuit ground and chassis ground. | | 2 | 2 | GND_EARTH | ✅ | Pin 2 connects to chassis/earth ground (GND_EARTH). This is correct for a Y-capacitor application providing coupling between circuit ground and chassis ground. | </details> <details> <summary><b>U15</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin connected to +V1P8S (1.8V supply). This provides the reference voltage for the A-side (lower voltage) of the translator. | | 2 | A1 | SIO_UART1_RTSB | ✅ | A1 pin connected to SIO_UART1_RTSB on the 1.8V side. This is the A-side (lower voltage) channel 1, properly paired with B1 for UART RTS flow control. | | 3 | A2 | SIO_UART1_CTSB | ✅ | A2 pin connected to SIO_UART1_CTSB on the 1.8V side. This is the A-side (lower voltage) channel 2, properly paired with B2 for UART CTS flow control. | | 4 | A3 | SIO_UART1_RXD | ✅ | A3 pin connected to SIO_UART1_RXD on the 1.8V side. This is the A-side (lower voltage) channel 3, properly paired with B3 for UART receive data. | | 5 | A4 | SIO_UART1_TXD | ✅ | A4 pin connected to SIO_UART1_TXD on the 1.8V side. This is the A-side (lower voltage) channel 4, properly paired with B4 for UART transmit data. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 7 | B4 | UART1_TXD | ✅ | B4 pin connected to UART1_TXD on the 3.3V side. This is the B-side (higher voltage) channel 4, properly paired with A4 for UART transmit data. | | 8 | B3 | UART1_RXD | ✅ | B3 pin connected to UART1_RXD on the 3.3V side. This is the B-side (higher voltage) channel 3, properly paired with A3 for UART receive data. | | 9 | B2 | UART1_CTSB | ✅ | B2 pin connected to UART1_CTSB on the 3.3V side. This is the B-side (higher voltage) channel 2, properly paired with A2 for UART CTS flow control. | | 10 | B1 | UART1_RTSB | ✅ | B1 pin connected to UART1_RTSB on the 3.3V side. This is the B-side (higher voltage) channel 1, properly paired with A1 for UART RTS flow control. | | 11 | VCCB | +3VSB | ✅ | VCCB pin connected to +3VSB (3.3V standby supply). This provides the reference voltage for the B-side (higher voltage) of the translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin connected to PMC_PLTRST_R_V1P8, which enables the translator when the platform is out of reset. | </details> <details> <summary><b>U7</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | UART2_RXD | ✅ | B2 pin connected to UART2_RXD on the 3.3V side. This is the B-side (higher voltage) channel 2 of the bidirectional level translator, properly paired with A2. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin connected to +V1P8S (1.8V supply). This provides the reference voltage for the A-side (lower voltage) of the translator. | | 4 | A2 | SIO_UART2_RXD | ✅ | A2 pin connected to SIO_UART2_RXD on the 1.8V side. This is the A-side (lower voltage) channel 2, properly paired with B2. | | 5 | A1 | SIO_UART2_TXD | ✅ | A1 pin connected to SIO_UART2_TXD on the 1.8V side. This is the A-side (lower voltage) channel 1, properly paired with B1. | | 6 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin connected to PMC_PLTRST_R_V1P8, which enables the translator when the platform is out of reset. | | 7 | VCCB | +3VSB | ✅ | VCCB pin connected to +3VSB (3.3V standby supply). This provides the reference voltage for the B-side (higher voltage) of the translator. | | 8 | B1 | UART2_TXD | ✅ | B1 pin connected to UART2_TXD on the 3.3V side. This is the B-side (higher voltage) channel 1, properly paired with A1. | </details> <details> <summary><b>U10</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the 1.8V reference voltage for the A-side of the level translator. | | 2 | A1 | SOC_GPIO_S5_2 | ✅ | A1 is correctly connected to SOC_GPIO_S5_2, which is translated to GPIO_S5_2 on the B-side through B1. | | 3 | A2 | SOC_GPIO_S5_1 | ✅ | A2 is correctly connected to SOC_GPIO_S5_1, which is translated to GPIO_S5_1 on the B-side through B2. | | 4 | A3 | SOC_GPIO_S5_0 | ✅ | A3 is correctly connected to SOC_GPIO_S5_0, which is translated to GPIO_S5_0 on the B-side through B3. | | 5 | A4 | | ✅ | Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators. | | 7 | B4 | GND | ✅ | Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 8 | B3 | GPIO_S5_0 | ✅ | B3 is correctly connected to GPIO_S5_0, which is the 3.3V translation of SOC_GPIO_S5_0 from A3. | | 9 | B2 | GPIO_S5_1 | ✅ | B2 is correctly connected to GPIO_S5_1, which is the 3.3V translation of SOC_GPIO_S5_1 from A2. | | 10 | B1 | GPIO_S5_2 | ✅ | B1 is correctly connected to GPIO_S5_2, which is the 3.3V translation of SOC_GPIO_S5_2 from A1. | | 11 | VCCB | +PS_3VSB | ✅ | VCCB is correctly connected to +PS_3VSB, providing the 3.3V reference voltage for the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, which enables the level translator when the platform is out of reset. | </details> <details> <summary><b>U17</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing the 1.8V reference voltage for the A-side of the level translator. | | 2 | A1 | I2S_MCLK | ✅ | A1 is correctly connected to I2S_MCLK, which is translated to I2SMCLK_GPIO on the B-side through B1. | | 3 | A2 | SOC_PWM1 | ✅ | A2 is correctly connected to SOC_PWM1, which is translated to PWM1 on the B-side through B2. | | 4 | A3 | SOC_PWM0 | ✅ | A3 is correctly connected to SOC_PWM0, which is translated to PWM0 on the B-side through B3. | | 5 | A4 | | ✅ | Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators. | | 7 | B4 | GND | ✅ | Channel 4 is unused with A4 (pin 5) left unconnected and B4 (pin 7) tied to GND. This configuration is consistent with common practices for unused channels in bidirectional level translators. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 8 | B3 | PWM0 | ✅ | B3 is correctly connected to PWM0, which is the 3.3V translation of SOC_PWM0 from A3. | | 9 | B2 | PWM1 | ✅ | B2 is correctly connected to PWM1, which is the 3.3V translation of SOC_PWM1 from A2. | | 10 | B1 | I2SMCLK_GPIO | ✅ | B1 is correctly connected to I2SMCLK_GPIO, which is the 3.3V translation of I2S_MCLK from A1. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing the 3.3V reference voltage for the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, which enables the level translator when the platform is out of reset. | </details> <details> <summary><b>U16</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S (1.8V supply), providing the A-side voltage reference for the level translator. | | 2 | A1 | I2S_DATIN_R | ✅ | A1 is correctly connected to I2S_DATIN_R, which translates to I2SDI_GPIO on the B-side through B1. | | 3 | A2 | I2S_DATOUT_R | ✅ | A2 is correctly connected to I2S_DATOUT_R, which translates to I2SDO_GPIO on the B-side through B2. | | 4 | A3 | I2S_FRM_R | ✅ | A3 is correctly connected to I2S_FRM_R, which translates to I2SFRM_GPIO on the B-side through B3. | | 5 | A4 | I2S_CLK_R | ✅ | A4 is correctly connected to I2S_CLK_R, which translates to I2SCLK_GPIO on the B-side through B4. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | I2SCLK_GPIO | ✅ | B4 is correctly connected to I2SCLK_GPIO, providing the 3.3V side connection for I2S clock that pairs with A4. | | 8 | B3 | I2SFRM_GPIO | ✅ | B3 is correctly connected to I2SFRM_GPIO, providing the 3.3V side connection for I2S frame sync that pairs with A3. | | 9 | B2 | I2SDO_GPIO | ✅ | B2 is correctly connected to I2SDO_GPIO, providing the 3.3V side connection for I2S data out that pairs with A2. | | 10 | B1 | I2SDI_GPIO | ✅ | B1 is correctly connected to I2SDI_GPIO, providing the 3.3V side connection for I2S data in that pairs with A1. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB (3.3V standby supply), providing the B-side voltage reference for the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset. | </details> <details> <summary><b>U18</b> - NTB0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTB0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A (1.8V supply) to provide the reference voltage for the A-side of the level translator. | | 2 | A1 | SOC_SPI_MOSI-R | ✅ | A1 is correctly connected to SOC_SPI_MOSI-R, which is the SPI MOSI signal from the SOC at 1.8V level. | | 3 | A2 | SOC_SPI_CLK-R | ✅ | A2 is correctly connected to SOC_SPI_CLK-R, which is the SPI clock signal from the SOC at 1.8V level. | | 4 | A3 | SOC_SPI_MISO-R | ✅ | A3 is correctly connected to SOC_SPI_MISO-R, which is the SPI MISO signal from the SOC at 1.8V level. | | 5 | A4 | SOC_SPI_CS0B-R | ✅ | A4 is correctly connected to SOC_SPI_CS0B-R, which is the SPI chip select 0 (active low) signal from the SOC at 1.8V level. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SPI_CS0 | ✅ | B4 is correctly connected to SPI_CS0, which is the SPI chip select 0 signal at variable voltage level (currently 3.3V). | | 8 | B3 | SPI_MISO | ✅ | B3 is correctly connected to SPI_MISO, which is the SPI MISO signal at variable voltage level (currently 3.3V). | | 9 | B2 | SPI_CLK | ✅ | B2 is correctly connected to SPI_CLK, which is the SPI clock signal at variable voltage level (currently 3.3V). | | 10 | B1 | SPI_MOSI | ✅ | B1 is correctly connected to SPI_MOSI, which is the SPI MOSI signal at variable voltage level (currently 3.3V). | | 11 | VCCB | +V_SPI | ✅ | VCCB is correctly connected to +V_SPI, which is a variable voltage supply (currently 3.3V) that can be configured as either 1.8V or 3.3V via resistor population options. | | 12 | OE | DDP_IO3L | ✅ | OE is correctly connected to DDP_IO3L with a 100K pull-up to +V1P8A, enabling the level translator by default and allowing the DediProg programmer to disable it when needed. | </details> <details> <summary><b>U14</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S (1.8V supply) to provide the reference voltage for the A-side of the level translator. | | 2 | A1 | SOC_SIO_SPI_CLK | ✅ | A1 is correctly connected to SOC_SIO_SPI_CLK, which is the SPI clock signal from the SOC at 1.8V level. | | 3 | A2 | SOC_SIO_SPI_MOSI | ✅ | A2 is correctly connected to SOC_SIO_SPI_MOSI, which is the SPI MOSI signal from the SOC at 1.8V level. | | 4 | A3 | SOC_SIO_SPI_MISO | ✅ | A3 is correctly connected to SOC_SIO_SPI_MISO, which is the SPI MISO signal from the SOC at 1.8V level. | | 5 | A4 | SOC_SIO_SPI_CS1 | ✅ | A4 is correctly connected to SOC_SIO_SPI_CS1, which is the SPI chip select 1 signal from the SOC at 1.8V level. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SIO_SPI_CS1 | ✅ | B4 is correctly connected to SIO_SPI_CS1, which is the SPI chip select 1 signal at 3.3V level. | | 8 | B3 | SIO_SPI_MISO | ✅ | B3 is correctly connected to SIO_SPI_MISO, which is the SPI MISO signal at 3.3V level. | | 9 | B2 | SIO_SPI_MOSI | ✅ | B2 is correctly connected to SIO_SPI_MOSI, which is the SPI MOSI signal at 3.3V level. | | 10 | B1 | SIO_SPI_CLK | ✅ | B1 is correctly connected to SIO_SPI_CLK, which is the SPI clock signal at 3.3V level. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB (3.3V standby supply) to provide the reference voltage for the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, which is a platform reset signal at 1.8V level that enables the level translator when the platform is out of reset. | </details> <details> <summary><b>U40</b> - PCA9306DCUT ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fpca9306) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/PCA9306DCUT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | SDA2 | GPIO_I2C_SDA | ❌ | <details><summary>SDA2 and SCL2 pins lack required pullup resistors to the high-voltage supply. While external pullups on a board connected to JP1 might be intended, the datasheet explicitly requires pullup resistors for proper I2C operation, and none are visible on this schematic page.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,77.42,31.26,84.92" aspect-ratio="1.29" } <ul><li>Pin 5 (SDA2) is connected to the GPIO_I2C_SDA net <em>(from schematic)</em></li><li>Pin 6 (SCL2) is connected to the GPIO_I2C_SCL net <em>(from schematic)</em></li><li>GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 pins 15 and 13 respectively, which is a 26-pin expansion header (HDR2X13) <em>(from schematic)</em></li><li>No pullup resistors are visible on the GPIO_I2C_SDA or GPIO_I2C_SCL nets on this schematic page <em>(from schematic)</em></li><li>Pin 5 is SDA2, the serial data on the high-voltage side <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</em></li><li>Pin 6 is SCL2, the serial clock on the high-voltage side <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</em></li><li>The datasheet states: &#x27;Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>The datasheet states: &#x27;pullup resistors required to pull SCL2 and SDA2 outputs to VDPU&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>The high-voltage supply (VDPU) should be +3VSB based on the VREF2 connection through R812 (200K resistor) <em>(from schematic)</em></li><li>I2C is an open-drain protocol that requires pullup resistors to function - without them, the bus cannot pull high <em>(reasoning)</em></li><li>While the design might intend for pullups to be provided on an external board connected to JP1, this creates a hard dependency on external hardware and the I2C bus will not function without it <em>(reasoning)</em></li><li>Best practice for I2C interfaces on expansion headers is to include pullups on the main board, possibly with the option to disable them if external pullups are present <em>(reasoning)</em></li><li>Recommendation: Add pullup resistors (typically 2.2K to 10K ohms depending on bus capacitance and speed requirements per I2C specification) from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB, or clearly document that external pullups are required <em>(reasoning)</em></li></ul></details> | | 6 | SCL2 | GPIO_I2C_SCL | ❌ | <details><summary>SDA2 and SCL2 pins lack required pullup resistors to the high-voltage supply. While external pullups on a board connected to JP1 might be intended, the datasheet explicitly requires pullup resistors for proper I2C operation, and none are visible on this schematic page.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.33" aspect-ratio="1.29" } <ul><li>Pin 5 (SDA2) is connected to the GPIO_I2C_SDA net <em>(from schematic)</em></li><li>Pin 6 (SCL2) is connected to the GPIO_I2C_SCL net <em>(from schematic)</em></li><li>GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 pins 15 and 13 respectively, which is a 26-pin expansion header (HDR2X13) <em>(from schematic)</em></li><li>No pullup resistors are visible on the GPIO_I2C_SDA or GPIO_I2C_SCL nets on this schematic page <em>(from schematic)</em></li><li>Pin 5 is SDA2, the serial data on the high-voltage side <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</em></li><li>Pin 6 is SCL2, the serial clock on the high-voltage side <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</em></li><li>The datasheet states: &#x27;Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>The datasheet states: &#x27;pullup resistors required to pull SCL2 and SDA2 outputs to VDPU&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>The high-voltage supply (VDPU) should be +3VSB based on the VREF2 connection through R812 (200K resistor) <em>(from schematic)</em></li><li>I2C is an open-drain protocol that requires pullup resistors to function - without them, the bus cannot pull high <em>(reasoning)</em></li><li>While the design might intend for pullups to be provided on an external board connected to JP1, this creates a hard dependency on external hardware and the I2C bus will not function without it <em>(reasoning)</em></li><li>Best practice for I2C interfaces on expansion headers is to include pullups on the main board, possibly with the option to disable them if external pullups are present <em>(reasoning)</em></li><li>Recommendation: Add pullup resistors (typically 2.2K to 10K ohms depending on bus capacitance and speed requirements per I2C specification) from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB, or clearly document that external pullups are required <em>(reasoning)</em></li></ul></details> | | 1 | GND | GND | ✅ | GND pin correctly connected to system ground. | | 2 | VREF1 | +V1P8S | ✅ | VREF1 pin correctly connected to +V1P8S (1.8V) low-voltage reference supply. | | 3 | SCL1 | I2C5_SCL | ✅ | SCL1 pin correctly connected to I2C5_SCL with appropriate 10K pullup resistor to +V1P8S. | | 4 | SDA1 | I2C5_SDA | ✅ | SDA1 pin correctly connected to I2C5_SDA with appropriate 10K pullup resistor to +V1P8S. | | 7 | VREF2 | $20N1576 | ✅ | VREF2 pin correctly connected through 200K resistor (R812) to +3VSB, establishing the required reference voltage. | | 8 | EN | $20N1576 | ✅ | EN pin correctly tied to VREF2 and pulled up through 200K resistor to +3VSB, enabling the translator. | </details> <details> <summary><b>R818</b> - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | R818 is a 0-ohm jumper correctly marked DNI (Do Not Install) for the 3.3V SPI flash configuration. It would connect the 1.8V supply (+V1P8A) to the flash power network if populated, but is left unpopulated because the installed part W25Q64BVSSIG requires 3.3V operation. | | 2 | 2 | +V1P8A | ✅ | R818 is a 0-ohm jumper correctly marked DNI (Do Not Install) for the 3.3V SPI flash configuration. It would connect the 1.8V supply (+V1P8A) to the flash power network if populated, but is left unpopulated because the installed part W25Q64BVSSIG requires 3.3V operation. | </details> <details> <summary><b>R152</b> - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | R152 is correctly populated to connect +3VSB (3.3V standby supply) to the SPI flash power OR-ing circuit, matching the voltage requirement of the installed W25Q64BVSSIG part. | | 2 | 2 | +3VSB | ✅ | R152 is correctly populated to connect +3VSB (3.3V standby supply) to the SPI flash power OR-ing circuit, matching the voltage requirement of the installed W25Q64BVSSIG part. | </details> <details> <summary><b>U3</b> - W25Q64BVSSIG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/653/W25Q64BV.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/W25Q64BVSSIG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPI_CS0 | ✅ | CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pullup resistor to +V_SPI, meeting datasheet recommendations for power-up tracking. | | 2 | SO/IO1 | SPI_MISO | ✅ | SO/IO1 (Serial Data Output) is correctly connected to SPI_MISO through level translator U18, providing the MISO signal for SPI communication. | | 3 | WP#/IO2 | SPI_WP | ✅ | WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pullup resistor to +V_SPI, disabling hardware write protection as recommended for standard SPI operation. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 5 | SI/IO0 | SPI_MOSI | ✅ | SI/IO0 (Serial Data Input) is correctly connected to SPI_MOSI through level translator U18, providing the MOSI signal for SPI communication. | | 6 | SCK | SPI_CLK | ✅ | SCK (Serial Clock) is correctly connected to SPI_CLK through level translator U18, providing the clock signal for SPI communication. | | 7 | HOLD#/IO3 | SPI_HOLD | ✅ | HOLD#/IO3 (Hold Input) is correctly connected to SPI_HOLD with a 10K pullup resistor to +V_SPI, disabling the hold function as recommended for standard SPI operation. | | 8 | VCC | +V_SPI | ✅ | VCC is correctly connected to +V_SPI with proper decoupling capacitors. The voltage level after diode drop (approximately 2.9-3.0V from 3.3V source) is within the 2.7-3.6V specification but has limited margin. | </details> <details> <summary><b>R147</b> - 110-0001859 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001859) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | R147 correctly pulls up the DDP_IO3L signal (connected to level translator U18 OE pin) to +V1P8A, providing a default enabled state for the level translator while allowing external control through the DediProg connector. | | 2 | 2 | DDP_IO3L | ✅ | R147 correctly pulls up the DDP_IO3L signal (connected to level translator U18 OE pin) to +V1P8A, providing a default enabled state for the level translator while allowing external control through the DediProg connector. | </details> <details> <summary><b>D8</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | DDP_VCC | ✅ | Anode 1 is correctly connected to DDP_VCC from the DediProg programming header J1 pin 1, allowing external programming power to be OR-ed with the internal supply. | | A2 | A2 | $20N2079 | ✅ | Anode 2 is correctly connected to the internal 3.3V standby supply (+3VSB) through R152, providing the second power source for the OR-ing configuration. | | C | C | +V_SPI | ✅ | Common cathode is correctly connected to +V_SPI, which powers the SPI flash U3. The OR-ing diode configuration allows the higher voltage source (DDP_VCC or +3VSB) to power the flash. | </details> <details> <summary><b>J1</b> - 258-0004612 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004612) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDP_VCC | ✅ | DDP_VCC provides power to the DediProg programmer interface. It is OR'd with +V_SPI through diode D8 and can be sourced from either +3VSB (via R152) or +V1P8A (via R818, DNI). | | 2 | 2 | GND | ✅ | Ground connection for the DediProg programmer interface. | | 3 | 3 | SPI_CS0 | ✅ | SPI chip select signal for the DediProg programmer interface, connected to U3 SPI flash CS# and level translator U18. | | 4 | 4 | SPI_CLK | ✅ | SPI clock signal for the DediProg programmer interface, connected to U3 SPI flash SCK and level translator U18. | | 5 | 5 | SPI_MISO | ✅ | SPI MISO (Master In Slave Out) signal for the DediProg programmer interface, connected to U3 SPI flash SO/IO1 and level translator U18. | | 6 | 6 | SPI_MOSI | ✅ | SPI MOSI (Master Out Slave In) signal for the DediProg programmer interface, connected to U3 SPI flash SI/IO0 and level translator U18. | | 7 | 7 | | ✅ | No connection on pin 7. | | 8 | 8 | DDP_IO3L | ✅ | DDP_IO3L controls the output enable of level translator U18, allowing the DediProg to take control of the SPI bus by disabling the SOC connection. | </details> <details> <summary><b>JP1</b> - 258-0005019 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0005019) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connections for the expansion header. | | 2 | 2 | GND | ✅ | Ground connections for the expansion header. | | 3 | 3 | +PS_5VSB | ✅ | 5V standby power supply output for the expansion header. | | 4 | 4 | +3VSB | ✅ | 3.3V standby power supply output for the expansion header. | | 5 | 5 | SIO_SPI_CS1 | ✅ | SPI chip select 1 signal, level-translated from SOC 1.8V to 3.3V via U14. | | 6 | 6 | UART1_TXD | ✅ | UART1 transmit signal, level-translated from SOC 1.8V to 3.3V via U15. | | 7 | 7 | SIO_SPI_MISO | ✅ | SPI MISO signal, level-translated from SOC 1.8V to 3.3V via U14. | | 8 | 8 | UART1_RXD | ✅ | UART1 receive signal, level-translated from SOC 1.8V to 3.3V via U15. | | 9 | 9 | SIO_SPI_MOSI | ✅ | SPI MOSI signal, level-translated from SOC 1.8V to 3.3V via U14. | | 10 | 10 | UART1_CTSB | ✅ | UART1 clear-to-send signal, level-translated from SOC 1.8V to 3.3V via U15. | | 11 | 11 | SIO_SPI_CLK | ✅ | SPI clock signal, level-translated from SOC 1.8V to 3.3V via U14. | | 12 | 12 | UART1_RTSB | ✅ | UART1 request-to-send signal, level-translated from SOC 1.8V to 3.3V via U15. | | 13 | 13 | GPIO_I2C_SCL | ✅ | I2C clock signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator). | | 14 | 14 | I2SCLK_GPIO | ✅ | I2S clock signal, level-translated from SOC 1.8V to 3.3V via U16. | | 15 | 15 | GPIO_I2C_SDA | ✅ | I2C data signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator). | | 16 | 16 | I2SFRM_GPIO | ✅ | I2S frame sync signal, level-translated from SOC 1.8V to 3.3V via U16. | | 17 | 17 | UART2_TXD | ✅ | UART2 transmit signal, level-translated from SOC 1.8V to 3.3V via U7. | | 18 | 18 | I2SDO_GPIO | ✅ | I2S data out signal, level-translated from SOC 1.8V to 3.3V via U16. | | 19 | 19 | UART2_RXD | ✅ | UART2 receive signal, level-translated from SOC 1.8V to 3.3V via U7. | | 20 | 20 | I2SDI_GPIO | ✅ | I2S data in signal, level-translated from SOC 1.8V to 3.3V via U16. | | 21 | 21 | GPIO_S5_0 | ✅ | GPIO S5_0 signal, level-translated from SOC 1.8V to 3.3V via U10. | | 22 | 22 | PWM0 | ✅ | PWM0 signal, level-translated from SOC 1.8V to 3.3V via U17. | | 23 | 23 | GPIO_S5_1 | ✅ | GPIO S5_1 signal, level-translated from SOC 1.8V to 3.3V via U10. | | 24 | 24 | PWM1 | ✅ | PWM1 signal, level-translated from SOC 1.8V to 3.3V via U17. | | 25 | 25 | GPIO_S5_2 | ✅ | GPIO S5_2 signal, level-translated from SOC 1.8V to 3.3V via U10. | | 26 | 26 | I2SMCLK_GPIO | ✅ | I2S master clock signal, level-translated from SOC 1.8V to 3.3V via U17. | </details> <details> <summary><b>R746</b> - 1120-0318 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | R746 is a 470Ω current limiting resistor connected between +VCC and GPIO_LED_CONTROL. This limits the LED current and also dissipates power when Q105 is on. | | 2 | 2 | GPIO_LED_CONTROL | ✅ | R746 is a 470Ω current limiting resistor connected between +VCC and GPIO_LED_CONTROL. This limits the LED current and also dissipates power when Q105 is on. | </details> <details> <summary><b>D2</b> - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GPIO_LED_CONTROL | ✅ | Anode is connected to GPIO_LED_CONTROL net. This connection is correct for the LED in this inverted logic configuration. | | C | CATHODE | GND | ✅ | Cathode is connected to GND, which is correct for the LED in this configuration. | </details> <details> <summary><b>R706</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_D2_LED_CTRL | ✅ | R706 is a 10K pull-down resistor connected between GPIO_D2_LED_CTRL and GND. This ensures the MOSFET gate is pulled low when not actively driven. | | 2 | 2 | GND | ✅ | R706 is a 10K pull-down resistor connected between GPIO_D2_LED_CTRL and GND. This ensures the MOSFET gate is pulled low when not actively driven. | </details> <details> <summary><b>Q105</b> - FDN327N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/FDN327N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | GPIO_LED_CONTROL | ✅ | Drain is connected to GPIO_LED_CONTROL net, which is the switched node for the LED driver circuit. This connection is correct for a low-side switch configuration. | | G | GATE | GPIO_D2_LED_CTRL | ✅ | Gate is connected to GPIO_D2_LED_CTRL control signal with a 10K pull-down resistor (R706) to ground. This connection is correct for controlling the MOSFET. | | S | SOURCE | GND | ✅ | Source is connected to GND, which is correct for an N-channel MOSFET in a low-side switch configuration. | </details> <details> <summary><b>C149</b> - 123-0003258 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_LED_CONTROL | ✅ | C149 is a 2.2uF capacitor connected between GPIO_LED_CONTROL and GND. This provides filtering but causes slow LED turn-on time of approximately 5ms. | | 2 | 2 | GND | ✅ | C149 is a 2.2uF capacitor connected between GPIO_LED_CONTROL and GND. This provides filtering but causes slow LED turn-on time of approximately 5ms. | </details> <details> <summary><b>R149</b> - 110-0002058 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ❌ | <details><summary>Pull-up resistor connecting FP_PWRBTN signal (pin 1) to +PS_5VSB power rail (pin 2). However, the resistor value is 4.7K ohm, which does not match the 10K value specified by the datasheet recommendation documented in the schematic notes.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="26.71,15.08,34.21,22.58" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to the FP_PWRBTN net <em>(from schematic)</em></li><li>Pin 2 is connected to the +PS_5VSB net (5V standby power) <em>(from schematic)</em></li><li>R149 is specified as 4.7K ohm 1% 1/10W 0402 resistor (Part Number 110-0002058) <em>(from schematic)</em></li><li>Schematic text notes near R149 state &#x27;USE 10K PU&#x27; and &#x27;DATASHEET SAYS&#x27;, indicating a datasheet specifies a 10K pull-up resistor should be used <em>(from schematic)</em></li><li>The actual resistor value of 4.7K does not match the 10K value indicated by the schematic notes <em>(reasoning)</em></li><li>Using +PS_5VSB for the pull-up is correct, as it ensures the power button remains functional even when the main system power is off <em>(reasoning)</em></li><li>A 4.7K pull-up will draw approximately 1.06mA when the button is pressed (5V / 4.7K), while a 10K pull-up would draw approximately 0.5mA <em>(reasoning)</em></li><li>The lower resistance provides faster rise times and better noise immunity, but may violate input current specifications or power consumption requirements of the receiving component <em>(reasoning)</em></li><li>Without documentation explaining the intentional deviation from the datasheet recommendation, this represents a specification violation <em>(reasoning)</em></li><li>Recommendation: Change R149 to 10K ohm to match the datasheet requirement noted on the schematic, or add documentation explaining why 4.7K was intentionally chosen and validated <em>(reasoning)</em></li></ul></details> | | 2 | 2 | +PS_5VSB | ❌ | <details><summary>Pull-up resistor connecting FP_PWRBTN signal (pin 1) to +PS_5VSB power rail (pin 2). However, the resistor value is 4.7K ohm, which does not match the 10K value specified by the datasheet recommendation documented in the schematic notes.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="26.71,13.91,34.21,21.41" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to the FP_PWRBTN net <em>(from schematic)</em></li><li>Pin 2 is connected to the +PS_5VSB net (5V standby power) <em>(from schematic)</em></li><li>R149 is specified as 4.7K ohm 1% 1/10W 0402 resistor (Part Number 110-0002058) <em>(from schematic)</em></li><li>Schematic text notes near R149 state &#x27;USE 10K PU&#x27; and &#x27;DATASHEET SAYS&#x27;, indicating a datasheet specifies a 10K pull-up resistor should be used <em>(from schematic)</em></li><li>The actual resistor value of 4.7K does not match the 10K value indicated by the schematic notes <em>(reasoning)</em></li><li>Using +PS_5VSB for the pull-up is correct, as it ensures the power button remains functional even when the main system power is off <em>(reasoning)</em></li><li>A 4.7K pull-up will draw approximately 1.06mA when the button is pressed (5V / 4.7K), while a 10K pull-up would draw approximately 0.5mA <em>(reasoning)</em></li><li>The lower resistance provides faster rise times and better noise immunity, but may violate input current specifications or power consumption requirements of the receiving component <em>(reasoning)</em></li><li>Without documentation explaining the intentional deviation from the datasheet recommendation, this represents a specification violation <em>(reasoning)</em></li><li>Recommendation: Change R149 to 10K ohm to match the datasheet requirement noted on the schematic, or add documentation explaining why 4.7K was intentionally chosen and validated <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>C154</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor ground connection, providing the return path for filtering and debouncing the FP_PWRBTN signal. | | 2 | 2 | FP_PWRBTN | ✅ | Decoupling capacitor signal pin connected to FP_PWRBTN net, providing filtering and debouncing for the power button signal. | </details> <details> <summary><b>D9</b> - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | TVS diode terminal connected to GND. Provides the ground reference for bidirectional ESD protection. | | P | P | FP_PWRBTN | ✅ | TVS diode terminal connected to FP_PWRBTN signal. Provides bidirectional ESD protection for the power button input. | </details> <details> <summary><b>J5</b> - 258-0002513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Header pin connected to FP_PWRBTN signal. Provides connection point for external power button. | | 2 | 2 | GND | ✅ | Header pin connected to GND. Provides ground return for external power button connection. | </details> <details> <summary><b>SW1</b> - 3770-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3770-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Switch signal pin connected to FP_PWRBTN net. When button is pressed, this pin connects to pin 2 (GND), pulling the power button signal low. | | 2 | 2 | GND | ✅ | Switch return pin connected to GND. Provides the ground reference for the power button when pressed. | | 3 | GND1 | GND_EARTH | ✅ | Shield/mounting pins (GND1 and GND2) connected to GND_EARTH. Provides chassis ground connection for EMI/ESD protection. | | 4 | GND2 | GND_EARTH | ✅ | Shield/mounting pins (GND1 and GND2) connected to GND_EARTH. Provides chassis ground connection for EMI/ESD protection. | </details> <details> <summary><b>D1</b> - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | +PS_5VSB | ✅ | Anode is correctly connected to +PS_5VSB to power the adaptor power indicator LED. | | C | CATHODE | PWR_LEDR | ✅ | Cathode is correctly connected through current-limiting resistor R148 to ground, completing the LED circuit. | </details> <details> <summary><b>Q9</b> - DIODE_ARRAY_75V_0.3A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | $22N1417 | ✅ | Anode A1 correctly connected to intermediate node $22N1417 from first charge pump stage. | | 2 | A2 | +10V | ✅ | Anode A2 correctly connected to +10V output of charge pump circuit. | | 3 | C | $22N1467 | ✅ | Common cathode correctly connected to $22N1467 node with capacitor C283 to CLK signal. | </details> <details> <summary><b>L3</b> - IND_2.2uH_20%_10A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/125-0004501) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | Inductor input correctly connected to PS3VSB_PHASE switch node from U13 SW pins. | | 2 | 2 | +PS_3VSB | ✅ | Inductor output correctly connected to +PS_3VSB output rail with output capacitors. | </details> <details> <summary><b>Q2</b> - DIODE_ARRAY_75V_0.3A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | +PS_5VSB | ✅ | Anode A1 correctly connected to +PS_5VSB input for first stage of charge pump circuit. | | 2 | A2 | $22N1417 | ✅ | Anode A2 correctly connected to intermediate node $22N1417 between charge pump stages. | | 3 | C | $22N1419 | ✅ | Common cathode correctly connected to $22N1419 node with capacitor C72 to CLK signal. | </details> <details> <summary><b>U13</b> - REG_LDO_BUCK_24V ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NB670) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN | PS5VSB_VIN | ✅ | VIN pin correctly connected to PS5VSB_VIN input rail with multiple input decoupling capacitors (22µF and 0.1µF) and ferrite beads to +PS_5VSB source. | | 2 | PGND | GND | ✅ | PGND pin correctly connected to GND plane for power ground return. | | 3 | N/C | | ✅ | N/C pin correctly left unconnected per datasheet. | | 4 | PG | +PS_3VSB_PG | ✅ | PG pin correctly configured as open-drain output with 100kΩ pull-up resistor to PS3_VCC, connected to power good monitoring circuit. | | 5 | CLK | $22N1411 | ✅ | CLK pin correctly connected to external charge pump circuit through capacitors C72 and C283 with diode networks Q2 and Q9 to generate +10V output. | | 6 | LDO | PS3_LDO | ✅ | LDO pin correctly connected to 10µF decoupling capacitor C95 for internal 3.3V linear regulator output. | | 7 | VOUT | +PS_3VSB | ✅ | VOUT pin correctly connected to +PS_3VSB output rail through inductor L3, with multiple output capacitors for 3.3V/6A output. | | 8 | SW1 | PS3VSB_PHASE | ✅ | SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit. | | 9 | SW2 | PS3VSB_PHASE | ✅ | SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit. | | 15 | SW3 | PS3VSB_PHASE | ✅ | SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit. | | 16 | SW4 | PS3VSB_PHASE | ✅ | SW1-SW4 pins correctly connected together to PS3VSB_PHASE switch node, driving inductor L3 and bootstrap circuit. | | 10 | BST | PS3_BST | ✅ | BST pin connected to bootstrap circuit with series resistor R291 (4.7Ω) and capacitor C306 (0.1µF) to SW node. The series resistor is non-standard but may be intentional for current limiting or damping. | | 11 | VCC | PS3_VCC | ✅ | VCC pin correctly connected to 1µF decoupling capacitor C97 for internal 5V LDO output that powers driver and control circuits. | | 12 | ENLDO | | ✅ | ENLDO pin correctly left floating, which enables the LDO and VCC per internal pull-up. | | 13 | EN | PS3_EN | ✅ | EN pin connected with 499kΩ pull-up resistor to PS5VSB_VIN for automatic startup. Recommended 10nF noise filter capacitor C85 is marked DNI, which may increase noise susceptibility. | | 14 | AGND | GND | ✅ | AGND pin correctly connected to GND plane for analog ground reference. | </details> <details> <summary><b>U35</b> - PWR_CTRL_EMB_PROC ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NCT3012S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 4 | SLP_S5# | SLP_S4_L | ❌ | <details><summary>Pin 4 (SLP_S5#) is connected to net SLP_S4_L. This represents a mismatch between the pin name (indicating S5 sleep state) and the connected signal (indicating S4 sleep state). While this could be intentional in systems that do not distinguish between S4 and S5 states, it should be verified against system requirements and the NCT3012S-X datasheet.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="18.08,38.61,25.58,46.11" aspect-ratio="1.29" } <ul><li>Pin 4 is labeled SLP_S5# on component U35 <em>(from schematic)</em></li><li>Pin 4 is connected to net SLP_S4_L <em>(from schematic)</em></li><li>Component U35 has a DeepS5_Sel pin (pin 1), indicating the chip has specific S5 state handling functionality <em>(from schematic)</em></li><li>In ACPI specifications, S4 (Suspend to Disk/Hibernate) and S5 (Soft Off) are different power states with different system behaviors <em>(reasoning)</em></li><li>The pin name SLP_S5# explicitly indicates this pin expects an S5 sleep state signal <em>(reasoning)</em></li><li>The net name SLP_S4_L indicates this is an S4 sleep state signal <em>(reasoning)</em></li><li>Both signals use active-low polarity (# and _L suffixes), so polarity is consistent <em>(reasoning)</em></li><li>No SLP_S5# or SLP_S5_L net is visible in the schematic, suggesting either the S5 signal does not exist in this design or there is a naming/connection error <em>(from schematic)</em></li><li>Some embedded systems may intentionally use S4 signals to control S5 behavior if they do not distinguish between these states <em>(reasoning)</em></li><li>Without the NCT3012S-X datasheet, it cannot be definitively determined whether the chip accepts S4 signals on the SLP_S5# pin <em>(reasoning)</em></li><li>Given the explicit pin naming and the presence of S5-specific functionality (DeepS5_Sel), this connection should be verified to ensure correct power state management <em>(reasoning)</em></li><li>If this is an error, pin 4 should be connected to an SLP_S5# signal; if intentional, this design decision should be documented <em>(reasoning)</em></li></ul></details> | | 1 | DeepS5_Sel | S5_SEL | ✅ | DeepS5_Sel configuration pin with 2.2K pull-up to +PS_5VSB. This pin likely selects the deep S5 mode behavior. | | 2 | VSB | +PS_5VSB | ✅ | VSB power supply pin correctly connected to +PS_5VSB rail with adequate decoupling capacitors nearby. | | 3 | PS_IN# | PB_RES | ✅ | PS_IN# (power switch input) connected to PB_RES through R308 (33 ohm series resistor) for protection and debouncing. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA pin connected to DDR_SMB_DATA for I2C/SMBus communication, likely for DDR memory or system management. | | 6 | SCLK | DDR_SMB_CLK | ✅ | SCLK pin connected to DDR_SMB_CLK for I2C/SMBus clock signal, pairing with the SDA line. | | 7 | PS_OUT# | PS_OUT_L | ✅ | PS_OUT# output pin connected to PS_OUT_L with a DNI pull-up resistor (R289). The absence of the pull-up may be correct if the output is push-pull. | | 8 | SYS5VSB_OFF | 5VSB_CTRL | ✅ | SYS5VSB_OFF output controls the 5VSB rail through Q10 gate and has proper pull-up through R288. Text notes indicate this signal controls EuP mode. | | 9 | GND | GND | ✅ | GND pin correctly connected to the ground net. | </details> <details> <summary><b>Q103</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. All three source pins are paralleled for lower resistance and better current handling capability. | | 2 | S2 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. All three source pins are paralleled for lower resistance and better current handling capability. | | 3 | S3 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. All three source pins are paralleled for lower resistance and better current handling capability. | | 4 | G | 5VSB_LSENB | ✅ | Gate pin correctly connected to control signal 5VSB_LSENB with appropriate gate drive circuit providing +10V when on and 0V when off. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled for lower resistance and better current handling capability. | </details> <details> <summary><b>Q104</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. All three source pins are paralleled and connected to the switched output that supplies downstream loads including Q6 and Q13. | | 2 | S2 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. All three source pins are paralleled and connected to the switched output that supplies downstream loads including Q6 and Q13. | | 3 | S3 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. All three source pins are paralleled and connected to the switched output that supplies downstream loads including Q6 and Q13. | | 4 | G | +3VSB_EN | ✅ | Gate pin correctly connected to +3VSB_EN control signal with proper high-side drive circuit. The gate is pulled up to +10V through R322 (100K) when enabled, providing VGS of approximately 6.7V, and pulled down through Q11 when disabled. | | 5 | D1 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch. | | 6 | D2 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch. | | 7 | D3 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch. | | 8 | D4 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck converter U13. All four drain pins are paralleled and connected to the 3.3V output of the buck converter, which serves as the input power source for the load switch. | </details> <details> <summary><b>D13</b> - 4.3V Zener ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4620-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode correctly connected to GND, establishing the reference for the 4.3V zener clamp voltage on the cathode. | | C | CATHODE | $22N2300 | ✅ | Cathode correctly connected to $22N2300, which is the gate control voltage for Q106. The zener clamps this voltage at 4.3V to create the protection threshold. | </details> <details> <summary><b>U36</b> - MOSFET_30V_15A_8-SOIC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.umw-ic.com/static/pdf/b379d167af492bcd72ba51c793d83236.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/IRF9321) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | $22N1502 | ✅ | Source pins correctly connected to $22N1502, which receives input power from DC_IN_1 through ferrite beads L12 and L13. This is the correct configuration for a P-channel MOSFET high-side switch where current flows from source to drain. | | 2 | S2 | $22N1502 | ✅ | Source pins correctly connected to $22N1502, which receives input power from DC_IN_1 through ferrite beads L12 and L13. This is the correct configuration for a P-channel MOSFET high-side switch where current flows from source to drain. | | 3 | S3 | $22N1502 | ✅ | Source pins correctly connected to $22N1502, which receives input power from DC_IN_1 through ferrite beads L12 and L13. This is the correct configuration for a P-channel MOSFET high-side switch where current flows from source to drain. | | 4 | G | DC_GATE_ENB | ✅ | Gate pin correctly connected to DC_GATE_ENB, which is the control signal from the protection circuit. When DC_GATE_ENB is pulled low by R309, U36 turns on; when Q106 pulls it high during overvoltage, U36 turns off. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB, which is the output rail being powered. This is the correct configuration for a P-channel MOSFET high-side switch where the drain is at the load side. | </details> <details> <summary><b>Q106</b> - BSS84 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/bss84-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BSS84) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | D | DC_GATE_ENB | ✅ | Drain pin correctly connected to DC_GATE_ENB, which is the gate control signal for U36. When Q106 turns on, it pulls DC_GATE_ENB toward $22N1502, reducing VGS of U36 and turning it off. | | G | G | $22N2300 | ✅ | Gate pin correctly connected to $22N2300, which is the control voltage from the zener clamp circuit (R855 and D13). When $22N1502 exceeds ~5.8V, the gate voltage becomes sufficiently negative to turn on Q106. | | S | S | $22N1502 | ✅ | Source pin correctly connected to $22N1502, which serves as the reference voltage for Q106. This is the higher potential node in normal operation, which is correct for a P-channel MOSFET. | </details> <details> <summary><b>Q6</b> - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB | ✅ | Drain pin correctly connected to +3VSB input rail. This is the input side of the high-side N-channel load switch. | | G | GATE | SYS_EN | ✅ | Gate pin correctly connected to SYS_EN control signal. The gate drive voltage of +10V provides sufficient VGS for proper MOSFET operation. | | S | SOURCE | +VCC3 | ✅ | Source pin correctly connected to +VCC3 output rail. This is the output side of the high-side N-channel load switch. | </details> <details> <summary><b>Q13</b> - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +5VSB | ✅ | Drain pin correctly connected to +5VSB input rail. This is the input side of the high-side N-channel load switch. | | G | GATE | SYS_EN | ✅ | Gate pin correctly connected to SYS_EN control signal. The gate drive voltage of +10V provides sufficient VGS for proper MOSFET operation. | | S | SOURCE | +VCC | ✅ | Source pin correctly connected to +VCC output rail. This is the output side of the high-side N-channel load switch. | </details> <details> <summary><b>Q12</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN | ✅ | Drain is connected to SYS_EN net, which controls the gates of Q13 and Q6 power MOSFETs. When Q12 is on, it pulls SYS_EN low; when off, R340 pulls it high to +10V. | | G | GATE | SYS_EN_GATE | ✅ | Gate is connected to SYS_EN_GATE net, which is the output of Q7. This forms the second stage of an inverter chain that level-shifts and inverts the SLP_S3_L signal. | | S | SOURCE | GND | ✅ | Source is connected to GND, which is correct for an N-channel MOSFET in a low-side switching configuration. | </details> <details> <summary><b>Q7</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN_GATE | ✅ | Drain is connected to SYS_EN_GATE net, which serves as the output of this inverter stage. When Q7 turns on, it pulls SYS_EN_GATE low; when off, R142 pulls it high to +10V. | | G | GATE | SLP_S3_L | ✅ | Gate is connected to SLP_S3_L signal, which is an active-low sleep control signal. This controls when Q7 turns on to pull down SYS_EN_GATE. | | S | SOURCE | GND | ✅ | Source is connected to GND, which is correct for an N-channel MOSFET in a low-side switching configuration. | </details> <details> <summary><b>Q10</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | S5_ENBL | ✅ | Drain is correctly connected to S5_ENBL, which is pulled up to +V1P8A through R133 (10K) and drives the base of Q4. | | G | GATE | 5VSB_CTRL | ✅ | Gate is correctly connected to 5VSB_CTRL from U35 pin 8, providing adequate gate drive voltage. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, providing the reference for the N-channel MOSFET low-side switch. | </details> <details> <summary><b>Q4</b> - XSTR_NPN_40V_200mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/MMBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B | BASE | S5_ENBL | ✅ | Base is correctly connected to S5_ENBL, which is controlled by Q10 and pulled up through R133. | | C | COLLECTOR | +3VSB_EN_L | ✅ | Collector is correctly connected to +3VSB_EN_L, which is pulled up through R321 and drives Q11 gate. | | E | EMITTER | GND | ✅ | Emitter is correctly connected to GND, providing the reference for the NPN transistor common-emitter configuration. | </details> <details> <summary><b>Q14</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | 5VSB_LSENB | ✅ | Drain is correctly connected to 5VSB_LSENB, which is pulled up to +10V through R324 and controls Q103 gate. | | G | GATE | 5VSB_GATE | ✅ | Gate is correctly connected to 5VSB_GATE, which is derived from 5VSB_CTRL through R323 and filtered by C340. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, providing the reference for the N-channel MOSFET low-side switch. | </details> <details> <summary><b>Q11</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB_EN | ✅ | Drain is correctly connected to +3VSB_EN, which is pulled up to +10V through R322 and controls Q104 gate. | | G | GATE | +3VSB_EN_L | ✅ | Gate is correctly connected to +3VSB_EN_L from Q4 collector, providing adequate gate drive voltage. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, providing the reference for the N-channel MOSFET low-side switch. | </details> <details> <summary><b>D6</b> - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB_PG | ✅ | Cathode 1 connected to +PS_3VSB_PG (power good signal from U13 pin 4). This diode clamps +3VSB_EN low when the power good signal is asserted low. | | 2 | 2 | +3VSB_EN | ✅ | Common anode connected to +3VSB_EN (gate control signal for Q104). This is the output node of the diode OR circuit that controls the 3VSB power switch based on power good and reset signals. | | 3 | 3 | PMC_RSMRST | ✅ | Cathode 2 connected to PMC_RSMRST (resume reset signal from platform management controller). This diode clamps +3VSB_EN low when reset is asserted. | </details> <details> <summary><b>J9</b> - JACK_PWR_2.1MM_RAPC712 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/414/RAPC712_cd.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/RAPC712) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DC_IN_1 | ✅ | Center pin correctly connected to DC_IN_1 net, serving as the positive DC power input. The connection includes protection circuitry that disconnects the input when voltage exceeds 5.8V. | | 2 | 2 | GND | ✅ | Sleeve pin correctly connected to GND net, serving as the ground return path for the DC power input. | | 3 | 3 | GND | ✅ | Switch contact pin connected to GND, which disables the plug detection functionality. While electrically safe, this connection does not utilize the jack's switched contact feature. | </details> <details> <summary><b>FB11</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB, paralleled with FB1 pin 1 for increased current capacity. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, paralleled with FB1 pin 2 for increased current capacity. | </details> <details> <summary><b>FB1</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB, the filtered 5V standby rail output from power switching MOSFETs Q103 and U36. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, the input to the 3.3V buck regulator U13 and associated input capacitors. | </details> <details> <summary><b>L13</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Pin 1 connects to $22N1502, paralleled with L12 pin 1 for increased current capacity. | | 2 | 2 | DC_IN_1 | ✅ | Pin 2 connects to DC_IN_1, paralleled with L12 pin 2 for increased current capacity. | </details> <details> <summary><b>L12</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Pin 1 connects to $22N1502, the source pins of P-channel MOSFET U36 and the filtered DC input node. | | 2 | 2 | DC_IN_1 | ✅ | Pin 2 connects to DC_IN_1, the 5V DC input from power jack J9. | </details> <details> <summary><b>U25</b> - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin connected to VR_HOT_L net for thermal alert output. | | 2 | SDIO | $23N2429 | ✅ | SDIO pin connected to SVID data line through 16.9Ω series resistor R80. | | 3 | ALERT | $23N2431 | ✅ | ALERT pin connected to SVID alert line through 0Ω resistor R62. | | 4 | SCLK | $23N2430 | ✅ | SCLK pin connected to SVID clock line through 20.0Ω series resistor R81. | | 5 | GND | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) connected to AGND-VCORE net, which connects to main GND through 0Ω resistor R37. | | 32 | GND1 | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) connected to AGND-VCORE net, which connects to main GND through 0Ω resistor R37. | | 49 | GND_PAD | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) connected to AGND-VCORE net, which connects to main GND through 0Ω resistor R37. | | 6 | VR_RDY | $23N3753 | ✅ | VR_RDY pin connected to power good output signal VCORE_PG through 0Ω resistor R79. | | 7 | VIN1 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 11 | VIN2 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 12 | VIN3 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 13 | VIN4 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 14 | VIN5 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 15 | VIN6 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 16 | VIN7 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 17 | VIN8 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 50 | VIN_PAD | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW net with proper decoupling. | | 8 | BST | $23N3711 | ✅ | BST pin connected to bootstrap circuit with R154 (2.20Ω) and C50 (0.22µF) to SW1. | | 9 | GH | | ✅ | GH pin (high-side gate driver output) is not connected. This is unusual but may be correct for an integrated power stage with internal MOSFETs. | | 10 | SW1 | $23N3731 | ✅ | SW1 pin connected to bootstrap circuit but not to main VCORE-SW net. This separation from SW2-SW7 is unusual and should be verified. | | 18 | SW2 | VCORE-SW | ✅ | Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18. | | 25 | SW3 | VCORE-SW | ✅ | Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18. | | 26 | SW4 | VCORE-SW | ✅ | Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18. | | 27 | SW5 | VCORE-SW | ✅ | Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18. | | 28 | SW6 | VCORE-SW | ✅ | Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18. | | 29 | SW7 | VCORE-SW | ✅ | Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18. | | 51 | SW_PAD | VCORE-SW | ✅ | Switch node output pins (SW2-SW7, SW_PAD) all connected to VCORE-SW net, which connects to output through inductor L18. | | 19 | PGND1 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to main GND net. | | 20 | PGND2 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to main GND net. | | 21 | PGND3 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to main GND net. | | 22 | PGND4 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to main GND net. | | 23 | PGND5 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to main GND net. | | 24 | PGND6 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to main GND net. | | 30 | GL | | ✅ | GL pin (low-side gate driver output) is not connected. This is unusual but may be correct for an integrated power stage with internal MOSFETs. | | 31 | VBOOT | $23N3477 | ✅ | VBOOT pin connected to voltage divider R70 (88.7kΩ) to set boot voltage. Text note indicates VBOOT = 1.1V. | | 33 | VCCP | $23N3625 | ✅ | VCCP pin connected to charge pump supply through R845 (1.00Ω) from +5VSB with 4.7µF decoupling capacitor C48. | | 34 | TSENSE | $23N3665 | ✅ | TSENSE pin connected to thermistor divider network with TH2 (100kΩ@25C) and R131 (14.0kΩ) for temperature sensing. | | 35 | IMAX | $23N3681 | ✅ | IMAX pin connected to resistor divider R105 (44.2kΩ) to set maximum current limit. Text note indicates IMAX = 14A. | | 36 | IOUT | $23N3683 | ✅ | IOUT pin connected to resistor divider R146 (16.5kΩ) and filter capacitor C47 (470pF) for output current reporting. | | 37 | ILIM | VCORE-ILIM | ✅ | ILIM pin connected to current loop compensation network through R95 (15.0kΩ). | | 38 | CSCOMP | VCORE-CSCOMP | ✅ | CSCOMP pin connected to current sense compensation network with capacitors C39 (470pF), C40 (2200pF), resistors R95, R96, and thermistor TH1. | | 39 | CSSUM | VCORE-CSSUM | ✅ | CSSUM pin connected to current sense summing network with capacitors C39, C40 and resistors R106, R107 for DCR current sensing. | | 40 | CSREF | VCORE-CSREF | ✅ | CSREF pin connected to current sense reference network with capacitor C45 (1000pF) and resistor R108 (10.0Ω). | | 41 | FREQ | $23N2930 | ✅ | FREQ pin connected to frequency setting resistor R93 (18.7kΩ). Text note indicates FSW = 650kHz. | | 42 | COMP | VCORE-COMP | ✅ | COMP pin connected to voltage loop compensation network with capacitors C35 (47pF), C37 (2200pF) and resistor R88 (3.01kΩ). | | 43 | FB | VCORE-FB | ✅ | FB pin connected to feedback network with resistors R88, R89 and capacitors C35, C36 for voltage regulation. | | 44 | DIFFOUT | VCORE-DIFFOUT | ✅ | DIFFOUT pin connected to differential amplifier output network with resistors R89 (1.00kΩ) and R90 (47Ω). | | 45 | VSN | VR-VCORE-VSN | ✅ | VSN pin connected to negative remote sense input through R65 (10.0Ω) for differential voltage sensing. | | 46 | VSP | VR-VCORE-VSP | ✅ | VSP pin connected to positive remote sense input through R92 (100Ω) and R63 (0Ω) for differential voltage sensing. | | 47 | VCC | $23N3860 | ✅ | VCC pin connected to internal supply through R166 (2.20Ω) from +5VSB with 1.0µF decoupling capacitor C24. | | 48 | EN | $23N5607 | ✅ | EN pin connected to enable circuit with pull-up to +VCC through R849 (0Ω) and pull-down R851 (10.0kΩ) to GND. | </details> <details> <summary><b>L8</b> - 3120-0183 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3120-0183) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of the input filter inductor. | | 2 | 2 | +5VSB_SW | ✅ | Pin 2 connects to the +5VSB_SW filtered supply rail that powers the U25 controller. This is the correct connection for the output side of the input filter inductor. | </details> <details> <summary><b>L18</b> - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Pin 1 connects to the VCORE-SW switching node from the U25 multiphase buck controller. This is the correct connection for the input side of the output filter inductor. | | 2 | 2 | +VCORE | ✅ | Pin 2 connects to the +VCORE output rail with appropriate output capacitors and load connections. This is the correct connection for the output side of the filter inductor. | </details> <details> <summary><b>R88</b> - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0032) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2824 | ✅ | R88 forms part of a Type III compensation network, creating a pole-zero pair with C37 between the COMP and FB pins of the voltage regulator. | | 2 | 2 | VCORE-FB | ✅ | R88 forms part of a Type III compensation network, creating a pole-zero pair with C37 between the COMP and FB pins of the voltage regulator. | </details> <details> <summary><b>R89</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | R89 provides a DC feedback path between the FB and DIFFOUT pins, part of the differential amplifier network for remote sensing. | | 2 | 2 | VCORE-DIFFOUT | ✅ | R89 provides a DC feedback path between the FB and DIFFOUT pins, part of the differential amplifier network for remote sensing. | </details> <details> <summary><b>R90</b> - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2818 | ✅ | R90 forms an RC filter with C36 in the DIFFOUT network, providing damping and filtering for the differential output path. | | 2 | 2 | VCORE-DIFFOUT | ✅ | R90 forms an RC filter with C36 in the DIFFOUT network, providing damping and filtering for the differential output path. | </details> <details> <summary><b>C35</b> - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | C35 is the direct compensation capacitor between COMP and FB pins, providing the high-frequency pole in the Type III compensation network. | | 2 | 2 | VCORE-FB | ✅ | C35 is the direct compensation capacitor between COMP and FB pins, providing the high-frequency pole in the Type III compensation network. | </details> <details> <summary><b>C36</b> - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | C36 forms an RC filter with R90 in the DIFFOUT network, connecting between FB and the filtered node feeding DIFFOUT. | | 2 | 2 | $23N2818 | ✅ | C36 forms an RC filter with R90 in the DIFFOUT network, connecting between FB and the filtered node feeding DIFFOUT. | </details> <details> <summary><b>C37</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | C37 forms part of the Type III compensation network, creating a pole-zero pair with R88 to provide phase boost in the voltage loop. | | 2 | 2 | $23N2824 | ✅ | C37 forms part of the Type III compensation network, creating a pole-zero pair with R88 to provide phase boost in the voltage loop. | </details> <details> <summary><b>R108</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSREF | ✅ | Connected to VCORE-CSREF (U25 pin 40). This is the current sense reference input. | | 2 | 2 | $23N3208 | ✅ | Connected to $23N3208, which connects to +VCORE through SP4. This provides the current sense reference from the output voltage. | </details> <details> <summary><b>C39</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP (U25 pin 38). This is one side of the current loop compensation capacitor. | | 2 | 2 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM (U25 pin 39). This completes the compensation capacitor between CSCOMP and CSSUM. | </details> <details> <summary><b>C45</b> - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSREF | ✅ | Connected to VCORE-CSREF (U25 pin 40). This provides filtering for the current sense reference. | | 2 | 2 | GND | ✅ | Connected to GND. This completes the filter capacitor for CSREF. | </details> <details> <summary><b>R107</b> - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1130-0002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM (U25 pin 39). This is the current sense sum input. | | 2 | 2 | $23N3209 | ✅ | Connected to $23N3209, which connects to VCORE-SW through SP3. This senses current from the switch node. | </details> <details> <summary><b>TH1</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP (U25 pin 38). This is one side of the temperature compensation thermistor. | | 2 | 2 | $23N3115 | ✅ | Connected to intermediate node $23N3115, which connects to R96 and R106. This completes the temperature compensation network. | </details> <details> <summary><b>C40</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP (U25 pin 38). This is one side of the current loop compensation capacitor. | | 2 | 2 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM (U25 pin 39). This completes the compensation capacitor between CSCOMP and CSSUM. | </details> <details> <summary><b>R95</b> - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0351) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-ILIM | ✅ | Connected to VCORE-ILIM (U25 pin 37). This pin sets the current limit threshold for the DC-DC converter. | | 2 | 2 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP (U25 pin 38). This pin provides current sense compensation. | </details> <details> <summary><b>R106</b> - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0037) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3115 | ✅ | Connected to intermediate node $23N3115, which connects to R96 and TH1. This is part of the resistor divider network. | | 2 | 2 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM (U25 pin 39). This completes the resistor divider for current sensing. | </details> <details> <summary><b>R96</b> - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0282) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP (U25 pin 38). This is part of the current sense compensation network. | | 2 | 2 | $23N3115 | ✅ | Connected to intermediate node $23N3115, which connects to R106 and TH1. This forms part of the resistor divider network. | </details> <details> <summary><b>C46</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | Filter capacitor positive terminal connected to the TSENSE input of U25, providing noise filtering for the temperature sensing circuit. | | 2 | 2 | AGND-VCORE | ✅ | Filter capacitor ground terminal connected to AGND-VCORE, the analog ground reference for the voltage regulator. | </details> <details> <summary><b>R131</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0055) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | 14.0K resistor in parallel with thermistor TH2, limiting the maximum resistance seen by the TSENSE input and providing a defined voltage range. | | 2 | 2 | GND | ✅ | 14.0K resistor in parallel with thermistor TH2, limiting the maximum resistance seen by the TSENSE input and providing a defined voltage range. | </details> <details> <summary><b>R78</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | 0Ω jumper connecting the TSENSE pin of U25 to the thermistor temperature sensing network. This allows for easy disconnection if needed. | | 2 | 2 | $23N3662 | ✅ | 0Ω jumper connecting the TSENSE pin of U25 to the thermistor temperature sensing network. This allows for easy disconnection if needed. | </details> <details> <summary><b>TH2</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Thermistor pin connected to the temperature sensing voltage divider node. This pin connects through R78 to the TSENSE input of U25. | | 2 | 2 | GND | ✅ | Thermistor pin connected to ground, completing the temperature sensing voltage divider. | </details> <details> <summary><b>R80</b> - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0329) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Connected to SVID_DATA-R signal line. This is the external side of the series resistor for the SVID data interface. | | 2 | 2 | $23N2429 | ✅ | Connected to U25 pin 2 (SDIO) through net $23N2429. This is the controller side of the series resistor. | </details> <details> <summary><b>R81</b> - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0099) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Connected to SVID_CLK-R signal line. This is the external side of the series resistor for the SVID clock interface. | | 2 | 2 | $23N2430 | ✅ | Connected to U25 pin 4 (SCLK) through net $23N2430. This is the controller side of the series resistor. | </details> <details> <summary><b>R62</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Connected to SVID_ALERT-R signal line. This is the external side of the 0Ω jumper for the SVID alert interface. | | 2 | 2 | $23N2431 | ✅ | Connected to U25 pin 3 (ALERT) through net $23N2431. This is the controller side of the 0Ω jumper. | </details> <details> <summary><b>R85</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0330) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S supply. This resistor is marked DNI and is electrically absent. | | 2 | 2 | SVID_DATA-R | ✅ | Connected to SVID_DATA-R signal line. This resistor is marked DNI and is electrically absent. | </details> <details> <summary><b>R86</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0330) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S supply. This resistor is marked DNI and is electrically absent. | | 2 | 2 | SVID_ALERT-R | ✅ | Connected to SVID_ALERT-R signal line. This resistor is marked DNI and is electrically absent. | </details> <details> <summary><b>R87</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0330) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S supply. This resistor is marked DNI and is electrically absent. | | 2 | 2 | SVID_CLK-R | ✅ | Connected to SVID_CLK-R signal line. This resistor is marked DNI and is electrically absent. | </details> <details> <summary><b>R65</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | Connected to intermediate node $23N2860, which combines local and remote sense signals for the negative path. | | 2 | 2 | VR-VCORE-VSN | ✅ | Connected to VR-VCORE-VSN (U25 pin 45), providing the negative differential sense input. The 10Ω value creates an asymmetry with the positive path but may be intentional for filtering or current limiting. | </details> <details> <summary><b>C38</b> - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | Would connect to intermediate node $23N2860 if installed, but component is marked DNI (Do Not Install). | | 2 | 2 | VR-VCORE-VSN | ✅ | Would connect to VR-VCORE-VSN if installed, forming a filter with R65, but component is marked DNI. | </details> <details> <summary><b>R63</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_SENSE | ✅ | Connected to VCC_SENSE for remote voltage sensing of the positive output. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP, providing remote sense input to U25 pin 46 (VSP). | </details> <details> <summary><b>R91</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND as part of the local voltage sense path for the negative side of the differential sense circuit. | | 2 | 2 | $23N2860 | ✅ | Connected to intermediate node $23N2860, which connects to VSS_SENSE through R64 and to VSN through R65. | </details> <details> <summary><b>R64</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VSS_SENSE | ✅ | Connected to VSS_SENSE for remote voltage sensing of the negative output (ground). | | 2 | 2 | $23N2860 | ✅ | Connected to intermediate node $23N2860, which connects to VSN through R65. | </details> <details> <summary><b>C34</b> - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VCORE-VSP | ✅ | Would connect to VR-VCORE-VSP if installed, but component is marked DNI (Do Not Install). | | 2 | 2 | VR-VCORE-VSN | ✅ | Would connect to VR-VCORE-VSN if installed, forming a differential filter capacitor between VSP and VSN, but component is marked DNI. | </details> <details> <summary><b>R92</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output as part of the local voltage sense path for the positive side of the differential sense circuit. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP, which connects to U25 pin 46 (VSP) and to VCC_SENSE through R63. | </details> <details> <summary><b>D4</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Cathode 1 connected to VCORE_PG power good signal. This pin receives the VCORE power good signal and forms one input of the OR-ing diode configuration. | | 2 | 2 | VGFX_PG | ✅ | Cathode 2 connected to VGFX_PG power good signal. This pin receives the VGFX power good signal and forms the second input of the OR-ing diode configuration. | | 3 | 3 | VCORE_GFX_PG | ✅ | Common anode connected to VCORE_GFX_PG combined power good output. This pin outputs the OR'd result of the two input power good signals. | </details> <details> <summary><b>R167</b> - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0052) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 supply rail. Provides pull-up voltage for VCORE_PG signal. | | 2 | 2 | VCORE_PG | ✅ | Connected to VCORE_PG power good signal. Provides weak pull-up to ensure signal is high when not actively driven low. | </details> <details> <summary><b>R94</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | Connected to VCORE_GFX_PG combined power good output. Provides pull-up for the OR'd power good signal. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 supply rail. Provides pull-up voltage for VCORE_GFX_PG signal. | </details> <details> <summary><b>C25</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Connected to VCORE_PG signal for filtering and decoupling. | | 2 | 2 | GND | ✅ | Connected to GND for signal filtering return path. | </details> <details> <summary><b>C65</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND for signal filtering return path. | | 2 | 2 | VCORE_GFX_PG | ✅ | Connected to VCORE_GFX_PG combined power good signal for filtering and decoupling. | </details> <details> <summary><b>R849</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC power rail to provide enable signal source. | | 2 | 2 | $23N5607 | ✅ | Connected to U25 EN pin through net $23N5607, providing enable control. | </details> <details> <summary><b>R851</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ✅ | Connected to U25 EN pin through net $23N5607, providing pull-down function. | | 2 | 2 | GND | ✅ | Connected to GND, completing the pull-down path. | </details> <details> <summary><b>C433</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ✅ | Connected to U25 EN pin through net $23N5607, providing filtering. | | 2 | 2 | GND | ✅ | Connected to GND, completing the bypass path. | </details> <details> <summary><b>C50</b> - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0008) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3733 | ✅ | Connected to R154 pin 2, forming the positive terminal of the bootstrap capacitor that charges through R154 from the BST pin. | | 2 | 2 | $23N3731 | ✅ | Connected to U25 pin 10 (SW1), referencing the bootstrap capacitor to the switch node as required for proper high-side gate driver operation. | </details> <details> <summary><b>R154</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1130-0234) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3711 | ✅ | Connected to U25 pin 8 (BST) as part of the bootstrap circuit for the high-side gate driver. | | 2 | 2 | $23N3733 | ✅ | Connected to C50 pin 1, forming the intermediate node in the bootstrap circuit between the BST pin and the bootstrap capacitor. | </details> <details> <summary><b>R79</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Connected to VCORE_PG signal, which is the system power good signal that is OR-ed with other power good signals through D4. | | 2 | 2 | $23N3753 | ✅ | Connected to U25 pin 6 (VR_RDY), which is the voltage regulator ready output signal indicating the regulator has reached regulation. | </details> <details> <summary><b>R166</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1130-0234) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB power rail, providing input to series resistor feeding U25 VCC pin. | | 2 | 2 | $23N3860 | ✅ | Connected to U25 pin 47 (VCC) through net $23N3860, with C24 providing decoupling to AGND-VCORE. | </details> <details> <summary><b>C24</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3860 | ✅ | Connected to U25 VCC supply net $23N3860 for decoupling. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing decoupling return path through analog ground. | </details> <details> <summary><b>C48</b> - 2232-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2232-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3625 | ✅ | Connected to U25 VCCP supply net $23N3625 for decoupling. | | 2 | 2 | GND | ✅ | Connected to GND, providing decoupling return path through main ground. | </details> <details> <summary><b>R845</b> - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1130-0193) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB power rail, providing input to series resistor feeding U25 VCCP pin. | | 2 | 2 | $23N3625 | ✅ | Connected to U25 pin 33 (VCCP) through net $23N3625, with C48 providing decoupling to GND. | </details> <details> <summary><b>R70</b> - 1120-0289 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0289) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3477 | ✅ | Connected to U25 VBOOT pin (pin 31) for configuration. Text note indicates VBOOT should be 1.1V and sets I2C address to 0x0. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE (analog ground), completing the VBOOT configuration resistor divider. | </details> <details> <summary><b>R93</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0351) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2930 | ✅ | Connected to U25 FREQ pin (pin 41) to set switching frequency. Text note indicates target frequency of 650kHz. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE (analog ground), completing the frequency-setting resistor divider. | </details> <details> <summary><b>R146</b> - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0338) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3683 | ✅ | Connected to U25 pin 36 (IOUT) for current monitoring. Forms an RC filter with C47 to filter the current output signal. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing the return path for the current monitoring circuit. | </details> <details> <summary><b>C47</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3683 | ✅ | Connected to U25 pin 36 (IOUT) along with R146. Forms an RC filter to reduce noise on the current monitoring output. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing the AC return path for the filter capacitor. | </details> <details> <summary><b>R105</b> - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0115) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3681 | ✅ | Connected to U25 pin 35 (IMAX) to set the maximum current limit. A text note indicates the target is 14A. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing the return path for the current limit setting circuit. | </details> <details> <summary><b>C52</b> - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2240-0005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3990 | ✅ | Connected to intermediate node $23N3990 of the RC snubber. Forms the capacitive element that works with R168 to dampen switching node ringing. | | 2 | 2 | GND | ✅ | Connected to GND. Completes the snubber circuit path from the switching node to ground. | </details> <details> <summary><b>R168</b> - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1141-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Connected to VCORE-SW switching node. This is the input side of an RC snubber circuit used to dampen ringing and reduce EMI on the switching node. | | 2 | 2 | $23N3990 | ✅ | Connected to intermediate node $23N3990 between the snubber resistor and capacitor. Forms the RC junction of the snubber network. | </details> <details> <summary><b>U26</b> - NCP81109GMNTXG ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | SW1 | $24N3595 | ❌ | <details><summary>SW1 is connected only to the bootstrap capacitor return ($24N3595) and is isolated from the main switch node (VGFX-SW). This appears incorrect as phase 1 should be connected to the output if it is intended to be active.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="37.39,41.84,44.89,49.34" aspect-ratio="1.29" } <ul><li>Pin 10 (SW1) is connected to net $24N3595 <em>(from schematic)</em></li><li>Net $24N3595 connects only to bootstrap capacitor C186 pin 2 and pin 10 (SW1) <em>(from schematic)</em></li><li>Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW <em>(from schematic)</em></li><li>Net VGFX-SW connects to inductor L4 pin 1, which connects to output +VGFX <em>(from schematic)</em></li><li>There is no connection between net $24N3595 (SW1) and net VGFX-SW <em>(from schematic)</em></li><li>Bootstrap circuit is present: pin 8 (BST) -&gt; $24N3593 -&gt; R228 -&gt; $24N3596 -&gt; C186 -&gt; $24N3595 -&gt; pin 10 (SW1) <em>(from schematic)</em></li><li>Pin 7 (VIN1) is connected to +5VSB_SW, indicating phase 1 is powered <em>(from schematic)</em></li><li>The presence of a populated bootstrap circuit (R228, C186) suggests phase 1 was intended to be active <em>(reasoning)</em></li><li>In a multiphase buck converter, all active switch nodes should be connected to share load current through their respective inductors to the common output <em>(reasoning)</em></li><li>Only one inductor (L4) is present, connecting VGFX-SW to +VGFX, suggesting all active phases should connect to VGFX-SW <em>(reasoning)</em></li><li>If phase 1 were intentionally disabled, the bootstrap circuit components would typically be unpopulated <em>(reasoning)</em></li><li>The isolation of SW1 from VGFX-SW while maintaining the bootstrap circuit and VIN1 connection is inconsistent and likely a design error <em>(reasoning)</em></li><li>SW1 should be connected to VGFX-SW to enable phase 1 to contribute to the output <em>(reasoning)</em></li></ul></details> | | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT is a thermal alert output connected to the system-level VR_HOT_L signal for thermal monitoring. | | 2 | SDIO | $24N3490 | ✅ | SDIO is the SVID data line with proper series termination (16.9Ω) and pull-up resistor (69.8Ω) to +V1P0S for bidirectional communication. | | 3 | ALERT | $24N3492 | ✅ | ALERT is the SVID alert output with 0Ω series resistor and DNI pull-up, properly configured for open-drain signaling. | | 4 | SCLK | $24N3491 | ✅ | SCLK is the SVID clock line with proper series termination (20.0Ω) and pull-up resistor (69.8Ω) to +V1P0S. | | 5 | GND | AGND-VGFX | ✅ | GND is the analog ground pin properly connected to AGND-VGFX, which is tied to system GND through a 0Ω jumper for star grounding. | | 6 | VR_RDY | $24N3598 | ✅ | VR_RDY is the power good output with 0Ω series resistor, pull-up to +VCC3 (1.91kΩ), and bypass capacitor, properly configured for system power sequencing. | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 are input power pins all connected to +5VSB_SW with appropriate bulk and decoupling capacitors (22µF and 0.1µF) for stable input supply. | | 8 | BST | $24N3593 | ✅ | BST is the bootstrap pin with proper bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) connected to SW1 for high-side gate driver supply. | | 9 | GH | | ✅ | GH is the high-side gate driver output with no visible external connection. This may indicate integrated MOSFETs, internal connections, or connections on another schematic page. | | 18 | SW2 | VGFX-SW | ✅ | SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present. | | 25 | SW3 | VGFX-SW | ✅ | SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present. | | 26 | SW4 | VGFX-SW | ✅ | SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present. | | 27 | SW5 | VGFX-SW | ✅ | SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present. | | 28 | SW6 | VGFX-SW | ✅ | SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present. | | 29 | SW7 | VGFX-SW | ✅ | SW2-SW7 are switch node outputs all paralleled together on VGFX-SW, feeding output inductor L4 (470nH) to generate +VGFX output. Proper snubber network (R231 2.2Ω, C187 1000pF) is present. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 are power ground pins all properly connected to system GND for low-impedance power return path. | | 30 | GL | | ✅ | GL is the low-side gate driver output with no visible external connection. This may indicate integrated MOSFETs, internal connections, or connections on another schematic page. | | 31 | VBOOT | $24N3564 | ✅ | VBOOT is the bootstrap voltage sense pin with 100kΩ pull-down to AGND-VGFX for monitoring bootstrap voltage level. | | 32 | GND1 | AGND-VGFX | ✅ | GND1 is an analog ground pin properly connected to AGND-VGFX for star grounding topology. | | 33 | VCCP | $24N3578 | ✅ | VCCP is the internal charge pump/LDO supply pin with proper input from +5VSB through 1Ω current limiting resistor and 4.7µF decoupling capacitor. | | 34 | TSENSE | $24N3584 | ✅ | TSENSE is the temperature sense input with proper thermistor network (TH4 100kΩ@25C, R226 14.0kΩ) and bypass capacitor for thermal monitoring and protection. | | 35 | IMAX | $24N3588 | ✅ | IMAX sets the maximum current limit to 14A per phase using R207 (44.2kΩ) to AGND-VGFX, as indicated by nearby text note. | | 36 | IOUT | $24N3589 | ✅ | IOUT is the output current reporting pin with proper RC filter (R227 16.5kΩ, C184 470pF) to AGND-VGFX for current telemetry. | | 37 | ILIM | VGFX-ILIM | ✅ | ILIM is the current limit threshold pin connected through R204 (15.0kΩ) to VGFX-CSCOMP for current loop compensation and limiting. | | 38 | CSCOMP | VGFX-CSCOMP | ✅ | CSCOMP is the current sense compensation pin with proper compensation network including capacitors (C113 470pF, C166 2200pF), resistors (R205 75.0kΩ, R204 15.0kΩ), and thermistor (TH3) for temperature-compensated current sensing. | | 39 | CSSUM | VGFX-CSSUM | ✅ | CSSUM is the current sense sum input with resistor network (R224 100kΩ, R223 165kΩ) for DCR current sensing from the switch node through SP2. | | 40 | CSREF | VGFX-CSREF | ✅ | CSREF is the current sense reference pin connected through R225 (10.0Ω) to output voltage via SP1, with C167 (1000pF) bypass, implementing DCR current sensing reference. | | 41 | FREQ | $24N3542 | ✅ | FREQ sets the switching frequency to 650kHz using R203 (18.7kΩ) to AGND-VGFX, as confirmed by nearby text note. | | 42 | COMP | VGFX-COMP | ✅ | COMP is the voltage loop compensation pin with Type III compensation network (C62 47pF, C64 2200pF, R198 3.01kΩ) for stable voltage regulation. | | 43 | FB | VGFX-FB | ✅ | FB is the feedback input with resistor divider (R198 3.01kΩ, R199 1.00kΩ) and compensation capacitors (C62 47pF, C63 220pF) setting the output voltage regulation point. | | 44 | DIFFOUT | VGFX-DIFFOUT | ✅ | DIFFOUT is the differential amplifier output connected through resistors (R199 1.00kΩ, R200 47Ω) to FB and compensation network for remote voltage sensing. | | 45 | VSN | VR-VGFX-VSN | ✅ | VSN is the negative remote sense input connected through R169 (10.0Ω) to a ground reference divider (R201 100Ω, R69 0Ω) for differential voltage sensing. | | 46 | VSP | VR-VGFX-VSP | ✅ | VSP is the positive remote sense input connected through R202 (100Ω) to +VGFX and through R68 (0Ω) to VCCGT_SENSE for remote voltage regulation at the load. | | 47 | VCC | $24N3610 | ✅ | VCC is the main supply input with proper input filtering through R229 (2.20Ω) from +5VSB and C53 (1.0µF) decoupling to AGND-VGFX. | | 48 | EN | $24N6011 | ✅ | EN is the enable input with proper configuration: 0Ω jumper from +VCC for enable, 10kΩ pull-down, and 0.1µF bypass capacitor. | | 49 | GND_PAD | AGND-VGFX | ✅ | GND_PAD is the exposed thermal/ground pad properly connected to AGND-VGFX for thermal dissipation and electrical grounding. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN_PAD is the exposed input voltage pad properly connected to +5VSB_SW for additional input current capability and thermal management. | | 51 | SW_PAD | VGFX-SW | ✅ | SW_PAD is the exposed switch node pad properly connected to VGFX-SW for additional current capability and thermal management of the switch nodes. | </details> <details> <summary><b>C76</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal connected to +VGFX output rail. Polarity is correct for a bulk output capacitor. | | 2 | N | GND | ✅ | Negative terminal connected to GND. Polarity is correct, but the 2V voltage rating is marginal for this application and provides minimal safety margin. | </details> <details> <summary><b>C77</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal connected to +VGFX output rail. Polarity is correct for a bulk output capacitor. | | 2 | N | GND | ✅ | Negative terminal connected to GND. Polarity is correct, but the 2V voltage rating is marginal for this application and provides minimal safety margin. | </details> <details> <summary><b>SP1</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Connected to +VGFX output rail. This provides the output voltage reference for DCR current sensing. | | 2 | 2 | $24N3559 | ✅ | Connected to $24N3559, which connects through R225 (10Ω) to VGFX-CSREF pin of the controller. This forms the reference path for DCR current sensing. | </details> <details> <summary><b>SP2</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to VGFX-SW switching node. This provides the switching node voltage reference for DCR current sensing. | | 2 | 2 | $24N3558 | ✅ | Connected to $24N3558, which connects through R224 (100kΩ) to VGFX-CSSUM pin of the controller. This forms the sum path for DCR current sensing. | </details> <details> <summary><b>L4</b> - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Pin 1 connects to the switching node VGFX-SW from the multiphase buck controller U26. This is the standard input connection for a buck converter output inductor. | | 2 | 2 | +VGFX | ✅ | Pin 2 connects to the output rail +VGFX and is filtered by multiple output capacitors. The inductor is rated for 17.5A, but a text note indicates IMAX = 24A, which may exceed the inductor's rating depending on whether 17.5A refers to saturation current or thermal rating. | </details> <details> <summary><b>R198</b> - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3524 | ✅ | Connected to internal node $24N3524, which connects to C64 pin 2, forming a series RC network with C64 from COMP to FB. | | 2 | 2 | VGFX-FB | ✅ | Connected to VGFX-FB feedback net, which connects to U26 pin 43 (FB), completing the compensation network. | </details> <details> <summary><b>R199</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | Connected to VGFX-FB feedback net, forming part of the differential sensing network between FB and DIFFOUT. | | 2 | 2 | VGFX-DIFFOUT | ✅ | Connected to VGFX-DIFFOUT net, which connects to U26 pin 44 (DIFFOUT), completing the differential sensing path. | </details> <details> <summary><b>R200</b> - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3522 | ✅ | Connected to internal node $24N3522, which connects to C63 pin 2, forming a series RC network in the differential path. | | 2 | 2 | VGFX-DIFFOUT | ✅ | Connected to VGFX-DIFFOUT net, completing the differential sensing network to U26 pin 44. | </details> <details> <summary><b>C62</b> - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | Connected to VGFX-COMP compensation pin, providing direct high-frequency feedback path. | | 2 | 2 | VGFX-FB | ✅ | Connected to VGFX-FB feedback net, completing the high-frequency compensation path. | </details> <details> <summary><b>C63</b> - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | Connected to VGFX-FB feedback net, forming part of the differential sensing filter network. | | 2 | 2 | $24N3522 | ✅ | Connected to internal node $24N3522, which connects to R200 pin 1, forming a series RC network. | </details> <details> <summary><b>C64</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | Connected to VGFX-COMP compensation pin, forming the main compensation capacitor. | | 2 | 2 | $24N3524 | ✅ | Connected to internal node $24N3524, which connects to R198 pin 1, forming a series RC compensation network. | </details> <details> <summary><b>R225</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Connected to VGFX-CSREF pin of the controller for current sense reference. | | 2 | 2 | $24N3559 | ✅ | Connected through net $24N3559 and short SP1 to the output voltage +VGFX, providing a reference for DCR current sensing. | </details> <details> <summary><b>C113</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP for current loop compensation. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C166. | </details> <details> <summary><b>R205</b> - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP for current sense compensation. | | 2 | 2 | $24N3557 | ✅ | Connected to intermediate node $24N3557, forming a parallel path with thermistor TH3 for temperature compensation. | </details> <details> <summary><b>C166</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP for current loop compensation. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C113. | </details> <details> <summary><b>C167</b> - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Connected to VGFX-CSREF for filtering the current sense reference. | | 2 | 2 | GND | ✅ | Connected to GND to provide AC filtering for the CSREF pin. | </details> <details> <summary><b>R224</b> - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM pin of the controller U26 for current sensing. | | 2 | 2 | $24N3558 | ✅ | Connected through net $24N3558 and short SP2 to the switching node VGFX-SW for DCR current sensing. | </details> <details> <summary><b>R204</b> - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-ILIM | ✅ | Connected to VGFX-ILIM pin of the controller for current limit setting. | | 2 | 2 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP to link the current limit setting to the compensation network. | </details> <details> <summary><b>TH3</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP (U26 pin 38). Part of current loop compensation network, in parallel with R205 (75K) to provide temperature-dependent compensation. | | 2 | 2 | $24N3557 | ✅ | Connected to $24N3557, which is the junction between R205 and R223 in the current sense compensation network. | </details> <details> <summary><b>R223</b> - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3557 | ✅ | Connected to the intermediate node $24N3557 which links to the CSCOMP compensation network. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM to provide feedback from the current sense sum to the compensation network. | </details> <details> <summary><b>C168</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | Connected to $24N3584 (U26 pin 34 TSENSE), providing filtering for the temperature sense signal. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX (analog ground), providing proper ground reference for filtering. | </details> <details> <summary><b>R178</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | Connected to $24N3584, which connects to U26 pin 34 (TSENSE) and C168 for filtering. | | 2 | 2 | $24N3583 | ✅ | Connected to $24N3583, which connects to the TH4/R226 voltage divider network. | </details> <details> <summary><b>TH4</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | Connected to $24N3583, which connects through R178 (0 ohm) to U26 pin 34 (TSENSE). Forms voltage divider with R226 (14K) for temperature sensing. | | 2 | 2 | GND | ✅ | Connected to GND, completing the voltage divider circuit for temperature sensing. | </details> <details> <summary><b>R226</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | Connected to $24N3583, forming the lower part of the voltage divider with TH4 for temperature sensing. | | 2 | 2 | GND | ✅ | Connected to GND, completing the voltage divider to ground. | </details> <details> <summary><b>R195</b> - 1120-0330 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ❌ | <details><summary>Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="17.39,32.43,24.89,39.93" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to +V1P0S (1.0V standby supply rail) <em>(from schematic)</em></li><li>Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) <em>(from schematic)</em></li><li>This resistor forms a pull-up for the SVID data line <em>(reasoning)</em></li><li>SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines <em>(reasoning)</em></li><li>Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ <em>(reasoning)</em></li><li>The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) <em>(reasoning)</em></li><li>The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up <em>(reasoning)</em></li><li>The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity <em>(reasoning)</em></li></ul></details> | | 2 | 2 | SVID_DATA-R | ❌ | <details><summary>Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="17.39,34.20,24.89,41.70" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to +V1P0S (1.0V standby supply rail) <em>(from schematic)</em></li><li>Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) <em>(from schematic)</em></li><li>This resistor forms a pull-up for the SVID data line <em>(reasoning)</em></li><li>SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines <em>(reasoning)</em></li><li>Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ <em>(reasoning)</em></li><li>The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) <em>(reasoning)</em></li><li>The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up <em>(reasoning)</em></li><li>The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R196</b> - 1120-0330 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ❌ | <details><summary>Pull-up resistor for SVID alert line, marked DNI (Do Not Install). Without this pull-up, the ALERT line will float when not actively driven, which may cause issues since R67 connects this signal to U26 pin 3 (ALERT).</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="18.98,32.43,26.48,39.93" aspect-ratio="1.29" } <ul><li>Pin 1 would connect to +V1P0S (1.0V standby supply rail) if populated <em>(from schematic)</em></li><li>Pin 2 would connect to SVID_ALERT-R if populated <em>(from schematic)</em></li><li>This component is marked DNI (Do Not Install) and is electrically absent from the circuit <em>(from schematic)</em></li><li>R67 (0Ω jumper) connects SVID_ALERT-R through to U26 pin 3 (ALERT), indicating the alert signal path is intended to be active <em>(from schematic)</em></li><li>SVID alert lines typically require pull-up resistors similar to data and clock lines, as they use open-drain outputs <em>(reasoning)</em></li><li>Without a pull-up resistor, the ALERT line will float when not actively driven, which can cause undefined logic levels and potential noise sensitivity <em>(reasoning)</em></li><li>If the alert function is intended to be used (suggested by R67 being populated), R196 should be populated with a pull-up resistor in the 1kΩ to 10kΩ range <em>(reasoning)</em></li><li>If the alert function is not used, the DNI status may be acceptable, though best practice would be to leave the pin unconnected or ensure it has a defined state <em>(reasoning)</em></li></ul></details> | | 2 | 2 | SVID_ALERT-R | ❌ | <details><summary>Pull-up resistor for SVID alert line, marked DNI (Do Not Install). Without this pull-up, the ALERT line will float when not actively driven, which may cause issues since R67 connects this signal to U26 pin 3 (ALERT).</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="18.98,34.20,26.48,41.70" aspect-ratio="1.29" } <ul><li>Pin 1 would connect to +V1P0S (1.0V standby supply rail) if populated <em>(from schematic)</em></li><li>Pin 2 would connect to SVID_ALERT-R if populated <em>(from schematic)</em></li><li>This component is marked DNI (Do Not Install) and is electrically absent from the circuit <em>(from schematic)</em></li><li>R67 (0Ω jumper) connects SVID_ALERT-R through to U26 pin 3 (ALERT), indicating the alert signal path is intended to be active <em>(from schematic)</em></li><li>SVID alert lines typically require pull-up resistors similar to data and clock lines, as they use open-drain outputs <em>(reasoning)</em></li><li>Without a pull-up resistor, the ALERT line will float when not actively driven, which can cause undefined logic levels and potential noise sensitivity <em>(reasoning)</em></li><li>If the alert function is intended to be used (suggested by R67 being populated), R196 should be populated with a pull-up resistor in the 1kΩ to 10kΩ range <em>(reasoning)</em></li><li>If the alert function is not used, the DNI status may be acceptable, though best practice would be to leave the pin unconnected or ensure it has a defined state <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R197</b> - 1120-0330 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ❌ | <details><summary>Pull-up resistor for SVID clock line connecting +V1P0S to SVID_CLK-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="20.58,32.43,28.08,39.93" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to +V1P0S (1.0V standby supply rail) <em>(from schematic)</em></li><li>Pin 2 is connected to SVID_CLK-R, which connects through series resistor R194 to U26 pin 4 (SCLK) <em>(from schematic)</em></li><li>This resistor forms a pull-up for the SVID clock line <em>(reasoning)</em></li><li>SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines <em>(reasoning)</em></li><li>Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ <em>(reasoning)</em></li><li>The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) <em>(reasoning)</em></li><li>The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up <em>(reasoning)</em></li><li>The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity <em>(reasoning)</em></li></ul></details> | | 2 | 2 | SVID_CLK-R | ❌ | <details><summary>Pull-up resistor for SVID clock line connecting +V1P0S to SVID_CLK-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="20.58,34.20,28.08,41.70" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to +V1P0S (1.0V standby supply rail) <em>(from schematic)</em></li><li>Pin 2 is connected to SVID_CLK-R, which connects through series resistor R194 to U26 pin 4 (SCLK) <em>(from schematic)</em></li><li>This resistor forms a pull-up for the SVID clock line <em>(reasoning)</em></li><li>SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines <em>(reasoning)</em></li><li>Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ <em>(reasoning)</em></li><li>The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) <em>(reasoning)</em></li><li>The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up <em>(reasoning)</em></li><li>The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>C61</b> - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VGFX-VSP | ✅ | Connected to VR-VGFX-VSP net. Component is DNI (Do Not Install), so it does not affect the circuit electrically. | | 2 | 2 | VR-VGFX-VSN | ✅ | Connected to VR-VGFX-VSN net. Component is DNI, so it does not load the circuit. | </details> <details> <summary><b>C104</b> - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | Connected to internal node $24N3528. Component is DNI, so it does not affect the circuit. | | 2 | 2 | VR-VGFX-VSN | ✅ | Connected to VR-VGFX-VSN net. Component is DNI, so it does not load the circuit. | </details> <details> <summary><b>R68</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCCGT_SENSE | ✅ | 0Ω jumper connects VCCGT_SENSE to VSP sense input. Creates imbalanced differential pair with VSN path which has 10Ω (R169). | | 2 | 2 | VR-VGFX-VSP | ✅ | 0Ω jumper connects VCCGT_SENSE to VSP sense input. Creates imbalanced differential pair with VSN path which has 10Ω (R169). | </details> <details> <summary><b>R69</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0Ω jumper connects GND to intermediate node $24N3528. In parallel with R201 (100Ω), providing the dominant low-resistance path. | | 2 | 2 | $24N3528 | ✅ | 0Ω jumper connects GND to intermediate node $24N3528. In parallel with R201 (100Ω), providing the dominant low-resistance path. | </details> <details> <summary><b>R201</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 100Ω resistor connects GND to intermediate node $24N3528. In parallel with R69 (0Ω) which dominates, making this resistor's contribution minimal. | | 2 | 2 | $24N3528 | ✅ | 100Ω resistor connects GND to intermediate node $24N3528. In parallel with R69 (0Ω) which dominates, making this resistor's contribution minimal. | </details> <details> <summary><b>R202</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | 100Ω resistor connects +VGFX to VSP sense input. In parallel with R68 (0Ω) which dominates the connection, making this resistor's contribution minimal. | | 2 | 2 | VR-VGFX-VSP | ✅ | 100Ω resistor connects +VGFX to VSP sense input. In parallel with R68 (0Ω) which dominates the connection, making this resistor's contribution minimal. | </details> <details> <summary><b>R169</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | 10Ω resistor in VSN path creates imbalanced differential pair with VSP path (0Ω through R68). May be intentional for filtering or current limiting. | | 2 | 2 | VR-VGFX-VSN | ✅ | 10Ω resistor in VSN path creates imbalanced differential pair with VSP path (0Ω through R68). May be intentional for filtering or current limiting. | </details> <details> <summary><b>R850</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC power rail. This pin sources the enable signal when the jumper is populated. | | 2 | 2 | $24N6011 | ✅ | Connected to net $24N6011, which drives the enable pin of U26. This forms part of the enable circuit. | </details> <details> <summary><b>R852</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to net $24N6011, providing a pull-down path for the enable circuit. | | 2 | 2 | GND | ✅ | Connected to GND, completing the pull-down path for the enable circuit. | </details> <details> <summary><b>C434</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to net $24N6011, providing decoupling and filtering for the enable signal. | | 2 | 2 | GND | ✅ | Connected to GND, completing the decoupling path for the enable signal. | </details> <details> <summary><b>C60</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG net to provide signal filtering and noise suppression. | | 2 | 2 | GND | ✅ | Connected to GND to complete the filtering path for the power good signal. | </details> <details> <summary><b>R184</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG net, which is the conditioned power good signal with pull-up and filtering. | | 2 | 2 | $24N3598 | ✅ | Connected to U26 pin 6 (VR_RDY), the voltage regulator power ready output signal. | </details> <details> <summary><b>R230</b> - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 power rail to provide pull-up voltage source for the power good signal. | | 2 | 2 | VGFX_PG | ✅ | Connected to VGFX_PG net, providing pull-up function for the power good signal. | </details> <details> <summary><b>R228</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3593 | ✅ | Connected to the BST (bootstrap) pin of U26 (NCP81109GMNTXG voltage regulator). This is the input side of the bootstrap charging resistor. | | 2 | 2 | $24N3596 | ✅ | Connected to the bootstrap capacitor C186 pin 1. This is the output side of the bootstrap charging resistor. | </details> <details> <summary><b>C186</b> - 2222-0008 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | 2 | $24N3595 | ❌ | <details><summary>Connected to SW1 (U26 pin 10), but should be connected to VGFX-SW (the main switching node). The bootstrap capacitor must reference the actual switching node where the inductor connects for proper gate driver operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="32.39,42.43,39.89,49.93" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to net $24N3595 <em>(from schematic)</em></li><li>Net $24N3595 connects only to U26 pin 10 (SW1) <em>(from schematic)</em></li><li>The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) <em>(from schematic)</em></li><li>The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node where power conversion occurs <em>(from schematic)</em></li><li>Net $24N3595 (SW1) is isolated from VGFX-SW and has no other connections besides U26 pin 10 and C186 pin 2 <em>(from schematic)</em></li><li>In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET <em>(reasoning)</em></li><li>The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects to extract power <em>(reasoning)</em></li><li>The bootstrap capacitor charges when the low-side FET is on (switching node is low) and provides voltage to drive the high-side FET gate when it turns on <em>(reasoning)</em></li><li>For the bootstrap circuit to function, the capacitor must be referenced to the actual switching node voltage, not to an isolated pin <em>(reasoning)</em></li><li>Since the inductor L4 connects to VGFX-SW, this is the actual switching node, and the bootstrap capacitor should be connected between BST and VGFX-SW <em>(reasoning)</em></li><li>The current configuration with C186 pin 2 connected to the isolated SW1 pin will not provide proper bootstrap voltage for the gate driver, as SW1 does not follow the switching node voltage <em>(reasoning)</em></li><li>Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit <em>(reasoning)</em></li></ul></details> | | 1 | 1 | $24N3596 | ✅ | Connected to R228 pin 2, forming the intermediate node in the bootstrap charging circuit between the BST pin and the bootstrap capacitor. | </details> <details> <summary><b>R846</b> - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This pin incorrectly attempts to supply power to the VCCP pin of U26, which is an internal LDO output that should not be externally driven. | | 2 | 2 | $24N3578 | ✅ | Connected to net $24N3578, which feeds the VCCP pin (pin 33) of U26. This connection is incorrect as VCCP is an internal LDO output that should not be driven from an external source. | </details> <details> <summary><b>R229</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This pin sources power for the VCC bias supply of U26 through the 2.2 ohm current-limiting resistor. | | 2 | 2 | $24N3610 | ✅ | Connected to net $24N3610, which supplies U26 pin 47 (VCC) and is bypassed by C53. This provides the bias supply voltage for the controller IC. | </details> <details> <summary><b>C185</b> - 2232-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3578 | ✅ | Connected to net $24N3578, which is the VCCP charge pump supply for U26 after current limiting by R846. This pin provides bypass capacitance for the charge pump supply. | | 2 | 2 | GND | ✅ | Connected to GND power ground. This provides the return path for the VCCP bypass capacitor, referenced to power ground to keep charge pump switching currents separate from the analog ground. | </details> <details> <summary><b>C53</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3610 | ✅ | Connected to net $24N3610, which is the VCC supply for U26 after current limiting by R229. This pin provides bypass capacitance for the controller bias supply. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX analog ground. This provides the return path for the VCC bypass capacitor, correctly referenced to the analog ground plane. | </details> <details> <summary><b>R203</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3542 | ✅ | Pin 1 connects to the FREQ pin (pin 41) of U26 (NCP81109GMNTXG) to set the switching frequency. A nearby text note indicates the target frequency is 650 kHz. | | 2 | 2 | AGND-VGFX | ✅ | Pin 2 connects to AGND-VGFX, which is the analog ground reference for the VGFX voltage regulator circuit. | </details> <details> <summary><b>R227</b> - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | Connected to U26 pin 36 (IOUT) for current monitoring. Forms part of the current sense output circuit with C184. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, the analog ground reference for the voltage regulator. | </details> <details> <summary><b>C184</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | Connected to U26 pin 36 (IOUT) for filtering the current monitoring signal. Works in conjunction with R227. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, the analog ground reference for the voltage regulator. | </details> <details> <summary><b>R207</b> - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3588 | ✅ | Connected to U26 pin 35 (IMAX) to set the maximum current limit. A nearby text note indicates the target is 14A. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, the analog ground reference for the voltage regulator. | </details> <details> <summary><b>C187</b> - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3623 | ✅ | Connected to intermediate node of RC snubber circuit from R231 pin 2. Forms the capacitive element of the snubber to ground. | | 2 | 2 | GND | ✅ | Connected to GND. Completes the RC snubber circuit path from the switching node to ground. | </details> <details> <summary><b>R231</b> - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to VGFX-SW switching node. Forms the series element of an RC snubber circuit to dampen high-frequency ringing on the switching node. | | 2 | 2 | $24N3623 | ✅ | Connected to intermediate node of RC snubber circuit, connecting to C187 pin 1. This forms the junction between the resistor and capacitor in the snubber. | </details> <details> <summary><b>R66</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to main power ground (GND). This is the expected connection for one side of the ground jumper. | | 2 | 2 | AGND-VGFX | ✅ | Connected to analog ground (AGND-VGFX). This is the expected connection for the other side of the ground jumper. | </details> <details> <summary><b>U41</b> - RT8207 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.richtek.com/SaveDownload.aspx?specid=RT8207P) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/RT8207) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VTTGND | GND | ✅ | VTTGND is correctly connected to GND for the VTT LDO power ground. | | 2 | VTTSNS | +VDIMM_VTT | ✅ | VTTSNS is correctly connected to +VDIMM_VTT for remote voltage sensing at the output capacitors. | | 3 | GND | GND | ✅ | GND is correctly connected to system ground for analog ground reference. | | 4 | MODE | GND | ✅ | MODE is connected to GND, which is a typical configuration for mode selection pins. | | 5 | VTTREF | $25N769 | ✅ | VTTREF is correctly connected to a bypass capacitor (C342, 0.22µF) to GND for stable buffered reference operation. | | 6 | DEM | $25N1291 | ✅ | DEM is connected to a 10K pull-up resistor to +5VSB, likely for diode emulation mode control. | | 8 | VDDQ | +VDIMM | ✅ | VDDQ is correctly connected to the +VDIMM output rail for reference input and feedback. | | 9 | FB | $25N987 | ✅ | FB is correctly connected to a resistive voltage divider (R814/R815) for adjustable output voltage setting at 1.35V (DDR3L). | | 10 | S3 | EN_VTT | ✅ | S3 is correctly connected to EN_VTT (derived from SLP_S3_L) for VTT output state control. | | 11 | S5 | EN_VDDQ | ✅ | S5 is correctly connected to EN_VDDQ (derived from SLP_S4_L) for overall power state control. | | 12 | TON | $25N1081 | ✅ | TON is correctly connected to +5VSB through R816 (464K) to set the switching frequency. However, there is a significant discrepancy between the actual resistor value and the schematic design note which specifies 806K for 285kHz operation, resulting in approximately 504kHz actual switching frequency instead of the intended 285kHz. | | 13 | PGOOD | DRAM_PWROK | ✅ | PGOOD is correctly connected as an open-drain output to DRAM_PWROK with an external pull-up resistor. | | 14 | VDD | $25N1195 | ✅ | VDD is correctly connected to a filtered analog supply with 2.2Ω resistor from +5VSB and 1µF bypass capacitor. | | 15 | VDDP | +5VSB | ✅ | VDDP is correctly connected to +5VSB as the main supply for gate drivers. | | 16 | CS | $25N1238 | ✅ | CS is correctly connected to VDD through a 3.83K resistor for current limit threshold setting. | | 18 | PGND | GND | ✅ | PGND is correctly connected to system ground for low-side MOSFET power ground. | | 19 | LGATE | $25N901 | ✅ | LGATE is correctly connected to the low-side MOSFET gate (Q102 pin 8). | | 20 | PHASE | DDR_PHASE | ✅ | PHASE is correctly connected to the switch node (Q102 pin 9) and output inductor (L11). | | 21 | UGATE | $25N897 | ✅ | UGATE is correctly connected to the high-side MOSFET gate (Q102 pin 1). | | 22 | BOOT | $25N771 | ✅ | BOOT is connected to a bootstrap network with C309 (0.1µF) and R298 (4.7Ω). The bootstrap capacitor is significantly smaller than the 1µF recommended by the datasheet, which may cause insufficient gate drive voltage. | | 23 | VLDOIN | +VDIMM | ✅ | VLDOIN is correctly connected to +VDIMM for tracking discharge mode operation. | | 24 | VTT | +VDIMM_VTT | ✅ | VTT is correctly connected to +VDIMM_VTT output with appropriate output capacitors (20µF total). | | 25 | GND_PAD | GND | ✅ | GND_PAD is correctly connected to system ground for thermal dissipation. | </details> <details> <summary><b>Q102</b> - FDMS3604S ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pub/Collateral/FDMS3604S-D.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/FDMS3604S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Q1G | $25N897 | ✅ | Q1G (high-side gate) is correctly connected to the controller's UGATE output (U41 pin 21) to drive the control MOSFET. | | 2 | VIN_A | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (drain pins of Q1) are correctly connected to the DDR3L_VIN input rail with appropriate input decoupling capacitors. | | 3 | VIN_B | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (drain pins of Q1) are correctly connected to the DDR3L_VIN input rail with appropriate input decoupling capacitors. | | 4 | VIN_C | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (drain pins of Q1) are correctly connected to the DDR3L_VIN input rail with appropriate input decoupling capacitors. | | 5 | PGND_A | GND | ✅ | PGND_A, PGND_B, PGND_C (source pins of Q2) are correctly connected to GND for the synchronous MOSFET return path. | | 6 | PGND_B | GND | ✅ | PGND_A, PGND_B, PGND_C (source pins of Q2) are correctly connected to GND for the synchronous MOSFET return path. | | 7 | PGND_C | GND | ✅ | PGND_A, PGND_B, PGND_C (source pins of Q2) are correctly connected to GND for the synchronous MOSFET return path. | | 8 | Q2G | $25N901 | ✅ | Q2G (low-side gate) is correctly connected to the controller's LGATE output (U41 pin 19) to drive the synchronous MOSFET. | | 9 | PHASE | DDR_PHASE | ✅ | PHASE (switch node) is correctly connected to the output inductor L11 and controller PHASE pin for current sensing in the synchronous buck converter. | </details> <details> <summary><b>L6</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is correctly connected to the +5VSB standby power rail, serving as the input to the ferrite bead filter in parallel with L5. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is correctly connected to the DDR3L_VIN net, providing filtered power to the DDR memory power supply input in parallel with L5. | </details> <details> <summary><b>L5</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is correctly connected to the +5VSB standby power rail, serving as the input to the ferrite bead filter. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is correctly connected to the DDR3L_VIN net, providing filtered power to the DDR memory power supply input. | </details> <details> <summary><b>L11</b> - 125-0004454 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/125-0004454) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | Pin 1 connects to the switching node DDR_PHASE from the RT8207 controller and FDMS3604S MOSFETs. This is the correct connection for the input side of the output filter inductor in this synchronous buck converter. | | 2 | 2 | +VDIMM | ✅ | Pin 2 connects to the +VDIMM output rail. This is the correct connection for the output side of the filter inductor, providing filtered DC power to the DDR memory voltage rail. | </details> <details> <summary><b>R814</b> - 1120-0187 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0187) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Upper resistor in feedback voltage divider, connected to +VDIMM output rail. Forms part of the feedback network for U41 (RT8207) VDDQ regulator. | | 2 | 2 | $25N987 | ✅ | Feedback divider node connected to U41 pin 9 (FB) through net $25N987. Forms the center tap of the voltage divider with R815. | </details> <details> <summary><b>C382</b> - 2220-0047 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0047) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | AC compensation capacitor connected to +VDIMM output rail. Forms high-frequency compensation network in parallel with R814. | | 2 | 2 | $25N987 | ✅ | Feedback node connection providing AC compensation. Connected to U41 pin 9 (FB) through net $25N987. | </details> <details> <summary><b>R815</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N987 | ✅ | Lower resistor in feedback voltage divider, connected to feedback node $25N987. Completes the voltage divider with R814 to set output voltage. | | 2 | 2 | GND | ✅ | Ground connection for feedback voltage divider. Completes the divider path from +VDIMM through R814, R815 to ground. | </details> <details> <summary><b>R817</b> - 1120-0267 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0267) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | Connected to VDD supply pin of U41 through net $25N1195. VDD is supplied from +5VSB through R813 (2.2 ohm) and bypassed by C380 (1uF). | | 2 | 2 | $25N1238 | ✅ | Connected to CS (current sense) pin of U41 through net $25N1238. This connection, along with pin 1 to VDD, forms a resistor divider or reference circuit for overcurrent protection. | </details> <details> <summary><b>C309</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | Connected to the switching node (DDR_PHASE) of the buck converter, which includes the PHASE output of controller U41 and the PHASE pin of MOSFET Q102. This is the correct connection for one side of the bootstrap capacitor. | | 2 | 2 | DDR_BST | ✅ | Connected to intermediate node DDR_BST, which connects through R298 to the BOOT pin of U41. This forms a bootstrap circuit with series damping resistor, which is a valid configuration. | </details> <details> <summary><b>R298</b> - 110-0004467 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004467) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N771 | ✅ | Connected to the BOOT pin of the RT8207 controller (U41 pin 22) via net $25N771. This is the correct connection for the bootstrap circuit series resistor. | | 2 | 2 | DDR_BST | ✅ | Connected to intermediate node DDR_BST, which connects to bootstrap capacitor C309. This completes the bootstrap circuit with series damping resistor configuration. | </details> <details> <summary><b>R813</b> - 110-0004466 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004466) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | Pin 1 connects to net $25N1195, which supplies the VDD pin (pin 14) of U41 (RT8207 DDR power controller). This net is decoupled by C380 (1uF) and also connects to the current sense divider network through R817. | | 2 | 2 | +5VSB | ✅ | Pin 2 connects to the +5VSB power rail, which is the standby 5V supply. This rail also directly supplies U41 pin 15 (VDDP) and other circuit elements through ferrite beads L5 and L6. | </details> <details> <summary><b>R816</b> - 1120-0149 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0149) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | 2 | $25N1081 | ❌ | <details><summary>Connected to U41 pin 12 (TON) to set the switching frequency. However, the resistor value is 464K, which results in approximately 504 kHz switching frequency, not the specified 285 kHz that requires 806K per the design note.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,36.84,35.12,44.34" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to net $25N1081 <em>(from schematic)</em></li><li>Net $25N1081 connects to U41 pin 12 (TON) and C378 pin 2 (DNI) <em>(from schematic)</em></li><li>C378 is marked DNI (Do Not Install), so it is electrically absent and does not affect the circuit <em>(from schematic)</em></li><li>R816 has a value of 464K ohms per part number 1120-0149 <em>(from schematic)</em></li><li>The design note states &#x27;Rton=806K , F=285KHz&#x27; as the intended design specification <em>(from schematic)</em></li><li>The design note provides the formula F= (Vin - 0.5) / 3.85p*Vin*Rton for calculating switching frequency <em>(from schematic)</em></li><li>Using the formula with Vin=5V and Rton=806K: F = (5-0.5)/(3.85e-12*5*806000) = 290 kHz, approximately matching the specified 285 kHz <em>(reasoning)</em></li><li>Using the formula with Vin=5V and the actual Rton=464K: F = (5-0.5)/(3.85e-12*5*464000) = 504 kHz <em>(reasoning)</em></li><li>The actual resistor value of 464K results in a switching frequency of approximately 504 kHz, which is 77% higher than the specified 285 kHz <em>(reasoning)</em></li><li>No other resistors are connected in parallel or series with R816 on the TON pin that would modify the effective resistance <em>(from schematic)</em></li><li>The resistor value should be changed to approximately 806K to meet the design specification of 285 kHz switching frequency <em>(reasoning)</em></li></ul></details> | | 1 | 1 | +5VSB | ✅ | Connected to +5VSB power rail, providing the reference voltage for the TON timing resistor. This connection is correct. | </details> <details> <summary><b>U21</b> - LDO_ULD_3A_SO8 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P8S_PGD | ✅ | PGOOD pin is correctly connected to +V1P8S_PGD net with pull-up resistor R23 (4.7K) to +V1P8S output. | | 2 | EN | +V1P8S_EN | ✅ | EN pin is correctly connected to +V1P8S_EN net through 0 ohm resistor R22 from 1P8V_EN signal. | | 3 | VIN | +PS_3VSB | ✅ | VIN pin is correctly connected to +PS_3VSB input supply with adequate input capacitance. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin is correctly connected to +PS_3VSB input supply, same as VIN. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as specified. | | 6 | VOUT | +V1P8S | ✅ | VOUT pin is correctly connected to +V1P8S output rail with adequate output capacitance. | | 7 | ADJ | +V1P8S_FB | ✅ | ADJ pin is correctly connected to feedback divider network (R24=12.1K to output, R25=9.53K to ground) setting output to approximately 1.816V. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins are both correctly connected to ground plane. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins are both correctly connected to ground plane. | </details> <details> <summary><b>R24</b> - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Upper feedback resistor (R1) correctly connects output +V1P8S to feedback pin +V1P8S_FB with 12.1K ohm value. | | 2 | 2 | +V1P8S_FB | ✅ | Upper feedback resistor (R1) correctly connects output +V1P8S to feedback pin +V1P8S_FB with 12.1K ohm value. | </details> <details> <summary><b>R23</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor correctly connects power good signal +V1P8S_PGD to output rail +V1P8S with 4.7K ohm value. | | 2 | 2 | +V1P8S_PGD | ✅ | Pull-up resistor correctly connects power good signal +V1P8S_PGD to output rail +V1P8S with 4.7K ohm value. | </details> <details> <summary><b>R25</b> - 110-0004490 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004490) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor (R2) correctly connects feedback pin +V1P8S_FB to ground with 9.53K ohm value. | | 2 | 2 | +V1P8S_FB | ✅ | Lower feedback resistor (R2) correctly connects feedback pin +V1P8S_FB to ground with 9.53K ohm value. | </details> <details> <summary><b>R22</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V_EN | ✅ | Zero ohm resistor correctly passes enable signal from 1P8V_EN to +V1P8S_EN for U21 enable control. | | 2 | 2 | +V1P8S_EN | ✅ | Zero ohm resistor correctly passes enable signal from 1P8V_EN to +V1P8S_EN for U21 enable control. | </details> <details> <summary><b>R134</b> - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | 1kΩ resistor connecting V1P0S_PG to 1P35V_EN (gate of Q5). Provides current limiting for gate drive and creates ~100μs time constant with C105 for controlled turn-on of the +V1P35S rail. | | 2 | 2 | 1P35V_EN | ✅ | 1kΩ resistor connecting V1P0S_PG to 1P35V_EN (gate of Q5). Provides current limiting for gate drive and creates ~100μs time constant with C105 for controlled turn-on of the +V1P35S rail. | </details> <details> <summary><b>R120</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | 10kΩ resistor connecting +V1P35S to 1P35V_PWG (base of Q3 transistor 1). Provides base drive for power sequencing logic that controls the 1.8V regulator enable. | | 2 | 2 | 1P35V_PWG | ✅ | 10kΩ resistor connecting +V1P35S to 1P35V_PWG (base of Q3 transistor 1). Provides base drive for power sequencing logic that controls the 1.8V regulator enable. | </details> <details> <summary><b>R126</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | 4.7kΩ pull-up resistor connecting +5VSB to 1P5V_EN_B. Pulls up the collector of Q3 transistor 1 and provides base drive for Q3 transistor 2 in the cascaded power sequencing circuit. | | 2 | 2 | 1P5V_EN_B | ✅ | 4.7kΩ pull-up resistor connecting +5VSB to 1P5V_EN_B. Pulls up the collector of Q3 transistor 1 and provides base drive for Q3 transistor 2 in the cascaded power sequencing circuit. | </details> <details> <summary><b>R125</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | 4.7kΩ pull-up resistor connecting +VCC to 1P8V_EN. Pulls up the collector of Q3 transistor 2 to enable the 1.8V regulator (U21) as part of the power sequencing logic. | | 2 | 2 | 1P8V_EN | ✅ | 4.7kΩ pull-up resistor connecting +VCC to 1P8V_EN. Pulls up the collector of Q3 transistor 2 to enable the 1.8V regulator (U21) as part of the power sequencing logic. | </details> <details> <summary><b>Q3</b> - XSTR_NPN_DUAL_40V_SOT-363 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter 1 is correctly connected to GND for NPN transistor operation. | | 2 | B1 | 1P35V_PWG | ✅ | Base 1 is correctly driven from +V1P35S through R120 (10kΩ) to sense when the 1.35V rail is present. | | 3 | C2 | 1P8V_EN | ✅ | Collector 2 is correctly connected to 1P8V_EN, which is pulled up through R125 (4.7kΩ) to +VCC. | | 4 | E2 | GND | ✅ | Emitter 2 is correctly connected to GND for NPN transistor operation. | | 5 | B2 | 1P5V_EN_B | ✅ | Base 2 is correctly connected to 1P5V_EN_B, which is the same net as Collector 1 (pin 6), creating a cascaded transistor configuration. | | 6 | C1 | 1P5V_EN_B | ✅ | Collector 1 is correctly connected to 1P5V_EN_B, which is pulled up through R126 (4.7kΩ) to +5VSB and also drives Base 2 (pin 5). | </details> <details> <summary><b>Q5</b> - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/132-0004421) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +VDIMM | ✅ | Drain is correctly connected to +VDIMM input power rail for high-side switch configuration. | | G | GATE | 1P35V_EN | ✅ | Gate is driven from V1P0S_PG through R134 (1kΩ). Gate drive voltage may be marginal if +VCC is 3.3V, resulting in VGS ≈ 1.95V, which is below the 2V design guideline noted on the schematic but within the VGS(th) range of 1.0-2.5V. | | S | SOURCE | +V1P35S | ✅ | Source is correctly connected to +V1P35S output rail for high-side switch configuration. | </details> <details> <summary><b>U38</b> - LDO_ULD_5A_SO8 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004525) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | FB | FB_V1P0S | ✅ | Feedback pin connected to resistor divider network (R135 and R136). The divider is correctly configured but sets output to 1.025V. Based on schematic notes indicating combined load requirements of 1.3A at 1.05V and 3.6A at 1.0V, and the note 'Combine +V1P0S and +V1P05S', the output voltage may be insufficient for loads requiring 1.05V. The root cause is the incorrect value of R136. | | 3 | VOUT-2 | +V1P0S | ✅ | Output pins correctly connected to +V1P0S rail with appropriate decoupling capacitors. | | 4 | VOUT-1 | +V1P0S | ✅ | Output pins correctly connected to +V1P0S rail with appropriate decoupling capacitors. | | 5 | VIN-2 | +VDIMM | ✅ | Input voltage pins correctly connected to +VDIMM supply rail. | | 9 | VIN-1 | +VDIMM | ✅ | Input voltage pins correctly connected to +VDIMM supply rail. | | 6 | VCNTL | VCNTL_V1P0S | ✅ | Voltage control pin connected to RC network with 10 ohm resistor to +VCC and 1uF capacitor to ground. | | 7 | POK | V1P0S_PG | ✅ | Power good output pin correctly connected with 10K pull-up resistor and used for downstream power sequencing. | | 8 | EN | 1P0V_EN | ✅ | Enable pin correctly connected to power sequencing signal through 0-ohm jumper resistor. | </details> <details> <summary><b>R136</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002029) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FB_V1P0S | ✅ | Upper feedback resistor (R1) in voltage divider. Current value of 40.2K results in 1.025V output. Based on schematic notes indicating combined load requirements (1.3A at 1.05V and 3.6A at 1.0V) and the note 'Combine +V1P0S and +V1P05S', the resistor value should be approximately 44.2K to achieve 1.05V output and properly supply all loads. | | 2 | 2 | +V1P0S | ✅ | Upper feedback resistor (R1) in voltage divider. Current value of 40.2K results in 1.025V output. Based on schematic notes indicating combined load requirements (1.3A at 1.05V and 3.6A at 1.0V) and the note 'Combine +V1P0S and +V1P05S', the resistor value should be approximately 44.2K to achieve 1.05V output and properly supply all loads. | </details> <details> <summary><b>R135</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004498) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor (R2) in voltage divider, correctly connected between FB pin and ground to set output voltage. | | 2 | 2 | FB_V1P0S | ✅ | Lower feedback resistor (R2) in voltage divider, correctly connected between FB pin and ground to set output voltage. | </details> <details> <summary><b>R306</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | Zero-ohm jumper resistor implementing power sequencing by connecting graphics core power good to regulator enable. | | 2 | 2 | 1P0V_EN | ✅ | Zero-ohm jumper resistor implementing power sequencing by connecting graphics core power good to regulator enable. | </details> <details> <summary><b>R319</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | Pull-up resistor for power good signal, correctly connected between V1P0S_PG and +VCC. | | 2 | 2 | +VCC | ✅ | Pull-up resistor for power good signal, correctly connected between V1P0S_PG and +VCC. | </details> <details> <summary><b>R320</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCNTL_V1P0S | ✅ | Control resistor forming RC network with C117 for VCNTL pin, connected between +VCC and VCNTL_V1P0S. | | 2 | 2 | +VCC | ✅ | Control resistor forming RC network with C117 for VCNTL pin, connected between +VCC and VCNTL_V1P0S. | </details> <details> <summary><b>U20</b> - NCP606 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncp605-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004677) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN1 | +PS_3VSB | ✅ | VIN1 and VIN2 are both correctly connected to +PS_3VSB input supply. Both pins must be connected together externally per datasheet requirements for full output current range operation. | | 6 | VIN2 | +PS_3VSB | ✅ | VIN1 and VIN2 are both correctly connected to +PS_3VSB input supply. Both pins must be connected together externally per datasheet requirements for full output current range operation. | | 2 | GND | GND | ✅ | GND and GND_PAD are both correctly connected to the GND net. The exposed pad connection to ground provides thermal relief as required. | | 7 | GND_PAD | GND | ✅ | GND and GND_PAD are both correctly connected to the GND net. The exposed pad connection to ground provides thermal relief as required. | | 3 | EN | +V1P8A_EN | ✅ | EN pin is correctly connected to +V1P8A_EN which implements power sequencing. The enable signal is derived from U24's power good output through R151, ensuring U24 (1.0V regulator) is stable before U20 (1.8V regulator) enables. | | 4 | VOUT | +V1P8A | ✅ | VOUT pin is correctly connected to +V1P8A output net with adequate decoupling. Output capacitor C151 (10uF) exceeds the 1.0 µF minimum requirement. | | 5 | SENSE/ADJ | +V1P8A_FB | ✅ | SENSE/ADJ pin is correctly connected to feedback divider network formed by R150 (12.1K) and R153 (27.4K). The calculated output voltage is approximately 1.802V, matching the intended 1.8V output. | </details> <details> <summary><b>R151</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | R151 (0 ohm jumper) correctly implements power sequencing by connecting the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN). | | 2 | 2 | +V1P8A_EN | ✅ | R151 (0 ohm jumper) correctly implements power sequencing by connecting the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN). | </details> <details> <summary><b>R153</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002726) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R153 (27.4K ohm) is correctly configured as R2 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and ground. | | 2 | 2 | GND | ✅ | R153 (27.4K ohm) is correctly configured as R2 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and ground. | </details> <details> <summary><b>R150</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R150 (12.1K ohm) is correctly configured as R1 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and output (+V1P8A). | | 2 | 2 | +V1P8A | ✅ | R150 (12.1K ohm) is correctly configured as R1 in the voltage divider network, connecting between the feedback node (+V1P8A_FB) and output (+V1P8A). | </details> <details> <summary><b>R34</b> - 6.04K ohm 1% 1/16W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0003781) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Upper resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and VOUT (pin 2) to set output voltage to 1.0V. | | 2 | 2 | +V1P0A | ✅ | Upper resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and VOUT (pin 2) to set output voltage to 1.0V. | </details> <details> <summary><b>R35</b> - 23.7K ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004494) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Lower resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and GND (pin 2) to set output voltage to 1.0V. | | 2 | 2 | GND | ✅ | Lower resistor of feedback divider network, correctly connected between ADJ pin (pin 1) and GND (pin 2) to set output voltage to 1.0V. | </details> <details> <summary><b>R32</b> - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Enable pull-up resistor, correctly connected between +5VSB (pin 1) and EN pin of U24 (pin 2) to enable the regulator when +5VSB is present. | | 2 | 2 | +V1P0A_ENABLE | ✅ | Enable pull-up resistor, correctly connected between +5VSB (pin 1) and EN pin of U24 (pin 2) to enable the regulator when +5VSB is present. | </details> <details> <summary><b>R33</b> - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | Power good pull-up resistor, correctly connected between +PS_3VSB (pin 1) and PGOOD pin of U24 (pin 2) to provide proper logic levels for open-drain output. | | 2 | 2 | +V1P0A_PWRGD | ✅ | Power good pull-up resistor, correctly connected between +PS_3VSB (pin 1) and PGOOD pin of U24 (pin 2) to provide proper logic levels for open-drain output. | </details> <details> <summary><b>U24</b> - LDO_ULD_3A_SO8 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P0A_PWRGD | ✅ | PGOOD pin correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB. Used for power sequencing to enable downstream regulator U20. | | 2 | EN | +V1P0A_ENABLE | ✅ | EN pin correctly connected to +V1P0A_ENABLE with pull-up resistor R32 to +5VSB and bypass capacitor C20 to ground. Enable threshold requirement >1.1V is met. | | 3 | VIN | +PS_3VSB | ✅ | VIN pin correctly connected to +PS_3VSB (3.3V standby rail) with appropriate input bypass capacitors nearby. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin correctly connected to +PS_3VSB, same as VIN. This is typical for LDOs with separate VIN and VDD pins. | | 5 | NC | | ✅ | NC pin has no connection, which is correct for a no-connect pin. | | 6 | VOUT | +V1P0A | ✅ | VOUT pin correctly connected to +V1P0A output rail with appropriate output capacitors C21 (22uF) and C22 (0.1uF) for stability. | | 7 | ADJ | +V1P0A_FB | ✅ | ADJ pin correctly connected to feedback divider network formed by R34 (6.04K) and R35 (23.7K), which sets output voltage to 1.0V per formula Vout=0.8(1+R1/R2). | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins both correctly connected to GND. Dual ground pins are typical for power devices to handle high currents. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins both correctly connected to GND. Dual ground pins are typical for power devices to handle high currents. | </details> <details> <summary><b>R61</b> - 20K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001957) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Pull-up resistor from SYS_PWRGD to +VCC3, providing pull-up for the output signal. | | 2 | 2 | SYS_PWRGD | ✅ | Pull-up resistor from SYS_PWRGD to +VCC3, providing pull-up for the output signal. | </details> <details> <summary><b>Q1</b> - XSTR_NPN_DUAL_40V_SOT-363 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter of transistor 1 (E1) correctly connected to ground. | | 2 | B1 | PSGOOD | ✅ | Base of transistor 1 (B1) connected to PSGOOD signal, which is driven by a wired-AND gate through D11 and pulled up through R206. | | 3 | C2 | SYS_PWRGD | ✅ | Collector of transistor 2 (C2) connected to SYS_PWRGD output, pulled up through R61 to +VCC3. | | 4 | E2 | GND | ✅ | Emitter of transistor 2 (E2) correctly connected to ground. | | 5 | B2 | PSPUP | ✅ | Base of transistor 2 (B2) connected to PSPUP, which is driven by the collector of transistor 1 and pulled up through R60. | | 6 | C1 | PSPUP | ✅ | Collector of transistor 1 (C1) connected to PSPUP, which drives the base of transistor 2 and is pulled up through R60. | </details> <details> <summary><b>R60</b> - 20K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001957) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | Pull-up resistor from PSPUP to +PS_3VSB, providing pull-up for the intermediate signal between the two transistors in Q1. | | 2 | 2 | PSPUP | ✅ | Pull-up resistor from PSPUP to +PS_3VSB, providing pull-up for the intermediate signal between the two transistors in Q1. | </details> <details> <summary><b>D11</b> - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | Anode 1 connected to +V1P0A_PWRGD power good signal. | | 2 | 2 | SLP_S3_L | ✅ | Anode 2 connected to SLP_S3_L sleep signal. | | 3 | 3 | PSGOOD | ✅ | Common cathode connected to PSGOOD, forming a wired-AND gate with the two input signals. | </details> <details> <summary><b>R206</b> - 200K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001951) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PSGOOD | ✅ | Pull-up resistor from PSGOOD to +V1P8S, providing both pull-up function and RC delay with C44. | | 2 | 2 | +V1P8S | ✅ | Pull-up resistor from PSGOOD to +V1P8S, providing both pull-up function and RC delay with C44. | </details> <details> <summary><b>FB7</b> - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Input pin connected to +VCC3 power rail. This pin receives 3.3V power that will be passed through to the CPU supply rail. | | 2 | 2 | +VCC3S | ✅ | Output pin connected to +VCC3S power rail that supplies the CPU. The rail is decoupled by C247 and carries approximately 43mA according to schematic notes. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **R151, R18, R192, R20, R216, R22, R243, R261, R306, R353, R354, R41, R42, R43, R46, R48, R51, R72, R73, R74, R809** (110-0001853): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001853) - **R147, R50** (110-0001859): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001859) - **R102, R116, R120, R13, R14, R183, R189, R190, R191, R2, R209, R210, R211, R219, R220, R221, R260, R268, R28, R29, R30, R319, R400, R706, R71, R75, R84, R97** (110-0001875): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001875) - **R134, R15, R16, R17, R186, R187, R208, R233, R234, R259, R401, R94** (110-0001923): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001923) - **R206** (110-0001951): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001951) - **R60, R61** (110-0001957): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001957) - **R179** (110-0001960): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001960) - **R11, R12, R269, R270** (110-0001967): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001967) - **R117, R171, R172, R177, R257, R44, R45, R47, R49, R52** (110-0001984): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001984) - **R819** (110-0002000): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002000) - **R136** (110-0002029): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002029) - **R125, R126, R149, R23, R32, R33** (110-0002058): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058) - **R21** (110-0002078): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002078) - **FB7, R152, R222, R265, R275, R818** (110-0002124): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002124) - **R150, R24** (110-0002560): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002560) - **R213, R38, R39** (110-0002631): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002631) - **R153** (110-0002726): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002726) - **R240, R241, R242, R258** (110-0003059): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0003059) - **R34** (110-0003781): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0003781) - **R813** (110-0004466): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004466) - **R298** (110-0004467): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004467) - **R185, R77** (110-0004472): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004472) - **R255** (110-0004474): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004474) - **R217, R218, R239** (110-0004476): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004476) - **R212** (110-0004478): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004478) - **R25** (110-0004490): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004490) - **R35** (110-0004494): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004494) - **R135** (110-0004498): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004498) - **R40** (110-0004695): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0004695) - **R832, R833, R834, R835** (1120-0003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0003) - **R837, R838, R839, R89** (1120-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0010) - **R815, R820, R821, R822, R823, R824, R825, R826, R827, R828, R829, R830, R831, R851** (1120-0011): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0011) - **R836** (1120-0018): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0018) - **R108, R320, R65** (1120-0022): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0022) - **R91, R92** (1120-0025): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0025) - **R847, R88** (1120-0032): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0032) - **R106** (1120-0037): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0037) - **R167** (1120-0052): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0052) - **R131** (1120-0055): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0055) - **R81** (1120-0099): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0099) - **R105** (1120-0115): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0115) - **R801, R802, R803, R804, R805, R806, R807, R808** (1120-0119): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0119) - **R816** (1120-0149): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0149) - **R814** (1120-0187): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0187) - **R843, R844** (1120-0203): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0203) - **R817** (1120-0267): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0267) - **R96** (1120-0282): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0282) - **R70** (1120-0289): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0289) - **R80** (1120-0329): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0329) - **R85, R86, R87** (1120-0330): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0330) - **R146** (1120-0338): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0338) - **R93, R95** (1120-0351): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0351) - **R848** (1120-0359): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0359) - **R62, R63, R64, R78, R79, R840, R841, R842, R849** (1121-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0001) - **R90** (1121-0025): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1121-0025) - **R107** (1130-0002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1130-0002) - **R845** (1130-0193): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1130-0193) - **R154, R166** (1130-0234): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1130-0234) - **R168** (1141-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1141-0026) - **C155, C17, C191, C192, C205, C206, C207, C208, C309, C65** (123-0001056): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001056) - **C252, C253** (123-0001107): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001107) - **C157** (123-0001144): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0001144) - **C233** (123-0004408): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0004408) - **C16** (123-0004415): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0004415) - **C76, C77** (123-0005035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/123-0005035) - **L11** (125-0004454): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/125-0004454) - **L3** (125-0004501): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/125-0004501) - **FB3** (126-0001423): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0001423) - **FB1, FB11, FB4, FB5, L12, L13, L5, L6** (126-0004457): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/126-0004457) - **D11** (130-0004403): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/130-0004403) - **U38** (140-0004525): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004525) - **U21, U24** (140-0004526): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004526) - **Y1** (145-0004789): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/145-0004789) - **X1, Y2** (145-0004792): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/145-0004792) - **P2** (158-0001269): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/158-0001269) - **P1** (158-0004513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/158-0004513) - **J10** (158-0004534): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/158-0004534) - **C35** (2220-0002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0002) - **C36** (2220-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0014) - **C39, C47** (2220-0025): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0025) - **C45** (2220-0035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0035) - **C429, C430, C431** (2220-0039): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0039) - **C382** (2220-0047): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2220-0047) - **C34** (2221-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0001) - **C37, C40** (2221-0002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0002) - **C38** (2221-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0004) - **C425** (2221-0017): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2221-0017) - **C50** (2222-0008): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0008) - **C24, C428** (2222-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0014) - **C25, C408, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C426, C427, C433, C46** (2222-0016): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2222-0016) - **C419, C420, C421, C422, C423, C424** (2232-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2232-0012) - **C48** (2232-0016): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2232-0016) - **C52** (2240-0005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2240-0005) - **C66, C67, C68, C78, C79, C80, C81** (2242-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2242-0014) - **C161** (2267-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/2267-0004) - **J5, J6, J7** (258-0002513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0002513) - **USB1** (258-0004503): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004503) - **J2** (258-0004524): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004524) - **J1** (258-0004612): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004612) - **J4** (258-0004869): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0004869) - **JP1** (258-0005019): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/258-0005019) - **FB12** (3044-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3044-0010) - **L8** (3120-0183): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3120-0183) - **L18, L4** (3120-0266): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3120-0266) - **CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17** (3142-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3142-0014) - **J11** (3362-0042): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3362-0042) - **J8** (3430-0212): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3430-0212) - **BH1** (353-0003073): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/353-0003073) - **FL1** (3750-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3750-0010) - **SW1** (3770-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3770-0026) - **TH1, TH2, TH3, TH4** (3880-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/3880-0004) - **U42** (4300-0071): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4300-0071) - **U5, U6** (4327-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4327-0009) - **D1, D2** (4560-0045): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4560-0045) - **D13** (4620-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/4620-0026) - **TP11, TP12, TP13, TP16** (999-0000002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/999-0000002) - **TP17, TP18** (999-0000003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/999-0000003) - **SP1, SP2** (999-0000005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/999-0000005) - **D3, D4, D6** (BAT54A-S): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT54A-S) - **D10, D5, D8** (BAT754C): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAT754C) - **Q2, Q9** (BAV99-7-F-S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/BAV99-7-F-S-X) - **U33** (M24C02-WMN6TP-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/M24C02-WMN6TP-X) - **U25, U26** (NCP81109GMNTXG): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NCP81109GMNTXG) - **U35** (NCT3012S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NCT3012S-X) - **U18** (NTB0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTB0104GU12) - **U4, U7** (NTS0102GT): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0102GT) - **U10, U14, U15, U16, U17, U19** (NTS0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NTS0104GU12) - **U29** (TPD4USB30): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/TPD4USB30) </details> <sub><sup>Note: DRCY uses AI. Please verify the outputs.</sup></sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component CPU1, pins AK12, AK13: DDI0 RCOMP pins are swapped. AK13 (negative RCOMP) is connected to DDI_RCOMP_P, and AK12 (positive RCOMP) is connected to DDI_RCOMP_N.

  • Pin AK13 has the name D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating negative/complement signal (from schematic)
  • Pin AK12 has the name DDI0_RCOMP_P with _P suffix indicating positive signal (from schematic)
  • Pin AK13 is connected to net DDI_RCOMP_P (positive net name) (from schematic)
  • Pin AK12 is connected to net DDI_RCOMP_N (negative net name) (from schematic)
  • The overline notation in pin names is a standard convention to indicate active-low or complement signals (reasoning)
  • A 402 ohm resistor (R217) is connected between DDI_RCOMP_N and DDI_RCOMP_P (from schematic)
  • The RCOMP pins require an external resistor for display port compensation per Intel Atom E3800 design guidelines (from datasheet 140-0004628)
  • The polarity of the RCOMP connections is reversed - the negative pin is connected to the positive net and vice versa (reasoning)
  • The connections should be corrected: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)

Replace a datasheet: 📤 CPU1

[🚨 Error] **Component `CPU1`, pins `AK12, AK13`: DDI0 RCOMP pins are swapped. AK13 (negative RCOMP) is connected to DDI_RCOMP_P, and AK12 (positive RCOMP) is connected to DDI_RCOMP_N.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,39.05" aspect-ratio="1.29" } - Pin AK13 has the name D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating negative/complement signal *(from schematic)* - Pin AK12 has the name DDI0_RCOMP_P with _P suffix indicating positive signal *(from schematic)* - Pin AK13 is connected to net DDI_RCOMP_P (positive net name) *(from schematic)* - Pin AK12 is connected to net DDI_RCOMP_N (negative net name) *(from schematic)* - The overline notation in pin names is a standard convention to indicate active-low or complement signals *(reasoning)* - A 402 ohm resistor (R217) is connected between DDI_RCOMP_N and DDI_RCOMP_P *(from schematic)* - The RCOMP pins require an external resistor for display port compensation per Intel Atom E3800 design guidelines *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - The polarity of the RCOMP connections is reversed - the negative pin is connected to the positive net and vice versa *(reasoning)* - The connections should be corrected: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P *(reasoning)* <sub>Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628)</sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component R50, pins 1, 2: R50 is a 100K pull-down resistor on the UART RX line. This is incorrect - UART signals should idle high (mark state), so this should be a pull-up resistor to +3VSB or BUF3_PWR instead of a pull-down to GND.

  • Pin 1 is connected to net GND (from schematic)
  • Pin 2 is connected to net DBG_UART3_RXD (from schematic)
  • R50 is a 100K-ohm resistor (part number 110-0001859) configured as a pull-down (from schematic)
  • DBG_UART3_RXD connects to U6 pin 8 (B1) and J4 pin 4 (from schematic)
  • In UART protocol, the idle state is logic high (mark state), and the start bit is logic low (reasoning)
  • When no cable is connected to the debug port, the RX line should be pulled high to indicate the proper idle state (reasoning)
  • A pull-down resistor causes the line to be low when nothing is connected, which violates the UART idle state requirement (reasoning)
  • A low RX line when disconnected could be interpreted by the UART receiver as a continuous start bit or break condition, potentially causing spurious interrupts or errors (reasoning)
  • When a cable is connected and transmitting logic high, the pull-down resistor fights against the external device's driver, though the 100K value is weak enough that this may not cause immediate functional problems (reasoning)
  • R50 should be changed to a pull-up resistor to +3VSB or BUF3_PWR (3.3V) instead of a pull-down to GND to maintain the correct UART idle state (reasoning)
  • The 100K ohm value is appropriate for a UART pull resistor, but the polarity is incorrect (reasoning)

Upload a datasheet: 📤 R50

[🚨 Error] **Component `R50`, pins `1, 2`: R50 is a 100K pull-down resistor on the UART RX line. This is incorrect - UART signals should idle high (mark state), so this should be a pull-up resistor to +3VSB or BUF3_PWR instead of a pull-down to GND.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="27eb0188bc47cc9ba6f9" diff-visibility="full" variant="default" view-coords="78.29,41.25,85.79,50.52" aspect-ratio="1.29" } - Pin 1 is connected to net GND *(from schematic)* - Pin 2 is connected to net DBG_UART3_RXD *(from schematic)* - R50 is a 100K-ohm resistor (part number 110-0001859) configured as a pull-down *(from schematic)* - DBG_UART3_RXD connects to U6 pin 8 (B1) and J4 pin 4 *(from schematic)* - In UART protocol, the idle state is logic high (mark state), and the start bit is logic low *(reasoning)* - When no cable is connected to the debug port, the RX line should be pulled high to indicate the proper idle state *(reasoning)* - A pull-down resistor causes the line to be low when nothing is connected, which violates the UART idle state requirement *(reasoning)* - A low RX line when disconnected could be interpreted by the UART receiver as a continuous start bit or break condition, potentially causing spurious interrupts or errors *(reasoning)* - When a cable is connected and transmitting logic high, the pull-down resistor fights against the external device&#x27;s driver, though the 100K value is weak enough that this may not cause immediate functional problems *(reasoning)* - R50 should be changed to a pull-up resistor to +3VSB or BUF3_PWR (3.3V) instead of a pull-down to GND to maintain the correct UART idle state *(reasoning)* - The 100K ohm value is appropriate for a UART pull resistor, but the polarity is incorrect *(reasoning)* <sub>Upload a datasheet: [📤 R50](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0001859)</sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component CPU1, pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33: CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.

  • Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic (from schematic)
  • The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
  • The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V (reasoning)
  • The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails (from datasheet 140-0004628, page 119)
  • The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) (from schematic)
  • Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail (reasoning)
  • Text annotations on the schematic near this net include 'VCC_CORE_V1P05' and '+V1P05S', suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead (from schematic)
  • Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) (reasoning)
  • The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions (reasoning)
  • Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error (from schematic)

Replace a datasheet: 📤 CPU1

[🚨 Error] **Component `CPU1`, pins `AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33`: CORE_V1P05_S3 pins are incorrectly connected to +V1P0S net (1.0V supply) instead of a dedicated 1.05V supply. These core voltage pins require 1.05V ±2% DC (1.029V to 1.071V range), but are receiving 1.0V, resulting in a 50mV undervoltage that exceeds the specified tolerance.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,28.61,61.48,49.63" aspect-ratio="1.29" } - Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all named CORE_V1P05_S3 in the datasheet and are connected to the +V1P0S net in the schematic *(from schematic)* - The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A, for the CORE_V1P05_S3 rail *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120>), page 120)* - The ±2% DC tolerance on 1.05V means the acceptable voltage range is 1.029V to 1.071V *(reasoning)* - The datasheet separately defines V1P0S as a 1.0V supply (typ 1.0V, ±2% DC, ±3% AC) for various functions including GPIO, PCIE, SATA, USB, DDI, DRAM, and UNCORE rails *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/eb22cbbe121fc6c44c06c9560f64e9392b916e9b/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119>), page 119)* - The +V1P0S net is also connected to numerous other CPU pins that explicitly require 1.0V according to their pin names: DDI_V1P0_S0IX (AJ18, AK19, AK21, AM16), GPIO_V1P0_S3 (AN25), PCIE_V1P0_S3 (AN18, AN21, AM21, AM18, AK18), SATA_V1P0_S3 (AN19), USB_V1P0_S3 (M14, U18, U19), VGA_V1P0_S3 (BJ6), SVID_V1P0_S3 (V32), and UNCORE_V1P0_S3 (AF16, AF18, G1, Y18) *(from schematic)* - Since the +V1P0S net serves many pins requiring 1.0V, it must be a 1.0V supply rail, not a 1.05V rail *(reasoning)* - Text annotations on the schematic near this net include &#x27;VCC_CORE_V1P05&#x27; and &#x27;+V1P05S&#x27;, suggesting the designer may have intended to create a separate 1.05V rail but mistakenly connected these pins to the 1.0V rail instead *(from schematic)* - Connecting the CORE_V1P05_S3 pins to a 1.0V supply results in a 50mV undervoltage (1.05V - 1.0V = 0.05V), which exceeds the ±21mV tolerance (±2% of 1.05V) *(reasoning)* - The CORE_V1P05_S3 pins should be connected to a separate dedicated 1.05V supply rail (V1P05S), not to the 1.0V supply rail (V1P0S) that serves other functions *(reasoning)* - Multiple decoupling capacitors (C182, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C254, C255, C261, C263, C274, C181, C183, C171) are connected between +V1P0S and GND, but this does not correct the fundamental voltage level error *(from schematic)* <sub>Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004628)</sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component U2, pins 15, 16: CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.

  • Pin 15 is connected to net HDMI_OUT_CLK_DN (from schematic)
  • Pin 16 is connected to net HDMI_OUT_CLK_DP (from schematic)
  • Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet (from schematic)
  • The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) (from schematic)
  • The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
All affected pins
Component U2, pins `15, 16`: CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.
  • Pin 15 is connected to net HDMI_OUT_CLK_DN (from schematic)
  • Pin 16 is connected to net HDMI_OUT_CLK_DP (from schematic)
  • Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet (from schematic)
  • The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) (from schematic)
  • The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
Component U2, pins `17, 18, 22, 23`: D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.
  • Pin 17 is connected to net HDMI_OUT_TX0_DN (from schematic)
  • Pin 18 is connected to net HDMI_OUT_TX0_DP (from schematic)
  • Pin 22 is connected to net HDMI_OUT_TX2_DN (from schematic)
  • Pin 23 is connected to net HDMI_OUT_TX2_DP (from schematic)
  • Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet (from schematic)
  • The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)
Component U2, pins `20, 21`: D1+ and D1- pins are swapped. Pin 20 should be D1+ but is connected to HDMI_OUT_TX1_DN, and pin 21 should be D1- but is connected to HDMI_OUT_TX1_DP.
  • Pin 20 is connected to net HDMI_OUT_TX1_DN (from schematic)
  • Pin 21 is connected to net HDMI_OUT_TX1_DP (from schematic)
  • Pin 20 should be D1+ (HDMI TMDS data channel 1 positive) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • Pin 21 should be D1- (HDMI TMDS data channel 1 negative) per the datasheet for PW package (from datasheet 140-0004333, page 4)
  • The schematic symbol has pin 20 labeled as D1- and pin 21 labeled as D1+, which is opposite to the datasheet (from schematic)
  • The D1 data channel signals are inverted due to the pin swap, which will prevent proper HDMI operation (reasoning)
  • The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout (reasoning)

Datasheets: 📄 U2

Replace a datasheet: 📤 U2

[🚨 Error] **Component `U2`, pins `15, 16`: CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,58.30,53.07,66.39" aspect-ratio="1.29" } - Pin 15 is connected to net HDMI_OUT_CLK_DN *(from schematic)* - Pin 16 is connected to net HDMI_OUT_CLK_DP *(from schematic)* - Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet *(from schematic)* - The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) *(from schematic)* - The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation *(reasoning)* - The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U2</code>, pins `15, 16`: CLK+ and CLK- pins are swapped. Pin 15 should be CLK+ but is connected to HDMI_OUT_CLK_DN, and pin 16 should be CLK- but is connected to HDMI_OUT_CLK_DP.</summary> - Pin 15 is connected to net HDMI_OUT_CLK_DN *(from schematic)* - Pin 16 is connected to net HDMI_OUT_CLK_DP *(from schematic)* - Pin 15 should be CLK+ (HDMI TMDS clock positive) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - Pin 16 should be CLK- (HDMI TMDS clock negative) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - The schematic symbol has pin 15 labeled as CLK- and pin 16 labeled as CLK+, which is opposite to the datasheet *(from schematic)* - The PKG_TYPE attribute is SSOP24_256P_222LS indicating the PW package (TSSOP) *(from schematic)* - The clock signals are inverted due to the pin swap, which will prevent proper HDMI operation *(reasoning)* - The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout *(reasoning)* </details> <details> <summary>Component <code>U2</code>, pins `17, 18, 22, 23`: D0 and D2 data channels are swapped. Pins 17/18 should be D2+/D2- but are connected to D0 signals, and pins 22/23 should be D0+/D0- but are connected to D2 signals.</summary> - Pin 17 is connected to net HDMI_OUT_TX0_DN *(from schematic)* - Pin 18 is connected to net HDMI_OUT_TX0_DP *(from schematic)* - Pin 22 is connected to net HDMI_OUT_TX2_DN *(from schematic)* - Pin 23 is connected to net HDMI_OUT_TX2_DP *(from schematic)* - Pin 17 should be D2+ (HDMI TMDS data channel 2 positive) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - Pin 18 should be D2- (HDMI TMDS data channel 2 negative) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - Pin 22 should be D0+ (HDMI TMDS data channel 0 positive) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - Pin 23 should be D0- (HDMI TMDS data channel 0 negative) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - The schematic symbol has pins 17/18 labeled as D0-/D0+ and pins 22/23 labeled as D2-/D2+, which is opposite to the datasheet *(from schematic)* - The D0 and D2 data channels are swapped, which will cause incorrect video data transmission and prevent proper HDMI operation *(reasoning)* - The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout *(reasoning)* </details> <details> <summary>Component <code>U2</code>, pins `20, 21`: D1+ and D1- pins are swapped. Pin 20 should be D1+ but is connected to HDMI_OUT_TX1_DN, and pin 21 should be D1- but is connected to HDMI_OUT_TX1_DP.</summary> - Pin 20 is connected to net HDMI_OUT_TX1_DN *(from schematic)* - Pin 21 is connected to net HDMI_OUT_TX1_DP *(from schematic)* - Pin 20 should be D1+ (HDMI TMDS data channel 1 positive) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - Pin 21 should be D1- (HDMI TMDS data channel 1 negative) per the datasheet for PW package *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - The schematic symbol has pin 20 labeled as D1- and pin 21 labeled as D1+, which is opposite to the datasheet *(from schematic)* - The D1 data channel signals are inverted due to the pin swap, which will prevent proper HDMI operation *(reasoning)* - The schematic symbol pin assignments must be corrected to match the PW package datasheet pinout *(reasoning)* </details> </details> Datasheets: [📄 U2](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) <sub>Replace a datasheet: [📤 U2](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/140-0004333)</sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component R21, pins 1, 2: R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.

  • Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail (from schematic)
  • Pin 2 of R21 is connected to the XDP_H_TDO net (from schematic)
  • XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface (from schematic)
  • R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package (from schematic)
  • The resistor is configured as a pull-up resistor from the signal line to the power rail (reasoning)
  • TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test (reasoning)
  • When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA (reasoning)
  • 35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device (reasoning)
  • Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption (reasoning)
  • Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value (reasoning)
  • No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value (from schematic)
  • The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application (reasoning)
  • While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values (reasoning)
  • The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value (reasoning)
All affected pins
Component J10, pin `57`: XDP test data out signal with unusual 51 ohm connection to +V1P8A power rail. This configuration is highly atypical for a JTAG TDO signal and likely incorrect.
  • Pin 57 is connected to net XDP_H_TDO (from schematic)
  • Resistor R21 (51 ohm, part 110-0002078) connects between +V1P8A and XDP_H_TDO (from schematic)
  • XDP_H_TDO is the test data output signal for the XDP/JTAG debug interface (reasoning)
  • TDO is typically an output signal from the device under test and is driven by the target device being debugged (reasoning)
  • A 51 ohm resistor to power rail acts as a pull-up, but this value is extremely low compared to typical pull-up resistors which range from 1K to 10K ohms (reasoning)
  • When TDO is driven low by the target device, this 51 ohm pull-up would draw approximately 35mA (1.8V / 51Ω), which is unusually high current for a logic signal and could exceed the drive capability of typical JTAG outputs (reasoning)
  • If series termination is intended for signal integrity, the resistor should be placed in series with the signal path (between the driver and load), not connected to the power rail (reasoning)
  • Other XDP/JTAG signals on the connector (TDI on pin 58, TMS on pin 56, TCK on pin 54, TRST on pin 52) do not show similar resistor connections to power, making this connection inconsistent with the rest of the debug interface design (from schematic)
  • Standard JTAG interface design does not typically require strong pull-ups on TDO outputs, as the signal is actively driven by the target device (reasoning)
  • This connection should be reviewed and verified against the system debug interface requirements, as it appears to be either a design error or an undocumented special requirement (reasoning)
Component R21, pins `1, 2`: R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.
  • Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail (from schematic)
  • Pin 2 of R21 is connected to the XDP_H_TDO net (from schematic)
  • XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface (from schematic)
  • R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package (from schematic)
  • The resistor is configured as a pull-up resistor from the signal line to the power rail (reasoning)
  • TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test (reasoning)
  • When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA (reasoning)
  • 35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device (reasoning)
  • Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption (reasoning)
  • Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value (reasoning)
  • No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value (from schematic)
  • The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application (reasoning)
  • While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values (reasoning)
  • The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value (reasoning)

Upload a datasheet: 📤 J10 📤 R21

[🚨 Error] **Component `R21`, pins `1, 2`: R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="3a073003e5413b0412d7" diff-visibility="full" variant="default" view-coords="33.07,50.37,41.94,57.87" aspect-ratio="1.29" } - Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail *(from schematic)* - Pin 2 of R21 is connected to the XDP_H_TDO net *(from schematic)* - XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface *(from schematic)* - R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package *(from schematic)* - The resistor is configured as a pull-up resistor from the signal line to the power rail *(reasoning)* - TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test *(reasoning)* - When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA *(reasoning)* - 35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device *(reasoning)* - Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption *(reasoning)* - Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value *(reasoning)* - No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value *(from schematic)* - The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application *(reasoning)* - While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values *(reasoning)* - The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>J10</code>, pin `57`: XDP test data out signal with unusual 51 ohm connection to +V1P8A power rail. This configuration is highly atypical for a JTAG TDO signal and likely incorrect.</summary> - Pin 57 is connected to net XDP_H_TDO *(from schematic)* - Resistor R21 (51 ohm, part 110-0002078) connects between +V1P8A and XDP_H_TDO *(from schematic)* - XDP_H_TDO is the test data output signal for the XDP/JTAG debug interface *(reasoning)* - TDO is typically an output signal from the device under test and is driven by the target device being debugged *(reasoning)* - A 51 ohm resistor to power rail acts as a pull-up, but this value is extremely low compared to typical pull-up resistors which range from 1K to 10K ohms *(reasoning)* - When TDO is driven low by the target device, this 51 ohm pull-up would draw approximately 35mA (1.8V / 51Ω), which is unusually high current for a logic signal and could exceed the drive capability of typical JTAG outputs *(reasoning)* - If series termination is intended for signal integrity, the resistor should be placed in series with the signal path (between the driver and load), not connected to the power rail *(reasoning)* - Other XDP/JTAG signals on the connector (TDI on pin 58, TMS on pin 56, TCK on pin 54, TRST on pin 52) do not show similar resistor connections to power, making this connection inconsistent with the rest of the debug interface design *(from schematic)* - Standard JTAG interface design does not typically require strong pull-ups on TDO outputs, as the signal is actively driven by the target device *(reasoning)* - This connection should be reviewed and verified against the system debug interface requirements, as it appears to be either a design error or an undocumented special requirement *(reasoning)* </details> <details> <summary>Component <code>R21</code>, pins `1, 2`: R21 is configured as a pull-up resistor connecting +V1P8A (1.8V analog supply) to XDP_H_TDO (JTAG Test Data Out signal going to expansion connector J10 pin 57). While the physical connections are correct, the 51Ω resistor value is inappropriately low for a pull-up on a JTAG/debug interface signal and would cause excessive current draw.</summary> - Pin 1 of R21 is connected to the +V1P8A net, which is a 1.8V analog power rail *(from schematic)* - Pin 2 of R21 is connected to the XDP_H_TDO net *(from schematic)* - XDP_H_TDO connects to pin 57 of connector J10, which is part of an Intel eXtensible Debug Port (XDP) interface *(from schematic)* - R21 has a value of 51Ω, 1% tolerance, 1/10W power rating in 0402 package *(from schematic)* - The resistor is configured as a pull-up resistor from the signal line to the power rail *(reasoning)* - TDO (Test Data Out) is an output signal in JTAG/debug interfaces, typically driven by the device under test *(reasoning)* - When XDP_H_TDO is driven low (0V), the current through R21 would be I = 1.8V / 51Ω ≈ 35mA *(reasoning)* - 35mA is an excessive current draw for a JTAG signal and could potentially damage or stress the output driver of the device *(reasoning)* - Power dissipation when driven low would be P = 1.8² / 51 ≈ 63.5mW, which is within the 100mW rating but represents wasteful power consumption *(reasoning)* - Standard pull-up resistor values for JTAG/debug signals are typically in the range of 1kΩ to 10kΩ, with 4.7kΩ being a common value *(reasoning)* - No schematic notes or documentation on the page provide justification for this unusually low pull-up resistor value *(from schematic)* - The specific part number 110-0002078 was intentionally selected, suggesting this may not be a simple typo, but the value is still inappropriate for this application *(reasoning)* - While Intel XDP interface specifications might have unique requirements, standard JTAG practice does not use such low pull-up values *(reasoning)* - The resistor value should be changed to a typical pull-up value in the 1kΩ to 10kΩ range (such as 1kΩ, 4.7kΩ, or 10kΩ) unless Intel XDP specifications explicitly require the 51Ω value *(reasoning)* </details> </details> <sub>Upload a datasheet: [📤 J10](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/158-0004534) [📤 R21](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002078)</sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component U40, pins 5, 6: SDA2 and SCL2 pins lack required pullup resistors to the high-voltage supply. While external pullups on a board connected to JP1 might be intended, the datasheet explicitly requires pullup resistors for proper I2C operation, and none are visible on this schematic page.

  • Pin 5 (SDA2) is connected to the GPIO_I2C_SDA net (from schematic)
  • Pin 6 (SCL2) is connected to the GPIO_I2C_SCL net (from schematic)
  • GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 pins 15 and 13 respectively, which is a 26-pin expansion header (HDR2X13) (from schematic)
  • No pullup resistors are visible on the GPIO_I2C_SDA or GPIO_I2C_SCL nets on this schematic page (from schematic)
  • Pin 5 is SDA2, the serial data on the high-voltage side (from datasheet PCA9306DCUT, page 4)
  • Pin 6 is SCL2, the serial clock on the high-voltage side (from datasheet PCA9306DCUT, page 4)
  • The datasheet states: 'Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)' (from datasheet PCA9306DCUT, page 10)
  • The datasheet states: 'pullup resistors required to pull SCL2 and SDA2 outputs to VDPU' (from datasheet PCA9306DCUT, page 10)
  • The high-voltage supply (VDPU) should be +3VSB based on the VREF2 connection through R812 (200K resistor) (from schematic)
  • I2C is an open-drain protocol that requires pullup resistors to function - without them, the bus cannot pull high (reasoning)
  • While the design might intend for pullups to be provided on an external board connected to JP1, this creates a hard dependency on external hardware and the I2C bus will not function without it (reasoning)
  • Best practice for I2C interfaces on expansion headers is to include pullups on the main board, possibly with the option to disable them if external pullups are present (reasoning)
  • Recommendation: Add pullup resistors (typically 2.2K to 10K ohms depending on bus capacitance and speed requirements per I2C specification) from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB, or clearly document that external pullups are required (reasoning)

Replace a datasheet: 📤 U40

[🚨 Error] **Component `U40`, pins `5, 6`: SDA2 and SCL2 pins lack required pullup resistors to the high-voltage supply. While external pullups on a board connected to JP1 might be intended, the datasheet explicitly requires pullup resistors for proper I2C operation, and none are visible on this schematic page.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.92" aspect-ratio="1.29" } - Pin 5 (SDA2) is connected to the GPIO_I2C_SDA net *(from schematic)* - Pin 6 (SCL2) is connected to the GPIO_I2C_SCL net *(from schematic)* - GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 pins 15 and 13 respectively, which is a 26-pin expansion header (HDR2X13) *(from schematic)* - No pullup resistors are visible on the GPIO_I2C_SDA or GPIO_I2C_SCL nets on this schematic page *(from schematic)* - Pin 5 is SDA2, the serial data on the high-voltage side *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4>), page 4)* - Pin 6 is SCL2, the serial clock on the high-voltage side *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4>), page 4)* - The datasheet states: &#x27;Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)&#x27; *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10>), page 10)* - The datasheet states: &#x27;pullup resistors required to pull SCL2 and SDA2 outputs to VDPU&#x27; *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10>), page 10)* - The high-voltage supply (VDPU) should be +3VSB based on the VREF2 connection through R812 (200K resistor) *(from schematic)* - I2C is an open-drain protocol that requires pullup resistors to function - without them, the bus cannot pull high *(reasoning)* - While the design might intend for pullups to be provided on an external board connected to JP1, this creates a hard dependency on external hardware and the I2C bus will not function without it *(reasoning)* - Best practice for I2C interfaces on expansion headers is to include pullups on the main board, possibly with the option to disable them if external pullups are present *(reasoning)* - Recommendation: Add pullup resistors (typically 2.2K to 10K ohms depending on bus capacitance and speed requirements per I2C specification) from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB, or clearly document that external pullups are required *(reasoning)* <sub>Replace a datasheet: [📤 U40](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/PCA9306DCUT)</sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[⚠️ Warning] Component R149, pins 1, 2: Pull-up resistor connecting FP_PWRBTN signal (pin 1) to +PS_5VSB power rail (pin 2). However, the resistor value is 4.7K ohm, which does not match the 10K value specified by the datasheet recommendation documented in the schematic notes.

  • Pin 1 is connected to the FP_PWRBTN net (from schematic)
  • Pin 2 is connected to the +PS_5VSB net (5V standby power) (from schematic)
  • R149 is specified as 4.7K ohm 1% 1/10W 0402 resistor (Part Number 110-0002058) (from schematic)
  • Schematic text notes near R149 state 'USE 10K PU' and 'DATASHEET SAYS', indicating a datasheet specifies a 10K pull-up resistor should be used (from schematic)
  • The actual resistor value of 4.7K does not match the 10K value indicated by the schematic notes (reasoning)
  • Using +PS_5VSB for the pull-up is correct, as it ensures the power button remains functional even when the main system power is off (reasoning)
  • A 4.7K pull-up will draw approximately 1.06mA when the button is pressed (5V / 4.7K), while a 10K pull-up would draw approximately 0.5mA (reasoning)
  • The lower resistance provides faster rise times and better noise immunity, but may violate input current specifications or power consumption requirements of the receiving component (reasoning)
  • Without documentation explaining the intentional deviation from the datasheet recommendation, this represents a specification violation (reasoning)
  • Recommendation: Change R149 to 10K ohm to match the datasheet requirement noted on the schematic, or add documentation explaining why 4.7K was intentionally chosen and validated (reasoning)

Upload a datasheet: 📤 R149

[⚠️ Warning] **Component `R149`, pins `1, 2`: Pull-up resistor connecting FP_PWRBTN signal (pin 1) to +PS_5VSB power rail (pin 2). However, the resistor value is 4.7K ohm, which does not match the 10K value specified by the datasheet recommendation documented in the schematic notes.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="26.71,13.91,34.21,22.58" aspect-ratio="1.29" } - Pin 1 is connected to the FP_PWRBTN net *(from schematic)* - Pin 2 is connected to the +PS_5VSB net (5V standby power) *(from schematic)* - R149 is specified as 4.7K ohm 1% 1/10W 0402 resistor (Part Number 110-0002058) *(from schematic)* - Schematic text notes near R149 state &#x27;USE 10K PU&#x27; and &#x27;DATASHEET SAYS&#x27;, indicating a datasheet specifies a 10K pull-up resistor should be used *(from schematic)* - The actual resistor value of 4.7K does not match the 10K value indicated by the schematic notes *(reasoning)* - Using +PS_5VSB for the pull-up is correct, as it ensures the power button remains functional even when the main system power is off *(reasoning)* - A 4.7K pull-up will draw approximately 1.06mA when the button is pressed (5V / 4.7K), while a 10K pull-up would draw approximately 0.5mA *(reasoning)* - The lower resistance provides faster rise times and better noise immunity, but may violate input current specifications or power consumption requirements of the receiving component *(reasoning)* - Without documentation explaining the intentional deviation from the datasheet recommendation, this represents a specification violation *(reasoning)* - Recommendation: Change R149 to 10K ohm to match the datasheet requirement noted on the schematic, or add documentation explaining why 4.7K was intentionally chosen and validated *(reasoning)* <sub>Upload a datasheet: [📤 R149](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/110-0002058)</sub>
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AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component U35, pin 4: Pin 4 (SLP_S5#) is connected to net SLP_S4_L. This represents a mismatch between the pin name (indicating S5 sleep state) and the connected signal (indicating S4 sleep state). While this could be intentional in systems that do not distinguish between S4 and S5 states, it should be verified against system requirements and the NCT3012S-X datasheet.

  • Pin 4 is labeled SLP_S5# on component U35 (from schematic)
  • Pin 4 is connected to net SLP_S4_L (from schematic)
  • Component U35 has a DeepS5_Sel pin (pin 1), indicating the chip has specific S5 state handling functionality (from schematic)
  • In ACPI specifications, S4 (Suspend to Disk/Hibernate) and S5 (Soft Off) are different power states with different system behaviors (reasoning)
  • The pin name SLP_S5# explicitly indicates this pin expects an S5 sleep state signal (reasoning)
  • The net name SLP_S4_L indicates this is an S4 sleep state signal (reasoning)
  • Both signals use active-low polarity (# and _L suffixes), so polarity is consistent (reasoning)
  • No SLP_S5# or SLP_S5_L net is visible in the schematic, suggesting either the S5 signal does not exist in this design or there is a naming/connection error (from schematic)
  • Some embedded systems may intentionally use S4 signals to control S5 behavior if they do not distinguish between these states (reasoning)
  • Without the NCT3012S-X datasheet, it cannot be definitively determined whether the chip accepts S4 signals on the SLP_S5# pin (reasoning)
  • Given the explicit pin naming and the presence of S5-specific functionality (DeepS5_Sel), this connection should be verified to ensure correct power state management (reasoning)
  • If this is an error, pin 4 should be connected to an SLP_S5# signal; if intentional, this design decision should be documented (reasoning)

Upload a datasheet: 📤 U35

[🚨 Error] **Component `U35`, pin `4`: Pin 4 (SLP_S5#) is connected to net SLP_S4_L. This represents a mismatch between the pin name (indicating S5 sleep state) and the connected signal (indicating S4 sleep state). While this could be intentional in systems that do not distinguish between S4 and S5 states, it should be verified against system requirements and the NCT3012S-X datasheet.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="18.08,38.61,25.58,46.11" aspect-ratio="1.29" } - Pin 4 is labeled SLP_S5# on component U35 *(from schematic)* - Pin 4 is connected to net SLP_S4_L *(from schematic)* - Component U35 has a DeepS5_Sel pin (pin 1), indicating the chip has specific S5 state handling functionality *(from schematic)* - In ACPI specifications, S4 (Suspend to Disk/Hibernate) and S5 (Soft Off) are different power states with different system behaviors *(reasoning)* - The pin name SLP_S5# explicitly indicates this pin expects an S5 sleep state signal *(reasoning)* - The net name SLP_S4_L indicates this is an S4 sleep state signal *(reasoning)* - Both signals use active-low polarity (# and _L suffixes), so polarity is consistent *(reasoning)* - No SLP_S5# or SLP_S5_L net is visible in the schematic, suggesting either the S5 signal does not exist in this design or there is a naming/connection error *(from schematic)* - Some embedded systems may intentionally use S4 signals to control S5 behavior if they do not distinguish between these states *(reasoning)* - Without the NCT3012S-X datasheet, it cannot be definitively determined whether the chip accepts S4 signals on the SLP_S5# pin *(reasoning)* - Given the explicit pin naming and the presence of S5-specific functionality (DeepS5_Sel), this connection should be verified to ensure correct power state management *(reasoning)* - If this is an error, pin 4 should be connected to an SLP_S5# signal; if intentional, this design decision should be documented *(reasoning)* <sub>Upload a datasheet: [📤 U35](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NCT3012S-X)</sub>
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AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component U26, pin 10: SW1 is connected only to the bootstrap capacitor return ($24N3595) and is isolated from the main switch node (VGFX-SW). This appears incorrect as phase 1 should be connected to the output if it is intended to be active.

  • Pin 10 (SW1) is connected to net $24N3595 (from schematic)
  • Net $24N3595 connects only to bootstrap capacitor C186 pin 2 and pin 10 (SW1) (from schematic)
  • Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW (from schematic)
  • Net VGFX-SW connects to inductor L4 pin 1, which connects to output +VGFX (from schematic)
  • There is no connection between net $24N3595 (SW1) and net VGFX-SW (from schematic)
  • Bootstrap circuit is present: pin 8 (BST) -> $24N3593 -> R228 -> $24N3596 -> C186 -> $24N3595 -> pin 10 (SW1) (from schematic)
  • Pin 7 (VIN1) is connected to +5VSB_SW, indicating phase 1 is powered (from schematic)
  • The presence of a populated bootstrap circuit (R228, C186) suggests phase 1 was intended to be active (reasoning)
  • In a multiphase buck converter, all active switch nodes should be connected to share load current through their respective inductors to the common output (reasoning)
  • Only one inductor (L4) is present, connecting VGFX-SW to +VGFX, suggesting all active phases should connect to VGFX-SW (reasoning)
  • If phase 1 were intentionally disabled, the bootstrap circuit components would typically be unpopulated (reasoning)
  • The isolation of SW1 from VGFX-SW while maintaining the bootstrap circuit and VIN1 connection is inconsistent and likely a design error (reasoning)
  • SW1 should be connected to VGFX-SW to enable phase 1 to contribute to the output (reasoning)
All affected pins
Component U26, pin `10`: SW1 is connected only to the bootstrap capacitor return ($24N3595) and is isolated from the main switch node (VGFX-SW). This appears incorrect as phase 1 should be connected to the output if it is intended to be active.
  • Pin 10 (SW1) is connected to net $24N3595 (from schematic)
  • Net $24N3595 connects only to bootstrap capacitor C186 pin 2 and pin 10 (SW1) (from schematic)
  • Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW (from schematic)
  • Net VGFX-SW connects to inductor L4 pin 1, which connects to output +VGFX (from schematic)
  • There is no connection between net $24N3595 (SW1) and net VGFX-SW (from schematic)
  • Bootstrap circuit is present: pin 8 (BST) -> $24N3593 -> R228 -> $24N3596 -> C186 -> $24N3595 -> pin 10 (SW1) (from schematic)
  • Pin 7 (VIN1) is connected to +5VSB_SW, indicating phase 1 is powered (from schematic)
  • The presence of a populated bootstrap circuit (R228, C186) suggests phase 1 was intended to be active (reasoning)
  • In a multiphase buck converter, all active switch nodes should be connected to share load current through their respective inductors to the common output (reasoning)
  • Only one inductor (L4) is present, connecting VGFX-SW to +VGFX, suggesting all active phases should connect to VGFX-SW (reasoning)
  • If phase 1 were intentionally disabled, the bootstrap circuit components would typically be unpopulated (reasoning)
  • The isolation of SW1 from VGFX-SW while maintaining the bootstrap circuit and VIN1 connection is inconsistent and likely a design error (reasoning)
  • SW1 should be connected to VGFX-SW to enable phase 1 to contribute to the output (reasoning)
Component C186, pin `2`: Connected to SW1 (U26 pin 10), but should be connected to VGFX-SW (the main switching node). The bootstrap capacitor must reference the actual switching node where the inductor connects for proper gate driver operation.
  • Pin 2 is connected to net $24N3595 (from schematic)
  • Net $24N3595 connects only to U26 pin 10 (SW1) (from schematic)
  • The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) (from schematic)
  • The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node where power conversion occurs (from schematic)
  • Net $24N3595 (SW1) is isolated from VGFX-SW and has no other connections besides U26 pin 10 and C186 pin 2 (from schematic)
  • In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET (reasoning)
  • The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects to extract power (reasoning)
  • The bootstrap capacitor charges when the low-side FET is on (switching node is low) and provides voltage to drive the high-side FET gate when it turns on (reasoning)
  • For the bootstrap circuit to function, the capacitor must be referenced to the actual switching node voltage, not to an isolated pin (reasoning)
  • Since the inductor L4 connects to VGFX-SW, this is the actual switching node, and the bootstrap capacitor should be connected between BST and VGFX-SW (reasoning)
  • The current configuration with C186 pin 2 connected to the isolated SW1 pin will not provide proper bootstrap voltage for the gate driver, as SW1 does not follow the switching node voltage (reasoning)
  • Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit (reasoning)

Upload a datasheet: 📤 U26

[🚨 Error] **Component `U26`, pin `10`: SW1 is connected only to the bootstrap capacitor return ($24N3595) and is isolated from the main switch node (VGFX-SW). This appears incorrect as phase 1 should be connected to the output if it is intended to be active.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="37.39,41.84,44.89,49.34" aspect-ratio="1.29" } - Pin 10 (SW1) is connected to net $24N3595 *(from schematic)* - Net $24N3595 connects only to bootstrap capacitor C186 pin 2 and pin 10 (SW1) *(from schematic)* - Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW *(from schematic)* - Net VGFX-SW connects to inductor L4 pin 1, which connects to output +VGFX *(from schematic)* - There is no connection between net $24N3595 (SW1) and net VGFX-SW *(from schematic)* - Bootstrap circuit is present: pin 8 (BST) -&gt; $24N3593 -&gt; R228 -&gt; $24N3596 -&gt; C186 -&gt; $24N3595 -&gt; pin 10 (SW1) *(from schematic)* - Pin 7 (VIN1) is connected to +5VSB_SW, indicating phase 1 is powered *(from schematic)* - The presence of a populated bootstrap circuit (R228, C186) suggests phase 1 was intended to be active *(reasoning)* - In a multiphase buck converter, all active switch nodes should be connected to share load current through their respective inductors to the common output *(reasoning)* - Only one inductor (L4) is present, connecting VGFX-SW to +VGFX, suggesting all active phases should connect to VGFX-SW *(reasoning)* - If phase 1 were intentionally disabled, the bootstrap circuit components would typically be unpopulated *(reasoning)* - The isolation of SW1 from VGFX-SW while maintaining the bootstrap circuit and VIN1 connection is inconsistent and likely a design error *(reasoning)* - SW1 should be connected to VGFX-SW to enable phase 1 to contribute to the output *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U26</code>, pin `10`: SW1 is connected only to the bootstrap capacitor return ($24N3595) and is isolated from the main switch node (VGFX-SW). This appears incorrect as phase 1 should be connected to the output if it is intended to be active.</summary> - Pin 10 (SW1) is connected to net $24N3595 *(from schematic)* - Net $24N3595 connects only to bootstrap capacitor C186 pin 2 and pin 10 (SW1) *(from schematic)* - Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW *(from schematic)* - Net VGFX-SW connects to inductor L4 pin 1, which connects to output +VGFX *(from schematic)* - There is no connection between net $24N3595 (SW1) and net VGFX-SW *(from schematic)* - Bootstrap circuit is present: pin 8 (BST) -&gt; $24N3593 -&gt; R228 -&gt; $24N3596 -&gt; C186 -&gt; $24N3595 -&gt; pin 10 (SW1) *(from schematic)* - Pin 7 (VIN1) is connected to +5VSB_SW, indicating phase 1 is powered *(from schematic)* - The presence of a populated bootstrap circuit (R228, C186) suggests phase 1 was intended to be active *(reasoning)* - In a multiphase buck converter, all active switch nodes should be connected to share load current through their respective inductors to the common output *(reasoning)* - Only one inductor (L4) is present, connecting VGFX-SW to +VGFX, suggesting all active phases should connect to VGFX-SW *(reasoning)* - If phase 1 were intentionally disabled, the bootstrap circuit components would typically be unpopulated *(reasoning)* - The isolation of SW1 from VGFX-SW while maintaining the bootstrap circuit and VIN1 connection is inconsistent and likely a design error *(reasoning)* - SW1 should be connected to VGFX-SW to enable phase 1 to contribute to the output *(reasoning)* </details> <details> <summary>Component <code>C186</code>, pin `2`: Connected to SW1 (U26 pin 10), but should be connected to VGFX-SW (the main switching node). The bootstrap capacitor must reference the actual switching node where the inductor connects for proper gate driver operation.</summary> - Pin 2 is connected to net $24N3595 *(from schematic)* - Net $24N3595 connects only to U26 pin 10 (SW1) *(from schematic)* - The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) *(from schematic)* - The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node where power conversion occurs *(from schematic)* - Net $24N3595 (SW1) is isolated from VGFX-SW and has no other connections besides U26 pin 10 and C186 pin 2 *(from schematic)* - In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET *(reasoning)* - The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects to extract power *(reasoning)* - The bootstrap capacitor charges when the low-side FET is on (switching node is low) and provides voltage to drive the high-side FET gate when it turns on *(reasoning)* - For the bootstrap circuit to function, the capacitor must be referenced to the actual switching node voltage, not to an isolated pin *(reasoning)* - Since the inductor L4 connects to VGFX-SW, this is the actual switching node, and the bootstrap capacitor should be connected between BST and VGFX-SW *(reasoning)* - The current configuration with C186 pin 2 connected to the isolated SW1 pin will not provide proper bootstrap voltage for the gate driver, as SW1 does not follow the switching node voltage *(reasoning)* - Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit *(reasoning)* </details> </details> <sub>Upload a datasheet: [📤 U26](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/NCP81109GMNTXG)</sub>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[⚠️ Warning] Component R195, pins 1, 2: Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).

  • Pin 1 is connected to +V1P0S (1.0V standby supply rail) (from schematic)
  • Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) (from schematic)
  • This resistor forms a pull-up for the SVID data line (reasoning)
  • SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines (reasoning)
  • Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ (reasoning)
  • The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) (reasoning)
  • The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up (reasoning)
  • The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity (reasoning)
All affected pins
Component R195, pins `1, 2`: Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).
  • Pin 1 is connected to +V1P0S (1.0V standby supply rail) (from schematic)
  • Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) (from schematic)
  • This resistor forms a pull-up for the SVID data line (reasoning)
  • SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines (reasoning)
  • Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ (reasoning)
  • The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) (reasoning)
  • The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up (reasoning)
  • The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity (reasoning)
Component R197, pins `1, 2`: Pull-up resistor for SVID clock line connecting +V1P0S to SVID_CLK-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).
  • Pin 1 is connected to +V1P0S (1.0V standby supply rail) (from schematic)
  • Pin 2 is connected to SVID_CLK-R, which connects through series resistor R194 to U26 pin 4 (SCLK) (from schematic)
  • This resistor forms a pull-up for the SVID clock line (reasoning)
  • SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines (reasoning)
  • Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ (reasoning)
  • The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) (reasoning)
  • The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up (reasoning)
  • The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity (reasoning)
[⚠️ Warning] **Component `R195`, pins `1, 2`: Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="17.39,32.43,24.89,41.70" aspect-ratio="1.29" } - Pin 1 is connected to +V1P0S (1.0V standby supply rail) *(from schematic)* - Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) *(from schematic)* - This resistor forms a pull-up for the SVID data line *(reasoning)* - SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines *(reasoning)* - Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ *(reasoning)* - The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) *(reasoning)* - The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up *(reasoning)* - The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>R195</code>, pins `1, 2`: Pull-up resistor for SVID data line connecting +V1P0S to SVID_DATA-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).</summary> - Pin 1 is connected to +V1P0S (1.0V standby supply rail) *(from schematic)* - Pin 2 is connected to SVID_DATA-R, which connects through series resistor R193 to U26 pin 2 (SDIO) *(from schematic)* - This resistor forms a pull-up for the SVID data line *(reasoning)* - SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines *(reasoning)* - Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ *(reasoning)* - The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) *(reasoning)* - The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up *(reasoning)* - The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity *(reasoning)* </details> <details> <summary>Component <code>R197</code>, pins `1, 2`: Pull-up resistor for SVID clock line connecting +V1P0S to SVID_CLK-R. The value (69.8Ω) is too low for typical SVID implementations and will cause excessive current draw (~14mA) and power dissipation (~14mW).</summary> - Pin 1 is connected to +V1P0S (1.0V standby supply rail) *(from schematic)* - Pin 2 is connected to SVID_CLK-R, which connects through series resistor R194 to U26 pin 4 (SCLK) *(from schematic)* - This resistor forms a pull-up for the SVID clock line *(reasoning)* - SVID (Serial VID) interfaces use open-drain outputs and require pull-up resistors on data and clock lines *(reasoning)* - Typical SVID pull-up resistor values are in the range of 1kΩ to 10kΩ, commonly 4.7kΩ *(reasoning)* - The 69.8Ω value will result in approximately 14.3mA current draw when the line is pulled low (1.0V / 69.8Ω) *(reasoning)* - The power dissipation will be approximately 14.3mW per resistor when active, which is excessive for a digital interface pull-up *(reasoning)* - The pull-up resistor value should be increased to the standard range of 1kΩ to 10kΩ to reduce current consumption and power dissipation while maintaining adequate signal integrity *(reasoning)* </details> </details>
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component R196, pins 1, 2: Pull-up resistor for SVID alert line, marked DNI (Do Not Install). Without this pull-up, the ALERT line will float when not actively driven, which may cause issues since R67 connects this signal to U26 pin 3 (ALERT).

  • Pin 1 would connect to +V1P0S (1.0V standby supply rail) if populated (from schematic)
  • Pin 2 would connect to SVID_ALERT-R if populated (from schematic)
  • This component is marked DNI (Do Not Install) and is electrically absent from the circuit (from schematic)
  • R67 (0Ω jumper) connects SVID_ALERT-R through to U26 pin 3 (ALERT), indicating the alert signal path is intended to be active (from schematic)
  • SVID alert lines typically require pull-up resistors similar to data and clock lines, as they use open-drain outputs (reasoning)
  • Without a pull-up resistor, the ALERT line will float when not actively driven, which can cause undefined logic levels and potential noise sensitivity (reasoning)
  • If the alert function is intended to be used (suggested by R67 being populated), R196 should be populated with a pull-up resistor in the 1kΩ to 10kΩ range (reasoning)
  • If the alert function is not used, the DNI status may be acceptable, though best practice would be to leave the pin unconnected or ensure it has a defined state (reasoning)
[🚨 Error] **Component `R196`, pins `1, 2`: Pull-up resistor for SVID alert line, marked DNI (Do Not Install). Without this pull-up, the ALERT line will float when not actively driven, which may cause issues since R67 connects this signal to U26 pin 3 (ALERT).** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="18.98,32.43,26.48,41.70" aspect-ratio="1.29" } - Pin 1 would connect to +V1P0S (1.0V standby supply rail) if populated *(from schematic)* - Pin 2 would connect to SVID_ALERT-R if populated *(from schematic)* - This component is marked DNI (Do Not Install) and is electrically absent from the circuit *(from schematic)* - R67 (0Ω jumper) connects SVID_ALERT-R through to U26 pin 3 (ALERT), indicating the alert signal path is intended to be active *(from schematic)* - SVID alert lines typically require pull-up resistors similar to data and clock lines, as they use open-drain outputs *(reasoning)* - Without a pull-up resistor, the ALERT line will float when not actively driven, which can cause undefined logic levels and potential noise sensitivity *(reasoning)* - If the alert function is intended to be used (suggested by R67 being populated), R196 should be populated with a pull-up resistor in the 1kΩ to 10kΩ range *(reasoning)* - If the alert function is not used, the DNI status may be acceptable, though best practice would be to leave the pin unconnected or ensure it has a defined state *(reasoning)*
Turbot.prj
AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:07:01 +00:00
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[🚨 Error] Component R816, pin 2: Connected to U41 pin 12 (TON) to set the switching frequency. However, the resistor value is 464K, which results in approximately 504 kHz switching frequency, not the specified 285 kHz that requires 806K per the design note.

  • Pin 2 is connected to net $25N1081 (from schematic)
  • Net $25N1081 connects to U41 pin 12 (TON) and C378 pin 2 (DNI) (from schematic)
  • C378 is marked DNI (Do Not Install), so it is electrically absent and does not affect the circuit (from schematic)
  • R816 has a value of 464K ohms per part number 1120-0149 (from schematic)
  • The design note states 'Rton=806K , F=285KHz' as the intended design specification (from schematic)
  • The design note provides the formula F= (Vin - 0.5) / 3.85pVinRton for calculating switching frequency (from schematic)
  • Using the formula with Vin=5V and Rton=806K: F = (5-0.5)/(3.85e-125806000) = 290 kHz, approximately matching the specified 285 kHz (reasoning)
  • Using the formula with Vin=5V and the actual Rton=464K: F = (5-0.5)/(3.85e-125464000) = 504 kHz (reasoning)
  • The actual resistor value of 464K results in a switching frequency of approximately 504 kHz, which is 77% higher than the specified 285 kHz (reasoning)
  • No other resistors are connected in parallel or series with R816 on the TON pin that would modify the effective resistance (from schematic)
  • The resistor value should be changed to approximately 806K to meet the design specification of 285 kHz switching frequency (reasoning)

Upload a datasheet: 📤 R816

[🚨 Error] **Component `R816`, pin `2`: Connected to U41 pin 12 (TON) to set the switching frequency. However, the resistor value is 464K, which results in approximately 504 kHz switching frequency, not the specified 285 kHz that requires 806K per the design note.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...eb22cbbe121fc6c44c06c9560f64e9392b916e9b" pr="193" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,36.84,35.12,44.34" aspect-ratio="1.29" } - Pin 2 is connected to net $25N1081 *(from schematic)* - Net $25N1081 connects to U41 pin 12 (TON) and C378 pin 2 (DNI) *(from schematic)* - C378 is marked DNI (Do Not Install), so it is electrically absent and does not affect the circuit *(from schematic)* - R816 has a value of 464K ohms per part number 1120-0149 *(from schematic)* - The design note states &#x27;Rton=806K , F=285KHz&#x27; as the intended design specification *(from schematic)* - The design note provides the formula F= (Vin - 0.5) / 3.85p*Vin*Rton for calculating switching frequency *(from schematic)* - Using the formula with Vin=5V and Rton=806K: F = (5-0.5)/(3.85e-12*5*806000) = 290 kHz, approximately matching the specified 285 kHz *(reasoning)* - Using the formula with Vin=5V and the actual Rton=464K: F = (5-0.5)/(3.85e-12*5*464000) = 504 kHz *(reasoning)* - The actual resistor value of 464K results in a switching frequency of approximately 504 kHz, which is 77% higher than the specified 285 kHz *(reasoning)* - No other resistors are connected in parallel or series with R816 on the TON pin that would modify the effective resistance *(from schematic)* - The resistor value should be changed to approximately 806K to meet the design specification of 285 kHz switching frequency *(reasoning)* <sub>Upload a datasheet: [📤 R816](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/2702cc92/.allspice/datasheets/1120-0149)</sub>

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Reference: NoIndexTests/E2E-Turbot-BOMGEN#193
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