E2E @ b39c3d51 - push to main #194

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shrikanthup wants to merge 2 commits from refs/pull/194/head into main

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Conversation 2 Commits 2 Changes 7 +512 -81

shrikanthup commented 2026-05-27 18:43:56 +00:00 (Migrated from staging.allspice.dev)

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Source: push to main
Ref: b39c3d51cbebe0a9f4865547df177b7e43dcde3c
Mode: e2e
Cache: enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache)
Cleanup: auto-closed after 7 days

Resolved config

{
  "dump_analysis_dir": "debug_dump",
  "libraries": [
    {
      "ipn_column": "IPN",
      "mpn_column": "MPN",
      "path": ".allspice/library.csv",
      "type": "csv"
    },
    {
      "digikey_client_id_env": "DIGIKEY_CLIENT_ID",
      "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET",
      "type": "digikey"
    }
  ]
}

Triggered at 2026-05-27T18:43:53.500655Z. Branch e9a05055 will be deleted on cleanup.

**Source:** push to main **Ref:** [`b39c3d51cbebe0a9f4865547df177b7e43dcde3c`](https://github.com/AllSpiceIO/connections-checker/tree/b39c3d51cbebe0a9f4865547df177b7e43dcde3c) **Mode:** e2e **Cache:** enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache) **Cleanup:** auto-closed after 7 days <details> <summary>Resolved config</summary> ```json { "dump_analysis_dir": "debug_dump", "libraries": [ { "ipn_column": "IPN", "mpn_column": "MPN", "path": ".allspice/library.csv", "type": "csv" }, { "digikey_client_id_env": "DIGIKEY_CLIENT_ID", "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET", "type": "digikey" } ] } ``` </details> Triggered at 2026-05-27T18:43:53.500655Z. Branch `e9a05055` will be deleted on cleanup.

AllSpiceAlice commented 2026-05-27 19:48:28 +00:00 (Migrated from staging.allspice.dev)

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DRCY has reviewed this Design Review, and there should be a review posted below.

DRCY has reviewed this Design Review, and there should be a review posted below.

AllSpiceAlice (Migrated from staging.allspice.dev) reviewed 2026-05-27 21:42:45 +00:00

AllSpiceAlice (Migrated from staging.allspice.dev) left a comment

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DRCY Connections Checker Review

DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 413 component(s) to review, and found 11 potential issue(s) in 13 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
AK12	DDI0_RCOMP_P	DDI_RCOMP_N	❌	DDI0_RCOMP differential pair pins are swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative signal) connects to net DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P indicating positive signal) connects to net DDI_RCOMP_N. These connections are reversed from what they should be. Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in both the schematic and datasheet (from schematic) Pin AK12 is labeled DDI0_RCOMP_P with _P suffix indicating positive signal in both the schematic and datasheet (from schematic) Pin AK13 connects to net DDI_RCOMP_P in the schematic (from schematic) Pin AK12 connects to net DDI_RCOMP_N in the schematic (from schematic) Compensation resistor R217 (402 ohm, 1%) correctly connects between nets DDI_RCOMP_N and DDI_RCOMP_P (from schematic) The datasheet identifies pin AK13 as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (with overline) (from datasheet 140-0004628, page 213) The datasheet identifies pin AK12 as DDI0_RCOMP_P (from datasheet 140-0004628, page 213) In differential signaling and pin naming conventions, overline notation indicates the negative or inverted signal (reasoning) The _P suffix in pin names conventionally indicates the positive signal in a differential pair (reasoning) Pin AK13 with overline should connect to DDI_RCOMP_N (negative net), not DDI_RCOMP_P (reasoning) Pin AK12 with _P suffix should connect to DDI_RCOMP_P (positive net), not DDI_RCOMP_N (reasoning) The nets should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)
AK13	~DDI0_RCOMP	DDI_RCOMP_P	❌	DDI0_RCOMP differential pair pins are swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative signal) connects to net DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P indicating positive signal) connects to net DDI_RCOMP_N. These connections are reversed from what they should be. Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in both the schematic and datasheet (from schematic) Pin AK12 is labeled DDI0_RCOMP_P with _P suffix indicating positive signal in both the schematic and datasheet (from schematic) Pin AK13 connects to net DDI_RCOMP_P in the schematic (from schematic) Pin AK12 connects to net DDI_RCOMP_N in the schematic (from schematic) Compensation resistor R217 (402 ohm, 1%) correctly connects between nets DDI_RCOMP_N and DDI_RCOMP_P (from schematic) The datasheet identifies pin AK13 as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (with overline) (from datasheet 140-0004628, page 213) The datasheet identifies pin AK12 as DDI0_RCOMP_P (from datasheet 140-0004628, page 213) In differential signaling and pin naming conventions, overline notation indicates the negative or inverted signal (reasoning) The _P suffix in pin names conventionally indicates the positive signal in a differential pair (reasoning) Pin AK13 with overline should connect to DDI_RCOMP_N (negative net), not DDI_RCOMP_P (reasoning) Pin AK12 with _P suffix should connect to DDI_RCOMP_P (positive net), not DDI_RCOMP_N (reasoning) The nets should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)
A29	RESERVED_A29	GPIO_NC13	✅	RESERVED_A29 pin connected to GPIO_NC13 with 10K pull-down resistor to ground. This configuration prevents the pin from floating when not actively driven.
B26	DDI0_BKLTCTL		✅	DDI0_BKLTCTL backlight control signal has no net connection. This is acceptable as backlight control may be handled externally or not required for HDMI.
B28	DDI0_VDDEN		✅	DDI0_VDDEN display power enable signal has no net connection. This is acceptable as display power may be handled externally or not required for HDMI.
B30	GPIO_S0_NC12	$3N566	✅	GPIO_S0_NC12 pin connected to test point TP15 and pulled down to ground through 10K resistor R102. This provides a test point with proper pull-down to prevent floating.
C26	DDI0_DDCDATA	HDMI_DDCDAT	✅	DDI0_DDCDATA connects to HDMI_DDCDAT, providing the I2C data line for HDMI DDC communication. This allows the system to read EDID from the HDMI display.
C27	DDI0_BKLTEN		✅	DDI0_BKLTEN backlight enable signal has no net connection. This is acceptable as backlight enable may be handled externally or not required for HDMI.
C28	DDI0_DDCCLK	HDMI_DDCCLK	✅	DDI0_DDCCLK connects to HDMI_DDCCLK, providing the I2C clock line for HDMI DDC communication. This allows the system to read EDID from the HDMI display.
C29	RESERVED_C29		✅	RESERVED_C29 pin has no net connection. Reserved pins without specific function can be left unconnected.
C30	RESERVED_C30		✅	RESERVED_C30 pin has no net connection. Reserved pins without specific function can be left unconnected.
D27	DDI0_HPD	HDMI_HPD_B	✅	DDI0_HPD connects to HDMI_HPD_B, which is the inverted output from Schmitt trigger inverter U39. The inverter receives HDMI_HPD and provides noise immunity for the hot plug detect signal.
D28	RESERVED_D28		✅	RESERVED_D28 pin has no net connection. Reserved pins without specific function can be left unconnected.
D32	RESERVED_D32		✅	RESERVED_D32 pin has no net connection. Reserved pins without specific function can be left unconnected.
D34	RESERVED_D34		✅	RESERVED_D34 pin has no net connection. Reserved pins without specific function can be left unconnected.
F28	RESERVED_F28		✅	RESERVED_F28 pin has no net connection. Reserved pins without specific function can be left unconnected.
F32	RESERVED_F32		✅	RESERVED_F32 pin has no net connection. Reserved pins without specific function can be left unconnected.
F34	RESERVED_F34		✅	RESERVED_F34 pin has no net connection. Reserved pins without specific function can be left unconnected.
G30	DDI1_DDCCLK	GND	✅	DDI1_DDCCLK connected directly to ground. This disables the DDC clock for DDI1, consistent with the intentional disabling of the DDI1 interface per design notes.
J28	RESERVED_J28		✅	RESERVED_J28 pin has no net connection. Reserved pins without specific function can be left unconnected.
J30	DDI1_BKLTEN		✅	DDI1_BKLTEN backlight enable signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
J34	RESERVED_J34		✅	RESERVED_J34 pin has no net connection. Reserved pins without specific function can be left unconnected.
K28	RESERVED_K28		✅	RESERVED_K28 pin has no net connection. Reserved pins without specific function can be left unconnected.
K30	DDI1_HPD	GND	✅	DDI1_HPD connected directly to ground. This indicates no display is connected to DDI1, consistent with the intentional disabling of the DDI1 interface per design notes.
K34	RESERVED_K34		✅	RESERVED_K34 pin has no net connection. Reserved pins without specific function can be left unconnected.
M30	DDI1_BKLTCTL		✅	DDI1_BKLTCTL backlight control signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
M32	RESERVED_M32		✅	RESERVED_M32 pin has no net connection. Reserved pins without specific function can be left unconnected.
N30	DDI1_VDDEN		✅	DDI1_VDDEN display power enable signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
N32	RESERVED_N32		✅	RESERVED_N32 pin has no net connection. Reserved pins without specific function can be left unconnected.
P14	RESERVED_P14	MCSI_RCOMP	✅	RESERVED_P14 pin connected to MCSI_RCOMP with 150 ohm resistor R213 to ground. This provides compensation for the MIPI CSI interface as indicated by the text note 'Bay Trail-I MCSI Port'.
P30	DDI1_DDCDATA	DDI1_DDCDAT	✅	DDI1_DDCDATA connects to DDI1_DDCDAT with 2.2K pull-down resistor R257 to ground. This disables the DDC data line for DDI1, consistent with the intentional disabling of the DDI1 interface per design notes.
R1	RESERVED_R1		✅	RESERVED_R1 pin has no net connection. Reserved pins without specific function can be left unconnected.
R3	RESERVED_R3		✅	RESERVED_R3 pin has no net connection. Reserved pins without specific function can be left unconnected.
T2	RESERVED_T2		✅	RESERVED_T2 pin has no net connection. Reserved pins without specific function can be left unconnected.
T3	RESERVED_T3		✅	RESERVED_T3 pin has no net connection. Reserved pins without specific function can be left unconnected.
T4	RESERVED_T4		✅	RESERVED_T4 pin has no net connection. Reserved pins without specific function can be left unconnected.
T6	RESERVED_T6		✅	RESERVED_T6 pin has no net connection. Reserved pins without specific function can be left unconnected.
T7	RESERVED_T7		✅	RESERVED_T7 pin has no net connection. Reserved pins without specific function can be left unconnected.
T9	RESERVED_T9		✅	RESERVED_T9 pin has no net connection. Reserved pins without specific function can be left unconnected.
T10	RESERVED_T10		✅	RESERVED_T10 pin has no net connection. Reserved pins without specific function can be left unconnected.
T12	RESERVED_T12		✅	RESERVED_T12 pin has no net connection. Reserved pins without specific function can be left unconnected.
T13	RESERVED_T13		✅	RESERVED_T13 pin has no net connection. Reserved pins without specific function can be left unconnected.
T14	RESERVED_T14		✅	RESERVED_T14 pin has no net connection. Reserved pins without specific function can be left unconnected.
V2	RESERVED_V2		✅	RESERVED_V2 pin has no net connection. Reserved pins without specific function can be left unconnected.
V3	RESERVED_V3		✅	RESERVED_V3 pin has no net connection. Reserved pins without specific function can be left unconnected.
V4	RESERVED_V4		✅	RESERVED_V4 pin has no net connection. Reserved pins without specific function can be left unconnected.
V6	RESERVED_V6		✅	RESERVED_V6 pin has no net connection. Reserved pins without specific function can be left unconnected.
V9	RESERVED_V9		✅	RESERVED_V9 pin has no net connection. Reserved pins without specific function can be left unconnected.
V10	RESERVED_V10		✅	RESERVED_V10 pin has no net connection. Reserved pins without specific function can be left unconnected.
V13	RESERVED_V13		✅	RESERVED_V13 pin has no net connection. Reserved pins without specific function can be left unconnected.
V14	RESERVED_V14		✅	RESERVED_V14 pin has no net connection. Reserved pins without specific function can be left unconnected.
W1	RESERVED_W1		✅	RESERVED_W1 pin has no net connection. Reserved pins without specific function can be left unconnected.
W3	RESERVED_W3		✅	RESERVED_W3 pin has no net connection. Reserved pins without specific function can be left unconnected.
Y2	RESERVED_Y2		✅	RESERVED_Y2 pin has no net connection. Reserved pins without specific function can be left unconnected.
Y3	RESERVED_Y3		✅	RESERVED_Y3 pin has no net connection. Reserved pins without specific function can be left unconnected.
Y4	RESERVED_Y4		✅	RESERVED_Y4 pin has no net connection. Reserved pins without specific function can be left unconnected.
Y6	RESERVED_Y6		✅	RESERVED_Y6 pin has no net connection. Reserved pins without specific function can be left unconnected.
Y12	RESERVED_Y12		✅	RESERVED_Y12 pin has no net connection. Reserved pins without specific function can be left unconnected.
Y13	RESERVED_Y13		✅	RESERVED_Y13 pin has no net connection. Reserved pins without specific function can be left unconnected.
BA1	VGA_GREEN		✅	VGA_GREEN output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated.
AB2	RESERVED_AB2		✅	RESERVED_AB2 pin has no net connection. Reserved pins without specific function can be left unconnected.
AB3	RESERVED_AB3		✅	RESERVED_AB3 pin has no net connection. Reserved pins without specific function can be left unconnected.
BA3	VGA_RED		✅	VGA_RED output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated.
AB7	RESERVED_AB7		✅	RESERVED_AB7 pin has no net connection. Reserved pins without specific function can be left unconnected.
AB9	RESERVED_AB9		✅	RESERVED_AB9 pin has no net connection. Reserved pins without specific function can be left unconnected.
AB12	RESERVED_AB12		✅	RESERVED_AB12 pin has no net connection. Reserved pins without specific function can be left unconnected.
AB13	RESERVED_AB13		✅	RESERVED_AB13 pin has no net connection. Reserved pins without specific function can be left unconnected.
AB14	RESERVED_AB14		✅	RESERVED_AB14 pin has no net connection. Reserved pins without specific function can be left unconnected.
AC1	DDI1_TXN_3		✅	DDI1_TXN_3 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
AC3	DDI1_TXP_3		✅	DDI1_TXP_3 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
BC1	VGA_DDCCLK	CRT_CLK	✅	VGA_DDCCLK connects through 150 ohm resistor R39 to ground. This terminates the DDC clock line, indicating VGA interface is intentionally disabled.
AD2	DDI1_TXN_2		✅	DDI1_TXN_2 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
BC2	VGA_DDCDATA	CRT_DAT	✅	VGA_DDCDATA connects through 150 ohm resistor R38 to ground. This terminates the DDC data line, indicating VGA interface is intentionally disabled.
AD3	DDI1_TXP_2		✅	DDI1_TXP_2 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
AD4	RESERVED_AD4		✅	RESERVED_AD4 pin has no net connection. Reserved pins without specific function can be left unconnected.
AD6	RESERVED_AD6		✅	RESERVED_AD6 pin has no net connection. Reserved pins without specific function can be left unconnected.
BD2	VGA_HSYNC		✅	VGA_HSYNC output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated.
AF2	DDI1_TXN_1		✅	DDI1_TXN_1 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
AF3	DDI1_TXP_1		✅	DDI1_TXP_1 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
AF13	RESERVED_AF13		✅	RESERVED_AF13 pin has no net connection. Reserved pins without specific function can be left unconnected.
AF14	RESERVED_AF14		✅	RESERVED_AF14 pin has no net connection. Reserved pins without specific function can be left unconnected.
AG1	DDI1_TXN_0		✅	DDI1_TXN_0 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
BF2	VGA_VSYNC		✅	VGA_VSYNC output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated.
AG3	DDI1_TXP_0		✅	DDI1_TXP_0 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
AH2	RESERVED_VSS3	$3N554	✅	RESERVED_VSS3 pin connected to ground through 0 ohm resistor R43. This provides a ground connection with the ability to isolate for debug purposes.
AH3	RESERVED_VSS2	$3N552	✅	RESERVED_VSS2 pin connected to ground through 0 ohm resistor R46. This provides a ground connection with the ability to isolate for debug purposes.
AH13	RESERVED_AH13		✅	RESERVED_AH13 pin has no net connection. Reserved pins without specific function can be left unconnected.
AH14	RESERVED_AH14		✅	RESERVED_AH14 pin has no net connection. Reserved pins without specific function can be left unconnected.
AK2	DDI1_AUXN		✅	DDI1_AUXN auxiliary channel negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
AK3	DDI1_AUXP		✅	DDI1_AUXP auxiliary channel positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes.
AL1	DDI0_AUXN		✅	DDI0_AUXN auxiliary channel negative signal has no net connection. This is acceptable as DDI0 is configured for HDMI which does not use the auxiliary channel.
AL3	DDI0_AUXP		✅	DDI0_AUXP auxiliary channel positive signal has no net connection. This is acceptable as DDI0 is configured for HDMI which does not use the auxiliary channel.
AM2	RESERVED_VSS1	$3N589	✅	RESERVED_VSS1 pin connected to ground through 0 ohm resistor R41. This provides a ground connection with the ability to isolate for debug purposes.
AM3	RESERVED_VSS0	$3N579	✅	RESERVED_VSS0 pin connected to ground through 0 ohm resistor R42. This provides a ground connection with the ability to isolate for debug purposes.
AM13	RESERVED_AM13		✅	RESERVED_AM13 pin has no net connection. Reserved pins without specific function can be left unconnected.
AM14	RESERVED_AM14		✅	RESERVED_AM14 pin has no net connection. Reserved pins without specific function can be left unconnected.
AP2	DDI0_TXN_3	HDMI_CLK_DN	✅	DDI0_TXN_3 connects to HDMI_CLK_DN, providing the negative differential clock signal for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AP3	DDI0_TXP_3	HDMI_CLK_DP	✅	DDI0_TXP_3 connects to HDMI_CLK_DP, providing the positive differential clock signal for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AR1	DDI0_TXN_2	HDMI_TX0_DN	✅	DDI0_TXN_2 connects to HDMI_TX0_DN, providing one of the negative differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AR3	DDI0_TXP_2	HDMI_TX0_DP	✅	DDI0_TXP_2 connects to HDMI_TX0_DP, providing one of the positive differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AT2	DDI0_TXP_1	HDMI_TX1_DP	✅	DDI0_TXP_1 connects to HDMI_TX1_DP, providing one of the positive differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AT3	DDI0_TXN_1	HDMI_TX1_DN	✅	DDI0_TXN_1 connects to HDMI_TX1_DN, providing one of the negative differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AV2	DDI0_TXN_0	HDMI_TX2_DN	✅	DDI0_TXN_0 connects to HDMI_TX2_DN, providing one of the negative differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AV3	DDI0_TXP_0	HDMI_TX2_DP	✅	DDI0_TXP_0 connects to HDMI_TX2_DP, providing one of the positive differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0.
AW1	VGA_IREF	$3N548	✅	VGA_IREF pin connects through 357 ohm resistor R40 to ground, setting the reference current for the VGA DAC. This configuration matches datasheet requirements for VGA DAC operation.
AY2	VGA_BLUE		✅	VGA_BLUE output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated.
AY3	VGA_IRTN	GND	✅	VGA_IRTN pin correctly connected to ground, providing the current return path for the VGA DAC as required by the datasheet.

U39 - SN74LVC1G14DCKR ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin with no net connection. This is acceptable per the datasheet which states the pin has no internal connection.
2	A	HDMI_HPD	✅	Input pin A connected to HDMI_HPD signal. This provides the Hot Plug Detect signal from the HDMI connector to the Schmitt-trigger inverter for signal conditioning.
3	GND	GND	✅	Ground pin correctly connected to the GND net.
4	Y	HDMI_HPD_B	✅	Output pin Y connected to HDMI_HPD_B which drives the CPU DDI0_HPD input. The inversion is intentional as indicated by the _B suffix in the signal name.
5	VCC	+V1P8S	✅	VCC pin connected to +V1P8S (1.8V supply) with proper bypass capacitor C375. The 1.8V supply is within the valid operating range and properly decoupled.

C375 - 123-0001056 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor pin connected to GND for bypass/decoupling function.
2	2	+V1P8S	✅	Capacitor pin connected to +V1P8S supply rail, providing local decoupling for U39 and the 1.8V power distribution.

R217 - 110-0004476 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI_RCOMP_N	✅	402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, which connect to CPU1 pins AK12 and AK13 respectively. This appears to be a compensation resistor for the DDI (Display Digital Interface) interface.
2	2	DDI_RCOMP_P	✅	402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, which connect to CPU1 pins AK12 and AK13 respectively. This appears to be a compensation resistor for the DDI (Display Digital Interface) interface.

R213 - 110-0002631 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCSI_RCOMP	✅	Connected to MCSI_RCOMP net, which connects to CPU1 pin P14 (labeled as RESERVED_P14).
2	2	GND	✅	Connected to GND, providing the ground reference for the MCSI compensation resistor.

R40 - 110-0004695 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$3N548	✅	Pin 1 connects to the VGA_IREF pin (AW1) of the Intel Atom E3825 SOC (CPU1) via net $3N548. This sets the reference current for the VGA DAC output.
2	2	GND	✅	Pin 2 connects to GND, completing the reference current path for the VGA DAC.

R257 - 110-0001984 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI1_DDCDAT	✅	Connected to DDI1_DDCDAT (CPU1 pin P30). This resistor is part of the intentional disabling of the DDI1 display port, providing a pull-down on the DDC data line.
2	2	GND	✅	Connected to GND, providing the return path for the pull-down resistor that terminates the unused DDI1_DDCDAT signal.

R38 - 110-0002631 ❌

DRCY flagged 2 potential issues in this component.

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_DAT	❌	Connected to VGA DDC data line (CRT_DAT) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor. Pin 1 is connected to net CRT_DAT (from schematic) Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic) DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation (reasoning) This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up (from schematic) The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC data line to ground, preventing any DDC communication (reasoning) If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) (reasoning) If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down (reasoning)
2	2	GND	❌	Connected to GND, forming the return path for the pull-down resistor. Pin 2 is connected to net GND (from schematic) This configuration creates a pull-down resistor from CRT_DAT to ground (from schematic)

R39 - 110-0002631 ❌

DRCY flagged 2 potential issues in this component.

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_CLK	❌	Connected to VGA DDC clock line (CRT_CLK) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor. Pin 1 is connected to net CRT_CLK (from schematic) Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) (from schematic) DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation (reasoning) This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up (from schematic) The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC clock line to ground, preventing any DDC communication (reasoning) If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) (reasoning) If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down (reasoning)
2	2	GND	❌	Connected to GND, forming the return path for the pull-down resistor. Pin 2 is connected to net GND (from schematic) This configuration creates a pull-down resistor from CRT_CLK to ground (from schematic)

R102 - 110-0001875 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for the pull-down resistor.
2	2	GPIO_NC13	✅	Pin 2 is connected to GPIO_NC13, which connects to CPU1 pin A29 (RESERVED_A29). This forms a 10K pull-down resistor on a reserved GPIO pin.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
C24	~PROCHOT	VR_HOT_L	✅	Processor hot thermal alert signal, correctly pulled up to 1.0V with 73.2Ω resistor.
N34	RESERVED_N34		✅	Reserved pin, left unconnected as permitted by design.
P34	RESERVED_P34		✅	Reserved pin, left unconnected as permitted by design.
BA12	SATA_GP0	SATA_GP0	✅	SATA general purpose output 0, correctly pulled down to ground with 10K resistor.
BA16	SATA_RXN_1	SATA1_RXN	✅	SATA port 1 receive negative signal, correctly AC-coupled to mSATA interface.
BA18	SD2_CLK		✅	SD2 clock signal, left unconnected as SD2 interface is unused.
BA20	SD2_D2		✅	SD2 data bit 2 signal, left unconnected as SD2 interface is unused.
BA24	~MMC1_RST		✅	MMC1 reset signal, left unconnected on this page but likely connected elsewhere.
BA26	SD3_D3	SD3_D3	✅	SD3 data bit 3 signal, routed to SD card interface.
BA30	LPE_I2S2_FRM	LPE_I2S_FRM	✅	I2S frame sync signal for Low Power Engine audio, correctly pulled up to 1.8V.
BB3	RESERVED_BB3		✅	Reserved pin, left unconnected as permitted by design.
BB4	RESERVED_BB4		✅	Reserved pin, left unconnected as permitted by design.
BB5	RESERVED_VSS6	RESERVED_VSS6	✅	Reserved VSS pin, correctly connected to ground through 0Ω resistor.
BB7	RESERVED_VSS7	RESERVED_VSS7	✅	Reserved VSS pin, correctly connected to ground through 0Ω resistor.
BB10	RESERVED_VSS4	ICLK_SATA_TERMP	✅	Reserved VSS pin, correctly connected to ground through 0Ω resistor.
BC10	RESERVED_VSS5	ICLK_SATA_TERMN	✅	Reserved VSS pin, correctly connected to ground through 0Ω resistor.
BC18	SD2_CMD		✅	SD2 command signal, left unconnected as SD2 interface is unused.
BC24	SD3_CD#	SD3_CD#	✅	SD3 card detect signal, connected to write protect through 0Ω resistor in intentional design choice.
BC30	LPE_I2S2_DATAOUT	LPE_I2S_DATOUT	✅	I2S data output signal for Low Power Engine audio, connected through 1K resistor to GPIO for hardware strapping.
BD5	SD3_WP_BD5	SD3_WP	✅	SD3 write protect signal, connected to card detect through 0Ω resistor in intentional design choice.
BD7	~PCIE_CLKREQ_1	CLKREQ1_B	✅	PCIe clock request 1 signal, correctly pulled up to 1.8V with 10K resistor.
BD10	SATA_TXP1	SATA1_TXP	✅	SATA port 1 transmit positive signal, correctly AC-coupled to mSATA interface.
BD18	~SD2_D3_CD		✅	SD2 data bit 3 / card detect signal, left unconnected as SD2 interface is unused.
BD20	SD2_D1		✅	SD2 data bit 1 signal, left unconnected as SD2 interface is unused.
BD22	~SD3_PWREN	/SD3+PWREN	✅	SD3 power enable signal, connected to test point for debug access.
BD26	SD3_D1	SD3_D1	✅	SD3 data bit 1 signal, routed to SD card interface.
BD28	LPE_I2S2_DATAIN	LPE_I2S_DATIN	✅	I2S data input signal for Low Power Engine audio, routed to audio codec.
BE3	~PCIE_CLKREQ_3	mPCIe_CLKREQ3_B	✅	PCIe clock request 3 signal, correctly pulled up to 1.8V with 10K resistor.
BF6	SATA_TXP_0	SATA0_TXP	✅	SATA port 0 transmit positive signal, correctly AC-coupled to SATA connector.
BF10	SATA_TXN_1	SATA1_TXN	✅	SATA port 1 transmit negative signal, correctly AC-coupled to mSATA interface.
BF20	HDA_LPE_RCOMP	HDA_RCOMP	✅	HDA/LPE compensation resistor pin, correctly connected to ground through 49.9Ω resistor.
BF22	SD3_1P8EN	SD3_1P8EN	✅	SD3 1.8V enable signal, connected to test point for debug access.
BF26	SD3_RCOMP	SD3_RCOMP	✅	SD3 compensation resistor pin, correctly connected to ground through 49.9Ω resistor.
BF28	LPE_I2S2_CLK	LPE_I2S_CLK	✅	I2S clock signal for Low Power Engine audio, routed to audio codec.
BG3	~PCIE_CLKREQ_0	CLKREQ0_B	✅	PCIe clock request 0 signal, correctly pulled up to 1.8V with 10K resistor.
BG5	~PCIE_CLKREQ_2	LAN_CLKREQ2_B	✅	PCIe clock request 2 signal, correctly pulled up to 1.8V with 10K resistor.
BG7	SATA_TXN_0	SATA0_TXN	✅	SATA port 0 transmit negative signal, correctly AC-coupled to SATA connector.
BG18	GPIO_S0_SC_15		✅	GPIO S0 SC 15 signal, left unconnected as this GPIO is unused.
BG19	HDA_SDI0		✅	HDA serial data input 0 signal, left unconnected as HDA interface is unused.
BG20	HDA_SDO		✅	HDA serial data output signal, left unconnected as HDA interface is unused.
BG21	HDA_SDI1		✅	HDA serial data input 1 signal, left unconnected as HDA interface is unused.
BG22	~HDA_RST		✅	HDA reset signal, left unconnected as HDA interface is unused.
BH18	GPIO_S0_SC_14		✅	GPIO S0 SC 14 signal, left unconnected as this GPIO is unused.
BH20	HDA_SYNC		✅	HDA sync signal, left unconnected as HDA interface is unused.
AK7	RESERVED_AK7		✅	Reserved pin, left unconnected as permitted by design.
AK9	RESERVED_AK9		✅	Reserved pin, left unconnected as permitted by design.
BJ21	HDA_CLK		✅	HDA clock signal, left unconnected as HDA interface is unused.
AP4	PCIE_TXN_3	mPCIE_TX_N	✅	PCIe lane 3 transmit negative signal, connected to mPCIe interface.
AP6	PCIE_TXP_3	mPCIE_TX_P	✅	PCIe lane 3 transmit positive signal, connected to mPCIe interface.
AP7	PCIE_RXN_3	mPCIE_RX_N	✅	PCIe lane 3 receive negative signal, connected to mPCIe interface.
AP9	PCIE_RXP_3	mPCIE_RX_P	✅	PCIe lane 3 receive positive signal, connected to mPCIe interface.
AP10	PCIE_RXN_2	PCIE_RXN2	✅	PCIe lane 2 receive negative signal, connected to LAN interface.
AP12	PCIE_RXP_2	PCIE_RXP2	✅	PCIe lane 2 receive positive signal, connected to LAN interface.
AP13	PCIE_RCOMP_N_AP13_AP13	PCIE_RCOMP_N	✅	PCIe compensation resistor negative terminal, correctly connected with 402Ω to positive terminal.
AP14	PCIE_RCOMP_P_AP14_AP14	PCIE_RCOMP_P	✅	PCIe compensation resistor positive terminal, correctly connected with 402Ω to negative terminal.
AT6	PCIE_TXN_2	PCIE_TXN2	✅	PCIe lane 2 transmit negative signal, connected to LAN interface.
AT7	PCIE_TXP_2	PCIE_TXP2	✅	PCIe lane 2 transmit positive signal, connected to LAN interface.
AT9	PCIE_RXN_1		✅	PCIe lane 1 receive negative signal, left unconnected as lane 1 is unused.
AT10	PCIE_RXP_1		✅	PCIe lane 1 receive positive signal, left unconnected as lane 1 is unused.
AT13	PCIE_RXN_0		✅	PCIe lane 0 receive negative signal, left unconnected as lane 0 is unused.
AT14	PCIE_RXP_0		✅	PCIe lane 0 receive positive signal, left unconnected as lane 0 is unused.
AT18	SATA_RCOMP_N_AT18	SATA_RCOMP_N	✅	SATA compensation resistor negative terminal, correctly connected with 402Ω to positive terminal.
AT20	MMC1_D3		✅	MMC1 data bit 3 signal, routed to eMMC interface.
AT22	MMC1_CLK		✅	MMC1 clock signal, routed to eMMC interface.
AT26	MMC1_D6		✅	MMC1 data bit 6 signal, routed to eMMC interface.
AT28	SD3_D0	SD3_D0	✅	SD3 data bit 0 signal, routed to SD card interface.
AU16	SATA_RXP_0	SATA0_RXP	✅	SATA port 0 receive positive signal, correctly AC-coupled to SATA connector.
AU18	SATA_RCOMP_P_AU18	SATA_RCOMP_P	✅	SATA compensation resistor positive terminal, correctly connected with 402Ω to negative terminal.
AU20	MMC1_D7		✅	MMC1 data bit 7 signal, routed to eMMC interface.
AU22	MMC1_D1		✅	MMC1 data bit 1 signal, routed to eMMC interface.
AU26	MMC1_D5		✅	MMC1 data bit 5 signal, routed to eMMC interface.
AU28	SD3_D2	SD3_D2	✅	SD3 data bit 2 signal, routed to SD card interface.
AV4	PCIE_TXN_1		✅	PCIe lane 1 transmit negative signal, left unconnected as lane 1 is unused.
AV6	PCIE_TXP_1		✅	PCIe lane 1 transmit positive signal, left unconnected as lane 1 is unused.
AV9	RESERVED_AV9		✅	Reserved pin, left unconnected as permitted by design.
AV10	RESERVED_AV10		✅	Reserved pin, left unconnected as permitted by design.
AV16	SATA_RXN_0	SATA0_RXN	✅	SATA port 0 receive negative signal, correctly AC-coupled to SATA connector.
AV20	MMC1_D0		✅	MMC1 data bit 0 signal, routed to eMMC interface.
AV22	MMC1_D2		✅	MMC1 data bit 2 signal, routed to eMMC interface.
AV26	MMC1_CMD		✅	MMC1 command signal, routed to eMMC interface.
AV28	SD3_CMD	SD3_CMD	✅	SD3 command signal, routed to SD card interface.
AY6	PCIE_TXN_0		✅	PCIe lane 0 transmit negative signal, left unconnected as lane 0 is unused.
AY7	PCIE_TXP_0		✅	PCIe lane 0 transmit positive signal, left unconnected as lane 0 is unused.
AY12	~SATA_LED	SATA_LED_B	✅	SATA LED output signal, correctly connected through current-limiting resistor to LED indicator.
AY14	SATA_GP1	SATA_GP1	✅	SATA general purpose output 1, correctly pulled down to ground with 10K resistor.
AY16	SATA_RXP_1	SATA1_RXP	✅	SATA port 1 receive positive signal, correctly AC-coupled to mSATA interface.
AY18	MMC1_RCOMP	MMC1_RCOMP	✅	MMC1 compensation resistor pin, correctly connected to ground through 49.9Ω resistor.
AY20	SD2_D0		✅	SD2 data bit 0 signal, left unconnected as SD2 interface is unused.
AY24	MMC1_D4		✅	MMC1 data bit 4 signal, routed to eMMC interface.
AY26	SD3_CLK	SD3_CLK	✅	SD3 clock signal, routed to SD card interface.

C10 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXP_C	✅	AC coupling capacitor for SATA TX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.
2	2	SATA0_TXP	✅	AC coupling capacitor for SATA TX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.

C11 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXN_C	✅	AC coupling capacitor for SATA TX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.
2	2	SATA0_TXN	✅	AC coupling capacitor for SATA TX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.

C12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXN_C	✅	AC coupling capacitor for SATA RX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.
2	2	SATA0_RXN	✅	AC coupling capacitor for SATA RX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.

C13 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXP_C	✅	AC coupling capacitor for SATA RX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.
2	2	SATA0_RXP	✅	AC coupling capacitor for SATA RX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification.

R239 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_RCOMP_N	✅	SATA RCOMP resistor correctly configured with 402 ohm value between CPU RCOMP pins for impedance calibration of SATA differential pairs.
2	2	SATA_RCOMP_P	✅	SATA RCOMP resistor correctly configured with 402 ohm value between CPU RCOMP pins for impedance calibration of SATA differential pairs.

R179 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_LED_B	✅	Current limiting resistor for SATA LED signal, correctly configured with 220 ohm value to limit current to approximately 8.2mA when jumper J6 is installed.
2	2	SATA_LED_R	✅	Current limiting resistor for SATA LED signal, correctly configured with 220 ohm value to limit current to approximately 8.2mA when jumper J6 is installed.

J6 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Jumper pin connected to +V1P8S supply, providing pull-up voltage for SATA LED signal when jumper is installed.
2	2	SATA_LED_R	✅	Jumper pin connected to SATA_LED_R net, allowing optional connection to +V1P8S for SATA LED functionality.

J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins for SATA signal connector, providing shielding between differential pairs. Correctly connected to GND net.
4	4	GND	✅	Ground pins for SATA signal connector, providing shielding between differential pairs. Correctly connected to GND net.
7	7	GND	✅	Ground pins for SATA signal connector, providing shielding between differential pairs. Correctly connected to GND net.
2	2	SATA0_TXP_C	✅	SATA TX+ signal pin, correctly connected through AC coupling capacitor C10 to CPU SATA0_TXP output.
3	3	SATA0_TXN_C	✅	SATA TX- signal pin, correctly connected through AC coupling capacitor C11 to CPU SATA0_TXN output.
5	5	SATA0_RXN_C	✅	SATA RX- signal pin, correctly connected through AC coupling capacitor C12 to CPU SATA0_RXN input.
6	6	SATA0_RXP_C	✅	SATA RX+ signal pin, correctly connected through AC coupling capacitor C13 to CPU SATA0_RXP input.
8	MH1	GND_EARTH	✅	Mounting hole pins correctly connected to GND_EARTH for EMI shielding and chassis ground connection.
9	MH2	GND_EARTH	✅	Mounting hole pins correctly connected to GND_EARTH for EMI shielding and chassis ground connection.

C177 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_N	✅	Connected to mSATA_RX_N net, providing AC coupling for SATA1 receive negative signal from mSATA connector to CPU.
2	2	SATA1_RXN	✅	Connected to SATA1_RXN net, which connects to CPU1 pin BA16 (SATA_RXN_1), completing the AC coupling path for the negative receive signal.

C178 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_P	✅	Connected to mSATA_RX_P net, providing AC coupling for SATA1 receive positive signal from mSATA connector to CPU.
2	2	SATA1_RXP	✅	Connected to SATA1_RXP net, which connects to CPU1 pin AY16 (SATA_RXP_1), completing the AC coupling path for the positive receive signal.

C179 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_P	✅	Connected to mSATA_TX_P net, providing AC coupling for SATA1 transmit positive signal from CPU to mSATA connector.
2	2	SATA1_TXP	✅	Connected to SATA1_TXP net, which connects to CPU1 pin BD10 (SATA_TXP1), completing the AC coupling path for the positive transmit signal.

C180 - 123-0001038 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_N	✅	Connected to mSATA_TX_N net, providing AC coupling for SATA1 transmit negative signal from CPU to mSATA connector.
2	2	SATA1_TXN	✅	Connected to SATA1_TXN net, which connects to CPU1 pin BF10 (SATA_TXN_1), completing the AC coupling path for the negative transmit signal.

R218 - 110-0004476 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PCIE_RCOMP_P	✅	Pin 1 connects to PCIE_RCOMP_P on the Intel Atom E3825 SOC (CPU1 pin AP14). This is the positive terminal of the PCIe compensation resistor.
2	2	PCIE_RCOMP_N	✅	Pin 2 connects to PCIE_RCOMP_N on the Intel Atom E3825 SOC (CPU1 pin AP13). This is the negative terminal of the PCIe compensation resistor.

R240 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for the MMC1_RCOMP compensation resistor.
2	2	MMC1_RCOMP	✅	Pin 2 is connected to MMC1_RCOMP on the CPU, providing impedance calibration reference for the MMC1 interface.

R258 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for the SD3_RCOMP compensation resistor.
2	2	SD3_RCOMP	✅	Pin 2 is connected to SD3_RCOMP on the CPU, providing impedance calibration reference for the SD3 interface.

R242 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDA_RCOMP	✅	Pin 1 is connected to HDA_RCOMP on the CPU, providing impedance calibration reference for the HDA interface.
2	2	GND	✅	Pin 2 is connected to GND, providing the ground reference for the HDA_RCOMP compensation resistor.

R189 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pull-down resistor connection to ground. Part of hardware strap configuration for GPIO_S0_SC_56, marked DNI.
2	2	GPIO_S0_SC_56	✅	Connected to GPIO_S0_SC_56 strap pin. Shares net with R219 to form mutually exclusive pull-up/pull-down strap option.

R219 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pull-up resistor connection to +V1P8S supply. Part of hardware strap configuration for GPIO_S0_SC_56, marked DNI.
2	2	GPIO_S0_SC_56	✅	Connected to GPIO_S0_SC_56 strap pin. Shares net with R189 to form mutually exclusive pull-up/pull-down strap option.

R234 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP3	✅	Connected to BOM_OP3 net, providing pull-down for hardware identification bit 3.
2	2	GND	✅	Connected to GND, providing the pull-down path.

R208 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP2	✅	Connected to BOM_OP2 net, providing pull-down for hardware identification bit 2.
2	2	GND	✅	Connected to GND, providing the pull-down path.

R233 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP1	✅	Connected to BOM_OP1 net but marked DNI, allowing BOM_OP1 to be pulled high through R211.
2	2	GND	✅	Connected to GND but component is DNI.

R401 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP4	✅	Connected to BOM_OP4 net but marked DNI, allowing BOM_OP4 to be pulled high through R400.
2	2	GND	✅	Connected to GND but component is DNI.

R209 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A but marked DNI, allowing BOM_OP2 to be pulled low through R208.
2	2	BOM_OP2	✅	Connected to BOM_OP2 but component is DNI.

R210 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A but marked DNI, allowing BOM_OP3 to be pulled low through R234.
2	2	BOM_OP3	✅	Connected to BOM_OP3 but component is DNI.

R211 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A, providing pull-up for hardware identification bit 1.
2	2	BOM_OP1	✅	Connected to BOM_OP1, providing the pull-up path.

R400 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A, providing pull-up for hardware identification bit 4.
2	2	BOM_OP4	✅	Connected to BOM_OP4, providing the pull-up path.

R190 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ1_B	✅	Pin 1 connects to CLKREQ1_B, providing pull-up for the PCIe clock request 1 signal from the CPU.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the CLKREQ1_B signal.

R191 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ0_B	✅	Pin 1 connects to CLKREQ0_B, providing pull-up for the PCIe clock request 0 signal from the CPU.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the CLKREQ0_B signal.

R2 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mPCIe_CLKREQ3_B	✅	Pin 1 connects to mPCIe_CLKREQ3_B, providing pull-up for the PCIe clock request 3 signal from the CPU, associated with the mPCIe card slot.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the mPCIe_CLKREQ3_B signal.

R71 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_CLKREQ2_B	✅	Pin 1 connects to LAN_CLKREQ2_B, providing pull-up for the PCIe clock request 2 signal from the CPU, associated with the Intel LAN controller.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the LAN_CLKREQ2_B signal.

R259 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_10_UNLOCK	✅	Pin 1 connects to GPIO_S5_10_UNLOCK signal. This is one end of a series resistor that allows external control of a hardware strap pin.
2	2	LPE_I2S_DATOUT	✅	Pin 2 connects to LPE_I2S_DATOUT, which is also known as GPIO_S0_SC65 and serves as a hardware strap pin on the CPU.

R260 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_DATOUT	✅	Pin 1 connects to LPE_I2S_DATOUT. This is a DNI pull-down resistor option for the hardware strap pin.
2	2	GND	✅	Pin 2 connects to GND. This would provide a pull-down path if the component were populated.

R268 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_FRM	✅	Pin 1 connects to LPE_I2S_FRM, which is a hardware strap pin (GPIO_S0_SC63) on the CPU.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing a pull-up voltage for the strap pin.

R73 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND, providing ground reference for the 0-ohm resistor.
2	2	ICLK_SATA_TERMP	✅	Pin 2 connects to ICLK_SATA_TERMP, which is CPU pin BB10 (RESERVED_VSS4), grounding the SATA termination positive pin.

R74 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND, providing ground reference for the 0-ohm resistor.
2	2	ICLK_SATA_TERMN	✅	Pin 2 connects to ICLK_SATA_TERMN, which is CPU pin BC10 (RESERVED_VSS5), grounding the SATA termination negative pin.

R72 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS6	✅	Pin 1 connects to RESERVED_VSS6, which is CPU pin BB5, a reserved pin that should be grounded.
2	2	GND	✅	Pin 2 connects to GND, properly grounding the reserved CPU pin through the 0-ohm resistor.

R192 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS7	✅	Pin 1 connects to RESERVED_VSS7, which is CPU pin BB7, a reserved pin that should be grounded.
2	2	GND	✅	Pin 2 connects to GND, properly grounding the reserved CPU pin through the 0-ohm resistor.

R354 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SD3_WP	✅	0 ohm resistor connecting SD3_WP to SD3_CD#, tying the write protect and card detect signals together. This unusual configuration may be intentional for the Bay Trail-I processor variant.
2	2	SD3_CD#	✅	0 ohm resistor connecting SD3_WP to SD3_CD#, tying the write protect and card detect signals together. This unusual configuration may be intentional for the Bay Trail-I processor variant.

R255 - 110-0004474 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR_HOT_L	✅	Connected to VR_HOT_L net, which connects to the CPU's PROCHOT (Processor Hot) signal. This pin forms one end of a pull-up resistor for the thermal management signal.
2	2	+V1P0S	✅	Connected to +V1P0S (1.0V supply rail), providing the pull-up voltage for the PROCHOT signal through the 73.2 ohm resistor.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A9	ILB_RTC_X2	BRTCX2	✅	ILB_RTC_X2 is connected to 32.768 kHz crystal with 18pF load capacitor.
A13	GPIO_S5_9	SOC_USB_HOST_EN1	✅	GPIO_S5_9 is connected to SOC_USB_HOST_EN1 net for USB host enable control.
A17	GPIO_S5_3	mPCIE_WAKEB	✅	GPIO_S5_3 is connected to mPCIE_WAKEB net with optional 2.2K pull-up (DNI).
A21	PCU_SPI_MOSI	SOC_SPI_MOSI	✅	PCU_SPI_MOSI is connected through 0-ohm series resistor R103 to the SPI flash interface.
A25	SVID_DATA	SVID_DATA	✅	SVID_DATA is connected through 16.9-ohm series resistor to voltage regulator interface.
B7	PMC_CORE_PWROK	PMC_CORE_PWROK	✅	PMC_CORE_PWROK is connected through 0-ohm resistor to SYS_PWRGD with optional 1uF capacitor (DNI).
B8	ILB_RTC_EXTPAD	BVCCRTC_EXTPAD	✅	ILB_RTC_EXTPAD is connected to 0.1uF decoupling capacitor for RTC battery backup.
B10	~PMC_RSMRST	PMC_RSMRST	✅	PMC_RSMRST# is connected with 100K pull-down, 10K pull-up, and 10pF filter capacitor.
B14	GPIO_S5_6	BOM_OP2	✅	GPIO_S5_6 is connected to BOM_OP2 net for board option configuration.
B16	GPIO_S5_1	SOC_GPIO_S5_1	✅	GPIO_S5_1 is connected to SOC_GPIO_S5_1 net for general purpose I/O.
B18	GPIO_S5_0	SOC_GPIO_S5_0	✅	GPIO_S5_0 is connected to SOC_GPIO_S5_0 net for general purpose I/O.
B22	PCU_SPI_MISO	SOC_SPI_MISO	✅	PCU_SPI_MISO is connected through 0-ohm series resistor R36 to the SPI flash interface.
B24	~SVID_ALERT	SVID_ALERT	✅	SVID_ALERT# is connected through 20-ohm series resistor and 69.8-ohm pull-up.
C9	ILB_RTC_X1	BRTCX1	✅	ILB_RTC_X1 is connected to 32.768 kHz crystal with 18pF load capacitor.
C11	~ILB_RTC_TEST	ILB_RTC_TESTB	✅	ILB_RTC_TEST# is connected to RTC test signal.
C12	~ILB_RTC_RST	RTCRST_L	✅	ILB_RTC_RST# is connected with 20K pull-up to +RTCVCC and 1uF filter capacitor.
C13	GPIO_S5_8	SOC_USB_HOST_EN0	✅	GPIO_S5_8 is connected to SOC_USB_HOST_EN0 net for USB host enable control.
C15	GPIO_S5_7	BOM_OP3	✅	GPIO_S5_7 is connected to BOM_OP3 net for board option configuration.
C16	GPIO_S5_5	BOM_OP1	✅	GPIO_S5_5 is connected to BOM_OP1 net for board option configuration.
C17	GPIO_S5_4	BOM_OP4	✅	GPIO_S5_4 is connected to BOM_OP4 net for board option configuration.
C18	GPIO_S5_2	SOC_GPIO_S5_2	✅	GPIO_S5_2 is connected to SOC_GPIO_S5_2 net for general purpose I/O.
C19	GPIO_S5_10	GPIO_S5_10_UNLOCK	✅	GPIO_S5_10 is connected to GPIO_S5_10_UNLOCK net for general purpose I/O.
C21	~PCU_SPI_CS_11	SOC_SPI_CS1B	✅	PCU_SPI_CS_11# is connected through 0-ohm series resistor (DNI) to SPI chip select 1.
C22	PCU_SPI_CLK	SOC_SPI_CLK	✅	PCU_SPI_CLK is connected through 0-ohm series resistor to SPI clock with optional 10pF capacitor (DNI).
C23	~PCU_SPI_CS_00	SOC_SPI_CS0B	✅	PCU_SPI_CS_00# is connected through 0-ohm series resistor to SPI chip select 0.
C25	SVID_CLK	SVID_CLK-R	✅	SVID_CLK is connected to voltage regulator serial VID clock signal.
D14	TAP_TCK	XDP_H_TCK	✅	TAP_TCK is connected to JTAG test clock with 51-ohm series resistor from ground.
D18	~TAP_PRDY	XDP_H_PRDYB	✅	TAP_PRDY# is connected to JTAG probe ready signal.
D20	PMC_ACPRESENT	PMC_ACPRESENT	✅	PMC_ACPRESENT is connected with 2.2K pull-up to +V1P8A for AC power detection.
D22	~PMC_SLP_S3	PMC_SLP_S3_L	✅	PMC_SLP_S3# is connected to level shifter for S3 sleep state indication.
D26	PMC_SUSPWRDNACK	SUSPWRDNACK	✅	PMC_SUSPWRDNACK is connected with 10K pull-up to +V1P8A and test point.
F12	TAP_TDI	XDP_H_TDI	✅	TAP_TDI is connected to JTAG test data in with 51-ohm series resistor from +V1P8A.
F14	TAP_TMS	XDP_H_TMS	✅	TAP_TMS is connected to JTAG test mode select with 51-ohm series resistor from +V1P8A.
F16	~TAP_PREQ	XDP_H_PREQB	✅	TAP_PREQ# is connected to JTAG probe request signal.
F18	~PMC_SLP_S0IX	PMC_SLP_S0IX	✅	PMC_SLP_S0IX# is connected to test point for S0ix sleep state monitoring.
F20	~PMC_PLTRST	PMC_PLTRST_R_V1P8	✅	PMC_PLTRST# is connected to level shifter for platform reset signaling.
F22	~PMC_SLP_S4	PMC_SLP_S4_L	✅	PMC_SLP_S4# is connected to level shifter for S4 sleep state indication.
F26	~PMC_WAKE_PCIE_0	PMC_PCIE_WAKE_R	✅	PMC_WAKE_PCIE_0# is connected through dual Schottky diode with 1K pull-up to +V1P8A.
G12	~TAP_TRST	XDP_H_TRSTB	✅	TAP_TRST# is connected to JTAG test reset with 51-ohm series resistor from ground.
G16	TAP_TDO	XDP_H_TDO	✅	TAP_TDO is connected to JTAG test data out signal.
G18	~PMC_SUS_STAT	LPCPD_L	✅	PMC_SUS_STAT# is connected to test point for suspend status monitoring.
G24	PMC_SUSCLK0_G24	PMC_SUSCLK0	✅	PMC_SUSCLK0_G24 is connected to level shifter with optional 2.2K pull-up (DNI).
J18	GPIO_S5_25	XDP_H_OBSDATA_A2	✅	GPIO_S5_25 is connected to XDP_H_OBSDATA_A2 net for debug observation data.
J20	GPIO_S5_14	GPIO_S514_J20	✅	GPIO_S5_14 is connected with 10K pull-up to +V1P8A.
J24	GPIO_S5_17	GPIO_S5_17	✅	GPIO_S5_17 is connected to jumper header with 10K pull-up to +V1P8S.
J26	~PMC_PWRBTN	PMC_PWRBTN	✅	PMC_PWRBTN# is connected through dual diode circuit with optional 20K pull-up (DNI).
K18	GPIO_S5_27	EXP_GPIO1	✅	GPIO_S5_27 is connected to EXP_GPIO1 net for expansion GPIO.
K20	GPIO_S5_28	EXP_GPIO2	✅	GPIO_S5_28 is connected to EXP_GPIO2 net for expansion GPIO.
K24	GPIO_S5_22	GPIO_D2_LED_CTRL	✅	GPIO_S5_22 is connected to GPIO_D2_LED_CTRL net for LED control.
K26	~PMC_BATLOW	PMC_BATLOW	✅	PMC_BATLOW# is connected with 20K pull-up to +V1P8A for battery low detection.
M18	GPIO_S5_26	XDP_H_OBSDATA_A3	✅	GPIO_S5_26 is connected to XDP_H_OBSDATA_A3 net for debug observation data.
M20	GPIO_S5_24	XDP_H_OBSDATA_A1	✅	GPIO_S5_24 is connected to XDP_H_OBSDATA_A1 net for debug observation data.
M22	GPIO_S5_29	EXP_GPIO3	✅	GPIO_S5_29 is connected to EXP_GPIO3 net for expansion GPIO.
M24	GPIO_S5_30	EXP_GPIO4	✅	GPIO_S5_30 is connected to EXP_GPIO4 net for expansion GPIO.
N24	GPIO_S5_23	XDP_H_OBSDATA_A0	✅	GPIO_S5_23 is connected to XDP_H_OBSDATA_A0 net for debug observation data.
N26	GPIO_RCOMP	GPIO_RCOMP	✅	GPIO_RCOMP is connected to 49.9-ohm compensation resistor to ground.
BA28	SIO_SPI_MISO	SOC_SIO_SPI_MISO	✅	SIO_SPI_MISO is connected to SIO SPI master in slave out signal.
BA34	~SIO_UART1_RTS	SIO_UART1_RTSB	✅	SIO_UART1_RTS is connected to UART1 request to send signal.
AD10	RESERVED_AD10		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AD12	RESERVED_AD12		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AD9	RESERVED_AD9		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AD13	ICLK_RCOMP	ICLK_RCOMP	✅	ICLK_RCOMP is connected to 47.5-ohm compensation resistor to ground.
AD14	ICLK_ICOMP	ICLK_ICOMP	✅	ICLK_ICOMP is connected to 4.02K-ohm compensation resistor to ground.
BD32	~SIO_UART2_RTS		✅	SIO_UART2_RTS is not connected, indicating UART2 hardware flow control is not used.
BD34	SIO_UART2_TXD	SIO_UART2_TXD	✅	SIO_UART2_TXD is connected to UART2 transmit data signal.
AF4	PCIE_CLKP_00		✅	PCIE_CLKP_00 and PCIE_CLKN_00 are not connected, indicating PCIe port 0 is not used.
AF6	PCIE_CLKN_00		✅	PCIE_CLKP_00 and PCIE_CLKN_00 are not connected, indicating PCIe port 0 is not used.
AF7	PCIE_CLKP_11		✅	PCIE_CLKP_11 and PCIE_CLKN_11 are not connected, indicating PCIe port 1 is not used.
AF9	PCIE_CLKN_11		✅	PCIE_CLKP_11 and PCIE_CLKN_11 are not connected, indicating PCIe port 1 is not used.
BF32	~SIO_UART2_CTS		✅	SIO_UART2_CTS is not connected, indicating UART2 hardware flow control is not used.
BF34	SIO_UART2_RXD	SIO_UART2_RXD	✅	SIO_UART2_RXD is connected to UART2 receive data signal.
BG9	~PMC_RSTBTN	PMC_RSTBTN	✅	PMC_RSTBTN# is connected to reset button input signal.
AH10	ICLK_OSCOUT	XTAL25_OUT	✅	ICLK_OSCOUT is connected to 25 MHz crystal with 27pF load capacitor.
AH12	ICLK_OSCIN	XTAL25_IN	✅	ICLK_OSCIN is connected to 25 MHz crystal with 27pF load capacitor.
BH4	PMC_PLT_CLK_22		✅	PMC_PLT_CLK_22 is not connected, indicating platform clock 2 is not used.
BH5	PMC_PLT_CLK_11		✅	PMC_PLT_CLK_11 is not connected, indicating platform clock 1 is not used.
BH6	PMC_PLT_CLK_44		✅	PMC_PLT_CLK_44 is not connected, indicating platform clock 4 is not used.
BH7	PMC_PLT_CLK_00		✅	PMC_PLT_CLK_00 is not connected, indicating platform clock 0 is not used.
BH8	PMC_PLT_CLK_33	I2S_MCLK	✅	PMC_PLT_CLK_33 is connected to I2S_MCLK net for I2S master clock.
AK4	PCIE_CLKN_22	PCIE_CLK-N2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 are connected to PCIe port 2 clock outputs.
AK6	PCIE_CLKP_22	PCIE_CLK-P2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 are connected to PCIe port 2 clock outputs.
BJ9	PMC_PLT_CLK_55		✅	PMC_PLT_CLK_55 is not connected, indicating platform clock 5 is not used.
AM4	PCIE_CLKN_33	mPCIE_REFCLK_N	✅	PCIE_CLKN_33 and PCIE_CLKP_33 are connected to mini PCIe reference clock outputs.
AM6	PCIE_CLKP_33	mPCIE_REFCLK_P	✅	PCIE_CLKN_33 and PCIE_CLKP_33 are connected to mini PCIe reference clock outputs.
AM10	RESERVED_AM10		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AM9	RESERVED_AM9		✅	Reserved pins are correctly left unconnected per datasheet requirements.
AT32	SIO_PWM_11	SOC_PWM1	✅	SIO_PWM_11 is connected to SOC_PWM1 net for PWM output 1.
AT34	RESERVED		✅	Reserved pin is correctly left unconnected per datasheet requirements.
AU32	SIO_PWM_00	SOC_PWM0	✅	SIO_PWM_00 is connected to SOC_PWM0 net for PWM output 0.
AU34	SIO_UART1_RXD	SIO_UART1_RXD	✅	SIO_UART1_RXD is connected to UART1 receive data signal.
AV32	~SIO_SPI_CS	SOC_SIO_SPI_CS1	✅	SIO_SPI_CS is connected to SIO SPI chip select signal.
AV34	SIO_UART1_TXD	SIO_UART1_TXD	✅	SIO_UART1_TXD is connected to UART1 transmit data signal.
AY28	SIO_SPI_MOSI	SOC_SIO_SPI_MOSI	✅	SIO_SPI_MOSI is connected to SIO SPI master out slave in signal.
AY30	SIO_SPI_CLK	SOC_SIO_SPI_CLK	✅	SIO_SPI_CLK is connected to SIO SPI clock signal.
AY34	~SIO_UART1_CTS	SIO_UART1_CTSB	✅	SIO_UART1_CTS is connected to UART1 clear to send signal.

U19 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the 1.8V supply for the A-side of the level shifter.
2	A1	PMC_PLTRST_R_V1P8	✅	A1 is correctly connected to PMC_PLTRST_R_V1P8, which is the 1.8V platform reset signal from the CPU.
3	A2	PMC_SUSCLK0	✅	A2 is correctly connected to PMC_SUSCLK0, which is the suspend clock signal from the CPU at 1.8V level.
4	A3	PMC_SLP_S4_L	✅	A3 is correctly connected to PMC_SLP_S4_L, which is the active-low sleep S4 state signal from the CPU at 1.8V level.
5	A4	PMC_SLP_S3_L	✅	A4 is correctly connected to PMC_SLP_S3_L, which is the active-low sleep S3 state signal from the CPU at 1.8V level.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	SLP_S3_L	✅	B4 is correctly connected to SLP_S3_L, which is the 3.3V level-shifted version of the sleep S3 state signal.
8	B3	SLP_S4_L	✅	B3 is correctly connected to SLP_S4_L, which is the 3.3V level-shifted version of the sleep S4 state signal.
9	B2	SUSCLK_3P3	✅	B2 is correctly connected to SUSCLK_3P3, which is the 3.3V level-shifted version of the suspend clock signal.
10	B1	PMC_PLTRST_L	✅	B1 is correctly connected to PMC_PLTRST_L, which is the 3.3V level-shifted version of the platform reset signal.
11	VCCB	PWR_BUF1	✅	VCCB is correctly connected to PWR_BUF1, which is connected through R26 (0 ohm) to +3VSB, providing the 3.3V supply for the B-side of the level shifter.
12	OE	PMC_OE	✅	OE is correctly connected to PMC_OE, which is pulled up to +V1P8A through R57 (2.2K), enabling the level shifter when the 1.8V rail is present.

Y1 - 145-0004789 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BRTCX2	✅	Crystal terminal connected to BRTCX2 (CPU1 pin A9) with 18pF load capacitor C42 and 10M feedback resistor R76.
2	2	BRTCX1	✅	Crystal terminal connected to BRTCX1 (CPU1 pin C9) with 18pF load capacitor C43 and 10M feedback resistor R76.

BH1 - 353-0003073 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+VBAT	✅	Positive battery terminals connected to +VBAT net, which supplies backup power to the RTC circuit through current-limiting resistor R278 and OR-ing diode D5.
2	P2	+VBAT	✅	Positive battery terminals connected to +VBAT net, which supplies backup power to the RTC circuit through current-limiting resistor R278 and OR-ing diode D5.
3	N	GND	✅	Negative battery terminal correctly connected to ground.

D5 - 4536-0009 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	+PS_3VSB	✅	Anode connected to +PS_3VSB (3.3V standby supply), providing primary power to RTC when system is on.
A2	A2	+VBAT_R	✅	Anode connected to +VBAT_R (battery voltage through current-limiting resistor), providing backup power to RTC when system is off.
C	C	+RTCVCC	✅	Common cathode connected to +RTCVCC, supplying power to the RTC circuit from either system power or battery backup.

Y2 - 145-0004792 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XTAL25_IN	✅	Crystal input terminal correctly connected to CPU oscillator input (ICLK_OSCIN) with appropriate 27pF load capacitor and 1M feedback resistor.
2	2	GND	✅	Ground pin correctly connected to GND net for crystal ground reference.
3	3	XTAL25_OUT	✅	Crystal output terminal correctly connected to CPU oscillator output (ICLK_OSCOUT) with appropriate 27pF load capacitor and 1M feedback resistor.
4	4	GND	✅	Ground pin correctly connected to GND net for crystal ground reference.

D10 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	3VSB_OK	✅	Anode 1 connected to 3VSB_OK signal, which monitors the 3VSB power rail status. This input to the diode OR gate will pull PS_OUT_L low when 3VSB is not ready.
A2	A2	PMC_PWRBTN	✅	Anode 2 connected to PMC_PWRBTN signal from the SoC. This active-low power button input will pull PS_OUT_L low when the power button is pressed.
C	C	PS_OUT_L	✅	Common cathode output connected to PS_OUT_L. This active-low signal will be asserted when either 3VSB is not ready or the power button is pressed.

D3 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PCIE_WAKE	✅	Cathodes tied together and connected to PMC_PCIE_WAKE net with 2.2K pull-up to +3VSB. This configuration is typical for a common-anode dual Schottky diode used in parallel.
2	2	PMC_PCIE_WAKE	✅	Cathodes tied together and connected to PMC_PCIE_WAKE net with 2.2K pull-up to +3VSB. This configuration is typical for a common-anode dual Schottky diode used in parallel.
3	3	PMC_PCIE_WAKE_R	✅	Common anode connected to PMC_PCIE_WAKE_R net with 1K pull-up to +V1P8A and to CPU wake input. Provides unidirectional level translation from 3.3V to 1.8V domain.

J7 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_17	✅	Pin 1 connects to GPIO_S5_17 from the CPU (pin J24), with a 10K pull-up resistor (R183) to +V1P8S. This forms one side of a configuration jumper.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the jumper. When the jumper is installed, it pulls GPIO_S5_17 low.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A7	USB_HSIC_RCOMP	USB_HSIC0_RCOMP	✅	USB HSIC compensation resistor correctly connected to 45.3 ohm resistor to ground.
B4	USB_HSIC0_DATA		✅	USB HSIC0 data pin is not connected, indicating HSIC port 0 is not used in this design.
B5	USB_HSIC0_STROBE		✅	USB HSIC0 strobe pin is not connected, indicating HSIC port 0 is not used in this design.
B12	GPIO_S5_43		✅	GPIO_S5_43 (USB_ULPI_REFCLK) is not connected, indicating ULPI interface is not used.
B20	~USB_OC_11	SOC_USB_HOST_OC1	✅	USB overcurrent detect for port 1 correctly connected with 10K pull-up to +V1P8A.
C7	USB_RCOMPI	USB_RCOMP	✅	USB compensation resistor input correctly connected to 45.3 ohm resistor to ground.
C20	~USB_OC_00	SOC_USB_HOST_OC0	✅	USB overcurrent detect for port 0 correctly connected with 10K pull-up to +V1P8A.
D2	USB_HSIC1_STROBE		✅	USB HSIC1 strobe pin is not connected, indicating HSIC port 1 is not used.
D4	USB3_RXP0	USB3_RXP0	✅	USB3 receive positive differential signal for SuperSpeed operation.
D6	USB_RCOMPO	USB_RCOMP	✅	USB compensation resistor output correctly connected to 45.3 ohm resistor to ground.
D10	ICLK_USB_TERM_1	ICLK_USB_TERM_0	✅	USB termination correctly connected to 1K resistor to ground. Net naming is confusing but functionally correct.
E2	USB_HSIC1_DATA		✅	USB HSIC1 data pin is not connected, indicating HSIC port 1 is not used.
E3	USB3_RXN0	USB3_RXN0	✅	USB3 receive negative differential signal for SuperSpeed operation.
F10	ICLK_USB_TERMN	ICLK_USB_TERM_1	✅	USB termination correctly connected to 1K resistor to ground. Net naming is confusing but functionally correct.
G2	GPIO_S5_31		✅	GPIO_S5_31 (USB_ULPI_CLK) is not connected, indicating ULPI interface is not used.
G14	USB_DN1	USB_DN1	✅	USB 2.0 data negative for port 1.
H3	GPIO_S5_42		✅	GPIO_S5_42 (USB_ULPI_STP) is not connected, indicating ULPI interface is not used.
H4	RESERVED_H4		✅	Reserved pin is not connected per datasheet guidance.
H5	RESERVED_H5		✅	Reserved pin is not connected per datasheet guidance.
H7	RESERVED_H7		✅	Reserved pin is not connected per datasheet guidance.
H8	RESERVED_H8		✅	Reserved pin is not connected per datasheet guidance.
H10	USB_DN3		✅	USB 2.0 data negative for port 3 is not connected, indicating port 3 is not used.
J3	GPIO_S5_40		✅	GPIO_S5_40 (USB_ULPI_DIR) is not connected, indicating ULPI interface is not used.
J12	USB_DN2	USB_HOST_DN	✅	USB 2.0 data negative for port 2 (host port).
J14	USB_DP1	USB_DP1	✅	USB 2.0 data positive for port 1.
K2	GPIO_S5_34		✅	GPIO_S5_34 (USB_ULPI_DATA[2]) is not connected, indicating ULPI interface is not used.
K3	GPIO_S5_35		✅	GPIO_S5_35 (USB_ULPI_DATA[3]) is not connected, indicating ULPI interface is not used.
K6	USB3_TXP0	USB3_TXP0	✅	USB3 transmit positive differential signal for SuperSpeed operation.
K7	USB3_TXN0	USB3_TXN0	✅	USB3 transmit negative differential signal for SuperSpeed operation.
K10	USB_DP3		✅	USB 2.0 data positive for port 3 is not connected, indicating port 3 is not used.
K12	USB_DP2	USB_HOST_DP	✅	USB 2.0 data positive for port 2 (host port).
K16	USB_DN0	USB_DN0	✅	USB 2.0 data negative for port 0.
L1	GPIO_S5_33		✅	GPIO_S5_33 (USB_ULPI_DATA[1]) is not connected, indicating ULPI interface is not used.
L3	GPIO_S5_39		✅	GPIO_S5_39 (USB_ULPI_DATA[7]) is not connected, indicating ULPI interface is not used.
M2	GPIO_S5_36		✅	GPIO_S5_36 (USB_ULPI_DATA[4]) is not connected, indicating ULPI interface is not used.
M3	GPIO_S5_32		✅	GPIO_S5_32 (USB_ULPI_DATA[0]) is not connected, indicating ULPI interface is not used.
M4	RESERVED_M4		✅	Reserved pin is not connected per datasheet guidance.
M6	RESERVED_M6		✅	Reserved pin is not connected per datasheet guidance.
M7	RESERVED_M7		✅	Reserved pin is not connected per datasheet guidance.
M9	RESERVED_M9		✅	Reserved pin is not connected per datasheet guidance.
M10	RESERVED_M10		✅	Reserved pin is not connected per datasheet guidance.
M12	USB3_REXT0	USB3_REXT0	✅	USB3 external resistor correctly connected to 1.24K resistor to ground.
M13	USB_PLL_MON	USB_PLL_MON	✅	USB PLL monitor signal connected to DNI test point for debug access.
M16	USB_DP0	USB_DP0	✅	USB 2.0 data positive for port 0.
N3	GPIO_S5_37		✅	GPIO_S5_37 (USB_ULPI_DATA[5]) is not connected, indicating ULPI interface is not used.
P2	GPIO_S5_38		✅	GPIO_S5_38 (USB_ULPI_DATA[6]) is not connected, indicating ULPI interface is not used.
P3	GPIO_S5_41		✅	GPIO_S5_41 (USB_ULPI_NXT) is not connected, indicating ULPI interface is not used.
P6	RESERVED_P6		✅	Reserved pin is not connected per datasheet guidance.
P7	RESERVED_P7		✅	Reserved pin is not connected per datasheet guidance.
P10	RESERVED_P10		✅	Reserved pin is not connected per datasheet guidance.
P12	RESERVED_P12		✅	Reserved pin is not connected per datasheet guidance.
BC12	GPIO_S0_SC_56	GPIO_S0_SC_56	✅	GPIO_S0_SC_56 is connected but not used in visible circuitry on this page.
BC14	GPIO_S0_SC_58	HDMI_CEC	✅	GPIO_S0_SC_58 is configured as HDMI CEC signal.
BC16	GPIO_S0_SC_61	PCU_UART3_RXD	✅	GPIO_S0_SC_61 is configured as UART3 RXD with level shifting to 3.3V debug connector.
BD12	GPIO_S0_SC_55	GPIO_S0_SC_55	✅	GPIO_S0_SC_55 is connected to a DNI test point.
BD14	GPIO_S0_SC_57	PCU_UART3_TXD	✅	GPIO_S0_SC_57 is configured as UART3 TXD with level shifting to 3.3V debug connector.
BD16	GPIO_S0_SC_60		✅	GPIO_S0_SC_60 is not connected.
BF14	GPIO_S0_SC_59		✅	GPIO_S0_SC_59 is not connected.
BF18	LPC_RCOMP	LPC_RCOMP	✅	LPC compensation resistor correctly connected to 49.9 ohm resistor to ground.
BF27	SIO_I2C4_DATA		✅	I2C4 data pin is not connected, indicating I2C4 interface is not used.
BG11	~PCU_SMB_ALERT	PCU_SMB_ALERT	✅	SMBus alert signal correctly connected with 2.2K pull-up and routed to LAN SMBus.
BG12	PCU_SMB_DATA	PCU_SMB_DATA	✅	SMBus data signal correctly connected with 2.2K pull-up and level shifted to DDR SMBus.
BG13	ILB_LPC_SERIRQ		✅	LPC SERIRQ signal is not connected, indicating LPC interface is not used.
BG14	ILB_LPC_AD_33		✅	LPC address/data bit 3 is not connected, indicating LPC interface is not used.
BG15	ILB_LPC_CLK_00		✅	LPC clock 0 is not connected, indicating LPC interface is not used.
BG16	~ILB_LPC_CLKRUN		✅	LPC CLKRUN signal is not connected, indicating LPC interface is not used.
BG17	~ILB_LPC_FRAME		✅	LPC FRAME signal is not connected, indicating LPC interface is not used.
BG23	SIO_I2C0_CLK		✅	I2C0 clock pin is not connected, indicating I2C0 interface is not used.
BG24	SIO_I2C1_DATA	SIO_I2C1_SDA	✅	I2C1 data signal connected to DNI test point for debug access.
BG25	SIO_I2C2_DATA		✅	I2C2 data pin is not connected, indicating I2C2 interface is not used.
BG26	SIO_I2C3_DATA		✅	I2C3 data pin is not connected, indicating I2C3 interface is not used.
BG27	SIO_I2C4_CLK		✅	I2C4 clock pin is not connected, indicating I2C4 interface is not used.
BG28	SIO_I2C5_CLK	SI0_I2C5_SCL	✅	I2C5 clock signal correctly connected with 22 ohm series resistor for signal integrity.
BG29	SIO_I2C6_CLK	SI0_I2C6_SCL	✅	I2C6 clock signal correctly connected with 22 ohm series resistor for signal integrity.
BG30	GPIO_S0_SC_093	TP10_NET	✅	GPIO_S0_SC_093 is intentionally grounded through 0 ohm resistor as indicated by schematic notes.
BH10	PCU_SMB_CLK	PCU_SMB_CLK	✅	SMBus clock signal correctly connected with 2.2K pull-up and level shifted to DDR SMBus.
BH12	ILB_8254_SPKR	ILB_8254_SPKR	✅	Speaker output signal is connected for system audio.
BH14	ILB_LPC_CLK_11		✅	LPC clock 1 is not connected, indicating LPC interface is not used.
BH16	ILB_LPC_AD_00		✅	LPC address/data bit 0 is not connected, indicating LPC interface is not used.
BH22	SIO_I2C0_DATA		✅	I2C0 data pin is not connected, indicating I2C0 interface is not used.
BH24	SIO_I2C1_CLK	SIO_I2C1_SCL	✅	I2C1 clock signal connected to DNI test point for debug access.
BH26	SIO_I2C3_CLK		✅	I2C3 clock pin is not connected, indicating I2C3 interface is not used.
BH28	SIO_I2C5_DATA	SI0_I2C5_SDA	✅	I2C5 data signal correctly connected with 22 ohm series resistor for signal integrity.
BH30	GPIO_S0_SC_092	TP9_NET	✅	GPIO_S0_SC_092 is intentionally grounded through 0 ohm resistor as indicated by schematic notes.
BJ13	ILB_LPC_AD_22		✅	LPC address/data bit 2 is not connected, indicating LPC interface is not used.
BJ17	ILB_LPC_AD_11		✅	LPC address/data bit 1 is not connected, indicating LPC interface is not used.
BJ25	SIO_I2C2_CLK		✅	I2C2 clock pin is not connected, indicating I2C2 interface is not used.
BJ29	SIO_I2C6_DATA	SI0_I2C6_SDA	✅	I2C6 data signal correctly connected with 22 ohm series resistor for signal integrity.

R48 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BUF2_PWR	✅	0 ohm resistor connecting BUF2_PWR to +VCC3, providing 3.3V supply to the VCCB pin of level translator U5. This connection is correct.
2	2	+VCC3	✅	0 ohm resistor connecting BUF2_PWR to +VCC3, providing 3.3V supply to the VCCB pin of level translator U5. This connection is correct.

U5 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DDR_SMB_CLK	✅	B2 pin connected to DDR_SMB_CLK net, which is the 3.3V side of the SMBus clock channel 2. This connection is correct for translating the clock signal to the higher voltage domain.
2	GND	GND	✅	GND pin correctly connected to the ground net.
3	VCCA	+V1P8S	✅	VCCA pin connected to +V1P8S (1.8V supply), which is correct as the A-side reference voltage for the level translator.
4	A2	PCU_SMB_CLK	✅	A2 pin connected to PCU_SMB_CLK, which is the 1.8V side of the SMBus clock channel 2. This connection is correct for translating the clock signal from the CPU.
5	A1	PCU_SMB_DATA	✅	A1 pin connected to PCU_SMB_DATA, which is the 1.8V side of the SMBus data channel 1. This connection is correct for translating the data signal from the CPU.
6	OE	PCU_SMB_BUFF_ENB	✅	OE pin connected to PCU_SMB_BUFF_ENB with a pullup to +V1P8S. This enables the level translator and allows CPU control of the buffer enable.
7	VCCB	BUF2_PWR	✅	VCCB pin connected to BUF2_PWR, which is supplied by +VCC3 (3.3V) through R48. This is correct as the B-side reference voltage for the level translator.
8	B1	DDR_SMB_DATA	✅	B1 pin connected to DDR_SMB_DATA net, which is the 3.3V side of the SMBus data channel 1. This connection is correct for translating the data signal to the higher voltage domain.

R51 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BUF3_PWR	✅	R51 is a 0 ohm resistor connecting +3VSB to BUF3_PWR, which powers the B-side (VCCB) of level shifter U6. The 0 ohm resistor allows for easy disconnection if needed.
2	2	+3VSB	✅	R51 is a 0 ohm resistor connecting +3VSB to BUF3_PWR, which powers the B-side (VCCB) of level shifter U6. The 0 ohm resistor allows for easy disconnection if needed.

U6 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DBG_UART3_TXD	✅	B2 pin connects to DBG_UART3_TXD, which routes through R819 (330 ohm series resistor) to the debug connector J4 pin 5. This is the 3.3V side of the UART transmit channel from the CPU.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the reference ground for the level shifter IC.
3	VCCA	+V1P8S	✅	VCCA pin is connected to +V1P8S (1.8V supply), providing the reference voltage for the A-side (CPU side) of the level shifter. Properly decoupled by C30 (0.1uF).
4	A2	PCU_UART3_TXD	✅	A2 pin connects to PCU_UART3_TXD, which connects to CPU1 pin BD14 (GPIO_S0_SC_57). This is the 1.8V side of the UART transmit channel from the CPU.
5	A1	PCU_UART3_RXD	✅	A1 pin connects to PCU_UART3_RXD, which connects to CPU1 pin BC16 (GPIO_S0_SC_61). This is the 1.8V side of the UART receive channel to the CPU.
6	OE	LSENB	✅	OE pin is connected to LSENB, which is pulled high to +V1P8S through R52 (2.2K ohm). This permanently enables the level shifter, which is appropriate for an always-available debug interface.
7	VCCB	BUF3_PWR	✅	VCCB pin is connected to BUF3_PWR, which connects through R51 (0 ohm) to +3VSB (3.3V standby supply). Properly decoupled by C31 (0.1uF). This provides the reference voltage for the B-side (debug connector side).
8	B1	DBG_UART3_RXD	✅	B1 pin connects to DBG_UART3_RXD, which connects to J4 pin 4 (debug connector). This is the 3.3V side of the UART receive channel from the debug connector. R50 (100K) provides a weak pull-down.

J4 - SIP6_RA ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net, providing common reference for the serial interface.
2	2		✅	Pin 2 is unconnected, which is acceptable as hardware flow control is not implemented for this debug serial port.
3	3		✅	Pin 3 is unconnected, which is acceptable for this USB-to-TTL serial cable interface. The pin typically carries VCC on standard FTDI-style cables but is not required for basic UART operation.
4	4	DBG_UART3_RXD	✅	Pin 4 correctly connects to DBG_UART3_RXD, which receives data into the CPU after level shifting from 3.3V to 1.8V through U6.
5	5	DBG_UART3_TXD_R	✅	Pin 5 correctly connects to DBG_UART3_TXD_R, which transmits data from the CPU after level shifting from 1.8V to 3.3V through U6, with R819 providing series termination.
6	6		✅	Pin 6 is unconnected, which is acceptable as hardware flow control is not implemented for this debug serial port.

R241 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPC_RCOMP	✅	LPC bus compensation resistor connection. This pin correctly connects to the CPU's LPC_RCOMP pin (BF18) for impedance calibration.
2	2	GND	✅	Ground connection for LPC compensation resistor. This pin correctly connects to the ground plane.

R212 - 110-0004478 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_REXT0	✅	USB 3.0 external reference resistor connection. This pin correctly connects to the CPU's USB3_REXT0 pin (M12) for PHY calibration.
2	2	GND	✅	Ground connection for USB 3.0 external reference resistor. This pin correctly connects to the ground plane.

R185 - 110-0004472 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for USB 2.0 compensation resistor. This pin correctly connects to the ground plane.
2	2	USB_RCOMP	✅	USB 2.0 compensation resistor connection. This pin correctly connects to both USB_RCOMPO (D6) and USB_RCOMPI (C7) pins of the CPU, which are tied together for impedance calibration.

R77 - 110-0004472 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for USB HSIC compensation resistor. This pin correctly connects to the ground plane.
2	2	USB_HSIC0_RCOMP	✅	USB HSIC compensation resistor connection. This pin correctly connects to the CPU's USB_HSIC_RCOMP pin (A7) for impedance calibration.

R12 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SCL	✅	22 ohm series resistor on I2C6 SCL line between SOC pin (SI0_I2C6_SCL) and external bus (I2C6_SCL). This provides signal conditioning and damping for the I2C bus.
2	2	I2C6_SCL	✅	22 ohm series resistor on I2C6 SCL line between SOC pin (SI0_I2C6_SCL) and external bus (I2C6_SCL). This provides signal conditioning and damping for the I2C bus.

R11 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SDA	✅	22 ohm series resistor on I2C6 SDA line between SOC pin (SI0_I2C6_SDA) and external bus (I2C6_SDA). This provides signal conditioning and damping for the I2C bus.
2	2	I2C6_SDA	✅	22 ohm series resistor on I2C6 SDA line between SOC pin (SI0_I2C6_SDA) and external bus (I2C6_SDA). This provides signal conditioning and damping for the I2C bus.

R269 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SDA	✅	22 ohm series resistor on I2C5 SDA line between SOC pin (SI0_I2C5_SDA) and external bus (I2C5_SDA). This provides signal conditioning and damping for the I2C bus.
2	2	I2C5_SDA	✅	22 ohm series resistor on I2C5 SDA line between SOC pin (SI0_I2C5_SDA) and external bus (I2C5_SDA). This provides signal conditioning and damping for the I2C bus.

R270 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SCL	✅	22 ohm series resistor on I2C5 SCL line between SOC pin (SI0_I2C5_SCL) and external bus (I2C5_SCL). This provides signal conditioning and damping for the I2C bus.
2	2	I2C5_SCL	✅	22 ohm series resistor on I2C5 SCL line between SOC pin (SI0_I2C5_SCL) and external bus (I2C5_SCL). This provides signal conditioning and damping for the I2C bus.

R842 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-SMB-ALERT#	✅	Pin 1 connects to LAN-SMB-ALERT#, routing the SMBus alert signal to a LAN interface.
2	2	PCU_SMB_ALERT	✅	Pin 2 connects to PCU_SMB_ALERT, which is the active-low SMBus alert signal from CPU1 with a 10K pull-up to +V1P8S via R75.

R841 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_CLK	✅	Pin 1 connects to DDR_SMB_CLK, which is the B-side output of level shifter U5 and has a 2.2K pull-up to +VCC3 via R44.
2	2	LAN-SMB-CLK	✅	Pin 2 connects to LAN-SMB-CLK, routing the SMBus clock signal to a LAN interface, pairing with R840 for the complete SMBus interface.

R840 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_DATA	✅	Pin 1 connects to DDR_SMB_DATA, which is the B-side output of level shifter U5 and has a 2.2K pull-up to +VCC3 via R47.
2	2	LAN-SMB-DATA	✅	Pin 2 connects to LAN-SMB-DATA, routing the SMBus data signal to a LAN interface.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A48	DRAM_VDD_S4	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
AK38	DRAM_VDD_S4_AK38	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
AM38	DRAM_VDD_S4_AM38	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
AV41	DRAM_VDD_S4_AV41	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
AV42	DRAM_VDD_S4_AV42	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
BB46	DRAM_VDD_S4_BB46	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
BD49	DRAM_VDD_S4_BD49	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
BD52	DRAM_VDD_S4_BD52	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
BD53	DRAM_VDD_S4_BD53	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
BF44	DRAM_VDD_S4_BF44	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
BG51	DRAM_VDD_S4_BG51	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
BJ48	DRAM_VDD_S4_BJ48	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
C51	DRAM_VDD_S4_C51	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
D44	DRAM_VDD_S4_D44	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
F49	DRAM_VDD_S4_F49	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
F52	DRAM_VDD_S4_F52	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
F53	DRAM_VDD_S4_F53	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
H46	DRAM_VDD_S4_H46	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
M41	DRAM_VDD_S4_M41	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
M42	DRAM_VDD_S4_M42	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
V38	DRAM_VDD_S4_V38	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
Y38	DRAM_VDD_S4_Y38	+VDIMM	✅	DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors.
N28	CORE_VSS_SENSE_N28	VSS_SENSE	✅	CORE_VSS_SENSE pin correctly connected to VSS_SENSE net for ground reference sensing. This enables accurate voltage regulation by providing ground reference at the processor.
P28	CORE_VCC_SENSE_P28	VCC_SENSE	✅	CORE_VCC_SENSE pin correctly connected to VCC_SENSE net for core voltage sensing. This enables accurate voltage regulation by sensing core voltage at the processor.
AA22	TP2_CORE_VCC_S0IX	$9N615	✅	Test point pin TP2_CORE_VCC_S0IX connected to net $9N615 with DNI test point TP2. This provides access to monitor core VCC voltage in S0IX state for debug purposes.
AA24	UNCORE_VNN_S3_AA24	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AC22	UNCORE_VNN_S3_AC22	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AC24	UNCORE_VNN_S3_AC24	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AD22	UNCORE_VNN_S3_AD22	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AD24	UNCORE_VNN_S3_AD24	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AF22	UNCORE_VNN_S3_AF22	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AF24	UNCORE_VNN_S3_AF24	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AG22	UNCORE_VNN_S3_AG22	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AG24	UNCORE_VNN_S3_AG24	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AJ22	UNCORE_VNN_S3_AJ22	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AJ24	UNCORE_VNN_S3_AJ24	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AK22	UNCORE_VNN_S3_AK22	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AK24	UNCORE_VNN_S3_AK24	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AK25	UNCORE_VNN_S3_AK25	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AK27	UNCORE_VNN_S3_AK27	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AK29	UNCORE_VNN_S3_AK29	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AK30	UNCORE_VNN_S3_AK30	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AK32	UNCORE_VNN_S3_AK32	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AM22	UNCORE_VNN_S3_AM22	+VGFX	✅	UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors.
AA27	CORE_VCC_S0IX_AA27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AA29	CORE_VCC_S0IX_AA29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AA30	CORE_VCC_S0IX_AA30	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AC27	CORE_VCC_S0IX_AC27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AC29	CORE_VCC_S0IX_AC29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AC30	CORE_VCC_S0IX_AC30	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AD27	CORE_VCC_S0IX_AD27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AD29	CORE_VCC_S0IX_AD29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AD30	CORE_VCC_S0IX_AD30	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AF27	CORE_VCC_S0IX_AF27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AF29	CORE_VCC_S0IX_AF29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AG27	CORE_VCC_S0IX_AG27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AG29	CORE_VCC_S0IX_AG29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
AG30	CORE_VCC_S0IX_AG30	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
P26	CORE_VCC_S0IX_P26	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
P27	CORE_VCC_S0IX_P27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
U27	CORE_VCC_S0IX_U27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
U29	CORE_VCC_S0IX_U29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
V27	CORE_VCC_S0IX_V27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
V29	CORE_VCC_S0IX_V29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
V30	CORE_VCC_S0IX_V30	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
Y27	CORE_VCC_S0IX_Y27	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
Y29	CORE_VCC_S0IX_Y29	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
Y30	CORE_VCC_S0IX_Y30	+VCORE	✅	CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors.
BB8	UNCORE_VNN_SENSE	VCCGT_SENSE	✅	UNCORE_VNN_SENSE pin correctly connected to VCCGT_SENSE net for voltage regulator feedback. This enables accurate voltage regulation by sensing voltage at the processor.
AD38	DRAM_VDD_S4_AD38	DRAM_VDD_CLK	✅	DRAM_VDD_S4 clock power pins correctly connected to DRAM_VDD_CLK rail, which is isolated from main +VDIMM through 0-ohm jumper R275. This provides clean power for DDR3L clock outputs with dedicated decoupling.
AF38	DRAM_VDD_S4_AF38	DRAM_VDD_CLK	✅	DRAM_VDD_S4 clock power pins correctly connected to DRAM_VDD_CLK rail, which is isolated from main +VDIMM through 0-ohm jumper R275. This provides clean power for DDR3L clock outputs with dedicated decoupling.
AF30	TP_CORE_V1P05_S4	$9N613	✅	Test point pin TP_CORE_V1P05_S4 connected to net $9N613 with DNI test point TP1. This provides access to monitor the 1.05V core supply in S4 state for debug purposes.

C292 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Provides the ground reference for the decoupling capacitor.
2	2	DRAM_VDD_CLK	✅	Connected to DRAM_VDD_CLK. Provides 1uF bulk decoupling capacitance for the DRAM clock power rail.

R275 - 110-0002124 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Connected to +VDIMM power rail. This pin sources power for the DRAM clock power rail through the 0-ohm jumper.
2	2	DRAM_VDD_CLK	✅	Connected to DRAM_VDD_CLK power rail. This pin provides power to the DRAM clock power domain with separate decoupling.

C291 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Provides the ground reference for the decoupling capacitor.
2	2	DRAM_VDD_CLK	✅	Connected to DRAM_VDD_CLK. Provides 0.1uF high-frequency decoupling for the DRAM clock power rail.

CPU1 - INTEL_ATOM_E3825_SOC ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
AC32	CORE_V1P05_S3_AC32	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
Y32	CORE_V1P05_S3_Y32	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
AA33	CORE_V1P05_S3_AA33	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
AF33	CORE_V1P05_S3_AF33	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
AG33	CORE_V1P05_S3_AG33	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
AG35	CORE_V1P05_S3_AG35	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
U33	CORE_V1P05_S3_U33	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
U35	CORE_V1P05_S3_U35	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
V33	CORE_V1P05_S3_V33	+V1P0S	❌	CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic) All nine pins are connected to the +V1P0S net in the schematic (from schematic) The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119) The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning) The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning) These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning) The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning) Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic) Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning) These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)
A3	VSS_A3_A3	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
A5	VSS_A5_A5	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
A6	VSS_A6_A6	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
A49	VSS_A49_A49	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
A51	VSS_A51_A51	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
A52	VSS_A52_A52	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
B2	VSS_B2_B2	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
B52	VSS_B52_B52	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
B53	VSS_B53_B53	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BE1	VSS_BE1_BE1	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BE53	VSS_BE53_BE53	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BG1	VSS_BG1_BG1	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BG53	VSS_BG53_BG53	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BH1	VSS_BH1_BH1	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BH2	VSS_BH2_BH2	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BH52	VSS_BH52_BH52	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BH53	VSS_BH53_BH53	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BJ2	VSS_BJ2_BJ2	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BJ3	VSS_BJ3_BJ3	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BJ5	VSS_BJ5_BJ5	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BJ49	VSS_BJ49_BJ49	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BJ51	VSS_BJ51_BJ51	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
BJ52	VSS_BJ52_BJ52	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
C1	VSS_C1_C1	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
C53	VSS_C53_C53	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
E1	VSS_E1_E1	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
E53	VSS_E53_E53	GND	✅	VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC.
B6	UNCORE_V1P0_G3_B6	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic.
C5	UNCORE_V1P0_G3_C5	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic.
U22	UNCORE_V1P0_G3_U22	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic.
V22	UNCORE_V1P0_G3_V22	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic.
C3	USB3_V1P0_G3_C3	+V1P0A	✅	USB3_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to the USB 3.0 interface.
Y19	USB3_V1P0_G3_Y19	+V1P0A	✅	USB3_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to the USB 3.0 interface.
F1	RESERVED_F1	$10N1595	✅	RESERVED_F1 pin connected to test point TP4 which is marked DNI. This is acceptable for a reserved pin.
M14	USB_V1P0_S3_M14	+V1P0S	✅	USB_V1P0_S3 pins correctly connected to +V1P0S rail. These supply 1.0V power to the USB interface logic.
U18	USB_V1P0_S3_U18	+V1P0S	✅	USB_V1P0_S3 pins correctly connected to +V1P0S rail. These supply 1.0V power to the USB interface logic.
U19	USB_V1P0_S3_U19	+V1P0S	✅	USB_V1P0_S3 pins correctly connected to +V1P0S rail. These supply 1.0V power to the USB interface logic.
N18	USB_V3P3_G3_N18	+3VSB	✅	USB_V3P3_G3 pins correctly connected to +3VSB rail. These supply always-on 3.3V power to the USB interface.
P18	USB_V3P3_G3_P18	+3VSB	✅	USB_V3P3_G3 pins correctly connected to +3VSB rail. These supply always-on 3.3V power to the USB interface.
N20	USB_V1P8_G3_N20	+V1P8A	✅	USB_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to the USB interface.
N22	PCU_V3P3_G3_N22	+3VSB	✅	PCU_V3P3_G3 pin correctly connected to +3VSB rail. This supplies always-on 3.3V power to the Platform Control Unit.
P22	RTC_VCC_P22	+RTCVCC	✅	RTC_VCC pin correctly connected to +RTCVCC rail with 0.1uF decoupling capacitor. This supplies battery-backed power to the Real Time Clock.
U16	USB_VSSA_U16	GND	✅	USB_VSSA pin correctly connected to GND net. This provides analog ground for the USB interface.
U24	UNCORE_V1P8_G3_U24	+V1P8A	✅	UNCORE_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to uncore logic.
U25	PMU_V1P8_G3_U25	+V1P8A	✅	PMU_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to the Power Management Unit.
V18	USB_HSIC_V1P24_G3_V18	+V1P0A	✅	USB_HSIC_V1P24_G3 pin correctly connected to +V1P0A rail. This is correct when USB HSIC is not used per datasheet guidance.
V22	UNCORE_V1P0_G3_V22	+V1P0A	✅	UNCORE_V1P0_G3 and UNCORE_V1P0_S0IX pins correctly connected to their respective power rails (+V1P0A and VCC_VIS_V1P0).
Y22	UNCORE_V1P0_S0IX_Y22	VCC_VIS_V1P0	✅	UNCORE_V1P0_G3 and UNCORE_V1P0_S0IX pins correctly connected to their respective power rails (+V1P0A and VCC_VIS_V1P0).
V24	UNCORE_V1P0_S0IX_V24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem.
Y24	UNCORE_V1P0_S0IX_Y24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem.
V25	PCU_V1P8_G3_V25	+V1P8A	✅	PCU_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to the Platform Control Unit.
V32	SVID_V1P0_S3_V32	+V1P0S	✅	SVID_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies 1.0V power to the SVID interface logic.
AA18	UNCORE_V1P8_G3_AA18	+V1P8A	✅	UNCORE_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to uncore logic.
AD16	VSS_AD16	VCC_VSS_V1P2	✅	VSS_AD16 and VSS_AD18 pins connected to VCC_VSS_V1P2 net, which connects through R216 to GND. This is correct when MIPI CSI is not used.
AD18	VSS_AD18	VCC_VSS_V1P2	✅	VSS_AD16 and VSS_AD18 pins connected to VCC_VSS_V1P2 net, which connects through R216 to GND. This is correct when MIPI CSI is not used.
AD35	DRAM_V1P0_S0IX_AD35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
AF35	DRAM_V1P0_S0IX_AF35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
AF36	DRAM_V1P0_S0IX_AF36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
AJ36	DRAM_V1P0_S0IX_AJ36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
AK35	DRAM_V1P0_S0IX_AK35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
AK36	DRAM_V1P0_S0IX_AK36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
Y35	DRAM_V1P0_S0IX_Y35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
Y36	DRAM_V1P0_S0IX_Y36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
AA36	DRAM_V1P0_S0IX_AA36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling.
BD1	VGA_V1P35_S3_F1_BD1	VCC_CRT_V1P35	✅	VGA_V1P35_S3_F1 pin correctly connected to VCC_CRT_V1P35 rail through ferrite bead FB4 from +V1P35S. This supplies filtered 1.35V power to the VGA interface.
AF16	UNCORE_V1P0_S3_AF16	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state.
AF18	UNCORE_V1P0_S3_AF18	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state.
G1	UNCORE_V1P0_S3_G1	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state.
Y18	UNCORE_V1P0_S3_Y18	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state.
AF21	UNCORE_V1P0_S0IX_AF21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, which connects through R222 to +V1P0S. These supply power to the graphics/display subsystem.
AG21	UNCORE_V1P0_S0IX_AG21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, which connects through R222 to +V1P0S. These supply power to the graphics/display subsystem.
AG18	ICLK_V1P35_S3_F2	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail through ferrite bead FB5 from +V1P35S. These supply power to the integrated clock logic.
AJ19	ICLK_V1P35_S3_F1_AJ19	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail through ferrite bead FB5 from +V1P35S. These supply power to the integrated clock logic.
AG19	UNCORE_V1P35_S0IX_F1_AG19	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling.
AG32	UNCORE_V1P35_S0IX_F2_AG32	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling.
AA25	UNCORE_V1P35_S0IX_F5_AA25	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling.
AF19	UNCORE_V1P35_S0IX_F6	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling.
V36	UNCORE_V1P35_S0IX_F3_V36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling.
U36	UNCORE_V1P35_S0IX_F4_U36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling.
AD36	DRAM_V1P35_S0IX_F1_AD36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling.
AJ18	DDI_V1P0_S0IX_AJ18	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic.
AK19	DDI_V1P0_S0IX_AK19	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic.
AK21	DDI_V1P0_S0IX_AK21	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic.
AM16	DDI_V1P0_S0IX_AM16	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic.
BJ6	VGA_V1P0_S3_BJ6	+V1P0S	✅	VGA_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies 1.0V power to the VGA interface logic.
AK18	PCIE_V1P0_S3_AK18	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic.
AM18	PCIE_V1P0_S3_AM18	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic.
AM21	PCIE_V1P0_S3_AM21	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic.
AN21	PCIE_V1P0_S3_AN21	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic.
AM27	LPC_V1P8V3P3_S3_AM27	+VCC3S	✅	LPC_V1P8V3P3_S3 pin correctly connected to +VCC3S rail. This supplies power to the LPC interface.
AM30	UNCORE_V1P8_S3_AM30	+V1P8S	✅	UNCORE_V1P8_S3 pins correctly connected to +V1P8S rail with appropriate decoupling. These supply 1.8V power to uncore logic.
AN32	UNCORE_V1P8_S3_AN32	+V1P8S	✅	UNCORE_V1P8_S3 pins correctly connected to +V1P8S rail with appropriate decoupling. These supply 1.8V power to uncore logic.
U38	UNCORE_V1P8_S3_U38	+V1P8S	✅	UNCORE_V1P8_S3 pins correctly connected to +V1P8S rail with appropriate decoupling. These supply 1.8V power to uncore logic.
AM32	HDA_LPE_V1P5V1P8_S3_AM32	+V1P8S	✅	HDA_LPE_V1P5V1P8_S3 pin correctly connected to +V1P8S rail. This supplies power to the HD Audio and Low Power Engine.
AN16	VSSA_AN16	GND	✅	VSSA pin correctly connected to GND net. This provides analog ground for the SoC.
AN18	PCIE_SATA_V1P0_S3_AN18	+V1P0S	✅	PCIE_SATA_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies power to the PCIe and SATA interface logic.
AN19	SATA_V1P0_S3_AN19	+V1P0S	✅	SATA_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies power to the SATA interface logic.
AN24	VGA_V3P3_S3_AN24	+VCC3S	✅	VGA_V3P3_S3 pin correctly connected to +VCC3S rail. This supplies 3.3V power to the VGA interface.
AN25	GPIO_V1P0_S3_AN25	+V1P0S	✅	GPIO_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies power to the GPIO logic.
AN27	SD3_V1P8V3P3_S3_AN27	+VCC3S	✅	SD3_V1P8V3P3_S3 pin correctly connected to +VCC3S rail. This supplies power to the SD card interface.
AN29	UNCORE_V1P0_S0IX_AN29	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem.
AN30	UNCORE_V1P0_S0IX_AN30	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem.

FB4 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply.
2	2	VCC_CRT_V1P35	✅	Output pin connected to VCC_CRT_V1P35, which powers the VGA/CRT interface. The ferrite provides filtering for this power domain.

FB5 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply.
2	2	VCC_ICLK_V1P35	✅	Output pin connected to VCC_ICLK_V1P35, which powers the internal clock circuitry. The ferrite provides filtering for this power domain.

FB3 - FERRITE_600OHM_1.3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply.
2	2	VCC_UNCORE_V1P35	✅	Output pin connected to VCC_UNCORE_V1P35, which powers multiple CPU UNCORE and DRAM voltage pins. The ferrite provides filtering for this power domain.

R222 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pin 1 connects to the main +V1P0S power rail, which supplies 1.0V to most CPU domains.
2	2	VCC_VIS_V1P0	✅	Pin 2 connects to VCC_VIS_V1P0, which powers the visual/graphics UNCORE_V1P0_S0IX domain of the CPU.

R265 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pin 1 connects to the main +V1P0S power rail, which supplies 1.0V to most CPU domains.
2	2	VCC_DRAM	✅	Pin 2 connects to VCC_DRAM, which powers the DRAM_V1P0_S0IX domain of the CPU.

R216 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VSS_V1P2	✅	Pin 1 connects to VCC_VSS_V1P2, which is connected to CPU VSS pins AD16 and AD18 (MIPI CSI analog ground pins).
2	2	GND	✅	Pin 2 connects to GND, implementing the grounded configuration for MIPI CSI VSS pins when CSI is not used.

D7 - D5V0L1B2LP-7B ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Pin N is connected to GND, completing the TVS protection circuit for the +5VSB rail.
P	P	+5VSB	✅	Pin P is connected to +5VSB rail for ESD protection of the 5V standby power supply.

J2 - 258-0004524 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to +5VSB but the component is marked DNI (Do Not Install) as an alternate to J8.
2	2	GND	✅	Pin 2 is connected to GND but the component is marked DNI as an alternate to J8.

C153 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to +5VSB for power supply decoupling and filtering.
2	2	GND	✅	Pin 2 is connected to GND, completing the bypass capacitor circuit for +5VSB filtering.

J8 - 3430-0212 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to +5VSB power rail, providing 5V standby power through this connector.
2	2	GND	✅	Pin 2 is connected to GND, providing the ground return path for the connector.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A11	VSS1	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A15	VSS2	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A19	VSS3	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A23	VSS4	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A27	VSS5	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A31	VSS6	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A35	VSS7	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A39	VSS8	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A43	VSS9	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
A47	VSS10	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA1	VSS11	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA3	VSS15	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA16	VSS12	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA19	VSS13	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA21	VSS14	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA32	VSS16	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA35	VSS17	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA38	VSS18	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AA53	VSS19	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB4	VSS21	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB6	VSS28	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB10	VSS20	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB41	VSS22	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB45	VSS23	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB47	VSS24	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB48	VSS25	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB50	VSS26	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AB51	VSS27	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC16	VSS29	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC18	VSS30	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC19	VSS31	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC21	VSS32	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC25	VSS33	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC33	VSS34	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC35	VSS35	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC36	VSS36	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AC38	VSS37	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AD7	VSS44	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AD19	VSS38	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AD21	VSS39	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AD25	VSS40	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AD32	VSS41	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AD33	VSS42	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AD47	VSS43	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE1	VSS45	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE3	VSS49	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE4	VSS50	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE6	VSS60	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE8	VSS61	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE9	VSS62	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE11	VSS46	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE12	VSS47	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE14	VSS48	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE40	VSS51	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE42	VSS52	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE43	VSS53	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE45	VSS54	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE46	VSS55	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE48	VSS56	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE50	VSS57	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE51	VSS58	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AE53	VSS59	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AF10	VSS63	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AF12	VSS64	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AF25	VSS65	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AF32	VSS66	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AF47	VSS67	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AG16	VSS68	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AG25	VSS69	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AG36	VSS70	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AG38	VSS71	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH4	VSS72	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH6	VSS110	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH7	VSS75	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH9	VSS76	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH41	VSS73	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH45	VSS74	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH47	VSS106	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH48	VSS107	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH50	VSS108	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AH51	VSS109	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ1	VSS77	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ3	VSS83	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ16	VSS78	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ21	VSS79	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ25	VSS80	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ27	VSS81	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ29	VSS82	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ30	VSS84	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ32	VSS85	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ33	VSS86	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ35	VSS87	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ38	VSS88	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AJ53	VSS89	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AK10	VSS90	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AK14	VSS91	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AK16	VSS92	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AK33	VSS93	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AK41	VSS94	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AK44	VSS95	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM7	VSS113	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM12	VSS96	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM19	VSS97	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM24	VSS98	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM25	VSS99	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM29	VSS100	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM33	VSS101	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM35	VSS102	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM36	VSS103	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM40	VSS104	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM44	VSS111	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AM51	VSS112	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN1	VSS114	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN3	VSS119	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN5	VSS131	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN6	VSS134	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN8	VSS135	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN9	VSS136	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN11	VSS115	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN12	VSS116	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN14	VSS117	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN22	VSS118	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN33	VSS120	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN35	VSS121	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN36	VSS122	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN38	VSS123	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN40	VSS124	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN42	VSS125	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN43	VSS126	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN45	VSS127	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN46	VSS128	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN48	VSS129	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN49	VSS130	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN51	VSS132	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AN53	VSS133	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AP40	VSS137	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT2			✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT4	VSS146	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT12	VSS138	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT16	VSS139	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT19	VSS140	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT24	VSS141	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT27	VSS142	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT30	VSS143	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT35	VSS144	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT38	VSS145	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT47	VSS147	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AT52	VSS148	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AU1	VSS149	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AU3	VSS151	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AU24	VSS150	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AU30	VSS152	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AU38	VSS153	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AU51	VSS154	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV7	VSS167	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV12	VSS155	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV13	VSS156	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV14	VSS157	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV18	VSS158	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV19	VSS159	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV24	VSS160	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV27	VSS161	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV30	VSS162	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV35	VSS163	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV38	VSS164	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV47	VSS165	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AV51	VSS166	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AW3	VSS171	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AW13	VSS168	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AW19	VSS169	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AW27	VSS170	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AW35	VSS172	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AY4	VSS177	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AY9	VSS179	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AY10	VSS173	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AY22	VSS174	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AY32	VSS175	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AY36	VSS176	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
AY50	VSS178	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA14	VSS180	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA19	VSS181	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA22	VSS182	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA27	VSS183	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA32	VSS184	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA35	VSS185	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA40	VSS186	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BA53	VSS187	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BB19	VSS188	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BB27	VSS189	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BB35	VSS190	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BC20	VSS191	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BC22	VSS192	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BC26	VSS193	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BC28	VSS194	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BC32	VSS195	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BC34	VSS196	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BC42	VSS197	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BD19	VSS198	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BD24	VSS199	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BD27	VSS200	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BD30	VSS201	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BD35	VSS202	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BE2	VSS204	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BE8	VSS206	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BE19	VSS203	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BE35	VSS205	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BF4	VSS213	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BF12	VSS207	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BF16	VSS208	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BF24	VSS209	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BF30	VSS211	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BF36	VSS212	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BF38	VSS210	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BG31	VSS214	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BG34	VSS215	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BG39	VSS216	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BG42	VSS217	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BG45	VSS218	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BG49	VSS219	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ7	VSS230	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ11	VSS220	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ15	VSS221	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ19	VSS222	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ23	VSS223	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ27	VSS224	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ31	VSS225	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ35	VSS226	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ39	VSS227	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ43	VSS228	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
BJ47	VSS229	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
C14	VSS231	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
C31	VSS232	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
C34	VSS233	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
C39	VSS234	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
C42	VSS235	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
C45	VSS236	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
C49	VSS237	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
D12	VSS238	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
D16	VSS239	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
D24	VSS240	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
D30	VSS241	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
D36	VSS242	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
D38	VSS243	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
E8	VSS246	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
E19	VSS244	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
E35	VSS245	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F2	VSS248	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F5	VSS253	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F7	VSS254	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F19	VSS247	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F24	VSS249	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F27	VSS250	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F30	VSS251	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
F35	VSS252	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G10	VSS255	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G20	VSS256	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G22	VSS257	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G26	VSS258	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G28	VSS259	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G32	VSS260	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G34	VSS261	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
G42	VSS262	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
H19	VSS263	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
H27	VSS264	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
H35	VSS265	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J1	VSS266	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J16	VSS267	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J19	VSS268	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J22	VSS269	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J27	VSS270	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J32	VSS271	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J35	VSS272	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J40	VSS273	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
J53	VSS274	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
K4	VSS279	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
K9	VSS281	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
K14	VSS275	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
K22	VSS276	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
K32	VSS277	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
K36	VSS278	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
K50	VSS280	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
L13	VSS282	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
L19	VSS283	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
L27	VSS284	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
L35	VSS285	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M19	VSS286	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M26	VSS287	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M27	VSS288	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M28	VSS105	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M34	VSS289	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M35	VSS290	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M38	VSS291	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M47	VSS292	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
M51	VSS293	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
N1	VSS294	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
N16	VSS295	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
N38	VSS296	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
N51	VSS297	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P4	VSS306	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P9	VSS309	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P13	VSS298	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P16	VSS299	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P19	VSS300	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P20	VSS301	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P24	VSS302	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P32	VSS303	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P35	VSS304	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P38	VSS305	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P47	VSS307	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
P52	VSS308	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
T40	VSS310	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U1	VSS311	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U3	VSS316	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U5	VSS326	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U6	VSS329	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U8	VSS330	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U9	VSS331	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U11	VSS312	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U12	VSS313	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U14	VSS314	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U21	VSS315	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U30	VSS317	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U32	VSS318	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U40	VSS319	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U42	VSS320	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U43	VSS321	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U45	VSS322	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U46	VSS323	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U48	VSS324	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U49	VSS325	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U51	VSS327	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
U53	VSS328	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V7	VSS340	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V12	VSS332	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V16	VSS333	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V19	VSS334	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V21	VSS335	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V35	VSS336	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V40	VSS337	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V44	VSS338	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
V51	VSS339	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y7	VSS349	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y9	VSS350	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y10	VSS341	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y14	VSS342	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y16	VSS343	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y21	VSS344	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y25	VSS345	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y33	VSS346	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y41	VSS347	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.
Y44	VSS348	GND	✅	All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution.

MEM3 - MICRON MT41K256M16HA ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
C1	VDDQ2	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
R1	VDD7	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
B2	VDD8	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
D2	VDDQ9	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
H2	VDDQ4	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
K2	VDD9	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
G7	VDD1	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
A8	VDDQ5	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
K8	VDD2	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
C9	VDDQ6	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
N1	VDD6	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
F1	VDDQ3	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
N9	VDD3	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
D9	VDD4	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
E9	VDDQ7	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
H9	VDDQ8	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
R9	VDD5	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
B1	VSSQ1	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
D1	VSSQ2	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
E1	VSS1	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
G1	VSSQ3	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
M1	VSS2	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
P1	VSS3	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
T1	VSS4	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
E2	VSSQ4	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
J2	VSS5	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
B3	VSS6	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
D8	VSSQ5	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
E8	VSSQ6	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
G8	VSS7	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
J8	VSS8	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
A9	VSS9	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
B9	VSSQ7	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
F9	VSSQ8	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
G9	VSSQ9	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
M9	VSS10	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
P9	VSS11	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
T9	VSS12	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
C7	DQSU	M_DQS_A_P3	✅	Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P3 and M_DQS_A_N3. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte of MEM3.
B7	/DQSU	M_DQS_A_N3	✅	Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P3 and M_DQS_A_N3. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte of MEM3.
D3	DMU	M_DM_A3	✅	Upper byte data mask (DMU) correctly connected to M_DM_A3. This input signal masks write data for the upper byte of MEM3 when asserted.
D7	DQU0	M_DATA_A29	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
C3	DQU1	M_DATA_A26	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
C8	DQU2	M_DATA_A28	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
C2	DQU3	M_DATA_A27	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
A7	DQU4	M_DATA_A25	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
A2	DQU5	M_DATA_A30	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
B8	DQU6	M_DATA_A24	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
A3	DQU7	M_DATA_A31	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31.
E3	DQL0	M_DATA_A16	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
F7	DQL1	M_DATA_A17	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
F2	DQL2	M_DATA_A18	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
F8	DQL3	M_DATA_A19	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
H3	DQL4	M_DATA_A20	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
H8	DQL5	M_DATA_A21	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
G2	DQL6	M_DATA_A22	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
H7	DQL7	M_DATA_A23	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31).
E7	DML	M_DM_A2	✅	Lower byte data mask (DML) correctly connected to M_DM_A2. This input signal masks write data for the lower byte of MEM3 when asserted.
F3	DQSL	M_DQS_A_P2	✅	Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P2 and M_DQS_A_N2. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte of MEM3.
G3	/DQSL	M_DQS_A_N2	✅	Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P2 and M_DQS_A_N2. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte of MEM3.
H1	VREFDQ	SM_VREF_DQ1_A	✅	Data reference voltage pin VREFDQ correctly connected to SM_VREF_DQ1_A, shared with MEM2. This ensures consistent data signal referencing across both devices.
J1	NC1__ODT1_		✅	No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration.
L1	NC2__/CS1_		✅	No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration.
J9	NC3__CKE1_		✅	No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration.
L9	NC4__ZQ1_		✅	No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration.
M7	NC5		✅	No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration.
J3	/RAS	M_RAS_A_L	✅	Command pins RAS#, CAS#, and WE# correctly connected to shared command bus, same as MEM2. This ensures both devices execute the same commands simultaneously for parallel operation.
K3	/CAS	M_CAS_A_L	✅	Command pins RAS#, CAS#, and WE# correctly connected to shared command bus, same as MEM2. This ensures both devices execute the same commands simultaneously for parallel operation.
L3	/WE	M_WE_A_L	✅	Command pins RAS#, CAS#, and WE# correctly connected to shared command bus, same as MEM2. This ensures both devices execute the same commands simultaneously for parallel operation.
J7	CK	M_CLK_A_P0	✅	Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2. This ensures both devices are synchronized to the same clock.
K7	/CK	M_CLK_A_N0	✅	Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2. This ensures both devices are synchronized to the same clock.
K1	ODT	M_ODT_A0	✅	On-die termination pin ODT correctly connected to M_ODT_A0, shared with MEM2. This ensures coordinated termination control for both devices.
K9	CKE	M_CKE_A0	✅	Clock enable pin CKE correctly connected to M_CKE_A0, shared with MEM2. This ensures synchronized power management for both devices.
L2	/CS	M_CS_A_L0	✅	Chip select pin CS# correctly connected to M_CS_A_L0, same as MEM2. This confirms both devices operate as a single rank with synchronized selection.
L8	ZQ	M_ZQ2	✅	ZQ calibration pin correctly connected to M_ZQ2, which has a 240Ω resistor (R327) to GND. This provides the external reference for output driver and ODT calibration, independent from MEM2.
M2	BA0	M_BS_A0	✅	Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2, same as MEM2. This ensures both devices select the same bank simultaneously.
N8	BA1	M_BS_A1	✅	Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2, same as MEM2. This ensures both devices select the same bank simultaneously.
M3	BA2	M_BS_A2	✅	Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2, same as MEM2. This ensures both devices select the same bank simultaneously.
M8	VREFCA	SM_VREF_CA1_A	✅	Control/address reference voltage pin VREFCA correctly connected to SM_VREF_CA1_A, shared with MEM2. This ensures consistent control/address signal referencing across both devices.
N3	A0	M_MA_A0	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
P7	A1	M_MA_A1	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
P3	A2	M_MA_A2	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
N2	A3	M_MA_A3	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
P8	A4	M_MA_A4	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
P2	A5	M_MA_A5	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
R8	A6	M_MA_A6	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
R2	A7	M_MA_A7	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
T8	A8	M_MA_A8	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
R3	A9	M_MA_A9	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
L7	A10_AP_	M_MA_A10	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
R7	A11	M_MA_A11	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
N7	A12_/BC_	M_MA_A12	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
T3	A13	M_MA_A13	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
T7	A14	M_MA_A14	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation.
T2	/RESET	M_A_RST_L	✅	Reset pin RESET# correctly connected to M_A_RST_L, shared with MEM2. This ensures synchronized reset and initialization for both devices.

MEM2 - MICRON MT41K256M16HA ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
C1	VDDQ2	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
R1	VDD7	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
B2	VDD8	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
D2	VDDQ9	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
H2	VDDQ4	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
K2	VDD9	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
G7	VDD1	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
A8	VDDQ5	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
K8	VDD2	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
C9	VDDQ6	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
N1	VDD6	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
F1	VDDQ3	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
N9	VDD3	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
D9	VDD4	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
E9	VDDQ7	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
H9	VDDQ8	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
R9	VDD5	+VDIMM	✅	Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains.
B1	VSSQ1	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
D1	VSSQ2	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
E1	VSS1	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
G1	VSSQ3	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
M1	VSS2	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
P1	VSS3	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
T1	VSS4	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
E2	VSSQ4	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
J2	VSS5	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
B3	VSS6	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
D8	VSSQ5	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
E8	VSSQ6	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
G8	VSS7	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
J8	VSS8	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
A9	VSS9	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
B9	VSSQ7	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
F9	VSSQ8	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
G9	VSSQ9	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
M9	VSS10	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
P9	VSS11	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
T9	VSS12	GND	✅	Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity.
C7	DQSU	M_DQS_A_P1	✅	Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P1 and M_DQS_A_N1. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte.
B7	/DQSU	M_DQS_A_N1	✅	Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P1 and M_DQS_A_N1. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte.
D3	DMU	M_DM_A1	✅	Upper byte data mask (DMU) correctly connected to M_DM_A1. This input signal masks write data for the upper byte when asserted.
D7	DQU0	M_DATA_A9	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
C3	DQU1	M_DATA_A10	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
C8	DQU2	M_DATA_A8	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
C2	DQU3	M_DATA_A11	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
A7	DQU4	M_DATA_A13	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
A2	DQU5	M_DATA_A15	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
B8	DQU6	M_DATA_A12	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
A3	DQU7	M_DATA_A14	✅	Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14.
E3	DQL0	M_DATA_A0	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
F7	DQL1	M_DATA_A1	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
F2	DQL2	M_DATA_A2	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
F8	DQL3	M_DATA_A3	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
H3	DQL4	M_DATA_A4	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
H8	DQL5	M_DATA_A5	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
G2	DQL6	M_DATA_A6	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
H7	DQL7	M_DATA_A7	✅	Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device.
E7	DML	M_DM_A0	✅	Lower byte data mask (DML) correctly connected to M_DM_A0. This input signal masks write data for the lower byte when asserted.
F3	DQSL	M_DQS_A_P0	✅	Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P0 and M_DQS_A_N0. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte.
G3	/DQSL	M_DQS_A_N0	✅	Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P0 and M_DQS_A_N0. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte.
H1	VREFDQ	SM_VREF_DQ1_A	✅	Data reference voltage pin VREFDQ correctly connected to SM_VREF_DQ1_A, which is generated by a resistor divider (R310 and R325, both 4.7kΩ) to provide VDIMM × 0.5. This reference is shared between MEM2 and MEM3.
J1	NC1__ODT1_		✅	No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration.
L1	NC2__/CS1_		✅	No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration.
J9	NC3__CKE1_		✅	No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration.
L9	NC4__ZQ1_		✅	No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration.
M7	NC5		✅	No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration.
J3	/RAS	M_RAS_A_L	✅	Command pins RAS#, CAS#, and WE# correctly connected to shared command bus M_RAS_A_L, M_CAS_A_L, and M_WE_A_L. These define memory operations and are shared between MEM2 and MEM3.
K3	/CAS	M_CAS_A_L	✅	Command pins RAS#, CAS#, and WE# correctly connected to shared command bus M_RAS_A_L, M_CAS_A_L, and M_WE_A_L. These define memory operations and are shared between MEM2 and MEM3.
L3	/WE	M_WE_A_L	✅	Command pins RAS#, CAS#, and WE# correctly connected to shared command bus M_RAS_A_L, M_CAS_A_L, and M_WE_A_L. These define memory operations and are shared between MEM2 and MEM3.
J7	CK	M_CLK_A_P0	✅	Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0. All control and address inputs are sampled on the CK/CK# crossing. Clock is shared between MEM2 and MEM3.
K7	/CK	M_CLK_A_N0	✅	Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0. All control and address inputs are sampled on the CK/CK# crossing. Clock is shared between MEM2 and MEM3.
K1	ODT	M_ODT_A0	✅	On-die termination pin ODT correctly connected to M_ODT_A0. This enables termination resistance for DQ, DQS, and DM signals, and is shared between MEM2 and MEM3.
K9	CKE	M_CKE_A0	✅	Clock enable pin CKE correctly connected to M_CKE_A0. This signal enables/disables internal circuitry and clocks, and is shared between MEM2 and MEM3 for synchronized power management.
L2	/CS	M_CS_A_L0	✅	Chip select pin CS# correctly connected to M_CS_A_L0. Both MEM2 and MEM3 share the same chip select, indicating they operate as a single rank with parallel data buses forming a 32-bit interface.
L8	ZQ	M_ZQ1	✅	ZQ calibration pin correctly connected to M_ZQ1, which has a 240Ω resistor (R140) to GND. This provides the external reference for output driver and ODT calibration as required by the datasheet.
M2	BA0	M_BS_A0	✅	Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2. These select one of eight internal banks and are shared between MEM2 and MEM3.
N8	BA1	M_BS_A1	✅	Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2. These select one of eight internal banks and are shared between MEM2 and MEM3.
M3	BA2	M_BS_A2	✅	Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2. These select one of eight internal banks and are shared between MEM2 and MEM3.
M8	VREFCA	SM_VREF_CA1_A	✅	Control/address reference voltage pin VREFCA correctly connected to SM_VREF_CA1_A, which is generated by a resistor divider (R144 and R326, both 4.7kΩ) to provide VDIMM × 0.5. This reference is shared between MEM2 and MEM3.
N3	A0	M_MA_A0	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
P7	A1	M_MA_A1	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
P3	A2	M_MA_A2	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
N2	A3	M_MA_A3	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
P8	A4	M_MA_A4	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
P2	A5	M_MA_A5	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
R8	A6	M_MA_A6	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
R2	A7	M_MA_A7	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
T8	A8	M_MA_A8	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
R3	A9	M_MA_A9	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
L7	A10_AP_	M_MA_A10	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
R7	A11	M_MA_A11	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
N7	A12_/BC_	M_MA_A12	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
T3	A13	M_MA_A13	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
T7	A14	M_MA_A14	✅	Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel.
T2	/RESET	M_A_RST_L	✅	Reset pin RESET# correctly connected to M_A_RST_L through 0Ω resistor R353. This asynchronous active-low reset is shared between MEM2 and MEM3, with optional DNI filtering capacitor C374.

R144 - 4.7K ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Upper resistor of VREFCA voltage divider, connected to +VDIMM power supply. This forms the high side of a 1:1 divider to create the DDR3 command/address reference voltage.
2	2	SM_VREF_CA1_A	✅	Output of voltage divider connected to SM_VREF_CA1_A reference voltage net. Provides VREFCA to both DDR3 memory devices.

C344 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_CA1_A	✅	Additional decoupling capacitor for VREFCA reference voltage. Provides filtering in parallel with C133 on the SM_VREF_CA1_A net.
2	2	GND	✅	Ground connection for VREFCA decoupling capacitor. Completes the filter path to ground.

R326 - 4.7K ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower resistor of VREFCA voltage divider, connected to GND. Forms the low side of a 1:1 divider with R144 to create the DDR3 command/address reference voltage.
2	2	SM_VREF_CA1_A	✅	Output of voltage divider connected to SM_VREF_CA1_A reference voltage net. Provides VREFCA to both DDR3 memory devices.

C133 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_CA1_A	✅	Decoupling capacitor for VREFCA reference voltage. Filters noise on the SM_VREF_CA1_A net that supplies the command/address reference to DDR3 memory.
2	2	GND	✅	Ground connection for VREFCA decoupling capacitor. Completes the filter path to ground.

R310 - 4.7K ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Upper leg of VREFDQ voltage divider, connected to +VDIMM supply.
2	2	SM_VREF_DQ1_A	✅	Midpoint of voltage divider, connected to SM_VREF_DQ1_A which supplies VREFDQ to memory chips MEM2 and MEM3.

C329 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_DQ1_A	✅	Bypass capacitor connected to SM_VREF_DQ1_A, providing additional filtering in parallel with C124.
2	2	GND	✅	Ground connection for bypass capacitor return path.

R325 - 4.7K ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower leg of VREFDQ voltage divider, connected to GND.
2	2	SM_VREF_DQ1_A	✅	Midpoint of voltage divider, connected to SM_VREF_DQ1_A which supplies VREFDQ to memory chips.

C124 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_DQ1_A	✅	Bypass capacitor connected to SM_VREF_DQ1_A for filtering the VREFDQ reference voltage.
2	2	GND	✅	Ground connection for bypass capacitor return path.

R140 - 110-0001971 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ1	✅	Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM2 via net M_ZQ1. This provides the reference impedance for the memory's output driver calibration.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit.

R327 - 110-0001971 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ2	✅	Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM3 via net M_ZQ2. This provides the reference impedance for the memory's output driver calibration.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit.

U33 - M24C02-WMN6TP-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	E0	DDR_E0	✅	E0 address pin connected to DDR_E0 net. Pull-down resistor R118 is DNI, leaving this pin without a defined logic level if U33 were populated. However, U33 itself is DNI, making this configuration acceptable.
2	E1	DDR_E1	✅	E1 address pin connected to DDR_E1 net. Pull-down resistor R123 is DNI, leaving this pin without a defined logic level if U33 were populated. However, U33 itself is DNI, making this configuration acceptable.
3	E2	GND	✅	E2 address pin correctly connected to GND, setting address bit 2 to logic 0.
4	GND	GND	✅	Ground pin correctly connected to GND net.
5	SDA	DDR_SMB_DATA	✅	SDA pin correctly connected to DDR_SMB_DATA for I2C data communication.
6	SCL	DDR_SMB_CLK	✅	SCL pin correctly connected to DDR_SMB_CLK for I2C clock communication.
7	~WC	DDR_WP_A	✅	Write Control pin connected to DDR_WP_A with configuration options via DNI resistors R121 (pull-up to +VCC3) and R122 (pull-down to GND). Both resistors are DNI, leaving this pin floating if U33 were populated. However, U33 itself is DNI, making this configuration acceptable.
8	VCC	+VCC3	✅	VCC pin correctly connected to +VCC3 with proper decoupling via C287.

C287 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Decoupling capacitor negative terminal correctly connected to GND.
2	2	+VCC3	✅	Decoupling capacitor positive terminal correctly connected to +VCC3 power rail.

R353 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_A_DRAMRST_L	✅	Connected to M_A_DRAMRST_L net, which is the source reset signal likely from a memory controller. This pin serves as the input to the 0-ohm jumper resistor.
2	2	M_A_RST_L	✅	Connected to M_A_RST_L net, which drives the /RESET pins of memory devices MEM2 and MEM3. This pin serves as the output of the 0-ohm jumper resistor.

C374 - 10pF 5% 50V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This pin would provide the ground return path for reset signal filtering if the component were installed.
2	2	M_A_RST_L	✅	Connected to M_A_RST_L, the memory reset signal. This pin would provide high-frequency filtering on the reset line if the component were installed.

C331 - 3.3pF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_CLK_A_N0	✅	Connected to M_CLK_A_N0, the negative differential clock signal to DDR3 memories MEM2 and MEM3. This capacitor is marked DNI and serves as an optional tuning component.
2	2	M_CLK_A_P0	✅	Connected to M_CLK_A_P0, the positive differential clock signal to DDR3 memories MEM2 and MEM3. This capacitor is marked DNI and serves as an optional tuning component.

FL1 - 3750-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CH1-IN	SD3_CD#	✅	CH1-IN filters the SD3_CD# (card detect) signal from the processor side. The signal is pulled up to +V1P8S through R182.
2	CH2-IN	SD3_D2	✅	CH2-IN filters the SD3_D2 (data line 2) signal. The signal is pulled up to +VCC3 through R174.
3	CH3-IN	SD3_D3	✅	CH3-IN filters the SD3_D3 (data line 3) signal. The signal is pulled up to +VCC3 through R180.
4	CH4-IN	SD3_CMD	✅	CH4-IN filters the SD3_CMD (command line) signal. The signal is pulled up to +VCC3 through R173.
5	CH5-IN	SD3_CLK	✅	CH5-IN filters the SD3_CLK (clock line) signal. The signal is pulled up to +VCC3 through R157.
6	CH6-IN	SD3_D0	✅	CH6-IN filters the SD3_D0 (data line 0) signal. The signal is pulled up to +VCC3 through R156.
7	CH7-IN	SD3_D1	✅	CH7-IN filters the SD3_D1 (data line 1) signal. The signal is pulled up to +VCC3 through R155.
8	CH8-IN		✅	CH8-IN is not connected. This channel is unused.
9	CH8-OUT		✅	CH8-OUT is not connected. This channel is unused.
10	CH7-OUT	SD3_D1_R	✅	CH7-OUT provides the filtered SD3_D1_R signal to the SD card connector.
11	CH6-OUT	SD3_D0_R	✅	CH6-OUT provides the filtered SD3_D0_R signal to the SD card connector.
12	CH5-OUT	SD3_CLK_R	✅	CH5-OUT provides the filtered SD3_CLK_R signal to the SD card connector.
13	CH4-OUT	SD3_CMD_R	✅	CH4-OUT provides the filtered SD3_CMD_R signal to the SD card connector.
14	CH3-OUT	SD3_D3_R	✅	CH3-OUT provides the filtered SD3_D3_R signal to the SD card connector.
15	CH2-OUT	SD3_D2_R	✅	CH2-OUT provides the filtered SD3_D2_R signal to the SD card connector.
16	CH1-OUT	SD3_CD_R	✅	CH1-OUT provides the filtered SD3_CD_R signal to the SD card connector.
17	GND_PAD	GND	✅	GND_PAD is connected to ground, providing the reference for the filter.

P2 - 158-0001269 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	SD3_D2_R	✅	DAT2 is connected to the filtered SD3_D2_R signal from FL1.
2	CD/DAT3	SD3_D3_R	✅	CD/DAT3 is connected to the filtered SD3_D3_R signal from FL1.
3	CMD	SD3_CMD_R	✅	CMD is connected to the filtered SD3_CMD_R signal from FL1.
4	VDD	+VCC3	✅	VDD is connected to +VCC3 with decoupling capacitors C162 and C159.
5	CLOCK	SD3_CLK_R	✅	CLOCK is connected to the filtered SD3_CLK_R signal from FL1.
6	VSS	GND	✅	VSS is connected to ground.
7	DAT0	SD3_D0_R	✅	DAT0 is connected to the filtered SD3_D0_R signal from FL1.
8	DAT1	SD3_D1_R	✅	DAT1 is connected to the filtered SD3_D1_R signal from FL1.
9	GND	GND	✅	GND is connected to ground.
10	CD	SD3_CD_R	✅	CD is connected to the filtered SD3_CD_R signal from FL1.
11	GND3	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD.
12	GND4	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD.
15	GND7	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD.
16	GND8	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD.
13	GND5	FGND-uSD-Front	✅	GND5 and GND6 are frame ground pins connected to FGND-uSD-Front.
14	GND6	FGND-uSD-Front	✅	GND5 and GND6 are frame ground pins connected to FGND-uSD-Front.

C17 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND.
2	2	+V1P8S	✅	Connected to +V1P8S supply rail (VCCA of U2).

R29 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CEC	✅	Connected to HDMI_CEC net (CEC_A of U2).
2	2	+V1P8S	✅	Connected to +V1P8S supply rail.

R171 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S supply rail.
2	2	HPD_ENB	✅	Connected to HPD_ENB net which controls CT_HPD pin of U2.

R30 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCDAT	✅	Connected to HDMI_DDCDAT net (SDA_A of U2).
2	2	+V1P8S	✅	Connected to +V1P8S supply rail.

U2 - TPD12S016PW ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CEC_A	HDMI_CEC	✅	CEC_A pin connects to HDMI_CEC net with external 10K pullup R29 to +V1P8S. This is the HDMI controller side CEC signal.
2	SCL_A	HDMI_DDCCLK	✅	SCL_A pin connects to HDMI_DDCCLK net with external 10K pullup R28 to +V1P8S. This is the HDMI controller side DDC clock signal.
3	SDA_A	HDMI_DDCDAT	✅	SDA_A pin connects to HDMI_DDCDAT net with external 10K pullup R30 to +V1P8S. This is the HDMI controller side DDC data signal.
4	HPD_A	HDMI_HPD	✅	HPD_A pin connects to HDMI_HPD net. This is the hot plug detect output to the HDMI controller.
5	LS_OE	LS_OE	✅	LS_OE pin connects to LS_OE net with 2.2K pullup R172 to +V1P8S. This enables the level shifters by default.
6	GND1	GND	✅	Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net.
14	GND2	GND	✅	Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net.
19	GND3	GND	✅	Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net.
7	CEC_B	C_HDMI_CEC	✅	CEC_B pin connects to C_HDMI_CEC net which goes to the HDMI connector CEC pin. This is the HDMI connector side CEC signal.
8	SCL_B	C_HDMI_SCL	✅	SCL_B pin connects to C_HDMI_SCL net which goes to the HDMI connector SCL pin. This is the HDMI connector side DDC clock signal.
9	SDA_B	C_HDMI_SDA	✅	SDA_B pin connects to C_HDMI_SDA net which goes to the HDMI connector SDA pin. This is the HDMI connector side DDC data signal.
10	HPD_B	C_HDMI_HPD	✅	HPD_B pin connects to C_HDMI_HPD net which goes to the HDMI connector hot plug detect pin. This is the hot plug detect input from the HDMI connector.
11	VCC5V	+5VSB	✅	VCC5V pin connects to +5VSB net with 0.1uF decoupling capacitor C155. This is the 5V supply input to the load switch.
12	CT_HPD	HPD_ENB	✅	CT_HPD pin connects to HPD_ENB net with 2.2K pullup R171 to +V1P8S. This enables the load switch and HPD by default.
13	5V_OUT	+HDMI_CRT_VCC	✅	5V_OUT pin connects to +HDMI_CRT_VCC net which supplies power to the HDMI connector through ferrite bead L7. This is the current-limited 5V output.
15	CLK-	HDMI_OUT_CLK_DN	✅	CLK- and CLK+ pins connect to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets which go through common mode choke L14 to the HDMI connector. These are the HDMI TMDS clock differential pair.
16	CLK+	HDMI_OUT_CLK_DP	✅	CLK- and CLK+ pins connect to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets which go through common mode choke L14 to the HDMI connector. These are the HDMI TMDS clock differential pair.
17	D0-	HDMI_OUT_TX0_DN	✅	D0- and D0+ pins connect to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets which go through common mode choke L15 to the HDMI connector. These are HDMI TMDS data channel 0 differential pair.
18	D0+	HDMI_OUT_TX0_DP	✅	D0- and D0+ pins connect to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets which go through common mode choke L15 to the HDMI connector. These are HDMI TMDS data channel 0 differential pair.
20	D1-	HDMI_OUT_TX1_DN	✅	D1- and D1+ pins connect to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets which go through common mode choke L16 to the HDMI connector. These are HDMI TMDS data channel 1 differential pair.
21	D1+	HDMI_OUT_TX1_DP	✅	D1- and D1+ pins connect to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets which go through common mode choke L16 to the HDMI connector. These are HDMI TMDS data channel 1 differential pair.
22	D2-	HDMI_OUT_TX2_DN	✅	D2- and D2+ pins connect to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets which go through common mode choke L17 to the HDMI connector. These are HDMI TMDS data channel 2 differential pair.
23	D2+	HDMI_OUT_TX2_DP	✅	D2- and D2+ pins connect to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets which go through common mode choke L17 to the HDMI connector. These are HDMI TMDS data channel 2 differential pair.
24	VCCA	+V1P8S	✅	VCCA pin connects to +V1P8S net with 0.1uF decoupling capacitor C17. This is the 1.8V supply for the TPD12S016.

R172 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S supply rail.
2	2	LS_OE	✅	Connected to LS_OE net which controls LS_OE pin of U2.

C155 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND.
2	2	+5VSB	✅	Connected to +5VSB supply rail (VCC5V of U2).

R28 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCCLK	✅	Connected to HDMI_DDCCLK net (SCL_A of U2).
2	2	+V1P8S	✅	Connected to +V1P8S supply rail.

L15 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX0_C_DN	✅	IN1 pin correctly connected to HDMI_TX0_C_DN, the negative data channel 0 signal after AC coupling.
3	IN2	HDMI_TX0_C_DP	✅	IN2 pin correctly connected to HDMI_TX0_C_DP, the positive data channel 0 signal after AC coupling.
4	OUT2	HDMI_OUT_TX0_DP	✅	OUT2 pin correctly connected to HDMI_OUT_TX0_DP, routing the positive data channel 0 signal to the ESD protection IC and connector.
6	OUT1	HDMI_OUT_TX0_DN	✅	OUT1 pin correctly connected to HDMI_OUT_TX0_DN, routing the negative data channel 0 signal to the ESD protection IC and connector.

L14 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_CLK_C_DN	✅	IN1 pin correctly connected to HDMI_CLK_C_DN, the negative clock signal after AC coupling.
3	IN2	HDMI_CLK_C_DP	✅	IN2 pin correctly connected to HDMI_CLK_C_DP, the positive clock signal after AC coupling.
4	OUT2	HDMI_OUT_CLK_DP	✅	OUT2 pin correctly connected to HDMI_OUT_CLK_DP, routing the positive clock signal to the ESD protection IC and connector.
6	OUT1	HDMI_OUT_CLK_DN	✅	OUT1 pin correctly connected to HDMI_OUT_CLK_DN, routing the negative clock signal to the ESD protection IC and connector.

L16 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX1_C_DN	✅	IN1 pin correctly connected to HDMI_TX1_C_DN, the negative data channel 1 signal after AC coupling.
3	IN2	HDMI_TX1_C_DP	✅	IN2 pin correctly connected to HDMI_TX1_C_DP, the positive data channel 1 signal after AC coupling.
4	OUT2	HDMI_OUT_TX1_DP	✅	OUT2 pin correctly connected to HDMI_OUT_TX1_DP, routing the positive data channel 1 signal to the ESD protection IC and connector.
6	OUT1	HDMI_OUT_TX1_DN	✅	OUT1 pin correctly connected to HDMI_OUT_TX1_DN, routing the negative data channel 1 signal to the ESD protection IC and connector.

L17 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX2_C_DN	✅	IN1 pin correctly connected to HDMI_TX2_C_DN, the negative data channel 2 signal after AC coupling.
3	IN2	HDMI_TX2_C_DP	✅	IN2 pin correctly connected to HDMI_TX2_C_DP, the positive data channel 2 signal after AC coupling.
4	OUT2	HDMI_OUT_TX2_DP	✅	OUT2 pin correctly connected to HDMI_OUT_TX2_DP, routing the positive data channel 2 signal to the ESD protection IC and connector.
6	OUT1	HDMI_OUT_TX2_DN	✅	OUT1 pin correctly connected to HDMI_OUT_TX2_DN, routing the negative data channel 2 signal to the ESD protection IC and connector.

R801 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_C_DN	✅	Connected to HDMI_TX2_C_DN, providing termination for the negative line of HDMI TX2 differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

R802 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_C_DP	✅	Connected to HDMI_TX2_C_DP, providing termination for the positive line of HDMI TX2 differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

R803 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_C_DN	✅	Connected to HDMI_TX1_C_DN, providing termination for the negative line of HDMI TX1 differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

R804 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_C_DP	✅	Connected to HDMI_TX1_C_DP, providing termination for the positive line of HDMI TX1 differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

R805 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_C_DN	✅	Connected to HDMI_TX0_C_DN, providing termination for the negative line of HDMI TX0 differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

R806 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_C_DP	✅	Connected to HDMI_TX0_C_DP, providing termination for the positive line of HDMI TX0 differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

R807 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CLK_C_DP	✅	Connected to HDMI_CLK_C_DP, providing termination for the positive line of HDMI clock differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

R808 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CLK_C_DN	✅	Connected to HDMI_CLK_C_DN, providing termination for the negative line of HDMI clock differential pair after AC coupling.
2	2	HDMI_TERM	✅	Connected to HDMI_TERM net, which is switched to ground through Q101.

Q101 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	HDMI_TERM	✅	Drain connects to HDMI_TERM net, which is the common termination point for eight 619Ω resistors (R801-R808) connected to the HDMI differential signal pairs after AC coupling. This MOSFET switches the termination network to ground.
G	GATE	$15N747	✅	Gate connects to net $15N747, which connects through 0Ω resistor R809 to +VCC3 power rail. This keeps the MOSFET permanently ON, enabling the termination network at all times.
S	SOURCE	GND	✅	Source connects to GND, which is correct for an N-channel MOSFET used to switch the termination network to ground.

R809 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$15N747	✅	This 0Ω resistor permanently connects the MOSFET gate (net $15N747) to the +VCC3 power rail, keeping Q101 always ON to enable the HDMI termination network.
2	2	+VCC3	✅	This 0Ω resistor permanently connects the MOSFET gate (net $15N747) to the +VCC3 power rail, keeping Q101 always ON to enable the HDMI termination network.

L7 - 126-0001418 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+HDMI_CRT_VCC	✅	Input pin (P1) correctly connected to +HDMI_CRT_VCC from U2's charge pump output, with C157 providing local decoupling.
2	P2	D5_0V_HDMI	✅	Output pin (P2) correctly connected to D5_0V_HDMI which supplies 5V power to the HDMI connector, providing EMI filtering.

P1 - 158-0004513 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	HPLG	C_HDMI_HPD	✅	Hot plug detect (HPLG) pin correctly connected to C_HDMI_HPD net, which routes to U2 pin 10 for level translation and ESD protection.
2	NC		✅	No connect (NC) pin has no net connection, which is correct for an unused pin.
3	DAT2+	HDMI_OUT_TX2_DP	✅	DAT2+ pin correctly connected to HDMI_OUT_TX2_DP differential signal through U2 and common mode choke L17.
4	DAT2_S	GND	✅	DAT2_S shield pin correctly connected to GND for proper shielding of data pair 2.
5	DAT2-	HDMI_OUT_TX2_DN	✅	DAT2- pin correctly connected to HDMI_OUT_TX2_DN differential signal through U2 and common mode choke L17.
6	DAT1+	HDMI_OUT_TX1_DP	✅	DAT1+ pin correctly connected to HDMI_OUT_TX1_DP differential signal through U2 and common mode choke L16.
7	DAT1_S	GND	✅	DAT1_S shield pin correctly connected to GND for proper shielding of data pair 1.
8	DAT1-	HDMI_OUT_TX1_DN	✅	DAT1- pin correctly connected to HDMI_OUT_TX1_DN differential signal through U2 and common mode choke L16.
9	DAT0+	HDMI_OUT_TX0_DP	✅	DAT0+ pin correctly connected to HDMI_OUT_TX0_DP differential signal through U2 and common mode choke L15.
10	DAT0_S	GND	✅	DAT0_S shield pin correctly connected to GND for proper shielding of data pair 0.
11	DAT0-	HDMI_OUT_TX0_DN	✅	DAT0- pin correctly connected to HDMI_OUT_TX0_DN differential signal through U2 and common mode choke L15.
12	CLK+	HDMI_OUT_CLK_DP	✅	CLK+ pin correctly connected to HDMI_OUT_CLK_DP differential clock signal through U2 and common mode choke L14.
13	CLK_S	GND	✅	CLK_S shield pin correctly connected to GND for proper shielding of clock pair.
14	CLK-	HDMI_OUT_CLK_DN	✅	CLK- pin correctly connected to HDMI_OUT_CLK_DN differential clock signal through U2 and common mode choke L14.
15	CEC	C_HDMI_CEC	✅	CEC pin correctly connected to C_HDMI_CEC net, which routes to U2 pin 7 for level translation and ESD protection.
16	DDC/CEC_GND	GND	✅	DDC/CEC_GND pin correctly connected to GND for proper ground reference of DDC and CEC signals.
17	SCL	C_HDMI_SCL	✅	SCL pin correctly connected to C_HDMI_SCL net, which routes to U2 pin 8 for level translation and ESD protection.
18	SDA	C_HDMI_SDA	✅	SDA pin correctly connected to C_HDMI_SDA net, which routes to U2 pin 9 for level translation and ESD protection.
19	+5V	D5_0V_HDMI	✅	+5V pin correctly connected to D5_0V_HDMI net through ferrite bead L7 for EMI filtering of the 5V supply to the connected device.
20	MTG1	GND_EARTH	✅	Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding.
21	MTG2	GND_EARTH	✅	Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding.
22	MTG3	GND_EARTH	✅	Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding.
23	MTG4	GND_EARTH	✅	Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding.

C157 - 123-0001144 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+HDMI_CRT_VCC	✅	Positive terminal correctly connected to +HDMI_CRT_VCC for decoupling the charge pump output.
2	2	GND	✅	Negative terminal correctly connected to GND for decoupling.

C161 - 2267-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	One terminal correctly connected to GND for high-voltage isolation between signal ground and chassis ground.
2	2	GND_EARTH	✅	Other terminal correctly connected to GND_EARTH for high-voltage isolation, providing AC coupling between signal ground and chassis ground for ESD protection.

L2 - BKP2125HS221-T ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP2	✅	Input from U32 channel 2 output (USBP2) for USB port B power distribution.
2	2	VBUS2	✅	Output to VBUS2 supplying power to USB port B connector with appropriate bypass and bulk capacitors.

L1 - BKP2125HS221-T ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP1	✅	Input from U32 channel 1 output (USBP1) for USB port A power distribution.
2	2	VBUS1	✅	Output to VBUS1 supplying power to USB port A connector with appropriate bypass and bulk capacitors.

FB13 - 3044-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input from +5VSB supply for USB power distribution.
2	2	+USBVCC	✅	Output to +USBVCC net supplying power to USB power switch U32 and level shifter U4.

U32 - AP2172MPG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	Ground pin correctly connected to GND net.
2	IN	+USBVCC	✅	Input power pin correctly connected to +USBVCC with appropriate bypass capacitors (C92, C93, C94).
3	EN1	USB_HOST_EN0	✅	Enable input for channel 1 correctly connected to level shifter output (U4 pin 1) for port 0 enable control.
4	EN2	USB_HOST_EN1	✅	Enable input for channel 2 correctly connected to level shifter output (U4 pin 8) for port 1 enable control.
5	OC2#	SOC_USB_HOST_OC1	✅	Overcurrent flag output for channel 2 connected to SOC_USB_HOST_OC1. Open-drain output requires pull-up resistor not visible on this page.
6	OUTB	USBP2	✅	Output for channel 2 correctly connected through ferrite bead L2 to VBUS2 with appropriate output capacitors.
7	OUTA	USBP1	✅	Output for channel 1 correctly connected through ferrite bead L1 to VBUS1 with appropriate output capacitors.
8	OC1#	SOC_USB_HOST_OC0	✅	Overcurrent flag output for channel 1 connected to SOC_USB_HOST_OC0. Open-drain output requires pull-up resistor not visible on this page.
9	GND_PAD	GND	✅	Exposed pad correctly connected to GND for thermal and electrical grounding.

U4 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	USB_HOST_EN0	✅	B2 pin correctly connected to USB_HOST_EN0 net, providing VCCB-level output to drive U32 EN1 pin for USB port 1 power control.
2	GND	GND	✅	GND pin correctly connected to ground net.
3	VCCA	+V1P8A	✅	VCCA pin correctly connected to +V1P8A supply, providing 1.8V reference for A-side I/O as confirmed by schematic notes.
4	A2	SOC_USB_HOST_EN0	✅	A2 pin correctly connected to SOC_USB_HOST_EN0, receiving 1.8V level enable signal from SOC for channel 2.
5	A1	SOC_USB_HOST_EN1	✅	A1 pin correctly connected to SOC_USB_HOST_EN1, receiving 1.8V level enable signal from SOC for channel 1.
6	OE	USB_HOST_BUFF_ENB	✅	OE pin correctly connected to USB_HOST_BUFF_ENB with 10K pull-up to VCCA, enabling the level translator by default.
7	VCCB	+USBVCC	✅	VCCB pin correctly connected to +USBVCC supply, providing reference voltage for B-side I/O to interface with USB power switch.
8	B1	USB_HOST_EN1	✅	B1 pin correctly connected to USB_HOST_EN1 net, providing VCCB-level output to drive U32 EN2 pin for USB port 2 power control.

R116 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB_HOST_BUFF_ENB	✅	10K pull-up resistor correctly configured to pull OE pin of U4 to VCCA (+V1P8A), enabling the level translator by default.
2	2	+V1P8A	✅	10K pull-up resistor correctly configured to pull OE pin of U4 to VCCA (+V1P8A), enabling the level translator by default.

U9 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H0	✅	D+ pin provides ESD protection for the USB 2.0 differential data positive line (USB_H0) going to USB connector port A.
2	D-	USB_L0	✅	D- pin provides ESD protection for the USB 2.0 differential data negative line (USB_L0) going to USB connector port A.
3	ID		✅	ID pin is left floating, which is acceptable for a USB host-only port that does not require OTG ID detection.
4	GND	GND	✅	GND pin is correctly connected to the ground net, providing the ground reference for the ESD protection device.
5	NC		✅	NC pin is correctly left unconnected as it is not internally connected within the device.
6	VBUS	VBUS1	✅	VBUS pin provides ESD protection for the VBUS1 power line going to USB connector port A.

U8 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H1	✅	D+ pin correctly connected to USB port B D+ signal (USB_H1) for ESD protection of the high-speed differential data line.
2	D-	USB_L1	✅	D- pin correctly connected to USB port B D- signal (USB_L1) for ESD protection of the high-speed differential data line.
3	ID		✅	ID pin is left floating, which is acceptable per the datasheet when the ID function is not used in the application.
4	GND	GND	✅	GND pin correctly connected to the ground net for proper ESD protection operation.
5	NC		✅	NC pin correctly left unconnected as it is not internally connected per the datasheet.
6	VBUS	VBUS2	✅	VBUS pin correctly connected to USB port B VBUS signal (VBUS2) for ESD protection of the high-voltage tolerant VBUS line.

U29 - TPD4USB30 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D1+	USB3_TX0P_C	✅	D1+ pin connected to USB3_TX0P_C, which is the USB 3.0 transmit positive differential signal going to the connector. This connection appears correct for ESD protection of the TX+ line.
2	D1-	USB3_TX0N_C	✅	D1- pin connected to USB3_TX0N_C, which is the USB 3.0 transmit negative differential signal going to the connector. This connection appears correct for ESD protection of the TX- line.
3	GND1	GND	✅	GND1 pin correctly connected to the GND net for ESD protection reference.
4	D2+	USB3_RX0P_C	✅	D2+ pin connected to USB3_RX0P_C, which is the USB 3.0 receive positive differential signal from the connector. This connection appears correct for ESD protection of the RX+ line.
5	D2-	USB3_RX0N_C	✅	D2- pin connected to USB3_RX0N_C, which is the USB 3.0 receive negative differential signal from the connector. This connection appears correct for ESD protection of the RX- line.
6	NC4	USB3_RX0N_C	✅	NC4 pin is connected to USB3_RX0N_C, the same net as pin 5 (D2-). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required.
7	NC3	USB3_RX0P_C	✅	NC3 pin is connected to USB3_RX0P_C, the same net as pin 4 (D2+). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required.
8	GND2	GND	✅	GND2 pin correctly connected to the GND net for ESD protection reference.
9	NC2	USB3_TX0N_C	✅	NC2 pin is connected to USB3_TX0N_C, the same net as pin 2 (D1-). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required.
10	NC1	USB3_TX0P_C	✅	NC1 pin is connected to USB3_TX0P_C, the same net as pin 1 (D1+). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required.

CHOKE2 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_TX0P-R	✅	IN1 carries the positive USB3 transmit signal (USB3_TX0P-R) from the SOC side through the common mode choke to the connector side (USB3_TX0P_C via OUT1).
3	IN2	USB3_TX0N-R	✅	IN2 carries the negative USB3 transmit signal (USB3_TX0N-R) from the SOC side through the common mode choke to the connector side (USB3_TX0N_C via OUT2).
4	OUT2	USB3_TX0N_C	✅	OUT2 outputs the negative USB3 transmit signal (USB3_TX0N_C) to the connector after common mode filtering.
6	OUT1	USB3_TX0P_C	✅	OUT1 outputs the positive USB3 transmit signal (USB3_TX0P_C) to the connector after common mode filtering.

CHOKE1 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_RX0N_C	✅	IN1 carries the negative USB3 receive signal (USB3_RX0N_C) from the connector side through the common mode choke to the SOC side (USB3_RXN0 via OUT1).
3	IN2	USB3_RX0P_C	✅	IN2 carries the positive USB3 receive signal (USB3_RX0P_C) from the connector side through the common mode choke to the SOC side (USB3_RXP0 via OUT2).
4	OUT2	USB3_RXP0	✅	OUT2 outputs the positive USB3 receive signal (USB3_RXP0) to the SOC after common mode filtering.
6	OUT1	USB3_RXN0	✅	OUT1 outputs the negative USB3 receive signal (USB3_RXN0) to the SOC after common mode filtering.

CHOKE4 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN0	✅	IN1 pin connected to USB_DN0, serving as the input for the USB D- signal on port 0. This pin is one end of the first winding of the common mode choke.
3	IN2	USB_DP0	✅	IN2 pin connected to USB_DP0, serving as the input for the USB D+ signal on port 0. This pin is one end of the second winding of the common mode choke.
4	OUT2	USB_H0	✅	OUT2 pin connected to USB_H0, serving as the output for the USB D+ signal. The signal then connects to ESD protection device U9 pin 1 (D+) and USB connector USB1 pin 3 (DA+).
6	OUT1	USB_L0	✅	OUT1 pin connected to USB_L0, serving as the output for the USB D- signal. The signal then connects to ESD protection device U9 pin 2 (D-) and USB connector USB1 pin 2 (DA-).

CHOKE3 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN1	✅	IN1 pin connected to USB_DN1, serving as the input for the USB D- signal on port 1. This pin is one end of the first winding of the common mode choke.
3	IN2	USB_DP1	✅	IN2 pin connected to USB_DP1, serving as the input for the USB D+ signal on port 1. This pin is one end of the second winding of the common mode choke.
4	OUT2	USB_H1	✅	OUT2 pin connected to USB_H1, serving as the output for the USB D+ signal. The signal then connects to ESD protection device U8 pin 1 (D+) and USB connector USB1 pin 12 (DB+).
6	OUT1	USB_L1	✅	OUT1 pin connected to USB_L1, serving as the output for the USB D- signal. The signal then connects to ESD protection device U8 pin 2 (D-) and USB connector USB1 pin 11 (DB-).

USB1 - DUAL_USB_2.0_3.0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUSA	VBUS1	✅	VBUSA provides 5V power to USB port A. Power is sourced from +USBVCC through power switch U32 channel A (OUTA), ferrite bead L1, with decoupling capacitors C82 and C91, and ESD protection U9.
2	DA-	USB_L0	✅	DA- is the USB 2.0 D- signal for port A. It connects through common mode choke CHOKE4 and ESD protection U9 to the SOC signal USB_DN0.
3	DA+	USB_H0	✅	DA+ is the USB 2.0 D+ signal for port A. It connects through common mode choke CHOKE4 and ESD protection U9 to the SOC signal USB_DP0.
4	GNDA	GND	✅	GNDA is the ground connection for USB port A, properly connected to the main GND plane.
5	SSRX-	USB3_RX0N_C	✅	SSRX- is the USB 3.0 SuperSpeed receive negative signal. It connects through ESD protection U29 and common mode choke CHOKE1 to the SOC signal USB3_RXN0.
6	SSRX+	USB3_RX0P_C	✅	SSRX+ is the USB 3.0 SuperSpeed receive positive signal. It connects through ESD protection U29 and common mode choke CHOKE1 to the SOC signal USB3_RXP0.
7	GND_DRAIN	GND	✅	GND_DRAIN is the shield drain ground connection, properly connected to the main GND plane.
8	SSTX-	USB3_TX0N_C	✅	SSTX- is the USB 3.0 SuperSpeed transmit negative signal. It connects through ESD protection U29, common mode choke CHOKE2, and AC coupling capacitor C191 to the SOC signal USB3_TXN0.
9	SSTX+	USB3_TX0P_C	✅	SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. It connects through ESD protection U29, common mode choke CHOKE2, and AC coupling capacitor C192 to the SOC signal USB3_TXP0.
10	VBUSB	VBUS2	✅	VBUSB provides 5V power to USB port B. Power is sourced from +USBVCC through power switch U32 channel B (OUTB), ferrite bead L2, with decoupling capacitors C70, C103, and C234, and ESD protection U8.
11	DB-	USB_L1	✅	DB- is the USB 2.0 D- signal for port B. It connects through common mode choke CHOKE3 and ESD protection U8 to the SOC signal USB_DN1.
12	DB+	USB_H1	✅	DB+ is the USB 2.0 D+ signal for port B. It connects through common mode choke CHOKE3 and ESD protection U8 to the SOC signal USB_DP1.
13	GNDB	GND	✅	GNDB is the ground connection for USB port B, properly connected to the main GND plane.
MH1	SHIELD1	GND_EARTH	✅	SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management.
MH2	SHIELD2	GND_EARTH	✅	SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management.
MH3	SHIELD3	GND_EARTH	✅	SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management.
MH4	SHIELD4	GND_EARTH	✅	SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management.

J10 - 158-0004534 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
57	57	XDP_H_TDO	❌	XDP test data out signal with 51 ohm resistor to +V1P8A. This connection is incorrect - the resistor value is far too low for a pull-up and the topology is wrong for series termination. Pin 57 is connected to net XDP_H_TDO (from schematic) Resistor R21 (51 ohm, part 110-0002078) connects XDP_H_TDO to +V1P8A power rail (from schematic) TDO (Test Data Out) is the standard JTAG/XDP output signal from the device under test (reasoning) TDO is typically an actively driven output signal and does not require a pull-up resistor (reasoning) A 51 ohm resistor to power would draw approximately 35mA when TDO is driven low (1.8V / 51Ω ≈ 35mA), which is excessively high current for a logic signal (reasoning) If this is intended as a pull-up resistor, 51 ohms is far too low - typical pull-up values are 1K-10K ohms (reasoning) If this is intended as series termination, the resistor should be placed in series with the signal path, not connected to the power rail (reasoning) Other XDP/JTAG signals on J10 (pins 52, 54, 56, 58 for TRSTB, TCK, TMS, TDI) do not have similar resistor connections, making this connection inconsistent with the rest of the interface (from schematic) The most likely correct configurations would be: (1) a higher value pull-up resistor (1K-10K) if a pull-up is needed, (2) a series resistor in the signal path if termination is needed, or (3) no resistor at all since TDO is typically actively driven (reasoning) This connection should be corrected to match standard JTAG/XDP interface practices (reasoning)
1	1	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
2	2	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
13	13	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
14	14	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
25	25	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
26	26	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
37	37	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
38	38	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
49	49	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
50	50	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
59	59	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
60	60	GND	✅	Ground pins distributed throughout the connector to provide return paths for high-speed signals and power.
3	3	mSATA_TX_P	✅	mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5).
5	5	mSATA_TX_N	✅	mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5).
4	4	mSATA_RX_P	✅	mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6).
6	6	mSATA_RX_N	✅	mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6).
7	7	+5VSB	✅	5V standby power pins distributed throughout the connector.
8	8	+5VSB	✅	5V standby power pins distributed throughout the connector.
19	19	+5VSB	✅	5V standby power pins distributed throughout the connector.
20	20	+5VSB	✅	5V standby power pins distributed throughout the connector.
31	31	+5VSB	✅	5V standby power pins distributed throughout the connector.
32	32	+5VSB	✅	5V standby power pins distributed throughout the connector.
43	43	+5VSB	✅	5V standby power pins distributed throughout the connector.
44	44	+5VSB	✅	5V standby power pins distributed throughout the connector.
9	9	mPCIE_REFCLK_P	✅	mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11).
11	11	mPCIE_REFCLK_N	✅	mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11).
10	10	USB_HOST_DP	✅	USB host differential pair (D+ on pin 10, D- on pin 12).
12	12	USB_HOST_DN	✅	USB host differential pair (D+ on pin 10, D- on pin 12).
15	15	mPCIE_TX_P	✅	mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17).
17	17	mPCIE_TX_N	✅	mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17).
16	16	mPCIE_RX_N	✅	mPCIE receive differential pair with polarity inversion (RX_P on pin 18, RX_N on pin 16).
18	18	mPCIE_RX_P	✅	mPCIE receive differential pair with polarity inversion (RX_P on pin 18, RX_N on pin 16).
21	21	I2C6_SCL	✅	I2C clock signal with 10K pull-up to +V1P8S.
22	22	mPCIE_WAKEB	✅	mPCIE wake signal (active low).
23	23	I2C6_SDA	✅	I2C data signal with 10K pull-up to +V1P8S.
24	24	mPCIe_CLKREQ3_B	✅	mPCIE clock request signal (active low).
27	27	EXP_GPIO1	✅	General purpose I/O expansion pins.
28	28	EXP_GPIO3	✅	General purpose I/O expansion pins.
29	29	EXP_GPIO2	✅	General purpose I/O expansion pins.
30	30	EXP_GPIO4	✅	General purpose I/O expansion pins.
33	33	XDP_H_OBSDATA_A1	✅	XDP observation data bus signals.
34	34	XDP_H_OBSDATA_A0	✅	XDP observation data bus signals.
35	35	XDP_H_OBSDATA_A2	✅	XDP observation data bus signals.
36	36	XDP_H_OBSDATA_A3	✅	XDP observation data bus signals.
39	39	XDP_H_PRDYB	✅	XDP PRDY signal (active low).
40	40	XDP_H_PREQB_PB	✅	XDP PREQ signal (active low) buffered through U1 with 200 ohm pull-up.
41	41	HOOK0	✅	HOOK0 test signal connected to PMC_RSMRST through 1K resistor.
42	42	HOOK1	✅	HOOK1 test signal connected to front panel power button through 0 ohm resistor.
45	45	HOOK2	✅	HOOK2 test signal connected to PMC_CORE_PWROK through 1K resistor.
46	46	PMC_RSTBTN	✅	PMC reset button signal with 1K pull-up to +V1P8S and 0.1uF debounce capacitor.
47	47	HOOK6	✅	HOOK6 test signal connected to PMC_PLTRST_R_V1P8 through 1K resistor.
48	48	ILB_RTC_TESTB	✅	ILB RTC test signal with 1K pull-up to +RTCVCC and 1uF capacitor.
51	51	HOOK4	✅	HOOK4 test signal connected to +3VSB through 0 ohm resistor.
52	52	XDP_H_TRSTB	✅	JTAG reset signal (active low) for XDP interface.
53	53	HOOK5	✅	HOOK5 test signal connected to +V1P8S through 0 ohm resistor.
54	54	XDP_H_TCK	✅	JTAG clock signal for XDP interface.
55	55	+V1P8A	✅	1.8V analog power supply for buffer U1 and other analog circuitry.
56	56	XDP_H_TMS	✅	JTAG mode select signal for XDP interface.
58	58	XDP_H_TDI	✅	JTAG data input signal for XDP interface.

R3 - 200 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XDP_H_PREQB_PB	✅	Connected to XDP_H_PREQB_PB, providing pull-up function for the buffer input.
2	2	+V1P8A	✅	Connected to +V1P8A power rail, completing the pull-up resistor configuration.

U1 - SN74AUP1G34 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin is correctly left unconnected.
2	A	XDP_H_PREQB_PB	✅	Input A is connected to XDP_H_PREQB_PB with a 200 ohm pull-up resistor to +V1P8A, providing proper input conditioning.
3	GND	GND	✅	GND pin is correctly connected to the ground net.
4	Y	XDP_H_PREQB	✅	Output Y is connected to XDP_H_PREQB, providing the buffered output signal.
5	VCC	+V1P8A	✅	VCC pin is connected to +V1P8A with proper 0.1uF bypass capacitor to ground as recommended by datasheet.

C5 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the bypass capacitor.
2	2	+V1P8A	✅	Connected to +V1P8A, providing power supply decoupling for U1 as recommended by datasheet.

R6 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal. This pin forms one end of a pull-up resistor for the reset button test signal.
2	2	+V1P8S	✅	Connected to +V1P8S power rail. This pin provides the pull-up voltage for the PMC_RSTBTN signal.

R7 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	ILB_RTC_TESTB	✅	Connected to ILB_RTC_TESTB signal. This pin forms one end of a pull-up resistor for the RTC test signal.
2	2	+RTCVCC	✅	Connected to +RTCVCC power rail. This pin provides the pull-up voltage for the ILB_RTC_TESTB signal.

C1 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal. This pin provides filtering and debouncing for the reset button signal.
2	2	GND	✅	Connected to GND. This pin provides the ground reference for the filter capacitor.

C2 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This pin provides the ground reference for the filter capacitor.
2	2	ILB_RTC_TESTB	✅	Connected to ILB_RTC_TESTB signal. This pin provides filtering for the RTC test signal.

R13 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SCL	✅	Pin 1 connects to I2C6_SCL and serves as one end of the pull-up resistor for the I2C clock line going to expansion connector J10 pin 21.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C clock line.

R14 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SDA	✅	Pin 1 connects to I2C6_SDA and serves as one end of the pull-up resistor for the I2C data line going to expansion connector J10 pin 23.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C data line.

R18 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB	✅	0 ohm jumper connecting +3VSB power rail to expansion connector pin HOOK4 (J10 pin 51). Allows easy disconnection or current measurement of power supply.
2	2	HOOK4	✅	0 ohm jumper connecting +3VSB power rail to expansion connector pin HOOK4 (J10 pin 51). Allows easy disconnection or current measurement of power supply.

R17 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PLTRST_R_V1P8	✅	1K ohm series resistor connecting PMC_PLTRST_R_V1P8 signal to expansion connector pin HOOK6 (J10 pin 47). Provides current limiting and signal isolation.
2	2	HOOK6	✅	1K ohm series resistor connecting PMC_PLTRST_R_V1P8 signal to expansion connector pin HOOK6 (J10 pin 47). Provides current limiting and signal isolation.

R5 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HOOK1	✅	0 ohm jumper connecting HOOK1 (J10 pin 42) to FP_PWRBTN signal. Allows easy disconnection or current measurement if needed.
2	2	FP_PWRBTN	✅	0 ohm jumper connecting HOOK1 (J10 pin 42) to FP_PWRBTN signal. Allows easy disconnection or current measurement if needed.

R16 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_CORE_PWROK	✅	1K ohm series resistor connecting PMC_CORE_PWROK signal to expansion connector pin HOOK2 (J10 pin 45). Provides current limiting and signal isolation.
2	2	HOOK2	✅	1K ohm series resistor connecting PMC_CORE_PWROK signal to expansion connector pin HOOK2 (J10 pin 45). Provides current limiting and signal isolation.

R15 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSMRST	✅	1K ohm series resistor connecting PMC_RSMRST signal to expansion connector pin HOOK0 (J10 pin 41). Provides current limiting and signal isolation.
2	2	HOOK0	✅	1K ohm series resistor connecting PMC_RSMRST signal to expansion connector pin HOOK0 (J10 pin 41). Provides current limiting and signal isolation.

R20 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	0 ohm jumper connecting +V1P8S power rail to expansion connector pin HOOK5 (J10 pin 53). Allows easy disconnection or current measurement of power supply.
2	2	HOOK5	✅	0 ohm jumper connecting +V1P8S power rail to expansion connector pin HOOK5 (J10 pin 53). Allows easy disconnection or current measurement of power supply.

R21 - 110-0002078 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A power rail (1.8V analog supply), providing the pull-up voltage for the XDP_H_TDO signal through the 51Ω resistor.
2	2	XDP_H_TDO	✅	Connected to XDP_H_TDO signal (JTAG Test Data Out) which routes to pin 57 of expansion connector J10. The 51Ω value is unusually low for a pull-up resistor and warrants verification against Intel XDP interface specifications, though it may be intentional for signal integrity or impedance matching requirements.

U42 - WGI210AT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	LAN_PWR_GOOD	$18N3538	✅	LAN_PWR_GOOD output with 10K pullup to +3VSB_LAN. This is a power good indicator signal.
2	NC_SI_CLK_IN	$18N3372	✅	NC_SI_CLK_IN pulled to ground through 1K resistor. This is a not-connected pin being terminated.
3	NC_SI_CRS_DV	$18N3374	✅	NC_SI_CRS_DV pulled to ground through 1K resistor. This is a not-connected pin being terminated.
4	JTAG_TDO		✅	JTAG_TDO left unconnected. This is acceptable for a JTAG output pin when JTAG is not used.
5	NC_SI_RXD1	$18N3305	✅	NC_SI_RXD1 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated.
6	NC_SI_RXD0	$18N3303	✅	NC_SI_RXD0 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated.
7	NC_SI_TX_EN	$18N3376	✅	NC_SI_TX_EN pulled to ground through 1K resistor. This is a not-connected pin being terminated.
8	NC_SI_TXD1	$18N3301	✅	NC_SI_TXD1 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated.
9	NC_SI_TXD0	$18N3299	✅	NC_SI_TXD0 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated.
10	VDD3P3_10	+3VSB_LAN	✅	VDD3P3_10 connected to +3VSB_LAN power rail with proper decoupling capacitors.
11	VDD0P9_11	+0V9_LAN	✅	VDD0P9_11 connected to +0V9_LAN power rail with proper decoupling capacitors.
12	NVM_SI	$18N2399	✅	NVM_SI (SPI MOSI) connected to EEPROM U43 through 33.2 ohm series resistor with weak pullup.
13	NVM_SK	$18N2397	✅	NVM_SK (SPI clock) connected to EEPROM U43 through 33.2 ohm series resistor.
14	NVM_SO	$18N3554	✅	NVM_SO (SPI MISO) connected to EEPROM U43 through 33.2 ohm series resistor.
15	NVM_CS_N	$18N2395	✅	NVM_CS_N (SPI chip select) connected to EEPROM U43 through 33.2 ohm series resistor.
16	PE_WAKE_N	PMC_PCIE_WAKE	✅	PE_WAKE_N connected to PMC_PCIE_WAKE signal for PCIe wake functionality.
17	PE_RST_N	PMC_PLTRST_L	✅	PE_RST_N connected to PMC_PLTRST_L signal for PCIe reset functionality.
18	JTAG_TMS	$18N3293	✅	JTAG_TMS pulled up to +3VSB_LAN through 10K resistor for JTAG interface.
19	JTAG_CLK	$18N3295	✅	JTAG_CLK pulled up to +3VSB_LAN through 10K resistor for JTAG interface.
20	PE_TXN	PCIE_C_RXP2	✅	PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity.
21	PE_TXP	PCIE_C_RXN2	✅	PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity.
23	PE_RXN	PCIE_C_TXP2	✅	PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity.
24	PE_RXP	PCIE_C_TXN2	✅	PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity.
22	NC/INTVCC		✅	NC/INTVCC pin left unconnected. This pin is either not connected or an internal voltage regulator output.
25	PECLK_N	PCIE_CLK-N2	✅	PECLK_N and PECLK_P connected to PCIe reference clock differential pair with test points.
26	PECLK_P	PCIE_CLK-P2	✅	PECLK_N and PECLK_P connected to PCIe reference clock differential pair with test points.
27	VDD3P3_27	+3VSB_LAN	✅	VDD3P3_27 connected to +3VSB_LAN power rail with proper decoupling capacitors.
28	DEV_OFF_N	$18N3540	✅	DEV_OFF_N pulled up to +3VSB_LAN through 10K resistor. This is a device enable/disable control.
29	JTAG_TDI	$18N3297	✅	JTAG_TDI pulled up to +3VSB_LAN through 10K resistor for JTAG interface.
30	LED1	LAN-LED1	✅	LED1 output connected through 301 ohm resistor to LINK-LED-N at RJ45 connector.
31	LED0	LAN-LED0	✅	LED0 output connected directly to RJ45 connector LED2_AC1 pin without series resistor.
32	VDD0P9_32	+0V9_LAN	✅	VDD0P9_32 connected to +0V9_LAN power rail with proper decoupling capacitors.
33	LED2	LAN-LED2	✅	LED2 output connected through 301 ohm resistor to 1G-LED-N at RJ45 connector.
34	SMB_CLK	LAN-SMB-CLK	✅	SMB_CLK connected to LAN-SMB-CLK for SMBus clock interface.
35	SMB_ALRT_N	LAN-SMB-ALERT#	✅	SMB_ALRT_N connected to LAN-SMB-ALERT# for SMBus alert signal.
36	SMB_DATA	LAN-SMB-DATA	✅	SMB_DATA connected to LAN-SMB-DATA for SMBus data interface.
37	CBOT	$18N2590	✅	CBOT and CTOP pins connected through 0.039uF capacitor for internal voltage regulator.
40	CTOP	$18N2588	✅	CBOT and CTOP pins connected through 0.039uF capacitor for internal voltage regulator.
38	VDD0P9_OUT	+0V9_LAN	✅	VDD0P9_OUT connected to +0V9_LAN. This is the internal 0.9V regulator output.
39	VDD1P5_OUT	+1V5_LAN	✅	VDD1P5_OUT connected to +1V5_LAN. This is the internal 1.5V regulator output.
41	VDD3P3_41	+3VSB_LAN	✅	VDD3P3_41 connected to +3VSB_LAN power rail with proper decoupling capacitors.
42	VDD0P9_42	+0V9_LAN	✅	VDD0P9_42 connected to +0V9_LAN power rail with proper decoupling capacitors.
43	NC_SI_ARB_IN		✅	NC_SI_ARB_IN and NC_SI_ARB_OUT left unconnected. These are not-connected pins.
44	NC_SI_ARB_OUT		✅	NC_SI_ARB_IN and NC_SI_ARB_OUT left unconnected. These are not-connected pins.
45	XTAL2	LAN_XTAL2	✅	XTAL2 and XTAL1 connected to 25MHz crystal with 27pF load capacitors.
46	XTAL1	LAN_XTAL1	✅	XTAL2 and XTAL1 connected to 25MHz crystal with 27pF load capacitors.
47	VDD1P5_47	+1V5_LAN	✅	VDD1P5_47 connected to +1V5_LAN power rail with proper decoupling capacitors.
48	RSET	LAN_RSET	✅	RSET connected to ground through 4.99K resistor for setting output impedance.
49	MDI_MINUS3/SER_N	MDI_N3	✅	MDI_MINUS3/SER_N and MDI_PLUS3/SER_P connected to Ethernet differential pair 3 at RJ45 connector.
50	MDI_PLUS3/SER_P	MDI_P3	✅	MDI_MINUS3/SER_N and MDI_PLUS3/SER_P connected to Ethernet differential pair 3 at RJ45 connector.
51	VDD3P3_51	+3VSB_LAN	✅	VDD3P3_51 connected to +3VSB_LAN power rail with proper decoupling capacitors.
52	MDI_MINUS2/SET_N	MDI_N2	✅	MDI_MINUS2/SET_N and MDI_PLUS2 connected to Ethernet differential pair 2 at RJ45 connector.
53	MDI_PLUS2	MDI_P2	✅	MDI_MINUS2/SET_N and MDI_PLUS2 connected to Ethernet differential pair 2 at RJ45 connector.
54	MDI_MINUS1/SRDS_SIG_DET	MDI_N1	✅	MDI_MINUS1/SRDS_SIG_DET and MDI_PLUS1/SFP_I2C_CLK connected to Ethernet differential pair 1 at RJ45 connector.
55	MDI_PLUS1/SFP_I2C_CLK	MDI_P1	✅	MDI_MINUS1/SRDS_SIG_DET and MDI_PLUS1/SFP_I2C_CLK connected to Ethernet differential pair 1 at RJ45 connector.
56	VDD1P5_56	+1V5_LAN	✅	VDD1P5_56 connected to +1V5_LAN power rail with proper decoupling capacitors.
57	MDI_MINUS0/SFP_I2C_DATA	MDI_N0	✅	MDI_MINUS0/SFP_I2C_DATA and MDI_PLUS0/NC connected to Ethernet differential pair 0 at RJ45 connector.
58	MDI_PLUS0/NC	MDI_P0	✅	MDI_MINUS0/SFP_I2C_DATA and MDI_PLUS0/NC connected to Ethernet differential pair 0 at RJ45 connector.
59	VDD0P9_59	+0V9_LAN	✅	VDD0P9_59 connected to +0V9_LAN power rail with proper decoupling capacitors.
60	SDP3		✅	SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected.
61	SDP1/PCIE_DIS		✅	SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected.
62	SDP2		✅	SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected.
63	SDP0		✅	SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected.
64	VDD3P3_64	+3VSB_LAN	✅	VDD3P3_64 connected to +3VSB_LAN power rail with proper decoupling capacitors.
65	GND_PAD	GND	✅	GND_PAD connected to ground plane.

R830 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pin 1 is connected to +3VSB_LAN and serves as the pull-up voltage source for the WP# pin of U43.
2	2	$18N3609	✅	Pin 2 is connected to net $18N3609 (U43 pin 3 WP#) and provides a pull-up to disable hardware write protection.

R835 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2439	✅	Pin 1 is connected to net $18N2439 (U43 pin 1 CS#) and serves as part of the series resistor for the SPI Chip Select line.
2	2	$18N2395	✅	Pin 2 is connected to net $18N2395 (U42 pin 15 NVM_CS_N) and serves as part of the series resistor for the SPI Chip Select line.

R831 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pin 1 is connected to +3VSB_LAN and serves as the pull-up voltage source for the HOLD# pin of U43.
2	2	$18N3659	✅	Pin 2 is connected to net $18N3659 (U43 pin 7 HOLD#) and provides a pull-up to disable the hold function for normal operation.

R832 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2435	✅	Pin 1 is connected to net $18N2435 (U43 pin 5 SI) and serves as part of the series resistor for the SPI Serial Input line.
2	2	$18N2399	✅	Pin 2 is connected to net $18N2399 (U42 pin 12 NVM_SI) and serves as part of the series resistor for the SPI Serial Input line.

R848 - 1120-0359 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pin 1 is connected to +3VSB_LAN and serves as the pull-up voltage source for the SI pin of U43.
2	2	$18N2435	✅	Pin 2 is connected to net $18N2435 (U43 pin 5 SI) and provides a weak pull-up to ensure the SI line has a defined state when not actively driven.

R833 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3554	✅	Pin 1 is connected to net $18N3554 (U42 pin 14 NVM_SO) and serves as part of the series resistor for the SPI Serial Output line.
2	2	$18N3552	✅	Pin 2 is connected to net $18N3552 (U43 pin 2 SO) and serves as part of the series resistor for the SPI Serial Output line.

R834 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2437	✅	Pin 1 is connected to net $18N2437 (U43 pin 6 SCK) and serves as part of the series resistor for the SPI Serial Clock line.
2	2	$18N2397	✅	Pin 2 is connected to net $18N2397 (U42 pin 13 NVM_SK) and serves as part of the series resistor for the SPI Serial Clock line.

U43 - AT25DF081A-SSH ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	$18N2439	✅	CS# (Chip Select) is correctly connected to the LAN controller (U42 pin 15 NVM_CS_N) through a 33.2Ω series resistor (R835) for signal integrity.
2	SO	$18N3552	✅	SO (Serial Output) is correctly connected to the LAN controller (U42 pin 14 NVM_SO) through a 33.2Ω series resistor (R833) for signal integrity.
3	WP#	$18N3609	✅	WP# (Write Protect) is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R830), disabling hardware write protection as recommended by the datasheet.
4	GND	GND	✅	GND is correctly connected to the ground net.
5	SI	$18N2435	✅	SI (Serial Input) is correctly connected to the LAN controller (U42 pin 12 NVM_SI) through a 33.2Ω series resistor (R832) with a 33.2KΩ pull-up resistor (R848) to +3VSB_LAN.
6	SCK	$18N2437	✅	SCK (Serial Clock) is correctly connected to the LAN controller (U42 pin 13 NVM_SK) through a 33.2Ω series resistor (R834) for signal integrity.
7	HOLD#	$18N3659	✅	HOLD# is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R831), disabling the hold function for normal operation as recommended by the datasheet.
8	VCC	+3VSB_LAN	✅	VCC is correctly connected to +3VSB_LAN (3.3V standby power), which is within the device's operating voltage range of 2.7V to 3.6V.

C428 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise.
2	2	GND	✅	Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise.

R843 - 1120-0203 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED1	✅	LED current limiting resistor for the link status LED. Pin 1 connects to LAN-LED1 from U42 LED1 output, pin 2 to LINK-LED-N at J11 pin 13.
2	2	LINK-LED-N	✅	LED current limiting resistor for the link status LED. Pin 1 connects to LAN-LED1 from U42 LED1 output, pin 2 to LINK-LED-N at J11 pin 13.

J11 - 3362-0042 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	MD1+	MDI_P0	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
2	MD1-	MDI_N0	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
3	MD2+	MDI_P1	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
4	MD2-	MDI_N1	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
7	MD3+	MDI_P2	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
8	MD3-	MDI_N2	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
9	MD4+	MDI_P3	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
10	MD4-	MDI_N3	✅	MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42.
5	CT1	$18N3856	✅	Center tap pins of the integrated transformer. Both pins are tied together to net $18N3856 and bypassed to ground through three capacitors (C426, C427, C428) for filtering.
6	CT2	$18N3856	✅	Center tap pins of the integrated transformer. Both pins are tied together to net $18N3856 and bypassed to ground through three capacitors (C426, C427, C428) for filtering.
11	LED2_AC1	LAN-LED0	✅	LED2_AC1 pin connects to LAN-LED0 net, which is driven by U42 pin 31 (LED0 output). This is one terminal of the second LED.
12	LED2_AD1	1G-LED-N	✅	LED2_AD1 pin connects to 1G-LED-N net through R844 (301 ohm) from U42 LED2 output. This is the other terminal of the second LED, indicating Gigabit link status.
13	LED1_C	LINK-LED-N	✅	LED1_C pin connects to LINK-LED-N net through R843 (301 ohm) from U42 LED1 output. This is the cathode of the first LED indicating link status.
14	LED1_A	+3VSB_LAN	✅	LED1_A pin connects to +3VSB_LAN power supply. This is the anode of the first LED, providing power for the link status indicator.
15	SHLD1	GND_EARTH	✅	Shield pins correctly connected to GND_EARTH for EMI shielding. This provides proper grounding of the connector shield while maintaining isolation from digital ground.
16	SHLD2	GND_EARTH	✅	Shield pins correctly connected to GND_EARTH for EMI shielding. This provides proper grounding of the connector shield while maintaining isolation from digital ground.

C430 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1G-LED-N	✅	EMI filtering capacitor on the Gigabit LED line. Pin 1 connects to 1G-LED-N, pin 2 to GND, reducing emissions from LED switching.
2	2	GND	✅	EMI filtering capacitor on the Gigabit LED line. Pin 1 connects to 1G-LED-N, pin 2 to GND, reducing emissions from LED switching.

C427 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise.
2	2	GND	✅	Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise.

C431 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED0	✅	EMI filtering capacitor on the LAN-LED0 line. Pin 1 connects to LAN-LED0, pin 2 to GND, reducing emissions from LED switching.
2	2	GND	✅	EMI filtering capacitor on the LAN-LED0 line. Pin 1 connects to LAN-LED0, pin 2 to GND, reducing emissions from LED switching.

C429 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LINK-LED-N	✅	EMI filtering capacitor on the link LED line. Pin 1 connects to LINK-LED-N, pin 2 to GND, reducing emissions from LED switching.
2	2	GND	✅	EMI filtering capacitor on the link LED line. Pin 1 connects to LINK-LED-N, pin 2 to GND, reducing emissions from LED switching.

R844 - 1120-0203 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED2	✅	LED current limiting resistor for the Gigabit link status LED. Pin 1 connects to LAN-LED2 from U42 LED2 output, pin 2 to 1G-LED-N at J11 pin 12.
2	2	1G-LED-N	✅	LED current limiting resistor for the Gigabit link status LED. Pin 1 connects to LAN-LED2 from U42 LED2 output, pin 2 to 1G-LED-N at J11 pin 12.

C426 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise.
2	2	GND	✅	Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise.

C253 - 123-0001107 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Load capacitor for crystal oscillator connected between LAN_XTAL2 and ground. The 27pF value is typical for crystal oscillator circuits.
2	2	GND	✅	Load capacitor for crystal oscillator connected between LAN_XTAL2 and ground. The 27pF value is typical for crystal oscillator circuits.

X1 - 145-0004792 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Crystal pin connected to LAN_XTAL2 net, which connects to U42 pin 45 (XTAL2). This is one of the two active crystal oscillator pins.
2	2	GND	✅	Ground connection for crystal case/shield. This is correct for a 4-pin crystal package.
3	3	LAN_XTAL1	✅	Crystal pin connected to LAN_XTAL1 net, which connects to U42 pin 46 (XTAL1). This is one of the two active crystal oscillator pins.
4	4	GND	✅	Ground connection for crystal case/shield. This is correct for a 4-pin crystal package.

R836 - 1120-0018 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	RSET resistor connected between ground and U42 pin 48 (RSET). This resistor sets the output impedance of the MDI interface.
2	2	LAN_RSET	✅	RSET resistor connected between ground and U42 pin 48 (RSET). This resistor sets the output impedance of the MDI interface.

C252 - 123-0001107 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL1	✅	Load capacitor for crystal oscillator connected between LAN_XTAL1 and ground. The 27pF value is typical for crystal oscillator circuits.
2	2	GND	✅	Load capacitor for crystal oscillator connected between LAN_XTAL1 and ground. The 27pF value is typical for crystal oscillator circuits.

FB12 - 3044-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB	✅	Input pin connected to +3VSB main standby rail. This ferrite bead filters the 3.3V standby supply for the LAN section.
2	2	+3VSB_LAN	✅	Output pin connected to +3VSB_LAN filtered rail. Provides filtered 3.3V power to the LAN controller U42.

C423 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply.
2	2	GND	✅	Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply.

C424 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply.
2	2	GND	✅	Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply.

C413 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.
2	2	GND	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.

C414 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.
2	2	GND	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.

C415 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.
2	2	GND	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.

C416 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.
2	2	GND	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.

C417 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.
2	2	GND	✅	High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering.

C419 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+1V5_LAN	✅	Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply.
2	2	GND	✅	Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply.

C420 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+0V9_LAN	✅	Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply.
2	2	GND	✅	Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply.

C421 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+1V5_LAN	✅	Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply.
2	2	GND	✅	Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply.

C422 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+0V9_LAN	✅	Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply.
2	2	GND	✅	Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply.

C408 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+0V9_LAN	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.
2	2	GND	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.

C409 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+0V9_LAN	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.
2	2	GND	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.

C410 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+0V9_LAN	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.
2	2	GND	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.

C411 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+1V5_LAN	✅	High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering.
2	2	GND	✅	High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering.

C412 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+1V5_LAN	✅	High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering.
2	2	GND	✅	High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering.

C418 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+0V9_LAN	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.
2	2	GND	✅	High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply.

C425 - 2221-0017 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2588	✅	Compensation capacitor for U42 internal voltage regulator. Connected between CTOP and CBOT pins for regulator stability.
2	2	$18N2590	✅	Compensation capacitor for U42 internal voltage regulator. Connected between CTOP and CBOT pins for regulator stability.

R820 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for JTAG_TMS signal on U42.
2	2	$18N3293	✅	Connected to JTAG_TMS signal net $18N3293.

R821 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for JTAG_CLK signal on U42.
2	2	$18N3295	✅	Connected to JTAG_CLK signal net $18N3295.

R822 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for JTAG_TDI signal on U42.
2	2	$18N3297	✅	Connected to JTAG_TDI signal net $18N3297.

R823 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_TXD0 signal on U42.
2	2	$18N3299	✅	Connected to NC_SI_TXD0 signal net $18N3299.

R824 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_TXD1 signal on U42.
2	2	$18N3301	✅	Connected to NC_SI_TXD1 signal net $18N3301.

R825 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_RXD0 signal on U42.
2	2	$18N3303	✅	Connected to NC_SI_RXD0 signal net $18N3303.

R826 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_RXD1 signal on U42.
2	2	$18N3305	✅	Connected to NC_SI_RXD1 signal net $18N3305.

R827 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for DEV_OFF_N signal on U42.
2	2	$18N3540	✅	Connected to DEV_OFF_N signal net $18N3540.

R828 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for LAN_PWR_GOOD signal on U42.
2	2	$18N3538	✅	Connected to LAN_PWR_GOOD signal net $18N3538.

R837 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3372	✅	Pull-down resistor connected to NC_SI_CLK_IN signal. Pulls the serial interface clock input to ground when not driven.
2	2	GND	✅	Connected to ground.

R838 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3374	✅	Pull-down resistor connected to NC_SI_CRS_DV signal. Pulls the carrier sense/data valid signal to ground when not active.
2	2	GND	✅	Connected to ground.

R839 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3376	✅	Pull-down resistor connected to NC_SI_TX_EN signal. Pulls the transmit enable signal to ground (disabled) when not driven.
2	2	GND	✅	Connected to ground.

U7 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	UART2_RXD	✅	B2 pin connects to UART2_RXD net, which is the 3.3V side of the UART2 receive data signal going to external connector JP1 pin 19.
2	GND	GND	✅	GND pin is correctly connected to the ground net.
3	VCCA	+V1P8S	✅	VCCA pin is connected to +V1P8S (1.8V supply) with appropriate decoupling capacitor C350 nearby.
4	A2	SIO_UART2_RXD	✅	A2 pin connects to SIO_UART2_RXD, which is the 1.8V side of the UART2 receive data signal from the SIO/SOC.
5	A1	SIO_UART2_TXD	✅	A1 pin connects to SIO_UART2_TXD, which is the 1.8V side of the UART2 transmit data signal from the SIO/SOC.
6	OE	PMC_PLTRST_R_V1P8	✅	OE pin is connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is not in reset.
7	VCCB	+3VSB	✅	VCCB pin is connected to +3VSB (3.3V standby supply) with appropriate decoupling capacitor C351 nearby.
8	B1	UART2_TXD	✅	B1 pin connects to UART2_TXD net, which is the 3.3V side of the UART2 transmit data signal going to external connector JP1 pin 17.

U15 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA pin is connected to +V1P8S (1.8V supply) with appropriate decoupling capacitor C356 nearby.
2	A1	SIO_UART1_RTSB	✅	A1 pin connects to SIO_UART1_RTSB, which is the 1.8V side of the UART1 Request To Send signal (active low) from the SIO/SOC.
3	A2	SIO_UART1_CTSB	✅	A2 pin connects to SIO_UART1_CTSB, which is the 1.8V side of the UART1 Clear To Send signal (active low) from the SIO/SOC.
4	A3	SIO_UART1_RXD	✅	A3 pin connects to SIO_UART1_RXD, which is the 1.8V side of the UART1 receive data signal from the SIO/SOC.
5	A4	SIO_UART1_TXD	✅	A4 pin connects to SIO_UART1_TXD, which is the 1.8V side of the UART1 transmit data signal from the SIO/SOC.
6	GND	GND	✅	GND pin is correctly connected to the ground net.
7	B4	UART1_TXD	✅	B4 pin connects to UART1_TXD net, which is the 3.3V side of the UART1 transmit data signal going to external connector JP1 pin 6.
8	B3	UART1_RXD	✅	B3 pin connects to UART1_RXD net, which is the 3.3V side of the UART1 receive data signal going to external connector JP1 pin 8.
9	B2	UART1_CTSB	✅	B2 pin connects to UART1_CTSB net, which is the 3.3V side of the UART1 Clear To Send signal (active low) going to external connector JP1 pin 10.
10	B1	UART1_RTSB	✅	B1 pin connects to UART1_RTSB net, which is the 3.3V side of the UART1 Request To Send signal (active low) going to external connector JP1 pin 12.
11	VCCB	+3VSB	✅	VCCB pin is connected to +3VSB (3.3V standby supply) with appropriate decoupling capacitor C357 nearby.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin is connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is not in reset.

U17 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S, providing the reference voltage for the A-side (1.8V) of the level translator.
2	A1	I2S_MCLK	✅	A1 is correctly connected to I2S_MCLK, which is translated to I2SMCLK_GPIO on the B-side through B1.
3	A2	SOC_PWM1	✅	A2 is correctly connected to SOC_PWM1, which is translated to PWM1 on the B-side through B2.
4	A3	SOC_PWM0	✅	A3 is correctly connected to SOC_PWM0, which is translated to PWM0 on the B-side through B3.
5	A4		✅	A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components.
7	B4	GND	✅	A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components.
6	GND	GND	✅	GND is correctly connected to the ground net, providing the common reference for the level translator.
8	B3	PWM0	✅	B3 is correctly connected to PWM0, forming the B-side of the translation pair with A3.
9	B2	PWM1	✅	B2 is correctly connected to PWM1, forming the B-side of the translation pair with A2.
10	B1	I2SMCLK_GPIO	✅	B1 is correctly connected to I2SMCLK_GPIO, forming the B-side of the translation pair with A1.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB, providing the reference voltage for the B-side (3.3V) of the level translator using an always-on 3.3V standby supply.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator after platform reset is deasserted.

U10 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the reference voltage for the A-side (1.8V) of the level translator.
2	A1	SOC_GPIO_S5_2	✅	A1 is correctly connected to SOC_GPIO_S5_2, which is translated to GPIO_S5_2 on the B-side through B1.
3	A2	SOC_GPIO_S5_1	✅	A2 is correctly connected to SOC_GPIO_S5_1, which is translated to GPIO_S5_1 on the B-side through B2.
4	A3	SOC_GPIO_S5_0	✅	A3 is correctly connected to SOC_GPIO_S5_0, which is translated to GPIO_S5_0 on the B-side through B3.
5	A4		✅	A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components.
7	B4	GND	✅	A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components.
6	GND	GND	✅	GND is correctly connected to the ground net, providing the common reference for the level translator.
8	B3	GPIO_S5_0	✅	B3 is correctly connected to GPIO_S5_0, forming the B-side of the translation pair with A3.
9	B2	GPIO_S5_1	✅	B2 is correctly connected to GPIO_S5_1, forming the B-side of the translation pair with A2.
10	B1	GPIO_S5_2	✅	B1 is correctly connected to GPIO_S5_2, forming the B-side of the translation pair with A1.
11	VCCB	+PS_3VSB	✅	VCCB is correctly connected to +PS_3VSB, providing the reference voltage for the B-side (3.3V) of the level translator. This matches the design note requiring an always-on 3.3V supply.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator after platform reset is deasserted.

U14 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to the +V1P8S (1.8V) supply rail, providing the A-side reference voltage for the level translator.
2	A1	SOC_SIO_SPI_CLK	✅	A1 is correctly connected to SOC_SIO_SPI_CLK, translating the SPI clock signal from the 1.8V SOC domain to the 3.3V domain on B1.
3	A2	SOC_SIO_SPI_MOSI	✅	A2 is correctly connected to SOC_SIO_SPI_MOSI, translating the SPI MOSI signal from the 1.8V SOC domain to the 3.3V domain on B2.
4	A3	SOC_SIO_SPI_MISO	✅	A3 is correctly connected to SOC_SIO_SPI_MISO, translating the SPI MISO signal from the 1.8V SOC domain to the 3.3V domain on B3.
5	A4	SOC_SIO_SPI_CS1	✅	A4 is correctly connected to SOC_SIO_SPI_CS1, translating the SPI chip select signal from the 1.8V SOC domain to the 3.3V domain on B4.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	SIO_SPI_CS1	✅	B4 is correctly connected to SIO_SPI_CS1, providing the 3.3V level-translated SPI chip select signal to the GPIO header.
8	B3	SIO_SPI_MISO	✅	B3 is correctly connected to SIO_SPI_MISO, providing the 3.3V level-translated SPI MISO signal to the GPIO header.
9	B2	SIO_SPI_MOSI	✅	B2 is correctly connected to SIO_SPI_MOSI, providing the 3.3V level-translated SPI MOSI signal to the GPIO header.
10	B1	SIO_SPI_CLK	✅	B1 is correctly connected to SIO_SPI_CLK, providing the 3.3V level-translated SPI clock signal to the GPIO header.
11	VCCB	+3VSB	✅	VCCB is correctly connected to the +3VSB (3.3V standby) supply rail, providing the B-side reference voltage for the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset.

U16 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA power supply pin correctly connected to +V1P8S (1.8V supply) to power the A-side of the level translator.
2	A1	I2S_DATIN_R	✅	A1 pin correctly connected to I2S_DATIN_R signal, which connects through R128 to LPE_I2S_DATIN. This translates the I2S data input signal from 1.8V to 3.3V for the GPIO header.
3	A2	I2S_DATOUT_R	✅	A2 pin correctly connected to I2S_DATOUT_R signal, which connects through R130 to LPE_I2S_DATOUT. This translates the I2S data output signal from 1.8V to 3.3V for the GPIO header.
4	A3	I2S_FRM_R	✅	A3 pin correctly connected to I2S_FRM_R signal, which connects through R129 to LPE_I2S_FRM. This translates the I2S frame signal from 1.8V to 3.3V for the GPIO header.
5	A4	I2S_CLK_R	✅	A4 pin correctly connected to I2S_CLK_R signal, which connects through R127 to LPE_I2S_CLK. This translates the I2S clock signal from 1.8V to 3.3V for the GPIO header.
6	GND	GND	✅	GND pin correctly connected to the ground net.
7	B4	I2SCLK_GPIO	✅	B4 pin correctly connected to I2SCLK_GPIO signal, which goes to JP1 pin 14. This is the 3.3V side of the I2S clock signal pair with A4.
8	B3	I2SFRM_GPIO	✅	B3 pin correctly connected to I2SFRM_GPIO signal, which goes to JP1 pin 16. This is the 3.3V side of the I2S frame signal pair with A3.
9	B2	I2SDO_GPIO	✅	B2 pin correctly connected to I2SDO_GPIO signal, which goes to JP1 pin 18. This is the 3.3V side of the I2S data output signal pair with A2.
10	B1	I2SDI_GPIO	✅	B1 pin correctly connected to I2SDI_GPIO signal, which goes to JP1 pin 20. This is the 3.3V side of the I2S data input signal pair with A1.
11	VCCB	+3VSB	✅	VCCB power supply pin correctly connected to +3VSB (3.3V standby supply) to power the B-side of the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE (output enable) pin correctly connected to PMC_PLTRST_R_V1P8, which is a platform reset signal at 1.8V level. This enables the translator when the platform is out of reset.

R127 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_CLK_R	✅	0-ohm resistor connecting I2S_CLK_R from U16 pin 5 to LPE_I2S_CLK. This provides a direct connection with optional series termination capability.
2	2	LPE_I2S_CLK	✅	0-ohm resistor connecting I2S_CLK_R from U16 pin 5 to LPE_I2S_CLK. This provides a direct connection with optional series termination capability.

R128 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_DATIN_R	✅	0-ohm resistor connecting I2S_DATIN_R from U16 pin 2 to LPE_I2S_DATIN. This provides a direct connection with optional series termination capability.
2	2	LPE_I2S_DATIN	✅	0-ohm resistor connecting I2S_DATIN_R from U16 pin 2 to LPE_I2S_DATIN. This provides a direct connection with optional series termination capability.

R129 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_FRM_R	✅	0-ohm resistor connecting I2S_FRM_R from U16 pin 4 to LPE_I2S_FRM. This provides a direct connection with optional series termination capability.
2	2	LPE_I2S_FRM	✅	0-ohm resistor connecting I2S_FRM_R from U16 pin 4 to LPE_I2S_FRM. This provides a direct connection with optional series termination capability.

R130 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_DATOUT_R	✅	0-ohm resistor connecting I2S_DATOUT_R from U16 pin 3 to LPE_I2S_DATOUT. This provides a direct connection with optional series termination capability.
2	2	LPE_I2S_DATOUT	✅	0-ohm resistor connecting I2S_DATOUT_R from U16 pin 3 to LPE_I2S_DATOUT. This provides a direct connection with optional series termination capability.

U18 - NTB0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the A-side reference voltage for the level translator.
2	A1	SOC_SPI_MOSI-R	✅	A1 is correctly connected to SOC_SPI_MOSI-R for SPI MOSI signal translation from the SOC side.
3	A2	SOC_SPI_CLK-R	✅	A2 is correctly connected to SOC_SPI_CLK-R for SPI clock signal translation from the SOC side.
4	A3	SOC_SPI_MISO-R	✅	A3 is correctly connected to SOC_SPI_MISO-R for SPI MISO signal translation from the SOC side.
5	A4	SOC_SPI_CS0B-R	✅	A4 is correctly connected to SOC_SPI_CS0B-R for SPI chip select signal translation from the SOC side.
6	GND	GND	✅	GND is correctly connected to ground.
7	B4	SPI_CS0	✅	B4 is correctly connected to SPI_CS0 for SPI chip select signal on the B-side.
8	B3	SPI_MISO	✅	B3 is correctly connected to SPI_MISO for SPI MISO signal on the B-side.
9	B2	SPI_CLK	✅	B2 is correctly connected to SPI_CLK for SPI clock signal on the B-side.
10	B1	SPI_MOSI	✅	B1 is correctly connected to SPI_MOSI for SPI MOSI signal on the B-side.
11	VCCB	+V_SPI	✅	VCCB is correctly connected to +V_SPI, providing the B-side reference voltage for the level translator.
12	OE	DDP_IO3L	✅	OE is correctly connected to DDP_IO3L with pull-up resistor R147, enabling the translator by default and allowing external control via the DediProg connector.

R147 - 100K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pin 1 is correctly connected to +V1P8A to provide pull-up voltage for the OE signal.
2	2	DDP_IO3L	✅	Pin 2 is correctly connected to DDP_IO3L, providing pull-up for the OE pin of U18.

U40 - PCA9306DCUT ❌

DRCY flagged 1 potential issues in this component.

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Pin Designator	Pin Name	Net	Correct?	Analysis
5	SDA2	GPIO_I2C_SDA	❌	SCL2 (pin 6) and SDA2 (pin 5) are connected to GPIO_I2C_SCL and GPIO_I2C_SDA respectively, which route to header JP1. However, no pullup resistors are present on these high-voltage side I2C signals, which are required for proper open-drain I2C operation. Pin 5 (SDA2) is connected to GPIO_I2C_SDA net, which routes to JP1 pin 15 (from schematic) Pin 6 (SCL2) is connected to GPIO_I2C_SCL net, which routes to JP1 pin 13 (from schematic) Pin 7 (VREF2) and pin 8 (EN) are both connected to net $20N1576, which connects through R812 (200K) to +3VSB (from schematic) No pullup resistors are present on GPIO_I2C_SDA or GPIO_I2C_SCL nets to +3VSB or any other high-voltage supply (from schematic) The low-voltage side pins 3 (SCL1) and 4 (SDA1) have proper pullup resistors R267 and R266 (10K) to +V1P8S (from schematic) Pin 5 is SDA2 (serial data, high-voltage side) and pin 6 is SCL2 (serial clock, high-voltage side) (from datasheet 4318-0010, page 4) Datasheet states: 'Translation on standard open-drain I2C bus is achieved by connecting pull-up resistors from SCL1 and SDA1 to VREF1 and from SCL2 and SDA2 to VDPU' (from datasheet 4318-0010, page 16) Typical application circuits in the datasheet show pullup resistors (RPU) on both SCL2 and SDA2 to the high-voltage supply (from datasheet 4318-0010, page 17) The datasheet application section emphasizes that pullup resistors are required for open-drain I2C operation (from datasheet 4318-0010, page 18) Without pullup resistors, the I2C bus cannot function properly as there is no mechanism to pull the lines high (reasoning) The presence of pullup resistors on the low-voltage side (R266, R267) indicates the designer understood this requirement, making the omission on the high-voltage side likely an oversight rather than intentional (reasoning) While it is possible that external devices connected via JP1 could provide pullup resistors, this is not documented in the schematic and creates an undocumented dependency on external hardware (reasoning) Best practice requires either: (1) including pullup resistors on this board (e.g., 10K from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB), or (2) adding a clear schematic note indicating that external pullup resistors are required (reasoning) The design as shown is incomplete and will not function without modification or external components (reasoning)
6	SCL2	GPIO_I2C_SCL	❌	SCL2 (pin 6) and SDA2 (pin 5) are connected to GPIO_I2C_SCL and GPIO_I2C_SDA respectively, which route to header JP1. However, no pullup resistors are present on these high-voltage side I2C signals, which are required for proper open-drain I2C operation. Pin 5 (SDA2) is connected to GPIO_I2C_SDA net, which routes to JP1 pin 15 (from schematic) Pin 6 (SCL2) is connected to GPIO_I2C_SCL net, which routes to JP1 pin 13 (from schematic) Pin 7 (VREF2) and pin 8 (EN) are both connected to net $20N1576, which connects through R812 (200K) to +3VSB (from schematic) No pullup resistors are present on GPIO_I2C_SDA or GPIO_I2C_SCL nets to +3VSB or any other high-voltage supply (from schematic) The low-voltage side pins 3 (SCL1) and 4 (SDA1) have proper pullup resistors R267 and R266 (10K) to +V1P8S (from schematic) Pin 5 is SDA2 (serial data, high-voltage side) and pin 6 is SCL2 (serial clock, high-voltage side) (from datasheet 4318-0010, page 4) Datasheet states: 'Translation on standard open-drain I2C bus is achieved by connecting pull-up resistors from SCL1 and SDA1 to VREF1 and from SCL2 and SDA2 to VDPU' (from datasheet 4318-0010, page 16) Typical application circuits in the datasheet show pullup resistors (RPU) on both SCL2 and SDA2 to the high-voltage supply (from datasheet 4318-0010, page 17) The datasheet application section emphasizes that pullup resistors are required for open-drain I2C operation (from datasheet 4318-0010, page 18) Without pullup resistors, the I2C bus cannot function properly as there is no mechanism to pull the lines high (reasoning) The presence of pullup resistors on the low-voltage side (R266, R267) indicates the designer understood this requirement, making the omission on the high-voltage side likely an oversight rather than intentional (reasoning) While it is possible that external devices connected via JP1 could provide pullup resistors, this is not documented in the schematic and creates an undocumented dependency on external hardware (reasoning) Best practice requires either: (1) including pullup resistors on this board (e.g., 10K from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB), or (2) adding a clear schematic note indicating that external pullup resistors are required (reasoning) The design as shown is incomplete and will not function without modification or external components (reasoning)
1	GND	GND	✅	GND pin correctly connected to ground plane.
2	VREF1	+V1P8S	✅	VREF1 correctly connected to +V1P8S (1.8V) low-voltage reference supply.
3	SCL1	I2C5_SCL	✅	SCL1 correctly connected to I2C5_SCL with 10K pullup resistor R267 to +V1P8S.
4	SDA1	I2C5_SDA	✅	SDA1 correctly connected to I2C5_SDA with 10K pullup resistor R266 to +V1P8S.
7	VREF2	$20N1576	✅	VREF2 and EN pins correctly shorted together and pulled to +3VSB through 200K resistor R812 per datasheet application guidance.
8	EN	$20N1576	✅	VREF2 and EN pins correctly shorted together and pulled to +3VSB through 200K resistor R812 per datasheet application guidance.

R266 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C5_SDA	✅	Connected to I2C5_SDA, providing pullup for SDA1 line of U40.
2	2	+V1P8S	✅	Connected to +V1P8S supply, completing the pullup resistor function.

R267 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C5_SCL	✅	Connected to I2C5_SCL, providing pullup for SCL1 line of U40.
2	2	+V1P8S	✅	Connected to +V1P8S supply, completing the pullup resistor function.

R812 - 110-0001951 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N1576	✅	Connected to net $20N1576 which shorts U40 VREF2 and EN pins together.
2	2	+3VSB	✅	Connected to +3VSB supply, providing the required 200K pullup for VREF2/EN per datasheet.

R818 - 0R00 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N2079	✅	R818 is correctly marked DNI (Do Not Install) because U3 is populated with W25Q64BVSSIG, a 3.3V SPI flash part. R818 would connect +V1P8A (1.8V) to the voltage selection circuit, but since a 3.3V part is used, R152 is populated instead to connect +3VSB.
2	2	+V1P8A	✅	R818 is correctly marked DNI (Do Not Install) because U3 is populated with W25Q64BVSSIG, a 3.3V SPI flash part. R818 would connect +V1P8A (1.8V) to the voltage selection circuit, but since a 3.3V part is used, R152 is populated instead to connect +3VSB.

R152 - 0R00 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N2079	✅	R152 is correctly populated as a 0-ohm jumper to connect +3VSB (3.3V) to the SPI flash power selection circuit, matching the installed W25Q64BVSSIG 3.3V part.
2	2	+3VSB	✅	R152 is correctly populated as a 0-ohm jumper to connect +3VSB (3.3V) to the SPI flash power selection circuit, matching the installed W25Q64BVSSIG 3.3V part.

R163 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	R163 correctly provides a 10K pull-up resistor on the CS# pin of U3, matching the datasheet recommendation.
2	2	SPI_CS0	✅	R163 correctly provides a 10K pull-up resistor on the CS# pin of U3, matching the datasheet recommendation.

D8 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	DDP_VCC	✅	Anode 1 is correctly connected to DDP_VCC (DediProg connector power) for OR-ing power sources.
A2	A2	$20N2079	✅	Anode 2 is correctly connected to $20N2079, which connects through R152 to +3VSB for system power supply.
C	C	+V_SPI	✅	Common cathode is correctly connected to +V_SPI, providing the OR-ed power output to the SPI flash.

R164 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	R164 correctly provides a 10K pull-up resistor on the WP# pin of U3 to disable write protection in standard SPI mode.
2	2	SPI_WP	✅	R164 correctly provides a 10K pull-up resistor on the WP# pin of U3 to disable write protection in standard SPI mode.

U3 - W25Q64BVSSIG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPI_CS0	✅	CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pull-up resistor to +V_SPI through R163.
2	SO/IO1	SPI_MISO	✅	SO/IO1 (Data Output) is correctly connected to SPI_MISO for standard SPI data output.
3	WP#/IO2	SPI_WP	✅	WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pull-up resistor to +V_SPI through R164, disabling write protection in standard SPI mode.
4	GND	GND	✅	GND is correctly connected to the ground net.
5	SI/IO0	SPI_MOSI	✅	SI/IO0 (Data Input) is correctly connected to SPI_MOSI for standard SPI data input.
6	SCK	SPI_CLK	✅	CLK (Serial Clock) is correctly connected to SPI_CLK for the SPI clock input.
7	HOLD#/IO3	SPI_HOLD	✅	HOLD#/IO3 is correctly connected to SPI_HOLD with a 10K pull-up resistor to +V_SPI through R165, disabling the hold function in standard SPI mode.
8	VCC	+V_SPI	✅	VCC is correctly connected to +V_SPI with proper decoupling capacitors. The power supply is derived from +3VSB through R152 and D8, providing approximately 2.9-3.0V which is within the 2.7-3.6V operating range.

R165 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	R165 correctly provides a 10K pull-up resistor on the HOLD# pin of U3 to disable the hold function in standard SPI mode.
2	2	SPI_HOLD	✅	R165 correctly provides a 10K pull-up resistor on the HOLD# pin of U3 to disable the hold function in standard SPI mode.

JP1 - 258-0005019 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connections for the expansion header.
2	2	GND	✅	Ground connections for the expansion header.
3	3	+PS_5VSB	✅	5V standby power supply output for the expansion header.
4	4	+3VSB	✅	3.3V standby power supply output for the expansion header.
5	5	SIO_SPI_CS1	✅	SPI chip select 1 signal, level-translated from SOC 1.8V to 3.3V via U14.
6	6	UART1_TXD	✅	UART1 transmit signal, level-translated from SOC 1.8V to 3.3V via U15.
7	7	SIO_SPI_MISO	✅	SPI MISO signal, level-translated from SOC 1.8V to 3.3V via U14.
8	8	UART1_RXD	✅	UART1 receive signal, level-translated from SOC 1.8V to 3.3V via U15.
9	9	SIO_SPI_MOSI	✅	SPI MOSI signal, level-translated from SOC 1.8V to 3.3V via U14.
10	10	UART1_CTSB	✅	UART1 clear-to-send signal, level-translated from SOC 1.8V to 3.3V via U15.
11	11	SIO_SPI_CLK	✅	SPI clock signal, level-translated from SOC 1.8V to 3.3V via U14.
12	12	UART1_RTSB	✅	UART1 request-to-send signal, level-translated from SOC 1.8V to 3.3V via U15.
13	13	GPIO_I2C_SCL	✅	I2C clock signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator).
14	14	I2SCLK_GPIO	✅	I2S clock signal, level-translated from SOC 1.8V to 3.3V via U16.
15	15	GPIO_I2C_SDA	✅	I2C data signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator).
16	16	I2SFRM_GPIO	✅	I2S frame sync signal, level-translated from SOC 1.8V to 3.3V via U16.
17	17	UART2_TXD	✅	UART2 transmit signal, level-translated from SOC 1.8V to 3.3V via U7.
18	18	I2SDO_GPIO	✅	I2S data out signal, level-translated from SOC 1.8V to 3.3V via U16.
19	19	UART2_RXD	✅	UART2 receive signal, level-translated from SOC 1.8V to 3.3V via U7.
20	20	I2SDI_GPIO	✅	I2S data in signal, level-translated from SOC 1.8V to 3.3V via U16.
21	21	GPIO_S5_0	✅	GPIO S5_0 signal, level-translated from SOC 1.8V to 3.3V via U10.
22	22	PWM0	✅	PWM0 signal, level-translated from SOC 1.8V to 3.3V via U17.
23	23	GPIO_S5_1	✅	GPIO S5_1 signal, level-translated from SOC 1.8V to 3.3V via U10.
24	24	PWM1	✅	PWM1 signal, level-translated from SOC 1.8V to 3.3V via U17.
25	25	GPIO_S5_2	✅	GPIO S5_2 signal, level-translated from SOC 1.8V to 3.3V via U10.
26	26	I2SMCLK_GPIO	✅	I2S master clock signal, level-translated from SOC 1.8V to 3.3V via U17.

J1 - 258-0004612 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDP_VCC	✅	DDP_VCC provides power to the DediProg programmer interface. It is OR'd with +V_SPI through diode D8 and can be sourced from either +3VSB (via R152) or +V1P8A (via R818, DNI).
2	2	GND	✅	Ground connection for the DediProg programmer interface.
3	3	SPI_CS0	✅	SPI chip select signal for the DediProg programmer interface, connected to U3 SPI flash CS# and level translator U18.
4	4	SPI_CLK	✅	SPI clock signal for the DediProg programmer interface, connected to U3 SPI flash SCK and level translator U18.
5	5	SPI_MISO	✅	SPI MISO (Master In Slave Out) signal for the DediProg programmer interface, connected to U3 SPI flash SO/IO1 and level translator U18.
6	6	SPI_MOSI	✅	SPI MOSI (Master Out Slave In) signal for the DediProg programmer interface, connected to U3 SPI flash SI/IO0 and level translator U18.
7	7		✅	No connection on pin 7.
8	8	DDP_IO3L	✅	DDP_IO3L controls the output enable of level translator U18, allowing the DediProg to take control of the SPI bus by disabling the SOC connection.

Q105 - FDN327N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	GPIO_LED_CONTROL	✅	Drain is connected to GPIO_LED_CONTROL node, which connects to +VCC through R746 (470Ω) and to LED D2 anode. This forms a shunt-mode LED control circuit where the MOSFET turns OFF the LED by pulling the node low.
G	GATE	GPIO_D2_LED_CTRL	✅	Gate is connected to GPIO_D2_LED_CTRL signal with a 10K pull-down resistor (R706) to GND. This provides proper gate drive control with default-OFF state when the GPIO is not driven.
S	SOURCE	GND	✅	Source is connected to GND, which is correct for an N-channel MOSFET used as a low-side switch in this shunt-mode LED control circuit.

D2 - 4560-0045 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GPIO_LED_CONTROL	✅	Anode is connected to GPIO_LED_CONTROL node, which connects to +VCC through current-limiting resistor R746 (470Ω). This is the correct polarity for LED operation.
C	CATHODE	GND	✅	Cathode is connected to GND, which is the correct polarity for LED operation. The LED is controlled by Q105 shunting current when active.

D9 - D5V0L1B2LP-7B ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Bidirectional TVS diode correctly connected between FP_PWRBTN signal and GND for ESD protection. The 5V reverse standoff voltage is appropriate for the 5V signal level.
P	P	FP_PWRBTN	✅	Bidirectional TVS diode correctly connected between FP_PWRBTN signal and GND for ESD protection. The 5V reverse standoff voltage is appropriate for the 5V signal level.

J5 - 258-0002513 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Header pin 1 connected to FP_PWRBTN net, allowing a jumper to be installed for test/debug purposes to simulate button press.
2	2	GND	✅	Header pin 2 connected to GND net, completing the jumper circuit to simulate button press when jumper is installed.

SW1 - 3770-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Switch signal pin connected to FP_PWRBTN net with pullup resistor R149 (4.7K), debounce capacitor C154 (0.1uF), and TVS diode D9 for ESD protection. Schematic notes indicate datasheet recommends 10K pullup, but 4.7K is used.
2	2	GND	✅	Switch return pin correctly connected to GND net, providing the signal ground return path when the button is pressed.
3	GND1	GND_EARTH	✅	Chassis ground pins correctly connected to GND_EARTH net for EMI shielding. GND_EARTH is isolated from signal GND (R145 is DNI), which is typical for EMI/EMC considerations.
4	GND2	GND_EARTH	✅	Chassis ground pins correctly connected to GND_EARTH net for EMI shielding. GND_EARTH is isolated from signal GND (R145 is DNI), which is typical for EMI/EMC considerations.

D1 - 4560-0045 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	+PS_5VSB	✅	Anode is correctly connected to +PS_5VSB supply rail to power the LED when adapter power is present.
C	CATHODE	PWR_LEDR	✅	Cathode is correctly connected through current limiting resistor R148 (470Ω) to ground, providing appropriate LED current of approximately 3.8mA.

U35 - PWR_CTRL_EMB_PROC ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
4	SLP_S5#	SLP_S4_L	❌	Pin 4 (SLP_S5#) is connected to net SLP_S4_L. There is an explicit naming mismatch between the pin name (indicating an S5 sleep state signal) and the connected net (indicating an S4 sleep state signal). This connection should be verified as S4 and S5 are distinct ACPI power states. Pin 4 (SLP_S5#) is connected to net SLP_S4_L (from schematic) The pin name SLP_S5# explicitly indicates this pin expects an ACPI S5 (Soft Off) sleep state signal (reasoning) The connected net SLP_S4_L indicates an ACPI S4 (Suspend to Disk/Hibernate) sleep state signal (reasoning) In ACPI specifications, S4 and S5 are distinct power states: S4 allows the system to save context to disk and wake from various sources, while S5 is a soft-off state with limited wake sources (reasoning) Both the # suffix (pin name) and _L suffix (net name) indicate active-low signals, so the polarity is consistent (reasoning) Other pins on U35 show consistent naming between pin names and net names (e.g., PS_OUT# to PS_OUT_L), making this S5/S4 mismatch stand out (from schematic) While this connection could theoretically be intentional if the system design uses S4 to trigger S5 functionality or treats these states identically, such a design choice would typically be explicitly documented (reasoning) Without the NCT3012S-X datasheet to verify the intended function and requirements of pin 4, this naming mismatch should be flagged as a potential error requiring verification (reasoning) The explicit nature of the mismatch suggests either a connection error or a net naming inconsistency that should be corrected (reasoning)
1	DeepS5_Sel	S5_SEL	✅	DeepS5_Sel is a configuration input with a 2.2K pull-up resistor to +PS_5VSB, likely used to select Deep S5 mode operation.
2	VSB	+PS_5VSB	✅	VSB is the power supply input for the controller, correctly connected to the +PS_5VSB rail with adequate decoupling capacitors nearby.
3	PS_IN#	PB_RES	✅	PS_IN# is the active-low power button input, correctly connected through a 33 ohm series resistor to the front panel power button for current limiting and debouncing.
5	SDA	DDR_SMB_DATA	✅	SDA is the I2C/SMBus data line, correctly connected to DDR_SMB_DATA for communication with DDR memory modules.
6	SCLK	DDR_SMB_CLK	✅	SCLK is the I2C/SMBus clock line, correctly connected to DDR_SMB_CLK for communication with DDR memory modules.
7	PS_OUT#	PS_OUT_L	✅	PS_OUT# is an active-low power state output signal connected to PS_OUT_L net, with a DNI resistor (R289) that would have pulled it up to +PS_3VSB if populated.
8	SYS5VSB_OFF	5VSB_CTRL	✅	SYS5VSB_OFF controls the 5VSB power rail enable/disable and EuP mode. It has a 1K pull-up to +PS_5VSB and drives the 5VSB gate control circuit through R323.
9	GND	GND	✅	GND is the ground pin, correctly connected to the system ground plane.

L3 - IND_2.2uH_20%_10A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3VSB_PHASE	✅	Inductor pin 1 correctly connected to switch node PS3VSB_PHASE for buck converter operation.
2	2	+PS_3VSB	✅	Inductor pin 2 correctly connected to output rail +PS_3VSB for buck converter operation.

U13 - REG_LDO_BUCK_24V ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN	PS5VSB_VIN	✅	VIN pin correctly connected to PS5VSB_VIN with appropriate input capacitors for decoupling and filtering.
2	PGND	GND	✅	PGND pin correctly connected to ground plane.
3	N/C		✅	N/C pin correctly left unconnected as specified in datasheet.
4	PG	+PS_3VSB_PG	✅	PG pin correctly configured as open-drain output with pull-up resistor and connected to power sequencing circuit.
5	CLK	$22N1411	✅	CLK pin correctly connected to external charge pump circuit for generating gate drive voltage.
6	LDO	PS3_LDO	✅	LDO pin correctly connected to 10uF output capacitor for internal 3.3V LDO regulation.
7	VOUT	+PS_3VSB	✅	VOUT pin correctly connected to output rail with multiple output capacitors for voltage sensing and regulation.
8	SW1	PS3VSB_PHASE	✅	SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology.
9	SW2	PS3VSB_PHASE	✅	SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology.
15	SW3	PS3VSB_PHASE	✅	SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology.
16	SW4	PS3VSB_PHASE	✅	SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology.
10	BST	PS3_BST	✅	BST pin correctly connected to bootstrap circuit with capacitor between SW and BST through damping resistor.
11	VCC	PS3_VCC	✅	VCC pin correctly connected to internal 5V LDO output with 1uF decoupling capacitor.
12	ENLDO		✅	ENLDO pin correctly left floating as it is internally pulled high for normal operation.
13	EN	PS3_EN	✅	EN pin correctly configured with pull-up resistor to VIN for buck regulator enable control.
14	AGND	GND	✅	AGND pin correctly connected to ground plane for analog ground reference.

Q106 - BSS84 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	D	DC_GATE_ENB	✅	Drain pin correctly connected to DC_GATE_ENB to control U36 gate voltage. When Q106 turns on, it pulls DC_GATE_ENB high to turn off U36.
G	G	$22N2300	✅	Gate pin correctly connected to $22N2300, which is driven by voltage divider R855 and clamped by zener diode D13 to detect overvoltage condition.
S	S	$22N1502	✅	Source pin correctly connected to $22N1502, which is the common reference point for the protection circuit and connects to DC_IN_1 through ferrite beads.

D13 - 4620-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Anode pin correctly connected to GND for zener diode voltage reference configuration.
C	CATHODE	$22N2300	✅	Cathode pin correctly connected to $22N2300 to clamp the gate drive voltage for Q106 at 4.3V, setting the trip point for the overvoltage protection circuit.

U36 - MOSFET_30V_15A_8-SOIC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	$22N1502	✅	Source pins correctly connected to $22N1502 net, which connects through ferrite beads to DC_IN_1. Multiple source pins are paralleled for higher current capability.
2	S2	$22N1502	✅	Source pins correctly connected to $22N1502 net, which connects through ferrite beads to DC_IN_1. Multiple source pins are paralleled for higher current capability.
3	S3	$22N1502	✅	Source pins correctly connected to $22N1502 net, which connects through ferrite beads to DC_IN_1. Multiple source pins are paralleled for higher current capability.
4	G	DC_GATE_ENB	✅	Gate pin correctly connected to DC_GATE_ENB control signal, which is driven by protection circuit Q106 and pulled down by R309.
5	D1	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability.
6	D2	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability.
7	D3	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability.
8	D4	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability.

Q103 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+5VSB	✅	Source pins correctly connected to +5VSB output rail. These three pins are paralleled to handle the high current (up to 15.3A) and reduce resistance.
2	S2	+5VSB	✅	Source pins correctly connected to +5VSB output rail. These three pins are paralleled to handle the high current (up to 15.3A) and reduce resistance.
3	S3	+5VSB	✅	Source pins correctly connected to +5VSB output rail. These three pins are paralleled to handle the high current (up to 15.3A) and reduce resistance.
4	G	5VSB_LSENB	✅	Gate pin correctly connected to 5VSB_LSENB control signal with proper gate drive circuitry for high-side N-Channel switching.
5	D1	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance.
6	D2	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance.
7	D3	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance.
8	D4	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance.

Q104 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+3VSB	✅	Source pins correctly connected to +3VSB output rail. These pins carry the switched output current to the system 3.3V standby supply.
2	S2	+3VSB	✅	Source pins correctly connected to +3VSB output rail. These pins carry the switched output current to the system 3.3V standby supply.
3	S3	+3VSB	✅	Source pins correctly connected to +3VSB output rail. These pins carry the switched output current to the system 3.3V standby supply.
4	G	+3VSB_EN	✅	Gate pin correctly connected to +3VSB_EN control signal with appropriate drive circuitry. The gate is driven to +10V when enabled, providing sufficient VGS for full enhancement.
5	D1	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output.
6	D2	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output.
7	D3	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output.
8	D4	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output.

Q6 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB	✅	Drain is connected to +3VSB (3.3V power rail), serving as the input power source for this high-side switch. This connection is correct.
G	GATE	SYS_EN	✅	Gate is connected to SYS_EN, which is driven to +10V when the MOSFET should be on and to GND when off. This provides sufficient gate drive voltage for full enhancement.
S	SOURCE	+VCC3	✅	Source is connected to +VCC3, the output rail of this high-side switch. This configuration is correct for an N-channel MOSFET with elevated gate drive.

Q13 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+5VSB	✅	Drain is connected to +5VSB (5V power rail), serving as the input power source for this high-side switch. This connection is correct.
G	GATE	SYS_EN	✅	Gate is connected to SYS_EN, which is driven to +10V when the MOSFET should be on and to GND when off. This provides sufficient gate drive voltage for full enhancement.
S	SOURCE	+VCC	✅	Source is connected to +VCC, the output rail of this high-side switch. This configuration is correct for an N-channel MOSFET with elevated gate drive.

Q4 - XSTR_NPN_40V_200mA_SOT23 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
B	BASE	S5_ENBL	❌	Package pinout mismatch: The schematic uses package SOT23_EBC, but the MMBT3904 datasheet specifies a B-E-C physical pinout. This mismatch will cause the base and emitter pins to be swapped on the physical PCB, preventing correct transistor operation. Pin B (BASE) is connected to net S5_ENBL in the schematic (from schematic) Pin E (EMITTER) is connected to net GND in the schematic (from schematic) The component specifies package SOT23_EBC in the PKG_TYPE attribute (from schematic) By convention observed in other components (e.g., SOT23_GSD for 2N7002K MOSFETs where G-S-D corresponds to physical pins 1-2-3), the package name SOT23_EBC indicates physical pin mapping: Pin 1=E, Pin 2=B, Pin 3=C (reasoning) The MMBT3904 datasheet shows the actual SOT-23 pinout as: Pin 1=Base, Pin 2=Emitter, Pin 3=Collector (from datasheet MMBT3904, page 3) With package SOT23_EBC, the footprint will map logical pin E to physical pin 1 and logical pin B to physical pin 2 (reasoning) When assembled on the PCB, physical pin 1 (Base per datasheet) will connect to the GND net (assigned to logical E), and physical pin 2 (Emitter per datasheet) will connect to S5_ENBL net (assigned to logical B) (reasoning) This pin swap will reverse-bias the base-emitter junction and prevent the transistor from functioning as intended (reasoning) The package should be changed to SOT23_BEC to match the MMBT3904 datasheet pinout, or a different transistor with E-B-C pinout should be selected (reasoning)
E	EMITTER	GND	❌	Package pinout mismatch: The schematic uses package SOT23_EBC, but the MMBT3904 datasheet specifies a B-E-C physical pinout. This mismatch will cause the base and emitter pins to be swapped on the physical PCB, preventing correct transistor operation. Pin B (BASE) is connected to net S5_ENBL in the schematic (from schematic) Pin E (EMITTER) is connected to net GND in the schematic (from schematic) The component specifies package SOT23_EBC in the PKG_TYPE attribute (from schematic) By convention observed in other components (e.g., SOT23_GSD for 2N7002K MOSFETs where G-S-D corresponds to physical pins 1-2-3), the package name SOT23_EBC indicates physical pin mapping: Pin 1=E, Pin 2=B, Pin 3=C (reasoning) The MMBT3904 datasheet shows the actual SOT-23 pinout as: Pin 1=Base, Pin 2=Emitter, Pin 3=Collector (from datasheet MMBT3904, page 3) With package SOT23_EBC, the footprint will map logical pin E to physical pin 1 and logical pin B to physical pin 2 (reasoning) When assembled on the PCB, physical pin 1 (Base per datasheet) will connect to the GND net (assigned to logical E), and physical pin 2 (Emitter per datasheet) will connect to S5_ENBL net (assigned to logical B) (reasoning) This pin swap will reverse-bias the base-emitter junction and prevent the transistor from functioning as intended (reasoning) The package should be changed to SOT23_BEC to match the MMBT3904 datasheet pinout, or a different transistor with E-B-C pinout should be selected (reasoning)
C	COLLECTOR	+3VSB_EN_L	✅	Collector is correctly connected to +3VSB_EN_L with a 1K pull-up resistor to +PS_5VSB, driving the gate of Q11.

Q11 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB_EN	✅	Drain is correctly connected to +3VSB_EN, which controls the gate of Q104 through a 100K pull-up resistor to +10V.
G	GATE	+3VSB_EN_L	✅	Gate is correctly connected to +3VSB_EN_L, which is driven by Q4 collector through a 1K pull-up resistor.
S	SOURCE	GND	✅	Source is correctly connected to GND for common-source configuration.

Q7 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN_GATE	✅	Drain connected to SYS_EN_GATE net, which is the output node of this inverter stage. When Q7 is on, it pulls this node low; when off, R142 pulls it high to +10V.
G	GATE	SLP_S3_L	✅	Gate connected to SLP_S3_L signal, which controls the MOSFET switching. When SLP_S3_L is high, Q7 turns on; when low, Q7 is off.
S	SOURCE	GND	✅	Source connected to GND, which is the correct configuration for an N-channel MOSFET used as a low-side switch.

Q12 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN	✅	Drain connected to SYS_EN net, which controls the gates of Q13 and Q6 to enable system power rails. When Q12 is on, it pulls SYS_EN low; when off, R340 pulls it high to +10V.
G	GATE	SYS_EN_GATE	✅	Gate connected to SYS_EN_GATE net, which is driven by Q7's drain. When SYS_EN_GATE is high (~10V), Q12 turns on; when low, Q12 is off.
S	SOURCE	GND	✅	Source connected to GND, which is the correct configuration for an N-channel MOSFET used as a low-side switch.

Q14 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	5VSB_LSENB	✅	Drain is connected to 5VSB_LSENB net, which controls the gate of Q103 P-channel power MOSFET and is pulled up to +10V through R324 (100K). This is a standard N-channel MOSFET low-side switch configuration for controlling the load switch.
G	GATE	5VSB_GATE	✅	Gate is connected to 5VSB_GATE, which is derived from 5VSB_CTRL through R323 (10K) with C340 (1uF) providing filtering. The gate voltage of approximately 5V when on is sufficient to fully enhance the MOSFET and is within the ±20V VGS rating.
S	SOURCE	GND	✅	Source is connected to GND, which is the standard configuration for an N-channel MOSFET low-side switch.

Q10 - FET_NCH_60V_300mA_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	S5_ENBL	✅	Drain is connected to S5_ENBL net, which is pulled up to +V1P8A through R133 (10K) and drives the base of Q4 NPN transistor. This is a standard N-channel MOSFET low-side switch configuration for controlling the S5_ENBL signal.
G	GATE	5VSB_CTRL	✅	Gate is connected to 5VSB_CTRL from U35 power controller, which is pulled up to +PS_5VSB through R288 (1K). The gate voltage of approximately 5V when on is sufficient to fully enhance the MOSFET and is within the ±20V VGS rating.
S	SOURCE	GND	✅	Source is connected to GND, which is the standard configuration for an N-channel MOSFET low-side switch.

Q2 - DIODE_ARRAY_75V_0.3A_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	+PS_5VSB	✅	Anode A1 connected to +PS_5VSB power rail for edge detection. This diode conducts when +PS_5VSB rises, coupling the positive edge through the common cathode and C72 to U13 CLK pin.
2	A2	$22N1417	✅	Anode A2 connected to intermediate node $22N1417, which connects to Q9 pin 1 and to GND through C71. This provides biasing and is normally reverse biased during operation.
3	C	$22N1419	✅	Common cathode connected to $22N1419, which couples to U13 CLK pin through C72. This is the output node of the edge detection circuit for the +PS_5VSB rail.

Q9 - DIODE_ARRAY_75V_0.3A_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	$22N1417	✅	Anode A1 connected to intermediate node $22N1417, which connects to Q2 pin 2 and to GND through C71. This provides biasing and is normally reverse biased during operation.
2	A2	+10V	✅	Anode A2 connected to +10V power rail for edge detection. This diode conducts when +10V rises, coupling the positive edge through the common cathode and C283 to U13 CLK pin.
3	C	$22N1467	✅	Common cathode connected to $22N1467, which couples to U13 CLK pin through C283. This is the output node of the edge detection circuit for the +10V rail.

D6 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB_PG	✅	Pin 1 (Anode 1) is connected to +PS_3VSB_PG, the power good signal from the 3.3VSB regulator. This allows the power good signal to pull the reset signal high through the diode when power is stable.
2	2	+3VSB_EN	✅	Pin 2 (Anode 2) is connected to +3VSB_EN, the enable signal for the 3VSB power stage. This allows the enable signal to pull the reset signal high through the diode when enabled.
3	3	PMC_RSMRST	✅	Pin 3 (Common Cathode) is connected to PMC_RSMRST, the resume reset signal. This pin outputs the OR'd result of the two input signals.

J9 - JACK_PWR_2.1MM_RAPC712 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DC_IN_1	✅	Center pin correctly connected to DC_IN_1 net, serving as the positive 5V DC power input with appropriate filtering and protection circuitry downstream.
2	2	GND	✅	Sleeve contact correctly connected to GND net, providing the ground return path for the DC power input.
3	3	GND	✅	Switched contact connected to GND, which is electrically safe but does not utilize the plug detection feature that this pin provides.

FB1 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_5VSB	✅	Pin 1 connects to +PS_5VSB power rail. This is the input side of the ferrite bead, filtering the 5V standby supply before it feeds the buck converter U13.
2	2	PS5VSB_VIN	✅	Pin 2 connects to PS5VSB_VIN, which is the input to buck converter U13 and has multiple input capacitors. This is the output side of the ferrite bead.

L12 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$22N1502	✅	Pin 1 connects to $22N1502, which is the source pins of U36 (P-channel MOSFET). This ferrite bead filters the current path from DC input to the 5VSB rail.
2	2	DC_IN_1	✅	Pin 2 connects to DC_IN_1, which is the 5V DC input from connector J9. L12 is paralleled with L13 to provide adequate current handling for the input path.

FB11 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_5VSB	✅	Pin 1 connects to +PS_5VSB power rail. FB11 is connected in parallel with FB1 to increase current handling capability.
2	2	PS5VSB_VIN	✅	Pin 2 connects to PS5VSB_VIN, parallel with FB1 pin 2. This parallel configuration provides adequate current capability for the buck converter input.

L13 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$22N1502	✅	Pin 1 connects to $22N1502, parallel with L12 pin 1. This parallel configuration increases current handling for the protection circuit.
2	2	DC_IN_1	✅	Pin 2 connects to DC_IN_1, parallel with L12 pin 2. The parallel configuration provides adequate current capability for the DC input path.

U25 - NCP81109GMNTXG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT pin is connected to VR_HOT_L net, serving as a thermal alert output signal.
2	SDIO	$23N2429	✅	SDIO and SCLK pins are connected to SVID interface signals through series termination resistors (16.9Ω and 20.0Ω respectively).
4	SCLK	$23N2430	✅	SDIO and SCLK pins are connected to SVID interface signals through series termination resistors (16.9Ω and 20.0Ω respectively).
3	ALERT	$23N2431	✅	ALERT pin is connected to SVID_ALERT-R through a 0Ω jumper, providing the SVID alert signal path.
5	GND	AGND-VCORE	✅	GND, GND1, and GND_PAD pins are all connected to AGND-VCORE, which connects to main GND through a 0Ω jumper, providing proper analog ground separation.
32	GND1	AGND-VCORE	✅	GND, GND1, and GND_PAD pins are all connected to AGND-VCORE, which connects to main GND through a 0Ω jumper, providing proper analog ground separation.
49	GND_PAD	AGND-VCORE	✅	GND, GND1, and GND_PAD pins are all connected to AGND-VCORE, which connects to main GND through a 0Ω jumper, providing proper analog ground separation.
6	VR_RDY	$23N3753	✅	VR_RDY pin connects through a 0Ω jumper to VCORE_PG, providing power good indication.
7	VIN1	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
11	VIN2	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
12	VIN3	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
13	VIN4	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
14	VIN5	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
15	VIN6	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
16	VIN7	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
17	VIN8	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
50	VIN_PAD	+5VSB_SW	✅	All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins.
8	BST	$23N3711	✅	BST pin connects through R154 (2.20Ω) and C50 (0.22µF) to SW1, forming the bootstrap circuit for the high-side gate driver.
9	GH		✅	GH pin shows no net connection in the schematic. Without datasheet confirmation, it is unclear if this is correct or if external MOSFETs are required.
10	SW1	$23N3731	✅	SW1 pin connects to the bootstrap circuit but not to the main VCORE-SW net. This may be intentional for bootstrap reference, but typically all switch nodes should be connected together in a multiphase converter.
18	SW2	VCORE-SW	✅	SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs.
25	SW3	VCORE-SW	✅	SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs.
26	SW4	VCORE-SW	✅	SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs.
27	SW5	VCORE-SW	✅	SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs.
28	SW6	VCORE-SW	✅	SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs.
29	SW7	VCORE-SW	✅	SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs.
51	SW_PAD	VCORE-SW	✅	SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs.
19	PGND1	GND	✅	PGND1-6 pins are all connected to GND, providing proper power ground connections.
20	PGND2	GND	✅	PGND1-6 pins are all connected to GND, providing proper power ground connections.
21	PGND3	GND	✅	PGND1-6 pins are all connected to GND, providing proper power ground connections.
22	PGND4	GND	✅	PGND1-6 pins are all connected to GND, providing proper power ground connections.
23	PGND5	GND	✅	PGND1-6 pins are all connected to GND, providing proper power ground connections.
24	PGND6	GND	✅	PGND1-6 pins are all connected to GND, providing proper power ground connections.
30	GL		✅	GL pin shows no net connection in the schematic. Without datasheet confirmation, it is unclear if this is correct or if external MOSFETs are required.
31	VBOOT	$23N3477	✅	VBOOT pin connects through R70 (88.7kΩ) to AGND-VCORE, setting the boot voltage. A text note indicates VBOOT should be 1.1V.
33	VCCP	$23N3625	✅	VCCP pin connects through R845 (1.00Ω) from +5VSB with C48 (4.7µF) decoupling, providing charge pump supply voltage.
34	TSENSE	$23N3665	✅	TSENSE pin connects through R78 (0Ω) to a thermistor divider network (TH2 100kΩ thermistor and R131 14.0kΩ), providing temperature sensing.
35	IMAX	$23N3681	✅	IMAX pin connects through R105 (44.2kΩ) to AGND-VCORE, setting the maximum current limit. A text note indicates IMAX should be 14A.
36	IOUT	$23N3683	✅	IOUT pin connects through R146 (16.5kΩ) to AGND-VCORE with C47 (470pF) filtering, providing output current reporting.
37	ILIM	VCORE-ILIM	✅	ILIM pin connects through R95 (15.0kΩ) to VCORE-CSCOMP, setting the current limit threshold.
38	CSCOMP	VCORE-CSCOMP	✅	CSCOMP pin connects to current sense compensation network with capacitors C39 (470pF) and C40 (2200pF) to CSSUM, plus resistors and thermistor for temperature compensation.
39	CSSUM	VCORE-CSSUM	✅	CSSUM pin connects to current sense sum network with DCR sensing through SP3 short to VCORE-SW and resistor divider to ground.
40	CSREF	VCORE-CSREF	✅	CSREF pin connects through R108 (10.0Ω) and SP4 short to +VCORE with C45 (1000pF) filtering, providing current sense reference.
41	FREQ	$23N2930	✅	FREQ pin connects through R93 (18.7kΩ) to AGND-VCORE, setting the switching frequency. A text note indicates FSW should be 650kHz.
42	COMP	VCORE-COMP	✅	COMP pin connects to voltage loop compensation network with C35 (47pF) and C37 (2200pF) providing frequency compensation.
43	FB	VCORE-FB	✅	FB pin connects to feedback network with resistor divider and compensation components for voltage regulation.
44	DIFFOUT	VCORE-DIFFOUT	✅	DIFFOUT pin connects through R89 (1.00kΩ) to FB and through R90 (47Ω) to intermediate net, forming part of the differential amplifier output.
45	VSN	VR-VCORE-VSN	✅	VSN pin connects through R65 (10.0Ω) to remote sense network with R91 (100Ω) to GND and R64 (0Ω) to VSS_SENSE, providing negative remote voltage sensing.
46	VSP	VR-VCORE-VSP	✅	VSP pin connects through R92 (100Ω) to +VCORE and through R63 (0Ω) to VCC_SENSE, providing positive remote voltage sensing.
47	VCC	$23N3860	✅	VCC pin connects through R166 (2.20Ω) from +5VSB with C24 (1.0µF) decoupling to AGND-VCORE, providing IC supply voltage.
48	EN	$23N5607	✅	EN pin connects through R849 (0Ω) to +VCC with R851 (10.0kΩ) pulldown and C433 (0.1µF) filtering, enabling the regulator when +VCC is present.

L8 - 3120-0183 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of an input filter inductor.
2	2	+5VSB_SW	✅	Pin 2 connects to the +5VSB_SW filtered input rail that supplies the U25 controller VIN pins. This is the correct connection for the output side of an input filter inductor.

L18 - 3120-0266 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Pin 1 connects to the VCORE-SW switching node from the multiphase buck converter controller U25. This is the correct connection for the input side of the output filter inductor.
2	2	+VCORE	✅	Pin 2 connects to the +VCORE output rail. This is the correct connection for the output side of the filter inductor in a buck converter.

TH2 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to net $23N3662, which receives the TSENSE signal from U25 through R78. This thermistor provides temperature sensing for the voltage regulator.
2	2	GND	✅	Connected to GND, providing the ground reference for the temperature sensing voltage divider.

TH1 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP net, which is the current sense compensation pin of U25. This thermistor provides temperature compensation for the current sensing loop.
2	2	$23N3115	✅	Connected to net $23N3115, which is the junction between R96 and R106 in the current sensing compensation network.

R78 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	Connected to net $23N3665, which connects to U25 pin 34 (TSENSE). This 0-ohm jumper allows the TSENSE signal to reach the thermistor network.
2	2	$23N3662	✅	Connected to net $23N3662, which is the junction of TH2 and R131. This completes the connection from TSENSE to the temperature sensing network.

R131 - 1120-0055 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to net $23N3662, forming a parallel combination with TH2 for temperature sensing. The 14K value sets the temperature sensing characteristics.
2	2	GND	✅	Connected to GND, completing the temperature sensing voltage divider to ground.

D4 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Cathode 1 of dual Schottky diode in common anode configuration, connected to VCORE_PG net. This pin receives the VCORE power good signal and forms one input of a wired-AND power good monitoring circuit.
2	2	VGFX_PG	✅	Cathode 2 of dual Schottky diode in common anode configuration, connected to VGFX_PG net. This pin receives the graphics voltage regulator power good signal and forms the second input of the wired-AND power good monitoring circuit.
3	3	VCORE_GFX_PG	✅	Common anode of dual Schottky diode, connected to VCORE_GFX_PG net. This pin outputs the combined power good signal that is high only when both VCORE_PG and VGFX_PG are high, implementing a wired-AND function.

R167 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Connected to +VCC3 power rail. Provides the pull-up voltage source for the VCORE_PG signal through the 1.91K resistor.
2	2	VCORE_PG	✅	Connected to VCORE_PG net. Provides pull-up for the VCORE power good signal from U25 VR_RDY pin, which is typically an open-drain output.

R79 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Connected to VCORE_PG net. This 0 ohm resistor provides a direct connection between the VR_RDY output and the power good monitoring circuit.
2	2	$23N3753	✅	Connected to internal net $23N3753 which connects to U25 pin 6 (VR_RDY). This provides the VCORE power good signal from the voltage regulator controller.

R94 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_GFX_PG	✅	Connected to VCORE_GFX_PG net and D4 pin 3 (common anode). Provides the load side of the pull-up resistor for the combined power good signal.
2	2	+VCC3	✅	Connected to +VCC3 power rail. Provides the pull-up voltage source for the combined power good signal through the 1K resistor.

R87 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system.
2	2	SVID_CLK-R	✅	DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system.

R85 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system.
2	2	SVID_DATA-R	✅	DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system.

R81 - 1120-0099 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line.
2	2	$23N2430	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line.

R80 - 1120-0329 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line.
2	2	$23N2429	✅	Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line.

R86 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system.
2	2	SVID_ALERT-R	✅	DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system.

R62 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin.
2	2	$23N2431	✅	Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin.

C87 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VCORE	✅	Positive terminal correctly connected to +VCORE output rail of the DC/DC regulator.
2	N	GND	✅	Negative terminal correctly connected to ground reference.

R88 - 1120-0032 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2824	✅	Connected to intermediate node $23N2824 in the voltage loop compensation network, forming part of a Type III compensator with C37.
2	2	VCORE-FB	✅	Connected to VCORE-FB feedback pin, completing the compensation network path from COMP through C37 and R88 to FB.

R90 - 1121-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2818	✅	Connected to intermediate node $23N2818 in the differential amplifier feedback network, forming a high-frequency filter with C36.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT differential output pin, completing the high-frequency filter path in parallel with R89.

C35 - 2220-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP compensation pin, providing direct high-frequency feedback path to FB.
2	2	VCORE-FB	✅	Connected to VCORE-FB feedback pin, completing the direct high-frequency feedback path from COMP to FB.

C36 - 2220-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB feedback pin, forming the first element of the high-frequency filter network for the differential amplifier.
2	2	$23N2818	✅	Connected to intermediate node $23N2818, forming the series connection point with R90 in the differential amplifier filter network.

C37 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP compensation pin, forming the first element of the series RC compensation network.
2	2	$23N2824	✅	Connected to intermediate node $23N2824, forming the series connection point with R88 in the compensation network.

R89 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB feedback pin, providing the main resistive feedback path to the differential amplifier output.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT differential output pin, completing the feedback path for the differential amplifier.

C40 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	2200pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, in parallel with C39 for current sense loop compensation.
2	2	VCORE-CSSUM	✅	2200pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, in parallel with C39 for current sense loop compensation.

R108 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSREF	✅	10.0 ohm resistor connecting VCORE-CSREF to the output voltage +VCORE through SP4, providing the reference for DCR current sensing.
2	2	$23N3208	✅	10.0 ohm resistor connecting VCORE-CSREF to the output voltage +VCORE through SP4, providing the reference for DCR current sensing.

R95 - 1120-0029 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-ILIM	✅	15.0K resistor connecting VCORE-ILIM to VCORE-CSCOMP, setting the current limit threshold for the voltage regulator.
2	2	VCORE-CSCOMP	✅	15.0K resistor connecting VCORE-ILIM to VCORE-CSCOMP, setting the current limit threshold for the voltage regulator.

R146 - 1120-0338 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3683	✅	16.5K pulldown resistor on the IOUT pin, configuring the output current monitoring level.
2	2	AGND-VCORE	✅	16.5K pulldown resistor on the IOUT pin, configuring the output current monitoring level.

C39 - 2220-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	470pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, forming part of the current sense loop compensation network.
2	2	VCORE-CSSUM	✅	470pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, forming part of the current sense loop compensation network.

C45 - 2220-0035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSREF	✅	1000pF bypass capacitor on the CSREF pin, providing filtering for the current sense reference voltage.
2	2	GND	✅	1000pF bypass capacitor on the CSREF pin, providing filtering for the current sense reference voltage.

R107 - 1130-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSSUM	✅	100K resistor connecting VCORE-CSSUM to the switching node VCORE-SW through SP3, implementing DCR current sensing.
2	2	$23N3209	✅	100K resistor connecting VCORE-CSSUM to the switching node VCORE-SW through SP3, implementing DCR current sensing.

R106 - 1120-0037 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3115	✅	165K resistor connecting the intermediate current sense node to VCORE-CSSUM, completing the DCR current sensing divider network.
2	2	VCORE-CSSUM	✅	165K resistor connecting the intermediate current sense node to VCORE-CSSUM, completing the DCR current sensing divider network.

R96 - 1120-0282 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	75.0K resistor in the current sense compensation network, connecting VCORE-CSCOMP to an intermediate node in the DCR current sensing path.
2	2	$23N3115	✅	75.0K resistor in the current sense compensation network, connecting VCORE-CSCOMP to an intermediate node in the DCR current sensing path.

R105 - 1120-0115 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3681	✅	44.2K pulldown resistor on the IMAX pin, setting the maximum current limit to 14A as indicated by the schematic note.
2	2	AGND-VCORE	✅	44.2K pulldown resistor on the IMAX pin, setting the maximum current limit to 14A as indicated by the schematic note.

R92 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output voltage. This is the positive input to the remote voltage sense circuit.
2	2	VR-VCORE-VSP	✅	Connected to VR-VCORE-VSP which goes to the VSP pin of the voltage regulator U25.

R63 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_SENSE	✅	Connected to VCC_SENSE remote sense point. This 0Ω jumper enables remote voltage sensing at the load.
2	2	VR-VCORE-VSP	✅	Connected to VR-VCORE-VSP, linking the remote sense point to the regulator's positive sense input.

R91 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This is the ground reference input to the remote voltage sense circuit.
2	2	$23N2860	✅	Connected to internal node $23N2860 which is part of the negative voltage sense path.

R64 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VSS_SENSE	✅	Connected to VSS_SENSE remote ground sense point. This 0Ω jumper enables remote ground sensing at the load.
2	2	$23N2860	✅	Connected to internal node $23N2860, linking the remote ground sense point to the negative sense path.

R65 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2860	✅	Connected to internal node $23N2860 in the negative voltage sense path.
2	2	VR-VCORE-VSN	✅	Connected to VR-VCORE-VSN which goes to the VSN pin of the voltage regulator U25.

C34 - 2221-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR-VCORE-VSP	✅	Connected to VR-VCORE-VSP. This capacitor is marked DNI and would provide differential filtering if installed.
2	2	VR-VCORE-VSN	✅	Connected to VR-VCORE-VSN. This DNI capacitor would filter the differential sense signal if installed.

C38 - 2221-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2860	✅	Connected to internal node $23N2860. This capacitor is marked DNI and would provide filtering on the negative sense line if installed.
2	2	VR-VCORE-VSN	✅	Connected to VR-VCORE-VSN. This DNI capacitor would filter the negative sense path if installed.

R849 - 1121-0001 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	❌	0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously. Pin 1 is connected to net +VCC (from schematic) Pin 2 is connected to net $23N5607 (from schematic) Net $23N5607 connects to U25 pin 48 (EN) (from schematic) R849 is a 0Ω jumper (part number 1121-0001) (from schematic) This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled (reasoning) R851 (10KΩ) is also populated on net $23N5607, connecting to GND (from schematic) With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND (reasoning) This creates unnecessary power dissipation in R851 (reasoning) Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω (reasoning) The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state (reasoning) Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path (reasoning)
2	2	$23N5607	❌	0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously. Pin 1 is connected to net +VCC (from schematic) Pin 2 is connected to net $23N5607 (from schematic) Net $23N5607 connects to U25 pin 48 (EN) (from schematic) R849 is a 0Ω jumper (part number 1121-0001) (from schematic) This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled (reasoning) R851 (10KΩ) is also populated on net $23N5607, connecting to GND (from schematic) With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND (reasoning) This creates unnecessary power dissipation in R851 (reasoning) Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω (reasoning) The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state (reasoning) Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path (reasoning)

R851 - 1120-0011 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N5607	❌	10KΩ pull-down resistor on EN pin of U25. With R849 (0Ω jumper to +VCC) also populated, creates wasteful current path drawing VCC/10KΩ continuously. Pin 1 is connected to net $23N5607 (from schematic) Pin 2 is connected to net GND (from schematic) Net $23N5607 connects to U25 pin 48 (EN) (from schematic) R851 is a 10KΩ resistor (part number 1120-0011) (from schematic) R849 (0Ω) connects +VCC to the same net $23N5607 (from schematic) This creates a direct current path from +VCC through R849 (0Ω) to the EN pin, then through R851 (10KΩ) to GND (reasoning) Continuous current draw of VCC/10KΩ results in unnecessary power dissipation (reasoning) The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at pulling the pin low (reasoning) R851 should be DNI when R849 is populated to avoid the wasteful current path (reasoning) If the intent is to have the regulator always enabled, only R849 should be populated; if the intent is to disable or allow external control, only R851 should be populated (reasoning)
2	2	GND	❌	10KΩ pull-down resistor on EN pin of U25. With R849 (0Ω jumper to +VCC) also populated, creates wasteful current path drawing VCC/10KΩ continuously. Pin 1 is connected to net $23N5607 (from schematic) Pin 2 is connected to net GND (from schematic) Net $23N5607 connects to U25 pin 48 (EN) (from schematic) R851 is a 10KΩ resistor (part number 1120-0011) (from schematic) R849 (0Ω) connects +VCC to the same net $23N5607 (from schematic) This creates a direct current path from +VCC through R849 (0Ω) to the EN pin, then through R851 (10KΩ) to GND (reasoning) Continuous current draw of VCC/10KΩ results in unnecessary power dissipation (reasoning) The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at pulling the pin low (reasoning) R851 should be DNI when R849 is populated to avoid the wasteful current path (reasoning) If the intent is to have the regulator always enabled, only R849 should be populated; if the intent is to disable or allow external control, only R851 should be populated (reasoning)

R154 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3711	✅	Connected to the BST (bootstrap) pin of U25 (NCP81109GMNTXG controller). This is the input side of the bootstrap resistor.
2	2	$23N3733	✅	Connected to the bootstrap capacitor C50. This is the output side of the bootstrap resistor, forming the RC network of the bootstrap circuit.

C50 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3733	✅	Connected to bootstrap resistor R154. This is the high-side terminal of the bootstrap capacitor.
2	2	$23N3731	✅	Connected to SW1 pin of U25. This is the low-side terminal of the bootstrap capacitor, referenced to the switch node.

R93 - 1120-0351 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2930	✅	Pin 1 connects to the FREQ pin (pin 41) of U25 (NCP81109GMNTXG multiphase controller) to set the switching frequency. A nearby text note indicates the target frequency is 650kHz.
2	2	AGND-VCORE	✅	Pin 2 connects to AGND-VCORE, which is the analog ground reference for the VCORE regulator section. This provides the ground reference for the frequency setting resistor.

U26 - NCP81109GMNTXG ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
10	SW1	$24N3595	❌	SW1 is isolated from the main switch node and only connected to the bootstrap capacitor return path. This configuration prevents phase 1 from contributing to the output. Pin 10 (SW1) is connected to net $24N3595 (from schematic) Bootstrap capacitor C186 (0.22µF) connects between $24N3596 and $24N3595 (SW1) (from schematic) Bootstrap resistor R228 (2.20Ω) connects between $24N3593 (BST, pin 8) and $24N3596 (from schematic) Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW (from schematic) Net VGFX-SW connects through inductor L4 to the output +VGFX (from schematic) There is no connection between net $24N3595 (SW1) and net VGFX-SW (from schematic) In a multiphase buck converter, all active switch nodes must be connected together to share current and drive the output (reasoning) The bootstrap circuit (R228, C186) connected to SW1 suggests phase 1 was intended to be active (reasoning) For the bootstrap circuit to function, SW1 must be switching, which requires it to be part of an active phase (reasoning) The isolation of SW1 from VGFX-SW prevents phase 1 from contributing to the output and renders the bootstrap circuit non-functional (reasoning) If phase 1 is intentionally disabled, the bootstrap components (R228, C186) should be marked DNP (reasoning) The correct configuration requires SW1 to be connected to VGFX-SW along with the other switch nodes (reasoning)
1	VRHOT	VR_HOT_L	✅	VRHOT pin is connected to VR_HOT_L net, which is a thermal alert output signal.
2	SDIO	$24N3490	✅	SDIO pin is connected to SVID data line through R193 (16.9Ω) series resistor with pull-up to +V1P0S through R195 (69.8Ω).
3	ALERT	$24N3492	✅	ALERT pin is connected to SVID alert line through R67 (0Ω) jumper with pull-up to +V1P0S through R196 (69.8Ω, DNI).
4	SCLK	$24N3491	✅	SCLK pin is connected to SVID clock line through R194 (20.0Ω) series resistor with pull-up to +V1P0S through R197 (69.8Ω).
5	GND	AGND-VGFX	✅	GND pin is connected to AGND-VGFX analog ground net, which connects to main GND through R66 (0Ω) jumper.
6	VR_RDY	$24N3598	✅	VR_RDY pin is connected to power good output VGFX_PG through R184 (0Ω) jumper, with pull-up R230 (1.91kΩ) to +VCC3 and decoupling C60 (0.1µF).
7	VIN1	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
11	VIN2	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
12	VIN3	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
13	VIN4	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
14	VIN5	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
15	VIN6	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
16	VIN7	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
17	VIN8	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
8	BST	$24N3593	✅	BST pin is connected to bootstrap circuit with R228 (2.20Ω) and C186 (0.22µF) to SW1 for high-side gate driver supply.
9	GH		✅	GH pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal.
18	SW2	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
25	SW3	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
26	SW4	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
27	SW5	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
28	SW6	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
29	SW7	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
19	PGND1	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
20	PGND2	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
21	PGND3	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
22	PGND4	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
23	PGND5	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
24	PGND6	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
30	GL		✅	GL pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal.
31	VBOOT	$24N3564	✅	VBOOT pin is connected to bootstrap voltage sense with R170 (100kΩ) pull-down to AGND-VGFX.
32	GND1	AGND-VGFX	✅	GND1 pin is connected to AGND-VGFX analog ground net.
33	VCCP	$24N3578	✅	VCCP pin is connected to internal LDO/charge pump supply with R846 (1Ω) from +5VSB and C185 (4.7µF) decoupling.
34	TSENSE	$24N3584	✅	TSENSE pin is connected to temperature sense network with TH4 (100kΩ@25C thermistor) and R226 (14.0kΩ) forming a divider to GND, with C168 (0.1µF) filtering.
35	IMAX	$24N3588	✅	IMAX pin is connected to R207 (44.2kΩ) to AGND-VGFX, setting the maximum current limit. A text note indicates IMAX = 14A.
36	IOUT	$24N3589	✅	IOUT pin is connected to output current reporting network with R227 (16.5kΩ) and C184 (470pF) to AGND-VGFX.
37	ILIM	VGFX-ILIM	✅	ILIM pin is connected to current limit threshold network with R204 (15.0kΩ) to VGFX-CSCOMP.
38	CSCOMP	VGFX-CSCOMP	✅	CSCOMP pin is connected to current sense compensation network with R204, R205, TH3, C113, and C166 for current loop stability and thermal compensation.
39	CSSUM	VGFX-CSSUM	✅	CSSUM pin is connected to current sense sum network with R224, R223, C113, and C166 for multiphase current sensing.
40	CSREF	VGFX-CSREF	✅	CSREF pin is connected to current sense reference with R225 (10.0Ω) to output voltage through SP1, and C167 (1000pF) to GND.
41	FREQ	$24N3542	✅	FREQ pin is connected to R203 (18.7kΩ) to AGND-VGFX, setting the switching frequency. A text note indicates FSW = 650kHz.
42	COMP	VGFX-COMP	✅	COMP pin is connected to voltage loop compensation network with C62 (47pF) to FB and C64 (2200pF) to feedback divider.
43	FB	VGFX-FB	✅	FB pin is connected to feedback network with R198 (3.01kΩ) divider, R199 (1.00kΩ) to DIFFOUT, and compensation capacitors C62 and C63.
44	DIFFOUT	VGFX-DIFFOUT	✅	DIFFOUT pin is connected to differential amplifier output network with R199 (1.00kΩ) to FB and R200 (47Ω) to compensation.
45	VSN	VR-VGFX-VSN	✅	VSN pin is connected to negative remote sense input with R169 (10.0Ω) from ground reference point.
46	VSP	VR-VGFX-VSP	✅	VSP pin is connected to positive remote sense input with R202 (100Ω) from +VGFX and R68 (0Ω) from VCCGT_SENSE.
47	VCC	$24N3610	✅	VCC pin is connected to supply input with R229 (2.20Ω) from +5VSB and C53 (1.0µF) decoupling to AGND-VGFX.
48	EN	$24N6011	✅	EN pin is connected to enable input with R850 (0Ω) pull-up to +VCC, R852 (10.0kΩ) pull-down to GND, and C434 (0.1µF) decoupling.
49	GND_PAD	AGND-VGFX	✅	GND_PAD is connected to AGND-VGFX analog ground net for thermal and electrical grounding.
50	VIN_PAD	+5VSB_SW	✅	VIN_PAD is connected to +5VSB_SW input supply for additional current handling capability.
51	SW_PAD	VGFX-SW	✅	SW_PAD is connected to VGFX-SW switch node for additional current handling capability.

L4 - 3120-0266 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to the switching node VGFX-SW from the voltage regulator U26. This is the correct connection for the input side of a buck converter output inductor.
2	2	+VGFX	✅	Connected to the output voltage rail +VGFX. This is the correct connection for the output side of a buck converter inductor. Note: The inductor is rated for 17.5A, and the current limit is set to 14A, which provides adequate margin. A text note indicates 'IMAX = 24A' near the inductor, but this may refer to peak current capability rather than continuous current.

SP2 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to the switching node VGFX-SW. This provides the switching voltage reference for current sensing through R224 to the CSSUM pin of U26.
2	2	$24N3558	✅	Connected through R224 (100kΩ) to the CSSUM pin (pin 39) of U26. This forms part of the current sensing sum network.

SP1 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Connected to the output voltage rail +VGFX. This provides the reference point for current sensing through R225 to the CSREF pin of U26.
2	2	$24N3559	✅	Connected through R225 (10Ω) to the CSREF pin (pin 40) of U26. This forms part of the current sensing reference network.

R207 - 1120-0115 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3588	✅	Connects U26 IMAX pin to AGND-VGFX to set the maximum current limit. A text note specifies 'IMAX = 14A' near this component, but without the NCP81109GMNTXG datasheet, the 44.2K value cannot be verified to achieve this specification.
2	2	AGND-VGFX	✅	Connects U26 IMAX pin to AGND-VGFX to set the maximum current limit. A text note specifies 'IMAX = 14A' near this component, but without the NCP81109GMNTXG datasheet, the 44.2K value cannot be verified to achieve this specification.

TH3 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP (U26 pin 38) as part of the current loop compensation network. This pin is part of a parallel combination with R205 to provide temperature-compensated current sensing.
2	2	$24N3557	✅	Connected to intermediate node $24N3557, which connects through R223 to VGFX-CSSUM. This completes the temperature-compensated current loop compensation network.

C168 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	C168 pin 1 connects to the TSENSE input net $24N3584, providing filtering for the temperature sense signal.
2	2	AGND-VGFX	✅	C168 pin 2 correctly connects to AGND-VGFX, the analog ground reference for the voltage regulator.

R178 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	R178 pin 1 connects to the TSENSE input net $24N3584, providing a series connection between the temperature sensing divider and the TSENSE pin.
2	2	$24N3583	✅	R178 pin 2 connects to the temperature sensing divider node $24N3583 where TH4 and R226 are in parallel.

R226 - 1120-0055 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	R226 pin 1 connects to the temperature sensing node $24N3583, forming a parallel combination with thermistor TH4.
2	2	GND	✅	R226 pin 2 correctly connects to GND, completing the parallel path with the thermistor.

TH4 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	Thermistor pin 1 connects to the temperature sensing network node $24N3583, which includes R226 in parallel and connects through R178 to U26 TSENSE pin.
2	2	GND	✅	Thermistor pin 2 correctly connects to GND, completing the temperature sensing network.

R193 - 1120-0329 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Series resistor between SVID_DATA-R signal and U26 SDIO pin. Provides signal integrity and protection for the SVID data line.
2	2	$24N3490	✅	Series resistor between SVID_DATA-R signal and U26 SDIO pin. Provides signal integrity and protection for the SVID data line.

R194 - 1120-0099 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Series resistor between SVID_CLK-R signal and U26 SCLK pin. Provides signal integrity and protection for the SVID clock line.
2	2	$24N3491	✅	Series resistor between SVID_CLK-R signal and U26 SCLK pin. Provides signal integrity and protection for the SVID clock line.

R67 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Zero ohm jumper between SVID_ALERT-R signal and U26 ALERT pin. The ALERT line has no pull-up resistor installed (R196 is DNI), which may be intentional if the signal is not used or pulled up elsewhere.
2	2	$24N3492	✅	Zero ohm jumper between SVID_ALERT-R signal and U26 ALERT pin. The ALERT line has no pull-up resistor installed (R196 is DNI), which may be intentional if the signal is not used or pulled up elsewhere.

R195 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor from +V1P0S to SVID_DATA-R signal. Provides the required pull-up for the bidirectional SVID data line.
2	2	SVID_DATA-R	✅	Pull-up resistor from +V1P0S to SVID_DATA-R signal. Provides the required pull-up for the bidirectional SVID data line.

R196 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor from +V1P0S to SVID_ALERT-R signal, marked DNI. The ALERT line has no pull-up resistor installed, which may be intentional if the signal is not used or pulled up elsewhere.
2	2	SVID_ALERT-R	✅	Pull-up resistor from +V1P0S to SVID_ALERT-R signal, marked DNI. The ALERT line has no pull-up resistor installed, which may be intentional if the signal is not used or pulled up elsewhere.

R197 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor from +V1P0S to SVID_CLK-R signal. Provides the required pull-up for the SVID clock line.
2	2	SVID_CLK-R	✅	Pull-up resistor from +V1P0S to SVID_CLK-R signal. Provides the required pull-up for the SVID clock line.

C434 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	Connected to net $24N6011 (enable signal). This provides filtering and bypassing for the enable pin.
2	2	GND	✅	Connected to GND. This completes the bypass capacitor path for the enable signal.

R852 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	Connected to net $24N6011 (enable signal). This is one side of the 10K pull-down resistor for the enable pin.
2	2	GND	✅	Connected to GND. This completes the pull-down resistor path for the enable signal.

R850 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Connected to +VCC power rail. This is the input side of the 0Ω jumper used to enable the voltage regulator U26.
2	2	$24N6011	✅	Connected to net $24N6011, which connects to the EN (enable) pin of U26, along with pull-down resistor R852 and bypass capacitor C434.

R230 - 1120-0052 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Pin 1 connects to the +VCC3 power rail, providing the pull-up voltage for the power good signal circuit.
2	2	VGFX_PG	✅	Pin 2 connects to the VGFX_PG net, providing the necessary pull-up for the open-drain VR_RDY output from the voltage regulator.

C60 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Pin 1 connects to the VGFX_PG net, providing filtering and noise suppression for the power good signal.
2	2	GND	✅	Pin 2 connects to ground, completing the bypass capacitor circuit for filtering the power good signal.

R184 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Pin 1 connects to the VGFX_PG net, which is the power good signal from the voltage regulator. This pin is part of a 0 ohm jumper that allows the VR_RDY signal to be routed to the power good net.
2	2	$24N3598	✅	Pin 2 connects to net $24N3598, which is the VR_RDY output from U26 pin 6. This connection routes the voltage regulator ready signal through the jumper to the power good net.

C186 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3596	✅	Connected to R228 pin 2, forming the intermediate node in the bootstrap circuit.
2	2	$24N3595	✅	Connected to U26 SW1 pin (switch node). The bootstrap capacitor charges when the switch node is low.

R228 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3593	✅	Connected to U26 BST pin (bootstrap supply). This resistor limits inrush current to the bootstrap capacitor C186.
2	2	$24N3596	✅	Connected to C186 pin 1, forming the intermediate node between the bootstrap resistor and capacitor.

R846 - 1130-0193 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB power supply rail. This pin sources power for the VCCP supply of the voltage regulator controller U26.
2	2	$24N3578	✅	Connected to net $24N3578, which supplies the VCCP pin (pin 33) of U26 and is decoupled by C185. This provides the control power supply for the voltage regulator controller.

C185 - 2232-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3578	✅	Connected to net $24N3578, which is the VCCP supply for U26. This is the positive terminal of the decoupling capacitor.
2	2	GND	✅	Connected to GND. This is the negative terminal of the decoupling capacitor, providing the return path for the VCCP supply.

R229 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB power rail, providing input power to the VCC supply path for U26.
2	2	$24N3610	✅	Connected to net $24N3610, which feeds U26 pin 47 (VCC) and is bypassed by C53.

C53 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3610	✅	Connected to net $24N3610, providing bypass capacitance for U26's VCC pin.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX, providing the ground return path for the VCC bypass capacitor.

R203 - 1120-0351 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3542	✅	Pin 1 connects to the FREQ pin of U26 (NCP81109GMNTXG) to set the switching frequency. The nearby text note indicates the target frequency is 650 kHz.
2	2	AGND-VGFX	✅	Pin 2 connects to AGND-VGFX, which is the analog ground reference for the voltage regulator U26. This provides the correct ground reference for the frequency-setting resistor.

R201 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing an alternate ground reference path for the VSN sensing circuit.
2	2	$24N3528	✅	Connected to intermediate node $24N3528 in the VSN sensing path.

R202 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Connected to +VGFX output voltage, providing local voltage sensing capability.
2	2	VR-VGFX-VSP	✅	Connected to VSP sense pin of U26 through VR-VGFX-VSP net.

R68 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCCGT_SENSE	✅	Connected to VCCGT_SENSE, enabling remote voltage sensing at the load.
2	2	VR-VGFX-VSP	✅	Connected to VSP sense pin of U26 through VR-VGFX-VSP net.

R69 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the VSN sensing path.
2	2	$24N3528	✅	Connected to intermediate node $24N3528 in the VSN sensing path.

R169 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3528	✅	Connected to intermediate node $24N3528, which is tied to ground through R69 and R201.
2	2	VR-VGFX-VSN	✅	Connected to VSN sense pin of U26 through VR-VGFX-VSN net.

C61 - 2221-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR-VGFX-VSP	✅	DNI capacitor that would provide differential filtering across VSP and VSN if populated. Designer chose not to install this component.
2	2	VR-VGFX-VSN	✅	DNI capacitor that would provide differential filtering across VSP and VSN if populated. Designer chose not to install this component.

C104 - 2221-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3528	✅	DNI capacitor that would provide additional filtering on the VSN line if populated. Designer chose not to install this component.
2	2	VR-VGFX-VSN	✅	DNI capacitor that would provide additional filtering on the VSN line if populated. Designer chose not to install this component.

R66 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to the main power ground net GND. This is one side of the 0-ohm jumper that bridges analog and power grounds.
2	2	AGND-VGFX	✅	Pin 2 connects to the analog ground net AGND-VGFX. This is the other side of the 0-ohm jumper that bridges analog and power grounds.

R231 - 1141-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to the VGFX-SW switching node. This is the input to the RC snubber network.
2	2	$24N3623	✅	Connected to the intermediate node between R231 and C187, forming the RC snubber network.

C187 - 2240-0005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3623	✅	Connected to the intermediate node between R231 and C187, forming the capacitive element of the RC snubber.
2	2	GND	✅	Connected to ground, completing the RC snubber path from the switching node to ground.

R854 - 1130-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Pin 1 is connected to the +VGFX output rail of the DC/DC GFX regulator. This is the positive terminal of the minimum load resistor.
2	2	GND	✅	Pin 2 is connected to GND, forming a minimum load resistor from +VGFX to ground. This provides a discharge path and ensures minimum load for regulator stability.

C76 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	Positive terminal of bulk output capacitor connected to +VGFX output rail.
2	N	GND	✅	Negative terminal of bulk output capacitor connected to ground.

C77 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	Positive terminal of bulk output capacitor connected to +VGFX output rail, in parallel with C76.
2	N	GND	✅	Negative terminal of bulk output capacitor connected to ground.

U41 - RT8207 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
22	BOOT	$25N771	❌	BOOT pin is connected to the bootstrap circuit through a 4.7-ohm resistor (R298) and 0.1µF capacitor (C309) to PHASE. However, the bootstrap capacitor value is significantly undersized compared to the 1µF datasheet recommendation, which may cause insufficient gate drive voltage. Pin 22 (BOOT) is connected to net $25N771 (from schematic) DDR_BST connects to C309 pin 2 (0.1µF capacitor) (from schematic) C309 pin 1 connects to DDR_PHASE (PHASE pin) (from schematic) BOOT is the boost flying capacitor connection for VDDQ per the datasheet (from datasheet 4124-0013) The datasheet recommends a 1µF flying bootstrap capacitor between BOOT and PHASE pins (from datasheet 4124-0013) The schematic uses C309 (0.1µF) as the bootstrap capacitor, which is 10x smaller than recommended (reasoning) The datasheet mentions adding a resistor in series with BOOT to reduce gate-drain coupling in high current applications (from datasheet 4124-0013) The 4.7Ω resistor R298 is likely for reducing gate-drain coupling (reasoning) An undersized bootstrap capacitor may result in insufficient gate drive voltage, increased switching losses, or potential shoot-through issues (reasoning) The bootstrap capacitor should be increased to 1µF as recommended by the datasheet (reasoning)
1	VTTGND	GND	✅	VTTGND is correctly connected to ground plane, providing power ground return for the VTT LDO.
2	VTTSNS	+VDIMM_VTT	✅	VTTSNS is correctly connected to the VTT output rail (+VDIMM_VTT) for remote voltage sensing of the VTT LDO output.
3	GND	GND	✅	GND pin is correctly connected to ground plane for analog ground reference.
4	MODE	GND	✅	MODE pin is connected to ground, which may configure a specific operating mode for the controller.
5	VTTREF	$25N769	✅	VTTREF is correctly connected to a bypass capacitor (C342, 0.22µF) to ground, providing the buffered reference output for VTT regulation.
6	DEM	$25N1291	✅	DEM pin is connected to a 10K pullup resistor to +5VSB, likely configuring diode emulation mode operation.
8	VDDQ	+VDIMM	✅	VDDQ pin is correctly connected to the VDDQ output rail (+VDIMM), providing the reference input for VTT/VTTREF and feedback for VDDQ output.
9	FB	$25N987	✅	FB pin is correctly connected to a resistive voltage divider (R814: 8.06K, R815: 10K) with compensation capacitor (C382: 22pF) to set VDDQ output voltage to approximately 1.35V for DDR3L operation.
10	S3	EN_VTT	✅	S3 pin is correctly connected to the EN_VTT signal through a 0-ohm resistor (R302) from SLP_S3_L, controlling VTT enable state.
11	S5	EN_VDDQ	✅	S5 pin is correctly connected to the EN_VDDQ signal through a 0-ohm resistor (R300) from SLP_S4_L, controlling VDDQ enable state.
12	TON	$25N1081	✅	TON pin is correctly connected to a 464K resistor (R816) to +5VSB to set the on-time and switching frequency. The actual frequency (~500kHz) differs from a schematic note mentioning 285kHz with 806K, but this appears intentional for the design.
13	PGOOD	DRAM_PWROK	✅	PGOOD pin is correctly connected to DRAM_PWROK with a 10K pullup resistor to +VDIMM, providing power good indication as an open-drain output.
14	VDD	$25N1195	✅	VDD pin is correctly connected to a filtered supply from +5VSB through a 2.2-ohm resistor (R813) with 1µF bypass capacitor (C380), providing analog supply voltage.
15	VDDP	+5VSB	✅	VDDP pin is correctly connected to +5VSB rail with bypass capacitors, providing supply voltage for the LGATE gate driver.
16	CS	$25N1238	✅	CS pin is correctly connected to a 3.83K resistor (R817) to VDD to set the current limit threshold. The value differs from the typical 6K but appears intentional for the 11A overcurrent protection requirement.
18	PGND	GND	✅	PGND pin is correctly connected to ground plane and the source pins of the low-side MOSFET (Q102), providing power ground for the switching circuit.
19	LGATE	$25N901	✅	LGATE pin is correctly connected to the low-side MOSFET gate (Q102 pin 8), providing the gate drive signal for the synchronous rectifier.
20	PHASE	DDR_PHASE	✅	PHASE pin is correctly connected to the switching node, connecting to the MOSFET switch node (Q102 pin 9), output inductor (L11), and bootstrap capacitor (C309).
21	UGATE	$25N897	✅	UGATE pin is correctly connected to the high-side MOSFET gate (Q102 pin 1), providing the gate drive signal for the main switch.
23	VLDOIN	+VDIMM	✅	VLDOIN pin is correctly connected to the +VDIMM output rail, enabling tracking discharge mode operation where VTT tracks VDDQ during shutdown.
24	VTT	+VDIMM_VTT	✅	VTT pin is correctly connected to the +VDIMM_VTT output rail with output capacitors (C361, C362: 10µF each, C343: 0.1µF), meeting the minimum 20µF requirement.
25	GND_PAD	GND	✅	GND_PAD (exposed pad) is correctly connected to ground plane for thermal dissipation and electrical grounding.

Q102 - FDMS3604S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	Q1G	$25N897	✅	Q1G (upper MOSFET gate) is correctly connected to UGATE output from controller U41 for high-side gate drive.
2	VIN_A	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (upper MOSFET drain pins) are correctly connected to DDR3L_VIN input rail with appropriate input capacitance.
3	VIN_B	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (upper MOSFET drain pins) are correctly connected to DDR3L_VIN input rail with appropriate input capacitance.
4	VIN_C	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (upper MOSFET drain pins) are correctly connected to DDR3L_VIN input rail with appropriate input capacitance.
5	PGND_A	GND	✅	PGND_A, PGND_B, PGND_C (lower MOSFET source pins) are correctly connected to GND for power ground return.
6	PGND_B	GND	✅	PGND_A, PGND_B, PGND_C (lower MOSFET source pins) are correctly connected to GND for power ground return.
7	PGND_C	GND	✅	PGND_A, PGND_B, PGND_C (lower MOSFET source pins) are correctly connected to GND for power ground return.
8	Q2G	$25N901	✅	Q2G (lower MOSFET gate) is correctly connected to LGATE output from controller U41 for low-side gate drive.
9	PHASE	DDR_PHASE	✅	PHASE (switch node) is correctly connected to the output inductor L11 and bootstrap capacitor C309, with feedback to controller U41.

L5 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to the +5VSB standby power rail, serving as the input side of the ferrite bead filter.
2	2	DDR3L_VIN	✅	Pin 2 is connected to the DDR3L_VIN net, serving as the output side of the ferrite bead filter that supplies the DDR power converter input.

L6 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to the +5VSB standby power rail, serving as the input side of the ferrite bead filter in parallel with L5.
2	2	DDR3L_VIN	✅	Pin 2 is connected to the DDR3L_VIN net, serving as the output side of the ferrite bead filter in parallel with L5.

L11 - 125-0004454 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_PHASE	✅	Pin 1 connects to the switching node DDR_PHASE, which is the output of the buck converter switching stage before filtering. This is the correct connection for the input side of an output filter inductor.
2	2	+VDIMM	✅	Pin 2 connects to the filtered output voltage rail +VDIMM. This is the correct connection for the output side of a buck converter filter inductor.

R814 - 1120-0187 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Upper feedback resistor connected from output voltage +VDIMM to feedback node. This connection is correct.
2	2	$25N987	✅	Connected to feedback node $25N987. See pin 1 analysis.

R815 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N987	✅	Lower feedback resistor connected from feedback node to ground. This connection is correct.
2	2	GND	✅	Connected to ground. See pin 1 analysis.

C382 - 2220-0047 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Compensation capacitor connected in parallel with upper feedback resistor R814. This connection is correct.
2	2	$25N987	✅	Connected to feedback node $25N987. See pin 1 analysis.

R300 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SLP_S4_L	✅	0 ohm jumper connecting SLP_S4_L to EN_VDDQ, routing the S4 sleep state signal to control the VDDQ rail enable (S5 pin of U41).
2	2	EN_VDDQ	✅	0 ohm jumper connecting SLP_S4_L to EN_VDDQ, routing the S4 sleep state signal to control the VDDQ rail enable (S5 pin of U41).

R293 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DRAM_S4_PWROK	✅	0 ohm jumper connecting DRAM_S4_PWROK to DRAM_PWROK, routing the power good signal from the intermediate node to the final output.
2	2	DRAM_PWROK	✅	0 ohm jumper connecting DRAM_S4_PWROK to DRAM_PWROK, routing the power good signal from the intermediate node to the final output.

R302 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SLP_S3_L	✅	0 ohm jumper connecting SLP_S3_L to EN_VTT, routing the S3 sleep state signal to control the VTT rail enable (S3 pin of U41).
2	2	EN_VTT	✅	0 ohm jumper connecting SLP_S3_L to EN_VTT, routing the S3 sleep state signal to control the VTT rail enable (S3 pin of U41).

R124 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DRAM_S4_PWROK	✅	10K pull-up resistor connecting DRAM_S4_PWROK to +VDIMM, providing pull-up for the power good signal from U41 pin 13.
2	2	+VDIMM	✅	10K pull-up resistor connecting DRAM_S4_PWROK to +VDIMM, providing pull-up for the power good signal from U41 pin 13.

R816 - 1120-0149 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
2	2	$25N1081	❌	Connected to U41 pin 12 (TON) to set switching frequency. However, the resistor value of 464K does not match the design specification of 806K stated in the schematic notes, which would result in incorrect switching frequency (504 kHz instead of the intended 285 kHz). Pin 2 is connected to net $25N1081, which connects to U41 pin 12 (TON) (from schematic) The TON pin sets the switching frequency of the RT8207M controller via an external resistor (reasoning) A schematic note states 'Rton=806K , F=285KHz' indicating the design intent for switching frequency (from schematic) A schematic note provides the formula 'F= (Vin - 0.5) / 3.85pVinRton' for calculating switching frequency (from schematic) R816 is specified as 464K (part number 1120-0149) (from schematic) Using the provided formula with Vin=5V and Rton=464K yields F = (5-0.5)/(3.85e-125464000) = 503.8 kHz (reasoning) Using the provided formula with Vin=5V and Rton=806K yields F = (5-0.5)/(3.85e-125806000) = 290 kHz, which matches the design specification of 285 kHz (reasoning) The resistor value of 464K does not match the design specification of 806K, resulting in a switching frequency approximately 1.74x higher than intended (reasoning) R816 should be changed to 806K (or nearest standard value) to achieve the intended 285 kHz switching frequency (reasoning)
1	1	+5VSB	✅	Connected to +5VSB supply rail. This pin provides the reference voltage for the TON timing resistor that sets the switching frequency of the RT8207M controller.

R817 - 1120-0267 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	Connected to net $25N1195 which supplies U41 pin 14 (VDD). This pin is part of the current sense and VDD supply network for the RT8207M controller.
2	2	$25N1238	✅	Connected to U41 pin 16 (CS - Current Sense). This pin provides current sense signal conditioning for the RT8207M controller.

R813 - 110-0004466 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	Connected to net $25N1195 which supplies U41 pin 14 (VDD). This pin is the load side of the current sense resistor.
2	2	+5VSB	✅	Connected to +5VSB supply rail. This pin is the source side of the current sense resistor that monitors input current to the RT8207M controller.

C379 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for decoupling capacitor. This pin is correctly connected to the GND net.
2	2	+5VSB	✅	Connected to +5VSB rail for bulk decoupling. This pin is correctly connected to provide input supply decoupling for the DDR power circuit.

C380 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for decoupling capacitor. This pin is correctly connected to the GND net.
2	2	$25N1195	✅	Connected to VDD supply net ($25N1195) for local decoupling of U41. This pin is correctly connected to provide decoupling for the controller IC's internal logic supply.

U21 - APL5933 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P8S_PGD	✅	PGOOD output is pulled up to the output voltage (+V1P8S) through R23 (4.7K). This is a valid configuration for an open-drain power good output.
2	EN	+V1P8S_EN	✅	EN pin is connected to the enable signal through R22 (0 ohm jumper). The enable signal includes sequencing logic to ensure the 1.35V rail is stable before enabling this 1.8V regulator.
3	VIN	+PS_3VSB	✅	VIN and VDD pins are both connected to +PS_3VSB (3.3V standby supply). This is correct as both pins typically need to be connected to the input supply.
4	VDD	+PS_3VSB	✅	VIN and VDD pins are both connected to +PS_3VSB (3.3V standby supply). This is correct as both pins typically need to be connected to the input supply.
5	NC		✅	NC pin has no connection, which is correct for a no-connect pin.
6	VOUT	+V1P8S	✅	VOUT pin is connected to +V1P8S output rail with appropriate output capacitors for filtering and stability.
7	ADJ	+V1P8S_FB	✅	ADJ pin is connected to a feedback divider formed by R24 (12.1K) and R25 (9.53K) that sets the output voltage to approximately 1.8V.
8	GND1	GND	✅	GND1 and GND2 pins are both properly connected to ground. Multiple ground pins are common in power ICs for thermal and electrical performance.
9	GND2	GND	✅	GND1 and GND2 pins are both properly connected to ground. Multiple ground pins are common in power ICs for thermal and electrical performance.

R25 - 110-0004490 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	R25 (9.53K) is the lower resistor (R2) in the feedback divider that sets the output voltage to 1.8V.
2	2	+V1P8S_FB	✅	R25 (9.53K) is the lower resistor (R2) in the feedback divider that sets the output voltage to 1.8V.

R24 - 110-0002560 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	R24 (12.1K) is the upper resistor (R1) in the feedback divider that sets the output voltage to 1.8V.
2	2	+V1P8S_FB	✅	R24 (12.1K) is the upper resistor (R1) in the feedback divider that sets the output voltage to 1.8V.

R23 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	R23 (4.7K) is a pull-up resistor for the power good signal, pulling it to the output voltage (1.8V).
2	2	+V1P8S_PGD	✅	R23 (4.7K) is a pull-up resistor for the power good signal, pulling it to the output voltage (1.8V).

R22 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1P8V_EN	✅	R22 (0 ohm) is a jumper connecting the enable signal from the sequencing circuit to the LDO enable pin.
2	2	+V1P8S_EN	✅	R22 (0 ohm) is a jumper connecting the enable signal from the sequencing circuit to the LDO enable pin.

R135 - 110-0004498 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower feedback resistor correctly connected to ground.
2	2	FB_V1P0S	✅	Upper terminal correctly connected to feedback node.

R136 - 110-0002029 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FB_V1P0S	✅	Lower terminal correctly connected to feedback node.
2	2	+V1P0S	✅	Upper feedback resistor correctly connected to output voltage.

R320 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCNTL_V1P0S	✅	Connected to VCNTL pin of U38. Connection appears intentional but cannot be fully verified without datasheet.
2	2	+VCC	✅	Connected to +VCC rail. 10 ohm value suggests current limiting or isolation function.

R319 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	Connected to power good output of U38.
2	2	+VCC	✅	Pullup resistor correctly connected to +VCC for power good signal.

U38 - APL5912KAC-TRGS-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	GND pin correctly connected to ground plane.
2	FB	FB_V1P0S	✅	FB pin correctly connected to feedback divider network consisting of R135 (143K to GND), R136 (40.2K to VOUT), and C119 (27pF compensation capacitor).
3	VOUT-2	+V1P0S	✅	VOUT-2 and VOUT-1 pins correctly connected to +V1P0S output rail with adequate output capacitance (76uF total).
4	VOUT-1	+V1P0S	✅	VOUT-2 and VOUT-1 pins correctly connected to +V1P0S output rail with adequate output capacitance (76uF total).
5	VIN-2	+VDIMM	✅	VIN-2 and VIN-1 pins correctly connected to +VDIMM input rail with adequate input capacitance (20uF total).
9	VIN-1	+VDIMM	✅	VIN-2 and VIN-1 pins correctly connected to +VDIMM input rail with adequate input capacitance (20uF total).
6	VCNTL	VCNTL_V1P0S	✅	VCNTL pin connected to +VCC through R320 (10 ohm) with C117 (1uF) to ground. Without datasheet, this connection cannot be fully verified but appears to be a control voltage input.
7	POK	V1P0S_PG	✅	POK (power good) pin correctly connected to V1P0S_PG with R319 (10K) pull-up to +VCC.
8	EN	1P0V_EN	✅	EN (enable) pin correctly connected to 1P0V_EN signal for power sequencing. Schematic note indicates enable threshold > 0.5V.

R32 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Enable pull-up resistor correctly connected between +5VSB and enable pin. The 4.7K value pulls the enable pin to 5V, well above the 1.1V threshold.
2	2	+V1P0A_ENABLE	✅	Enable pull-up resistor correctly connected between +5VSB and enable pin. The 4.7K value pulls the enable pin to 5V, well above the 1.1V threshold.

R33 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB	✅	Power good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin. The 4.7K value provides standard pull-up for open-drain power good output.
2	2	+V1P0A_PWRGD	✅	Power good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin. The 4.7K value provides standard pull-up for open-drain power good output.

R34 - 110-0003781 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Upper feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and output voltage (+V1P0A). The 6.04K value sets the output to 1.004V.
2	2	+V1P0A	✅	Upper feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and output voltage (+V1P0A). The 6.04K value sets the output to 1.004V.

U24 - APL5933 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P0A_PWRGD	✅	PGOOD pin correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB. This provides open-drain power good signaling to downstream circuits.
2	EN	+V1P0A_ENABLE	✅	EN pin correctly connected to +V1P0A_ENABLE net with pull-up resistor R32 to +5VSB. The enable threshold is >1.1V per schematic notes, and the 5V pull-up easily meets this requirement.
3	VIN	+PS_3VSB	✅	VIN pin correctly connected to +PS_3VSB input power rail with appropriate input filtering capacitors.
4	VDD	+PS_3VSB	✅	VDD pin correctly connected to +PS_3VSB input power rail, same as VIN pin.
5	NC		✅	NC pin correctly left unconnected as specified by the pin name.
6	VOUT	+V1P0A	✅	VOUT pin correctly connected to +V1P0A output rail with appropriate output filtering capacitors C22 (0.1uF) and C21 (22uF).
7	ADJ	+V1P0A_FB	✅	ADJ pin correctly connected to feedback network consisting of R34 (6.04K to VOUT) and R35 (23.7K to GND). This sets output voltage to 1.004V, matching the 1.0V target.
8	GND1	GND	✅	GND1 and GND2 pins correctly connected to ground plane.
9	GND2	GND	✅	GND1 and GND2 pins correctly connected to ground plane.

R35 - 110-0004494 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Lower feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and ground. The 23.7K value works with R34 to set the output to 1.004V.
2	2	GND	✅	Lower feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and ground. The 23.7K value works with R34 to set the output to 1.004V.

U20 - 140-0004677 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN1	+PS_3VSB	✅	VIN1 and VIN2 pins are both correctly connected to +PS_3VSB input supply. The datasheet requires both pins to be connected together externally for full output current range operation.
6	VIN2	+PS_3VSB	✅	VIN1 and VIN2 pins are both correctly connected to +PS_3VSB input supply. The datasheet requires both pins to be connected together externally for full output current range operation.
2	GND	GND	✅	GND and GND_PAD pins are both correctly connected to the GND net for power supply ground and thermal relief.
7	GND_PAD	GND	✅	GND and GND_PAD pins are both correctly connected to the GND net for power supply ground and thermal relief.
3	EN	+V1P8A_EN	✅	EN pin is correctly connected to +V1P8A_EN, which is controlled by the power good signal from U24 (+V1P0A_PWRGD) through R151 (0 ohm). This implements power sequencing where +V1P8A is enabled after +V1P0A is stable.
4	VOUT	+V1P8A	✅	VOUT pin is correctly connected to +V1P8A output net with appropriate decoupling capacitor C151 (10uF), which exceeds the datasheet minimum requirement of 1.0uF.
5	SENSE/ADJ	+V1P8A_FB	✅	SENSE/ADJ pin is correctly connected to the feedback network consisting of R150 (12.1K) to VOUT and R153 (27.4K) to GND, which sets the output voltage to approximately 1.802V (target 1.8V).

R153 - 110-0002726 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	R153 (27.4K ohm) is correctly configured as R2 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to ground.
2	2	GND	✅	R153 (27.4K ohm) is correctly configured as R2 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to ground.

R150 - 110-0002560 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	R150 (12.1K ohm) is correctly configured as R1 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to the output voltage (+V1P8A).
2	2	+V1P8A	✅	R150 (12.1K ohm) is correctly configured as R1 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to the output voltage (+V1P8A).

R151 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	R151 (0 ohm) is correctly configured to connect the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN), implementing power sequencing.
2	2	+V1P8A_EN	✅	R151 (0 ohm) is correctly configured to connect the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN), implementing power sequencing.

Q5 - RXR035N03 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+VDIMM	✅	Drain is correctly connected to +VDIMM input rail for high-side switch configuration.
G	GATE	1P35V_EN	✅	Gate is driven by V1P0S_PG through R134 (1kΩ) to enable the switch. Gate drive voltage may be marginal depending on +VCC voltage; designer notes indicate VGS should exceed 2V for proper operation.
S	SOURCE	+V1P35S	✅	Source is correctly connected to +V1P35S output rail for high-side switch configuration.

R134 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	1kΩ resistor correctly connects V1P0S_PG power good signal to Q5 gate, providing appropriate gate drive current limiting.
2	2	1P35V_EN	✅	1kΩ resistor correctly connects V1P0S_PG power good signal to Q5 gate, providing appropriate gate drive current limiting.

R120 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	10kΩ resistor correctly connects V1P35S output to Q3 base for power good sensing, providing appropriate base current.
2	2	1P35V_PWG	✅	10kΩ resistor correctly connects V1P35S output to Q3 base for power good sensing, providing appropriate base current.

R60 - 110-0001957 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB	✅	20K pull-up resistor from +PS_3VSB to PSPUP, providing pull-up for Q1 transistor 1 collector output.
2	2	PSPUP	✅	20K pull-up resistor from +PS_3VSB to PSPUP, providing pull-up for Q1 transistor 1 collector output.

R61 - 110-0001957 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	20K pull-up resistor from +VCC3 to SYS_PWRGD, providing pull-up for Q1 transistor 2 collector output.
2	2	SYS_PWRGD	✅	20K pull-up resistor from +VCC3 to SYS_PWRGD, providing pull-up for Q1 transistor 2 collector output.

R206 - 110-0001951 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PSGOOD	✅	200K pull-up resistor from +V1P8S to PSGOOD, working with C44 (1uF) to create approximately 200ms delay that meets the >100ms requirement noted on the schematic.
2	2	+V1P8S	✅	200K pull-up resistor from +V1P8S to PSGOOD, working with C44 (1uF) to create approximately 200ms delay that meets the >100ms requirement noted on the schematic.

R125 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	4.7K pull-up resistor from +VCC to 1P8V_EN, providing pull-up for Q3 transistor 2 collector output.
2	2	1P8V_EN	✅	4.7K pull-up resistor from +VCC to 1P8V_EN, providing pull-up for Q3 transistor 2 collector output.

R126 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	4.7K pull-up resistor from +5VSB to 1P5V_EN_B, providing pull-up for Q3 transistor 1 collector output.
2	2	1P5V_EN_B	✅	4.7K pull-up resistor from +5VSB to 1P5V_EN_B, providing pull-up for Q3 transistor 1 collector output.

Q1 - 132-0004425 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter of first NPN transistor (E1) correctly connected to ground for common-emitter configuration.
2	B1	PSGOOD	✅	Base of first NPN transistor (B1) connected to PSGOOD signal, which controls the first stage of the power sequencing circuit.
3	C2	SYS_PWRGD	✅	Collector of second NPN transistor (C2) connected to SYS_PWRGD output signal, which is the final output of the two-stage buffer.
4	E2	GND	✅	Emitter of second NPN transistor (E2) correctly connected to ground for common-emitter configuration.
5	B2	PSPUP	✅	Base of second NPN transistor (B2) connected to PSPUP signal, which is the intermediate signal between the two transistor stages.
6	C1	PSPUP	✅	Collector of first NPN transistor (C1) connected to PSPUP signal, which is the output of the first stage and input to the second stage.

Q3 - 132-0004425 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter of first NPN transistor (E1) correctly connected to ground for common-emitter configuration.
2	B1	1P35V_PWG	✅	Base of first NPN transistor (B1) connected to 1P35V_PWG power good signal, which initiates the power sequencing.
3	C2	1P8V_EN	✅	Collector of second NPN transistor (C2) connected to 1P8V_EN enable signal, which is the final output enabling the 1.8V rail.
4	E2	GND	✅	Emitter of second NPN transistor (E2) correctly connected to ground for common-emitter configuration.
5	B2	1P5V_EN_B	✅	Base of second NPN transistor (B2) connected to 1P5V_EN_B signal, which is the intermediate signal between the two transistor stages.
6	C1	1P5V_EN_B	✅	Collector of first NPN transistor (C1) connected to 1P5V_EN_B signal, which is the output of the first stage and input to the second stage.

D11 - 130-0004403 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	Anode 1 of dual Schottky diode connected to +V1P0A_PWRGD signal, one input of the diode AND gate.
2	2	SLP_S3_L	✅	Anode 2 of dual Schottky diode connected to SLP_S3_L signal, the second input of the diode AND gate.
3	3	PSGOOD	✅	Common cathode of dual Schottky diode connected to PSGOOD signal, the output of the diode AND gate.

FB7 - 110-0002124 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Input pin connected to +VCC3 power rail. This is the source side of the 0-ohm jumper that feeds the +VCC3S CPU power rail.
2	2	+VCC3S	✅	Output pin connected to +VCC3S power rail. This feeds the CPU power rail with appropriate decoupling capacitor C247.

R306 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_GFX_PG	✅	Pin 1 connects to VCORE_GFX_PG, which is a power good signal from a graphics core voltage regulator used for power sequencing.
2	2	1P0V_EN	✅	Pin 2 connects to 1P0V_EN, which is the enable signal for U38, a 5A LDO regulator generating +V1P0S.

📤 Upload Missing Datasheets

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• R127, R128, R129, R130, R151, R18, R192, R20, R216, R22, R293, R300, R302, R306, R354, R48, R5, R51, R72, R73, R74, R809 (110-0001853): 📤 Upload a datasheet
• R147 (110-0001859): 📤 Upload a datasheet
• R116, R120, R124, R13, R14, R163, R164, R165, R189, R190, R191, R2, R209, R210, R211, R219, R220, R221, R260, R266, R267, R268, R28, R29, R30, R319, R400, R71, R810 (110-0001875): 📤 Upload a datasheet
• R134, R15, R16, R17, R208, R233, R234, R259, R401, R6, R7 (110-0001923): 📤 Upload a datasheet
• R206, R812 (110-0001951): 📤 Upload a datasheet
• R3 (110-0001954): 📤 Upload a datasheet
• R60, R61 (110-0001957): 📤 Upload a datasheet
• R179 (110-0001960): 📤 Upload a datasheet
• R11, R12, R269, R270 (110-0001967): 📤 Upload a datasheet
• R171, R172 (110-0001984): 📤 Upload a datasheet
• R136 (110-0002029): 📤 Upload a datasheet
• R125, R126, R23, R32, R33 (110-0002058): 📤 Upload a datasheet
• R21 (110-0002078): 📤 Upload a datasheet
• FB7, R152, R222, R265, R275, R818 (110-0002124): 📤 Upload a datasheet
• R150, R24 (110-0002560): 📤 Upload a datasheet
• R153 (110-0002726): 📤 Upload a datasheet
• R240, R241, R242, R258 (110-0003059): 📤 Upload a datasheet
• R34 (110-0003781): 📤 Upload a datasheet
• R813 (110-0004466): 📤 Upload a datasheet
• R298 (110-0004467): 📤 Upload a datasheet
• R185, R77 (110-0004472): 📤 Upload a datasheet
• R255 (110-0004474): 📤 Upload a datasheet
• R218, R239 (110-0004476): 📤 Upload a datasheet
• R212 (110-0004478): 📤 Upload a datasheet
• R25 (110-0004490): 📤 Upload a datasheet
• R35 (110-0004494): 📤 Upload a datasheet
• R135 (110-0004498): 📤 Upload a datasheet
• R832, R833, R834, R835 (1120-0003): 📤 Upload a datasheet
• R837, R838, R839 (1120-0010): 📤 Upload a datasheet
• R815, R820, R821, R822, R823, R824, R825, R826, R827, R828, R830, R831 (1120-0011): 📤 Upload a datasheet
• R836 (1120-0018): 📤 Upload a datasheet
• R320 (1120-0022): 📤 Upload a datasheet
• R801, R802, R803, R804, R805, R806, R807, R808 (1120-0119): 📤 Upload a datasheet
• R816 (1120-0149): 📤 Upload a datasheet
• R814 (1120-0187): 📤 Upload a datasheet
• R843, R844 (1120-0203): 📤 Upload a datasheet
• R817 (1120-0267): 📤 Upload a datasheet
• R848 (1120-0359): 📤 Upload a datasheet
• R840, R841, R842 (1121-0001): 📤 Upload a datasheet
• C1, C205, C206, C207, C208, C309, C375, C5 (123-0001056): 📤 Upload a datasheet
• C2, C379, C380 (123-0001066): 📤 Upload a datasheet
• C252, C253 (123-0001107): 📤 Upload a datasheet
• C342 (123-0003769): 📤 Upload a datasheet
• C76, C77, C87 (123-0005035): 📤 Upload a datasheet
• L11 (125-0004454): 📤 Upload a datasheet
• L3 (125-0004501): 📤 Upload a datasheet
• FB3 (126-0001423): 📤 Upload a datasheet
• FB1, FB11, FB4, FB5, L12, L13, L5, L6 (126-0004457): 📤 Upload a datasheet
• D11, D3 (130-0004403): 📤 Upload a datasheet
• U38 (140-0004525): 📤 Upload a datasheet
• U21, U24 (140-0004526): 📤 Upload a datasheet
• Y1 (145-0004789): 📤 Upload a datasheet
• X1, Y2 (145-0004792): 📤 Upload a datasheet
• P2 (158-0001269): 📤 Upload a datasheet
• P1 (158-0004513): 📤 Upload a datasheet
• J10 (158-0004534): 📤 Upload a datasheet
• C429, C430, C431 (2220-0039): 📤 Upload a datasheet
• C382 (2220-0047): 📤 Upload a datasheet
• C425 (2221-0017): 📤 Upload a datasheet
• C428 (2222-0014): 📤 Upload a datasheet
• C408, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C426, C427 (2222-0016): 📤 Upload a datasheet
• C419, C420, C421, C422, C423, C424 (2232-0012): 📤 Upload a datasheet
• J5, J6, J7 (258-0002513): 📤 Upload a datasheet
• USB1 (258-0004503): 📤 Upload a datasheet
• J2 (258-0004524): 📤 Upload a datasheet
• J1 (258-0004612): 📤 Upload a datasheet
• J4 (258-0004869): 📤 Upload a datasheet
• JP1 (258-0005019): 📤 Upload a datasheet
• FB12 (3044-0010): 📤 Upload a datasheet
• FB13 (3044-0012): 📤 Upload a datasheet
• L8 (3120-0183): 📤 Upload a datasheet
• L18, L4 (3120-0266): 📤 Upload a datasheet
• CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17 (3142-0014): 📤 Upload a datasheet
• J11 (3362-0042): 📤 Upload a datasheet
• J8 (3430-0212): 📤 Upload a datasheet
• BH1 (353-0003073): 📤 Upload a datasheet
• FL1 (3750-0010): 📤 Upload a datasheet
• SW1 (3770-0026): 📤 Upload a datasheet
• TH1, TH2, TH3, TH4 (3880-0004): 📤 Upload a datasheet
• U18 (4327-0008): 📤 Upload a datasheet
• U5, U6, U7 (4327-0009): 📤 Upload a datasheet
• U10, U14, U15, U16, U17, U19 (4327-0010): 📤 Upload a datasheet
• D10, D5, D8 (4536-0009): 📤 Upload a datasheet
• D1, D2 (4560-0045): 📤 Upload a datasheet
• D13 (4620-0026): 📤 Upload a datasheet
• TP11, TP12 (999-0000002): 📤 Upload a datasheet
• TP17, TP18 (999-0000003): 📤 Upload a datasheet
• SP1, SP2 (999-0000005): 📤 Upload a datasheet
• D4, D6 (BAT54A-S): 📤 Upload a datasheet
• Q2, Q9 (BAV99-7-F-S-X): 📤 Upload a datasheet
• L1, L2 (BKP2125HS221-T): 📤 Upload a datasheet
• U33 (M24C02-WMN6TP-X): 📤 Upload a datasheet
• U25, U26 (NCP81109GMNTXG): 📤 Upload a datasheet
• U35 (NCT3012S-X): 📤 Upload a datasheet
• U4 (NTS0102GT): 📤 Upload a datasheet
• U29 (TPD4USB30): 📤 Upload a datasheet
• U42 (WGI210AT): 📤 Upload a datasheet

_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 413 component(s) to review, and found 11 potential issue(s) in 13 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary><b>Component Details</b></summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AK12 | DDI0_RCOMP_P | DDI_RCOMP_N | ❌ | <details><summary>DDI0_RCOMP differential pair pins are swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative signal) connects to net DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P indicating positive signal) connects to net DDI_RCOMP_N. These connections are reversed from what they should be.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,31.55,45.57,39.05" aspect-ratio="1.29" } <ul><li>Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in both the schematic and datasheet <em>(from schematic)</em></li><li>Pin AK12 is labeled DDI0_RCOMP_P with _P suffix indicating positive signal in both the schematic and datasheet <em>(from schematic)</em></li><li>Pin AK13 connects to net DDI_RCOMP_P in the schematic <em>(from schematic)</em></li><li>Pin AK12 connects to net DDI_RCOMP_N in the schematic <em>(from schematic)</em></li><li>Compensation resistor R217 (402 ohm, 1%) correctly connects between nets DDI_RCOMP_N and DDI_RCOMP_P <em>(from schematic)</em></li><li>The datasheet identifies pin AK13 as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (with overline) <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>The datasheet identifies pin AK12 as DDI0_RCOMP_P <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>In differential signaling and pin naming conventions, overline notation indicates the negative or inverted signal <em>(reasoning)</em></li><li>The _P suffix in pin names conventionally indicates the positive signal in a differential pair <em>(reasoning)</em></li><li>Pin AK13 with overline should connect to DDI_RCOMP_N (negative net), not DDI_RCOMP_P <em>(reasoning)</em></li><li>Pin AK12 with _P suffix should connect to DDI_RCOMP_P (positive net), not DDI_RCOMP_N <em>(reasoning)</em></li><li>The nets should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P <em>(reasoning)</em></li></ul></details> | | AK13 | ~DDI0_RCOMP | DDI_RCOMP_P | ❌ | <details><summary>DDI0_RCOMP differential pair pins are swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative signal) connects to net DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P indicating positive signal) connects to net DDI_RCOMP_N. These connections are reversed from what they should be.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,38.46" aspect-ratio="1.29" } <ul><li>Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in both the schematic and datasheet <em>(from schematic)</em></li><li>Pin AK12 is labeled DDI0_RCOMP_P with _P suffix indicating positive signal in both the schematic and datasheet <em>(from schematic)</em></li><li>Pin AK13 connects to net DDI_RCOMP_P in the schematic <em>(from schematic)</em></li><li>Pin AK12 connects to net DDI_RCOMP_N in the schematic <em>(from schematic)</em></li><li>Compensation resistor R217 (402 ohm, 1%) correctly connects between nets DDI_RCOMP_N and DDI_RCOMP_P <em>(from schematic)</em></li><li>The datasheet identifies pin AK13 as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (with overline) <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>The datasheet identifies pin AK12 as DDI0_RCOMP_P <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>In differential signaling and pin naming conventions, overline notation indicates the negative or inverted signal <em>(reasoning)</em></li><li>The _P suffix in pin names conventionally indicates the positive signal in a differential pair <em>(reasoning)</em></li><li>Pin AK13 with overline should connect to DDI_RCOMP_N (negative net), not DDI_RCOMP_P <em>(reasoning)</em></li><li>Pin AK12 with _P suffix should connect to DDI_RCOMP_P (positive net), not DDI_RCOMP_N <em>(reasoning)</em></li><li>The nets should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P <em>(reasoning)</em></li></ul></details> | | A29 | RESERVED_A29 | GPIO_NC13 | ✅ | RESERVED_A29 pin connected to GPIO_NC13 with 10K pull-down resistor to ground. This configuration prevents the pin from floating when not actively driven. | | B26 | DDI0_BKLTCTL | | ✅ | DDI0_BKLTCTL backlight control signal has no net connection. This is acceptable as backlight control may be handled externally or not required for HDMI. | | B28 | DDI0_VDDEN | | ✅ | DDI0_VDDEN display power enable signal has no net connection. This is acceptable as display power may be handled externally or not required for HDMI. | | B30 | GPIO_S0_NC12 | $3N566 | ✅ | GPIO_S0_NC12 pin connected to test point TP15 and pulled down to ground through 10K resistor R102. This provides a test point with proper pull-down to prevent floating. | | C26 | DDI0_DDCDATA | HDMI_DDCDAT | ✅ | DDI0_DDCDATA connects to HDMI_DDCDAT, providing the I2C data line for HDMI DDC communication. This allows the system to read EDID from the HDMI display. | | C27 | DDI0_BKLTEN | | ✅ | DDI0_BKLTEN backlight enable signal has no net connection. This is acceptable as backlight enable may be handled externally or not required for HDMI. | | C28 | DDI0_DDCCLK | HDMI_DDCCLK | ✅ | DDI0_DDCCLK connects to HDMI_DDCCLK, providing the I2C clock line for HDMI DDC communication. This allows the system to read EDID from the HDMI display. | | C29 | RESERVED_C29 | | ✅ | RESERVED_C29 pin has no net connection. Reserved pins without specific function can be left unconnected. | | C30 | RESERVED_C30 | | ✅ | RESERVED_C30 pin has no net connection. Reserved pins without specific function can be left unconnected. | | D27 | DDI0_HPD | HDMI_HPD_B | ✅ | DDI0_HPD connects to HDMI_HPD_B, which is the inverted output from Schmitt trigger inverter U39. The inverter receives HDMI_HPD and provides noise immunity for the hot plug detect signal. | | D28 | RESERVED_D28 | | ✅ | RESERVED_D28 pin has no net connection. Reserved pins without specific function can be left unconnected. | | D32 | RESERVED_D32 | | ✅ | RESERVED_D32 pin has no net connection. Reserved pins without specific function can be left unconnected. | | D34 | RESERVED_D34 | | ✅ | RESERVED_D34 pin has no net connection. Reserved pins without specific function can be left unconnected. | | F28 | RESERVED_F28 | | ✅ | RESERVED_F28 pin has no net connection. Reserved pins without specific function can be left unconnected. | | F32 | RESERVED_F32 | | ✅ | RESERVED_F32 pin has no net connection. Reserved pins without specific function can be left unconnected. | | F34 | RESERVED_F34 | | ✅ | RESERVED_F34 pin has no net connection. Reserved pins without specific function can be left unconnected. | | G30 | DDI1_DDCCLK | GND | ✅ | DDI1_DDCCLK connected directly to ground. This disables the DDC clock for DDI1, consistent with the intentional disabling of the DDI1 interface per design notes. | | J28 | RESERVED_J28 | | ✅ | RESERVED_J28 pin has no net connection. Reserved pins without specific function can be left unconnected. | | J30 | DDI1_BKLTEN | | ✅ | DDI1_BKLTEN backlight enable signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | J34 | RESERVED_J34 | | ✅ | RESERVED_J34 pin has no net connection. Reserved pins without specific function can be left unconnected. | | K28 | RESERVED_K28 | | ✅ | RESERVED_K28 pin has no net connection. Reserved pins without specific function can be left unconnected. | | K30 | DDI1_HPD | GND | ✅ | DDI1_HPD connected directly to ground. This indicates no display is connected to DDI1, consistent with the intentional disabling of the DDI1 interface per design notes. | | K34 | RESERVED_K34 | | ✅ | RESERVED_K34 pin has no net connection. Reserved pins without specific function can be left unconnected. | | M30 | DDI1_BKLTCTL | | ✅ | DDI1_BKLTCTL backlight control signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | M32 | RESERVED_M32 | | ✅ | RESERVED_M32 pin has no net connection. Reserved pins without specific function can be left unconnected. | | N30 | DDI1_VDDEN | | ✅ | DDI1_VDDEN display power enable signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | N32 | RESERVED_N32 | | ✅ | RESERVED_N32 pin has no net connection. Reserved pins without specific function can be left unconnected. | | P14 | RESERVED_P14 | MCSI_RCOMP | ✅ | RESERVED_P14 pin connected to MCSI_RCOMP with 150 ohm resistor R213 to ground. This provides compensation for the MIPI CSI interface as indicated by the text note 'Bay Trail-I MCSI Port'. | | P30 | DDI1_DDCDATA | DDI1_DDCDAT | ✅ | DDI1_DDCDATA connects to DDI1_DDCDAT with 2.2K pull-down resistor R257 to ground. This disables the DDC data line for DDI1, consistent with the intentional disabling of the DDI1 interface per design notes. | | R1 | RESERVED_R1 | | ✅ | RESERVED_R1 pin has no net connection. Reserved pins without specific function can be left unconnected. | | R3 | RESERVED_R3 | | ✅ | RESERVED_R3 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T2 | RESERVED_T2 | | ✅ | RESERVED_T2 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T3 | RESERVED_T3 | | ✅ | RESERVED_T3 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T4 | RESERVED_T4 | | ✅ | RESERVED_T4 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T6 | RESERVED_T6 | | ✅ | RESERVED_T6 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T7 | RESERVED_T7 | | ✅ | RESERVED_T7 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T9 | RESERVED_T9 | | ✅ | RESERVED_T9 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T10 | RESERVED_T10 | | ✅ | RESERVED_T10 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T12 | RESERVED_T12 | | ✅ | RESERVED_T12 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T13 | RESERVED_T13 | | ✅ | RESERVED_T13 pin has no net connection. Reserved pins without specific function can be left unconnected. | | T14 | RESERVED_T14 | | ✅ | RESERVED_T14 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V2 | RESERVED_V2 | | ✅ | RESERVED_V2 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V3 | RESERVED_V3 | | ✅ | RESERVED_V3 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V4 | RESERVED_V4 | | ✅ | RESERVED_V4 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V6 | RESERVED_V6 | | ✅ | RESERVED_V6 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V9 | RESERVED_V9 | | ✅ | RESERVED_V9 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V10 | RESERVED_V10 | | ✅ | RESERVED_V10 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V13 | RESERVED_V13 | | ✅ | RESERVED_V13 pin has no net connection. Reserved pins without specific function can be left unconnected. | | V14 | RESERVED_V14 | | ✅ | RESERVED_V14 pin has no net connection. Reserved pins without specific function can be left unconnected. | | W1 | RESERVED_W1 | | ✅ | RESERVED_W1 pin has no net connection. Reserved pins without specific function can be left unconnected. | | W3 | RESERVED_W3 | | ✅ | RESERVED_W3 pin has no net connection. Reserved pins without specific function can be left unconnected. | | Y2 | RESERVED_Y2 | | ✅ | RESERVED_Y2 pin has no net connection. Reserved pins without specific function can be left unconnected. | | Y3 | RESERVED_Y3 | | ✅ | RESERVED_Y3 pin has no net connection. Reserved pins without specific function can be left unconnected. | | Y4 | RESERVED_Y4 | | ✅ | RESERVED_Y4 pin has no net connection. Reserved pins without specific function can be left unconnected. | | Y6 | RESERVED_Y6 | | ✅ | RESERVED_Y6 pin has no net connection. Reserved pins without specific function can be left unconnected. | | Y12 | RESERVED_Y12 | | ✅ | RESERVED_Y12 pin has no net connection. Reserved pins without specific function can be left unconnected. | | Y13 | RESERVED_Y13 | | ✅ | RESERVED_Y13 pin has no net connection. Reserved pins without specific function can be left unconnected. | | BA1 | VGA_GREEN | | ✅ | VGA_GREEN output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated. | | AB2 | RESERVED_AB2 | | ✅ | RESERVED_AB2 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AB3 | RESERVED_AB3 | | ✅ | RESERVED_AB3 pin has no net connection. Reserved pins without specific function can be left unconnected. | | BA3 | VGA_RED | | ✅ | VGA_RED output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated. | | AB7 | RESERVED_AB7 | | ✅ | RESERVED_AB7 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AB9 | RESERVED_AB9 | | ✅ | RESERVED_AB9 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AB12 | RESERVED_AB12 | | ✅ | RESERVED_AB12 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AB13 | RESERVED_AB13 | | ✅ | RESERVED_AB13 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AB14 | RESERVED_AB14 | | ✅ | RESERVED_AB14 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AC1 | DDI1_TXN_3 | | ✅ | DDI1_TXN_3 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | AC3 | DDI1_TXP_3 | | ✅ | DDI1_TXP_3 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | BC1 | VGA_DDCCLK | CRT_CLK | ✅ | VGA_DDCCLK connects through 150 ohm resistor R39 to ground. This terminates the DDC clock line, indicating VGA interface is intentionally disabled. | | AD2 | DDI1_TXN_2 | | ✅ | DDI1_TXN_2 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | BC2 | VGA_DDCDATA | CRT_DAT | ✅ | VGA_DDCDATA connects through 150 ohm resistor R38 to ground. This terminates the DDC data line, indicating VGA interface is intentionally disabled. | | AD3 | DDI1_TXP_2 | | ✅ | DDI1_TXP_2 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | AD4 | RESERVED_AD4 | | ✅ | RESERVED_AD4 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AD6 | RESERVED_AD6 | | ✅ | RESERVED_AD6 pin has no net connection. Reserved pins without specific function can be left unconnected. | | BD2 | VGA_HSYNC | | ✅ | VGA_HSYNC output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated. | | AF2 | DDI1_TXN_1 | | ✅ | DDI1_TXN_1 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | AF3 | DDI1_TXP_1 | | ✅ | DDI1_TXP_1 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | AF13 | RESERVED_AF13 | | ✅ | RESERVED_AF13 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AF14 | RESERVED_AF14 | | ✅ | RESERVED_AF14 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AG1 | DDI1_TXN_0 | | ✅ | DDI1_TXN_0 transmit lane negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | BF2 | VGA_VSYNC | | ✅ | VGA_VSYNC output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated. | | AG3 | DDI1_TXP_0 | | ✅ | DDI1_TXP_0 transmit lane positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | AH2 | RESERVED_VSS3 | $3N554 | ✅ | RESERVED_VSS3 pin connected to ground through 0 ohm resistor R43. This provides a ground connection with the ability to isolate for debug purposes. | | AH3 | RESERVED_VSS2 | $3N552 | ✅ | RESERVED_VSS2 pin connected to ground through 0 ohm resistor R46. This provides a ground connection with the ability to isolate for debug purposes. | | AH13 | RESERVED_AH13 | | ✅ | RESERVED_AH13 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AH14 | RESERVED_AH14 | | ✅ | RESERVED_AH14 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AK2 | DDI1_AUXN | | ✅ | DDI1_AUXN auxiliary channel negative signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | AK3 | DDI1_AUXP | | ✅ | DDI1_AUXP auxiliary channel positive signal has no net connection. This is correct as DDI1 interface is intentionally disabled per design notes. | | AL1 | DDI0_AUXN | | ✅ | DDI0_AUXN auxiliary channel negative signal has no net connection. This is acceptable as DDI0 is configured for HDMI which does not use the auxiliary channel. | | AL3 | DDI0_AUXP | | ✅ | DDI0_AUXP auxiliary channel positive signal has no net connection. This is acceptable as DDI0 is configured for HDMI which does not use the auxiliary channel. | | AM2 | RESERVED_VSS1 | $3N589 | ✅ | RESERVED_VSS1 pin connected to ground through 0 ohm resistor R41. This provides a ground connection with the ability to isolate for debug purposes. | | AM3 | RESERVED_VSS0 | $3N579 | ✅ | RESERVED_VSS0 pin connected to ground through 0 ohm resistor R42. This provides a ground connection with the ability to isolate for debug purposes. | | AM13 | RESERVED_AM13 | | ✅ | RESERVED_AM13 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AM14 | RESERVED_AM14 | | ✅ | RESERVED_AM14 pin has no net connection. Reserved pins without specific function can be left unconnected. | | AP2 | DDI0_TXN_3 | HDMI_CLK_DN | ✅ | DDI0_TXN_3 connects to HDMI_CLK_DN, providing the negative differential clock signal for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AP3 | DDI0_TXP_3 | HDMI_CLK_DP | ✅ | DDI0_TXP_3 connects to HDMI_CLK_DP, providing the positive differential clock signal for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AR1 | DDI0_TXN_2 | HDMI_TX0_DN | ✅ | DDI0_TXN_2 connects to HDMI_TX0_DN, providing one of the negative differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AR3 | DDI0_TXP_2 | HDMI_TX0_DP | ✅ | DDI0_TXP_2 connects to HDMI_TX0_DP, providing one of the positive differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AT2 | DDI0_TXP_1 | HDMI_TX1_DP | ✅ | DDI0_TXP_1 connects to HDMI_TX1_DP, providing one of the positive differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AT3 | DDI0_TXN_1 | HDMI_TX1_DN | ✅ | DDI0_TXN_1 connects to HDMI_TX1_DN, providing one of the negative differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AV2 | DDI0_TXN_0 | HDMI_TX2_DN | ✅ | DDI0_TXN_0 connects to HDMI_TX2_DN, providing one of the negative differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AV3 | DDI0_TXP_0 | HDMI_TX2_DP | ✅ | DDI0_TXP_0 connects to HDMI_TX2_DP, providing one of the positive differential data signals for HDMI interface. This is part of the HDMI transmit interface from DDI0. | | AW1 | VGA_IREF | $3N548 | ✅ | VGA_IREF pin connects through 357 ohm resistor R40 to ground, setting the reference current for the VGA DAC. This configuration matches datasheet requirements for VGA DAC operation. | | AY2 | VGA_BLUE | | ✅ | VGA_BLUE output has no net connection. This is consistent with VGA interface being unused, as other VGA signals are also not connected or terminated. | | AY3 | VGA_IRTN | GND | ✅ | VGA_IRTN pin correctly connected to ground, providing the current return path for the VGA DAC as required by the datasheet. | </details> <details> <summary><b>U39</b> - SN74LVC1G14DCKR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf?ts=1753365169590&ref_url=https%25253A%25252F%25252Fwww.ti.com%25252Fproduct%25252FSN74LVC1G14) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/SN74LVC1G14DCKR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin with no net connection. This is acceptable per the datasheet which states the pin has no internal connection. | | 2 | A | HDMI_HPD | ✅ | Input pin A connected to HDMI_HPD signal. This provides the Hot Plug Detect signal from the HDMI connector to the Schmitt-trigger inverter for signal conditioning. | | 3 | GND | GND | ✅ | Ground pin correctly connected to the GND net. | | 4 | Y | HDMI_HPD_B | ✅ | Output pin Y connected to HDMI_HPD_B which drives the CPU DDI0_HPD input. The inversion is intentional as indicated by the _B suffix in the signal name. | | 5 | VCC | +V1P8S | ✅ | VCC pin connected to +V1P8S (1.8V supply) with proper bypass capacitor C375. The 1.8V supply is within the valid operating range and properly decoupled. | </details> <details> <summary><b>C375</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor pin connected to GND for bypass/decoupling function. | | 2 | 2 | +V1P8S | ✅ | Capacitor pin connected to +V1P8S supply rail, providing local decoupling for U39 and the 1.8V power distribution. | </details> <details> <summary><b>R217</b> - 110-0004476 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI_RCOMP_N | ✅ | 402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, which connect to CPU1 pins AK12 and AK13 respectively. This appears to be a compensation resistor for the DDI (Display Digital Interface) interface. | | 2 | 2 | DDI_RCOMP_P | ✅ | 402 ohm resistor connected between DDI_RCOMP_N and DDI_RCOMP_P nets, which connect to CPU1 pins AK12 and AK13 respectively. This appears to be a compensation resistor for the DDI (Display Digital Interface) interface. | </details> <details> <summary><b>R213</b> - 110-0002631 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCSI_RCOMP | ✅ | Connected to MCSI_RCOMP net, which connects to CPU1 pin P14 (labeled as RESERVED_P14). | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the MCSI compensation resistor. | </details> <details> <summary><b>R40</b> - 110-0004695 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N548 | ✅ | Pin 1 connects to the VGA_IREF pin (AW1) of the Intel Atom E3825 SOC (CPU1) via net $3N548. This sets the reference current for the VGA DAC output. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, completing the reference current path for the VGA DAC. | </details> <details> <summary><b>R257</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI1_DDCDAT | ✅ | Connected to DDI1_DDCDAT (CPU1 pin P30). This resistor is part of the intentional disabling of the DDI1 display port, providing a pull-down on the DDC data line. | | 2 | 2 | GND | ✅ | Connected to GND, providing the return path for the pull-down resistor that terminates the unused DDI1_DDCDAT signal. | </details> <details> <summary><b>R38</b> - 110-0002631 ❌</summary> DRCY flagged 2 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_DAT | ❌ | <details><summary>Connected to VGA DDC data line (CRT_DAT) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,40.96,76.02,48.46" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_DAT <em>(from schematic)</em></li><li>Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) <em>(from schematic)</em></li><li>DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation <em>(reasoning)</em></li><li>This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up <em>(from schematic)</em></li><li>The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC data line to ground, preventing any DDC communication <em>(reasoning)</em></li><li>If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) <em>(reasoning)</em></li><li>If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down <em>(reasoning)</em></li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>Connected to GND, forming the return path for the pull-down resistor.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,40.96,76.93,48.46" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to net GND <em>(from schematic)</em></li><li>This configuration creates a pull-down resistor from CRT_DAT to ground <em>(from schematic)</em></li></ul></details> | </details> <details> <summary><b>R39</b> - 110-0002631 ❌</summary> DRCY flagged 2 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_CLK | ❌ | <details><summary>Connected to VGA DDC clock line (CRT_CLK) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,39.19,76.02,46.69" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_CLK <em>(from schematic)</em></li><li>Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) <em>(from schematic)</em></li><li>DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation <em>(reasoning)</em></li><li>This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up <em>(from schematic)</em></li><li>The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC clock line to ground, preventing any DDC communication <em>(reasoning)</em></li><li>If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) <em>(reasoning)</em></li><li>If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down <em>(reasoning)</em></li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>Connected to GND, forming the return path for the pull-down resistor.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,39.19,76.93,46.69" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to net GND <em>(from schematic)</em></li><li>This configuration creates a pull-down resistor from CRT_CLK to ground <em>(from schematic)</em></li></ul></details> | </details> <details> <summary><b>R102</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for the pull-down resistor. | | 2 | 2 | GPIO_NC13 | ✅ | Pin 2 is connected to GPIO_NC13, which connects to CPU1 pin A29 (RESERVED_A29). This forms a 10K pull-down resistor on a reserved GPIO pin. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C24 | ~PROCHOT | VR_HOT_L | ✅ | Processor hot thermal alert signal, correctly pulled up to 1.0V with 73.2Ω resistor. | | N34 | RESERVED_N34 | | ✅ | Reserved pin, left unconnected as permitted by design. | | P34 | RESERVED_P34 | | ✅ | Reserved pin, left unconnected as permitted by design. | | BA12 | SATA_GP0 | SATA_GP0 | ✅ | SATA general purpose output 0, correctly pulled down to ground with 10K resistor. | | BA16 | SATA_RXN_1 | SATA1_RXN | ✅ | SATA port 1 receive negative signal, correctly AC-coupled to mSATA interface. | | BA18 | SD2_CLK | | ✅ | SD2 clock signal, left unconnected as SD2 interface is unused. | | BA20 | SD2_D2 | | ✅ | SD2 data bit 2 signal, left unconnected as SD2 interface is unused. | | BA24 | ~MMC1_RST | | ✅ | MMC1 reset signal, left unconnected on this page but likely connected elsewhere. | | BA26 | SD3_D3 | SD3_D3 | ✅ | SD3 data bit 3 signal, routed to SD card interface. | | BA30 | LPE_I2S2_FRM | LPE_I2S_FRM | ✅ | I2S frame sync signal for Low Power Engine audio, correctly pulled up to 1.8V. | | BB3 | RESERVED_BB3 | | ✅ | Reserved pin, left unconnected as permitted by design. | | BB4 | RESERVED_BB4 | | ✅ | Reserved pin, left unconnected as permitted by design. | | BB5 | RESERVED_VSS6 | RESERVED_VSS6 | ✅ | Reserved VSS pin, correctly connected to ground through 0Ω resistor. | | BB7 | RESERVED_VSS7 | RESERVED_VSS7 | ✅ | Reserved VSS pin, correctly connected to ground through 0Ω resistor. | | BB10 | RESERVED_VSS4 | ICLK_SATA_TERMP | ✅ | Reserved VSS pin, correctly connected to ground through 0Ω resistor. | | BC10 | RESERVED_VSS5 | ICLK_SATA_TERMN | ✅ | Reserved VSS pin, correctly connected to ground through 0Ω resistor. | | BC18 | SD2_CMD | | ✅ | SD2 command signal, left unconnected as SD2 interface is unused. | | BC24 | SD3_CD# | SD3_CD# | ✅ | SD3 card detect signal, connected to write protect through 0Ω resistor in intentional design choice. | | BC30 | LPE_I2S2_DATAOUT | LPE_I2S_DATOUT | ✅ | I2S data output signal for Low Power Engine audio, connected through 1K resistor to GPIO for hardware strapping. | | BD5 | SD3_WP_BD5 | SD3_WP | ✅ | SD3 write protect signal, connected to card detect through 0Ω resistor in intentional design choice. | | BD7 | ~PCIE_CLKREQ_1 | CLKREQ1_B | ✅ | PCIe clock request 1 signal, correctly pulled up to 1.8V with 10K resistor. | | BD10 | SATA_TXP1 | SATA1_TXP | ✅ | SATA port 1 transmit positive signal, correctly AC-coupled to mSATA interface. | | BD18 | ~SD2_D3_CD | | ✅ | SD2 data bit 3 / card detect signal, left unconnected as SD2 interface is unused. | | BD20 | SD2_D1 | | ✅ | SD2 data bit 1 signal, left unconnected as SD2 interface is unused. | | BD22 | ~SD3_PWREN | /SD3+PWREN | ✅ | SD3 power enable signal, connected to test point for debug access. | | BD26 | SD3_D1 | SD3_D1 | ✅ | SD3 data bit 1 signal, routed to SD card interface. | | BD28 | LPE_I2S2_DATAIN | LPE_I2S_DATIN | ✅ | I2S data input signal for Low Power Engine audio, routed to audio codec. | | BE3 | ~PCIE_CLKREQ_3 | mPCIe_CLKREQ3_B | ✅ | PCIe clock request 3 signal, correctly pulled up to 1.8V with 10K resistor. | | BF6 | SATA_TXP_0 | SATA0_TXP | ✅ | SATA port 0 transmit positive signal, correctly AC-coupled to SATA connector. | | BF10 | SATA_TXN_1 | SATA1_TXN | ✅ | SATA port 1 transmit negative signal, correctly AC-coupled to mSATA interface. | | BF20 | HDA_LPE_RCOMP | HDA_RCOMP | ✅ | HDA/LPE compensation resistor pin, correctly connected to ground through 49.9Ω resistor. | | BF22 | SD3_1P8EN | SD3_1P8EN | ✅ | SD3 1.8V enable signal, connected to test point for debug access. | | BF26 | SD3_RCOMP | SD3_RCOMP | ✅ | SD3 compensation resistor pin, correctly connected to ground through 49.9Ω resistor. | | BF28 | LPE_I2S2_CLK | LPE_I2S_CLK | ✅ | I2S clock signal for Low Power Engine audio, routed to audio codec. | | BG3 | ~PCIE_CLKREQ_0 | CLKREQ0_B | ✅ | PCIe clock request 0 signal, correctly pulled up to 1.8V with 10K resistor. | | BG5 | ~PCIE_CLKREQ_2 | LAN_CLKREQ2_B | ✅ | PCIe clock request 2 signal, correctly pulled up to 1.8V with 10K resistor. | | BG7 | SATA_TXN_0 | SATA0_TXN | ✅ | SATA port 0 transmit negative signal, correctly AC-coupled to SATA connector. | | BG18 | GPIO_S0_SC_15 | | ✅ | GPIO S0 SC 15 signal, left unconnected as this GPIO is unused. | | BG19 | HDA_SDI0 | | ✅ | HDA serial data input 0 signal, left unconnected as HDA interface is unused. | | BG20 | HDA_SDO | | ✅ | HDA serial data output signal, left unconnected as HDA interface is unused. | | BG21 | HDA_SDI1 | | ✅ | HDA serial data input 1 signal, left unconnected as HDA interface is unused. | | BG22 | ~HDA_RST | | ✅ | HDA reset signal, left unconnected as HDA interface is unused. | | BH18 | GPIO_S0_SC_14 | | ✅ | GPIO S0 SC 14 signal, left unconnected as this GPIO is unused. | | BH20 | HDA_SYNC | | ✅ | HDA sync signal, left unconnected as HDA interface is unused. | | AK7 | RESERVED_AK7 | | ✅ | Reserved pin, left unconnected as permitted by design. | | AK9 | RESERVED_AK9 | | ✅ | Reserved pin, left unconnected as permitted by design. | | BJ21 | HDA_CLK | | ✅ | HDA clock signal, left unconnected as HDA interface is unused. | | AP4 | PCIE_TXN_3 | mPCIE_TX_N | ✅ | PCIe lane 3 transmit negative signal, connected to mPCIe interface. | | AP6 | PCIE_TXP_3 | mPCIE_TX_P | ✅ | PCIe lane 3 transmit positive signal, connected to mPCIe interface. | | AP7 | PCIE_RXN_3 | mPCIE_RX_N | ✅ | PCIe lane 3 receive negative signal, connected to mPCIe interface. | | AP9 | PCIE_RXP_3 | mPCIE_RX_P | ✅ | PCIe lane 3 receive positive signal, connected to mPCIe interface. | | AP10 | PCIE_RXN_2 | PCIE_RXN2 | ✅ | PCIe lane 2 receive negative signal, connected to LAN interface. | | AP12 | PCIE_RXP_2 | PCIE_RXP2 | ✅ | PCIe lane 2 receive positive signal, connected to LAN interface. | | AP13 | PCIE_RCOMP_N_AP13_AP13 | PCIE_RCOMP_N | ✅ | PCIe compensation resistor negative terminal, correctly connected with 402Ω to positive terminal. | | AP14 | PCIE_RCOMP_P_AP14_AP14 | PCIE_RCOMP_P | ✅ | PCIe compensation resistor positive terminal, correctly connected with 402Ω to negative terminal. | | AT6 | PCIE_TXN_2 | PCIE_TXN2 | ✅ | PCIe lane 2 transmit negative signal, connected to LAN interface. | | AT7 | PCIE_TXP_2 | PCIE_TXP2 | ✅ | PCIe lane 2 transmit positive signal, connected to LAN interface. | | AT9 | PCIE_RXN_1 | | ✅ | PCIe lane 1 receive negative signal, left unconnected as lane 1 is unused. | | AT10 | PCIE_RXP_1 | | ✅ | PCIe lane 1 receive positive signal, left unconnected as lane 1 is unused. | | AT13 | PCIE_RXN_0 | | ✅ | PCIe lane 0 receive negative signal, left unconnected as lane 0 is unused. | | AT14 | PCIE_RXP_0 | | ✅ | PCIe lane 0 receive positive signal, left unconnected as lane 0 is unused. | | AT18 | SATA_RCOMP_N_AT18 | SATA_RCOMP_N | ✅ | SATA compensation resistor negative terminal, correctly connected with 402Ω to positive terminal. | | AT20 | MMC1_D3 | | ✅ | MMC1 data bit 3 signal, routed to eMMC interface. | | AT22 | MMC1_CLK | | ✅ | MMC1 clock signal, routed to eMMC interface. | | AT26 | MMC1_D6 | | ✅ | MMC1 data bit 6 signal, routed to eMMC interface. | | AT28 | SD3_D0 | SD3_D0 | ✅ | SD3 data bit 0 signal, routed to SD card interface. | | AU16 | SATA_RXP_0 | SATA0_RXP | ✅ | SATA port 0 receive positive signal, correctly AC-coupled to SATA connector. | | AU18 | SATA_RCOMP_P_AU18 | SATA_RCOMP_P | ✅ | SATA compensation resistor positive terminal, correctly connected with 402Ω to negative terminal. | | AU20 | MMC1_D7 | | ✅ | MMC1 data bit 7 signal, routed to eMMC interface. | | AU22 | MMC1_D1 | | ✅ | MMC1 data bit 1 signal, routed to eMMC interface. | | AU26 | MMC1_D5 | | ✅ | MMC1 data bit 5 signal, routed to eMMC interface. | | AU28 | SD3_D2 | SD3_D2 | ✅ | SD3 data bit 2 signal, routed to SD card interface. | | AV4 | PCIE_TXN_1 | | ✅ | PCIe lane 1 transmit negative signal, left unconnected as lane 1 is unused. | | AV6 | PCIE_TXP_1 | | ✅ | PCIe lane 1 transmit positive signal, left unconnected as lane 1 is unused. | | AV9 | RESERVED_AV9 | | ✅ | Reserved pin, left unconnected as permitted by design. | | AV10 | RESERVED_AV10 | | ✅ | Reserved pin, left unconnected as permitted by design. | | AV16 | SATA_RXN_0 | SATA0_RXN | ✅ | SATA port 0 receive negative signal, correctly AC-coupled to SATA connector. | | AV20 | MMC1_D0 | | ✅ | MMC1 data bit 0 signal, routed to eMMC interface. | | AV22 | MMC1_D2 | | ✅ | MMC1 data bit 2 signal, routed to eMMC interface. | | AV26 | MMC1_CMD | | ✅ | MMC1 command signal, routed to eMMC interface. | | AV28 | SD3_CMD | SD3_CMD | ✅ | SD3 command signal, routed to SD card interface. | | AY6 | PCIE_TXN_0 | | ✅ | PCIe lane 0 transmit negative signal, left unconnected as lane 0 is unused. | | AY7 | PCIE_TXP_0 | | ✅ | PCIe lane 0 transmit positive signal, left unconnected as lane 0 is unused. | | AY12 | ~SATA_LED | SATA_LED_B | ✅ | SATA LED output signal, correctly connected through current-limiting resistor to LED indicator. | | AY14 | SATA_GP1 | SATA_GP1 | ✅ | SATA general purpose output 1, correctly pulled down to ground with 10K resistor. | | AY16 | SATA_RXP_1 | SATA1_RXP | ✅ | SATA port 1 receive positive signal, correctly AC-coupled to mSATA interface. | | AY18 | MMC1_RCOMP | MMC1_RCOMP | ✅ | MMC1 compensation resistor pin, correctly connected to ground through 49.9Ω resistor. | | AY20 | SD2_D0 | | ✅ | SD2 data bit 0 signal, left unconnected as SD2 interface is unused. | | AY24 | MMC1_D4 | | ✅ | MMC1 data bit 4 signal, routed to eMMC interface. | | AY26 | SD3_CLK | SD3_CLK | ✅ | SD3 clock signal, routed to SD card interface. | </details> <details> <summary><b>C10</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXP_C | ✅ | AC coupling capacitor for SATA TX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | | 2 | 2 | SATA0_TXP | ✅ | AC coupling capacitor for SATA TX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | </details> <details> <summary><b>C11</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXN_C | ✅ | AC coupling capacitor for SATA TX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | | 2 | 2 | SATA0_TXN | ✅ | AC coupling capacitor for SATA TX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | </details> <details> <summary><b>C12</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXN_C | ✅ | AC coupling capacitor for SATA RX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | | 2 | 2 | SATA0_RXN | ✅ | AC coupling capacitor for SATA RX- signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | </details> <details> <summary><b>C13</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXP_C | ✅ | AC coupling capacitor for SATA RX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | | 2 | 2 | SATA0_RXP | ✅ | AC coupling capacitor for SATA RX+ signal, correctly placed between connector and CPU with appropriate 0.01uF value per SATA specification. | </details> <details> <summary><b>R239</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_RCOMP_N | ✅ | SATA RCOMP resistor correctly configured with 402 ohm value between CPU RCOMP pins for impedance calibration of SATA differential pairs. | | 2 | 2 | SATA_RCOMP_P | ✅ | SATA RCOMP resistor correctly configured with 402 ohm value between CPU RCOMP pins for impedance calibration of SATA differential pairs. | </details> <details> <summary><b>R179</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001960) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_LED_B | ✅ | Current limiting resistor for SATA LED signal, correctly configured with 220 ohm value to limit current to approximately 8.2mA when jumper J6 is installed. | | 2 | 2 | SATA_LED_R | ✅ | Current limiting resistor for SATA LED signal, correctly configured with 220 ohm value to limit current to approximately 8.2mA when jumper J6 is installed. | </details> <details> <summary><b>J6</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Jumper pin connected to +V1P8S supply, providing pull-up voltage for SATA LED signal when jumper is installed. | | 2 | 2 | SATA_LED_R | ✅ | Jumper pin connected to SATA_LED_R net, allowing optional connection to +V1P8S for SATA LED functionality. | </details> <details> <summary><b>J3</b> - HDR_7POS_SER_GOLD_SATA_R/A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-67490-001.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0003610) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins for SATA signal connector, providing shielding between differential pairs. Correctly connected to GND net. | | 4 | 4 | GND | ✅ | Ground pins for SATA signal connector, providing shielding between differential pairs. Correctly connected to GND net. | | 7 | 7 | GND | ✅ | Ground pins for SATA signal connector, providing shielding between differential pairs. Correctly connected to GND net. | | 2 | 2 | SATA0_TXP_C | ✅ | SATA TX+ signal pin, correctly connected through AC coupling capacitor C10 to CPU SATA0_TXP output. | | 3 | 3 | SATA0_TXN_C | ✅ | SATA TX- signal pin, correctly connected through AC coupling capacitor C11 to CPU SATA0_TXN output. | | 5 | 5 | SATA0_RXN_C | ✅ | SATA RX- signal pin, correctly connected through AC coupling capacitor C12 to CPU SATA0_RXN input. | | 6 | 6 | SATA0_RXP_C | ✅ | SATA RX+ signal pin, correctly connected through AC coupling capacitor C13 to CPU SATA0_RXP input. | | 8 | MH1 | GND_EARTH | ✅ | Mounting hole pins correctly connected to GND_EARTH for EMI shielding and chassis ground connection. | | 9 | MH2 | GND_EARTH | ✅ | Mounting hole pins correctly connected to GND_EARTH for EMI shielding and chassis ground connection. | </details> <details> <summary><b>C177</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_N | ✅ | Connected to mSATA_RX_N net, providing AC coupling for SATA1 receive negative signal from mSATA connector to CPU. | | 2 | 2 | SATA1_RXN | ✅ | Connected to SATA1_RXN net, which connects to CPU1 pin BA16 (SATA_RXN_1), completing the AC coupling path for the negative receive signal. | </details> <details> <summary><b>C178</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_P | ✅ | Connected to mSATA_RX_P net, providing AC coupling for SATA1 receive positive signal from mSATA connector to CPU. | | 2 | 2 | SATA1_RXP | ✅ | Connected to SATA1_RXP net, which connects to CPU1 pin AY16 (SATA_RXP_1), completing the AC coupling path for the positive receive signal. | </details> <details> <summary><b>C179</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_P | ✅ | Connected to mSATA_TX_P net, providing AC coupling for SATA1 transmit positive signal from CPU to mSATA connector. | | 2 | 2 | SATA1_TXP | ✅ | Connected to SATA1_TXP net, which connects to CPU1 pin BD10 (SATA_TXP1), completing the AC coupling path for the positive transmit signal. | </details> <details> <summary><b>C180</b> - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_N | ✅ | Connected to mSATA_TX_N net, providing AC coupling for SATA1 transmit negative signal from CPU to mSATA connector. | | 2 | 2 | SATA1_TXN | ✅ | Connected to SATA1_TXN net, which connects to CPU1 pin BF10 (SATA_TXN_1), completing the AC coupling path for the negative transmit signal. | </details> <details> <summary><b>R218</b> - 110-0004476 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PCIE_RCOMP_P | ✅ | Pin 1 connects to PCIE_RCOMP_P on the Intel Atom E3825 SOC (CPU1 pin AP14). This is the positive terminal of the PCIe compensation resistor. | | 2 | 2 | PCIE_RCOMP_N | ✅ | Pin 2 connects to PCIE_RCOMP_N on the Intel Atom E3825 SOC (CPU1 pin AP13). This is the negative terminal of the PCIe compensation resistor. | </details> <details> <summary><b>R240</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for the MMC1_RCOMP compensation resistor. | | 2 | 2 | MMC1_RCOMP | ✅ | Pin 2 is connected to MMC1_RCOMP on the CPU, providing impedance calibration reference for the MMC1 interface. | </details> <details> <summary><b>R258</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for the SD3_RCOMP compensation resistor. | | 2 | 2 | SD3_RCOMP | ✅ | Pin 2 is connected to SD3_RCOMP on the CPU, providing impedance calibration reference for the SD3 interface. | </details> <details> <summary><b>R242</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDA_RCOMP | ✅ | Pin 1 is connected to HDA_RCOMP on the CPU, providing impedance calibration reference for the HDA interface. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, providing the ground reference for the HDA_RCOMP compensation resistor. | </details> <details> <summary><b>R189</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pull-down resistor connection to ground. Part of hardware strap configuration for GPIO_S0_SC_56, marked DNI. | | 2 | 2 | GPIO_S0_SC_56 | ✅ | Connected to GPIO_S0_SC_56 strap pin. Shares net with R219 to form mutually exclusive pull-up/pull-down strap option. | </details> <details> <summary><b>R219</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor connection to +V1P8S supply. Part of hardware strap configuration for GPIO_S0_SC_56, marked DNI. | | 2 | 2 | GPIO_S0_SC_56 | ✅ | Connected to GPIO_S0_SC_56 strap pin. Shares net with R189 to form mutually exclusive pull-up/pull-down strap option. | </details> <details> <summary><b>R234</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP3 | ✅ | Connected to BOM_OP3 net, providing pull-down for hardware identification bit 3. | | 2 | 2 | GND | ✅ | Connected to GND, providing the pull-down path. | </details> <details> <summary><b>R208</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP2 | ✅ | Connected to BOM_OP2 net, providing pull-down for hardware identification bit 2. | | 2 | 2 | GND | ✅ | Connected to GND, providing the pull-down path. | </details> <details> <summary><b>R233</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP1 | ✅ | Connected to BOM_OP1 net but marked DNI, allowing BOM_OP1 to be pulled high through R211. | | 2 | 2 | GND | ✅ | Connected to GND but component is DNI. | </details> <details> <summary><b>R401</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP4 | ✅ | Connected to BOM_OP4 net but marked DNI, allowing BOM_OP4 to be pulled high through R400. | | 2 | 2 | GND | ✅ | Connected to GND but component is DNI. | </details> <details> <summary><b>R209</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A but marked DNI, allowing BOM_OP2 to be pulled low through R208. | | 2 | 2 | BOM_OP2 | ✅ | Connected to BOM_OP2 but component is DNI. | </details> <details> <summary><b>R210</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A but marked DNI, allowing BOM_OP3 to be pulled low through R234. | | 2 | 2 | BOM_OP3 | ✅ | Connected to BOM_OP3 but component is DNI. | </details> <details> <summary><b>R211</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A, providing pull-up for hardware identification bit 1. | | 2 | 2 | BOM_OP1 | ✅ | Connected to BOM_OP1, providing the pull-up path. | </details> <details> <summary><b>R400</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A, providing pull-up for hardware identification bit 4. | | 2 | 2 | BOM_OP4 | ✅ | Connected to BOM_OP4, providing the pull-up path. | </details> <details> <summary><b>R190</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ1_B | ✅ | Pin 1 connects to CLKREQ1_B, providing pull-up for the PCIe clock request 1 signal from the CPU. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the CLKREQ1_B signal. | </details> <details> <summary><b>R191</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ0_B | ✅ | Pin 1 connects to CLKREQ0_B, providing pull-up for the PCIe clock request 0 signal from the CPU. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the CLKREQ0_B signal. | </details> <details> <summary><b>R2</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mPCIe_CLKREQ3_B | ✅ | Pin 1 connects to mPCIe_CLKREQ3_B, providing pull-up for the PCIe clock request 3 signal from the CPU, associated with the mPCIe card slot. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the mPCIe_CLKREQ3_B signal. | </details> <details> <summary><b>R71</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_CLKREQ2_B | ✅ | Pin 1 connects to LAN_CLKREQ2_B, providing pull-up for the PCIe clock request 2 signal from the CPU, associated with the Intel LAN controller. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the LAN_CLKREQ2_B signal. | </details> <details> <summary><b>R259</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_10_UNLOCK | ✅ | Pin 1 connects to GPIO_S5_10_UNLOCK signal. This is one end of a series resistor that allows external control of a hardware strap pin. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | Pin 2 connects to LPE_I2S_DATOUT, which is also known as GPIO_S0_SC65 and serves as a hardware strap pin on the CPU. | </details> <details> <summary><b>R260</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_DATOUT | ✅ | Pin 1 connects to LPE_I2S_DATOUT. This is a DNI pull-down resistor option for the hardware strap pin. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This would provide a pull-down path if the component were populated. | </details> <details> <summary><b>R268</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_FRM | ✅ | Pin 1 connects to LPE_I2S_FRM, which is a hardware strap pin (GPIO_S0_SC63) on the CPU. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing a pull-up voltage for the strap pin. | </details> <details> <summary><b>R73</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND, providing ground reference for the 0-ohm resistor. | | 2 | 2 | ICLK_SATA_TERMP | ✅ | Pin 2 connects to ICLK_SATA_TERMP, which is CPU pin BB10 (RESERVED_VSS4), grounding the SATA termination positive pin. | </details> <details> <summary><b>R74</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND, providing ground reference for the 0-ohm resistor. | | 2 | 2 | ICLK_SATA_TERMN | ✅ | Pin 2 connects to ICLK_SATA_TERMN, which is CPU pin BC10 (RESERVED_VSS5), grounding the SATA termination negative pin. | </details> <details> <summary><b>R72</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS6 | ✅ | Pin 1 connects to RESERVED_VSS6, which is CPU pin BB5, a reserved pin that should be grounded. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, properly grounding the reserved CPU pin through the 0-ohm resistor. | </details> <details> <summary><b>R192</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS7 | ✅ | Pin 1 connects to RESERVED_VSS7, which is CPU pin BB7, a reserved pin that should be grounded. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, properly grounding the reserved CPU pin through the 0-ohm resistor. | </details> <details> <summary><b>R354</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SD3_WP | ✅ | 0 ohm resistor connecting SD3_WP to SD3_CD#, tying the write protect and card detect signals together. This unusual configuration may be intentional for the Bay Trail-I processor variant. | | 2 | 2 | SD3_CD# | ✅ | 0 ohm resistor connecting SD3_WP to SD3_CD#, tying the write protect and card detect signals together. This unusual configuration may be intentional for the Bay Trail-I processor variant. | </details> <details> <summary><b>R255</b> - 110-0004474 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004474) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR_HOT_L | ✅ | Connected to VR_HOT_L net, which connects to the CPU's PROCHOT (Processor Hot) signal. This pin forms one end of a pull-up resistor for the thermal management signal. | | 2 | 2 | +V1P0S | ✅ | Connected to +V1P0S (1.0V supply rail), providing the pull-up voltage for the PROCHOT signal through the 73.2 ohm resistor. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A9 | ILB_RTC_X2 | BRTCX2 | ✅ | ILB_RTC_X2 is connected to 32.768 kHz crystal with 18pF load capacitor. | | A13 | GPIO_S5_9 | SOC_USB_HOST_EN1 | ✅ | GPIO_S5_9 is connected to SOC_USB_HOST_EN1 net for USB host enable control. | | A17 | GPIO_S5_3 | mPCIE_WAKEB | ✅ | GPIO_S5_3 is connected to mPCIE_WAKEB net with optional 2.2K pull-up (DNI). | | A21 | PCU_SPI_MOSI | SOC_SPI_MOSI | ✅ | PCU_SPI_MOSI is connected through 0-ohm series resistor R103 to the SPI flash interface. | | A25 | SVID_DATA | SVID_DATA | ✅ | SVID_DATA is connected through 16.9-ohm series resistor to voltage regulator interface. | | B7 | PMC_CORE_PWROK | PMC_CORE_PWROK | ✅ | PMC_CORE_PWROK is connected through 0-ohm resistor to SYS_PWRGD with optional 1uF capacitor (DNI). | | B8 | ILB_RTC_EXTPAD | BVCCRTC_EXTPAD | ✅ | ILB_RTC_EXTPAD is connected to 0.1uF decoupling capacitor for RTC battery backup. | | B10 | ~PMC_RSMRST | PMC_RSMRST | ✅ | PMC_RSMRST# is connected with 100K pull-down, 10K pull-up, and 10pF filter capacitor. | | B14 | GPIO_S5_6 | BOM_OP2 | ✅ | GPIO_S5_6 is connected to BOM_OP2 net for board option configuration. | | B16 | GPIO_S5_1 | SOC_GPIO_S5_1 | ✅ | GPIO_S5_1 is connected to SOC_GPIO_S5_1 net for general purpose I/O. | | B18 | GPIO_S5_0 | SOC_GPIO_S5_0 | ✅ | GPIO_S5_0 is connected to SOC_GPIO_S5_0 net for general purpose I/O. | | B22 | PCU_SPI_MISO | SOC_SPI_MISO | ✅ | PCU_SPI_MISO is connected through 0-ohm series resistor R36 to the SPI flash interface. | | B24 | ~SVID_ALERT | SVID_ALERT | ✅ | SVID_ALERT# is connected through 20-ohm series resistor and 69.8-ohm pull-up. | | C9 | ILB_RTC_X1 | BRTCX1 | ✅ | ILB_RTC_X1 is connected to 32.768 kHz crystal with 18pF load capacitor. | | C11 | ~ILB_RTC_TEST | ILB_RTC_TESTB | ✅ | ILB_RTC_TEST# is connected to RTC test signal. | | C12 | ~ILB_RTC_RST | RTCRST_L | ✅ | ILB_RTC_RST# is connected with 20K pull-up to +RTCVCC and 1uF filter capacitor. | | C13 | GPIO_S5_8 | SOC_USB_HOST_EN0 | ✅ | GPIO_S5_8 is connected to SOC_USB_HOST_EN0 net for USB host enable control. | | C15 | GPIO_S5_7 | BOM_OP3 | ✅ | GPIO_S5_7 is connected to BOM_OP3 net for board option configuration. | | C16 | GPIO_S5_5 | BOM_OP1 | ✅ | GPIO_S5_5 is connected to BOM_OP1 net for board option configuration. | | C17 | GPIO_S5_4 | BOM_OP4 | ✅ | GPIO_S5_4 is connected to BOM_OP4 net for board option configuration. | | C18 | GPIO_S5_2 | SOC_GPIO_S5_2 | ✅ | GPIO_S5_2 is connected to SOC_GPIO_S5_2 net for general purpose I/O. | | C19 | GPIO_S5_10 | GPIO_S5_10_UNLOCK | ✅ | GPIO_S5_10 is connected to GPIO_S5_10_UNLOCK net for general purpose I/O. | | C21 | ~PCU_SPI_CS_11 | SOC_SPI_CS1B | ✅ | PCU_SPI_CS_11# is connected through 0-ohm series resistor (DNI) to SPI chip select 1. | | C22 | PCU_SPI_CLK | SOC_SPI_CLK | ✅ | PCU_SPI_CLK is connected through 0-ohm series resistor to SPI clock with optional 10pF capacitor (DNI). | | C23 | ~PCU_SPI_CS_00 | SOC_SPI_CS0B | ✅ | PCU_SPI_CS_00# is connected through 0-ohm series resistor to SPI chip select 0. | | C25 | SVID_CLK | SVID_CLK-R | ✅ | SVID_CLK is connected to voltage regulator serial VID clock signal. | | D14 | TAP_TCK | XDP_H_TCK | ✅ | TAP_TCK is connected to JTAG test clock with 51-ohm series resistor from ground. | | D18 | ~TAP_PRDY | XDP_H_PRDYB | ✅ | TAP_PRDY# is connected to JTAG probe ready signal. | | D20 | PMC_ACPRESENT | PMC_ACPRESENT | ✅ | PMC_ACPRESENT is connected with 2.2K pull-up to +V1P8A for AC power detection. | | D22 | ~PMC_SLP_S3 | PMC_SLP_S3_L | ✅ | PMC_SLP_S3# is connected to level shifter for S3 sleep state indication. | | D26 | PMC_SUSPWRDNACK | SUSPWRDNACK | ✅ | PMC_SUSPWRDNACK is connected with 10K pull-up to +V1P8A and test point. | | F12 | TAP_TDI | XDP_H_TDI | ✅ | TAP_TDI is connected to JTAG test data in with 51-ohm series resistor from +V1P8A. | | F14 | TAP_TMS | XDP_H_TMS | ✅ | TAP_TMS is connected to JTAG test mode select with 51-ohm series resistor from +V1P8A. | | F16 | ~TAP_PREQ | XDP_H_PREQB | ✅ | TAP_PREQ# is connected to JTAG probe request signal. | | F18 | ~PMC_SLP_S0IX | PMC_SLP_S0IX | ✅ | PMC_SLP_S0IX# is connected to test point for S0ix sleep state monitoring. | | F20 | ~PMC_PLTRST | PMC_PLTRST_R_V1P8 | ✅ | PMC_PLTRST# is connected to level shifter for platform reset signaling. | | F22 | ~PMC_SLP_S4 | PMC_SLP_S4_L | ✅ | PMC_SLP_S4# is connected to level shifter for S4 sleep state indication. | | F26 | ~PMC_WAKE_PCIE_0 | PMC_PCIE_WAKE_R | ✅ | PMC_WAKE_PCIE_0# is connected through dual Schottky diode with 1K pull-up to +V1P8A. | | G12 | ~TAP_TRST | XDP_H_TRSTB | ✅ | TAP_TRST# is connected to JTAG test reset with 51-ohm series resistor from ground. | | G16 | TAP_TDO | XDP_H_TDO | ✅ | TAP_TDO is connected to JTAG test data out signal. | | G18 | ~PMC_SUS_STAT | LPCPD_L | ✅ | PMC_SUS_STAT# is connected to test point for suspend status monitoring. | | G24 | PMC_SUSCLK0_G24 | PMC_SUSCLK0 | ✅ | PMC_SUSCLK0_G24 is connected to level shifter with optional 2.2K pull-up (DNI). | | J18 | GPIO_S5_25 | XDP_H_OBSDATA_A2 | ✅ | GPIO_S5_25 is connected to XDP_H_OBSDATA_A2 net for debug observation data. | | J20 | GPIO_S5_14 | GPIO_S514_J20 | ✅ | GPIO_S5_14 is connected with 10K pull-up to +V1P8A. | | J24 | GPIO_S5_17 | GPIO_S5_17 | ✅ | GPIO_S5_17 is connected to jumper header with 10K pull-up to +V1P8S. | | J26 | ~PMC_PWRBTN | PMC_PWRBTN | ✅ | PMC_PWRBTN# is connected through dual diode circuit with optional 20K pull-up (DNI). | | K18 | GPIO_S5_27 | EXP_GPIO1 | ✅ | GPIO_S5_27 is connected to EXP_GPIO1 net for expansion GPIO. | | K20 | GPIO_S5_28 | EXP_GPIO2 | ✅ | GPIO_S5_28 is connected to EXP_GPIO2 net for expansion GPIO. | | K24 | GPIO_S5_22 | GPIO_D2_LED_CTRL | ✅ | GPIO_S5_22 is connected to GPIO_D2_LED_CTRL net for LED control. | | K26 | ~PMC_BATLOW | PMC_BATLOW | ✅ | PMC_BATLOW# is connected with 20K pull-up to +V1P8A for battery low detection. | | M18 | GPIO_S5_26 | XDP_H_OBSDATA_A3 | ✅ | GPIO_S5_26 is connected to XDP_H_OBSDATA_A3 net for debug observation data. | | M20 | GPIO_S5_24 | XDP_H_OBSDATA_A1 | ✅ | GPIO_S5_24 is connected to XDP_H_OBSDATA_A1 net for debug observation data. | | M22 | GPIO_S5_29 | EXP_GPIO3 | ✅ | GPIO_S5_29 is connected to EXP_GPIO3 net for expansion GPIO. | | M24 | GPIO_S5_30 | EXP_GPIO4 | ✅ | GPIO_S5_30 is connected to EXP_GPIO4 net for expansion GPIO. | | N24 | GPIO_S5_23 | XDP_H_OBSDATA_A0 | ✅ | GPIO_S5_23 is connected to XDP_H_OBSDATA_A0 net for debug observation data. | | N26 | GPIO_RCOMP | GPIO_RCOMP | ✅ | GPIO_RCOMP is connected to 49.9-ohm compensation resistor to ground. | | BA28 | SIO_SPI_MISO | SOC_SIO_SPI_MISO | ✅ | SIO_SPI_MISO is connected to SIO SPI master in slave out signal. | | BA34 | ~SIO_UART1_RTS | SIO_UART1_RTSB | ✅ | SIO_UART1_RTS is connected to UART1 request to send signal. | | AD10 | RESERVED_AD10 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AD12 | RESERVED_AD12 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AD9 | RESERVED_AD9 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AD13 | ICLK_RCOMP | ICLK_RCOMP | ✅ | ICLK_RCOMP is connected to 47.5-ohm compensation resistor to ground. | | AD14 | ICLK_ICOMP | ICLK_ICOMP | ✅ | ICLK_ICOMP is connected to 4.02K-ohm compensation resistor to ground. | | BD32 | ~SIO_UART2_RTS | | ✅ | SIO_UART2_RTS is not connected, indicating UART2 hardware flow control is not used. | | BD34 | SIO_UART2_TXD | SIO_UART2_TXD | ✅ | SIO_UART2_TXD is connected to UART2 transmit data signal. | | AF4 | PCIE_CLKP_00 | | ✅ | PCIE_CLKP_00 and PCIE_CLKN_00 are not connected, indicating PCIe port 0 is not used. | | AF6 | PCIE_CLKN_00 | | ✅ | PCIE_CLKP_00 and PCIE_CLKN_00 are not connected, indicating PCIe port 0 is not used. | | AF7 | PCIE_CLKP_11 | | ✅ | PCIE_CLKP_11 and PCIE_CLKN_11 are not connected, indicating PCIe port 1 is not used. | | AF9 | PCIE_CLKN_11 | | ✅ | PCIE_CLKP_11 and PCIE_CLKN_11 are not connected, indicating PCIe port 1 is not used. | | BF32 | ~SIO_UART2_CTS | | ✅ | SIO_UART2_CTS is not connected, indicating UART2 hardware flow control is not used. | | BF34 | SIO_UART2_RXD | SIO_UART2_RXD | ✅ | SIO_UART2_RXD is connected to UART2 receive data signal. | | BG9 | ~PMC_RSTBTN | PMC_RSTBTN | ✅ | PMC_RSTBTN# is connected to reset button input signal. | | AH10 | ICLK_OSCOUT | XTAL25_OUT | ✅ | ICLK_OSCOUT is connected to 25 MHz crystal with 27pF load capacitor. | | AH12 | ICLK_OSCIN | XTAL25_IN | ✅ | ICLK_OSCIN is connected to 25 MHz crystal with 27pF load capacitor. | | BH4 | PMC_PLT_CLK_22 | | ✅ | PMC_PLT_CLK_22 is not connected, indicating platform clock 2 is not used. | | BH5 | PMC_PLT_CLK_11 | | ✅ | PMC_PLT_CLK_11 is not connected, indicating platform clock 1 is not used. | | BH6 | PMC_PLT_CLK_44 | | ✅ | PMC_PLT_CLK_44 is not connected, indicating platform clock 4 is not used. | | BH7 | PMC_PLT_CLK_00 | | ✅ | PMC_PLT_CLK_00 is not connected, indicating platform clock 0 is not used. | | BH8 | PMC_PLT_CLK_33 | I2S_MCLK | ✅ | PMC_PLT_CLK_33 is connected to I2S_MCLK net for I2S master clock. | | AK4 | PCIE_CLKN_22 | PCIE_CLK-N2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 are connected to PCIe port 2 clock outputs. | | AK6 | PCIE_CLKP_22 | PCIE_CLK-P2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 are connected to PCIe port 2 clock outputs. | | BJ9 | PMC_PLT_CLK_55 | | ✅ | PMC_PLT_CLK_55 is not connected, indicating platform clock 5 is not used. | | AM4 | PCIE_CLKN_33 | mPCIE_REFCLK_N | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 are connected to mini PCIe reference clock outputs. | | AM6 | PCIE_CLKP_33 | mPCIE_REFCLK_P | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 are connected to mini PCIe reference clock outputs. | | AM10 | RESERVED_AM10 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AM9 | RESERVED_AM9 | | ✅ | Reserved pins are correctly left unconnected per datasheet requirements. | | AT32 | SIO_PWM_11 | SOC_PWM1 | ✅ | SIO_PWM_11 is connected to SOC_PWM1 net for PWM output 1. | | AT34 | RESERVED | | ✅ | Reserved pin is correctly left unconnected per datasheet requirements. | | AU32 | SIO_PWM_00 | SOC_PWM0 | ✅ | SIO_PWM_00 is connected to SOC_PWM0 net for PWM output 0. | | AU34 | SIO_UART1_RXD | SIO_UART1_RXD | ✅ | SIO_UART1_RXD is connected to UART1 receive data signal. | | AV32 | ~SIO_SPI_CS | SOC_SIO_SPI_CS1 | ✅ | SIO_SPI_CS is connected to SIO SPI chip select signal. | | AV34 | SIO_UART1_TXD | SIO_UART1_TXD | ✅ | SIO_UART1_TXD is connected to UART1 transmit data signal. | | AY28 | SIO_SPI_MOSI | SOC_SIO_SPI_MOSI | ✅ | SIO_SPI_MOSI is connected to SIO SPI master out slave in signal. | | AY30 | SIO_SPI_CLK | SOC_SIO_SPI_CLK | ✅ | SIO_SPI_CLK is connected to SIO SPI clock signal. | | AY34 | ~SIO_UART1_CTS | SIO_UART1_CTSB | ✅ | SIO_UART1_CTS is connected to UART1 clear to send signal. | </details> <details> <summary><b>U19</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the 1.8V supply for the A-side of the level shifter. | | 2 | A1 | PMC_PLTRST_R_V1P8 | ✅ | A1 is correctly connected to PMC_PLTRST_R_V1P8, which is the 1.8V platform reset signal from the CPU. | | 3 | A2 | PMC_SUSCLK0 | ✅ | A2 is correctly connected to PMC_SUSCLK0, which is the suspend clock signal from the CPU at 1.8V level. | | 4 | A3 | PMC_SLP_S4_L | ✅ | A3 is correctly connected to PMC_SLP_S4_L, which is the active-low sleep S4 state signal from the CPU at 1.8V level. | | 5 | A4 | PMC_SLP_S3_L | ✅ | A4 is correctly connected to PMC_SLP_S3_L, which is the active-low sleep S3 state signal from the CPU at 1.8V level. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SLP_S3_L | ✅ | B4 is correctly connected to SLP_S3_L, which is the 3.3V level-shifted version of the sleep S3 state signal. | | 8 | B3 | SLP_S4_L | ✅ | B3 is correctly connected to SLP_S4_L, which is the 3.3V level-shifted version of the sleep S4 state signal. | | 9 | B2 | SUSCLK_3P3 | ✅ | B2 is correctly connected to SUSCLK_3P3, which is the 3.3V level-shifted version of the suspend clock signal. | | 10 | B1 | PMC_PLTRST_L | ✅ | B1 is correctly connected to PMC_PLTRST_L, which is the 3.3V level-shifted version of the platform reset signal. | | 11 | VCCB | PWR_BUF1 | ✅ | VCCB is correctly connected to PWR_BUF1, which is connected through R26 (0 ohm) to +3VSB, providing the 3.3V supply for the B-side of the level shifter. | | 12 | OE | PMC_OE | ✅ | OE is correctly connected to PMC_OE, which is pulled up to +V1P8A through R57 (2.2K), enabling the level shifter when the 1.8V rail is present. | </details> <details> <summary><b>Y1</b> - 145-0004789 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/145-0004789) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BRTCX2 | ✅ | Crystal terminal connected to BRTCX2 (CPU1 pin A9) with 18pF load capacitor C42 and 10M feedback resistor R76. | | 2 | 2 | BRTCX1 | ✅ | Crystal terminal connected to BRTCX1 (CPU1 pin C9) with 18pF load capacitor C43 and 10M feedback resistor R76. | </details> <details> <summary><b>BH1</b> - 353-0003073 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/353-0003073) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +VBAT | ✅ | Positive battery terminals connected to +VBAT net, which supplies backup power to the RTC circuit through current-limiting resistor R278 and OR-ing diode D5. | | 2 | P2 | +VBAT | ✅ | Positive battery terminals connected to +VBAT net, which supplies backup power to the RTC circuit through current-limiting resistor R278 and OR-ing diode D5. | | 3 | N | GND | ✅ | Negative battery terminal correctly connected to ground. | </details> <details> <summary><b>D5</b> - 4536-0009 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | +PS_3VSB | ✅ | Anode connected to +PS_3VSB (3.3V standby supply), providing primary power to RTC when system is on. | | A2 | A2 | +VBAT_R | ✅ | Anode connected to +VBAT_R (battery voltage through current-limiting resistor), providing backup power to RTC when system is off. | | C | C | +RTCVCC | ✅ | Common cathode connected to +RTCVCC, supplying power to the RTC circuit from either system power or battery backup. | </details> <details> <summary><b>Y2</b> - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XTAL25_IN | ✅ | Crystal input terminal correctly connected to CPU oscillator input (ICLK_OSCIN) with appropriate 27pF load capacitor and 1M feedback resistor. | | 2 | 2 | GND | ✅ | Ground pin correctly connected to GND net for crystal ground reference. | | 3 | 3 | XTAL25_OUT | ✅ | Crystal output terminal correctly connected to CPU oscillator output (ICLK_OSCOUT) with appropriate 27pF load capacitor and 1M feedback resistor. | | 4 | 4 | GND | ✅ | Ground pin correctly connected to GND net for crystal ground reference. | </details> <details> <summary><b>D10</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | 3VSB_OK | ✅ | Anode 1 connected to 3VSB_OK signal, which monitors the 3VSB power rail status. This input to the diode OR gate will pull PS_OUT_L low when 3VSB is not ready. | | A2 | A2 | PMC_PWRBTN | ✅ | Anode 2 connected to PMC_PWRBTN signal from the SoC. This active-low power button input will pull PS_OUT_L low when the power button is pressed. | | C | C | PS_OUT_L | ✅ | Common cathode output connected to PS_OUT_L. This active-low signal will be asserted when either 3VSB is not ready or the power button is pressed. | </details> <details> <summary><b>D3</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE | ✅ | Cathodes tied together and connected to PMC_PCIE_WAKE net with 2.2K pull-up to +3VSB. This configuration is typical for a common-anode dual Schottky diode used in parallel. | | 2 | 2 | PMC_PCIE_WAKE | ✅ | Cathodes tied together and connected to PMC_PCIE_WAKE net with 2.2K pull-up to +3VSB. This configuration is typical for a common-anode dual Schottky diode used in parallel. | | 3 | 3 | PMC_PCIE_WAKE_R | ✅ | Common anode connected to PMC_PCIE_WAKE_R net with 1K pull-up to +V1P8A and to CPU wake input. Provides unidirectional level translation from 3.3V to 1.8V domain. | </details> <details> <summary><b>J7</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_17 | ✅ | Pin 1 connects to GPIO_S5_17 from the CPU (pin J24), with a 10K pull-up resistor (R183) to +V1P8S. This forms one side of a configuration jumper. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the jumper. When the jumper is installed, it pulls GPIO_S5_17 low. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A7 | USB_HSIC_RCOMP | USB_HSIC0_RCOMP | ✅ | USB HSIC compensation resistor correctly connected to 45.3 ohm resistor to ground. | | B4 | USB_HSIC0_DATA | | ✅ | USB HSIC0 data pin is not connected, indicating HSIC port 0 is not used in this design. | | B5 | USB_HSIC0_STROBE | | ✅ | USB HSIC0 strobe pin is not connected, indicating HSIC port 0 is not used in this design. | | B12 | GPIO_S5_43 | | ✅ | GPIO_S5_43 (USB_ULPI_REFCLK) is not connected, indicating ULPI interface is not used. | | B20 | ~USB_OC_11 | SOC_USB_HOST_OC1 | ✅ | USB overcurrent detect for port 1 correctly connected with 10K pull-up to +V1P8A. | | C7 | USB_RCOMPI | USB_RCOMP | ✅ | USB compensation resistor input correctly connected to 45.3 ohm resistor to ground. | | C20 | ~USB_OC_00 | SOC_USB_HOST_OC0 | ✅ | USB overcurrent detect for port 0 correctly connected with 10K pull-up to +V1P8A. | | D2 | USB_HSIC1_STROBE | | ✅ | USB HSIC1 strobe pin is not connected, indicating HSIC port 1 is not used. | | D4 | USB3_RXP0 | USB3_RXP0 | ✅ | USB3 receive positive differential signal for SuperSpeed operation. | | D6 | USB_RCOMPO | USB_RCOMP | ✅ | USB compensation resistor output correctly connected to 45.3 ohm resistor to ground. | | D10 | ICLK_USB_TERM_1 | ICLK_USB_TERM_0 | ✅ | USB termination correctly connected to 1K resistor to ground. Net naming is confusing but functionally correct. | | E2 | USB_HSIC1_DATA | | ✅ | USB HSIC1 data pin is not connected, indicating HSIC port 1 is not used. | | E3 | USB3_RXN0 | USB3_RXN0 | ✅ | USB3 receive negative differential signal for SuperSpeed operation. | | F10 | ICLK_USB_TERMN | ICLK_USB_TERM_1 | ✅ | USB termination correctly connected to 1K resistor to ground. Net naming is confusing but functionally correct. | | G2 | GPIO_S5_31 | | ✅ | GPIO_S5_31 (USB_ULPI_CLK) is not connected, indicating ULPI interface is not used. | | G14 | USB_DN1 | USB_DN1 | ✅ | USB 2.0 data negative for port 1. | | H3 | GPIO_S5_42 | | ✅ | GPIO_S5_42 (USB_ULPI_STP) is not connected, indicating ULPI interface is not used. | | H4 | RESERVED_H4 | | ✅ | Reserved pin is not connected per datasheet guidance. | | H5 | RESERVED_H5 | | ✅ | Reserved pin is not connected per datasheet guidance. | | H7 | RESERVED_H7 | | ✅ | Reserved pin is not connected per datasheet guidance. | | H8 | RESERVED_H8 | | ✅ | Reserved pin is not connected per datasheet guidance. | | H10 | USB_DN3 | | ✅ | USB 2.0 data negative for port 3 is not connected, indicating port 3 is not used. | | J3 | GPIO_S5_40 | | ✅ | GPIO_S5_40 (USB_ULPI_DIR) is not connected, indicating ULPI interface is not used. | | J12 | USB_DN2 | USB_HOST_DN | ✅ | USB 2.0 data negative for port 2 (host port). | | J14 | USB_DP1 | USB_DP1 | ✅ | USB 2.0 data positive for port 1. | | K2 | GPIO_S5_34 | | ✅ | GPIO_S5_34 (USB_ULPI_DATA[2]) is not connected, indicating ULPI interface is not used. | | K3 | GPIO_S5_35 | | ✅ | GPIO_S5_35 (USB_ULPI_DATA[3]) is not connected, indicating ULPI interface is not used. | | K6 | USB3_TXP0 | USB3_TXP0 | ✅ | USB3 transmit positive differential signal for SuperSpeed operation. | | K7 | USB3_TXN0 | USB3_TXN0 | ✅ | USB3 transmit negative differential signal for SuperSpeed operation. | | K10 | USB_DP3 | | ✅ | USB 2.0 data positive for port 3 is not connected, indicating port 3 is not used. | | K12 | USB_DP2 | USB_HOST_DP | ✅ | USB 2.0 data positive for port 2 (host port). | | K16 | USB_DN0 | USB_DN0 | ✅ | USB 2.0 data negative for port 0. | | L1 | GPIO_S5_33 | | ✅ | GPIO_S5_33 (USB_ULPI_DATA[1]) is not connected, indicating ULPI interface is not used. | | L3 | GPIO_S5_39 | | ✅ | GPIO_S5_39 (USB_ULPI_DATA[7]) is not connected, indicating ULPI interface is not used. | | M2 | GPIO_S5_36 | | ✅ | GPIO_S5_36 (USB_ULPI_DATA[4]) is not connected, indicating ULPI interface is not used. | | M3 | GPIO_S5_32 | | ✅ | GPIO_S5_32 (USB_ULPI_DATA[0]) is not connected, indicating ULPI interface is not used. | | M4 | RESERVED_M4 | | ✅ | Reserved pin is not connected per datasheet guidance. | | M6 | RESERVED_M6 | | ✅ | Reserved pin is not connected per datasheet guidance. | | M7 | RESERVED_M7 | | ✅ | Reserved pin is not connected per datasheet guidance. | | M9 | RESERVED_M9 | | ✅ | Reserved pin is not connected per datasheet guidance. | | M10 | RESERVED_M10 | | ✅ | Reserved pin is not connected per datasheet guidance. | | M12 | USB3_REXT0 | USB3_REXT0 | ✅ | USB3 external resistor correctly connected to 1.24K resistor to ground. | | M13 | USB_PLL_MON | USB_PLL_MON | ✅ | USB PLL monitor signal connected to DNI test point for debug access. | | M16 | USB_DP0 | USB_DP0 | ✅ | USB 2.0 data positive for port 0. | | N3 | GPIO_S5_37 | | ✅ | GPIO_S5_37 (USB_ULPI_DATA[5]) is not connected, indicating ULPI interface is not used. | | P2 | GPIO_S5_38 | | ✅ | GPIO_S5_38 (USB_ULPI_DATA[6]) is not connected, indicating ULPI interface is not used. | | P3 | GPIO_S5_41 | | ✅ | GPIO_S5_41 (USB_ULPI_NXT) is not connected, indicating ULPI interface is not used. | | P6 | RESERVED_P6 | | ✅ | Reserved pin is not connected per datasheet guidance. | | P7 | RESERVED_P7 | | ✅ | Reserved pin is not connected per datasheet guidance. | | P10 | RESERVED_P10 | | ✅ | Reserved pin is not connected per datasheet guidance. | | P12 | RESERVED_P12 | | ✅ | Reserved pin is not connected per datasheet guidance. | | BC12 | GPIO_S0_SC_56 | GPIO_S0_SC_56 | ✅ | GPIO_S0_SC_56 is connected but not used in visible circuitry on this page. | | BC14 | GPIO_S0_SC_58 | HDMI_CEC | ✅ | GPIO_S0_SC_58 is configured as HDMI CEC signal. | | BC16 | GPIO_S0_SC_61 | PCU_UART3_RXD | ✅ | GPIO_S0_SC_61 is configured as UART3 RXD with level shifting to 3.3V debug connector. | | BD12 | GPIO_S0_SC_55 | GPIO_S0_SC_55 | ✅ | GPIO_S0_SC_55 is connected to a DNI test point. | | BD14 | GPIO_S0_SC_57 | PCU_UART3_TXD | ✅ | GPIO_S0_SC_57 is configured as UART3 TXD with level shifting to 3.3V debug connector. | | BD16 | GPIO_S0_SC_60 | | ✅ | GPIO_S0_SC_60 is not connected. | | BF14 | GPIO_S0_SC_59 | | ✅ | GPIO_S0_SC_59 is not connected. | | BF18 | LPC_RCOMP | LPC_RCOMP | ✅ | LPC compensation resistor correctly connected to 49.9 ohm resistor to ground. | | BF27 | SIO_I2C4_DATA | | ✅ | I2C4 data pin is not connected, indicating I2C4 interface is not used. | | BG11 | ~PCU_SMB_ALERT | PCU_SMB_ALERT | ✅ | SMBus alert signal correctly connected with 2.2K pull-up and routed to LAN SMBus. | | BG12 | PCU_SMB_DATA | PCU_SMB_DATA | ✅ | SMBus data signal correctly connected with 2.2K pull-up and level shifted to DDR SMBus. | | BG13 | ILB_LPC_SERIRQ | | ✅ | LPC SERIRQ signal is not connected, indicating LPC interface is not used. | | BG14 | ILB_LPC_AD_33 | | ✅ | LPC address/data bit 3 is not connected, indicating LPC interface is not used. | | BG15 | ILB_LPC_CLK_00 | | ✅ | LPC clock 0 is not connected, indicating LPC interface is not used. | | BG16 | ~ILB_LPC_CLKRUN | | ✅ | LPC CLKRUN signal is not connected, indicating LPC interface is not used. | | BG17 | ~ILB_LPC_FRAME | | ✅ | LPC FRAME signal is not connected, indicating LPC interface is not used. | | BG23 | SIO_I2C0_CLK | | ✅ | I2C0 clock pin is not connected, indicating I2C0 interface is not used. | | BG24 | SIO_I2C1_DATA | SIO_I2C1_SDA | ✅ | I2C1 data signal connected to DNI test point for debug access. | | BG25 | SIO_I2C2_DATA | | ✅ | I2C2 data pin is not connected, indicating I2C2 interface is not used. | | BG26 | SIO_I2C3_DATA | | ✅ | I2C3 data pin is not connected, indicating I2C3 interface is not used. | | BG27 | SIO_I2C4_CLK | | ✅ | I2C4 clock pin is not connected, indicating I2C4 interface is not used. | | BG28 | SIO_I2C5_CLK | SI0_I2C5_SCL | ✅ | I2C5 clock signal correctly connected with 22 ohm series resistor for signal integrity. | | BG29 | SIO_I2C6_CLK | SI0_I2C6_SCL | ✅ | I2C6 clock signal correctly connected with 22 ohm series resistor for signal integrity. | | BG30 | GPIO_S0_SC_093 | TP10_NET | ✅ | GPIO_S0_SC_093 is intentionally grounded through 0 ohm resistor as indicated by schematic notes. | | BH10 | PCU_SMB_CLK | PCU_SMB_CLK | ✅ | SMBus clock signal correctly connected with 2.2K pull-up and level shifted to DDR SMBus. | | BH12 | ILB_8254_SPKR | ILB_8254_SPKR | ✅ | Speaker output signal is connected for system audio. | | BH14 | ILB_LPC_CLK_11 | | ✅ | LPC clock 1 is not connected, indicating LPC interface is not used. | | BH16 | ILB_LPC_AD_00 | | ✅ | LPC address/data bit 0 is not connected, indicating LPC interface is not used. | | BH22 | SIO_I2C0_DATA | | ✅ | I2C0 data pin is not connected, indicating I2C0 interface is not used. | | BH24 | SIO_I2C1_CLK | SIO_I2C1_SCL | ✅ | I2C1 clock signal connected to DNI test point for debug access. | | BH26 | SIO_I2C3_CLK | | ✅ | I2C3 clock pin is not connected, indicating I2C3 interface is not used. | | BH28 | SIO_I2C5_DATA | SI0_I2C5_SDA | ✅ | I2C5 data signal correctly connected with 22 ohm series resistor for signal integrity. | | BH30 | GPIO_S0_SC_092 | TP9_NET | ✅ | GPIO_S0_SC_092 is intentionally grounded through 0 ohm resistor as indicated by schematic notes. | | BJ13 | ILB_LPC_AD_22 | | ✅ | LPC address/data bit 2 is not connected, indicating LPC interface is not used. | | BJ17 | ILB_LPC_AD_11 | | ✅ | LPC address/data bit 1 is not connected, indicating LPC interface is not used. | | BJ25 | SIO_I2C2_CLK | | ✅ | I2C2 clock pin is not connected, indicating I2C2 interface is not used. | | BJ29 | SIO_I2C6_DATA | SI0_I2C6_SDA | ✅ | I2C6 data signal correctly connected with 22 ohm series resistor for signal integrity. | </details> <details> <summary><b>R48</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF2_PWR | ✅ | 0 ohm resistor connecting BUF2_PWR to +VCC3, providing 3.3V supply to the VCCB pin of level translator U5. This connection is correct. | | 2 | 2 | +VCC3 | ✅ | 0 ohm resistor connecting BUF2_PWR to +VCC3, providing 3.3V supply to the VCCB pin of level translator U5. This connection is correct. | </details> <details> <summary><b>U5</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DDR_SMB_CLK | ✅ | B2 pin connected to DDR_SMB_CLK net, which is the 3.3V side of the SMBus clock channel 2. This connection is correct for translating the clock signal to the higher voltage domain. | | 2 | GND | GND | ✅ | GND pin correctly connected to the ground net. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin connected to +V1P8S (1.8V supply), which is correct as the A-side reference voltage for the level translator. | | 4 | A2 | PCU_SMB_CLK | ✅ | A2 pin connected to PCU_SMB_CLK, which is the 1.8V side of the SMBus clock channel 2. This connection is correct for translating the clock signal from the CPU. | | 5 | A1 | PCU_SMB_DATA | ✅ | A1 pin connected to PCU_SMB_DATA, which is the 1.8V side of the SMBus data channel 1. This connection is correct for translating the data signal from the CPU. | | 6 | OE | PCU_SMB_BUFF_ENB | ✅ | OE pin connected to PCU_SMB_BUFF_ENB with a pullup to +V1P8S. This enables the level translator and allows CPU control of the buffer enable. | | 7 | VCCB | BUF2_PWR | ✅ | VCCB pin connected to BUF2_PWR, which is supplied by +VCC3 (3.3V) through R48. This is correct as the B-side reference voltage for the level translator. | | 8 | B1 | DDR_SMB_DATA | ✅ | B1 pin connected to DDR_SMB_DATA net, which is the 3.3V side of the SMBus data channel 1. This connection is correct for translating the data signal to the higher voltage domain. | </details> <details> <summary><b>R51</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF3_PWR | ✅ | R51 is a 0 ohm resistor connecting +3VSB to BUF3_PWR, which powers the B-side (VCCB) of level shifter U6. The 0 ohm resistor allows for easy disconnection if needed. | | 2 | 2 | +3VSB | ✅ | R51 is a 0 ohm resistor connecting +3VSB to BUF3_PWR, which powers the B-side (VCCB) of level shifter U6. The 0 ohm resistor allows for easy disconnection if needed. | </details> <details> <summary><b>U6</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DBG_UART3_TXD | ✅ | B2 pin connects to DBG_UART3_TXD, which routes through R819 (330 ohm series resistor) to the debug connector J4 pin 5. This is the 3.3V side of the UART transmit channel from the CPU. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the reference ground for the level shifter IC. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin is connected to +V1P8S (1.8V supply), providing the reference voltage for the A-side (CPU side) of the level shifter. Properly decoupled by C30 (0.1uF). | | 4 | A2 | PCU_UART3_TXD | ✅ | A2 pin connects to PCU_UART3_TXD, which connects to CPU1 pin BD14 (GPIO_S0_SC_57). This is the 1.8V side of the UART transmit channel from the CPU. | | 5 | A1 | PCU_UART3_RXD | ✅ | A1 pin connects to PCU_UART3_RXD, which connects to CPU1 pin BC16 (GPIO_S0_SC_61). This is the 1.8V side of the UART receive channel to the CPU. | | 6 | OE | LSENB | ✅ | OE pin is connected to LSENB, which is pulled high to +V1P8S through R52 (2.2K ohm). This permanently enables the level shifter, which is appropriate for an always-available debug interface. | | 7 | VCCB | BUF3_PWR | ✅ | VCCB pin is connected to BUF3_PWR, which connects through R51 (0 ohm) to +3VSB (3.3V standby supply). Properly decoupled by C31 (0.1uF). This provides the reference voltage for the B-side (debug connector side). | | 8 | B1 | DBG_UART3_RXD | ✅ | B1 pin connects to DBG_UART3_RXD, which connects to J4 pin 4 (debug connector). This is the 3.3V side of the UART receive channel from the debug connector. R50 (100K) provides a weak pull-down. | </details> <details> <summary><b>J4</b> - SIP6_RA ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004869) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net, providing common reference for the serial interface. | | 2 | 2 | | ✅ | Pin 2 is unconnected, which is acceptable as hardware flow control is not implemented for this debug serial port. | | 3 | 3 | | ✅ | Pin 3 is unconnected, which is acceptable for this USB-to-TTL serial cable interface. The pin typically carries VCC on standard FTDI-style cables but is not required for basic UART operation. | | 4 | 4 | DBG_UART3_RXD | ✅ | Pin 4 correctly connects to DBG_UART3_RXD, which receives data into the CPU after level shifting from 3.3V to 1.8V through U6. | | 5 | 5 | DBG_UART3_TXD_R | ✅ | Pin 5 correctly connects to DBG_UART3_TXD_R, which transmits data from the CPU after level shifting from 1.8V to 3.3V through U6, with R819 providing series termination. | | 6 | 6 | | ✅ | Pin 6 is unconnected, which is acceptable as hardware flow control is not implemented for this debug serial port. | </details> <details> <summary><b>R241</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPC_RCOMP | ✅ | LPC bus compensation resistor connection. This pin correctly connects to the CPU's LPC_RCOMP pin (BF18) for impedance calibration. | | 2 | 2 | GND | ✅ | Ground connection for LPC compensation resistor. This pin correctly connects to the ground plane. | </details> <details> <summary><b>R212</b> - 110-0004478 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004478) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_REXT0 | ✅ | USB 3.0 external reference resistor connection. This pin correctly connects to the CPU's USB3_REXT0 pin (M12) for PHY calibration. | | 2 | 2 | GND | ✅ | Ground connection for USB 3.0 external reference resistor. This pin correctly connects to the ground plane. | </details> <details> <summary><b>R185</b> - 110-0004472 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for USB 2.0 compensation resistor. This pin correctly connects to the ground plane. | | 2 | 2 | USB_RCOMP | ✅ | USB 2.0 compensation resistor connection. This pin correctly connects to both USB_RCOMPO (D6) and USB_RCOMPI (C7) pins of the CPU, which are tied together for impedance calibration. | </details> <details> <summary><b>R77</b> - 110-0004472 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for USB HSIC compensation resistor. This pin correctly connects to the ground plane. | | 2 | 2 | USB_HSIC0_RCOMP | ✅ | USB HSIC compensation resistor connection. This pin correctly connects to the CPU's USB_HSIC_RCOMP pin (A7) for impedance calibration. | </details> <details> <summary><b>R12</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SCL | ✅ | 22 ohm series resistor on I2C6 SCL line between SOC pin (SI0_I2C6_SCL) and external bus (I2C6_SCL). This provides signal conditioning and damping for the I2C bus. | | 2 | 2 | I2C6_SCL | ✅ | 22 ohm series resistor on I2C6 SCL line between SOC pin (SI0_I2C6_SCL) and external bus (I2C6_SCL). This provides signal conditioning and damping for the I2C bus. | </details> <details> <summary><b>R11</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SDA | ✅ | 22 ohm series resistor on I2C6 SDA line between SOC pin (SI0_I2C6_SDA) and external bus (I2C6_SDA). This provides signal conditioning and damping for the I2C bus. | | 2 | 2 | I2C6_SDA | ✅ | 22 ohm series resistor on I2C6 SDA line between SOC pin (SI0_I2C6_SDA) and external bus (I2C6_SDA). This provides signal conditioning and damping for the I2C bus. | </details> <details> <summary><b>R269</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SDA | ✅ | 22 ohm series resistor on I2C5 SDA line between SOC pin (SI0_I2C5_SDA) and external bus (I2C5_SDA). This provides signal conditioning and damping for the I2C bus. | | 2 | 2 | I2C5_SDA | ✅ | 22 ohm series resistor on I2C5 SDA line between SOC pin (SI0_I2C5_SDA) and external bus (I2C5_SDA). This provides signal conditioning and damping for the I2C bus. | </details> <details> <summary><b>R270</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SCL | ✅ | 22 ohm series resistor on I2C5 SCL line between SOC pin (SI0_I2C5_SCL) and external bus (I2C5_SCL). This provides signal conditioning and damping for the I2C bus. | | 2 | 2 | I2C5_SCL | ✅ | 22 ohm series resistor on I2C5 SCL line between SOC pin (SI0_I2C5_SCL) and external bus (I2C5_SCL). This provides signal conditioning and damping for the I2C bus. | </details> <details> <summary><b>R842</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-SMB-ALERT# | ✅ | Pin 1 connects to LAN-SMB-ALERT#, routing the SMBus alert signal to a LAN interface. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Pin 2 connects to PCU_SMB_ALERT, which is the active-low SMBus alert signal from CPU1 with a 10K pull-up to +V1P8S via R75. | </details> <details> <summary><b>R841</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_CLK | ✅ | Pin 1 connects to DDR_SMB_CLK, which is the B-side output of level shifter U5 and has a 2.2K pull-up to +VCC3 via R44. | | 2 | 2 | LAN-SMB-CLK | ✅ | Pin 2 connects to LAN-SMB-CLK, routing the SMBus clock signal to a LAN interface, pairing with R840 for the complete SMBus interface. | </details> <details> <summary><b>R840</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_DATA | ✅ | Pin 1 connects to DDR_SMB_DATA, which is the B-side output of level shifter U5 and has a 2.2K pull-up to +VCC3 via R47. | | 2 | 2 | LAN-SMB-DATA | ✅ | Pin 2 connects to LAN-SMB-DATA, routing the SMBus data signal to a LAN interface. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A48 | DRAM_VDD_S4 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | AK38 | DRAM_VDD_S4_AK38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | AM38 | DRAM_VDD_S4_AM38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | AV41 | DRAM_VDD_S4_AV41 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | AV42 | DRAM_VDD_S4_AV42 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | BB46 | DRAM_VDD_S4_BB46 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | BD49 | DRAM_VDD_S4_BD49 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | BD52 | DRAM_VDD_S4_BD52 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | BD53 | DRAM_VDD_S4_BD53 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | BF44 | DRAM_VDD_S4_BF44 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | BG51 | DRAM_VDD_S4_BG51 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | BJ48 | DRAM_VDD_S4_BJ48 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | C51 | DRAM_VDD_S4_C51 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | D44 | DRAM_VDD_S4_D44 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | F49 | DRAM_VDD_S4_F49 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | F52 | DRAM_VDD_S4_F52 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | F53 | DRAM_VDD_S4_F53 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | H46 | DRAM_VDD_S4_H46 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | M41 | DRAM_VDD_S4_M41 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | M42 | DRAM_VDD_S4_M42 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | V38 | DRAM_VDD_S4_V38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | Y38 | DRAM_VDD_S4_Y38 | +VDIMM | ✅ | DRAM_VDD_S4 power supply pins correctly connected to +VDIMM rail providing 1.35V for DDR3L memory. Adequate decoupling capacitance provided with mix of 10uF, 1uF, and 0.1uF capacitors. | | N28 | CORE_VSS_SENSE_N28 | VSS_SENSE | ✅ | CORE_VSS_SENSE pin correctly connected to VSS_SENSE net for ground reference sensing. This enables accurate voltage regulation by providing ground reference at the processor. | | P28 | CORE_VCC_SENSE_P28 | VCC_SENSE | ✅ | CORE_VCC_SENSE pin correctly connected to VCC_SENSE net for core voltage sensing. This enables accurate voltage regulation by sensing core voltage at the processor. | | AA22 | TP2_CORE_VCC_S0IX | $9N615 | ✅ | Test point pin TP2_CORE_VCC_S0IX connected to net $9N615 with DNI test point TP2. This provides access to monitor core VCC voltage in S0IX state for debug purposes. | | AA24 | UNCORE_VNN_S3_AA24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AC22 | UNCORE_VNN_S3_AC22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AC24 | UNCORE_VNN_S3_AC24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AD22 | UNCORE_VNN_S3_AD22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AD24 | UNCORE_VNN_S3_AD24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AF22 | UNCORE_VNN_S3_AF22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AF24 | UNCORE_VNN_S3_AF24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AG22 | UNCORE_VNN_S3_AG22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AG24 | UNCORE_VNN_S3_AG24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AJ22 | UNCORE_VNN_S3_AJ22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AJ24 | UNCORE_VNN_S3_AJ24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AK22 | UNCORE_VNN_S3_AK22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AK24 | UNCORE_VNN_S3_AK24 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AK25 | UNCORE_VNN_S3_AK25 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AK27 | UNCORE_VNN_S3_AK27 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AK29 | UNCORE_VNN_S3_AK29 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AK30 | UNCORE_VNN_S3_AK30 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AK32 | UNCORE_VNN_S3_AK32 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AM22 | UNCORE_VNN_S3_AM22 | +VGFX | ✅ | UNCORE_VNN_S3 power supply pins correctly connected to +VGFX rail providing graphics/uncore voltage. Adequate decoupling with 113uF total capacitance including 22uF bulk and 1uF high-frequency capacitors. | | AA27 | CORE_VCC_S0IX_AA27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AA29 | CORE_VCC_S0IX_AA29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AA30 | CORE_VCC_S0IX_AA30 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AC27 | CORE_VCC_S0IX_AC27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AC29 | CORE_VCC_S0IX_AC29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AC30 | CORE_VCC_S0IX_AC30 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AD27 | CORE_VCC_S0IX_AD27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AD29 | CORE_VCC_S0IX_AD29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AD30 | CORE_VCC_S0IX_AD30 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AF27 | CORE_VCC_S0IX_AF27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AF29 | CORE_VCC_S0IX_AF29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AG27 | CORE_VCC_S0IX_AG27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AG29 | CORE_VCC_S0IX_AG29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | AG30 | CORE_VCC_S0IX_AG30 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | P26 | CORE_VCC_S0IX_P26 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | P27 | CORE_VCC_S0IX_P27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | U27 | CORE_VCC_S0IX_U27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | U29 | CORE_VCC_S0IX_U29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | V27 | CORE_VCC_S0IX_V27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | V29 | CORE_VCC_S0IX_V29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | V30 | CORE_VCC_S0IX_V30 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | Y27 | CORE_VCC_S0IX_Y27 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | Y29 | CORE_VCC_S0IX_Y29 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | Y30 | CORE_VCC_S0IX_Y30 | +VCORE | ✅ | CORE_VCC_S0IX power supply pins correctly connected to +VCORE rail providing processor core voltage. Well-decoupled with 130.5uF total capacitance including bulk, mid-frequency, and high-frequency capacitors. | | BB8 | UNCORE_VNN_SENSE | VCCGT_SENSE | ✅ | UNCORE_VNN_SENSE pin correctly connected to VCCGT_SENSE net for voltage regulator feedback. This enables accurate voltage regulation by sensing voltage at the processor. | | AD38 | DRAM_VDD_S4_AD38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 clock power pins correctly connected to DRAM_VDD_CLK rail, which is isolated from main +VDIMM through 0-ohm jumper R275. This provides clean power for DDR3L clock outputs with dedicated decoupling. | | AF38 | DRAM_VDD_S4_AF38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 clock power pins correctly connected to DRAM_VDD_CLK rail, which is isolated from main +VDIMM through 0-ohm jumper R275. This provides clean power for DDR3L clock outputs with dedicated decoupling. | | AF30 | TP_CORE_V1P05_S4 | $9N613 | ✅ | Test point pin TP_CORE_V1P05_S4 connected to net $9N613 with DNI test point TP1. This provides access to monitor the 1.05V core supply in S4 state for debug purposes. | </details> <details> <summary><b>C292</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Provides the ground reference for the decoupling capacitor. | | 2 | 2 | DRAM_VDD_CLK | ✅ | Connected to DRAM_VDD_CLK. Provides 1uF bulk decoupling capacitance for the DRAM clock power rail. | </details> <details> <summary><b>R275</b> - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM power rail. This pin sources power for the DRAM clock power rail through the 0-ohm jumper. | | 2 | 2 | DRAM_VDD_CLK | ✅ | Connected to DRAM_VDD_CLK power rail. This pin provides power to the DRAM clock power domain with separate decoupling. | </details> <details> <summary><b>C291</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Provides the ground reference for the decoupling capacitor. | | 2 | 2 | DRAM_VDD_CLK | ✅ | Connected to DRAM_VDD_CLK. Provides 0.1uF high-frequency decoupling for the DRAM clock power rail. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AC32 | CORE_V1P05_S3_AC32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,41.55,44.21,49.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | Y32 | CORE_V1P05_S3_Y32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,42.13,44.21,49.63" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | AA33 | CORE_V1P05_S3_AA33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,33.31,44.21,40.81" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | AF33 | CORE_V1P05_S3_AF33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,28.61,61.48,36.11" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | AG33 | CORE_V1P05_S3_AG33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.20,61.48,36.70" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | AG35 | CORE_V1P05_S3_AG35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.79,61.48,37.29" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | U33 | CORE_V1P05_S3_U33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.37,61.48,37.87" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | U35 | CORE_V1P05_S3_U35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.96,61.48,38.46" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | V33 | CORE_V1P05_S3_V33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,31.55,61.48,39.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply <em>(from schematic)</em></li><li>All nine pins are connected to the +V1P0S net in the schematic <em>(from schematic)</em></li><li>The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</em></li><li>The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) <em>(reasoning)</em></li><li>The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) <em>(reasoning)</em></li><li>These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) <em>(reasoning)</em></li><li>The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification <em>(reasoning)</em></li><li>Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply <em>(from schematic)</em></li><li>Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications <em>(reasoning)</em></li><li>These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V <em>(reasoning)</em></li></ul></details> | | A3 | VSS_A3_A3 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | A5 | VSS_A5_A5 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | A6 | VSS_A6_A6 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | A49 | VSS_A49_A49 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | A51 | VSS_A51_A51 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | A52 | VSS_A52_A52 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | B2 | VSS_B2_B2 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | B52 | VSS_B52_B52 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | B53 | VSS_B53_B53 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BE1 | VSS_BE1_BE1 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BE53 | VSS_BE53_BE53 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BG1 | VSS_BG1_BG1 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BG53 | VSS_BG53_BG53 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BH1 | VSS_BH1_BH1 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BH2 | VSS_BH2_BH2 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BH52 | VSS_BH52_BH52 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BH53 | VSS_BH53_BH53 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BJ2 | VSS_BJ2_BJ2 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BJ3 | VSS_BJ3_BJ3 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BJ5 | VSS_BJ5_BJ5 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BJ49 | VSS_BJ49_BJ49 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BJ51 | VSS_BJ51_BJ51 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | BJ52 | VSS_BJ52_BJ52 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | C1 | VSS_C1_C1 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | C53 | VSS_C53_C53 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | E1 | VSS_E1_E1 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | E53 | VSS_E53_E53 | GND | ✅ | VSS (ground) pins correctly connected to the GND net. These provide ground return paths for the SoC. | | B6 | UNCORE_V1P0_G3_B6 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic. | | C5 | UNCORE_V1P0_G3_C5 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic. | | U22 | UNCORE_V1P0_G3_U22 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic. | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to uncore logic. | | C3 | USB3_V1P0_G3_C3 | +V1P0A | ✅ | USB3_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to the USB 3.0 interface. | | Y19 | USB3_V1P0_G3_Y19 | +V1P0A | ✅ | USB3_V1P0_G3 pins correctly connected to +V1P0A rail. These supply always-on 1.0V power to the USB 3.0 interface. | | F1 | RESERVED_F1 | $10N1595 | ✅ | RESERVED_F1 pin connected to test point TP4 which is marked DNI. This is acceptable for a reserved pin. | | M14 | USB_V1P0_S3_M14 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S rail. These supply 1.0V power to the USB interface logic. | | U18 | USB_V1P0_S3_U18 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S rail. These supply 1.0V power to the USB interface logic. | | U19 | USB_V1P0_S3_U19 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S rail. These supply 1.0V power to the USB interface logic. | | N18 | USB_V3P3_G3_N18 | +3VSB | ✅ | USB_V3P3_G3 pins correctly connected to +3VSB rail. These supply always-on 3.3V power to the USB interface. | | P18 | USB_V3P3_G3_P18 | +3VSB | ✅ | USB_V3P3_G3 pins correctly connected to +3VSB rail. These supply always-on 3.3V power to the USB interface. | | N20 | USB_V1P8_G3_N20 | +V1P8A | ✅ | USB_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to the USB interface. | | N22 | PCU_V3P3_G3_N22 | +3VSB | ✅ | PCU_V3P3_G3 pin correctly connected to +3VSB rail. This supplies always-on 3.3V power to the Platform Control Unit. | | P22 | RTC_VCC_P22 | +RTCVCC | ✅ | RTC_VCC pin correctly connected to +RTCVCC rail with 0.1uF decoupling capacitor. This supplies battery-backed power to the Real Time Clock. | | U16 | USB_VSSA_U16 | GND | ✅ | USB_VSSA pin correctly connected to GND net. This provides analog ground for the USB interface. | | U24 | UNCORE_V1P8_G3_U24 | +V1P8A | ✅ | UNCORE_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to uncore logic. | | U25 | PMU_V1P8_G3_U25 | +V1P8A | ✅ | PMU_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to the Power Management Unit. | | V18 | USB_HSIC_V1P24_G3_V18 | +V1P0A | ✅ | USB_HSIC_V1P24_G3 pin correctly connected to +V1P0A rail. This is correct when USB HSIC is not used per datasheet guidance. | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | UNCORE_V1P0_G3 and UNCORE_V1P0_S0IX pins correctly connected to their respective power rails (+V1P0A and VCC_VIS_V1P0). | | Y22 | UNCORE_V1P0_S0IX_Y22 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_G3 and UNCORE_V1P0_S0IX pins correctly connected to their respective power rails (+V1P0A and VCC_VIS_V1P0). | | V24 | UNCORE_V1P0_S0IX_V24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem. | | Y24 | UNCORE_V1P0_S0IX_Y24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem. | | V25 | PCU_V1P8_G3_V25 | +V1P8A | ✅ | PCU_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to the Platform Control Unit. | | V32 | SVID_V1P0_S3_V32 | +V1P0S | ✅ | SVID_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies 1.0V power to the SVID interface logic. | | AA18 | UNCORE_V1P8_G3_AA18 | +V1P8A | ✅ | UNCORE_V1P8_G3 pin correctly connected to +V1P8A rail. This supplies always-on 1.8V power to uncore logic. | | AD16 | VSS_AD16 | VCC_VSS_V1P2 | ✅ | VSS_AD16 and VSS_AD18 pins connected to VCC_VSS_V1P2 net, which connects through R216 to GND. This is correct when MIPI CSI is not used. | | AD18 | VSS_AD18 | VCC_VSS_V1P2 | ✅ | VSS_AD16 and VSS_AD18 pins connected to VCC_VSS_V1P2 net, which connects through R216 to GND. This is correct when MIPI CSI is not used. | | AD35 | DRAM_V1P0_S0IX_AD35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | AF35 | DRAM_V1P0_S0IX_AF35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | AF36 | DRAM_V1P0_S0IX_AF36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | AJ36 | DRAM_V1P0_S0IX_AJ36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | AK35 | DRAM_V1P0_S0IX_AK35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | AK36 | DRAM_V1P0_S0IX_AK36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | Y35 | DRAM_V1P0_S0IX_Y35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | Y36 | DRAM_V1P0_S0IX_Y36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | AA36 | DRAM_V1P0_S0IX_AA36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail, which connects through R265 to +V1P0S with appropriate decoupling. | | BD1 | VGA_V1P35_S3_F1_BD1 | VCC_CRT_V1P35 | ✅ | VGA_V1P35_S3_F1 pin correctly connected to VCC_CRT_V1P35 rail through ferrite bead FB4 from +V1P35S. This supplies filtered 1.35V power to the VGA interface. | | AF16 | UNCORE_V1P0_S3_AF16 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state. | | AF18 | UNCORE_V1P0_S3_AF18 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state. | | G1 | UNCORE_V1P0_S3_G1 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state. | | Y18 | UNCORE_V1P0_S3_Y18 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to uncore logic in S3 suspend state. | | AF21 | UNCORE_V1P0_S0IX_AF21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, which connects through R222 to +V1P0S. These supply power to the graphics/display subsystem. | | AG21 | UNCORE_V1P0_S0IX_AG21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail, which connects through R222 to +V1P0S. These supply power to the graphics/display subsystem. | | AG18 | ICLK_V1P35_S3_F2 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail through ferrite bead FB5 from +V1P35S. These supply power to the integrated clock logic. | | AJ19 | ICLK_V1P35_S3_F1_AJ19 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail through ferrite bead FB5 from +V1P35S. These supply power to the integrated clock logic. | | AG19 | UNCORE_V1P35_S0IX_F1_AG19 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling. | | AG32 | UNCORE_V1P35_S0IX_F2_AG32 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling. | | AA25 | UNCORE_V1P35_S0IX_F5_AA25 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling. | | AF19 | UNCORE_V1P35_S0IX_F6 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling. | | V36 | UNCORE_V1P35_S0IX_F3_V36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling. | | U36 | UNCORE_V1P35_S0IX_F4_U36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling. | | AD36 | DRAM_V1P35_S0IX_F1_AD36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail through ferrite bead FB3 from +V1P35S with appropriate decoupling. | | AJ18 | DDI_V1P0_S0IX_AJ18 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic. | | AK19 | DDI_V1P0_S0IX_AK19 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic. | | AK21 | DDI_V1P0_S0IX_AK21 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic. | | AM16 | DDI_V1P0_S0IX_AM16 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S rail. These supply power to the display interface logic. | | BJ6 | VGA_V1P0_S3_BJ6 | +V1P0S | ✅ | VGA_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies 1.0V power to the VGA interface logic. | | AK18 | PCIE_V1P0_S3_AK18 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic. | | AM18 | PCIE_V1P0_S3_AM18 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic. | | AM21 | PCIE_V1P0_S3_AM21 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic. | | AN21 | PCIE_V1P0_S3_AN21 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S rail. These supply power to the PCIe interface logic. | | AM27 | LPC_V1P8V3P3_S3_AM27 | +VCC3S | ✅ | LPC_V1P8V3P3_S3 pin correctly connected to +VCC3S rail. This supplies power to the LPC interface. | | AM30 | UNCORE_V1P8_S3_AM30 | +V1P8S | ✅ | UNCORE_V1P8_S3 pins correctly connected to +V1P8S rail with appropriate decoupling. These supply 1.8V power to uncore logic. | | AN32 | UNCORE_V1P8_S3_AN32 | +V1P8S | ✅ | UNCORE_V1P8_S3 pins correctly connected to +V1P8S rail with appropriate decoupling. These supply 1.8V power to uncore logic. | | U38 | UNCORE_V1P8_S3_U38 | +V1P8S | ✅ | UNCORE_V1P8_S3 pins correctly connected to +V1P8S rail with appropriate decoupling. These supply 1.8V power to uncore logic. | | AM32 | HDA_LPE_V1P5V1P8_S3_AM32 | +V1P8S | ✅ | HDA_LPE_V1P5V1P8_S3 pin correctly connected to +V1P8S rail. This supplies power to the HD Audio and Low Power Engine. | | AN16 | VSSA_AN16 | GND | ✅ | VSSA pin correctly connected to GND net. This provides analog ground for the SoC. | | AN18 | PCIE_SATA_V1P0_S3_AN18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies power to the PCIe and SATA interface logic. | | AN19 | SATA_V1P0_S3_AN19 | +V1P0S | ✅ | SATA_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies power to the SATA interface logic. | | AN24 | VGA_V3P3_S3_AN24 | +VCC3S | ✅ | VGA_V3P3_S3 pin correctly connected to +VCC3S rail. This supplies 3.3V power to the VGA interface. | | AN25 | GPIO_V1P0_S3_AN25 | +V1P0S | ✅ | GPIO_V1P0_S3 pin correctly connected to +V1P0S rail. This supplies power to the GPIO logic. | | AN27 | SD3_V1P8V3P3_S3_AN27 | +VCC3S | ✅ | SD3_V1P8V3P3_S3 pin correctly connected to +VCC3S rail. This supplies power to the SD card interface. | | AN29 | UNCORE_V1P0_S0IX_AN29 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem. | | AN30 | UNCORE_V1P0_S0IX_AN30 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail. These supply power to the graphics/display subsystem. | </details> <details> <summary><b>FB4</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Output pin connected to VCC_CRT_V1P35, which powers the VGA/CRT interface. The ferrite provides filtering for this power domain. | </details> <details> <summary><b>FB5</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Output pin connected to VCC_ICLK_V1P35, which powers the internal clock circuitry. The ferrite provides filtering for this power domain. | </details> <details> <summary><b>FB3</b> - FERRITE_600OHM_1.3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0001423) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to the +V1P35S source rail. This is the correct orientation for a ferrite bead filtering the power supply. | | 2 | 2 | VCC_UNCORE_V1P35 | ✅ | Output pin connected to VCC_UNCORE_V1P35, which powers multiple CPU UNCORE and DRAM voltage pins. The ferrite provides filtering for this power domain. | </details> <details> <summary><b>R222</b> - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pin 1 connects to the main +V1P0S power rail, which supplies 1.0V to most CPU domains. | | 2 | 2 | VCC_VIS_V1P0 | ✅ | Pin 2 connects to VCC_VIS_V1P0, which powers the visual/graphics UNCORE_V1P0_S0IX domain of the CPU. | </details> <details> <summary><b>R265</b> - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pin 1 connects to the main +V1P0S power rail, which supplies 1.0V to most CPU domains. | | 2 | 2 | VCC_DRAM | ✅ | Pin 2 connects to VCC_DRAM, which powers the DRAM_V1P0_S0IX domain of the CPU. | </details> <details> <summary><b>R216</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VSS_V1P2 | ✅ | Pin 1 connects to VCC_VSS_V1P2, which is connected to CPU VSS pins AD16 and AD18 (MIPI CSI analog ground pins). | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, implementing the grounded configuration for MIPI CSI VSS pins when CSI is not used. | </details> <details> <summary><b>D7</b> - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N is connected to GND, completing the TVS protection circuit for the +5VSB rail. | | P | P | +5VSB | ✅ | Pin P is connected to +5VSB rail for ESD protection of the 5V standby power supply. | </details> <details> <summary><b>J2</b> - 258-0004524 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004524) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to +5VSB but the component is marked DNI (Do Not Install) as an alternate to J8. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND but the component is marked DNI as an alternate to J8. | </details> <details> <summary><b>C153</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to +5VSB for power supply decoupling and filtering. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, completing the bypass capacitor circuit for +5VSB filtering. | </details> <details> <summary><b>J8</b> - 3430-0212 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3430-0212) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to +5VSB power rail, providing 5V standby power through this connector. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, providing the ground return path for the connector. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A11 | VSS1 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A15 | VSS2 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A19 | VSS3 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A23 | VSS4 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A27 | VSS5 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A31 | VSS6 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A35 | VSS7 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A39 | VSS8 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A43 | VSS9 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | A47 | VSS10 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA1 | VSS11 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA3 | VSS15 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA16 | VSS12 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA19 | VSS13 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA21 | VSS14 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA32 | VSS16 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA35 | VSS17 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA38 | VSS18 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AA53 | VSS19 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB4 | VSS21 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB6 | VSS28 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB10 | VSS20 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB41 | VSS22 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB45 | VSS23 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB47 | VSS24 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB48 | VSS25 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB50 | VSS26 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AB51 | VSS27 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC16 | VSS29 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC18 | VSS30 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC19 | VSS31 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC21 | VSS32 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC25 | VSS33 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC33 | VSS34 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC35 | VSS35 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC36 | VSS36 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AC38 | VSS37 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AD7 | VSS44 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AD19 | VSS38 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AD21 | VSS39 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AD25 | VSS40 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AD32 | VSS41 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AD33 | VSS42 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AD47 | VSS43 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE1 | VSS45 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE3 | VSS49 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE4 | VSS50 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE6 | VSS60 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE8 | VSS61 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE9 | VSS62 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE11 | VSS46 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE12 | VSS47 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE14 | VSS48 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE40 | VSS51 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE42 | VSS52 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE43 | VSS53 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE45 | VSS54 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE46 | VSS55 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE48 | VSS56 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE50 | VSS57 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE51 | VSS58 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AE53 | VSS59 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AF10 | VSS63 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AF12 | VSS64 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AF25 | VSS65 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AF32 | VSS66 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AF47 | VSS67 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AG16 | VSS68 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AG25 | VSS69 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AG36 | VSS70 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AG38 | VSS71 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH4 | VSS72 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH6 | VSS110 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH7 | VSS75 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH9 | VSS76 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH41 | VSS73 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH45 | VSS74 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH47 | VSS106 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH48 | VSS107 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH50 | VSS108 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AH51 | VSS109 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ1 | VSS77 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ3 | VSS83 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ16 | VSS78 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ21 | VSS79 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ25 | VSS80 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ27 | VSS81 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ29 | VSS82 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ30 | VSS84 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ32 | VSS85 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ33 | VSS86 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ35 | VSS87 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ38 | VSS88 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AJ53 | VSS89 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AK10 | VSS90 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AK14 | VSS91 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AK16 | VSS92 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AK33 | VSS93 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AK41 | VSS94 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AK44 | VSS95 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM7 | VSS113 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM12 | VSS96 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM19 | VSS97 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM24 | VSS98 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM25 | VSS99 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM29 | VSS100 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM33 | VSS101 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM35 | VSS102 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM36 | VSS103 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM40 | VSS104 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM44 | VSS111 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AM51 | VSS112 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN1 | VSS114 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN3 | VSS119 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN5 | VSS131 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN6 | VSS134 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN8 | VSS135 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN9 | VSS136 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN11 | VSS115 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN12 | VSS116 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN14 | VSS117 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN22 | VSS118 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN33 | VSS120 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN35 | VSS121 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN36 | VSS122 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN38 | VSS123 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN40 | VSS124 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN42 | VSS125 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN43 | VSS126 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN45 | VSS127 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN46 | VSS128 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN48 | VSS129 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN49 | VSS130 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN51 | VSS132 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AN53 | VSS133 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AP40 | VSS137 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT2 | | | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT4 | VSS146 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT12 | VSS138 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT16 | VSS139 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT19 | VSS140 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT24 | VSS141 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT27 | VSS142 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT30 | VSS143 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT35 | VSS144 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT38 | VSS145 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT47 | VSS147 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AT52 | VSS148 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AU1 | VSS149 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AU3 | VSS151 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AU24 | VSS150 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AU30 | VSS152 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AU38 | VSS153 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AU51 | VSS154 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV7 | VSS167 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV12 | VSS155 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV13 | VSS156 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV14 | VSS157 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV18 | VSS158 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV19 | VSS159 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV24 | VSS160 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV27 | VSS161 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV30 | VSS162 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV35 | VSS163 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV38 | VSS164 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV47 | VSS165 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AV51 | VSS166 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AW3 | VSS171 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AW13 | VSS168 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AW19 | VSS169 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AW27 | VSS170 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AW35 | VSS172 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AY4 | VSS177 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AY9 | VSS179 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AY10 | VSS173 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AY22 | VSS174 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AY32 | VSS175 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AY36 | VSS176 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | AY50 | VSS178 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA14 | VSS180 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA19 | VSS181 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA22 | VSS182 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA27 | VSS183 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA32 | VSS184 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA35 | VSS185 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA40 | VSS186 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BA53 | VSS187 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BB19 | VSS188 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BB27 | VSS189 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BB35 | VSS190 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BC20 | VSS191 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BC22 | VSS192 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BC26 | VSS193 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BC28 | VSS194 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BC32 | VSS195 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BC34 | VSS196 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BC42 | VSS197 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BD19 | VSS198 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BD24 | VSS199 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BD27 | VSS200 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BD30 | VSS201 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BD35 | VSS202 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BE2 | VSS204 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BE8 | VSS206 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BE19 | VSS203 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BE35 | VSS205 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BF4 | VSS213 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BF12 | VSS207 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BF16 | VSS208 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BF24 | VSS209 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BF30 | VSS211 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BF36 | VSS212 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BF38 | VSS210 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BG31 | VSS214 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BG34 | VSS215 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BG39 | VSS216 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BG42 | VSS217 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BG45 | VSS218 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BG49 | VSS219 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ7 | VSS230 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ11 | VSS220 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ15 | VSS221 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ19 | VSS222 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ23 | VSS223 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ27 | VSS224 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ31 | VSS225 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ35 | VSS226 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ39 | VSS227 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ43 | VSS228 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | BJ47 | VSS229 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | C14 | VSS231 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | C31 | VSS232 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | C34 | VSS233 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | C39 | VSS234 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | C42 | VSS235 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | C45 | VSS236 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | C49 | VSS237 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | D12 | VSS238 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | D16 | VSS239 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | D24 | VSS240 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | D30 | VSS241 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | D36 | VSS242 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | D38 | VSS243 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | E8 | VSS246 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | E19 | VSS244 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | E35 | VSS245 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F2 | VSS248 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F5 | VSS253 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F7 | VSS254 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F19 | VSS247 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F24 | VSS249 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F27 | VSS250 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F30 | VSS251 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | F35 | VSS252 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G10 | VSS255 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G20 | VSS256 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G22 | VSS257 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G26 | VSS258 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G28 | VSS259 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G32 | VSS260 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G34 | VSS261 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | G42 | VSS262 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | H19 | VSS263 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | H27 | VSS264 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | H35 | VSS265 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J1 | VSS266 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J16 | VSS267 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J19 | VSS268 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J22 | VSS269 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J27 | VSS270 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J32 | VSS271 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J35 | VSS272 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J40 | VSS273 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | J53 | VSS274 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | K4 | VSS279 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | K9 | VSS281 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | K14 | VSS275 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | K22 | VSS276 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | K32 | VSS277 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | K36 | VSS278 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | K50 | VSS280 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | L13 | VSS282 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | L19 | VSS283 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | L27 | VSS284 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | L35 | VSS285 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M19 | VSS286 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M26 | VSS287 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M27 | VSS288 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M28 | VSS105 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M34 | VSS289 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M35 | VSS290 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M38 | VSS291 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M47 | VSS292 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | M51 | VSS293 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | N1 | VSS294 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | N16 | VSS295 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | N38 | VSS296 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | N51 | VSS297 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P4 | VSS306 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P9 | VSS309 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P13 | VSS298 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P16 | VSS299 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P19 | VSS300 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P20 | VSS301 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P24 | VSS302 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P32 | VSS303 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P35 | VSS304 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P38 | VSS305 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P47 | VSS307 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | P52 | VSS308 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | T40 | VSS310 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U1 | VSS311 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U3 | VSS316 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U5 | VSS326 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U6 | VSS329 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U8 | VSS330 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U9 | VSS331 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U11 | VSS312 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U12 | VSS313 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U14 | VSS314 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U21 | VSS315 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U30 | VSS317 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U32 | VSS318 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U40 | VSS319 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U42 | VSS320 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U43 | VSS321 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U45 | VSS322 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U46 | VSS323 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U48 | VSS324 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U49 | VSS325 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U51 | VSS327 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | U53 | VSS328 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V7 | VSS340 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V12 | VSS332 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V16 | VSS333 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V19 | VSS334 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V21 | VSS335 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V35 | VSS336 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V40 | VSS337 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V44 | VSS338 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | V51 | VSS339 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y7 | VSS349 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y9 | VSS350 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y10 | VSS341 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y14 | VSS342 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y16 | VSS343 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y21 | VSS344 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y25 | VSS345 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y33 | VSS346 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y41 | VSS347 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | | Y44 | VSS348 | GND | ✅ | All VSS ground pins are correctly connected to the GND net. These approximately 350 ground pins provide proper grounding for the Intel Atom E3825 SoC and are essential for proper operation, signal integrity, and power distribution. | </details> <details> <summary><b>MEM3</b> - MICRON MT41K256M16HA ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | C1 | VDDQ2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | R1 | VDD7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | B2 | VDD8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | D2 | VDDQ9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | H2 | VDDQ4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | K2 | VDD9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | G7 | VDD1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | A8 | VDDQ5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | K8 | VDD2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | C9 | VDDQ6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | N1 | VDD6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | F1 | VDDQ3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | N9 | VDD3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | D9 | VDD4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | E9 | VDDQ7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | H9 | VDDQ8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | R9 | VDD5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail, shared with MEM2. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | B1 | VSSQ1 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | D1 | VSSQ2 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | E1 | VSS1 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | G1 | VSSQ3 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | M1 | VSS2 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | P1 | VSS3 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | T1 | VSS4 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | E2 | VSSQ4 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | J2 | VSS5 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | B3 | VSS6 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | D8 | VSSQ5 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | E8 | VSSQ6 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | G8 | VSS7 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | J8 | VSS8 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | A9 | VSS9 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | B9 | VSSQ7 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | F9 | VSSQ8 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | G9 | VSSQ9 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | M9 | VSS10 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | P9 | VSS11 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | T9 | VSS12 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND, shared with MEM2. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | C7 | DQSU | M_DQS_A_P3 | ✅ | Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P3 and M_DQS_A_N3. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte of MEM3. | | B7 | /DQSU | M_DQS_A_N3 | ✅ | Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P3 and M_DQS_A_N3. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte of MEM3. | | D3 | DMU | M_DM_A3 | ✅ | Upper byte data mask (DMU) correctly connected to M_DM_A3. This input signal masks write data for the upper byte of MEM3 when asserted. | | D7 | DQU0 | M_DATA_A29 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | C3 | DQU1 | M_DATA_A26 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | C8 | DQU2 | M_DATA_A28 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | C2 | DQU3 | M_DATA_A27 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | A7 | DQU4 | M_DATA_A25 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | A2 | DQU5 | M_DATA_A30 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | B8 | DQU6 | M_DATA_A24 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | A3 | DQU7 | M_DATA_A31 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A29, DQ9→A26, DQ10→A28, DQ11→A27, DQ12→A25, DQ13→A30, DQ14→A24, DQ15→A31. | | E3 | DQL0 | M_DATA_A16 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | F7 | DQL1 | M_DATA_A17 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | F2 | DQL2 | M_DATA_A18 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | F8 | DQL3 | M_DATA_A19 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | H3 | DQL4 | M_DATA_A20 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | H8 | DQL5 | M_DATA_A21 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | G2 | DQL6 | M_DATA_A22 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | H7 | DQL7 | M_DATA_A23 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A16 through M_DATA_A23 in sequential order. These form bits 16-23 of the combined 32-bit data bus (MEM2 provides bits 0-15, MEM3 provides bits 16-31). | | E7 | DML | M_DM_A2 | ✅ | Lower byte data mask (DML) correctly connected to M_DM_A2. This input signal masks write data for the lower byte of MEM3 when asserted. | | F3 | DQSL | M_DQS_A_P2 | ✅ | Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P2 and M_DQS_A_N2. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte of MEM3. | | G3 | /DQSL | M_DQS_A_N2 | ✅ | Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P2 and M_DQS_A_N2. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte of MEM3. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | Data reference voltage pin VREFDQ correctly connected to SM_VREF_DQ1_A, shared with MEM2. This ensures consistent data signal referencing across both devices. | | J1 | NC1__ODT1_ | | ✅ | No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration. | | L1 | NC2__/CS1_ | | ✅ | No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration. | | J9 | NC3__CKE1_ | | ✅ | No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration. | | L9 | NC4__ZQ1_ | | ✅ | No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration. | | M7 | NC5 | | ✅ | No-connect pins (NC) are correctly left unconnected, same as MEM2. These pins are designated for alternate rank functions that are not used in this single-rank configuration. | | J3 | /RAS | M_RAS_A_L | ✅ | Command pins RAS#, CAS#, and WE# correctly connected to shared command bus, same as MEM2. This ensures both devices execute the same commands simultaneously for parallel operation. | | K3 | /CAS | M_CAS_A_L | ✅ | Command pins RAS#, CAS#, and WE# correctly connected to shared command bus, same as MEM2. This ensures both devices execute the same commands simultaneously for parallel operation. | | L3 | /WE | M_WE_A_L | ✅ | Command pins RAS#, CAS#, and WE# correctly connected to shared command bus, same as MEM2. This ensures both devices execute the same commands simultaneously for parallel operation. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2. This ensures both devices are synchronized to the same clock. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0, shared with MEM2. This ensures both devices are synchronized to the same clock. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination pin ODT correctly connected to M_ODT_A0, shared with MEM2. This ensures coordinated termination control for both devices. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable pin CKE correctly connected to M_CKE_A0, shared with MEM2. This ensures synchronized power management for both devices. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select pin CS# correctly connected to M_CS_A_L0, same as MEM2. This confirms both devices operate as a single rank with synchronized selection. | | L8 | ZQ | M_ZQ2 | ✅ | ZQ calibration pin correctly connected to M_ZQ2, which has a 240Ω resistor (R327) to GND. This provides the external reference for output driver and ODT calibration, independent from MEM2. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2, same as MEM2. This ensures both devices select the same bank simultaneously. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2, same as MEM2. This ensures both devices select the same bank simultaneously. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2, same as MEM2. This ensures both devices select the same bank simultaneously. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | Control/address reference voltage pin VREFCA correctly connected to SM_VREF_CA1_A, shared with MEM2. This ensures consistent control/address signal referencing across both devices. | | N3 | A0 | M_MA_A0 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | P7 | A1 | M_MA_A1 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | P3 | A2 | M_MA_A2 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | N2 | A3 | M_MA_A3 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | P8 | A4 | M_MA_A4 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | P2 | A5 | M_MA_A5 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | R8 | A6 | M_MA_A6 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | R2 | A7 | M_MA_A7 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | T8 | A8 | M_MA_A8 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | R3 | A9 | M_MA_A9 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | R7 | A11 | M_MA_A11 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | T3 | A13 | M_MA_A13 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | T7 | A14 | M_MA_A14 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14, same as MEM2. This allows both devices to access the same memory locations simultaneously for parallel operation. | | T2 | /RESET | M_A_RST_L | ✅ | Reset pin RESET# correctly connected to M_A_RST_L, shared with MEM2. This ensures synchronized reset and initialization for both devices. | </details> <details> <summary><b>MEM2</b> - MICRON MT41K256M16HA ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | C1 | VDDQ2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | R1 | VDD7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | B2 | VDD8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | D2 | VDDQ9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | H2 | VDDQ4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | K2 | VDD9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | G7 | VDD1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | A8 | VDDQ5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | K8 | VDD2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | C9 | VDDQ6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | N1 | VDD6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | F1 | VDDQ3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | N9 | VDD3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | D9 | VDD4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | E9 | VDDQ7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | H9 | VDDQ8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | R9 | VDD5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) all correctly connected to +VDIMM rail. This provides the 1.35V DDR3L operating voltage to both core and I/O power domains. | | B1 | VSSQ1 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | D1 | VSSQ2 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | E1 | VSS1 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | G1 | VSSQ3 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | M1 | VSS2 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | P1 | VSS3 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | T1 | VSS4 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | E2 | VSSQ4 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | J2 | VSS5 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | B3 | VSS6 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | D8 | VSSQ5 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | E8 | VSSQ6 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | G8 | VSS7 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | J8 | VSS8 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | A9 | VSS9 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | B9 | VSSQ7 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | F9 | VSSQ8 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | G9 | VSSQ9 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | M9 | VSS10 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | P9 | VSS11 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | T9 | VSS12 | GND | ✅ | Ground pins (VSS and VSSQ) all correctly connected to GND. VSSQ pins provide isolated ground return for data signals to improve noise immunity. | | C7 | DQSU | M_DQS_A_P1 | ✅ | Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P1 and M_DQS_A_N1. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte. | | B7 | /DQSU | M_DQS_A_N1 | ✅ | Upper byte data strobe differential pair (DQSU/DQSU#) correctly connected to M_DQS_A_P1 and M_DQS_A_N1. These strobes are edge-aligned with read data and center-aligned with write data for the upper byte. | | D3 | DMU | M_DM_A1 | ✅ | Upper byte data mask (DMU) correctly connected to M_DM_A1. This input signal masks write data for the upper byte when asserted. | | D7 | DQU0 | M_DATA_A9 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | C3 | DQU1 | M_DATA_A10 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | C8 | DQU2 | M_DATA_A8 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | C2 | DQU3 | M_DATA_A11 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | A7 | DQU4 | M_DATA_A13 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | A2 | DQU5 | M_DATA_A15 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | B8 | DQU6 | M_DATA_A12 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | A3 | DQU7 | M_DATA_A14 | ✅ | Upper byte data pins (DQ8-DQ15) connected with intentional bit swapping within the byte lane for routing optimization. DQ8→A9, DQ9→A10, DQ10→A8, DQ11→A11, DQ12→A13, DQ13→A15, DQ14→A12, DQ15→A14. | | E3 | DQL0 | M_DATA_A0 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | F7 | DQL1 | M_DATA_A1 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | F2 | DQL2 | M_DATA_A2 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | F8 | DQL3 | M_DATA_A3 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | H3 | DQL4 | M_DATA_A4 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | H8 | DQL5 | M_DATA_A5 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | G2 | DQL6 | M_DATA_A6 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | H7 | DQL7 | M_DATA_A7 | ✅ | Lower byte data pins (DQ0-DQ7) connected to M_DATA_A0 through M_DATA_A7 in sequential order. These form the lower 8 bits of the 16-bit data bus from this device. | | E7 | DML | M_DM_A0 | ✅ | Lower byte data mask (DML) correctly connected to M_DM_A0. This input signal masks write data for the lower byte when asserted. | | F3 | DQSL | M_DQS_A_P0 | ✅ | Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P0 and M_DQS_A_N0. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte. | | G3 | /DQSL | M_DQS_A_N0 | ✅ | Lower byte data strobe differential pair (DQSL/DQSL#) correctly connected to M_DQS_A_P0 and M_DQS_A_N0. These strobes are edge-aligned with read data and center-aligned with write data for the lower byte. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | Data reference voltage pin VREFDQ correctly connected to SM_VREF_DQ1_A, which is generated by a resistor divider (R310 and R325, both 4.7kΩ) to provide VDIMM × 0.5. This reference is shared between MEM2 and MEM3. | | J1 | NC1__ODT1_ | | ✅ | No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration. | | L1 | NC2__/CS1_ | | ✅ | No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration. | | J9 | NC3__CKE1_ | | ✅ | No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration. | | L9 | NC4__ZQ1_ | | ✅ | No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration. | | M7 | NC5 | | ✅ | No-connect pins (NC) are correctly left unconnected. These pins are designated for alternate rank functions (ODT1, CS1, CKE1, ZQ1) that are not used in this single-rank configuration. | | J3 | /RAS | M_RAS_A_L | ✅ | Command pins RAS#, CAS#, and WE# correctly connected to shared command bus M_RAS_A_L, M_CAS_A_L, and M_WE_A_L. These define memory operations and are shared between MEM2 and MEM3. | | K3 | /CAS | M_CAS_A_L | ✅ | Command pins RAS#, CAS#, and WE# correctly connected to shared command bus M_RAS_A_L, M_CAS_A_L, and M_WE_A_L. These define memory operations and are shared between MEM2 and MEM3. | | L3 | /WE | M_WE_A_L | ✅ | Command pins RAS#, CAS#, and WE# correctly connected to shared command bus M_RAS_A_L, M_CAS_A_L, and M_WE_A_L. These define memory operations and are shared between MEM2 and MEM3. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0. All control and address inputs are sampled on the CK/CK# crossing. Clock is shared between MEM2 and MEM3. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock pins CK and CK# correctly connected to M_CLK_A_P0 and M_CLK_A_N0. All control and address inputs are sampled on the CK/CK# crossing. Clock is shared between MEM2 and MEM3. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination pin ODT correctly connected to M_ODT_A0. This enables termination resistance for DQ, DQS, and DM signals, and is shared between MEM2 and MEM3. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable pin CKE correctly connected to M_CKE_A0. This signal enables/disables internal circuitry and clocks, and is shared between MEM2 and MEM3 for synchronized power management. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select pin CS# correctly connected to M_CS_A_L0. Both MEM2 and MEM3 share the same chip select, indicating they operate as a single rank with parallel data buses forming a 32-bit interface. | | L8 | ZQ | M_ZQ1 | ✅ | ZQ calibration pin correctly connected to M_ZQ1, which has a 240Ω resistor (R140) to GND. This provides the external reference for output driver and ODT calibration as required by the datasheet. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2. These select one of eight internal banks and are shared between MEM2 and MEM3. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2. These select one of eight internal banks and are shared between MEM2 and MEM3. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address pins BA0-BA2 correctly connected to shared bank address bus M_BS_A0 through M_BS_A2. These select one of eight internal banks and are shared between MEM2 and MEM3. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | Control/address reference voltage pin VREFCA correctly connected to SM_VREF_CA1_A, which is generated by a resistor divider (R144 and R326, both 4.7kΩ) to provide VDIMM × 0.5. This reference is shared between MEM2 and MEM3. | | N3 | A0 | M_MA_A0 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | P7 | A1 | M_MA_A1 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | P3 | A2 | M_MA_A2 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | N2 | A3 | M_MA_A3 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | P8 | A4 | M_MA_A4 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | P2 | A5 | M_MA_A5 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | R8 | A6 | M_MA_A6 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | R2 | A7 | M_MA_A7 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | T8 | A8 | M_MA_A8 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | R3 | A9 | M_MA_A9 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | R7 | A11 | M_MA_A11 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | T3 | A13 | M_MA_A13 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | T7 | A14 | M_MA_A14 | ✅ | Address pins A0-A14 correctly connected to shared address bus M_MA_A0 through M_MA_A14. These pins are shared between MEM2 and MEM3 for parallel operation on the same channel. | | T2 | /RESET | M_A_RST_L | ✅ | Reset pin RESET# correctly connected to M_A_RST_L through 0Ω resistor R353. This asynchronous active-low reset is shared between MEM2 and MEM3, with optional DNI filtering capacitor C374. | </details> <details> <summary><b>R144</b> - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Upper resistor of VREFCA voltage divider, connected to +VDIMM power supply. This forms the high side of a 1:1 divider to create the DDR3 command/address reference voltage. | | 2 | 2 | SM_VREF_CA1_A | ✅ | Output of voltage divider connected to SM_VREF_CA1_A reference voltage net. Provides VREFCA to both DDR3 memory devices. | </details> <details> <summary><b>C344</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_CA1_A | ✅ | Additional decoupling capacitor for VREFCA reference voltage. Provides filtering in parallel with C133 on the SM_VREF_CA1_A net. | | 2 | 2 | GND | ✅ | Ground connection for VREFCA decoupling capacitor. Completes the filter path to ground. | </details> <details> <summary><b>R326</b> - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower resistor of VREFCA voltage divider, connected to GND. Forms the low side of a 1:1 divider with R144 to create the DDR3 command/address reference voltage. | | 2 | 2 | SM_VREF_CA1_A | ✅ | Output of voltage divider connected to SM_VREF_CA1_A reference voltage net. Provides VREFCA to both DDR3 memory devices. | </details> <details> <summary><b>C133</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_CA1_A | ✅ | Decoupling capacitor for VREFCA reference voltage. Filters noise on the SM_VREF_CA1_A net that supplies the command/address reference to DDR3 memory. | | 2 | 2 | GND | ✅ | Ground connection for VREFCA decoupling capacitor. Completes the filter path to ground. | </details> <details> <summary><b>R310</b> - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Upper leg of VREFDQ voltage divider, connected to +VDIMM supply. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Midpoint of voltage divider, connected to SM_VREF_DQ1_A which supplies VREFDQ to memory chips MEM2 and MEM3. | </details> <details> <summary><b>C329</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Bypass capacitor connected to SM_VREF_DQ1_A, providing additional filtering in parallel with C124. | | 2 | 2 | GND | ✅ | Ground connection for bypass capacitor return path. | </details> <details> <summary><b>R325</b> - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower leg of VREFDQ voltage divider, connected to GND. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Midpoint of voltage divider, connected to SM_VREF_DQ1_A which supplies VREFDQ to memory chips. | </details> <details> <summary><b>C124</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Bypass capacitor connected to SM_VREF_DQ1_A for filtering the VREFDQ reference voltage. | | 2 | 2 | GND | ✅ | Ground connection for bypass capacitor return path. | </details> <details> <summary><b>R140</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ1 | ✅ | Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM2 via net M_ZQ1. This provides the reference impedance for the memory's output driver calibration. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit. | </details> <details> <summary><b>R327</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ2 | ✅ | Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM3 via net M_ZQ2. This provides the reference impedance for the memory's output driver calibration. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit. | </details> <details> <summary><b>U33</b> - M24C02-WMN6TP-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/M24C02-WMN6TP-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E0 | DDR_E0 | ✅ | E0 address pin connected to DDR_E0 net. Pull-down resistor R118 is DNI, leaving this pin without a defined logic level if U33 were populated. However, U33 itself is DNI, making this configuration acceptable. | | 2 | E1 | DDR_E1 | ✅ | E1 address pin connected to DDR_E1 net. Pull-down resistor R123 is DNI, leaving this pin without a defined logic level if U33 were populated. However, U33 itself is DNI, making this configuration acceptable. | | 3 | E2 | GND | ✅ | E2 address pin correctly connected to GND, setting address bit 2 to logic 0. | | 4 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA pin correctly connected to DDR_SMB_DATA for I2C data communication. | | 6 | SCL | DDR_SMB_CLK | ✅ | SCL pin correctly connected to DDR_SMB_CLK for I2C clock communication. | | 7 | ~WC | DDR_WP_A | ✅ | Write Control pin connected to DDR_WP_A with configuration options via DNI resistors R121 (pull-up to +VCC3) and R122 (pull-down to GND). Both resistors are DNI, leaving this pin floating if U33 were populated. However, U33 itself is DNI, making this configuration acceptable. | | 8 | VCC | +VCC3 | ✅ | VCC pin correctly connected to +VCC3 with proper decoupling via C287. | </details> <details> <summary><b>C287</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor negative terminal correctly connected to GND. | | 2 | 2 | +VCC3 | ✅ | Decoupling capacitor positive terminal correctly connected to +VCC3 power rail. | </details> <details> <summary><b>R353</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_A_DRAMRST_L | ✅ | Connected to M_A_DRAMRST_L net, which is the source reset signal likely from a memory controller. This pin serves as the input to the 0-ohm jumper resistor. | | 2 | 2 | M_A_RST_L | ✅ | Connected to M_A_RST_L net, which drives the /RESET pins of memory devices MEM2 and MEM3. This pin serves as the output of the 0-ohm jumper resistor. | </details> <details> <summary><b>C374</b> - 10pF 5% 50V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This pin would provide the ground return path for reset signal filtering if the component were installed. | | 2 | 2 | M_A_RST_L | ✅ | Connected to M_A_RST_L, the memory reset signal. This pin would provide high-frequency filtering on the reset line if the component were installed. | </details> <details> <summary><b>C331</b> - 3.3pF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_CLK_A_N0 | ✅ | Connected to M_CLK_A_N0, the negative differential clock signal to DDR3 memories MEM2 and MEM3. This capacitor is marked DNI and serves as an optional tuning component. | | 2 | 2 | M_CLK_A_P0 | ✅ | Connected to M_CLK_A_P0, the positive differential clock signal to DDR3 memories MEM2 and MEM3. This capacitor is marked DNI and serves as an optional tuning component. | </details> <details> <summary><b>FL1</b> - 3750-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3750-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CH1-IN | SD3_CD# | ✅ | CH1-IN filters the SD3_CD# (card detect) signal from the processor side. The signal is pulled up to +V1P8S through R182. | | 2 | CH2-IN | SD3_D2 | ✅ | CH2-IN filters the SD3_D2 (data line 2) signal. The signal is pulled up to +VCC3 through R174. | | 3 | CH3-IN | SD3_D3 | ✅ | CH3-IN filters the SD3_D3 (data line 3) signal. The signal is pulled up to +VCC3 through R180. | | 4 | CH4-IN | SD3_CMD | ✅ | CH4-IN filters the SD3_CMD (command line) signal. The signal is pulled up to +VCC3 through R173. | | 5 | CH5-IN | SD3_CLK | ✅ | CH5-IN filters the SD3_CLK (clock line) signal. The signal is pulled up to +VCC3 through R157. | | 6 | CH6-IN | SD3_D0 | ✅ | CH6-IN filters the SD3_D0 (data line 0) signal. The signal is pulled up to +VCC3 through R156. | | 7 | CH7-IN | SD3_D1 | ✅ | CH7-IN filters the SD3_D1 (data line 1) signal. The signal is pulled up to +VCC3 through R155. | | 8 | CH8-IN | | ✅ | CH8-IN is not connected. This channel is unused. | | 9 | CH8-OUT | | ✅ | CH8-OUT is not connected. This channel is unused. | | 10 | CH7-OUT | SD3_D1_R | ✅ | CH7-OUT provides the filtered SD3_D1_R signal to the SD card connector. | | 11 | CH6-OUT | SD3_D0_R | ✅ | CH6-OUT provides the filtered SD3_D0_R signal to the SD card connector. | | 12 | CH5-OUT | SD3_CLK_R | ✅ | CH5-OUT provides the filtered SD3_CLK_R signal to the SD card connector. | | 13 | CH4-OUT | SD3_CMD_R | ✅ | CH4-OUT provides the filtered SD3_CMD_R signal to the SD card connector. | | 14 | CH3-OUT | SD3_D3_R | ✅ | CH3-OUT provides the filtered SD3_D3_R signal to the SD card connector. | | 15 | CH2-OUT | SD3_D2_R | ✅ | CH2-OUT provides the filtered SD3_D2_R signal to the SD card connector. | | 16 | CH1-OUT | SD3_CD_R | ✅ | CH1-OUT provides the filtered SD3_CD_R signal to the SD card connector. | | 17 | GND_PAD | GND | ✅ | GND_PAD is connected to ground, providing the reference for the filter. | </details> <details> <summary><b>P2</b> - 158-0001269 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/158-0001269) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | SD3_D2_R | ✅ | DAT2 is connected to the filtered SD3_D2_R signal from FL1. | | 2 | CD/DAT3 | SD3_D3_R | ✅ | CD/DAT3 is connected to the filtered SD3_D3_R signal from FL1. | | 3 | CMD | SD3_CMD_R | ✅ | CMD is connected to the filtered SD3_CMD_R signal from FL1. | | 4 | VDD | +VCC3 | ✅ | VDD is connected to +VCC3 with decoupling capacitors C162 and C159. | | 5 | CLOCK | SD3_CLK_R | ✅ | CLOCK is connected to the filtered SD3_CLK_R signal from FL1. | | 6 | VSS | GND | ✅ | VSS is connected to ground. | | 7 | DAT0 | SD3_D0_R | ✅ | DAT0 is connected to the filtered SD3_D0_R signal from FL1. | | 8 | DAT1 | SD3_D1_R | ✅ | DAT1 is connected to the filtered SD3_D1_R signal from FL1. | | 9 | GND | GND | ✅ | GND is connected to ground. | | 10 | CD | SD3_CD_R | ✅ | CD is connected to the filtered SD3_CD_R signal from FL1. | | 11 | GND3 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD. | | 12 | GND4 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD. | | 15 | GND7 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD. | | 16 | GND8 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are frame ground pins connected to FGND-uSD. | | 13 | GND5 | FGND-uSD-Front | ✅ | GND5 and GND6 are frame ground pins connected to FGND-uSD-Front. | | 14 | GND6 | FGND-uSD-Front | ✅ | GND5 and GND6 are frame ground pins connected to FGND-uSD-Front. | </details> <details> <summary><b>C17</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail (VCCA of U2). | </details> <details> <summary><b>R29</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CEC | ✅ | Connected to HDMI_CEC net (CEC_A of U2). | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail. | </details> <details> <summary><b>R171</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S supply rail. | | 2 | 2 | HPD_ENB | ✅ | Connected to HPD_ENB net which controls CT_HPD pin of U2. | </details> <details> <summary><b>R30</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCDAT | ✅ | Connected to HDMI_DDCDAT net (SDA_A of U2). | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail. | </details> <details> <summary><b>U2</b> - TPD12S016PW ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/TPD12S016PW) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CEC_A | HDMI_CEC | ✅ | CEC_A pin connects to HDMI_CEC net with external 10K pullup R29 to +V1P8S. This is the HDMI controller side CEC signal. | | 2 | SCL_A | HDMI_DDCCLK | ✅ | SCL_A pin connects to HDMI_DDCCLK net with external 10K pullup R28 to +V1P8S. This is the HDMI controller side DDC clock signal. | | 3 | SDA_A | HDMI_DDCDAT | ✅ | SDA_A pin connects to HDMI_DDCDAT net with external 10K pullup R30 to +V1P8S. This is the HDMI controller side DDC data signal. | | 4 | HPD_A | HDMI_HPD | ✅ | HPD_A pin connects to HDMI_HPD net. This is the hot plug detect output to the HDMI controller. | | 5 | LS_OE | LS_OE | ✅ | LS_OE pin connects to LS_OE net with 2.2K pullup R172 to +V1P8S. This enables the level shifters by default. | | 6 | GND1 | GND | ✅ | Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net. | | 14 | GND2 | GND | ✅ | Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net. | | 19 | GND3 | GND | ✅ | Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net. | | 7 | CEC_B | C_HDMI_CEC | ✅ | CEC_B pin connects to C_HDMI_CEC net which goes to the HDMI connector CEC pin. This is the HDMI connector side CEC signal. | | 8 | SCL_B | C_HDMI_SCL | ✅ | SCL_B pin connects to C_HDMI_SCL net which goes to the HDMI connector SCL pin. This is the HDMI connector side DDC clock signal. | | 9 | SDA_B | C_HDMI_SDA | ✅ | SDA_B pin connects to C_HDMI_SDA net which goes to the HDMI connector SDA pin. This is the HDMI connector side DDC data signal. | | 10 | HPD_B | C_HDMI_HPD | ✅ | HPD_B pin connects to C_HDMI_HPD net which goes to the HDMI connector hot plug detect pin. This is the hot plug detect input from the HDMI connector. | | 11 | VCC5V | +5VSB | ✅ | VCC5V pin connects to +5VSB net with 0.1uF decoupling capacitor C155. This is the 5V supply input to the load switch. | | 12 | CT_HPD | HPD_ENB | ✅ | CT_HPD pin connects to HPD_ENB net with 2.2K pullup R171 to +V1P8S. This enables the load switch and HPD by default. | | 13 | 5V_OUT | +HDMI_CRT_VCC | ✅ | 5V_OUT pin connects to +HDMI_CRT_VCC net which supplies power to the HDMI connector through ferrite bead L7. This is the current-limited 5V output. | | 15 | CLK- | HDMI_OUT_CLK_DN | ✅ | CLK- and CLK+ pins connect to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets which go through common mode choke L14 to the HDMI connector. These are the HDMI TMDS clock differential pair. | | 16 | CLK+ | HDMI_OUT_CLK_DP | ✅ | CLK- and CLK+ pins connect to HDMI_OUT_CLK_DN and HDMI_OUT_CLK_DP nets which go through common mode choke L14 to the HDMI connector. These are the HDMI TMDS clock differential pair. | | 17 | D0- | HDMI_OUT_TX0_DN | ✅ | D0- and D0+ pins connect to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets which go through common mode choke L15 to the HDMI connector. These are HDMI TMDS data channel 0 differential pair. | | 18 | D0+ | HDMI_OUT_TX0_DP | ✅ | D0- and D0+ pins connect to HDMI_OUT_TX0_DN and HDMI_OUT_TX0_DP nets which go through common mode choke L15 to the HDMI connector. These are HDMI TMDS data channel 0 differential pair. | | 20 | D1- | HDMI_OUT_TX1_DN | ✅ | D1- and D1+ pins connect to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets which go through common mode choke L16 to the HDMI connector. These are HDMI TMDS data channel 1 differential pair. | | 21 | D1+ | HDMI_OUT_TX1_DP | ✅ | D1- and D1+ pins connect to HDMI_OUT_TX1_DN and HDMI_OUT_TX1_DP nets which go through common mode choke L16 to the HDMI connector. These are HDMI TMDS data channel 1 differential pair. | | 22 | D2- | HDMI_OUT_TX2_DN | ✅ | D2- and D2+ pins connect to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets which go through common mode choke L17 to the HDMI connector. These are HDMI TMDS data channel 2 differential pair. | | 23 | D2+ | HDMI_OUT_TX2_DP | ✅ | D2- and D2+ pins connect to HDMI_OUT_TX2_DN and HDMI_OUT_TX2_DP nets which go through common mode choke L17 to the HDMI connector. These are HDMI TMDS data channel 2 differential pair. | | 24 | VCCA | +V1P8S | ✅ | VCCA pin connects to +V1P8S net with 0.1uF decoupling capacitor C17. This is the 1.8V supply for the TPD12S016. | </details> <details> <summary><b>R172</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S supply rail. | | 2 | 2 | LS_OE | ✅ | Connected to LS_OE net which controls LS_OE pin of U2. | </details> <details> <summary><b>C155</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. | | 2 | 2 | +5VSB | ✅ | Connected to +5VSB supply rail (VCC5V of U2). | </details> <details> <summary><b>R28</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCCLK | ✅ | Connected to HDMI_DDCCLK net (SCL_A of U2). | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail. | </details> <details> <summary><b>L15</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX0_C_DN | ✅ | IN1 pin correctly connected to HDMI_TX0_C_DN, the negative data channel 0 signal after AC coupling. | | 3 | IN2 | HDMI_TX0_C_DP | ✅ | IN2 pin correctly connected to HDMI_TX0_C_DP, the positive data channel 0 signal after AC coupling. | | 4 | OUT2 | HDMI_OUT_TX0_DP | ✅ | OUT2 pin correctly connected to HDMI_OUT_TX0_DP, routing the positive data channel 0 signal to the ESD protection IC and connector. | | 6 | OUT1 | HDMI_OUT_TX0_DN | ✅ | OUT1 pin correctly connected to HDMI_OUT_TX0_DN, routing the negative data channel 0 signal to the ESD protection IC and connector. | </details> <details> <summary><b>L14</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_CLK_C_DN | ✅ | IN1 pin correctly connected to HDMI_CLK_C_DN, the negative clock signal after AC coupling. | | 3 | IN2 | HDMI_CLK_C_DP | ✅ | IN2 pin correctly connected to HDMI_CLK_C_DP, the positive clock signal after AC coupling. | | 4 | OUT2 | HDMI_OUT_CLK_DP | ✅ | OUT2 pin correctly connected to HDMI_OUT_CLK_DP, routing the positive clock signal to the ESD protection IC and connector. | | 6 | OUT1 | HDMI_OUT_CLK_DN | ✅ | OUT1 pin correctly connected to HDMI_OUT_CLK_DN, routing the negative clock signal to the ESD protection IC and connector. | </details> <details> <summary><b>L16</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX1_C_DN | ✅ | IN1 pin correctly connected to HDMI_TX1_C_DN, the negative data channel 1 signal after AC coupling. | | 3 | IN2 | HDMI_TX1_C_DP | ✅ | IN2 pin correctly connected to HDMI_TX1_C_DP, the positive data channel 1 signal after AC coupling. | | 4 | OUT2 | HDMI_OUT_TX1_DP | ✅ | OUT2 pin correctly connected to HDMI_OUT_TX1_DP, routing the positive data channel 1 signal to the ESD protection IC and connector. | | 6 | OUT1 | HDMI_OUT_TX1_DN | ✅ | OUT1 pin correctly connected to HDMI_OUT_TX1_DN, routing the negative data channel 1 signal to the ESD protection IC and connector. | </details> <details> <summary><b>L17</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX2_C_DN | ✅ | IN1 pin correctly connected to HDMI_TX2_C_DN, the negative data channel 2 signal after AC coupling. | | 3 | IN2 | HDMI_TX2_C_DP | ✅ | IN2 pin correctly connected to HDMI_TX2_C_DP, the positive data channel 2 signal after AC coupling. | | 4 | OUT2 | HDMI_OUT_TX2_DP | ✅ | OUT2 pin correctly connected to HDMI_OUT_TX2_DP, routing the positive data channel 2 signal to the ESD protection IC and connector. | | 6 | OUT1 | HDMI_OUT_TX2_DN | ✅ | OUT1 pin correctly connected to HDMI_OUT_TX2_DN, routing the negative data channel 2 signal to the ESD protection IC and connector. | </details> <details> <summary><b>R801</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DN | ✅ | Connected to HDMI_TX2_C_DN, providing termination for the negative line of HDMI TX2 differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>R802</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DP | ✅ | Connected to HDMI_TX2_C_DP, providing termination for the positive line of HDMI TX2 differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>R803</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DN | ✅ | Connected to HDMI_TX1_C_DN, providing termination for the negative line of HDMI TX1 differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>R804</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DP | ✅ | Connected to HDMI_TX1_C_DP, providing termination for the positive line of HDMI TX1 differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>R805</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DN | ✅ | Connected to HDMI_TX0_C_DN, providing termination for the negative line of HDMI TX0 differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>R806</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DP | ✅ | Connected to HDMI_TX0_C_DP, providing termination for the positive line of HDMI TX0 differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>R807</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CLK_C_DP | ✅ | Connected to HDMI_CLK_C_DP, providing termination for the positive line of HDMI clock differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>R808</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CLK_C_DN | ✅ | Connected to HDMI_CLK_C_DN, providing termination for the negative line of HDMI clock differential pair after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Connected to HDMI_TERM net, which is switched to ground through Q101. | </details> <details> <summary><b>Q101</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | HDMI_TERM | ✅ | Drain connects to HDMI_TERM net, which is the common termination point for eight 619Ω resistors (R801-R808) connected to the HDMI differential signal pairs after AC coupling. This MOSFET switches the termination network to ground. | | G | GATE | $15N747 | ✅ | Gate connects to net $15N747, which connects through 0Ω resistor R809 to +VCC3 power rail. This keeps the MOSFET permanently ON, enabling the termination network at all times. | | S | SOURCE | GND | ✅ | Source connects to GND, which is correct for an N-channel MOSFET used to switch the termination network to ground. | </details> <details> <summary><b>R809</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $15N747 | ✅ | This 0Ω resistor permanently connects the MOSFET gate (net $15N747) to the +VCC3 power rail, keeping Q101 always ON to enable the HDMI termination network. | | 2 | 2 | +VCC3 | ✅ | This 0Ω resistor permanently connects the MOSFET gate (net $15N747) to the +VCC3 power rail, keeping Q101 always ON to enable the HDMI termination network. | </details> <details> <summary><b>L7</b> - 126-0001418 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/ferriteBeadInductortypefilter/ENFA0003_PDF_FERRITEBEADINDUCTORTYPEFILTER?lastModifiedDatetime=20250707190934) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BLM18KG221SN1D) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +HDMI_CRT_VCC | ✅ | Input pin (P1) correctly connected to +HDMI_CRT_VCC from U2's charge pump output, with C157 providing local decoupling. | | 2 | P2 | D5_0V_HDMI | ✅ | Output pin (P2) correctly connected to D5_0V_HDMI which supplies 5V power to the HDMI connector, providing EMI filtering. | </details> <details> <summary><b>P1</b> - 158-0004513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/158-0004513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | HPLG | C_HDMI_HPD | ✅ | Hot plug detect (HPLG) pin correctly connected to C_HDMI_HPD net, which routes to U2 pin 10 for level translation and ESD protection. | | 2 | NC | | ✅ | No connect (NC) pin has no net connection, which is correct for an unused pin. | | 3 | DAT2+ | HDMI_OUT_TX2_DP | ✅ | DAT2+ pin correctly connected to HDMI_OUT_TX2_DP differential signal through U2 and common mode choke L17. | | 4 | DAT2_S | GND | ✅ | DAT2_S shield pin correctly connected to GND for proper shielding of data pair 2. | | 5 | DAT2- | HDMI_OUT_TX2_DN | ✅ | DAT2- pin correctly connected to HDMI_OUT_TX2_DN differential signal through U2 and common mode choke L17. | | 6 | DAT1+ | HDMI_OUT_TX1_DP | ✅ | DAT1+ pin correctly connected to HDMI_OUT_TX1_DP differential signal through U2 and common mode choke L16. | | 7 | DAT1_S | GND | ✅ | DAT1_S shield pin correctly connected to GND for proper shielding of data pair 1. | | 8 | DAT1- | HDMI_OUT_TX1_DN | ✅ | DAT1- pin correctly connected to HDMI_OUT_TX1_DN differential signal through U2 and common mode choke L16. | | 9 | DAT0+ | HDMI_OUT_TX0_DP | ✅ | DAT0+ pin correctly connected to HDMI_OUT_TX0_DP differential signal through U2 and common mode choke L15. | | 10 | DAT0_S | GND | ✅ | DAT0_S shield pin correctly connected to GND for proper shielding of data pair 0. | | 11 | DAT0- | HDMI_OUT_TX0_DN | ✅ | DAT0- pin correctly connected to HDMI_OUT_TX0_DN differential signal through U2 and common mode choke L15. | | 12 | CLK+ | HDMI_OUT_CLK_DP | ✅ | CLK+ pin correctly connected to HDMI_OUT_CLK_DP differential clock signal through U2 and common mode choke L14. | | 13 | CLK_S | GND | ✅ | CLK_S shield pin correctly connected to GND for proper shielding of clock pair. | | 14 | CLK- | HDMI_OUT_CLK_DN | ✅ | CLK- pin correctly connected to HDMI_OUT_CLK_DN differential clock signal through U2 and common mode choke L14. | | 15 | CEC | C_HDMI_CEC | ✅ | CEC pin correctly connected to C_HDMI_CEC net, which routes to U2 pin 7 for level translation and ESD protection. | | 16 | DDC/CEC_GND | GND | ✅ | DDC/CEC_GND pin correctly connected to GND for proper ground reference of DDC and CEC signals. | | 17 | SCL | C_HDMI_SCL | ✅ | SCL pin correctly connected to C_HDMI_SCL net, which routes to U2 pin 8 for level translation and ESD protection. | | 18 | SDA | C_HDMI_SDA | ✅ | SDA pin correctly connected to C_HDMI_SDA net, which routes to U2 pin 9 for level translation and ESD protection. | | 19 | +5V | D5_0V_HDMI | ✅ | +5V pin correctly connected to D5_0V_HDMI net through ferrite bead L7 for EMI filtering of the 5V supply to the connected device. | | 20 | MTG1 | GND_EARTH | ✅ | Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding. | | 21 | MTG2 | GND_EARTH | ✅ | Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding. | | 22 | MTG3 | GND_EARTH | ✅ | Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding. | | 23 | MTG4 | GND_EARTH | ✅ | Mounting tab pins (MTG1-4) correctly connected to GND_EARTH for chassis grounding and shielding. | </details> <details> <summary><b>C157</b> - 123-0001144 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +HDMI_CRT_VCC | ✅ | Positive terminal correctly connected to +HDMI_CRT_VCC for decoupling the charge pump output. | | 2 | 2 | GND | ✅ | Negative terminal correctly connected to GND for decoupling. | </details> <details> <summary><b>C161</b> - 2267-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | One terminal correctly connected to GND for high-voltage isolation between signal ground and chassis ground. | | 2 | 2 | GND_EARTH | ✅ | Other terminal correctly connected to GND_EARTH for high-voltage isolation, providing AC coupling between signal ground and chassis ground for ESD protection. | </details> <details> <summary><b>L2</b> - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP2 | ✅ | Input from U32 channel 2 output (USBP2) for USB port B power distribution. | | 2 | 2 | VBUS2 | ✅ | Output to VBUS2 supplying power to USB port B connector with appropriate bypass and bulk capacitors. | </details> <details> <summary><b>L1</b> - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP1 | ✅ | Input from U32 channel 1 output (USBP1) for USB port A power distribution. | | 2 | 2 | VBUS1 | ✅ | Output to VBUS1 supplying power to USB port A connector with appropriate bypass and bulk capacitors. | </details> <details> <summary><b>FB13</b> - 3044-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3044-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input from +5VSB supply for USB power distribution. | | 2 | 2 | +USBVCC | ✅ | Output to +USBVCC net supplying power to USB power switch U32 and level shifter U4. | </details> <details> <summary><b>U32</b> - AP2172MPG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP2162_72.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/AP2172MPG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | IN | +USBVCC | ✅ | Input power pin correctly connected to +USBVCC with appropriate bypass capacitors (C92, C93, C94). | | 3 | EN1 | USB_HOST_EN0 | ✅ | Enable input for channel 1 correctly connected to level shifter output (U4 pin 1) for port 0 enable control. | | 4 | EN2 | USB_HOST_EN1 | ✅ | Enable input for channel 2 correctly connected to level shifter output (U4 pin 8) for port 1 enable control. | | 5 | OC2# | SOC_USB_HOST_OC1 | ✅ | Overcurrent flag output for channel 2 connected to SOC_USB_HOST_OC1. Open-drain output requires pull-up resistor not visible on this page. | | 6 | OUTB | USBP2 | ✅ | Output for channel 2 correctly connected through ferrite bead L2 to VBUS2 with appropriate output capacitors. | | 7 | OUTA | USBP1 | ✅ | Output for channel 1 correctly connected through ferrite bead L1 to VBUS1 with appropriate output capacitors. | | 8 | OC1# | SOC_USB_HOST_OC0 | ✅ | Overcurrent flag output for channel 1 connected to SOC_USB_HOST_OC0. Open-drain output requires pull-up resistor not visible on this page. | | 9 | GND_PAD | GND | ✅ | Exposed pad correctly connected to GND for thermal and electrical grounding. | </details> <details> <summary><b>U4</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | USB_HOST_EN0 | ✅ | B2 pin correctly connected to USB_HOST_EN0 net, providing VCCB-level output to drive U32 EN1 pin for USB port 1 power control. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground net. | | 3 | VCCA | +V1P8A | ✅ | VCCA pin correctly connected to +V1P8A supply, providing 1.8V reference for A-side I/O as confirmed by schematic notes. | | 4 | A2 | SOC_USB_HOST_EN0 | ✅ | A2 pin correctly connected to SOC_USB_HOST_EN0, receiving 1.8V level enable signal from SOC for channel 2. | | 5 | A1 | SOC_USB_HOST_EN1 | ✅ | A1 pin correctly connected to SOC_USB_HOST_EN1, receiving 1.8V level enable signal from SOC for channel 1. | | 6 | OE | USB_HOST_BUFF_ENB | ✅ | OE pin correctly connected to USB_HOST_BUFF_ENB with 10K pull-up to VCCA, enabling the level translator by default. | | 7 | VCCB | +USBVCC | ✅ | VCCB pin correctly connected to +USBVCC supply, providing reference voltage for B-side I/O to interface with USB power switch. | | 8 | B1 | USB_HOST_EN1 | ✅ | B1 pin correctly connected to USB_HOST_EN1 net, providing VCCB-level output to drive U32 EN2 pin for USB port 2 power control. | </details> <details> <summary><b>R116</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB_HOST_BUFF_ENB | ✅ | 10K pull-up resistor correctly configured to pull OE pin of U4 to VCCA (+V1P8A), enabling the level translator by default. | | 2 | 2 | +V1P8A | ✅ | 10K pull-up resistor correctly configured to pull OE pin of U4 to VCCA (+V1P8A), enabling the level translator by default. | </details> <details> <summary><b>U9</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H0 | ✅ | D+ pin provides ESD protection for the USB 2.0 differential data positive line (USB_H0) going to USB connector port A. | | 2 | D- | USB_L0 | ✅ | D- pin provides ESD protection for the USB 2.0 differential data negative line (USB_L0) going to USB connector port A. | | 3 | ID | | ✅ | ID pin is left floating, which is acceptable for a USB host-only port that does not require OTG ID detection. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the ESD protection device. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as it is not internally connected within the device. | | 6 | VBUS | VBUS1 | ✅ | VBUS pin provides ESD protection for the VBUS1 power line going to USB connector port A. | </details> <details> <summary><b>U8</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H1 | ✅ | D+ pin correctly connected to USB port B D+ signal (USB_H1) for ESD protection of the high-speed differential data line. | | 2 | D- | USB_L1 | ✅ | D- pin correctly connected to USB port B D- signal (USB_L1) for ESD protection of the high-speed differential data line. | | 3 | ID | | ✅ | ID pin is left floating, which is acceptable per the datasheet when the ID function is not used in the application. | | 4 | GND | GND | ✅ | GND pin correctly connected to the ground net for proper ESD protection operation. | | 5 | NC | | ✅ | NC pin correctly left unconnected as it is not internally connected per the datasheet. | | 6 | VBUS | VBUS2 | ✅ | VBUS pin correctly connected to USB port B VBUS signal (VBUS2) for ESD protection of the high-voltage tolerant VBUS line. | </details> <details> <summary><b>U29</b> - TPD4USB30 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/TPD4USB30) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D1+ | USB3_TX0P_C | ✅ | D1+ pin connected to USB3_TX0P_C, which is the USB 3.0 transmit positive differential signal going to the connector. This connection appears correct for ESD protection of the TX+ line. | | 2 | D1- | USB3_TX0N_C | ✅ | D1- pin connected to USB3_TX0N_C, which is the USB 3.0 transmit negative differential signal going to the connector. This connection appears correct for ESD protection of the TX- line. | | 3 | GND1 | GND | ✅ | GND1 pin correctly connected to the GND net for ESD protection reference. | | 4 | D2+ | USB3_RX0P_C | ✅ | D2+ pin connected to USB3_RX0P_C, which is the USB 3.0 receive positive differential signal from the connector. This connection appears correct for ESD protection of the RX+ line. | | 5 | D2- | USB3_RX0N_C | ✅ | D2- pin connected to USB3_RX0N_C, which is the USB 3.0 receive negative differential signal from the connector. This connection appears correct for ESD protection of the RX- line. | | 6 | NC4 | USB3_RX0N_C | ✅ | NC4 pin is connected to USB3_RX0N_C, the same net as pin 5 (D2-). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required. | | 7 | NC3 | USB3_RX0P_C | ✅ | NC3 pin is connected to USB3_RX0P_C, the same net as pin 4 (D2+). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required. | | 8 | GND2 | GND | ✅ | GND2 pin correctly connected to the GND net for ESD protection reference. | | 9 | NC2 | USB3_TX0N_C | ✅ | NC2 pin is connected to USB3_TX0N_C, the same net as pin 2 (D1-). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required. | | 10 | NC1 | USB3_TX0P_C | ✅ | NC1 pin is connected to USB3_TX0P_C, the same net as pin 1 (D1+). The 'NC' designation suggests this should be a no-connect pin, but the connection may be intentional for improved ESD performance. Datasheet verification is required. | </details> <details> <summary><b>CHOKE2</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_TX0P-R | ✅ | IN1 carries the positive USB3 transmit signal (USB3_TX0P-R) from the SOC side through the common mode choke to the connector side (USB3_TX0P_C via OUT1). | | 3 | IN2 | USB3_TX0N-R | ✅ | IN2 carries the negative USB3 transmit signal (USB3_TX0N-R) from the SOC side through the common mode choke to the connector side (USB3_TX0N_C via OUT2). | | 4 | OUT2 | USB3_TX0N_C | ✅ | OUT2 outputs the negative USB3 transmit signal (USB3_TX0N_C) to the connector after common mode filtering. | | 6 | OUT1 | USB3_TX0P_C | ✅ | OUT1 outputs the positive USB3 transmit signal (USB3_TX0P_C) to the connector after common mode filtering. | </details> <details> <summary><b>CHOKE1</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_RX0N_C | ✅ | IN1 carries the negative USB3 receive signal (USB3_RX0N_C) from the connector side through the common mode choke to the SOC side (USB3_RXN0 via OUT1). | | 3 | IN2 | USB3_RX0P_C | ✅ | IN2 carries the positive USB3 receive signal (USB3_RX0P_C) from the connector side through the common mode choke to the SOC side (USB3_RXP0 via OUT2). | | 4 | OUT2 | USB3_RXP0 | ✅ | OUT2 outputs the positive USB3 receive signal (USB3_RXP0) to the SOC after common mode filtering. | | 6 | OUT1 | USB3_RXN0 | ✅ | OUT1 outputs the negative USB3 receive signal (USB3_RXN0) to the SOC after common mode filtering. | </details> <details> <summary><b>CHOKE4</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN0 | ✅ | IN1 pin connected to USB_DN0, serving as the input for the USB D- signal on port 0. This pin is one end of the first winding of the common mode choke. | | 3 | IN2 | USB_DP0 | ✅ | IN2 pin connected to USB_DP0, serving as the input for the USB D+ signal on port 0. This pin is one end of the second winding of the common mode choke. | | 4 | OUT2 | USB_H0 | ✅ | OUT2 pin connected to USB_H0, serving as the output for the USB D+ signal. The signal then connects to ESD protection device U9 pin 1 (D+) and USB connector USB1 pin 3 (DA+). | | 6 | OUT1 | USB_L0 | ✅ | OUT1 pin connected to USB_L0, serving as the output for the USB D- signal. The signal then connects to ESD protection device U9 pin 2 (D-) and USB connector USB1 pin 2 (DA-). | </details> <details> <summary><b>CHOKE3</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN1 | ✅ | IN1 pin connected to USB_DN1, serving as the input for the USB D- signal on port 1. This pin is one end of the first winding of the common mode choke. | | 3 | IN2 | USB_DP1 | ✅ | IN2 pin connected to USB_DP1, serving as the input for the USB D+ signal on port 1. This pin is one end of the second winding of the common mode choke. | | 4 | OUT2 | USB_H1 | ✅ | OUT2 pin connected to USB_H1, serving as the output for the USB D+ signal. The signal then connects to ESD protection device U8 pin 1 (D+) and USB connector USB1 pin 12 (DB+). | | 6 | OUT1 | USB_L1 | ✅ | OUT1 pin connected to USB_L1, serving as the output for the USB D- signal. The signal then connects to ESD protection device U8 pin 2 (D-) and USB connector USB1 pin 11 (DB-). | </details> <details> <summary><b>USB1</b> - DUAL_USB_2.0_3.0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004503) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUSA | VBUS1 | ✅ | VBUSA provides 5V power to USB port A. Power is sourced from +USBVCC through power switch U32 channel A (OUTA), ferrite bead L1, with decoupling capacitors C82 and C91, and ESD protection U9. | | 2 | DA- | USB_L0 | ✅ | DA- is the USB 2.0 D- signal for port A. It connects through common mode choke CHOKE4 and ESD protection U9 to the SOC signal USB_DN0. | | 3 | DA+ | USB_H0 | ✅ | DA+ is the USB 2.0 D+ signal for port A. It connects through common mode choke CHOKE4 and ESD protection U9 to the SOC signal USB_DP0. | | 4 | GNDA | GND | ✅ | GNDA is the ground connection for USB port A, properly connected to the main GND plane. | | 5 | SSRX- | USB3_RX0N_C | ✅ | SSRX- is the USB 3.0 SuperSpeed receive negative signal. It connects through ESD protection U29 and common mode choke CHOKE1 to the SOC signal USB3_RXN0. | | 6 | SSRX+ | USB3_RX0P_C | ✅ | SSRX+ is the USB 3.0 SuperSpeed receive positive signal. It connects through ESD protection U29 and common mode choke CHOKE1 to the SOC signal USB3_RXP0. | | 7 | GND_DRAIN | GND | ✅ | GND_DRAIN is the shield drain ground connection, properly connected to the main GND plane. | | 8 | SSTX- | USB3_TX0N_C | ✅ | SSTX- is the USB 3.0 SuperSpeed transmit negative signal. It connects through ESD protection U29, common mode choke CHOKE2, and AC coupling capacitor C191 to the SOC signal USB3_TXN0. | | 9 | SSTX+ | USB3_TX0P_C | ✅ | SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. It connects through ESD protection U29, common mode choke CHOKE2, and AC coupling capacitor C192 to the SOC signal USB3_TXP0. | | 10 | VBUSB | VBUS2 | ✅ | VBUSB provides 5V power to USB port B. Power is sourced from +USBVCC through power switch U32 channel B (OUTB), ferrite bead L2, with decoupling capacitors C70, C103, and C234, and ESD protection U8. | | 11 | DB- | USB_L1 | ✅ | DB- is the USB 2.0 D- signal for port B. It connects through common mode choke CHOKE3 and ESD protection U8 to the SOC signal USB_DN1. | | 12 | DB+ | USB_H1 | ✅ | DB+ is the USB 2.0 D+ signal for port B. It connects through common mode choke CHOKE3 and ESD protection U8 to the SOC signal USB_DP1. | | 13 | GNDB | GND | ✅ | GNDB is the ground connection for USB port B, properly connected to the main GND plane. | | MH1 | SHIELD1 | GND_EARTH | ✅ | SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management. | | MH2 | SHIELD2 | GND_EARTH | ✅ | SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management. | | MH3 | SHIELD3 | GND_EARTH | ✅ | SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management. | | MH4 | SHIELD4 | GND_EARTH | ✅ | SHIELD1-4 are the connector shield pins, connected to GND_EARTH. A DNI capacitor C211 provides optional AC coupling between GND_EARTH and GND for EMI management. | </details> <details> <summary><b>J10</b> - 158-0004534 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/158-0004534) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 57 | 57 | XDP_H_TDO | ❌ | <details><summary>XDP test data out signal with 51 ohm resistor to +V1P8A. This connection is incorrect - the resistor value is far too low for a pull-up and the topology is wrong for series termination.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="3a073003e5413b0412d7" diff-visibility="full" variant="default" view-coords="42.16,50.37,49.66,57.87" aspect-ratio="1.29" } <ul><li>Pin 57 is connected to net XDP_H_TDO <em>(from schematic)</em></li><li>Resistor R21 (51 ohm, part 110-0002078) connects XDP_H_TDO to +V1P8A power rail <em>(from schematic)</em></li><li>TDO (Test Data Out) is the standard JTAG/XDP output signal from the device under test <em>(reasoning)</em></li><li>TDO is typically an actively driven output signal and does not require a pull-up resistor <em>(reasoning)</em></li><li>A 51 ohm resistor to power would draw approximately 35mA when TDO is driven low (1.8V / 51Ω ≈ 35mA), which is excessively high current for a logic signal <em>(reasoning)</em></li><li>If this is intended as a pull-up resistor, 51 ohms is far too low - typical pull-up values are 1K-10K ohms <em>(reasoning)</em></li><li>If this is intended as series termination, the resistor should be placed in series with the signal path, not connected to the power rail <em>(reasoning)</em></li><li>Other XDP/JTAG signals on J10 (pins 52, 54, 56, 58 for TRSTB, TCK, TMS, TDI) do not have similar resistor connections, making this connection inconsistent with the rest of the interface <em>(from schematic)</em></li><li>The most likely correct configurations would be: (1) a higher value pull-up resistor (1K-10K) if a pull-up is needed, (2) a series resistor in the signal path if termination is needed, or (3) no resistor at all since TDO is typically actively driven <em>(reasoning)</em></li><li>This connection should be corrected to match standard JTAG/XDP interface practices <em>(reasoning)</em></li></ul></details> | | 1 | 1 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 2 | 2 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 13 | 13 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 14 | 14 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 25 | 25 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 26 | 26 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 37 | 37 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 38 | 38 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 49 | 49 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 50 | 50 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 59 | 59 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 60 | 60 | GND | ✅ | Ground pins distributed throughout the connector to provide return paths for high-speed signals and power. | | 3 | 3 | mSATA_TX_P | ✅ | mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5). | | 5 | 5 | mSATA_TX_N | ✅ | mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5). | | 4 | 4 | mSATA_RX_P | ✅ | mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6). | | 6 | 6 | mSATA_RX_N | ✅ | mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6). | | 7 | 7 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 8 | 8 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 19 | 19 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 20 | 20 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 31 | 31 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 32 | 32 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 43 | 43 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 44 | 44 | +5VSB | ✅ | 5V standby power pins distributed throughout the connector. | | 9 | 9 | mPCIE_REFCLK_P | ✅ | mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11). | | 11 | 11 | mPCIE_REFCLK_N | ✅ | mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11). | | 10 | 10 | USB_HOST_DP | ✅ | USB host differential pair (D+ on pin 10, D- on pin 12). | | 12 | 12 | USB_HOST_DN | ✅ | USB host differential pair (D+ on pin 10, D- on pin 12). | | 15 | 15 | mPCIE_TX_P | ✅ | mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17). | | 17 | 17 | mPCIE_TX_N | ✅ | mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17). | | 16 | 16 | mPCIE_RX_N | ✅ | mPCIE receive differential pair with polarity inversion (RX_P on pin 18, RX_N on pin 16). | | 18 | 18 | mPCIE_RX_P | ✅ | mPCIE receive differential pair with polarity inversion (RX_P on pin 18, RX_N on pin 16). | | 21 | 21 | I2C6_SCL | ✅ | I2C clock signal with 10K pull-up to +V1P8S. | | 22 | 22 | mPCIE_WAKEB | ✅ | mPCIE wake signal (active low). | | 23 | 23 | I2C6_SDA | ✅ | I2C data signal with 10K pull-up to +V1P8S. | | 24 | 24 | mPCIe_CLKREQ3_B | ✅ | mPCIE clock request signal (active low). | | 27 | 27 | EXP_GPIO1 | ✅ | General purpose I/O expansion pins. | | 28 | 28 | EXP_GPIO3 | ✅ | General purpose I/O expansion pins. | | 29 | 29 | EXP_GPIO2 | ✅ | General purpose I/O expansion pins. | | 30 | 30 | EXP_GPIO4 | ✅ | General purpose I/O expansion pins. | | 33 | 33 | XDP_H_OBSDATA_A1 | ✅ | XDP observation data bus signals. | | 34 | 34 | XDP_H_OBSDATA_A0 | ✅ | XDP observation data bus signals. | | 35 | 35 | XDP_H_OBSDATA_A2 | ✅ | XDP observation data bus signals. | | 36 | 36 | XDP_H_OBSDATA_A3 | ✅ | XDP observation data bus signals. | | 39 | 39 | XDP_H_PRDYB | ✅ | XDP PRDY signal (active low). | | 40 | 40 | XDP_H_PREQB_PB | ✅ | XDP PREQ signal (active low) buffered through U1 with 200 ohm pull-up. | | 41 | 41 | HOOK0 | ✅ | HOOK0 test signal connected to PMC_RSMRST through 1K resistor. | | 42 | 42 | HOOK1 | ✅ | HOOK1 test signal connected to front panel power button through 0 ohm resistor. | | 45 | 45 | HOOK2 | ✅ | HOOK2 test signal connected to PMC_CORE_PWROK through 1K resistor. | | 46 | 46 | PMC_RSTBTN | ✅ | PMC reset button signal with 1K pull-up to +V1P8S and 0.1uF debounce capacitor. | | 47 | 47 | HOOK6 | ✅ | HOOK6 test signal connected to PMC_PLTRST_R_V1P8 through 1K resistor. | | 48 | 48 | ILB_RTC_TESTB | ✅ | ILB RTC test signal with 1K pull-up to +RTCVCC and 1uF capacitor. | | 51 | 51 | HOOK4 | ✅ | HOOK4 test signal connected to +3VSB through 0 ohm resistor. | | 52 | 52 | XDP_H_TRSTB | ✅ | JTAG reset signal (active low) for XDP interface. | | 53 | 53 | HOOK5 | ✅ | HOOK5 test signal connected to +V1P8S through 0 ohm resistor. | | 54 | 54 | XDP_H_TCK | ✅ | JTAG clock signal for XDP interface. | | 55 | 55 | +V1P8A | ✅ | 1.8V analog power supply for buffer U1 and other analog circuitry. | | 56 | 56 | XDP_H_TMS | ✅ | JTAG mode select signal for XDP interface. | | 58 | 58 | XDP_H_TDI | ✅ | JTAG data input signal for XDP interface. | </details> <details> <summary><b>R3</b> - 200 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001954) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XDP_H_PREQB_PB | ✅ | Connected to XDP_H_PREQB_PB, providing pull-up function for the buffer input. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A power rail, completing the pull-up resistor configuration. | </details> <details> <summary><b>U1</b> - SN74AUP1G34 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](http://www.ti.com/lit/gpn/SN74AUP1G34) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/SN74AUP1G34DBV) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin is correctly left unconnected. | | 2 | A | XDP_H_PREQB_PB | ✅ | Input A is connected to XDP_H_PREQB_PB with a 200 ohm pull-up resistor to +V1P8A, providing proper input conditioning. | | 3 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 4 | Y | XDP_H_PREQB | ✅ | Output Y is connected to XDP_H_PREQB, providing the buffered output signal. | | 5 | VCC | +V1P8A | ✅ | VCC pin is connected to +V1P8A with proper 0.1uF bypass capacitor to ground as recommended by datasheet. | </details> <details> <summary><b>C5</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the bypass capacitor. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A, providing power supply decoupling for U1 as recommended by datasheet. | </details> <details> <summary><b>R6</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal. This pin forms one end of a pull-up resistor for the reset button test signal. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail. This pin provides the pull-up voltage for the PMC_RSTBTN signal. | </details> <details> <summary><b>R7</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | ILB_RTC_TESTB | ✅ | Connected to ILB_RTC_TESTB signal. This pin forms one end of a pull-up resistor for the RTC test signal. | | 2 | 2 | +RTCVCC | ✅ | Connected to +RTCVCC power rail. This pin provides the pull-up voltage for the ILB_RTC_TESTB signal. | </details> <details> <summary><b>C1</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal. This pin provides filtering and debouncing for the reset button signal. | | 2 | 2 | GND | ✅ | Connected to GND. This pin provides the ground reference for the filter capacitor. | </details> <details> <summary><b>C2</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001066) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This pin provides the ground reference for the filter capacitor. | | 2 | 2 | ILB_RTC_TESTB | ✅ | Connected to ILB_RTC_TESTB signal. This pin provides filtering for the RTC test signal. | </details> <details> <summary><b>R13</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SCL | ✅ | Pin 1 connects to I2C6_SCL and serves as one end of the pull-up resistor for the I2C clock line going to expansion connector J10 pin 21. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C clock line. | </details> <details> <summary><b>R14</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SDA | ✅ | Pin 1 connects to I2C6_SDA and serves as one end of the pull-up resistor for the I2C data line going to expansion connector J10 pin 23. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S, providing the pull-up voltage for the I2C data line. | </details> <details> <summary><b>R18</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB | ✅ | 0 ohm jumper connecting +3VSB power rail to expansion connector pin HOOK4 (J10 pin 51). Allows easy disconnection or current measurement of power supply. | | 2 | 2 | HOOK4 | ✅ | 0 ohm jumper connecting +3VSB power rail to expansion connector pin HOOK4 (J10 pin 51). Allows easy disconnection or current measurement of power supply. | </details> <details> <summary><b>R17</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PLTRST_R_V1P8 | ✅ | 1K ohm series resistor connecting PMC_PLTRST_R_V1P8 signal to expansion connector pin HOOK6 (J10 pin 47). Provides current limiting and signal isolation. | | 2 | 2 | HOOK6 | ✅ | 1K ohm series resistor connecting PMC_PLTRST_R_V1P8 signal to expansion connector pin HOOK6 (J10 pin 47). Provides current limiting and signal isolation. | </details> <details> <summary><b>R5</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HOOK1 | ✅ | 0 ohm jumper connecting HOOK1 (J10 pin 42) to FP_PWRBTN signal. Allows easy disconnection or current measurement if needed. | | 2 | 2 | FP_PWRBTN | ✅ | 0 ohm jumper connecting HOOK1 (J10 pin 42) to FP_PWRBTN signal. Allows easy disconnection or current measurement if needed. | </details> <details> <summary><b>R16</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_CORE_PWROK | ✅ | 1K ohm series resistor connecting PMC_CORE_PWROK signal to expansion connector pin HOOK2 (J10 pin 45). Provides current limiting and signal isolation. | | 2 | 2 | HOOK2 | ✅ | 1K ohm series resistor connecting PMC_CORE_PWROK signal to expansion connector pin HOOK2 (J10 pin 45). Provides current limiting and signal isolation. | </details> <details> <summary><b>R15</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSMRST | ✅ | 1K ohm series resistor connecting PMC_RSMRST signal to expansion connector pin HOOK0 (J10 pin 41). Provides current limiting and signal isolation. | | 2 | 2 | HOOK0 | ✅ | 1K ohm series resistor connecting PMC_RSMRST signal to expansion connector pin HOOK0 (J10 pin 41). Provides current limiting and signal isolation. | </details> <details> <summary><b>R20</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 0 ohm jumper connecting +V1P8S power rail to expansion connector pin HOOK5 (J10 pin 53). Allows easy disconnection or current measurement of power supply. | | 2 | 2 | HOOK5 | ✅ | 0 ohm jumper connecting +V1P8S power rail to expansion connector pin HOOK5 (J10 pin 53). Allows easy disconnection or current measurement of power supply. | </details> <details> <summary><b>R21</b> - 110-0002078 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002078) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A power rail (1.8V analog supply), providing the pull-up voltage for the XDP_H_TDO signal through the 51Ω resistor. | | 2 | 2 | XDP_H_TDO | ✅ | Connected to XDP_H_TDO signal (JTAG Test Data Out) which routes to pin 57 of expansion connector J10. The 51Ω value is unusually low for a pull-up resistor and warrants verification against Intel XDP interface specifications, though it may be intentional for signal integrity or impedance matching requirements. | </details> <details> <summary><b>U42</b> - WGI210AT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/WGI210AT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | LAN_PWR_GOOD | $18N3538 | ✅ | LAN_PWR_GOOD output with 10K pullup to +3VSB_LAN. This is a power good indicator signal. | | 2 | NC_SI_CLK_IN | $18N3372 | ✅ | NC_SI_CLK_IN pulled to ground through 1K resistor. This is a not-connected pin being terminated. | | 3 | NC_SI_CRS_DV | $18N3374 | ✅ | NC_SI_CRS_DV pulled to ground through 1K resistor. This is a not-connected pin being terminated. | | 4 | JTAG_TDO | | ✅ | JTAG_TDO left unconnected. This is acceptable for a JTAG output pin when JTAG is not used. | | 5 | NC_SI_RXD1 | $18N3305 | ✅ | NC_SI_RXD1 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated. | | 6 | NC_SI_RXD0 | $18N3303 | ✅ | NC_SI_RXD0 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated. | | 7 | NC_SI_TX_EN | $18N3376 | ✅ | NC_SI_TX_EN pulled to ground through 1K resistor. This is a not-connected pin being terminated. | | 8 | NC_SI_TXD1 | $18N3301 | ✅ | NC_SI_TXD1 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated. | | 9 | NC_SI_TXD0 | $18N3299 | ✅ | NC_SI_TXD0 pulled up to +3VSB_LAN through 10K resistor. This is a not-connected pin being terminated. | | 10 | VDD3P3_10 | +3VSB_LAN | ✅ | VDD3P3_10 connected to +3VSB_LAN power rail with proper decoupling capacitors. | | 11 | VDD0P9_11 | +0V9_LAN | ✅ | VDD0P9_11 connected to +0V9_LAN power rail with proper decoupling capacitors. | | 12 | NVM_SI | $18N2399 | ✅ | NVM_SI (SPI MOSI) connected to EEPROM U43 through 33.2 ohm series resistor with weak pullup. | | 13 | NVM_SK | $18N2397 | ✅ | NVM_SK (SPI clock) connected to EEPROM U43 through 33.2 ohm series resistor. | | 14 | NVM_SO | $18N3554 | ✅ | NVM_SO (SPI MISO) connected to EEPROM U43 through 33.2 ohm series resistor. | | 15 | NVM_CS_N | $18N2395 | ✅ | NVM_CS_N (SPI chip select) connected to EEPROM U43 through 33.2 ohm series resistor. | | 16 | PE_WAKE_N | PMC_PCIE_WAKE | ✅ | PE_WAKE_N connected to PMC_PCIE_WAKE signal for PCIe wake functionality. | | 17 | PE_RST_N | PMC_PLTRST_L | ✅ | PE_RST_N connected to PMC_PLTRST_L signal for PCIe reset functionality. | | 18 | JTAG_TMS | $18N3293 | ✅ | JTAG_TMS pulled up to +3VSB_LAN through 10K resistor for JTAG interface. | | 19 | JTAG_CLK | $18N3295 | ✅ | JTAG_CLK pulled up to +3VSB_LAN through 10K resistor for JTAG interface. | | 20 | PE_TXN | PCIE_C_RXP2 | ✅ | PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity. | | 21 | PE_TXP | PCIE_C_RXN2 | ✅ | PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity. | | 23 | PE_RXN | PCIE_C_TXP2 | ✅ | PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity. | | 24 | PE_RXP | PCIE_C_TXN2 | ✅ | PCIe differential pairs with intentional polarity inversion for routing convenience. PE_TXP/TXN connect to host RX with inverted polarity, and PE_RXP/RXN connect to host TX with inverted polarity. | | 22 | NC/INTVCC | | ✅ | NC/INTVCC pin left unconnected. This pin is either not connected or an internal voltage regulator output. | | 25 | PECLK_N | PCIE_CLK-N2 | ✅ | PECLK_N and PECLK_P connected to PCIe reference clock differential pair with test points. | | 26 | PECLK_P | PCIE_CLK-P2 | ✅ | PECLK_N and PECLK_P connected to PCIe reference clock differential pair with test points. | | 27 | VDD3P3_27 | +3VSB_LAN | ✅ | VDD3P3_27 connected to +3VSB_LAN power rail with proper decoupling capacitors. | | 28 | DEV_OFF_N | $18N3540 | ✅ | DEV_OFF_N pulled up to +3VSB_LAN through 10K resistor. This is a device enable/disable control. | | 29 | JTAG_TDI | $18N3297 | ✅ | JTAG_TDI pulled up to +3VSB_LAN through 10K resistor for JTAG interface. | | 30 | LED1 | LAN-LED1 | ✅ | LED1 output connected through 301 ohm resistor to LINK-LED-N at RJ45 connector. | | 31 | LED0 | LAN-LED0 | ✅ | LED0 output connected directly to RJ45 connector LED2_AC1 pin without series resistor. | | 32 | VDD0P9_32 | +0V9_LAN | ✅ | VDD0P9_32 connected to +0V9_LAN power rail with proper decoupling capacitors. | | 33 | LED2 | LAN-LED2 | ✅ | LED2 output connected through 301 ohm resistor to 1G-LED-N at RJ45 connector. | | 34 | SMB_CLK | LAN-SMB-CLK | ✅ | SMB_CLK connected to LAN-SMB-CLK for SMBus clock interface. | | 35 | SMB_ALRT_N | LAN-SMB-ALERT# | ✅ | SMB_ALRT_N connected to LAN-SMB-ALERT# for SMBus alert signal. | | 36 | SMB_DATA | LAN-SMB-DATA | ✅ | SMB_DATA connected to LAN-SMB-DATA for SMBus data interface. | | 37 | CBOT | $18N2590 | ✅ | CBOT and CTOP pins connected through 0.039uF capacitor for internal voltage regulator. | | 40 | CTOP | $18N2588 | ✅ | CBOT and CTOP pins connected through 0.039uF capacitor for internal voltage regulator. | | 38 | VDD0P9_OUT | +0V9_LAN | ✅ | VDD0P9_OUT connected to +0V9_LAN. This is the internal 0.9V regulator output. | | 39 | VDD1P5_OUT | +1V5_LAN | ✅ | VDD1P5_OUT connected to +1V5_LAN. This is the internal 1.5V regulator output. | | 41 | VDD3P3_41 | +3VSB_LAN | ✅ | VDD3P3_41 connected to +3VSB_LAN power rail with proper decoupling capacitors. | | 42 | VDD0P9_42 | +0V9_LAN | ✅ | VDD0P9_42 connected to +0V9_LAN power rail with proper decoupling capacitors. | | 43 | NC_SI_ARB_IN | | ✅ | NC_SI_ARB_IN and NC_SI_ARB_OUT left unconnected. These are not-connected pins. | | 44 | NC_SI_ARB_OUT | | ✅ | NC_SI_ARB_IN and NC_SI_ARB_OUT left unconnected. These are not-connected pins. | | 45 | XTAL2 | LAN_XTAL2 | ✅ | XTAL2 and XTAL1 connected to 25MHz crystal with 27pF load capacitors. | | 46 | XTAL1 | LAN_XTAL1 | ✅ | XTAL2 and XTAL1 connected to 25MHz crystal with 27pF load capacitors. | | 47 | VDD1P5_47 | +1V5_LAN | ✅ | VDD1P5_47 connected to +1V5_LAN power rail with proper decoupling capacitors. | | 48 | RSET | LAN_RSET | ✅ | RSET connected to ground through 4.99K resistor for setting output impedance. | | 49 | MDI_MINUS3/SER_N | MDI_N3 | ✅ | MDI_MINUS3/SER_N and MDI_PLUS3/SER_P connected to Ethernet differential pair 3 at RJ45 connector. | | 50 | MDI_PLUS3/SER_P | MDI_P3 | ✅ | MDI_MINUS3/SER_N and MDI_PLUS3/SER_P connected to Ethernet differential pair 3 at RJ45 connector. | | 51 | VDD3P3_51 | +3VSB_LAN | ✅ | VDD3P3_51 connected to +3VSB_LAN power rail with proper decoupling capacitors. | | 52 | MDI_MINUS2/SET_N | MDI_N2 | ✅ | MDI_MINUS2/SET_N and MDI_PLUS2 connected to Ethernet differential pair 2 at RJ45 connector. | | 53 | MDI_PLUS2 | MDI_P2 | ✅ | MDI_MINUS2/SET_N and MDI_PLUS2 connected to Ethernet differential pair 2 at RJ45 connector. | | 54 | MDI_MINUS1/SRDS_SIG_DET | MDI_N1 | ✅ | MDI_MINUS1/SRDS_SIG_DET and MDI_PLUS1/SFP_I2C_CLK connected to Ethernet differential pair 1 at RJ45 connector. | | 55 | MDI_PLUS1/SFP_I2C_CLK | MDI_P1 | ✅ | MDI_MINUS1/SRDS_SIG_DET and MDI_PLUS1/SFP_I2C_CLK connected to Ethernet differential pair 1 at RJ45 connector. | | 56 | VDD1P5_56 | +1V5_LAN | ✅ | VDD1P5_56 connected to +1V5_LAN power rail with proper decoupling capacitors. | | 57 | MDI_MINUS0/SFP_I2C_DATA | MDI_N0 | ✅ | MDI_MINUS0/SFP_I2C_DATA and MDI_PLUS0/NC connected to Ethernet differential pair 0 at RJ45 connector. | | 58 | MDI_PLUS0/NC | MDI_P0 | ✅ | MDI_MINUS0/SFP_I2C_DATA and MDI_PLUS0/NC connected to Ethernet differential pair 0 at RJ45 connector. | | 59 | VDD0P9_59 | +0V9_LAN | ✅ | VDD0P9_59 connected to +0V9_LAN power rail with proper decoupling capacitors. | | 60 | SDP3 | | ✅ | SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected. | | 61 | SDP1/PCIE_DIS | | ✅ | SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected. | | 62 | SDP2 | | ✅ | SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected. | | 63 | SDP0 | | ✅ | SDP0, SDP1/PCIE_DIS, SDP2, and SDP3 software defined pins left unconnected. | | 64 | VDD3P3_64 | +3VSB_LAN | ✅ | VDD3P3_64 connected to +3VSB_LAN power rail with proper decoupling capacitors. | | 65 | GND_PAD | GND | ✅ | GND_PAD connected to ground plane. | </details> <details> <summary><b>R830</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pin 1 is connected to +3VSB_LAN and serves as the pull-up voltage source for the WP# pin of U43. | | 2 | 2 | $18N3609 | ✅ | Pin 2 is connected to net $18N3609 (U43 pin 3 WP#) and provides a pull-up to disable hardware write protection. | </details> <details> <summary><b>R835</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2439 | ✅ | Pin 1 is connected to net $18N2439 (U43 pin 1 CS#) and serves as part of the series resistor for the SPI Chip Select line. | | 2 | 2 | $18N2395 | ✅ | Pin 2 is connected to net $18N2395 (U42 pin 15 NVM_CS_N) and serves as part of the series resistor for the SPI Chip Select line. | </details> <details> <summary><b>R831</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pin 1 is connected to +3VSB_LAN and serves as the pull-up voltage source for the HOLD# pin of U43. | | 2 | 2 | $18N3659 | ✅ | Pin 2 is connected to net $18N3659 (U43 pin 7 HOLD#) and provides a pull-up to disable the hold function for normal operation. | </details> <details> <summary><b>R832</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2435 | ✅ | Pin 1 is connected to net $18N2435 (U43 pin 5 SI) and serves as part of the series resistor for the SPI Serial Input line. | | 2 | 2 | $18N2399 | ✅ | Pin 2 is connected to net $18N2399 (U42 pin 12 NVM_SI) and serves as part of the series resistor for the SPI Serial Input line. | </details> <details> <summary><b>R848</b> - 1120-0359 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0359) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pin 1 is connected to +3VSB_LAN and serves as the pull-up voltage source for the SI pin of U43. | | 2 | 2 | $18N2435 | ✅ | Pin 2 is connected to net $18N2435 (U43 pin 5 SI) and provides a weak pull-up to ensure the SI line has a defined state when not actively driven. | </details> <details> <summary><b>R833</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3554 | ✅ | Pin 1 is connected to net $18N3554 (U42 pin 14 NVM_SO) and serves as part of the series resistor for the SPI Serial Output line. | | 2 | 2 | $18N3552 | ✅ | Pin 2 is connected to net $18N3552 (U43 pin 2 SO) and serves as part of the series resistor for the SPI Serial Output line. | </details> <details> <summary><b>R834</b> - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2437 | ✅ | Pin 1 is connected to net $18N2437 (U43 pin 6 SCK) and serves as part of the series resistor for the SPI Serial Clock line. | | 2 | 2 | $18N2397 | ✅ | Pin 2 is connected to net $18N2397 (U42 pin 13 NVM_SK) and serves as part of the series resistor for the SPI Serial Clock line. | </details> <details> <summary><b>U43</b> - AT25DF081A-SSH ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25df081a-datasheet?language=en) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/AT25DF081A-SSH) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | $18N2439 | ✅ | CS# (Chip Select) is correctly connected to the LAN controller (U42 pin 15 NVM_CS_N) through a 33.2Ω series resistor (R835) for signal integrity. | | 2 | SO | $18N3552 | ✅ | SO (Serial Output) is correctly connected to the LAN controller (U42 pin 14 NVM_SO) through a 33.2Ω series resistor (R833) for signal integrity. | | 3 | WP# | $18N3609 | ✅ | WP# (Write Protect) is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R830), disabling hardware write protection as recommended by the datasheet. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 5 | SI | $18N2435 | ✅ | SI (Serial Input) is correctly connected to the LAN controller (U42 pin 12 NVM_SI) through a 33.2Ω series resistor (R832) with a 33.2KΩ pull-up resistor (R848) to +3VSB_LAN. | | 6 | SCK | $18N2437 | ✅ | SCK (Serial Clock) is correctly connected to the LAN controller (U42 pin 13 NVM_SK) through a 33.2Ω series resistor (R834) for signal integrity. | | 7 | HOLD# | $18N3659 | ✅ | HOLD# is correctly pulled up to +3VSB_LAN through a 10KΩ resistor (R831), disabling the hold function for normal operation as recommended by the datasheet. | | 8 | VCC | +3VSB_LAN | ✅ | VCC is correctly connected to +3VSB_LAN (3.3V standby power), which is within the device's operating voltage range of 2.7V to 3.6V. | </details> <details> <summary><b>C428</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise. | | 2 | 2 | GND | ✅ | Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise. | </details> <details> <summary><b>R843</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED1 | ✅ | LED current limiting resistor for the link status LED. Pin 1 connects to LAN-LED1 from U42 LED1 output, pin 2 to LINK-LED-N at J11 pin 13. | | 2 | 2 | LINK-LED-N | ✅ | LED current limiting resistor for the link status LED. Pin 1 connects to LAN-LED1 from U42 LED1 output, pin 2 to LINK-LED-N at J11 pin 13. | </details> <details> <summary><b>J11</b> - 3362-0042 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3362-0042) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | MD1+ | MDI_P0 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 2 | MD1- | MDI_N0 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 3 | MD2+ | MDI_P1 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 4 | MD2- | MDI_N1 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 7 | MD3+ | MDI_P2 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 8 | MD3- | MDI_N2 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 9 | MD4+ | MDI_P3 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 10 | MD4- | MDI_N3 | ✅ | MDI differential pairs for Ethernet connection. These pins connect the four twisted pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) to the WGI210AT Ethernet controller U42. | | 5 | CT1 | $18N3856 | ✅ | Center tap pins of the integrated transformer. Both pins are tied together to net $18N3856 and bypassed to ground through three capacitors (C426, C427, C428) for filtering. | | 6 | CT2 | $18N3856 | ✅ | Center tap pins of the integrated transformer. Both pins are tied together to net $18N3856 and bypassed to ground through three capacitors (C426, C427, C428) for filtering. | | 11 | LED2_AC1 | LAN-LED0 | ✅ | LED2_AC1 pin connects to LAN-LED0 net, which is driven by U42 pin 31 (LED0 output). This is one terminal of the second LED. | | 12 | LED2_AD1 | 1G-LED-N | ✅ | LED2_AD1 pin connects to 1G-LED-N net through R844 (301 ohm) from U42 LED2 output. This is the other terminal of the second LED, indicating Gigabit link status. | | 13 | LED1_C | LINK-LED-N | ✅ | LED1_C pin connects to LINK-LED-N net through R843 (301 ohm) from U42 LED1 output. This is the cathode of the first LED indicating link status. | | 14 | LED1_A | +3VSB_LAN | ✅ | LED1_A pin connects to +3VSB_LAN power supply. This is the anode of the first LED, providing power for the link status indicator. | | 15 | SHLD1 | GND_EARTH | ✅ | Shield pins correctly connected to GND_EARTH for EMI shielding. This provides proper grounding of the connector shield while maintaining isolation from digital ground. | | 16 | SHLD2 | GND_EARTH | ✅ | Shield pins correctly connected to GND_EARTH for EMI shielding. This provides proper grounding of the connector shield while maintaining isolation from digital ground. | </details> <details> <summary><b>C430</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1G-LED-N | ✅ | EMI filtering capacitor on the Gigabit LED line. Pin 1 connects to 1G-LED-N, pin 2 to GND, reducing emissions from LED switching. | | 2 | 2 | GND | ✅ | EMI filtering capacitor on the Gigabit LED line. Pin 1 connects to 1G-LED-N, pin 2 to GND, reducing emissions from LED switching. | </details> <details> <summary><b>C427</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise. | | 2 | 2 | GND | ✅ | Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise. | </details> <details> <summary><b>C431</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED0 | ✅ | EMI filtering capacitor on the LAN-LED0 line. Pin 1 connects to LAN-LED0, pin 2 to GND, reducing emissions from LED switching. | | 2 | 2 | GND | ✅ | EMI filtering capacitor on the LAN-LED0 line. Pin 1 connects to LAN-LED0, pin 2 to GND, reducing emissions from LED switching. | </details> <details> <summary><b>C429</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LINK-LED-N | ✅ | EMI filtering capacitor on the link LED line. Pin 1 connects to LINK-LED-N, pin 2 to GND, reducing emissions from LED switching. | | 2 | 2 | GND | ✅ | EMI filtering capacitor on the link LED line. Pin 1 connects to LINK-LED-N, pin 2 to GND, reducing emissions from LED switching. | </details> <details> <summary><b>R844</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED2 | ✅ | LED current limiting resistor for the Gigabit link status LED. Pin 1 connects to LAN-LED2 from U42 LED2 output, pin 2 to 1G-LED-N at J11 pin 12. | | 2 | 2 | 1G-LED-N | ✅ | LED current limiting resistor for the Gigabit link status LED. Pin 1 connects to LAN-LED2 from U42 LED2 output, pin 2 to 1G-LED-N at J11 pin 12. | </details> <details> <summary><b>C426</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise. | | 2 | 2 | GND | ✅ | Center tap bypass capacitor. Pin 1 connects to the transformer center tap net $18N3856, pin 2 to GND, providing filtering for common-mode noise. | </details> <details> <summary><b>C253</b> - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Load capacitor for crystal oscillator connected between LAN_XTAL2 and ground. The 27pF value is typical for crystal oscillator circuits. | | 2 | 2 | GND | ✅ | Load capacitor for crystal oscillator connected between LAN_XTAL2 and ground. The 27pF value is typical for crystal oscillator circuits. | </details> <details> <summary><b>X1</b> - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Crystal pin connected to LAN_XTAL2 net, which connects to U42 pin 45 (XTAL2). This is one of the two active crystal oscillator pins. | | 2 | 2 | GND | ✅ | Ground connection for crystal case/shield. This is correct for a 4-pin crystal package. | | 3 | 3 | LAN_XTAL1 | ✅ | Crystal pin connected to LAN_XTAL1 net, which connects to U42 pin 46 (XTAL1). This is one of the two active crystal oscillator pins. | | 4 | 4 | GND | ✅ | Ground connection for crystal case/shield. This is correct for a 4-pin crystal package. | </details> <details> <summary><b>R836</b> - 1120-0018 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0018) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | RSET resistor connected between ground and U42 pin 48 (RSET). This resistor sets the output impedance of the MDI interface. | | 2 | 2 | LAN_RSET | ✅ | RSET resistor connected between ground and U42 pin 48 (RSET). This resistor sets the output impedance of the MDI interface. | </details> <details> <summary><b>C252</b> - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL1 | ✅ | Load capacitor for crystal oscillator connected between LAN_XTAL1 and ground. The 27pF value is typical for crystal oscillator circuits. | | 2 | 2 | GND | ✅ | Load capacitor for crystal oscillator connected between LAN_XTAL1 and ground. The 27pF value is typical for crystal oscillator circuits. | </details> <details> <summary><b>FB12</b> - 3044-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3044-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB | ✅ | Input pin connected to +3VSB main standby rail. This ferrite bead filters the 3.3V standby supply for the LAN section. | | 2 | 2 | +3VSB_LAN | ✅ | Output pin connected to +3VSB_LAN filtered rail. Provides filtered 3.3V power to the LAN controller U42. | </details> <details> <summary><b>C423</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply. | | 2 | 2 | GND | ✅ | Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply. | </details> <details> <summary><b>C424</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply. | | 2 | 2 | GND | ✅ | Bulk decoupling capacitor for +3VSB_LAN rail. 10uF capacitor provides energy storage for the LAN controller 3.3V supply. | </details> <details> <summary><b>C413</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | </details> <details> <summary><b>C414</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | </details> <details> <summary><b>C415</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | </details> <details> <summary><b>C416</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | </details> <details> <summary><b>C417</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +3VSB_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | </details> <details> <summary><b>C419</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +1V5_LAN | ✅ | Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply. | | 2 | 2 | GND | ✅ | Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply. | </details> <details> <summary><b>C420</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +0V9_LAN | ✅ | Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply. | | 2 | 2 | GND | ✅ | Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply. | </details> <details> <summary><b>C421</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +1V5_LAN | ✅ | Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply. | | 2 | 2 | GND | ✅ | Bulk decoupling capacitor for +1V5_LAN rail. 10uF capacitor provides energy storage for the LAN controller 1.5V supply. | </details> <details> <summary><b>C422</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +0V9_LAN | ✅ | Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply. | | 2 | 2 | GND | ✅ | Bulk decoupling capacitor for +0V9_LAN rail. 10uF capacitor provides energy storage for the LAN controller 0.9V core supply. | </details> <details> <summary><b>C408</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +0V9_LAN | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | </details> <details> <summary><b>C409</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +0V9_LAN | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | </details> <details> <summary><b>C410</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +0V9_LAN | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | </details> <details> <summary><b>C411</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +1V5_LAN | ✅ | High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | </details> <details> <summary><b>C412</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +1V5_LAN | ✅ | High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +1V5_LAN rail. 0.1uF capacitor provides local high-frequency filtering. | </details> <details> <summary><b>C418</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +0V9_LAN | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor for +0V9_LAN rail. 0.1uF capacitor provides local high-frequency filtering for the core supply. | </details> <details> <summary><b>C425</b> - 2221-0017 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2221-0017) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2588 | ✅ | Compensation capacitor for U42 internal voltage regulator. Connected between CTOP and CBOT pins for regulator stability. | | 2 | 2 | $18N2590 | ✅ | Compensation capacitor for U42 internal voltage regulator. Connected between CTOP and CBOT pins for regulator stability. | </details> <details> <summary><b>R820</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for JTAG_TMS signal on U42. | | 2 | 2 | $18N3293 | ✅ | Connected to JTAG_TMS signal net $18N3293. | </details> <details> <summary><b>R821</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for JTAG_CLK signal on U42. | | 2 | 2 | $18N3295 | ✅ | Connected to JTAG_CLK signal net $18N3295. | </details> <details> <summary><b>R822</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for JTAG_TDI signal on U42. | | 2 | 2 | $18N3297 | ✅ | Connected to JTAG_TDI signal net $18N3297. | </details> <details> <summary><b>R823</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_TXD0 signal on U42. | | 2 | 2 | $18N3299 | ✅ | Connected to NC_SI_TXD0 signal net $18N3299. | </details> <details> <summary><b>R824</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_TXD1 signal on U42. | | 2 | 2 | $18N3301 | ✅ | Connected to NC_SI_TXD1 signal net $18N3301. | </details> <details> <summary><b>R825</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_RXD0 signal on U42. | | 2 | 2 | $18N3303 | ✅ | Connected to NC_SI_RXD0 signal net $18N3303. | </details> <details> <summary><b>R826</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for NC_SI_RXD1 signal on U42. | | 2 | 2 | $18N3305 | ✅ | Connected to NC_SI_RXD1 signal net $18N3305. | </details> <details> <summary><b>R827</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for DEV_OFF_N signal on U42. | | 2 | 2 | $18N3540 | ✅ | Connected to DEV_OFF_N signal net $18N3540. | </details> <details> <summary><b>R828</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connected to +3VSB_LAN power rail. Provides pull-up for LAN_PWR_GOOD signal on U42. | | 2 | 2 | $18N3538 | ✅ | Connected to LAN_PWR_GOOD signal net $18N3538. | </details> <details> <summary><b>R837</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3372 | ✅ | Pull-down resistor connected to NC_SI_CLK_IN signal. Pulls the serial interface clock input to ground when not driven. | | 2 | 2 | GND | ✅ | Connected to ground. | </details> <details> <summary><b>R838</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3374 | ✅ | Pull-down resistor connected to NC_SI_CRS_DV signal. Pulls the carrier sense/data valid signal to ground when not active. | | 2 | 2 | GND | ✅ | Connected to ground. | </details> <details> <summary><b>R839</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3376 | ✅ | Pull-down resistor connected to NC_SI_TX_EN signal. Pulls the transmit enable signal to ground (disabled) when not driven. | | 2 | 2 | GND | ✅ | Connected to ground. | </details> <details> <summary><b>U7</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | UART2_RXD | ✅ | B2 pin connects to UART2_RXD net, which is the 3.3V side of the UART2 receive data signal going to external connector JP1 pin 19. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin is connected to +V1P8S (1.8V supply) with appropriate decoupling capacitor C350 nearby. | | 4 | A2 | SIO_UART2_RXD | ✅ | A2 pin connects to SIO_UART2_RXD, which is the 1.8V side of the UART2 receive data signal from the SIO/SOC. | | 5 | A1 | SIO_UART2_TXD | ✅ | A1 pin connects to SIO_UART2_TXD, which is the 1.8V side of the UART2 transmit data signal from the SIO/SOC. | | 6 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin is connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is not in reset. | | 7 | VCCB | +3VSB | ✅ | VCCB pin is connected to +3VSB (3.3V standby supply) with appropriate decoupling capacitor C351 nearby. | | 8 | B1 | UART2_TXD | ✅ | B1 pin connects to UART2_TXD net, which is the 3.3V side of the UART2 transmit data signal going to external connector JP1 pin 17. | </details> <details> <summary><b>U15</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin is connected to +V1P8S (1.8V supply) with appropriate decoupling capacitor C356 nearby. | | 2 | A1 | SIO_UART1_RTSB | ✅ | A1 pin connects to SIO_UART1_RTSB, which is the 1.8V side of the UART1 Request To Send signal (active low) from the SIO/SOC. | | 3 | A2 | SIO_UART1_CTSB | ✅ | A2 pin connects to SIO_UART1_CTSB, which is the 1.8V side of the UART1 Clear To Send signal (active low) from the SIO/SOC. | | 4 | A3 | SIO_UART1_RXD | ✅ | A3 pin connects to SIO_UART1_RXD, which is the 1.8V side of the UART1 receive data signal from the SIO/SOC. | | 5 | A4 | SIO_UART1_TXD | ✅ | A4 pin connects to SIO_UART1_TXD, which is the 1.8V side of the UART1 transmit data signal from the SIO/SOC. | | 6 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 7 | B4 | UART1_TXD | ✅ | B4 pin connects to UART1_TXD net, which is the 3.3V side of the UART1 transmit data signal going to external connector JP1 pin 6. | | 8 | B3 | UART1_RXD | ✅ | B3 pin connects to UART1_RXD net, which is the 3.3V side of the UART1 receive data signal going to external connector JP1 pin 8. | | 9 | B2 | UART1_CTSB | ✅ | B2 pin connects to UART1_CTSB net, which is the 3.3V side of the UART1 Clear To Send signal (active low) going to external connector JP1 pin 10. | | 10 | B1 | UART1_RTSB | ✅ | B1 pin connects to UART1_RTSB net, which is the 3.3V side of the UART1 Request To Send signal (active low) going to external connector JP1 pin 12. | | 11 | VCCB | +3VSB | ✅ | VCCB pin is connected to +3VSB (3.3V standby supply) with appropriate decoupling capacitor C357 nearby. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin is connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is not in reset. | </details> <details> <summary><b>U17</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing the reference voltage for the A-side (1.8V) of the level translator. | | 2 | A1 | I2S_MCLK | ✅ | A1 is correctly connected to I2S_MCLK, which is translated to I2SMCLK_GPIO on the B-side through B1. | | 3 | A2 | SOC_PWM1 | ✅ | A2 is correctly connected to SOC_PWM1, which is translated to PWM1 on the B-side through B2. | | 4 | A3 | SOC_PWM0 | ✅ | A3 is correctly connected to SOC_PWM0, which is translated to PWM0 on the B-side through B3. | | 5 | A4 | | ✅ | A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components. | | 7 | B4 | GND | ✅ | A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net, providing the common reference for the level translator. | | 8 | B3 | PWM0 | ✅ | B3 is correctly connected to PWM0, forming the B-side of the translation pair with A3. | | 9 | B2 | PWM1 | ✅ | B2 is correctly connected to PWM1, forming the B-side of the translation pair with A2. | | 10 | B1 | I2SMCLK_GPIO | ✅ | B1 is correctly connected to I2SMCLK_GPIO, forming the B-side of the translation pair with A1. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing the reference voltage for the B-side (3.3V) of the level translator using an always-on 3.3V standby supply. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator after platform reset is deasserted. | </details> <details> <summary><b>U10</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the reference voltage for the A-side (1.8V) of the level translator. | | 2 | A1 | SOC_GPIO_S5_2 | ✅ | A1 is correctly connected to SOC_GPIO_S5_2, which is translated to GPIO_S5_2 on the B-side through B1. | | 3 | A2 | SOC_GPIO_S5_1 | ✅ | A2 is correctly connected to SOC_GPIO_S5_1, which is translated to GPIO_S5_1 on the B-side through B2. | | 4 | A3 | SOC_GPIO_S5_0 | ✅ | A3 is correctly connected to SOC_GPIO_S5_0, which is translated to GPIO_S5_0 on the B-side through B3. | | 5 | A4 | | ✅ | A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components. | | 7 | B4 | GND | ✅ | A4 is left unconnected while B4 is tied to GND. This configuration disables the fourth channel and appears intentional given the consistent implementation across multiple similar components. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net, providing the common reference for the level translator. | | 8 | B3 | GPIO_S5_0 | ✅ | B3 is correctly connected to GPIO_S5_0, forming the B-side of the translation pair with A3. | | 9 | B2 | GPIO_S5_1 | ✅ | B2 is correctly connected to GPIO_S5_1, forming the B-side of the translation pair with A2. | | 10 | B1 | GPIO_S5_2 | ✅ | B1 is correctly connected to GPIO_S5_2, forming the B-side of the translation pair with A1. | | 11 | VCCB | +PS_3VSB | ✅ | VCCB is correctly connected to +PS_3VSB, providing the reference voltage for the B-side (3.3V) of the level translator. This matches the design note requiring an always-on 3.3V supply. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator after platform reset is deasserted. | </details> <details> <summary><b>U14</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to the +V1P8S (1.8V) supply rail, providing the A-side reference voltage for the level translator. | | 2 | A1 | SOC_SIO_SPI_CLK | ✅ | A1 is correctly connected to SOC_SIO_SPI_CLK, translating the SPI clock signal from the 1.8V SOC domain to the 3.3V domain on B1. | | 3 | A2 | SOC_SIO_SPI_MOSI | ✅ | A2 is correctly connected to SOC_SIO_SPI_MOSI, translating the SPI MOSI signal from the 1.8V SOC domain to the 3.3V domain on B2. | | 4 | A3 | SOC_SIO_SPI_MISO | ✅ | A3 is correctly connected to SOC_SIO_SPI_MISO, translating the SPI MISO signal from the 1.8V SOC domain to the 3.3V domain on B3. | | 5 | A4 | SOC_SIO_SPI_CS1 | ✅ | A4 is correctly connected to SOC_SIO_SPI_CS1, translating the SPI chip select signal from the 1.8V SOC domain to the 3.3V domain on B4. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SIO_SPI_CS1 | ✅ | B4 is correctly connected to SIO_SPI_CS1, providing the 3.3V level-translated SPI chip select signal to the GPIO header. | | 8 | B3 | SIO_SPI_MISO | ✅ | B3 is correctly connected to SIO_SPI_MISO, providing the 3.3V level-translated SPI MISO signal to the GPIO header. | | 9 | B2 | SIO_SPI_MOSI | ✅ | B2 is correctly connected to SIO_SPI_MOSI, providing the 3.3V level-translated SPI MOSI signal to the GPIO header. | | 10 | B1 | SIO_SPI_CLK | ✅ | B1 is correctly connected to SIO_SPI_CLK, providing the 3.3V level-translated SPI clock signal to the GPIO header. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to the +3VSB (3.3V standby) supply rail, providing the B-side reference voltage for the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset. | </details> <details> <summary><b>U16</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA power supply pin correctly connected to +V1P8S (1.8V supply) to power the A-side of the level translator. | | 2 | A1 | I2S_DATIN_R | ✅ | A1 pin correctly connected to I2S_DATIN_R signal, which connects through R128 to LPE_I2S_DATIN. This translates the I2S data input signal from 1.8V to 3.3V for the GPIO header. | | 3 | A2 | I2S_DATOUT_R | ✅ | A2 pin correctly connected to I2S_DATOUT_R signal, which connects through R130 to LPE_I2S_DATOUT. This translates the I2S data output signal from 1.8V to 3.3V for the GPIO header. | | 4 | A3 | I2S_FRM_R | ✅ | A3 pin correctly connected to I2S_FRM_R signal, which connects through R129 to LPE_I2S_FRM. This translates the I2S frame signal from 1.8V to 3.3V for the GPIO header. | | 5 | A4 | I2S_CLK_R | ✅ | A4 pin correctly connected to I2S_CLK_R signal, which connects through R127 to LPE_I2S_CLK. This translates the I2S clock signal from 1.8V to 3.3V for the GPIO header. | | 6 | GND | GND | ✅ | GND pin correctly connected to the ground net. | | 7 | B4 | I2SCLK_GPIO | ✅ | B4 pin correctly connected to I2SCLK_GPIO signal, which goes to JP1 pin 14. This is the 3.3V side of the I2S clock signal pair with A4. | | 8 | B3 | I2SFRM_GPIO | ✅ | B3 pin correctly connected to I2SFRM_GPIO signal, which goes to JP1 pin 16. This is the 3.3V side of the I2S frame signal pair with A3. | | 9 | B2 | I2SDO_GPIO | ✅ | B2 pin correctly connected to I2SDO_GPIO signal, which goes to JP1 pin 18. This is the 3.3V side of the I2S data output signal pair with A2. | | 10 | B1 | I2SDI_GPIO | ✅ | B1 pin correctly connected to I2SDI_GPIO signal, which goes to JP1 pin 20. This is the 3.3V side of the I2S data input signal pair with A1. | | 11 | VCCB | +3VSB | ✅ | VCCB power supply pin correctly connected to +3VSB (3.3V standby supply) to power the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE (output enable) pin correctly connected to PMC_PLTRST_R_V1P8, which is a platform reset signal at 1.8V level. This enables the translator when the platform is out of reset. | </details> <details> <summary><b>R127</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_CLK_R | ✅ | 0-ohm resistor connecting I2S_CLK_R from U16 pin 5 to LPE_I2S_CLK. This provides a direct connection with optional series termination capability. | | 2 | 2 | LPE_I2S_CLK | ✅ | 0-ohm resistor connecting I2S_CLK_R from U16 pin 5 to LPE_I2S_CLK. This provides a direct connection with optional series termination capability. | </details> <details> <summary><b>R128</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_DATIN_R | ✅ | 0-ohm resistor connecting I2S_DATIN_R from U16 pin 2 to LPE_I2S_DATIN. This provides a direct connection with optional series termination capability. | | 2 | 2 | LPE_I2S_DATIN | ✅ | 0-ohm resistor connecting I2S_DATIN_R from U16 pin 2 to LPE_I2S_DATIN. This provides a direct connection with optional series termination capability. | </details> <details> <summary><b>R129</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_FRM_R | ✅ | 0-ohm resistor connecting I2S_FRM_R from U16 pin 4 to LPE_I2S_FRM. This provides a direct connection with optional series termination capability. | | 2 | 2 | LPE_I2S_FRM | ✅ | 0-ohm resistor connecting I2S_FRM_R from U16 pin 4 to LPE_I2S_FRM. This provides a direct connection with optional series termination capability. | </details> <details> <summary><b>R130</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_DATOUT_R | ✅ | 0-ohm resistor connecting I2S_DATOUT_R from U16 pin 3 to LPE_I2S_DATOUT. This provides a direct connection with optional series termination capability. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | 0-ohm resistor connecting I2S_DATOUT_R from U16 pin 3 to LPE_I2S_DATOUT. This provides a direct connection with optional series termination capability. | </details> <details> <summary><b>U18</b> - NTB0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0008) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the A-side reference voltage for the level translator. | | 2 | A1 | SOC_SPI_MOSI-R | ✅ | A1 is correctly connected to SOC_SPI_MOSI-R for SPI MOSI signal translation from the SOC side. | | 3 | A2 | SOC_SPI_CLK-R | ✅ | A2 is correctly connected to SOC_SPI_CLK-R for SPI clock signal translation from the SOC side. | | 4 | A3 | SOC_SPI_MISO-R | ✅ | A3 is correctly connected to SOC_SPI_MISO-R for SPI MISO signal translation from the SOC side. | | 5 | A4 | SOC_SPI_CS0B-R | ✅ | A4 is correctly connected to SOC_SPI_CS0B-R for SPI chip select signal translation from the SOC side. | | 6 | GND | GND | ✅ | GND is correctly connected to ground. | | 7 | B4 | SPI_CS0 | ✅ | B4 is correctly connected to SPI_CS0 for SPI chip select signal on the B-side. | | 8 | B3 | SPI_MISO | ✅ | B3 is correctly connected to SPI_MISO for SPI MISO signal on the B-side. | | 9 | B2 | SPI_CLK | ✅ | B2 is correctly connected to SPI_CLK for SPI clock signal on the B-side. | | 10 | B1 | SPI_MOSI | ✅ | B1 is correctly connected to SPI_MOSI for SPI MOSI signal on the B-side. | | 11 | VCCB | +V_SPI | ✅ | VCCB is correctly connected to +V_SPI, providing the B-side reference voltage for the level translator. | | 12 | OE | DDP_IO3L | ✅ | OE is correctly connected to DDP_IO3L with pull-up resistor R147, enabling the translator by default and allowing external control via the DediProg connector. | </details> <details> <summary><b>R147</b> - 100K ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001859) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pin 1 is correctly connected to +V1P8A to provide pull-up voltage for the OE signal. | | 2 | 2 | DDP_IO3L | ✅ | Pin 2 is correctly connected to DDP_IO3L, providing pull-up for the OE pin of U18. | </details> <details> <summary><b>U40</b> - PCA9306DCUT ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fpca9306) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4318-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | SDA2 | GPIO_I2C_SDA | ❌ | <details><summary>SCL2 (pin 6) and SDA2 (pin 5) are connected to GPIO_I2C_SCL and GPIO_I2C_SDA respectively, which route to header JP1. However, no pullup resistors are present on these high-voltage side I2C signals, which are required for proper open-drain I2C operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,77.42,31.26,84.92" aspect-ratio="1.29" } <ul><li>Pin 5 (SDA2) is connected to GPIO_I2C_SDA net, which routes to JP1 pin 15 <em>(from schematic)</em></li><li>Pin 6 (SCL2) is connected to GPIO_I2C_SCL net, which routes to JP1 pin 13 <em>(from schematic)</em></li><li>Pin 7 (VREF2) and pin 8 (EN) are both connected to net $20N1576, which connects through R812 (200K) to +3VSB <em>(from schematic)</em></li><li>No pullup resistors are present on GPIO_I2C_SDA or GPIO_I2C_SCL nets to +3VSB or any other high-voltage supply <em>(from schematic)</em></li><li>The low-voltage side pins 3 (SCL1) and 4 (SDA1) have proper pullup resistors R267 and R266 (10K) to +V1P8S <em>(from schematic)</em></li><li>Pin 5 is SDA2 (serial data, high-voltage side) and pin 6 is SCL2 (serial clock, high-voltage side) <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">4318-0010</a>, page 4)</em></li><li>Datasheet states: &#x27;Translation on standard open-drain I2C bus is achieved by connecting pull-up resistors from SCL1 and SDA1 to VREF1 and from SCL2 and SDA2 to VDPU&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=16">4318-0010</a>, page 16)</em></li><li>Typical application circuits in the datasheet show pullup resistors (RPU) on both SCL2 and SDA2 to the high-voltage supply <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17">4318-0010</a>, page 17)</em></li><li>The datasheet application section emphasizes that pullup resistors are required for open-drain I2C operation <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=18">4318-0010</a>, page 18)</em></li><li>Without pullup resistors, the I2C bus cannot function properly as there is no mechanism to pull the lines high <em>(reasoning)</em></li><li>The presence of pullup resistors on the low-voltage side (R266, R267) indicates the designer understood this requirement, making the omission on the high-voltage side likely an oversight rather than intentional <em>(reasoning)</em></li><li>While it is possible that external devices connected via JP1 could provide pullup resistors, this is not documented in the schematic and creates an undocumented dependency on external hardware <em>(reasoning)</em></li><li>Best practice requires either: (1) including pullup resistors on this board (e.g., 10K from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB), or (2) adding a clear schematic note indicating that external pullup resistors are required <em>(reasoning)</em></li><li>The design as shown is incomplete and will not function without modification or external components <em>(reasoning)</em></li></ul></details> | | 6 | SCL2 | GPIO_I2C_SCL | ❌ | <details><summary>SCL2 (pin 6) and SDA2 (pin 5) are connected to GPIO_I2C_SCL and GPIO_I2C_SDA respectively, which route to header JP1. However, no pullup resistors are present on these high-voltage side I2C signals, which are required for proper open-drain I2C operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.33" aspect-ratio="1.29" } <ul><li>Pin 5 (SDA2) is connected to GPIO_I2C_SDA net, which routes to JP1 pin 15 <em>(from schematic)</em></li><li>Pin 6 (SCL2) is connected to GPIO_I2C_SCL net, which routes to JP1 pin 13 <em>(from schematic)</em></li><li>Pin 7 (VREF2) and pin 8 (EN) are both connected to net $20N1576, which connects through R812 (200K) to +3VSB <em>(from schematic)</em></li><li>No pullup resistors are present on GPIO_I2C_SDA or GPIO_I2C_SCL nets to +3VSB or any other high-voltage supply <em>(from schematic)</em></li><li>The low-voltage side pins 3 (SCL1) and 4 (SDA1) have proper pullup resistors R267 and R266 (10K) to +V1P8S <em>(from schematic)</em></li><li>Pin 5 is SDA2 (serial data, high-voltage side) and pin 6 is SCL2 (serial clock, high-voltage side) <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">4318-0010</a>, page 4)</em></li><li>Datasheet states: &#x27;Translation on standard open-drain I2C bus is achieved by connecting pull-up resistors from SCL1 and SDA1 to VREF1 and from SCL2 and SDA2 to VDPU&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=16">4318-0010</a>, page 16)</em></li><li>Typical application circuits in the datasheet show pullup resistors (RPU) on both SCL2 and SDA2 to the high-voltage supply <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17">4318-0010</a>, page 17)</em></li><li>The datasheet application section emphasizes that pullup resistors are required for open-drain I2C operation <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=18">4318-0010</a>, page 18)</em></li><li>Without pullup resistors, the I2C bus cannot function properly as there is no mechanism to pull the lines high <em>(reasoning)</em></li><li>The presence of pullup resistors on the low-voltage side (R266, R267) indicates the designer understood this requirement, making the omission on the high-voltage side likely an oversight rather than intentional <em>(reasoning)</em></li><li>While it is possible that external devices connected via JP1 could provide pullup resistors, this is not documented in the schematic and creates an undocumented dependency on external hardware <em>(reasoning)</em></li><li>Best practice requires either: (1) including pullup resistors on this board (e.g., 10K from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB), or (2) adding a clear schematic note indicating that external pullup resistors are required <em>(reasoning)</em></li><li>The design as shown is incomplete and will not function without modification or external components <em>(reasoning)</em></li></ul></details> | | 1 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 2 | VREF1 | +V1P8S | ✅ | VREF1 correctly connected to +V1P8S (1.8V) low-voltage reference supply. | | 3 | SCL1 | I2C5_SCL | ✅ | SCL1 correctly connected to I2C5_SCL with 10K pullup resistor R267 to +V1P8S. | | 4 | SDA1 | I2C5_SDA | ✅ | SDA1 correctly connected to I2C5_SDA with 10K pullup resistor R266 to +V1P8S. | | 7 | VREF2 | $20N1576 | ✅ | VREF2 and EN pins correctly shorted together and pulled to +3VSB through 200K resistor R812 per datasheet application guidance. | | 8 | EN | $20N1576 | ✅ | VREF2 and EN pins correctly shorted together and pulled to +3VSB through 200K resistor R812 per datasheet application guidance. | </details> <details> <summary><b>R266</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C5_SDA | ✅ | Connected to I2C5_SDA, providing pullup for SDA1 line of U40. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply, completing the pullup resistor function. | </details> <details> <summary><b>R267</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C5_SCL | ✅ | Connected to I2C5_SCL, providing pullup for SCL1 line of U40. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply, completing the pullup resistor function. | </details> <details> <summary><b>R812</b> - 110-0001951 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001951) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N1576 | ✅ | Connected to net $20N1576 which shorts U40 VREF2 and EN pins together. | | 2 | 2 | +3VSB | ✅ | Connected to +3VSB supply, providing the required 200K pullup for VREF2/EN per datasheet. | </details> <details> <summary><b>R818</b> - 0R00 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | R818 is correctly marked DNI (Do Not Install) because U3 is populated with W25Q64BVSSIG, a 3.3V SPI flash part. R818 would connect +V1P8A (1.8V) to the voltage selection circuit, but since a 3.3V part is used, R152 is populated instead to connect +3VSB. | | 2 | 2 | +V1P8A | ✅ | R818 is correctly marked DNI (Do Not Install) because U3 is populated with W25Q64BVSSIG, a 3.3V SPI flash part. R818 would connect +V1P8A (1.8V) to the voltage selection circuit, but since a 3.3V part is used, R152 is populated instead to connect +3VSB. | </details> <details> <summary><b>R152</b> - 0R00 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | R152 is correctly populated as a 0-ohm jumper to connect +3VSB (3.3V) to the SPI flash power selection circuit, matching the installed W25Q64BVSSIG 3.3V part. | | 2 | 2 | +3VSB | ✅ | R152 is correctly populated as a 0-ohm jumper to connect +3VSB (3.3V) to the SPI flash power selection circuit, matching the installed W25Q64BVSSIG 3.3V part. | </details> <details> <summary><b>R163</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | R163 correctly provides a 10K pull-up resistor on the CS# pin of U3, matching the datasheet recommendation. | | 2 | 2 | SPI_CS0 | ✅ | R163 correctly provides a 10K pull-up resistor on the CS# pin of U3, matching the datasheet recommendation. | </details> <details> <summary><b>D8</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | DDP_VCC | ✅ | Anode 1 is correctly connected to DDP_VCC (DediProg connector power) for OR-ing power sources. | | A2 | A2 | $20N2079 | ✅ | Anode 2 is correctly connected to $20N2079, which connects through R152 to +3VSB for system power supply. | | C | C | +V_SPI | ✅ | Common cathode is correctly connected to +V_SPI, providing the OR-ed power output to the SPI flash. | </details> <details> <summary><b>R164</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | R164 correctly provides a 10K pull-up resistor on the WP# pin of U3 to disable write protection in standard SPI mode. | | 2 | 2 | SPI_WP | ✅ | R164 correctly provides a 10K pull-up resistor on the WP# pin of U3 to disable write protection in standard SPI mode. | </details> <details> <summary><b>U3</b> - W25Q64BVSSIG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/653/W25Q64BV.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4356-0059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPI_CS0 | ✅ | CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pull-up resistor to +V_SPI through R163. | | 2 | SO/IO1 | SPI_MISO | ✅ | SO/IO1 (Data Output) is correctly connected to SPI_MISO for standard SPI data output. | | 3 | WP#/IO2 | SPI_WP | ✅ | WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pull-up resistor to +V_SPI through R164, disabling write protection in standard SPI mode. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 5 | SI/IO0 | SPI_MOSI | ✅ | SI/IO0 (Data Input) is correctly connected to SPI_MOSI for standard SPI data input. | | 6 | SCK | SPI_CLK | ✅ | CLK (Serial Clock) is correctly connected to SPI_CLK for the SPI clock input. | | 7 | HOLD#/IO3 | SPI_HOLD | ✅ | HOLD#/IO3 is correctly connected to SPI_HOLD with a 10K pull-up resistor to +V_SPI through R165, disabling the hold function in standard SPI mode. | | 8 | VCC | +V_SPI | ✅ | VCC is correctly connected to +V_SPI with proper decoupling capacitors. The power supply is derived from +3VSB through R152 and D8, providing approximately 2.9-3.0V which is within the 2.7-3.6V operating range. | </details> <details> <summary><b>R165</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | R165 correctly provides a 10K pull-up resistor on the HOLD# pin of U3 to disable the hold function in standard SPI mode. | | 2 | 2 | SPI_HOLD | ✅ | R165 correctly provides a 10K pull-up resistor on the HOLD# pin of U3 to disable the hold function in standard SPI mode. | </details> <details> <summary><b>JP1</b> - 258-0005019 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0005019) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connections for the expansion header. | | 2 | 2 | GND | ✅ | Ground connections for the expansion header. | | 3 | 3 | +PS_5VSB | ✅ | 5V standby power supply output for the expansion header. | | 4 | 4 | +3VSB | ✅ | 3.3V standby power supply output for the expansion header. | | 5 | 5 | SIO_SPI_CS1 | ✅ | SPI chip select 1 signal, level-translated from SOC 1.8V to 3.3V via U14. | | 6 | 6 | UART1_TXD | ✅ | UART1 transmit signal, level-translated from SOC 1.8V to 3.3V via U15. | | 7 | 7 | SIO_SPI_MISO | ✅ | SPI MISO signal, level-translated from SOC 1.8V to 3.3V via U14. | | 8 | 8 | UART1_RXD | ✅ | UART1 receive signal, level-translated from SOC 1.8V to 3.3V via U15. | | 9 | 9 | SIO_SPI_MOSI | ✅ | SPI MOSI signal, level-translated from SOC 1.8V to 3.3V via U14. | | 10 | 10 | UART1_CTSB | ✅ | UART1 clear-to-send signal, level-translated from SOC 1.8V to 3.3V via U15. | | 11 | 11 | SIO_SPI_CLK | ✅ | SPI clock signal, level-translated from SOC 1.8V to 3.3V via U14. | | 12 | 12 | UART1_RTSB | ✅ | UART1 request-to-send signal, level-translated from SOC 1.8V to 3.3V via U15. | | 13 | 13 | GPIO_I2C_SCL | ✅ | I2C clock signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator). | | 14 | 14 | I2SCLK_GPIO | ✅ | I2S clock signal, level-translated from SOC 1.8V to 3.3V via U16. | | 15 | 15 | GPIO_I2C_SDA | ✅ | I2C data signal, level-translated from SOC 1.8V to 3.3V via U40 (PCA9306DCUT I2C translator). | | 16 | 16 | I2SFRM_GPIO | ✅ | I2S frame sync signal, level-translated from SOC 1.8V to 3.3V via U16. | | 17 | 17 | UART2_TXD | ✅ | UART2 transmit signal, level-translated from SOC 1.8V to 3.3V via U7. | | 18 | 18 | I2SDO_GPIO | ✅ | I2S data out signal, level-translated from SOC 1.8V to 3.3V via U16. | | 19 | 19 | UART2_RXD | ✅ | UART2 receive signal, level-translated from SOC 1.8V to 3.3V via U7. | | 20 | 20 | I2SDI_GPIO | ✅ | I2S data in signal, level-translated from SOC 1.8V to 3.3V via U16. | | 21 | 21 | GPIO_S5_0 | ✅ | GPIO S5_0 signal, level-translated from SOC 1.8V to 3.3V via U10. | | 22 | 22 | PWM0 | ✅ | PWM0 signal, level-translated from SOC 1.8V to 3.3V via U17. | | 23 | 23 | GPIO_S5_1 | ✅ | GPIO S5_1 signal, level-translated from SOC 1.8V to 3.3V via U10. | | 24 | 24 | PWM1 | ✅ | PWM1 signal, level-translated from SOC 1.8V to 3.3V via U17. | | 25 | 25 | GPIO_S5_2 | ✅ | GPIO S5_2 signal, level-translated from SOC 1.8V to 3.3V via U10. | | 26 | 26 | I2SMCLK_GPIO | ✅ | I2S master clock signal, level-translated from SOC 1.8V to 3.3V via U17. | </details> <details> <summary><b>J1</b> - 258-0004612 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004612) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDP_VCC | ✅ | DDP_VCC provides power to the DediProg programmer interface. It is OR'd with +V_SPI through diode D8 and can be sourced from either +3VSB (via R152) or +V1P8A (via R818, DNI). | | 2 | 2 | GND | ✅ | Ground connection for the DediProg programmer interface. | | 3 | 3 | SPI_CS0 | ✅ | SPI chip select signal for the DediProg programmer interface, connected to U3 SPI flash CS# and level translator U18. | | 4 | 4 | SPI_CLK | ✅ | SPI clock signal for the DediProg programmer interface, connected to U3 SPI flash SCK and level translator U18. | | 5 | 5 | SPI_MISO | ✅ | SPI MISO (Master In Slave Out) signal for the DediProg programmer interface, connected to U3 SPI flash SO/IO1 and level translator U18. | | 6 | 6 | SPI_MOSI | ✅ | SPI MOSI (Master Out Slave In) signal for the DediProg programmer interface, connected to U3 SPI flash SI/IO0 and level translator U18. | | 7 | 7 | | ✅ | No connection on pin 7. | | 8 | 8 | DDP_IO3L | ✅ | DDP_IO3L controls the output enable of level translator U18, allowing the DediProg to take control of the SPI bus by disabling the SOC connection. | </details> <details> <summary><b>Q105</b> - FDN327N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/FDN327N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | GPIO_LED_CONTROL | ✅ | Drain is connected to GPIO_LED_CONTROL node, which connects to +VCC through R746 (470Ω) and to LED D2 anode. This forms a shunt-mode LED control circuit where the MOSFET turns OFF the LED by pulling the node low. | | G | GATE | GPIO_D2_LED_CTRL | ✅ | Gate is connected to GPIO_D2_LED_CTRL signal with a 10K pull-down resistor (R706) to GND. This provides proper gate drive control with default-OFF state when the GPIO is not driven. | | S | SOURCE | GND | ✅ | Source is connected to GND, which is correct for an N-channel MOSFET used as a low-side switch in this shunt-mode LED control circuit. | </details> <details> <summary><b>D2</b> - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GPIO_LED_CONTROL | ✅ | Anode is connected to GPIO_LED_CONTROL node, which connects to +VCC through current-limiting resistor R746 (470Ω). This is the correct polarity for LED operation. | | C | CATHODE | GND | ✅ | Cathode is connected to GND, which is the correct polarity for LED operation. The LED is controlled by Q105 shunting current when active. | </details> <details> <summary><b>D9</b> - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Bidirectional TVS diode correctly connected between FP_PWRBTN signal and GND for ESD protection. The 5V reverse standoff voltage is appropriate for the 5V signal level. | | P | P | FP_PWRBTN | ✅ | Bidirectional TVS diode correctly connected between FP_PWRBTN signal and GND for ESD protection. The 5V reverse standoff voltage is appropriate for the 5V signal level. | </details> <details> <summary><b>J5</b> - 258-0002513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Header pin 1 connected to FP_PWRBTN net, allowing a jumper to be installed for test/debug purposes to simulate button press. | | 2 | 2 | GND | ✅ | Header pin 2 connected to GND net, completing the jumper circuit to simulate button press when jumper is installed. | </details> <details> <summary><b>SW1</b> - 3770-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3770-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Switch signal pin connected to FP_PWRBTN net with pullup resistor R149 (4.7K), debounce capacitor C154 (0.1uF), and TVS diode D9 for ESD protection. Schematic notes indicate datasheet recommends 10K pullup, but 4.7K is used. | | 2 | 2 | GND | ✅ | Switch return pin correctly connected to GND net, providing the signal ground return path when the button is pressed. | | 3 | GND1 | GND_EARTH | ✅ | Chassis ground pins correctly connected to GND_EARTH net for EMI shielding. GND_EARTH is isolated from signal GND (R145 is DNI), which is typical for EMI/EMC considerations. | | 4 | GND2 | GND_EARTH | ✅ | Chassis ground pins correctly connected to GND_EARTH net for EMI shielding. GND_EARTH is isolated from signal GND (R145 is DNI), which is typical for EMI/EMC considerations. | </details> <details> <summary><b>D1</b> - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | +PS_5VSB | ✅ | Anode is correctly connected to +PS_5VSB supply rail to power the LED when adapter power is present. | | C | CATHODE | PWR_LEDR | ✅ | Cathode is correctly connected through current limiting resistor R148 (470Ω) to ground, providing appropriate LED current of approximately 3.8mA. | </details> <details> <summary><b>U35</b> - PWR_CTRL_EMB_PROC ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NCT3012S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 4 | SLP_S5# | SLP_S4_L | ❌ | <details><summary>Pin 4 (SLP_S5#) is connected to net SLP_S4_L. There is an explicit naming mismatch between the pin name (indicating an S5 sleep state signal) and the connected net (indicating an S4 sleep state signal). This connection should be verified as S4 and S5 are distinct ACPI power states.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="18.08,38.61,25.58,46.11" aspect-ratio="1.29" } <ul><li>Pin 4 (SLP_S5#) is connected to net SLP_S4_L <em>(from schematic)</em></li><li>The pin name SLP_S5# explicitly indicates this pin expects an ACPI S5 (Soft Off) sleep state signal <em>(reasoning)</em></li><li>The connected net SLP_S4_L indicates an ACPI S4 (Suspend to Disk/Hibernate) sleep state signal <em>(reasoning)</em></li><li>In ACPI specifications, S4 and S5 are distinct power states: S4 allows the system to save context to disk and wake from various sources, while S5 is a soft-off state with limited wake sources <em>(reasoning)</em></li><li>Both the # suffix (pin name) and _L suffix (net name) indicate active-low signals, so the polarity is consistent <em>(reasoning)</em></li><li>Other pins on U35 show consistent naming between pin names and net names (e.g., PS_OUT# to PS_OUT_L), making this S5/S4 mismatch stand out <em>(from schematic)</em></li><li>While this connection could theoretically be intentional if the system design uses S4 to trigger S5 functionality or treats these states identically, such a design choice would typically be explicitly documented <em>(reasoning)</em></li><li>Without the NCT3012S-X datasheet to verify the intended function and requirements of pin 4, this naming mismatch should be flagged as a potential error requiring verification <em>(reasoning)</em></li><li>The explicit nature of the mismatch suggests either a connection error or a net naming inconsistency that should be corrected <em>(reasoning)</em></li></ul></details> | | 1 | DeepS5_Sel | S5_SEL | ✅ | DeepS5_Sel is a configuration input with a 2.2K pull-up resistor to +PS_5VSB, likely used to select Deep S5 mode operation. | | 2 | VSB | +PS_5VSB | ✅ | VSB is the power supply input for the controller, correctly connected to the +PS_5VSB rail with adequate decoupling capacitors nearby. | | 3 | PS_IN# | PB_RES | ✅ | PS_IN# is the active-low power button input, correctly connected through a 33 ohm series resistor to the front panel power button for current limiting and debouncing. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA is the I2C/SMBus data line, correctly connected to DDR_SMB_DATA for communication with DDR memory modules. | | 6 | SCLK | DDR_SMB_CLK | ✅ | SCLK is the I2C/SMBus clock line, correctly connected to DDR_SMB_CLK for communication with DDR memory modules. | | 7 | PS_OUT# | PS_OUT_L | ✅ | PS_OUT# is an active-low power state output signal connected to PS_OUT_L net, with a DNI resistor (R289) that would have pulled it up to +PS_3VSB if populated. | | 8 | SYS5VSB_OFF | 5VSB_CTRL | ✅ | SYS5VSB_OFF controls the 5VSB power rail enable/disable and EuP mode. It has a 1K pull-up to +PS_5VSB and drives the 5VSB gate control circuit through R323. | | 9 | GND | GND | ✅ | GND is the ground pin, correctly connected to the system ground plane. | </details> <details> <summary><b>L3</b> - IND_2.2uH_20%_10A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/125-0004501) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | Inductor pin 1 correctly connected to switch node PS3VSB_PHASE for buck converter operation. | | 2 | 2 | +PS_3VSB | ✅ | Inductor pin 2 correctly connected to output rail +PS_3VSB for buck converter operation. | </details> <details> <summary><b>U13</b> - REG_LDO_BUCK_24V ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NB670) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN | PS5VSB_VIN | ✅ | VIN pin correctly connected to PS5VSB_VIN with appropriate input capacitors for decoupling and filtering. | | 2 | PGND | GND | ✅ | PGND pin correctly connected to ground plane. | | 3 | N/C | | ✅ | N/C pin correctly left unconnected as specified in datasheet. | | 4 | PG | +PS_3VSB_PG | ✅ | PG pin correctly configured as open-drain output with pull-up resistor and connected to power sequencing circuit. | | 5 | CLK | $22N1411 | ✅ | CLK pin correctly connected to external charge pump circuit for generating gate drive voltage. | | 6 | LDO | PS3_LDO | ✅ | LDO pin correctly connected to 10uF output capacitor for internal 3.3V LDO regulation. | | 7 | VOUT | +PS_3VSB | ✅ | VOUT pin correctly connected to output rail with multiple output capacitors for voltage sensing and regulation. | | 8 | SW1 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology. | | 9 | SW2 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology. | | 15 | SW3 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology. | | 16 | SW4 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switch node PS3VSB_PHASE, driving inductor L3 in standard buck converter topology. | | 10 | BST | PS3_BST | ✅ | BST pin correctly connected to bootstrap circuit with capacitor between SW and BST through damping resistor. | | 11 | VCC | PS3_VCC | ✅ | VCC pin correctly connected to internal 5V LDO output with 1uF decoupling capacitor. | | 12 | ENLDO | | ✅ | ENLDO pin correctly left floating as it is internally pulled high for normal operation. | | 13 | EN | PS3_EN | ✅ | EN pin correctly configured with pull-up resistor to VIN for buck regulator enable control. | | 14 | AGND | GND | ✅ | AGND pin correctly connected to ground plane for analog ground reference. | </details> <details> <summary><b>Q106</b> - BSS84 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/bss84-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BSS84) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | D | DC_GATE_ENB | ✅ | Drain pin correctly connected to DC_GATE_ENB to control U36 gate voltage. When Q106 turns on, it pulls DC_GATE_ENB high to turn off U36. | | G | G | $22N2300 | ✅ | Gate pin correctly connected to $22N2300, which is driven by voltage divider R855 and clamped by zener diode D13 to detect overvoltage condition. | | S | S | $22N1502 | ✅ | Source pin correctly connected to $22N1502, which is the common reference point for the protection circuit and connects to DC_IN_1 through ferrite beads. | </details> <details> <summary><b>D13</b> - 4620-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4620-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode pin correctly connected to GND for zener diode voltage reference configuration. | | C | CATHODE | $22N2300 | ✅ | Cathode pin correctly connected to $22N2300 to clamp the gate drive voltage for Q106 at 4.3V, setting the trip point for the overvoltage protection circuit. | </details> <details> <summary><b>U36</b> - MOSFET_30V_15A_8-SOIC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.umw-ic.com/static/pdf/b379d167af492bcd72ba51c793d83236.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/IRF9321) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | $22N1502 | ✅ | Source pins correctly connected to $22N1502 net, which connects through ferrite beads to DC_IN_1. Multiple source pins are paralleled for higher current capability. | | 2 | S2 | $22N1502 | ✅ | Source pins correctly connected to $22N1502 net, which connects through ferrite beads to DC_IN_1. Multiple source pins are paralleled for higher current capability. | | 3 | S3 | $22N1502 | ✅ | Source pins correctly connected to $22N1502 net, which connects through ferrite beads to DC_IN_1. Multiple source pins are paralleled for higher current capability. | | 4 | G | DC_GATE_ENB | ✅ | Gate pin correctly connected to DC_GATE_ENB control signal, which is driven by protection circuit Q106 and pulled down by R309. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB power rail. Multiple drain pins are paralleled for higher current capability. | </details> <details> <summary><b>Q103</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. These three pins are paralleled to handle the high current (up to 15.3A) and reduce resistance. | | 2 | S2 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. These three pins are paralleled to handle the high current (up to 15.3A) and reduce resistance. | | 3 | S3 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. These three pins are paralleled to handle the high current (up to 15.3A) and reduce resistance. | | 4 | G | 5VSB_LSENB | ✅ | Gate pin correctly connected to 5VSB_LSENB control signal with proper gate drive circuitry for high-side N-Channel switching. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input power rail. These four pins are paralleled to handle high current and minimize resistance. | </details> <details> <summary><b>Q104</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. These pins carry the switched output current to the system 3.3V standby supply. | | 2 | S2 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. These pins carry the switched output current to the system 3.3V standby supply. | | 3 | S3 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. These pins carry the switched output current to the system 3.3V standby supply. | | 4 | G | +3VSB_EN | ✅ | Gate pin correctly connected to +3VSB_EN control signal with appropriate drive circuitry. The gate is driven to +10V when enabled, providing sufficient VGS for full enhancement. | | 5 | D1 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output. | | 6 | D2 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output. | | 7 | D3 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output. | | 8 | D4 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail from buck regulator U13. These pins receive power from the 3.3V buck converter output. | </details> <details> <summary><b>Q6</b> - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB | ✅ | Drain is connected to +3VSB (3.3V power rail), serving as the input power source for this high-side switch. This connection is correct. | | G | GATE | SYS_EN | ✅ | Gate is connected to SYS_EN, which is driven to +10V when the MOSFET should be on and to GND when off. This provides sufficient gate drive voltage for full enhancement. | | S | SOURCE | +VCC3 | ✅ | Source is connected to +VCC3, the output rail of this high-side switch. This configuration is correct for an N-channel MOSFET with elevated gate drive. | </details> <details> <summary><b>Q13</b> - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +5VSB | ✅ | Drain is connected to +5VSB (5V power rail), serving as the input power source for this high-side switch. This connection is correct. | | G | GATE | SYS_EN | ✅ | Gate is connected to SYS_EN, which is driven to +10V when the MOSFET should be on and to GND when off. This provides sufficient gate drive voltage for full enhancement. | | S | SOURCE | +VCC | ✅ | Source is connected to +VCC, the output rail of this high-side switch. This configuration is correct for an N-channel MOSFET with elevated gate drive. | </details> <details> <summary><b>Q4</b> - XSTR_NPN_40V_200mA_SOT23 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/MMBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B | BASE | S5_ENBL | ❌ | <details><summary>Package pinout mismatch: The schematic uses package SOT23_EBC, but the MMBT3904 datasheet specifies a B-E-C physical pinout. This mismatch will cause the base and emitter pins to be swapped on the physical PCB, preventing correct transistor operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="13.08,80.36,20.58,87.86" aspect-ratio="1.29" } <ul><li>Pin B (BASE) is connected to net S5_ENBL in the schematic <em>(from schematic)</em></li><li>Pin E (EMITTER) is connected to net GND in the schematic <em>(from schematic)</em></li><li>The component specifies package SOT23_EBC in the PKG_TYPE attribute <em>(from schematic)</em></li><li>By convention observed in other components (e.g., SOT23_GSD for 2N7002K MOSFETs where G-S-D corresponds to physical pins 1-2-3), the package name SOT23_EBC indicates physical pin mapping: Pin 1=E, Pin 2=B, Pin 3=C <em>(reasoning)</em></li><li>The MMBT3904 datasheet shows the actual SOT-23 pinout as: Pin 1=Base, Pin 2=Emitter, Pin 3=Collector <em>(from datasheet <a href="https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1#page=3">MMBT3904</a>, page 3)</em></li><li>With package SOT23_EBC, the footprint will map logical pin E to physical pin 1 and logical pin B to physical pin 2 <em>(reasoning)</em></li><li>When assembled on the PCB, physical pin 1 (Base per datasheet) will connect to the GND net (assigned to logical E), and physical pin 2 (Emitter per datasheet) will connect to S5_ENBL net (assigned to logical B) <em>(reasoning)</em></li><li>This pin swap will reverse-bias the base-emitter junction and prevent the transistor from functioning as intended <em>(reasoning)</em></li><li>The package should be changed to SOT23_BEC to match the MMBT3904 datasheet pinout, or a different transistor with E-B-C pinout should be selected <em>(reasoning)</em></li></ul></details> | | E | EMITTER | GND | ❌ | <details><summary>Package pinout mismatch: The schematic uses package SOT23_EBC, but the MMBT3904 datasheet specifies a B-E-C physical pinout. This mismatch will cause the base and emitter pins to be swapped on the physical PCB, preventing correct transistor operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="13.99,80.94,21.49,88.44" aspect-ratio="1.29" } <ul><li>Pin B (BASE) is connected to net S5_ENBL in the schematic <em>(from schematic)</em></li><li>Pin E (EMITTER) is connected to net GND in the schematic <em>(from schematic)</em></li><li>The component specifies package SOT23_EBC in the PKG_TYPE attribute <em>(from schematic)</em></li><li>By convention observed in other components (e.g., SOT23_GSD for 2N7002K MOSFETs where G-S-D corresponds to physical pins 1-2-3), the package name SOT23_EBC indicates physical pin mapping: Pin 1=E, Pin 2=B, Pin 3=C <em>(reasoning)</em></li><li>The MMBT3904 datasheet shows the actual SOT-23 pinout as: Pin 1=Base, Pin 2=Emitter, Pin 3=Collector <em>(from datasheet <a href="https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1#page=3">MMBT3904</a>, page 3)</em></li><li>With package SOT23_EBC, the footprint will map logical pin E to physical pin 1 and logical pin B to physical pin 2 <em>(reasoning)</em></li><li>When assembled on the PCB, physical pin 1 (Base per datasheet) will connect to the GND net (assigned to logical E), and physical pin 2 (Emitter per datasheet) will connect to S5_ENBL net (assigned to logical B) <em>(reasoning)</em></li><li>This pin swap will reverse-bias the base-emitter junction and prevent the transistor from functioning as intended <em>(reasoning)</em></li><li>The package should be changed to SOT23_BEC to match the MMBT3904 datasheet pinout, or a different transistor with E-B-C pinout should be selected <em>(reasoning)</em></li></ul></details> | | C | COLLECTOR | +3VSB_EN_L | ✅ | Collector is correctly connected to +3VSB_EN_L with a 1K pull-up resistor to +PS_5VSB, driving the gate of Q11. | </details> <details> <summary><b>Q11</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB_EN | ✅ | Drain is correctly connected to +3VSB_EN, which controls the gate of Q104 through a 100K pull-up resistor to +10V. | | G | GATE | +3VSB_EN_L | ✅ | Gate is correctly connected to +3VSB_EN_L, which is driven by Q4 collector through a 1K pull-up resistor. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND for common-source configuration. | </details> <details> <summary><b>Q7</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN_GATE | ✅ | Drain connected to SYS_EN_GATE net, which is the output node of this inverter stage. When Q7 is on, it pulls this node low; when off, R142 pulls it high to +10V. | | G | GATE | SLP_S3_L | ✅ | Gate connected to SLP_S3_L signal, which controls the MOSFET switching. When SLP_S3_L is high, Q7 turns on; when low, Q7 is off. | | S | SOURCE | GND | ✅ | Source connected to GND, which is the correct configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary><b>Q12</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN | ✅ | Drain connected to SYS_EN net, which controls the gates of Q13 and Q6 to enable system power rails. When Q12 is on, it pulls SYS_EN low; when off, R340 pulls it high to +10V. | | G | GATE | SYS_EN_GATE | ✅ | Gate connected to SYS_EN_GATE net, which is driven by Q7's drain. When SYS_EN_GATE is high (~10V), Q12 turns on; when low, Q12 is off. | | S | SOURCE | GND | ✅ | Source connected to GND, which is the correct configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary><b>Q14</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | 5VSB_LSENB | ✅ | Drain is connected to 5VSB_LSENB net, which controls the gate of Q103 P-channel power MOSFET and is pulled up to +10V through R324 (100K). This is a standard N-channel MOSFET low-side switch configuration for controlling the load switch. | | G | GATE | 5VSB_GATE | ✅ | Gate is connected to 5VSB_GATE, which is derived from 5VSB_CTRL through R323 (10K) with C340 (1uF) providing filtering. The gate voltage of approximately 5V when on is sufficient to fully enhance the MOSFET and is within the ±20V VGS rating. | | S | SOURCE | GND | ✅ | Source is connected to GND, which is the standard configuration for an N-channel MOSFET low-side switch. | </details> <details> <summary><b>Q10</b> - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | S5_ENBL | ✅ | Drain is connected to S5_ENBL net, which is pulled up to +V1P8A through R133 (10K) and drives the base of Q4 NPN transistor. This is a standard N-channel MOSFET low-side switch configuration for controlling the S5_ENBL signal. | | G | GATE | 5VSB_CTRL | ✅ | Gate is connected to 5VSB_CTRL from U35 power controller, which is pulled up to +PS_5VSB through R288 (1K). The gate voltage of approximately 5V when on is sufficient to fully enhance the MOSFET and is within the ±20V VGS rating. | | S | SOURCE | GND | ✅ | Source is connected to GND, which is the standard configuration for an N-channel MOSFET low-side switch. | </details> <details> <summary><b>Q2</b> - DIODE_ARRAY_75V_0.3A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | +PS_5VSB | ✅ | Anode A1 connected to +PS_5VSB power rail for edge detection. This diode conducts when +PS_5VSB rises, coupling the positive edge through the common cathode and C72 to U13 CLK pin. | | 2 | A2 | $22N1417 | ✅ | Anode A2 connected to intermediate node $22N1417, which connects to Q9 pin 1 and to GND through C71. This provides biasing and is normally reverse biased during operation. | | 3 | C | $22N1419 | ✅ | Common cathode connected to $22N1419, which couples to U13 CLK pin through C72. This is the output node of the edge detection circuit for the +PS_5VSB rail. | </details> <details> <summary><b>Q9</b> - DIODE_ARRAY_75V_0.3A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | $22N1417 | ✅ | Anode A1 connected to intermediate node $22N1417, which connects to Q2 pin 2 and to GND through C71. This provides biasing and is normally reverse biased during operation. | | 2 | A2 | +10V | ✅ | Anode A2 connected to +10V power rail for edge detection. This diode conducts when +10V rises, coupling the positive edge through the common cathode and C283 to U13 CLK pin. | | 3 | C | $22N1467 | ✅ | Common cathode connected to $22N1467, which couples to U13 CLK pin through C283. This is the output node of the edge detection circuit for the +10V rail. | </details> <details> <summary><b>D6</b> - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB_PG | ✅ | Pin 1 (Anode 1) is connected to +PS_3VSB_PG, the power good signal from the 3.3VSB regulator. This allows the power good signal to pull the reset signal high through the diode when power is stable. | | 2 | 2 | +3VSB_EN | ✅ | Pin 2 (Anode 2) is connected to +3VSB_EN, the enable signal for the 3VSB power stage. This allows the enable signal to pull the reset signal high through the diode when enabled. | | 3 | 3 | PMC_RSMRST | ✅ | Pin 3 (Common Cathode) is connected to PMC_RSMRST, the resume reset signal. This pin outputs the OR'd result of the two input signals. | </details> <details> <summary><b>J9</b> - JACK_PWR_2.1MM_RAPC712 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/414/RAPC712_cd.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/RAPC712) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DC_IN_1 | ✅ | Center pin correctly connected to DC_IN_1 net, serving as the positive 5V DC power input with appropriate filtering and protection circuitry downstream. | | 2 | 2 | GND | ✅ | Sleeve contact correctly connected to GND net, providing the ground return path for the DC power input. | | 3 | 3 | GND | ✅ | Switched contact connected to GND, which is electrically safe but does not utilize the plug detection feature that this pin provides. | </details> <details> <summary><b>FB1</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB power rail. This is the input side of the ferrite bead, filtering the 5V standby supply before it feeds the buck converter U13. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, which is the input to buck converter U13 and has multiple input capacitors. This is the output side of the ferrite bead. | </details> <details> <summary><b>L12</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Pin 1 connects to $22N1502, which is the source pins of U36 (P-channel MOSFET). This ferrite bead filters the current path from DC input to the 5VSB rail. | | 2 | 2 | DC_IN_1 | ✅ | Pin 2 connects to DC_IN_1, which is the 5V DC input from connector J9. L12 is paralleled with L13 to provide adequate current handling for the input path. | </details> <details> <summary><b>FB11</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB power rail. FB11 is connected in parallel with FB1 to increase current handling capability. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, parallel with FB1 pin 2. This parallel configuration provides adequate current capability for the buck converter input. | </details> <details> <summary><b>L13</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Pin 1 connects to $22N1502, parallel with L12 pin 1. This parallel configuration increases current handling for the protection circuit. | | 2 | 2 | DC_IN_1 | ✅ | Pin 2 connects to DC_IN_1, parallel with L12 pin 2. The parallel configuration provides adequate current capability for the DC input path. | </details> <details> <summary><b>U25</b> - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin is connected to VR_HOT_L net, serving as a thermal alert output signal. | | 2 | SDIO | $23N2429 | ✅ | SDIO and SCLK pins are connected to SVID interface signals through series termination resistors (16.9Ω and 20.0Ω respectively). | | 4 | SCLK | $23N2430 | ✅ | SDIO and SCLK pins are connected to SVID interface signals through series termination resistors (16.9Ω and 20.0Ω respectively). | | 3 | ALERT | $23N2431 | ✅ | ALERT pin is connected to SVID_ALERT-R through a 0Ω jumper, providing the SVID alert signal path. | | 5 | GND | AGND-VCORE | ✅ | GND, GND1, and GND_PAD pins are all connected to AGND-VCORE, which connects to main GND through a 0Ω jumper, providing proper analog ground separation. | | 32 | GND1 | AGND-VCORE | ✅ | GND, GND1, and GND_PAD pins are all connected to AGND-VCORE, which connects to main GND through a 0Ω jumper, providing proper analog ground separation. | | 49 | GND_PAD | AGND-VCORE | ✅ | GND, GND1, and GND_PAD pins are all connected to AGND-VCORE, which connects to main GND through a 0Ω jumper, providing proper analog ground separation. | | 6 | VR_RDY | $23N3753 | ✅ | VR_RDY pin connects through a 0Ω jumper to VCORE_PG, providing power good indication. | | 7 | VIN1 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 11 | VIN2 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 12 | VIN3 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 13 | VIN4 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 14 | VIN5 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 15 | VIN6 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 16 | VIN7 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 17 | VIN8 | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 50 | VIN_PAD | +5VSB_SW | ✅ | All VIN pins (VIN1-8) and VIN_PAD are connected to +5VSB_SW, properly paralleling the input power pins. | | 8 | BST | $23N3711 | ✅ | BST pin connects through R154 (2.20Ω) and C50 (0.22µF) to SW1, forming the bootstrap circuit for the high-side gate driver. | | 9 | GH | | ✅ | GH pin shows no net connection in the schematic. Without datasheet confirmation, it is unclear if this is correct or if external MOSFETs are required. | | 10 | SW1 | $23N3731 | ✅ | SW1 pin connects to the bootstrap circuit but not to the main VCORE-SW net. This may be intentional for bootstrap reference, but typically all switch nodes should be connected together in a multiphase converter. | | 18 | SW2 | VCORE-SW | ✅ | SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs. | | 25 | SW3 | VCORE-SW | ✅ | SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs. | | 26 | SW4 | VCORE-SW | ✅ | SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs. | | 27 | SW5 | VCORE-SW | ✅ | SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs. | | 28 | SW6 | VCORE-SW | ✅ | SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs. | | 29 | SW7 | VCORE-SW | ✅ | SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs. | | 51 | SW_PAD | VCORE-SW | ✅ | SW2-7 and SW_PAD pins are all connected to VCORE-SW net, properly paralleling the switch node outputs. | | 19 | PGND1 | GND | ✅ | PGND1-6 pins are all connected to GND, providing proper power ground connections. | | 20 | PGND2 | GND | ✅ | PGND1-6 pins are all connected to GND, providing proper power ground connections. | | 21 | PGND3 | GND | ✅ | PGND1-6 pins are all connected to GND, providing proper power ground connections. | | 22 | PGND4 | GND | ✅ | PGND1-6 pins are all connected to GND, providing proper power ground connections. | | 23 | PGND5 | GND | ✅ | PGND1-6 pins are all connected to GND, providing proper power ground connections. | | 24 | PGND6 | GND | ✅ | PGND1-6 pins are all connected to GND, providing proper power ground connections. | | 30 | GL | | ✅ | GL pin shows no net connection in the schematic. Without datasheet confirmation, it is unclear if this is correct or if external MOSFETs are required. | | 31 | VBOOT | $23N3477 | ✅ | VBOOT pin connects through R70 (88.7kΩ) to AGND-VCORE, setting the boot voltage. A text note indicates VBOOT should be 1.1V. | | 33 | VCCP | $23N3625 | ✅ | VCCP pin connects through R845 (1.00Ω) from +5VSB with C48 (4.7µF) decoupling, providing charge pump supply voltage. | | 34 | TSENSE | $23N3665 | ✅ | TSENSE pin connects through R78 (0Ω) to a thermistor divider network (TH2 100kΩ thermistor and R131 14.0kΩ), providing temperature sensing. | | 35 | IMAX | $23N3681 | ✅ | IMAX pin connects through R105 (44.2kΩ) to AGND-VCORE, setting the maximum current limit. A text note indicates IMAX should be 14A. | | 36 | IOUT | $23N3683 | ✅ | IOUT pin connects through R146 (16.5kΩ) to AGND-VCORE with C47 (470pF) filtering, providing output current reporting. | | 37 | ILIM | VCORE-ILIM | ✅ | ILIM pin connects through R95 (15.0kΩ) to VCORE-CSCOMP, setting the current limit threshold. | | 38 | CSCOMP | VCORE-CSCOMP | ✅ | CSCOMP pin connects to current sense compensation network with capacitors C39 (470pF) and C40 (2200pF) to CSSUM, plus resistors and thermistor for temperature compensation. | | 39 | CSSUM | VCORE-CSSUM | ✅ | CSSUM pin connects to current sense sum network with DCR sensing through SP3 short to VCORE-SW and resistor divider to ground. | | 40 | CSREF | VCORE-CSREF | ✅ | CSREF pin connects through R108 (10.0Ω) and SP4 short to +VCORE with C45 (1000pF) filtering, providing current sense reference. | | 41 | FREQ | $23N2930 | ✅ | FREQ pin connects through R93 (18.7kΩ) to AGND-VCORE, setting the switching frequency. A text note indicates FSW should be 650kHz. | | 42 | COMP | VCORE-COMP | ✅ | COMP pin connects to voltage loop compensation network with C35 (47pF) and C37 (2200pF) providing frequency compensation. | | 43 | FB | VCORE-FB | ✅ | FB pin connects to feedback network with resistor divider and compensation components for voltage regulation. | | 44 | DIFFOUT | VCORE-DIFFOUT | ✅ | DIFFOUT pin connects through R89 (1.00kΩ) to FB and through R90 (47Ω) to intermediate net, forming part of the differential amplifier output. | | 45 | VSN | VR-VCORE-VSN | ✅ | VSN pin connects through R65 (10.0Ω) to remote sense network with R91 (100Ω) to GND and R64 (0Ω) to VSS_SENSE, providing negative remote voltage sensing. | | 46 | VSP | VR-VCORE-VSP | ✅ | VSP pin connects through R92 (100Ω) to +VCORE and through R63 (0Ω) to VCC_SENSE, providing positive remote voltage sensing. | | 47 | VCC | $23N3860 | ✅ | VCC pin connects through R166 (2.20Ω) from +5VSB with C24 (1.0µF) decoupling to AGND-VCORE, providing IC supply voltage. | | 48 | EN | $23N5607 | ✅ | EN pin connects through R849 (0Ω) to +VCC with R851 (10.0kΩ) pulldown and C433 (0.1µF) filtering, enabling the regulator when +VCC is present. | </details> <details> <summary><b>L8</b> - 3120-0183 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3120-0183) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of an input filter inductor. | | 2 | 2 | +5VSB_SW | ✅ | Pin 2 connects to the +5VSB_SW filtered input rail that supplies the U25 controller VIN pins. This is the correct connection for the output side of an input filter inductor. | </details> <details> <summary><b>L18</b> - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Pin 1 connects to the VCORE-SW switching node from the multiphase buck converter controller U25. This is the correct connection for the input side of the output filter inductor. | | 2 | 2 | +VCORE | ✅ | Pin 2 connects to the +VCORE output rail. This is the correct connection for the output side of the filter inductor in a buck converter. | </details> <details> <summary><b>TH2</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to net $23N3662, which receives the TSENSE signal from U25 through R78. This thermistor provides temperature sensing for the voltage regulator. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the temperature sensing voltage divider. | </details> <details> <summary><b>TH1</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP net, which is the current sense compensation pin of U25. This thermistor provides temperature compensation for the current sensing loop. | | 2 | 2 | $23N3115 | ✅ | Connected to net $23N3115, which is the junction between R96 and R106 in the current sensing compensation network. | </details> <details> <summary><b>R78</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | Connected to net $23N3665, which connects to U25 pin 34 (TSENSE). This 0-ohm jumper allows the TSENSE signal to reach the thermistor network. | | 2 | 2 | $23N3662 | ✅ | Connected to net $23N3662, which is the junction of TH2 and R131. This completes the connection from TSENSE to the temperature sensing network. | </details> <details> <summary><b>R131</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to net $23N3662, forming a parallel combination with TH2 for temperature sensing. The 14K value sets the temperature sensing characteristics. | | 2 | 2 | GND | ✅ | Connected to GND, completing the temperature sensing voltage divider to ground. | </details> <details> <summary><b>D4</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Cathode 1 of dual Schottky diode in common anode configuration, connected to VCORE_PG net. This pin receives the VCORE power good signal and forms one input of a wired-AND power good monitoring circuit. | | 2 | 2 | VGFX_PG | ✅ | Cathode 2 of dual Schottky diode in common anode configuration, connected to VGFX_PG net. This pin receives the graphics voltage regulator power good signal and forms the second input of the wired-AND power good monitoring circuit. | | 3 | 3 | VCORE_GFX_PG | ✅ | Common anode of dual Schottky diode, connected to VCORE_GFX_PG net. This pin outputs the combined power good signal that is high only when both VCORE_PG and VGFX_PG are high, implementing a wired-AND function. | </details> <details> <summary><b>R167</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 power rail. Provides the pull-up voltage source for the VCORE_PG signal through the 1.91K resistor. | | 2 | 2 | VCORE_PG | ✅ | Connected to VCORE_PG net. Provides pull-up for the VCORE power good signal from U25 VR_RDY pin, which is typically an open-drain output. | </details> <details> <summary><b>R79</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Connected to VCORE_PG net. This 0 ohm resistor provides a direct connection between the VR_RDY output and the power good monitoring circuit. | | 2 | 2 | $23N3753 | ✅ | Connected to internal net $23N3753 which connects to U25 pin 6 (VR_RDY). This provides the VCORE power good signal from the voltage regulator controller. | </details> <details> <summary><b>R94</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | Connected to VCORE_GFX_PG net and D4 pin 3 (common anode). Provides the load side of the pull-up resistor for the combined power good signal. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 power rail. Provides the pull-up voltage source for the combined power good signal through the 1K resistor. | </details> <details> <summary><b>R87</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_CLK-R | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system. | </details> <details> <summary><b>R85</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_DATA-R | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system. | </details> <details> <summary><b>R81</b> - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line. | | 2 | 2 | $23N2430 | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line. | </details> <details> <summary><b>R80</b> - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line. | | 2 | 2 | $23N2429 | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line. | </details> <details> <summary><b>R86</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_ALERT-R | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system. | </details> <details> <summary><b>R62</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin. | | 2 | 2 | $23N2431 | ✅ | Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin. | </details> <details> <summary><b>C87</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VCORE | ✅ | Positive terminal correctly connected to +VCORE output rail of the DC/DC regulator. | | 2 | N | GND | ✅ | Negative terminal correctly connected to ground reference. | </details> <details> <summary><b>R88</b> - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2824 | ✅ | Connected to intermediate node $23N2824 in the voltage loop compensation network, forming part of a Type III compensator with C37. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB feedback pin, completing the compensation network path from COMP through C37 and R88 to FB. | </details> <details> <summary><b>R90</b> - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2818 | ✅ | Connected to intermediate node $23N2818 in the differential amplifier feedback network, forming a high-frequency filter with C36. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT differential output pin, completing the high-frequency filter path in parallel with R89. | </details> <details> <summary><b>C35</b> - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP compensation pin, providing direct high-frequency feedback path to FB. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB feedback pin, completing the direct high-frequency feedback path from COMP to FB. | </details> <details> <summary><b>C36</b> - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB feedback pin, forming the first element of the high-frequency filter network for the differential amplifier. | | 2 | 2 | $23N2818 | ✅ | Connected to intermediate node $23N2818, forming the series connection point with R90 in the differential amplifier filter network. | </details> <details> <summary><b>C37</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP compensation pin, forming the first element of the series RC compensation network. | | 2 | 2 | $23N2824 | ✅ | Connected to intermediate node $23N2824, forming the series connection point with R88 in the compensation network. | </details> <details> <summary><b>R89</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB feedback pin, providing the main resistive feedback path to the differential amplifier output. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT differential output pin, completing the feedback path for the differential amplifier. | </details> <details> <summary><b>C40</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | 2200pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, in parallel with C39 for current sense loop compensation. | | 2 | 2 | VCORE-CSSUM | ✅ | 2200pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, in parallel with C39 for current sense loop compensation. | </details> <details> <summary><b>R108</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSREF | ✅ | 10.0 ohm resistor connecting VCORE-CSREF to the output voltage +VCORE through SP4, providing the reference for DCR current sensing. | | 2 | 2 | $23N3208 | ✅ | 10.0 ohm resistor connecting VCORE-CSREF to the output voltage +VCORE through SP4, providing the reference for DCR current sensing. | </details> <details> <summary><b>R95</b> - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-ILIM | ✅ | 15.0K resistor connecting VCORE-ILIM to VCORE-CSCOMP, setting the current limit threshold for the voltage regulator. | | 2 | 2 | VCORE-CSCOMP | ✅ | 15.0K resistor connecting VCORE-ILIM to VCORE-CSCOMP, setting the current limit threshold for the voltage regulator. | </details> <details> <summary><b>R146</b> - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3683 | ✅ | 16.5K pulldown resistor on the IOUT pin, configuring the output current monitoring level. | | 2 | 2 | AGND-VCORE | ✅ | 16.5K pulldown resistor on the IOUT pin, configuring the output current monitoring level. | </details> <details> <summary><b>C39</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | 470pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, forming part of the current sense loop compensation network. | | 2 | 2 | VCORE-CSSUM | ✅ | 470pF capacitor connected between VCORE-CSCOMP and VCORE-CSSUM, forming part of the current sense loop compensation network. | </details> <details> <summary><b>C45</b> - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSREF | ✅ | 1000pF bypass capacitor on the CSREF pin, providing filtering for the current sense reference voltage. | | 2 | 2 | GND | ✅ | 1000pF bypass capacitor on the CSREF pin, providing filtering for the current sense reference voltage. | </details> <details> <summary><b>R107</b> - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSSUM | ✅ | 100K resistor connecting VCORE-CSSUM to the switching node VCORE-SW through SP3, implementing DCR current sensing. | | 2 | 2 | $23N3209 | ✅ | 100K resistor connecting VCORE-CSSUM to the switching node VCORE-SW through SP3, implementing DCR current sensing. | </details> <details> <summary><b>R106</b> - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3115 | ✅ | 165K resistor connecting the intermediate current sense node to VCORE-CSSUM, completing the DCR current sensing divider network. | | 2 | 2 | VCORE-CSSUM | ✅ | 165K resistor connecting the intermediate current sense node to VCORE-CSSUM, completing the DCR current sensing divider network. | </details> <details> <summary><b>R96</b> - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | 75.0K resistor in the current sense compensation network, connecting VCORE-CSCOMP to an intermediate node in the DCR current sensing path. | | 2 | 2 | $23N3115 | ✅ | 75.0K resistor in the current sense compensation network, connecting VCORE-CSCOMP to an intermediate node in the DCR current sensing path. | </details> <details> <summary><b>R105</b> - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3681 | ✅ | 44.2K pulldown resistor on the IMAX pin, setting the maximum current limit to 14A as indicated by the schematic note. | | 2 | 2 | AGND-VCORE | ✅ | 44.2K pulldown resistor on the IMAX pin, setting the maximum current limit to 14A as indicated by the schematic note. | </details> <details> <summary><b>R92</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output voltage. This is the positive input to the remote voltage sense circuit. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP which goes to the VSP pin of the voltage regulator U25. | </details> <details> <summary><b>R63</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_SENSE | ✅ | Connected to VCC_SENSE remote sense point. This 0Ω jumper enables remote voltage sensing at the load. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP, linking the remote sense point to the regulator's positive sense input. | </details> <details> <summary><b>R91</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This is the ground reference input to the remote voltage sense circuit. | | 2 | 2 | $23N2860 | ✅ | Connected to internal node $23N2860 which is part of the negative voltage sense path. | </details> <details> <summary><b>R64</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VSS_SENSE | ✅ | Connected to VSS_SENSE remote ground sense point. This 0Ω jumper enables remote ground sensing at the load. | | 2 | 2 | $23N2860 | ✅ | Connected to internal node $23N2860, linking the remote ground sense point to the negative sense path. | </details> <details> <summary><b>R65</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | Connected to internal node $23N2860 in the negative voltage sense path. | | 2 | 2 | VR-VCORE-VSN | ✅ | Connected to VR-VCORE-VSN which goes to the VSN pin of the voltage regulator U25. | </details> <details> <summary><b>C34</b> - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP. This capacitor is marked DNI and would provide differential filtering if installed. | | 2 | 2 | VR-VCORE-VSN | ✅ | Connected to VR-VCORE-VSN. This DNI capacitor would filter the differential sense signal if installed. | </details> <details> <summary><b>C38</b> - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | Connected to internal node $23N2860. This capacitor is marked DNI and would provide filtering on the negative sense line if installed. | | 2 | 2 | VR-VCORE-VSN | ✅ | Connected to VR-VCORE-VSN. This DNI capacitor would filter the negative sense path if installed. | </details> <details> <summary><b>R849</b> - 1121-0001 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ❌ | <details><summary>0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,36.25,40.57,43.75" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net +VCC <em>(from schematic)</em></li><li>Pin 2 is connected to net $23N5607 <em>(from schematic)</em></li><li>Net $23N5607 connects to U25 pin 48 (EN) <em>(from schematic)</em></li><li>R849 is a 0Ω jumper (part number 1121-0001) <em>(from schematic)</em></li><li>This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled <em>(reasoning)</em></li><li>R851 (10KΩ) is also populated on net $23N5607, connecting to GND <em>(from schematic)</em></li><li>With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND <em>(reasoning)</em></li><li>This creates unnecessary power dissipation in R851 <em>(reasoning)</em></li><li>Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω <em>(reasoning)</em></li><li>The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state <em>(reasoning)</em></li><li>Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path <em>(reasoning)</em></li></ul></details> | | 2 | 2 | $23N5607 | ❌ | <details><summary>0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,38.02,40.57,45.52" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net +VCC <em>(from schematic)</em></li><li>Pin 2 is connected to net $23N5607 <em>(from schematic)</em></li><li>Net $23N5607 connects to U25 pin 48 (EN) <em>(from schematic)</em></li><li>R849 is a 0Ω jumper (part number 1121-0001) <em>(from schematic)</em></li><li>This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled <em>(reasoning)</em></li><li>R851 (10KΩ) is also populated on net $23N5607, connecting to GND <em>(from schematic)</em></li><li>With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND <em>(reasoning)</em></li><li>This creates unnecessary power dissipation in R851 <em>(reasoning)</em></li><li>Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω <em>(reasoning)</em></li><li>The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state <em>(reasoning)</em></li><li>Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R851</b> - 1120-0011 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ❌ | <details><summary>10KΩ pull-down resistor on EN pin of U25. With R849 (0Ω jumper to +VCC) also populated, creates wasteful current path drawing VCC/10KΩ continuously.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,39.78,40.57,47.28" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net $23N5607 <em>(from schematic)</em></li><li>Pin 2 is connected to net GND <em>(from schematic)</em></li><li>Net $23N5607 connects to U25 pin 48 (EN) <em>(from schematic)</em></li><li>R851 is a 10KΩ resistor (part number 1120-0011) <em>(from schematic)</em></li><li>R849 (0Ω) connects +VCC to the same net $23N5607 <em>(from schematic)</em></li><li>This creates a direct current path from +VCC through R849 (0Ω) to the EN pin, then through R851 (10KΩ) to GND <em>(reasoning)</em></li><li>Continuous current draw of VCC/10KΩ results in unnecessary power dissipation <em>(reasoning)</em></li><li>The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at pulling the pin low <em>(reasoning)</em></li><li>R851 should be DNI when R849 is populated to avoid the wasteful current path <em>(reasoning)</em></li><li>If the intent is to have the regulator always enabled, only R849 should be populated; if the intent is to disable or allow external control, only R851 should be populated <em>(reasoning)</em></li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>10KΩ pull-down resistor on EN pin of U25. With R849 (0Ω jumper to +VCC) also populated, creates wasteful current path drawing VCC/10KΩ continuously.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,41.55,40.57,49.05" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net $23N5607 <em>(from schematic)</em></li><li>Pin 2 is connected to net GND <em>(from schematic)</em></li><li>Net $23N5607 connects to U25 pin 48 (EN) <em>(from schematic)</em></li><li>R851 is a 10KΩ resistor (part number 1120-0011) <em>(from schematic)</em></li><li>R849 (0Ω) connects +VCC to the same net $23N5607 <em>(from schematic)</em></li><li>This creates a direct current path from +VCC through R849 (0Ω) to the EN pin, then through R851 (10KΩ) to GND <em>(reasoning)</em></li><li>Continuous current draw of VCC/10KΩ results in unnecessary power dissipation <em>(reasoning)</em></li><li>The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at pulling the pin low <em>(reasoning)</em></li><li>R851 should be DNI when R849 is populated to avoid the wasteful current path <em>(reasoning)</em></li><li>If the intent is to have the regulator always enabled, only R849 should be populated; if the intent is to disable or allow external control, only R851 should be populated <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R154</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3711 | ✅ | Connected to the BST (bootstrap) pin of U25 (NCP81109GMNTXG controller). This is the input side of the bootstrap resistor. | | 2 | 2 | $23N3733 | ✅ | Connected to the bootstrap capacitor C50. This is the output side of the bootstrap resistor, forming the RC network of the bootstrap circuit. | </details> <details> <summary><b>C50</b> - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3733 | ✅ | Connected to bootstrap resistor R154. This is the high-side terminal of the bootstrap capacitor. | | 2 | 2 | $23N3731 | ✅ | Connected to SW1 pin of U25. This is the low-side terminal of the bootstrap capacitor, referenced to the switch node. | </details> <details> <summary><b>R93</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2930 | ✅ | Pin 1 connects to the FREQ pin (pin 41) of U25 (NCP81109GMNTXG multiphase controller) to set the switching frequency. A nearby text note indicates the target frequency is 650kHz. | | 2 | 2 | AGND-VCORE | ✅ | Pin 2 connects to AGND-VCORE, which is the analog ground reference for the VCORE regulator section. This provides the ground reference for the frequency setting resistor. | </details> <details> <summary><b>U26</b> - NCP81109GMNTXG ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | SW1 | $24N3595 | ❌ | <details><summary>SW1 is isolated from the main switch node and only connected to the bootstrap capacitor return path. This configuration prevents phase 1 from contributing to the output.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="37.39,41.84,44.89,49.34" aspect-ratio="1.29" } <ul><li>Pin 10 (SW1) is connected to net $24N3595 <em>(from schematic)</em></li><li>Bootstrap capacitor C186 (0.22µF) connects between $24N3596 and $24N3595 (SW1) <em>(from schematic)</em></li><li>Bootstrap resistor R228 (2.20Ω) connects between $24N3593 (BST, pin 8) and $24N3596 <em>(from schematic)</em></li><li>Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW <em>(from schematic)</em></li><li>Net VGFX-SW connects through inductor L4 to the output +VGFX <em>(from schematic)</em></li><li>There is no connection between net $24N3595 (SW1) and net VGFX-SW <em>(from schematic)</em></li><li>In a multiphase buck converter, all active switch nodes must be connected together to share current and drive the output <em>(reasoning)</em></li><li>The bootstrap circuit (R228, C186) connected to SW1 suggests phase 1 was intended to be active <em>(reasoning)</em></li><li>For the bootstrap circuit to function, SW1 must be switching, which requires it to be part of an active phase <em>(reasoning)</em></li><li>The isolation of SW1 from VGFX-SW prevents phase 1 from contributing to the output and renders the bootstrap circuit non-functional <em>(reasoning)</em></li><li>If phase 1 is intentionally disabled, the bootstrap components (R228, C186) should be marked DNP <em>(reasoning)</em></li><li>The correct configuration requires SW1 to be connected to VGFX-SW along with the other switch nodes <em>(reasoning)</em></li></ul></details> | | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin is connected to VR_HOT_L net, which is a thermal alert output signal. | | 2 | SDIO | $24N3490 | ✅ | SDIO pin is connected to SVID data line through R193 (16.9Ω) series resistor with pull-up to +V1P0S through R195 (69.8Ω). | | 3 | ALERT | $24N3492 | ✅ | ALERT pin is connected to SVID alert line through R67 (0Ω) jumper with pull-up to +V1P0S through R196 (69.8Ω, DNI). | | 4 | SCLK | $24N3491 | ✅ | SCLK pin is connected to SVID clock line through R194 (20.0Ω) series resistor with pull-up to +V1P0S through R197 (69.8Ω). | | 5 | GND | AGND-VGFX | ✅ | GND pin is connected to AGND-VGFX analog ground net, which connects to main GND through R66 (0Ω) jumper. | | 6 | VR_RDY | $24N3598 | ✅ | VR_RDY pin is connected to power good output VGFX_PG through R184 (0Ω) jumper, with pull-up R230 (1.91kΩ) to +VCC3 and decoupling C60 (0.1µF). | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 8 | BST | $24N3593 | ✅ | BST pin is connected to bootstrap circuit with R228 (2.20Ω) and C186 (0.22µF) to SW1 for high-side gate driver supply. | | 9 | GH | | ✅ | GH pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal. | | 18 | SW2 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 25 | SW3 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 26 | SW4 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 27 | SW5 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 28 | SW6 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 29 | SW7 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 30 | GL | | ✅ | GL pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal. | | 31 | VBOOT | $24N3564 | ✅ | VBOOT pin is connected to bootstrap voltage sense with R170 (100kΩ) pull-down to AGND-VGFX. | | 32 | GND1 | AGND-VGFX | ✅ | GND1 pin is connected to AGND-VGFX analog ground net. | | 33 | VCCP | $24N3578 | ✅ | VCCP pin is connected to internal LDO/charge pump supply with R846 (1Ω) from +5VSB and C185 (4.7µF) decoupling. | | 34 | TSENSE | $24N3584 | ✅ | TSENSE pin is connected to temperature sense network with TH4 (100kΩ@25C thermistor) and R226 (14.0kΩ) forming a divider to GND, with C168 (0.1µF) filtering. | | 35 | IMAX | $24N3588 | ✅ | IMAX pin is connected to R207 (44.2kΩ) to AGND-VGFX, setting the maximum current limit. A text note indicates IMAX = 14A. | | 36 | IOUT | $24N3589 | ✅ | IOUT pin is connected to output current reporting network with R227 (16.5kΩ) and C184 (470pF) to AGND-VGFX. | | 37 | ILIM | VGFX-ILIM | ✅ | ILIM pin is connected to current limit threshold network with R204 (15.0kΩ) to VGFX-CSCOMP. | | 38 | CSCOMP | VGFX-CSCOMP | ✅ | CSCOMP pin is connected to current sense compensation network with R204, R205, TH3, C113, and C166 for current loop stability and thermal compensation. | | 39 | CSSUM | VGFX-CSSUM | ✅ | CSSUM pin is connected to current sense sum network with R224, R223, C113, and C166 for multiphase current sensing. | | 40 | CSREF | VGFX-CSREF | ✅ | CSREF pin is connected to current sense reference with R225 (10.0Ω) to output voltage through SP1, and C167 (1000pF) to GND. | | 41 | FREQ | $24N3542 | ✅ | FREQ pin is connected to R203 (18.7kΩ) to AGND-VGFX, setting the switching frequency. A text note indicates FSW = 650kHz. | | 42 | COMP | VGFX-COMP | ✅ | COMP pin is connected to voltage loop compensation network with C62 (47pF) to FB and C64 (2200pF) to feedback divider. | | 43 | FB | VGFX-FB | ✅ | FB pin is connected to feedback network with R198 (3.01kΩ) divider, R199 (1.00kΩ) to DIFFOUT, and compensation capacitors C62 and C63. | | 44 | DIFFOUT | VGFX-DIFFOUT | ✅ | DIFFOUT pin is connected to differential amplifier output network with R199 (1.00kΩ) to FB and R200 (47Ω) to compensation. | | 45 | VSN | VR-VGFX-VSN | ✅ | VSN pin is connected to negative remote sense input with R169 (10.0Ω) from ground reference point. | | 46 | VSP | VR-VGFX-VSP | ✅ | VSP pin is connected to positive remote sense input with R202 (100Ω) from +VGFX and R68 (0Ω) from VCCGT_SENSE. | | 47 | VCC | $24N3610 | ✅ | VCC pin is connected to supply input with R229 (2.20Ω) from +5VSB and C53 (1.0µF) decoupling to AGND-VGFX. | | 48 | EN | $24N6011 | ✅ | EN pin is connected to enable input with R850 (0Ω) pull-up to +VCC, R852 (10.0kΩ) pull-down to GND, and C434 (0.1µF) decoupling. | | 49 | GND_PAD | AGND-VGFX | ✅ | GND_PAD is connected to AGND-VGFX analog ground net for thermal and electrical grounding. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN_PAD is connected to +5VSB_SW input supply for additional current handling capability. | | 51 | SW_PAD | VGFX-SW | ✅ | SW_PAD is connected to VGFX-SW switch node for additional current handling capability. | </details> <details> <summary><b>L4</b> - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to the switching node VGFX-SW from the voltage regulator U26. This is the correct connection for the input side of a buck converter output inductor. | | 2 | 2 | +VGFX | ✅ | Connected to the output voltage rail +VGFX. This is the correct connection for the output side of a buck converter inductor. Note: The inductor is rated for 17.5A, and the current limit is set to 14A, which provides adequate margin. A text note indicates 'IMAX = 24A' near the inductor, but this may refer to peak current capability rather than continuous current. | </details> <details> <summary><b>SP2</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to the switching node VGFX-SW. This provides the switching voltage reference for current sensing through R224 to the CSSUM pin of U26. | | 2 | 2 | $24N3558 | ✅ | Connected through R224 (100kΩ) to the CSSUM pin (pin 39) of U26. This forms part of the current sensing sum network. | </details> <details> <summary><b>SP1</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Connected to the output voltage rail +VGFX. This provides the reference point for current sensing through R225 to the CSREF pin of U26. | | 2 | 2 | $24N3559 | ✅ | Connected through R225 (10Ω) to the CSREF pin (pin 40) of U26. This forms part of the current sensing reference network. | </details> <details> <summary><b>R207</b> - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3588 | ✅ | Connects U26 IMAX pin to AGND-VGFX to set the maximum current limit. A text note specifies 'IMAX = 14A' near this component, but without the NCP81109GMNTXG datasheet, the 44.2K value cannot be verified to achieve this specification. | | 2 | 2 | AGND-VGFX | ✅ | Connects U26 IMAX pin to AGND-VGFX to set the maximum current limit. A text note specifies 'IMAX = 14A' near this component, but without the NCP81109GMNTXG datasheet, the 44.2K value cannot be verified to achieve this specification. | </details> <details> <summary><b>TH3</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP (U26 pin 38) as part of the current loop compensation network. This pin is part of a parallel combination with R205 to provide temperature-compensated current sensing. | | 2 | 2 | $24N3557 | ✅ | Connected to intermediate node $24N3557, which connects through R223 to VGFX-CSSUM. This completes the temperature-compensated current loop compensation network. | </details> <details> <summary><b>C168</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | C168 pin 1 connects to the TSENSE input net $24N3584, providing filtering for the temperature sense signal. | | 2 | 2 | AGND-VGFX | ✅ | C168 pin 2 correctly connects to AGND-VGFX, the analog ground reference for the voltage regulator. | </details> <details> <summary><b>R178</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | R178 pin 1 connects to the TSENSE input net $24N3584, providing a series connection between the temperature sensing divider and the TSENSE pin. | | 2 | 2 | $24N3583 | ✅ | R178 pin 2 connects to the temperature sensing divider node $24N3583 where TH4 and R226 are in parallel. | </details> <details> <summary><b>R226</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | R226 pin 1 connects to the temperature sensing node $24N3583, forming a parallel combination with thermistor TH4. | | 2 | 2 | GND | ✅ | R226 pin 2 correctly connects to GND, completing the parallel path with the thermistor. | </details> <details> <summary><b>TH4</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | Thermistor pin 1 connects to the temperature sensing network node $24N3583, which includes R226 in parallel and connects through R178 to U26 TSENSE pin. | | 2 | 2 | GND | ✅ | Thermistor pin 2 correctly connects to GND, completing the temperature sensing network. | </details> <details> <summary><b>R193</b> - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Series resistor between SVID_DATA-R signal and U26 SDIO pin. Provides signal integrity and protection for the SVID data line. | | 2 | 2 | $24N3490 | ✅ | Series resistor between SVID_DATA-R signal and U26 SDIO pin. Provides signal integrity and protection for the SVID data line. | </details> <details> <summary><b>R194</b> - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Series resistor between SVID_CLK-R signal and U26 SCLK pin. Provides signal integrity and protection for the SVID clock line. | | 2 | 2 | $24N3491 | ✅ | Series resistor between SVID_CLK-R signal and U26 SCLK pin. Provides signal integrity and protection for the SVID clock line. | </details> <details> <summary><b>R67</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Zero ohm jumper between SVID_ALERT-R signal and U26 ALERT pin. The ALERT line has no pull-up resistor installed (R196 is DNI), which may be intentional if the signal is not used or pulled up elsewhere. | | 2 | 2 | $24N3492 | ✅ | Zero ohm jumper between SVID_ALERT-R signal and U26 ALERT pin. The ALERT line has no pull-up resistor installed (R196 is DNI), which may be intentional if the signal is not used or pulled up elsewhere. | </details> <details> <summary><b>R195</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor from +V1P0S to SVID_DATA-R signal. Provides the required pull-up for the bidirectional SVID data line. | | 2 | 2 | SVID_DATA-R | ✅ | Pull-up resistor from +V1P0S to SVID_DATA-R signal. Provides the required pull-up for the bidirectional SVID data line. | </details> <details> <summary><b>R196</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor from +V1P0S to SVID_ALERT-R signal, marked DNI. The ALERT line has no pull-up resistor installed, which may be intentional if the signal is not used or pulled up elsewhere. | | 2 | 2 | SVID_ALERT-R | ✅ | Pull-up resistor from +V1P0S to SVID_ALERT-R signal, marked DNI. The ALERT line has no pull-up resistor installed, which may be intentional if the signal is not used or pulled up elsewhere. | </details> <details> <summary><b>R197</b> - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor from +V1P0S to SVID_CLK-R signal. Provides the required pull-up for the SVID clock line. | | 2 | 2 | SVID_CLK-R | ✅ | Pull-up resistor from +V1P0S to SVID_CLK-R signal. Provides the required pull-up for the SVID clock line. | </details> <details> <summary><b>C434</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to net $24N6011 (enable signal). This provides filtering and bypassing for the enable pin. | | 2 | 2 | GND | ✅ | Connected to GND. This completes the bypass capacitor path for the enable signal. | </details> <details> <summary><b>R852</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to net $24N6011 (enable signal). This is one side of the 10K pull-down resistor for the enable pin. | | 2 | 2 | GND | ✅ | Connected to GND. This completes the pull-down resistor path for the enable signal. | </details> <details> <summary><b>R850</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC power rail. This is the input side of the 0Ω jumper used to enable the voltage regulator U26. | | 2 | 2 | $24N6011 | ✅ | Connected to net $24N6011, which connects to the EN (enable) pin of U26, along with pull-down resistor R852 and bypass capacitor C434. | </details> <details> <summary><b>R230</b> - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Pin 1 connects to the +VCC3 power rail, providing the pull-up voltage for the power good signal circuit. | | 2 | 2 | VGFX_PG | ✅ | Pin 2 connects to the VGFX_PG net, providing the necessary pull-up for the open-drain VR_RDY output from the voltage regulator. | </details> <details> <summary><b>C60</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Pin 1 connects to the VGFX_PG net, providing filtering and noise suppression for the power good signal. | | 2 | 2 | GND | ✅ | Pin 2 connects to ground, completing the bypass capacitor circuit for filtering the power good signal. | </details> <details> <summary><b>R184</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Pin 1 connects to the VGFX_PG net, which is the power good signal from the voltage regulator. This pin is part of a 0 ohm jumper that allows the VR_RDY signal to be routed to the power good net. | | 2 | 2 | $24N3598 | ✅ | Pin 2 connects to net $24N3598, which is the VR_RDY output from U26 pin 6. This connection routes the voltage regulator ready signal through the jumper to the power good net. | </details> <details> <summary><b>C186</b> - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3596 | ✅ | Connected to R228 pin 2, forming the intermediate node in the bootstrap circuit. | | 2 | 2 | $24N3595 | ✅ | Connected to U26 SW1 pin (switch node). The bootstrap capacitor charges when the switch node is low. | </details> <details> <summary><b>R228</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3593 | ✅ | Connected to U26 BST pin (bootstrap supply). This resistor limits inrush current to the bootstrap capacitor C186. | | 2 | 2 | $24N3596 | ✅ | Connected to C186 pin 1, forming the intermediate node between the bootstrap resistor and capacitor. | </details> <details> <summary><b>R846</b> - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB power supply rail. This pin sources power for the VCCP supply of the voltage regulator controller U26. | | 2 | 2 | $24N3578 | ✅ | Connected to net $24N3578, which supplies the VCCP pin (pin 33) of U26 and is decoupled by C185. This provides the control power supply for the voltage regulator controller. | </details> <details> <summary><b>C185</b> - 2232-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3578 | ✅ | Connected to net $24N3578, which is the VCCP supply for U26. This is the positive terminal of the decoupling capacitor. | | 2 | 2 | GND | ✅ | Connected to GND. This is the negative terminal of the decoupling capacitor, providing the return path for the VCCP supply. | </details> <details> <summary><b>R229</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB power rail, providing input power to the VCC supply path for U26. | | 2 | 2 | $24N3610 | ✅ | Connected to net $24N3610, which feeds U26 pin 47 (VCC) and is bypassed by C53. | </details> <details> <summary><b>C53</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3610 | ✅ | Connected to net $24N3610, providing bypass capacitance for U26's VCC pin. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, providing the ground return path for the VCC bypass capacitor. | </details> <details> <summary><b>R203</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3542 | ✅ | Pin 1 connects to the FREQ pin of U26 (NCP81109GMNTXG) to set the switching frequency. The nearby text note indicates the target frequency is 650 kHz. | | 2 | 2 | AGND-VGFX | ✅ | Pin 2 connects to AGND-VGFX, which is the analog ground reference for the voltage regulator U26. This provides the correct ground reference for the frequency-setting resistor. | </details> <details> <summary><b>R201</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing an alternate ground reference path for the VSN sensing circuit. | | 2 | 2 | $24N3528 | ✅ | Connected to intermediate node $24N3528 in the VSN sensing path. | </details> <details> <summary><b>R202</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Connected to +VGFX output voltage, providing local voltage sensing capability. | | 2 | 2 | VR-VGFX-VSP | ✅ | Connected to VSP sense pin of U26 through VR-VGFX-VSP net. | </details> <details> <summary><b>R68</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCCGT_SENSE | ✅ | Connected to VCCGT_SENSE, enabling remote voltage sensing at the load. | | 2 | 2 | VR-VGFX-VSP | ✅ | Connected to VSP sense pin of U26 through VR-VGFX-VSP net. | </details> <details> <summary><b>R69</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the VSN sensing path. | | 2 | 2 | $24N3528 | ✅ | Connected to intermediate node $24N3528 in the VSN sensing path. | </details> <details> <summary><b>R169</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | Connected to intermediate node $24N3528, which is tied to ground through R69 and R201. | | 2 | 2 | VR-VGFX-VSN | ✅ | Connected to VSN sense pin of U26 through VR-VGFX-VSN net. | </details> <details> <summary><b>C61</b> - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VGFX-VSP | ✅ | DNI capacitor that would provide differential filtering across VSP and VSN if populated. Designer chose not to install this component. | | 2 | 2 | VR-VGFX-VSN | ✅ | DNI capacitor that would provide differential filtering across VSP and VSN if populated. Designer chose not to install this component. | </details> <details> <summary><b>C104</b> - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | DNI capacitor that would provide additional filtering on the VSN line if populated. Designer chose not to install this component. | | 2 | 2 | VR-VGFX-VSN | ✅ | DNI capacitor that would provide additional filtering on the VSN line if populated. Designer chose not to install this component. | </details> <details> <summary><b>R66</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to the main power ground net GND. This is one side of the 0-ohm jumper that bridges analog and power grounds. | | 2 | 2 | AGND-VGFX | ✅ | Pin 2 connects to the analog ground net AGND-VGFX. This is the other side of the 0-ohm jumper that bridges analog and power grounds. | </details> <details> <summary><b>R231</b> - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to the VGFX-SW switching node. This is the input to the RC snubber network. | | 2 | 2 | $24N3623 | ✅ | Connected to the intermediate node between R231 and C187, forming the RC snubber network. | </details> <details> <summary><b>C187</b> - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3623 | ✅ | Connected to the intermediate node between R231 and C187, forming the capacitive element of the RC snubber. | | 2 | 2 | GND | ✅ | Connected to ground, completing the RC snubber path from the switching node to ground. | </details> <details> <summary><b>R854</b> - 1130-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Pin 1 is connected to the +VGFX output rail of the DC/DC GFX regulator. This is the positive terminal of the minimum load resistor. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, forming a minimum load resistor from +VGFX to ground. This provides a discharge path and ensures minimum load for regulator stability. | </details> <details> <summary><b>C76</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal of bulk output capacitor connected to +VGFX output rail. | | 2 | N | GND | ✅ | Negative terminal of bulk output capacitor connected to ground. | </details> <details> <summary><b>C77</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal of bulk output capacitor connected to +VGFX output rail, in parallel with C76. | | 2 | N | GND | ✅ | Negative terminal of bulk output capacitor connected to ground. | </details> <details> <summary><b>U41</b> - RT8207 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.richtek.com/SaveDownload.aspx?specid=RT8207P) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4124-0013) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 22 | BOOT | $25N771 | ❌ | <details><summary>BOOT pin is connected to the bootstrap circuit through a 4.7-ohm resistor (R298) and 0.1µF capacitor (C309) to PHASE. However, the bootstrap capacitor value is significantly undersized compared to the 1µF datasheet recommendation, which may cause insufficient gate drive voltage.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="45.80,38.02,53.30,45.52" aspect-ratio="1.29" } <ul><li>Pin 22 (BOOT) is connected to net $25N771 <em>(from schematic)</em></li><li>DDR_BST connects to C309 pin 2 (0.1µF capacitor) <em>(from schematic)</em></li><li>C309 pin 1 connects to DDR_PHASE (PHASE pin) <em>(from schematic)</em></li><li>BOOT is the boost flying capacitor connection for VDDQ per the datasheet <em>(from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P">4124-0013</a>)</em></li><li>The datasheet recommends a 1µF flying bootstrap capacitor between BOOT and PHASE pins <em>(from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P">4124-0013</a>)</em></li><li>The schematic uses C309 (0.1µF) as the bootstrap capacitor, which is 10x smaller than recommended <em>(reasoning)</em></li><li>The datasheet mentions adding a resistor in series with BOOT to reduce gate-drain coupling in high current applications <em>(from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P">4124-0013</a>)</em></li><li>The 4.7Ω resistor R298 is likely for reducing gate-drain coupling <em>(reasoning)</em></li><li>An undersized bootstrap capacitor may result in insufficient gate drive voltage, increased switching losses, or potential shoot-through issues <em>(reasoning)</em></li><li>The bootstrap capacitor should be increased to 1µF as recommended by the datasheet <em>(reasoning)</em></li></ul></details> | | 1 | VTTGND | GND | ✅ | VTTGND is correctly connected to ground plane, providing power ground return for the VTT LDO. | | 2 | VTTSNS | +VDIMM_VTT | ✅ | VTTSNS is correctly connected to the VTT output rail (+VDIMM_VTT) for remote voltage sensing of the VTT LDO output. | | 3 | GND | GND | ✅ | GND pin is correctly connected to ground plane for analog ground reference. | | 4 | MODE | GND | ✅ | MODE pin is connected to ground, which may configure a specific operating mode for the controller. | | 5 | VTTREF | $25N769 | ✅ | VTTREF is correctly connected to a bypass capacitor (C342, 0.22µF) to ground, providing the buffered reference output for VTT regulation. | | 6 | DEM | $25N1291 | ✅ | DEM pin is connected to a 10K pullup resistor to +5VSB, likely configuring diode emulation mode operation. | | 8 | VDDQ | +VDIMM | ✅ | VDDQ pin is correctly connected to the VDDQ output rail (+VDIMM), providing the reference input for VTT/VTTREF and feedback for VDDQ output. | | 9 | FB | $25N987 | ✅ | FB pin is correctly connected to a resistive voltage divider (R814: 8.06K, R815: 10K) with compensation capacitor (C382: 22pF) to set VDDQ output voltage to approximately 1.35V for DDR3L operation. | | 10 | S3 | EN_VTT | ✅ | S3 pin is correctly connected to the EN_VTT signal through a 0-ohm resistor (R302) from SLP_S3_L, controlling VTT enable state. | | 11 | S5 | EN_VDDQ | ✅ | S5 pin is correctly connected to the EN_VDDQ signal through a 0-ohm resistor (R300) from SLP_S4_L, controlling VDDQ enable state. | | 12 | TON | $25N1081 | ✅ | TON pin is correctly connected to a 464K resistor (R816) to +5VSB to set the on-time and switching frequency. The actual frequency (~500kHz) differs from a schematic note mentioning 285kHz with 806K, but this appears intentional for the design. | | 13 | PGOOD | DRAM_PWROK | ✅ | PGOOD pin is correctly connected to DRAM_PWROK with a 10K pullup resistor to +VDIMM, providing power good indication as an open-drain output. | | 14 | VDD | $25N1195 | ✅ | VDD pin is correctly connected to a filtered supply from +5VSB through a 2.2-ohm resistor (R813) with 1µF bypass capacitor (C380), providing analog supply voltage. | | 15 | VDDP | +5VSB | ✅ | VDDP pin is correctly connected to +5VSB rail with bypass capacitors, providing supply voltage for the LGATE gate driver. | | 16 | CS | $25N1238 | ✅ | CS pin is correctly connected to a 3.83K resistor (R817) to VDD to set the current limit threshold. The value differs from the typical 6K but appears intentional for the 11A overcurrent protection requirement. | | 18 | PGND | GND | ✅ | PGND pin is correctly connected to ground plane and the source pins of the low-side MOSFET (Q102), providing power ground for the switching circuit. | | 19 | LGATE | $25N901 | ✅ | LGATE pin is correctly connected to the low-side MOSFET gate (Q102 pin 8), providing the gate drive signal for the synchronous rectifier. | | 20 | PHASE | DDR_PHASE | ✅ | PHASE pin is correctly connected to the switching node, connecting to the MOSFET switch node (Q102 pin 9), output inductor (L11), and bootstrap capacitor (C309). | | 21 | UGATE | $25N897 | ✅ | UGATE pin is correctly connected to the high-side MOSFET gate (Q102 pin 1), providing the gate drive signal for the main switch. | | 23 | VLDOIN | +VDIMM | ✅ | VLDOIN pin is correctly connected to the +VDIMM output rail, enabling tracking discharge mode operation where VTT tracks VDDQ during shutdown. | | 24 | VTT | +VDIMM_VTT | ✅ | VTT pin is correctly connected to the +VDIMM_VTT output rail with output capacitors (C361, C362: 10µF each, C343: 0.1µF), meeting the minimum 20µF requirement. | | 25 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) is correctly connected to ground plane for thermal dissipation and electrical grounding. | </details> <details> <summary><b>Q102</b> - FDMS3604S ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pub/Collateral/FDMS3604S-D.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4860-0031) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Q1G | $25N897 | ✅ | Q1G (upper MOSFET gate) is correctly connected to UGATE output from controller U41 for high-side gate drive. | | 2 | VIN_A | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (upper MOSFET drain pins) are correctly connected to DDR3L_VIN input rail with appropriate input capacitance. | | 3 | VIN_B | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (upper MOSFET drain pins) are correctly connected to DDR3L_VIN input rail with appropriate input capacitance. | | 4 | VIN_C | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (upper MOSFET drain pins) are correctly connected to DDR3L_VIN input rail with appropriate input capacitance. | | 5 | PGND_A | GND | ✅ | PGND_A, PGND_B, PGND_C (lower MOSFET source pins) are correctly connected to GND for power ground return. | | 6 | PGND_B | GND | ✅ | PGND_A, PGND_B, PGND_C (lower MOSFET source pins) are correctly connected to GND for power ground return. | | 7 | PGND_C | GND | ✅ | PGND_A, PGND_B, PGND_C (lower MOSFET source pins) are correctly connected to GND for power ground return. | | 8 | Q2G | $25N901 | ✅ | Q2G (lower MOSFET gate) is correctly connected to LGATE output from controller U41 for low-side gate drive. | | 9 | PHASE | DDR_PHASE | ✅ | PHASE (switch node) is correctly connected to the output inductor L11 and bootstrap capacitor C309, with feedback to controller U41. | </details> <details> <summary><b>L5</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to the +5VSB standby power rail, serving as the input side of the ferrite bead filter. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is connected to the DDR3L_VIN net, serving as the output side of the ferrite bead filter that supplies the DDR power converter input. | </details> <details> <summary><b>L6</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to the +5VSB standby power rail, serving as the input side of the ferrite bead filter in parallel with L5. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is connected to the DDR3L_VIN net, serving as the output side of the ferrite bead filter in parallel with L5. | </details> <details> <summary><b>L11</b> - 125-0004454 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/125-0004454) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | Pin 1 connects to the switching node DDR_PHASE, which is the output of the buck converter switching stage before filtering. This is the correct connection for the input side of an output filter inductor. | | 2 | 2 | +VDIMM | ✅ | Pin 2 connects to the filtered output voltage rail +VDIMM. This is the correct connection for the output side of a buck converter filter inductor. | </details> <details> <summary><b>R814</b> - 1120-0187 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0187) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Upper feedback resistor connected from output voltage +VDIMM to feedback node. This connection is correct. | | 2 | 2 | $25N987 | ✅ | Connected to feedback node $25N987. See pin 1 analysis. | </details> <details> <summary><b>R815</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N987 | ✅ | Lower feedback resistor connected from feedback node to ground. This connection is correct. | | 2 | 2 | GND | ✅ | Connected to ground. See pin 1 analysis. | </details> <details> <summary><b>C382</b> - 2220-0047 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2220-0047) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Compensation capacitor connected in parallel with upper feedback resistor R814. This connection is correct. | | 2 | 2 | $25N987 | ✅ | Connected to feedback node $25N987. See pin 1 analysis. | </details> <details> <summary><b>R300</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SLP_S4_L | ✅ | 0 ohm jumper connecting SLP_S4_L to EN_VDDQ, routing the S4 sleep state signal to control the VDDQ rail enable (S5 pin of U41). | | 2 | 2 | EN_VDDQ | ✅ | 0 ohm jumper connecting SLP_S4_L to EN_VDDQ, routing the S4 sleep state signal to control the VDDQ rail enable (S5 pin of U41). | </details> <details> <summary><b>R293</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DRAM_S4_PWROK | ✅ | 0 ohm jumper connecting DRAM_S4_PWROK to DRAM_PWROK, routing the power good signal from the intermediate node to the final output. | | 2 | 2 | DRAM_PWROK | ✅ | 0 ohm jumper connecting DRAM_S4_PWROK to DRAM_PWROK, routing the power good signal from the intermediate node to the final output. | </details> <details> <summary><b>R302</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SLP_S3_L | ✅ | 0 ohm jumper connecting SLP_S3_L to EN_VTT, routing the S3 sleep state signal to control the VTT rail enable (S3 pin of U41). | | 2 | 2 | EN_VTT | ✅ | 0 ohm jumper connecting SLP_S3_L to EN_VTT, routing the S3 sleep state signal to control the VTT rail enable (S3 pin of U41). | </details> <details> <summary><b>R124</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DRAM_S4_PWROK | ✅ | 10K pull-up resistor connecting DRAM_S4_PWROK to +VDIMM, providing pull-up for the power good signal from U41 pin 13. | | 2 | 2 | +VDIMM | ✅ | 10K pull-up resistor connecting DRAM_S4_PWROK to +VDIMM, providing pull-up for the power good signal from U41 pin 13. | </details> <details> <summary><b>R816</b> - 1120-0149 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0149) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | 2 | $25N1081 | ❌ | <details><summary>Connected to U41 pin 12 (TON) to set switching frequency. However, the resistor value of 464K does not match the design specification of 806K stated in the schematic notes, which would result in incorrect switching frequency (504 kHz instead of the intended 285 kHz).</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,36.84,35.12,44.34" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to net $25N1081, which connects to U41 pin 12 (TON) <em>(from schematic)</em></li><li>The TON pin sets the switching frequency of the RT8207M controller via an external resistor <em>(reasoning)</em></li><li>A schematic note states &#x27;Rton=806K , F=285KHz&#x27; indicating the design intent for switching frequency <em>(from schematic)</em></li><li>A schematic note provides the formula &#x27;F= (Vin - 0.5) / 3.85p*Vin*Rton&#x27; for calculating switching frequency <em>(from schematic)</em></li><li>R816 is specified as 464K (part number 1120-0149) <em>(from schematic)</em></li><li>Using the provided formula with Vin=5V and Rton=464K yields F = (5-0.5)/(3.85e-12*5*464000) = 503.8 kHz <em>(reasoning)</em></li><li>Using the provided formula with Vin=5V and Rton=806K yields F = (5-0.5)/(3.85e-12*5*806000) = 290 kHz, which matches the design specification of 285 kHz <em>(reasoning)</em></li><li>The resistor value of 464K does not match the design specification of 806K, resulting in a switching frequency approximately 1.74x higher than intended <em>(reasoning)</em></li><li>R816 should be changed to 806K (or nearest standard value) to achieve the intended 285 kHz switching frequency <em>(reasoning)</em></li></ul></details> | | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This pin provides the reference voltage for the TON timing resistor that sets the switching frequency of the RT8207M controller. | </details> <details> <summary><b>R817</b> - 1120-0267 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0267) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | Connected to net $25N1195 which supplies U41 pin 14 (VDD). This pin is part of the current sense and VDD supply network for the RT8207M controller. | | 2 | 2 | $25N1238 | ✅ | Connected to U41 pin 16 (CS - Current Sense). This pin provides current sense signal conditioning for the RT8207M controller. | </details> <details> <summary><b>R813</b> - 110-0004466 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004466) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | Connected to net $25N1195 which supplies U41 pin 14 (VDD). This pin is the load side of the current sense resistor. | | 2 | 2 | +5VSB | ✅ | Connected to +5VSB supply rail. This pin is the source side of the current sense resistor that monitors input current to the RT8207M controller. | </details> <details> <summary><b>C379</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001066) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for decoupling capacitor. This pin is correctly connected to the GND net. | | 2 | 2 | +5VSB | ✅ | Connected to +5VSB rail for bulk decoupling. This pin is correctly connected to provide input supply decoupling for the DDR power circuit. | </details> <details> <summary><b>C380</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001066) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for decoupling capacitor. This pin is correctly connected to the GND net. | | 2 | 2 | $25N1195 | ✅ | Connected to VDD supply net ($25N1195) for local decoupling of U41. This pin is correctly connected to provide decoupling for the controller IC's internal logic supply. | </details> <details> <summary><b>U21</b> - APL5933 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P8S_PGD | ✅ | PGOOD output is pulled up to the output voltage (+V1P8S) through R23 (4.7K). This is a valid configuration for an open-drain power good output. | | 2 | EN | +V1P8S_EN | ✅ | EN pin is connected to the enable signal through R22 (0 ohm jumper). The enable signal includes sequencing logic to ensure the 1.35V rail is stable before enabling this 1.8V regulator. | | 3 | VIN | +PS_3VSB | ✅ | VIN and VDD pins are both connected to +PS_3VSB (3.3V standby supply). This is correct as both pins typically need to be connected to the input supply. | | 4 | VDD | +PS_3VSB | ✅ | VIN and VDD pins are both connected to +PS_3VSB (3.3V standby supply). This is correct as both pins typically need to be connected to the input supply. | | 5 | NC | | ✅ | NC pin has no connection, which is correct for a no-connect pin. | | 6 | VOUT | +V1P8S | ✅ | VOUT pin is connected to +V1P8S output rail with appropriate output capacitors for filtering and stability. | | 7 | ADJ | +V1P8S_FB | ✅ | ADJ pin is connected to a feedback divider formed by R24 (12.1K) and R25 (9.53K) that sets the output voltage to approximately 1.8V. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins are both properly connected to ground. Multiple ground pins are common in power ICs for thermal and electrical performance. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins are both properly connected to ground. Multiple ground pins are common in power ICs for thermal and electrical performance. | </details> <details> <summary><b>R25</b> - 110-0004490 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004490) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | R25 (9.53K) is the lower resistor (R2) in the feedback divider that sets the output voltage to 1.8V. | | 2 | 2 | +V1P8S_FB | ✅ | R25 (9.53K) is the lower resistor (R2) in the feedback divider that sets the output voltage to 1.8V. | </details> <details> <summary><b>R24</b> - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | R24 (12.1K) is the upper resistor (R1) in the feedback divider that sets the output voltage to 1.8V. | | 2 | 2 | +V1P8S_FB | ✅ | R24 (12.1K) is the upper resistor (R1) in the feedback divider that sets the output voltage to 1.8V. | </details> <details> <summary><b>R23</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | R23 (4.7K) is a pull-up resistor for the power good signal, pulling it to the output voltage (1.8V). | | 2 | 2 | +V1P8S_PGD | ✅ | R23 (4.7K) is a pull-up resistor for the power good signal, pulling it to the output voltage (1.8V). | </details> <details> <summary><b>R22</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V_EN | ✅ | R22 (0 ohm) is a jumper connecting the enable signal from the sequencing circuit to the LDO enable pin. | | 2 | 2 | +V1P8S_EN | ✅ | R22 (0 ohm) is a jumper connecting the enable signal from the sequencing circuit to the LDO enable pin. | </details> <details> <summary><b>R135</b> - 110-0004498 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004498) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor correctly connected to ground. | | 2 | 2 | FB_V1P0S | ✅ | Upper terminal correctly connected to feedback node. | </details> <details> <summary><b>R136</b> - 110-0002029 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002029) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FB_V1P0S | ✅ | Lower terminal correctly connected to feedback node. | | 2 | 2 | +V1P0S | ✅ | Upper feedback resistor correctly connected to output voltage. | </details> <details> <summary><b>R320</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCNTL_V1P0S | ✅ | Connected to VCNTL pin of U38. Connection appears intentional but cannot be fully verified without datasheet. | | 2 | 2 | +VCC | ✅ | Connected to +VCC rail. 10 ohm value suggests current limiting or isolation function. | </details> <details> <summary><b>R319</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | Connected to power good output of U38. | | 2 | 2 | +VCC | ✅ | Pullup resistor correctly connected to +VCC for power good signal. | </details> <details> <summary><b>U38</b> - APL5912KAC-TRGS-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004525) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 2 | FB | FB_V1P0S | ✅ | FB pin correctly connected to feedback divider network consisting of R135 (143K to GND), R136 (40.2K to VOUT), and C119 (27pF compensation capacitor). | | 3 | VOUT-2 | +V1P0S | ✅ | VOUT-2 and VOUT-1 pins correctly connected to +V1P0S output rail with adequate output capacitance (76uF total). | | 4 | VOUT-1 | +V1P0S | ✅ | VOUT-2 and VOUT-1 pins correctly connected to +V1P0S output rail with adequate output capacitance (76uF total). | | 5 | VIN-2 | +VDIMM | ✅ | VIN-2 and VIN-1 pins correctly connected to +VDIMM input rail with adequate input capacitance (20uF total). | | 9 | VIN-1 | +VDIMM | ✅ | VIN-2 and VIN-1 pins correctly connected to +VDIMM input rail with adequate input capacitance (20uF total). | | 6 | VCNTL | VCNTL_V1P0S | ✅ | VCNTL pin connected to +VCC through R320 (10 ohm) with C117 (1uF) to ground. Without datasheet, this connection cannot be fully verified but appears to be a control voltage input. | | 7 | POK | V1P0S_PG | ✅ | POK (power good) pin correctly connected to V1P0S_PG with R319 (10K) pull-up to +VCC. | | 8 | EN | 1P0V_EN | ✅ | EN (enable) pin correctly connected to 1P0V_EN signal for power sequencing. Schematic note indicates enable threshold > 0.5V. | </details> <details> <summary><b>R32</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Enable pull-up resistor correctly connected between +5VSB and enable pin. The 4.7K value pulls the enable pin to 5V, well above the 1.1V threshold. | | 2 | 2 | +V1P0A_ENABLE | ✅ | Enable pull-up resistor correctly connected between +5VSB and enable pin. The 4.7K value pulls the enable pin to 5V, well above the 1.1V threshold. | </details> <details> <summary><b>R33</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | Power good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin. The 4.7K value provides standard pull-up for open-drain power good output. | | 2 | 2 | +V1P0A_PWRGD | ✅ | Power good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin. The 4.7K value provides standard pull-up for open-drain power good output. | </details> <details> <summary><b>R34</b> - 110-0003781 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0003781) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Upper feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and output voltage (+V1P0A). The 6.04K value sets the output to 1.004V. | | 2 | 2 | +V1P0A | ✅ | Upper feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and output voltage (+V1P0A). The 6.04K value sets the output to 1.004V. | </details> <details> <summary><b>U24</b> - APL5933 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P0A_PWRGD | ✅ | PGOOD pin correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB. This provides open-drain power good signaling to downstream circuits. | | 2 | EN | +V1P0A_ENABLE | ✅ | EN pin correctly connected to +V1P0A_ENABLE net with pull-up resistor R32 to +5VSB. The enable threshold is >1.1V per schematic notes, and the 5V pull-up easily meets this requirement. | | 3 | VIN | +PS_3VSB | ✅ | VIN pin correctly connected to +PS_3VSB input power rail with appropriate input filtering capacitors. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin correctly connected to +PS_3VSB input power rail, same as VIN pin. | | 5 | NC | | ✅ | NC pin correctly left unconnected as specified by the pin name. | | 6 | VOUT | +V1P0A | ✅ | VOUT pin correctly connected to +V1P0A output rail with appropriate output filtering capacitors C22 (0.1uF) and C21 (22uF). | | 7 | ADJ | +V1P0A_FB | ✅ | ADJ pin correctly connected to feedback network consisting of R34 (6.04K to VOUT) and R35 (23.7K to GND). This sets output voltage to 1.004V, matching the 1.0V target. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins correctly connected to ground plane. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins correctly connected to ground plane. | </details> <details> <summary><b>R35</b> - 110-0004494 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004494) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Lower feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and ground. The 23.7K value works with R34 to set the output to 1.004V. | | 2 | 2 | GND | ✅ | Lower feedback resistor correctly connected between ADJ pin feedback net (+V1P0A_FB) and ground. The 23.7K value works with R34 to set the output to 1.004V. | </details> <details> <summary><b>U20</b> - 140-0004677 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncp605-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004677) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN1 | +PS_3VSB | ✅ | VIN1 and VIN2 pins are both correctly connected to +PS_3VSB input supply. The datasheet requires both pins to be connected together externally for full output current range operation. | | 6 | VIN2 | +PS_3VSB | ✅ | VIN1 and VIN2 pins are both correctly connected to +PS_3VSB input supply. The datasheet requires both pins to be connected together externally for full output current range operation. | | 2 | GND | GND | ✅ | GND and GND_PAD pins are both correctly connected to the GND net for power supply ground and thermal relief. | | 7 | GND_PAD | GND | ✅ | GND and GND_PAD pins are both correctly connected to the GND net for power supply ground and thermal relief. | | 3 | EN | +V1P8A_EN | ✅ | EN pin is correctly connected to +V1P8A_EN, which is controlled by the power good signal from U24 (+V1P0A_PWRGD) through R151 (0 ohm). This implements power sequencing where +V1P8A is enabled after +V1P0A is stable. | | 4 | VOUT | +V1P8A | ✅ | VOUT pin is correctly connected to +V1P8A output net with appropriate decoupling capacitor C151 (10uF), which exceeds the datasheet minimum requirement of 1.0uF. | | 5 | SENSE/ADJ | +V1P8A_FB | ✅ | SENSE/ADJ pin is correctly connected to the feedback network consisting of R150 (12.1K) to VOUT and R153 (27.4K) to GND, which sets the output voltage to approximately 1.802V (target 1.8V). | </details> <details> <summary><b>R153</b> - 110-0002726 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002726) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R153 (27.4K ohm) is correctly configured as R2 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to ground. | | 2 | 2 | GND | ✅ | R153 (27.4K ohm) is correctly configured as R2 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to ground. | </details> <details> <summary><b>R150</b> - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R150 (12.1K ohm) is correctly configured as R1 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to the output voltage (+V1P8A). | | 2 | 2 | +V1P8A | ✅ | R150 (12.1K ohm) is correctly configured as R1 in the feedback divider network, connecting the SENSE/ADJ pin (via +V1P8A_FB) to the output voltage (+V1P8A). | </details> <details> <summary><b>R151</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | R151 (0 ohm) is correctly configured to connect the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN), implementing power sequencing. | | 2 | 2 | +V1P8A_EN | ✅ | R151 (0 ohm) is correctly configured to connect the power good signal from U24 (+V1P0A_PWRGD) to the enable input of U20 (+V1P8A_EN), implementing power sequencing. | </details> <details> <summary><b>Q5</b> - RXR035N03 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/132-0004421) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +VDIMM | ✅ | Drain is correctly connected to +VDIMM input rail for high-side switch configuration. | | G | GATE | 1P35V_EN | ✅ | Gate is driven by V1P0S_PG through R134 (1kΩ) to enable the switch. Gate drive voltage may be marginal depending on +VCC voltage; designer notes indicate VGS should exceed 2V for proper operation. | | S | SOURCE | +V1P35S | ✅ | Source is correctly connected to +V1P35S output rail for high-side switch configuration. | </details> <details> <summary><b>R134</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | 1kΩ resistor correctly connects V1P0S_PG power good signal to Q5 gate, providing appropriate gate drive current limiting. | | 2 | 2 | 1P35V_EN | ✅ | 1kΩ resistor correctly connects V1P0S_PG power good signal to Q5 gate, providing appropriate gate drive current limiting. | </details> <details> <summary><b>R120</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | 10kΩ resistor correctly connects V1P35S output to Q3 base for power good sensing, providing appropriate base current. | | 2 | 2 | 1P35V_PWG | ✅ | 10kΩ resistor correctly connects V1P35S output to Q3 base for power good sensing, providing appropriate base current. | </details> <details> <summary><b>R60</b> - 110-0001957 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001957) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | 20K pull-up resistor from +PS_3VSB to PSPUP, providing pull-up for Q1 transistor 1 collector output. | | 2 | 2 | PSPUP | ✅ | 20K pull-up resistor from +PS_3VSB to PSPUP, providing pull-up for Q1 transistor 1 collector output. | </details> <details> <summary><b>R61</b> - 110-0001957 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001957) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | 20K pull-up resistor from +VCC3 to SYS_PWRGD, providing pull-up for Q1 transistor 2 collector output. | | 2 | 2 | SYS_PWRGD | ✅ | 20K pull-up resistor from +VCC3 to SYS_PWRGD, providing pull-up for Q1 transistor 2 collector output. | </details> <details> <summary><b>R206</b> - 110-0001951 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001951) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PSGOOD | ✅ | 200K pull-up resistor from +V1P8S to PSGOOD, working with C44 (1uF) to create approximately 200ms delay that meets the >100ms requirement noted on the schematic. | | 2 | 2 | +V1P8S | ✅ | 200K pull-up resistor from +V1P8S to PSGOOD, working with C44 (1uF) to create approximately 200ms delay that meets the >100ms requirement noted on the schematic. | </details> <details> <summary><b>R125</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | 4.7K pull-up resistor from +VCC to 1P8V_EN, providing pull-up for Q3 transistor 2 collector output. | | 2 | 2 | 1P8V_EN | ✅ | 4.7K pull-up resistor from +VCC to 1P8V_EN, providing pull-up for Q3 transistor 2 collector output. | </details> <details> <summary><b>R126</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | 4.7K pull-up resistor from +5VSB to 1P5V_EN_B, providing pull-up for Q3 transistor 1 collector output. | | 2 | 2 | 1P5V_EN_B | ✅ | 4.7K pull-up resistor from +5VSB to 1P5V_EN_B, providing pull-up for Q3 transistor 1 collector output. | </details> <details> <summary><b>Q1</b> - 132-0004425 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter of first NPN transistor (E1) correctly connected to ground for common-emitter configuration. | | 2 | B1 | PSGOOD | ✅ | Base of first NPN transistor (B1) connected to PSGOOD signal, which controls the first stage of the power sequencing circuit. | | 3 | C2 | SYS_PWRGD | ✅ | Collector of second NPN transistor (C2) connected to SYS_PWRGD output signal, which is the final output of the two-stage buffer. | | 4 | E2 | GND | ✅ | Emitter of second NPN transistor (E2) correctly connected to ground for common-emitter configuration. | | 5 | B2 | PSPUP | ✅ | Base of second NPN transistor (B2) connected to PSPUP signal, which is the intermediate signal between the two transistor stages. | | 6 | C1 | PSPUP | ✅ | Collector of first NPN transistor (C1) connected to PSPUP signal, which is the output of the first stage and input to the second stage. | </details> <details> <summary><b>Q3</b> - 132-0004425 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter of first NPN transistor (E1) correctly connected to ground for common-emitter configuration. | | 2 | B1 | 1P35V_PWG | ✅ | Base of first NPN transistor (B1) connected to 1P35V_PWG power good signal, which initiates the power sequencing. | | 3 | C2 | 1P8V_EN | ✅ | Collector of second NPN transistor (C2) connected to 1P8V_EN enable signal, which is the final output enabling the 1.8V rail. | | 4 | E2 | GND | ✅ | Emitter of second NPN transistor (E2) correctly connected to ground for common-emitter configuration. | | 5 | B2 | 1P5V_EN_B | ✅ | Base of second NPN transistor (B2) connected to 1P5V_EN_B signal, which is the intermediate signal between the two transistor stages. | | 6 | C1 | 1P5V_EN_B | ✅ | Collector of first NPN transistor (C1) connected to 1P5V_EN_B signal, which is the output of the first stage and input to the second stage. | </details> <details> <summary><b>D11</b> - 130-0004403 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | Anode 1 of dual Schottky diode connected to +V1P0A_PWRGD signal, one input of the diode AND gate. | | 2 | 2 | SLP_S3_L | ✅ | Anode 2 of dual Schottky diode connected to SLP_S3_L signal, the second input of the diode AND gate. | | 3 | 3 | PSGOOD | ✅ | Common cathode of dual Schottky diode connected to PSGOOD signal, the output of the diode AND gate. | </details> <details> <summary><b>FB7</b> - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Input pin connected to +VCC3 power rail. This is the source side of the 0-ohm jumper that feeds the +VCC3S CPU power rail. | | 2 | 2 | +VCC3S | ✅ | Output pin connected to +VCC3S power rail. This feeds the CPU power rail with appropriate decoupling capacitor C247. | </details> <details> <summary><b>R306</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | Pin 1 connects to VCORE_GFX_PG, which is a power good signal from a graphics core voltage regulator used for power sequencing. | | 2 | 2 | 1P0V_EN | ✅ | Pin 2 connects to 1P0V_EN, which is the enable signal for U38, a 5A LDO regulator generating +V1P0S. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **R127, R128, R129, R130, R151, R18, R192, R20, R216, R22, R293, R300, R302, R306, R354, R48, R5, R51, R72, R73, R74, R809** (110-0001853): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001853) - **R147** (110-0001859): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001859) - **R116, R120, R124, R13, R14, R163, R164, R165, R189, R190, R191, R2, R209, R210, R211, R219, R220, R221, R260, R266, R267, R268, R28, R29, R30, R319, R400, R71, R810** (110-0001875): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001875) - **R134, R15, R16, R17, R208, R233, R234, R259, R401, R6, R7** (110-0001923): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001923) - **R206, R812** (110-0001951): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001951) - **R3** (110-0001954): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001954) - **R60, R61** (110-0001957): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001957) - **R179** (110-0001960): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001960) - **R11, R12, R269, R270** (110-0001967): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001967) - **R171, R172** (110-0001984): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0001984) - **R136** (110-0002029): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002029) - **R125, R126, R23, R32, R33** (110-0002058): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002058) - **R21** (110-0002078): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002078) - **FB7, R152, R222, R265, R275, R818** (110-0002124): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002124) - **R150, R24** (110-0002560): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002560) - **R153** (110-0002726): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0002726) - **R240, R241, R242, R258** (110-0003059): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0003059) - **R34** (110-0003781): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0003781) - **R813** (110-0004466): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004466) - **R298** (110-0004467): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004467) - **R185, R77** (110-0004472): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004472) - **R255** (110-0004474): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004474) - **R218, R239** (110-0004476): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004476) - **R212** (110-0004478): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004478) - **R25** (110-0004490): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004490) - **R35** (110-0004494): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004494) - **R135** (110-0004498): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/110-0004498) - **R832, R833, R834, R835** (1120-0003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0003) - **R837, R838, R839** (1120-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0010) - **R815, R820, R821, R822, R823, R824, R825, R826, R827, R828, R830, R831** (1120-0011): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0011) - **R836** (1120-0018): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0018) - **R320** (1120-0022): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0022) - **R801, R802, R803, R804, R805, R806, R807, R808** (1120-0119): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0119) - **R816** (1120-0149): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0149) - **R814** (1120-0187): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0187) - **R843, R844** (1120-0203): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0203) - **R817** (1120-0267): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0267) - **R848** (1120-0359): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0359) - **R840, R841, R842** (1121-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1121-0001) - **C1, C205, C206, C207, C208, C309, C375, C5** (123-0001056): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001056) - **C2, C379, C380** (123-0001066): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001066) - **C252, C253** (123-0001107): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0001107) - **C342** (123-0003769): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0003769) - **C76, C77, C87** (123-0005035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/123-0005035) - **L11** (125-0004454): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/125-0004454) - **L3** (125-0004501): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/125-0004501) - **FB3** (126-0001423): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0001423) - **FB1, FB11, FB4, FB5, L12, L13, L5, L6** (126-0004457): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/126-0004457) - **D11, D3** (130-0004403): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/130-0004403) - **U38** (140-0004525): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004525) - **U21, U24** (140-0004526): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004526) - **Y1** (145-0004789): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/145-0004789) - **X1, Y2** (145-0004792): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/145-0004792) - **P2** (158-0001269): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/158-0001269) - **P1** (158-0004513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/158-0004513) - **J10** (158-0004534): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/158-0004534) - **C429, C430, C431** (2220-0039): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2220-0039) - **C382** (2220-0047): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2220-0047) - **C425** (2221-0017): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2221-0017) - **C428** (2222-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0014) - **C408, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C426, C427** (2222-0016): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2222-0016) - **C419, C420, C421, C422, C423, C424** (2232-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/2232-0012) - **J5, J6, J7** (258-0002513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0002513) - **USB1** (258-0004503): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004503) - **J2** (258-0004524): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004524) - **J1** (258-0004612): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004612) - **J4** (258-0004869): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0004869) - **JP1** (258-0005019): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/258-0005019) - **FB12** (3044-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3044-0010) - **FB13** (3044-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3044-0012) - **L8** (3120-0183): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3120-0183) - **L18, L4** (3120-0266): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3120-0266) - **CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17** (3142-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3142-0014) - **J11** (3362-0042): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3362-0042) - **J8** (3430-0212): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3430-0212) - **BH1** (353-0003073): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/353-0003073) - **FL1** (3750-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3750-0010) - **SW1** (3770-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3770-0026) - **TH1, TH2, TH3, TH4** (3880-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/3880-0004) - **U18** (4327-0008): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0008) - **U5, U6, U7** (4327-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0009) - **U10, U14, U15, U16, U17, U19** (4327-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4327-0010) - **D10, D5, D8** (4536-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4536-0009) - **D1, D2** (4560-0045): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4560-0045) - **D13** (4620-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4620-0026) - **TP11, TP12** (999-0000002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/999-0000002) - **TP17, TP18** (999-0000003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/999-0000003) - **SP1, SP2** (999-0000005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/999-0000005) - **D4, D6** (BAT54A-S): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BAT54A-S) - **Q2, Q9** (BAV99-7-F-S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BAV99-7-F-S-X) - **L1, L2** (BKP2125HS221-T): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/BKP2125HS221-T) - **U33** (M24C02-WMN6TP-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/M24C02-WMN6TP-X) - **U25, U26** (NCP81109GMNTXG): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NCP81109GMNTXG) - **U35** (NCT3012S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NCT3012S-X) - **U4** (NTS0102GT): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NTS0102GT) - **U29** (TPD4USB30): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/TPD4USB30) - **U42** (WGI210AT): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/WGI210AT) </details> _{^{Note: DRCY uses AI. Please verify the outputs.}}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component CPU1, pins AK12, AK13: DDI0_RCOMP differential pair pins are swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative signal) connects to net DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P indicating positive signal) connects to net DDI_RCOMP_N. These connections are reversed from what they should be.

• Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in both the schematic and datasheet (from schematic)
• Pin AK12 is labeled DDI0_RCOMP_P with _P suffix indicating positive signal in both the schematic and datasheet (from schematic)
• Pin AK13 connects to net DDI_RCOMP_P in the schematic (from schematic)
• Pin AK12 connects to net DDI_RCOMP_N in the schematic (from schematic)
• Compensation resistor R217 (402 ohm, 1%) correctly connects between nets DDI_RCOMP_N and DDI_RCOMP_P (from schematic)
• The datasheet identifies pin AK13 as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (with overline) (from datasheet 140-0004628, page 213)
• The datasheet identifies pin AK12 as DDI0_RCOMP_P (from datasheet 140-0004628, page 213)
• In differential signaling and pin naming conventions, overline notation indicates the negative or inverted signal (reasoning)
• The _P suffix in pin names conventionally indicates the positive signal in a differential pair (reasoning)
• Pin AK13 with overline should connect to DDI_RCOMP_N (negative net), not DDI_RCOMP_P (reasoning)
• Pin AK12 with _P suffix should connect to DDI_RCOMP_P (positive net), not DDI_RCOMP_N (reasoning)
• The nets should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AK12, AK13`: DDI0_RCOMP differential pair pins are swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative signal) connects to net DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P indicating positive signal) connects to net DDI_RCOMP_N. These connections are reversed from what they should be.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,39.05" aspect-ratio="1.29" } - Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in both the schematic and datasheet *(from schematic)* - Pin AK12 is labeled DDI0_RCOMP_P with _P suffix indicating positive signal in both the schematic and datasheet *(from schematic)* - Pin AK13 connects to net DDI_RCOMP_P in the schematic *(from schematic)* - Pin AK12 connects to net DDI_RCOMP_N in the schematic *(from schematic)* - Compensation resistor R217 (402 ohm, 1%) correctly connects between nets DDI_RCOMP_N and DDI_RCOMP_P *(from schematic)* - The datasheet identifies pin AK13 as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (with overline) *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213>), page 213)* - The datasheet identifies pin AK12 as DDI0_RCOMP_P *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213>), page 213)* - In differential signaling and pin naming conventions, overline notation indicates the negative or inverted signal *(reasoning)* - The _P suffix in pin names conventionally indicates the positive signal in a differential pair *(reasoning)* - Pin AK13 with overline should connect to DDI_RCOMP_N (negative net), not DDI_RCOMP_P *(reasoning)* - Pin AK12 with _P suffix should connect to DDI_RCOMP_P (positive net), not DDI_RCOMP_N *(reasoning)* - The nets should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P *(reasoning)* _{Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component R38, pin 1: Connected to VGA DDC data line (CRT_DAT) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.

• Pin 1 is connected to net CRT_DAT (from schematic)
• Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic)
• DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation (reasoning)
• This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up (from schematic)
• The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC data line to ground, preventing any DDC communication (reasoning)
• If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) (reasoning)
• If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down (reasoning)

All affected pins

Component R38, pin `1`: Connected to VGA DDC data line (CRT_DAT) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.

• Pin 1 is connected to net CRT_DAT (from schematic)
• Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic)
• DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation (reasoning)
• This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up (from schematic)
• The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC data line to ground, preventing any DDC communication (reasoning)
• If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) (reasoning)
• If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down (reasoning)

Component R38, pin `2`: Connected to GND, forming the return path for the pull-down resistor.

• Pin 2 is connected to net GND (from schematic)
• This configuration creates a pull-down resistor from CRT_DAT to ground (from schematic)

Component R39, pin `1`: Connected to VGA DDC clock line (CRT_CLK) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.

• Pin 1 is connected to net CRT_CLK (from schematic)
• Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) (from schematic)
• DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation (reasoning)
• This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up (from schematic)
• The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC clock line to ground, preventing any DDC communication (reasoning)
• If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) (reasoning)
• If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down (reasoning)

Component R39, pin `2`: Connected to GND, forming the return path for the pull-down resistor.

• Pin 2 is connected to net GND (from schematic)
• This configuration creates a pull-down resistor from CRT_CLK to ground (from schematic)

[🚨 Error] **Component `R38`, pin `1`: Connected to VGA DDC data line (CRT_DAT) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,40.96,76.02,48.46" aspect-ratio="1.29" } - Pin 1 is connected to net CRT_DAT *(from schematic)* - Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) *(from schematic)* - DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation *(reasoning)* - This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up *(from schematic)* - The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC data line to ground, preventing any DDC communication *(reasoning)* - If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) *(reasoning)* - If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>R38</code>, pin `1`: Connected to VGA DDC data line (CRT_DAT) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.</summary> - Pin 1 is connected to net CRT_DAT *(from schematic)* - Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) *(from schematic)* - DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation *(reasoning)* - This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up *(from schematic)* - The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC data line to ground, preventing any DDC communication *(reasoning)* - If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) *(reasoning)* - If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down *(reasoning)* </details> <details> <summary>Component <code>R38</code>, pin `2`: Connected to GND, forming the return path for the pull-down resistor.</summary> - Pin 2 is connected to net GND *(from schematic)* - This configuration creates a pull-down resistor from CRT_DAT to ground *(from schematic)* </details> <details> <summary>Component <code>R39</code>, pin `1`: Connected to VGA DDC clock line (CRT_CLK) from CPU. This pin should typically connect to a pull-up resistor for proper DDC/I2C operation, but is instead connected to a 150Ω pull-down resistor.</summary> - Pin 1 is connected to net CRT_CLK *(from schematic)* - Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) *(from schematic)* - DDC (Display Data Channel) uses I2C protocol which requires pull-up resistors on both data and clock lines for proper operation *(reasoning)* - This resistor is configured as a pull-down (pin 1 to signal, pin 2 to GND) rather than a pull-up *(from schematic)* - The 150Ω value is unusually low for a pull-down resistor and would effectively short the DDC clock line to ground, preventing any DDC communication *(reasoning)* - If VGA DDC functionality is intended, this should be changed to a pull-up resistor with typical values of 2.2kΩ to 10kΩ connected to an appropriate voltage rail (typically 3.3V or 5V) *(reasoning)* - If VGA DDC is intentionally disabled, a direct connection to GND or removal of the connection would be more typical than a 150Ω pull-down *(reasoning)* </details> <details> <summary>Component <code>R39</code>, pin `2`: Connected to GND, forming the return path for the pull-down resistor.</summary> - Pin 2 is connected to net GND *(from schematic)* - This configuration creates a pull-down resistor from CRT_CLK to ground *(from schematic)* </details> </details>

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component CPU1, pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33: CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.

• Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply (from schematic)
• All nine pins are connected to the +V1P0S net in the schematic (from schematic)
• The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
• The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC (from datasheet 140-0004628, page 119)
• The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) (reasoning)
• The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) (reasoning)
• These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) (reasoning)
• The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification (reasoning)
• Schematic text notes reference '+V1P05S' and 'VCC_CORE_V1P05' with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply (from schematic)
• Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications (reasoning)
• These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33`: CORE_V1P05_S3 pins are incorrectly connected to +V1P0S (1.0V) instead of the required +V1P05S (1.05V) supply. The pin names explicitly indicate these require 1.05V, but the schematic connects them to a 1.0V rail, resulting in a voltage that is 50mV (4.8%) below the nominal requirement and outside the acceptable ±2% DC tolerance range.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,28.61,61.48,49.63" aspect-ratio="1.29" } - Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are named CORE_V1P05_S3_* in the schematic, indicating they require the V1P05S power supply *(from schematic)* - All nine pins are connected to the +V1P0S net in the schematic *(from schematic)* - The datasheet specifies V1P05S supply voltage as 1.05V ±2% DC, ±3% AC with 1.3A maximum current for the CORE_V1P05_S3 rail *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120>), page 120)* - The datasheet specifies V1P0S supply voltage as 1.0V ±2% DC, ±3% AC *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/598938c2e9102fa92d39d27919ce3c273c6b761a/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119>), page 119)* - The acceptable voltage range for CORE_V1P05_S3 is 1.029V to 1.071V (1.05V ±2% DC = ±21mV) *(reasoning)* - The +V1P0S supply voltage range is 0.98V to 1.02V (1.0V ±2% DC = ±20mV) *(reasoning)* - These voltage ranges do not overlap - the maximum voltage from +V1P0S (1.02V) is below the minimum required for CORE_V1P05_S3 (1.029V) *(reasoning)* - The 50mV difference between 1.0V and 1.05V represents a 4.8% deviation from the nominal 1.05V requirement, which exceeds the ±2% DC tolerance specification *(reasoning)* - Schematic text notes reference &#x27;+V1P05S&#x27; and &#x27;VCC_CORE_V1P05&#x27; with placement notes for pins AC32 and Y32, indicating the designer intended to use a 1.05V supply *(from schematic)* - Supplying 1.0V to pins that require 1.05V will cause the processor core to operate below its specified voltage range, potentially resulting in malfunction, instability, or failure to meet performance specifications *(reasoning)* - These pins should be connected to a +V1P05S rail at 1.05V instead of the +V1P0S rail at 1.0V *(reasoning)* _{Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/140-0004628)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component J10, pin 57: XDP test data out signal with 51 ohm resistor to +V1P8A. This connection is incorrect - the resistor value is far too low for a pull-up and the topology is wrong for series termination.

• Pin 57 is connected to net XDP_H_TDO (from schematic)
• Resistor R21 (51 ohm, part 110-0002078) connects XDP_H_TDO to +V1P8A power rail (from schematic)
• TDO (Test Data Out) is the standard JTAG/XDP output signal from the device under test (reasoning)
• TDO is typically an actively driven output signal and does not require a pull-up resistor (reasoning)
• A 51 ohm resistor to power would draw approximately 35mA when TDO is driven low (1.8V / 51Ω ≈ 35mA), which is excessively high current for a logic signal (reasoning)
• If this is intended as a pull-up resistor, 51 ohms is far too low - typical pull-up values are 1K-10K ohms (reasoning)
• If this is intended as series termination, the resistor should be placed in series with the signal path, not connected to the power rail (reasoning)
• Other XDP/JTAG signals on J10 (pins 52, 54, 56, 58 for TRSTB, TCK, TMS, TDI) do not have similar resistor connections, making this connection inconsistent with the rest of the interface (from schematic)
• The most likely correct configurations would be: (1) a higher value pull-up resistor (1K-10K) if a pull-up is needed, (2) a series resistor in the signal path if termination is needed, or (3) no resistor at all since TDO is typically actively driven (reasoning)
• This connection should be corrected to match standard JTAG/XDP interface practices (reasoning)

_{Upload a datasheet: 📤 J10}

[🚨 Error] **Component `J10`, pin `57`: XDP test data out signal with 51 ohm resistor to +V1P8A. This connection is incorrect - the resistor value is far too low for a pull-up and the topology is wrong for series termination.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="3a073003e5413b0412d7" diff-visibility="full" variant="default" view-coords="42.16,50.37,49.66,57.87" aspect-ratio="1.29" } - Pin 57 is connected to net XDP_H_TDO *(from schematic)* - Resistor R21 (51 ohm, part 110-0002078) connects XDP_H_TDO to +V1P8A power rail *(from schematic)* - TDO (Test Data Out) is the standard JTAG/XDP output signal from the device under test *(reasoning)* - TDO is typically an actively driven output signal and does not require a pull-up resistor *(reasoning)* - A 51 ohm resistor to power would draw approximately 35mA when TDO is driven low (1.8V / 51Ω ≈ 35mA), which is excessively high current for a logic signal *(reasoning)* - If this is intended as a pull-up resistor, 51 ohms is far too low - typical pull-up values are 1K-10K ohms *(reasoning)* - If this is intended as series termination, the resistor should be placed in series with the signal path, not connected to the power rail *(reasoning)* - Other XDP/JTAG signals on J10 (pins 52, 54, 56, 58 for TRSTB, TCK, TMS, TDI) do not have similar resistor connections, making this connection inconsistent with the rest of the interface *(from schematic)* - The most likely correct configurations would be: (1) a higher value pull-up resistor (1K-10K) if a pull-up is needed, (2) a series resistor in the signal path if termination is needed, or (3) no resistor at all since TDO is typically actively driven *(reasoning)* - This connection should be corrected to match standard JTAG/XDP interface practices *(reasoning)* _{Upload a datasheet: [📤 J10](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/158-0004534)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component U40, pins 5, 6: SCL2 (pin 6) and SDA2 (pin 5) are connected to GPIO_I2C_SCL and GPIO_I2C_SDA respectively, which route to header JP1. However, no pullup resistors are present on these high-voltage side I2C signals, which are required for proper open-drain I2C operation.

• Pin 5 (SDA2) is connected to GPIO_I2C_SDA net, which routes to JP1 pin 15 (from schematic)
• Pin 6 (SCL2) is connected to GPIO_I2C_SCL net, which routes to JP1 pin 13 (from schematic)
• Pin 7 (VREF2) and pin 8 (EN) are both connected to net $20N1576, which connects through R812 (200K) to +3VSB (from schematic)
• No pullup resistors are present on GPIO_I2C_SDA or GPIO_I2C_SCL nets to +3VSB or any other high-voltage supply (from schematic)
• The low-voltage side pins 3 (SCL1) and 4 (SDA1) have proper pullup resistors R267 and R266 (10K) to +V1P8S (from schematic)
• Pin 5 is SDA2 (serial data, high-voltage side) and pin 6 is SCL2 (serial clock, high-voltage side) (from datasheet 4318-0010, page 4)
• Datasheet states: 'Translation on standard open-drain I2C bus is achieved by connecting pull-up resistors from SCL1 and SDA1 to VREF1 and from SCL2 and SDA2 to VDPU' (from datasheet 4318-0010, page 16)
• Typical application circuits in the datasheet show pullup resistors (RPU) on both SCL2 and SDA2 to the high-voltage supply (from datasheet 4318-0010, page 17)
• The datasheet application section emphasizes that pullup resistors are required for open-drain I2C operation (from datasheet 4318-0010, page 18)
• Without pullup resistors, the I2C bus cannot function properly as there is no mechanism to pull the lines high (reasoning)
• The presence of pullup resistors on the low-voltage side (R266, R267) indicates the designer understood this requirement, making the omission on the high-voltage side likely an oversight rather than intentional (reasoning)
• While it is possible that external devices connected via JP1 could provide pullup resistors, this is not documented in the schematic and creates an undocumented dependency on external hardware (reasoning)
• Best practice requires either: (1) including pullup resistors on this board (e.g., 10K from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB), or (2) adding a clear schematic note indicating that external pullup resistors are required (reasoning)
• The design as shown is incomplete and will not function without modification or external components (reasoning)

_{Replace a datasheet: 📤 U40}

[🚨 Error] **Component `U40`, pins `5, 6`: SCL2 (pin 6) and SDA2 (pin 5) are connected to GPIO_I2C_SCL and GPIO_I2C_SDA respectively, which route to header JP1. However, no pullup resistors are present on these high-voltage side I2C signals, which are required for proper open-drain I2C operation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.92" aspect-ratio="1.29" } - Pin 5 (SDA2) is connected to GPIO_I2C_SDA net, which routes to JP1 pin 15 *(from schematic)* - Pin 6 (SCL2) is connected to GPIO_I2C_SCL net, which routes to JP1 pin 13 *(from schematic)* - Pin 7 (VREF2) and pin 8 (EN) are both connected to net $20N1576, which connects through R812 (200K) to +3VSB *(from schematic)* - No pullup resistors are present on GPIO_I2C_SDA or GPIO_I2C_SCL nets to +3VSB or any other high-voltage supply *(from schematic)* - The low-voltage side pins 3 (SCL1) and 4 (SDA1) have proper pullup resistors R267 and R266 (10K) to +V1P8S *(from schematic)* - Pin 5 is SDA2 (serial data, high-voltage side) and pin 6 is SCL2 (serial clock, high-voltage side) *(from datasheet [4318-0010](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4>), page 4)* - Datasheet states: &#x27;Translation on standard open-drain I2C bus is achieved by connecting pull-up resistors from SCL1 and SDA1 to VREF1 and from SCL2 and SDA2 to VDPU&#x27; *(from datasheet [4318-0010](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=16>), page 16)* - Typical application circuits in the datasheet show pullup resistors (RPU) on both SCL2 and SDA2 to the high-voltage supply *(from datasheet [4318-0010](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17>), page 17)* - The datasheet application section emphasizes that pullup resistors are required for open-drain I2C operation *(from datasheet [4318-0010](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=18>), page 18)* - Without pullup resistors, the I2C bus cannot function properly as there is no mechanism to pull the lines high *(reasoning)* - The presence of pullup resistors on the low-voltage side (R266, R267) indicates the designer understood this requirement, making the omission on the high-voltage side likely an oversight rather than intentional *(reasoning)* - While it is possible that external devices connected via JP1 could provide pullup resistors, this is not documented in the schematic and creates an undocumented dependency on external hardware *(reasoning)* - Best practice requires either: (1) including pullup resistors on this board (e.g., 10K from GPIO_I2C_SCL and GPIO_I2C_SDA to +3VSB), or (2) adding a clear schematic note indicating that external pullup resistors are required *(reasoning)* - The design as shown is incomplete and will not function without modification or external components *(reasoning)* _{Replace a datasheet: [📤 U40](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4318-0010)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component U35, pin 4: Pin 4 (SLP_S5#) is connected to net SLP_S4_L. There is an explicit naming mismatch between the pin name (indicating an S5 sleep state signal) and the connected net (indicating an S4 sleep state signal). This connection should be verified as S4 and S5 are distinct ACPI power states.

• Pin 4 (SLP_S5#) is connected to net SLP_S4_L (from schematic)
• The pin name SLP_S5# explicitly indicates this pin expects an ACPI S5 (Soft Off) sleep state signal (reasoning)
• The connected net SLP_S4_L indicates an ACPI S4 (Suspend to Disk/Hibernate) sleep state signal (reasoning)
• In ACPI specifications, S4 and S5 are distinct power states: S4 allows the system to save context to disk and wake from various sources, while S5 is a soft-off state with limited wake sources (reasoning)
• Both the # suffix (pin name) and _L suffix (net name) indicate active-low signals, so the polarity is consistent (reasoning)
• Other pins on U35 show consistent naming between pin names and net names (e.g., PS_OUT# to PS_OUT_L), making this S5/S4 mismatch stand out (from schematic)
• While this connection could theoretically be intentional if the system design uses S4 to trigger S5 functionality or treats these states identically, such a design choice would typically be explicitly documented (reasoning)
• Without the NCT3012S-X datasheet to verify the intended function and requirements of pin 4, this naming mismatch should be flagged as a potential error requiring verification (reasoning)
• The explicit nature of the mismatch suggests either a connection error or a net naming inconsistency that should be corrected (reasoning)

_{Upload a datasheet: 📤 U35}

[🚨 Error] **Component `U35`, pin `4`: Pin 4 (SLP_S5#) is connected to net SLP_S4_L. There is an explicit naming mismatch between the pin name (indicating an S5 sleep state signal) and the connected net (indicating an S4 sleep state signal). This connection should be verified as S4 and S5 are distinct ACPI power states.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="18.08,38.61,25.58,46.11" aspect-ratio="1.29" } - Pin 4 (SLP_S5#) is connected to net SLP_S4_L *(from schematic)* - The pin name SLP_S5# explicitly indicates this pin expects an ACPI S5 (Soft Off) sleep state signal *(reasoning)* - The connected net SLP_S4_L indicates an ACPI S4 (Suspend to Disk/Hibernate) sleep state signal *(reasoning)* - In ACPI specifications, S4 and S5 are distinct power states: S4 allows the system to save context to disk and wake from various sources, while S5 is a soft-off state with limited wake sources *(reasoning)* - Both the # suffix (pin name) and _L suffix (net name) indicate active-low signals, so the polarity is consistent *(reasoning)* - Other pins on U35 show consistent naming between pin names and net names (e.g., PS_OUT# to PS_OUT_L), making this S5/S4 mismatch stand out *(from schematic)* - While this connection could theoretically be intentional if the system design uses S4 to trigger S5 functionality or treats these states identically, such a design choice would typically be explicitly documented *(reasoning)* - Without the NCT3012S-X datasheet to verify the intended function and requirements of pin 4, this naming mismatch should be flagged as a potential error requiring verification *(reasoning)* - The explicit nature of the mismatch suggests either a connection error or a net naming inconsistency that should be corrected *(reasoning)* _{Upload a datasheet: [📤 U35](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NCT3012S-X)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component Q4, pins B, E: Package pinout mismatch: The schematic uses package SOT23_EBC, but the MMBT3904 datasheet specifies a B-E-C physical pinout. This mismatch will cause the base and emitter pins to be swapped on the physical PCB, preventing correct transistor operation.

• Pin B (BASE) is connected to net S5_ENBL in the schematic (from schematic)
• Pin E (EMITTER) is connected to net GND in the schematic (from schematic)
• The component specifies package SOT23_EBC in the PKG_TYPE attribute (from schematic)
• By convention observed in other components (e.g., SOT23_GSD for 2N7002K MOSFETs where G-S-D corresponds to physical pins 1-2-3), the package name SOT23_EBC indicates physical pin mapping: Pin 1=E, Pin 2=B, Pin 3=C (reasoning)
• The MMBT3904 datasheet shows the actual SOT-23 pinout as: Pin 1=Base, Pin 2=Emitter, Pin 3=Collector (from datasheet MMBT3904, page 3)
• With package SOT23_EBC, the footprint will map logical pin E to physical pin 1 and logical pin B to physical pin 2 (reasoning)
• When assembled on the PCB, physical pin 1 (Base per datasheet) will connect to the GND net (assigned to logical E), and physical pin 2 (Emitter per datasheet) will connect to S5_ENBL net (assigned to logical B) (reasoning)
• This pin swap will reverse-bias the base-emitter junction and prevent the transistor from functioning as intended (reasoning)
• The package should be changed to SOT23_BEC to match the MMBT3904 datasheet pinout, or a different transistor with E-B-C pinout should be selected (reasoning)

_{Replace a datasheet: 📤 Q4}

[🚨 Error] **Component `Q4`, pins `B, E`: Package pinout mismatch: The schematic uses package SOT23_EBC, but the MMBT3904 datasheet specifies a B-E-C physical pinout. This mismatch will cause the base and emitter pins to be swapped on the physical PCB, preventing correct transistor operation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="13.08,80.36,21.49,88.44" aspect-ratio="1.29" } - Pin B (BASE) is connected to net S5_ENBL in the schematic *(from schematic)* - Pin E (EMITTER) is connected to net GND in the schematic *(from schematic)* - The component specifies package SOT23_EBC in the PKG_TYPE attribute *(from schematic)* - By convention observed in other components (e.g., SOT23_GSD for 2N7002K MOSFETs where G-S-D corresponds to physical pins 1-2-3), the package name SOT23_EBC indicates physical pin mapping: Pin 1=E, Pin 2=B, Pin 3=C *(reasoning)* - The MMBT3904 datasheet shows the actual SOT-23 pinout as: Pin 1=Base, Pin 2=Emitter, Pin 3=Collector *(from datasheet [MMBT3904](<https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1#page=3>), page 3)* - With package SOT23_EBC, the footprint will map logical pin E to physical pin 1 and logical pin B to physical pin 2 *(reasoning)* - When assembled on the PCB, physical pin 1 (Base per datasheet) will connect to the GND net (assigned to logical E), and physical pin 2 (Emitter per datasheet) will connect to S5_ENBL net (assigned to logical B) *(reasoning)* - This pin swap will reverse-bias the base-emitter junction and prevent the transistor from functioning as intended *(reasoning)* - The package should be changed to SOT23_BEC to match the MMBT3904 datasheet pinout, or a different transistor with E-B-C pinout should be selected *(reasoning)* _{Replace a datasheet: [📤 Q4](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/MMBT3904)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[⚠️ Warning] Component R849, pins 1, 2: 0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously.

• Pin 1 is connected to net +VCC (from schematic)
• Pin 2 is connected to net $23N5607 (from schematic)
• Net $23N5607 connects to U25 pin 48 (EN) (from schematic)
• R849 is a 0Ω jumper (part number 1121-0001) (from schematic)
• This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled (reasoning)
• R851 (10KΩ) is also populated on net $23N5607, connecting to GND (from schematic)
• With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND (reasoning)
• This creates unnecessary power dissipation in R851 (reasoning)
• Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω (reasoning)
• The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state (reasoning)
• Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path (reasoning)

All affected pins

Component R849, pins `1, 2`: 0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously.

• Pin 1 is connected to net +VCC (from schematic)
• Pin 2 is connected to net $23N5607 (from schematic)
• Net $23N5607 connects to U25 pin 48 (EN) (from schematic)
• R849 is a 0Ω jumper (part number 1121-0001) (from schematic)
• This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled (reasoning)
• R851 (10KΩ) is also populated on net $23N5607, connecting to GND (from schematic)
• With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND (reasoning)
• This creates unnecessary power dissipation in R851 (reasoning)
• Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω (reasoning)
• The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state (reasoning)
• Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path (reasoning)

Component R851, pins `1, 2`: 10KΩ pull-down resistor on EN pin of U25. With R849 (0Ω jumper to +VCC) also populated, creates wasteful current path drawing VCC/10KΩ continuously.

• Pin 1 is connected to net $23N5607 (from schematic)
• Pin 2 is connected to net GND (from schematic)
• Net $23N5607 connects to U25 pin 48 (EN) (from schematic)
• R851 is a 10KΩ resistor (part number 1120-0011) (from schematic)
• R849 (0Ω) connects +VCC to the same net $23N5607 (from schematic)
• This creates a direct current path from +VCC through R849 (0Ω) to the EN pin, then through R851 (10KΩ) to GND (reasoning)
• Continuous current draw of VCC/10KΩ results in unnecessary power dissipation (reasoning)
• The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at pulling the pin low (reasoning)
• R851 should be DNI when R849 is populated to avoid the wasteful current path (reasoning)
• If the intent is to have the regulator always enabled, only R849 should be populated; if the intent is to disable or allow external control, only R851 should be populated (reasoning)

[⚠️ Warning] **Component `R849`, pins `1, 2`: 0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,36.25,40.57,45.52" aspect-ratio="1.29" } - Pin 1 is connected to net +VCC *(from schematic)* - Pin 2 is connected to net $23N5607 *(from schematic)* - Net $23N5607 connects to U25 pin 48 (EN) *(from schematic)* - R849 is a 0Ω jumper (part number 1121-0001) *(from schematic)* - This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled *(reasoning)* - R851 (10KΩ) is also populated on net $23N5607, connecting to GND *(from schematic)* - With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND *(reasoning)* - This creates unnecessary power dissipation in R851 *(reasoning)* - Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω *(reasoning)* - The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state *(reasoning)* - Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>R849</code>, pins `1, 2`: 0Ω jumper connects +VCC to EN pin of U25 (NCP81109GMNTXG). With R851 also populated as 10KΩ pull-down, creates wasteful current path from +VCC to GND drawing VCC/10KΩ continuously.</summary> - Pin 1 is connected to net +VCC *(from schematic)* - Pin 2 is connected to net $23N5607 *(from schematic)* - Net $23N5607 connects to U25 pin 48 (EN) *(from schematic)* - R849 is a 0Ω jumper (part number 1121-0001) *(from schematic)* - This configuration connects +VCC directly to the EN pin, forcing the regulator to be always enabled *(reasoning)* - R851 (10KΩ) is also populated on net $23N5607, connecting to GND *(from schematic)* - With R849 as 0Ω and R851 as 10KΩ to GND, a continuous current of VCC/10KΩ flows from +VCC through R849 to the EN pin and then through R851 to GND *(reasoning)* - This creates unnecessary power dissipation in R851 *(reasoning)* - Typical enable pin circuits use either a pull-up resistor or a pull-down resistor, not both simultaneously with one being 0Ω *(reasoning)* - The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at controlling the pin state *(reasoning)* - Recommend making R851 DNI when R849 is populated to eliminate the wasteful current path *(reasoning)* </details> <details> <summary>Component <code>R851</code>, pins `1, 2`: 10KΩ pull-down resistor on EN pin of U25. With R849 (0Ω jumper to +VCC) also populated, creates wasteful current path drawing VCC/10KΩ continuously.</summary> - Pin 1 is connected to net $23N5607 *(from schematic)* - Pin 2 is connected to net GND *(from schematic)* - Net $23N5607 connects to U25 pin 48 (EN) *(from schematic)* - R851 is a 10KΩ resistor (part number 1120-0011) *(from schematic)* - R849 (0Ω) connects +VCC to the same net $23N5607 *(from schematic)* - This creates a direct current path from +VCC through R849 (0Ω) to the EN pin, then through R851 (10KΩ) to GND *(reasoning)* - Continuous current draw of VCC/10KΩ results in unnecessary power dissipation *(reasoning)* - The EN pin voltage would be approximately +VCC due to R849 being 0Ω, making R851 ineffective at pulling the pin low *(reasoning)* - R851 should be DNI when R849 is populated to avoid the wasteful current path *(reasoning)* - If the intent is to have the regulator always enabled, only R849 should be populated; if the intent is to disable or allow external control, only R851 should be populated *(reasoning)* </details> </details>

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component U26, pin 10: SW1 is isolated from the main switch node and only connected to the bootstrap capacitor return path. This configuration prevents phase 1 from contributing to the output.

• Pin 10 (SW1) is connected to net $24N3595 (from schematic)
• Bootstrap capacitor C186 (0.22µF) connects between $24N3596 and $24N3595 (SW1) (from schematic)
• Bootstrap resistor R228 (2.20Ω) connects between $24N3593 (BST, pin 8) and $24N3596 (from schematic)
• Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW (from schematic)
• Net VGFX-SW connects through inductor L4 to the output +VGFX (from schematic)
• There is no connection between net $24N3595 (SW1) and net VGFX-SW (from schematic)
• In a multiphase buck converter, all active switch nodes must be connected together to share current and drive the output (reasoning)
• The bootstrap circuit (R228, C186) connected to SW1 suggests phase 1 was intended to be active (reasoning)
• For the bootstrap circuit to function, SW1 must be switching, which requires it to be part of an active phase (reasoning)
• The isolation of SW1 from VGFX-SW prevents phase 1 from contributing to the output and renders the bootstrap circuit non-functional (reasoning)
• If phase 1 is intentionally disabled, the bootstrap components (R228, C186) should be marked DNP (reasoning)
• The correct configuration requires SW1 to be connected to VGFX-SW along with the other switch nodes (reasoning)

_{Upload a datasheet: 📤 U26}

[🚨 Error] **Component `U26`, pin `10`: SW1 is isolated from the main switch node and only connected to the bootstrap capacitor return path. This configuration prevents phase 1 from contributing to the output.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="37.39,41.84,44.89,49.34" aspect-ratio="1.29" } - Pin 10 (SW1) is connected to net $24N3595 *(from schematic)* - Bootstrap capacitor C186 (0.22µF) connects between $24N3596 and $24N3595 (SW1) *(from schematic)* - Bootstrap resistor R228 (2.20Ω) connects between $24N3593 (BST, pin 8) and $24N3596 *(from schematic)* - Pins 18, 25-29 (SW2-SW7) are all connected to net VGFX-SW *(from schematic)* - Net VGFX-SW connects through inductor L4 to the output +VGFX *(from schematic)* - There is no connection between net $24N3595 (SW1) and net VGFX-SW *(from schematic)* - In a multiphase buck converter, all active switch nodes must be connected together to share current and drive the output *(reasoning)* - The bootstrap circuit (R228, C186) connected to SW1 suggests phase 1 was intended to be active *(reasoning)* - For the bootstrap circuit to function, SW1 must be switching, which requires it to be part of an active phase *(reasoning)* - The isolation of SW1 from VGFX-SW prevents phase 1 from contributing to the output and renders the bootstrap circuit non-functional *(reasoning)* - If phase 1 is intentionally disabled, the bootstrap components (R228, C186) should be marked DNP *(reasoning)* - The correct configuration requires SW1 to be connected to VGFX-SW along with the other switch nodes *(reasoning)* _{Upload a datasheet: [📤 U26](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/NCP81109GMNTXG)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component U41, pin 22: BOOT pin is connected to the bootstrap circuit through a 4.7-ohm resistor (R298) and 0.1µF capacitor (C309) to PHASE. However, the bootstrap capacitor value is significantly undersized compared to the 1µF datasheet recommendation, which may cause insufficient gate drive voltage.

• Pin 22 (BOOT) is connected to net $25N771 (from schematic)
• DDR_BST connects to C309 pin 2 (0.1µF capacitor) (from schematic)
• C309 pin 1 connects to DDR_PHASE (PHASE pin) (from schematic)
• BOOT is the boost flying capacitor connection for VDDQ per the datasheet (from datasheet 4124-0013)
• The datasheet recommends a 1µF flying bootstrap capacitor between BOOT and PHASE pins (from datasheet 4124-0013)
• The schematic uses C309 (0.1µF) as the bootstrap capacitor, which is 10x smaller than recommended (reasoning)
• The datasheet mentions adding a resistor in series with BOOT to reduce gate-drain coupling in high current applications (from datasheet 4124-0013)
• The 4.7Ω resistor R298 is likely for reducing gate-drain coupling (reasoning)
• An undersized bootstrap capacitor may result in insufficient gate drive voltage, increased switching losses, or potential shoot-through issues (reasoning)
• The bootstrap capacitor should be increased to 1µF as recommended by the datasheet (reasoning)

_{Replace a datasheet: 📤 U41}

[🚨 Error] **Component `U41`, pin `22`: BOOT pin is connected to the bootstrap circuit through a 4.7-ohm resistor (R298) and 0.1µF capacitor (C309) to PHASE. However, the bootstrap capacitor value is significantly undersized compared to the 1µF datasheet recommendation, which may cause insufficient gate drive voltage.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="45.80,38.02,53.30,45.52" aspect-ratio="1.29" } - Pin 22 (BOOT) is connected to net $25N771 *(from schematic)* - DDR_BST connects to C309 pin 2 (0.1µF capacitor) *(from schematic)* - C309 pin 1 connects to DDR_PHASE (PHASE pin) *(from schematic)* - BOOT is the boost flying capacitor connection for VDDQ per the datasheet *(from datasheet [4124-0013](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P>))* - The datasheet recommends a 1µF flying bootstrap capacitor between BOOT and PHASE pins *(from datasheet [4124-0013](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P>))* - The schematic uses C309 (0.1µF) as the bootstrap capacitor, which is 10x smaller than recommended *(reasoning)* - The datasheet mentions adding a resistor in series with BOOT to reduce gate-drain coupling in high current applications *(from datasheet [4124-0013](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P>))* - The 4.7Ω resistor R298 is likely for reducing gate-drain coupling *(reasoning)* - An undersized bootstrap capacitor may result in insufficient gate drive voltage, increased switching losses, or potential shoot-through issues *(reasoning)* - The bootstrap capacitor should be increased to 1µF as recommended by the datasheet *(reasoning)* _{Replace a datasheet: [📤 U41](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/4124-0013)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 21:42:45 +00:00

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[🚨 Error] Component R816, pin 2: Connected to U41 pin 12 (TON) to set switching frequency. However, the resistor value of 464K does not match the design specification of 806K stated in the schematic notes, which would result in incorrect switching frequency (504 kHz instead of the intended 285 kHz).

• Pin 2 is connected to net $25N1081, which connects to U41 pin 12 (TON) (from schematic)
• The TON pin sets the switching frequency of the RT8207M controller via an external resistor (reasoning)
• A schematic note states 'Rton=806K , F=285KHz' indicating the design intent for switching frequency (from schematic)
• A schematic note provides the formula 'F= (Vin - 0.5) / 3.85pVinRton' for calculating switching frequency (from schematic)
• R816 is specified as 464K (part number 1120-0149) (from schematic)
• Using the provided formula with Vin=5V and Rton=464K yields F = (5-0.5)/(3.85e-125464000) = 503.8 kHz (reasoning)
• Using the provided formula with Vin=5V and Rton=806K yields F = (5-0.5)/(3.85e-125806000) = 290 kHz, which matches the design specification of 285 kHz (reasoning)
• The resistor value of 464K does not match the design specification of 806K, resulting in a switching frequency approximately 1.74x higher than intended (reasoning)
• R816 should be changed to 806K (or nearest standard value) to achieve the intended 285 kHz switching frequency (reasoning)

_{Upload a datasheet: 📤 R816}

[🚨 Error] **Component `R816`, pin `2`: Connected to U41 pin 12 (TON) to set switching frequency. However, the resistor value of 464K does not match the design specification of 806K stated in the schematic notes, which would result in incorrect switching frequency (504 kHz instead of the intended 285 kHz).** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...598938c2e9102fa92d39d27919ce3c273c6b761a" pr="194" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,36.84,35.12,44.34" aspect-ratio="1.29" } - Pin 2 is connected to net $25N1081, which connects to U41 pin 12 (TON) *(from schematic)* - The TON pin sets the switching frequency of the RT8207M controller via an external resistor *(reasoning)* - A schematic note states &#x27;Rton=806K , F=285KHz&#x27; indicating the design intent for switching frequency *(from schematic)* - A schematic note provides the formula &#x27;F= (Vin - 0.5) / 3.85p*Vin*Rton&#x27; for calculating switching frequency *(from schematic)* - R816 is specified as 464K (part number 1120-0149) *(from schematic)* - Using the provided formula with Vin=5V and Rton=464K yields F = (5-0.5)/(3.85e-12*5*464000) = 503.8 kHz *(reasoning)* - Using the provided formula with Vin=5V and Rton=806K yields F = (5-0.5)/(3.85e-12*5*806000) = 290 kHz, which matches the design specification of 285 kHz *(reasoning)* - The resistor value of 464K does not match the design specification of 806K, resulting in a switching frequency approximately 1.74x higher than intended *(reasoning)* - R816 should be changed to 806K (or nearest standard value) to achieve the intended 285 kHz switching frequency *(reasoning)* _{Upload a datasheet: [📤 R816](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/e9a05055/.allspice/datasheets/1120-0149)}

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Reference: NoIndexTests/E2E-Turbot-BOMGEN#194

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