E2E @ 24f21021 - manual run: su/alternate-formats verification @ 24f2102 (3x per repo) #195

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shrikanthup wants to merge 2 commits from refs/pull/195/head into main

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Conversation 2 Commits 2 Changes 7 +504 -81

shrikanthup commented 2026-05-27 18:50:46 +00:00 (Migrated from staging.allspice.dev)

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Source: manual run: su/alternate-formats verification @ 24f2102 (3x per repo)
Ref: 24f210213d4b98412292018488d65ea5fa571e4f
Mode: e2e
Cache: enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache)
Cleanup: auto-closed after 7 days

Resolved config

{
  "dump_analysis_dir": "debug_dump",
  "libraries": [
    {
      "ipn_column": "IPN",
      "mpn_column": "MPN",
      "path": ".allspice/library.csv",
      "type": "csv"
    },
    {
      "digikey_client_id_env": "DIGIKEY_CLIENT_ID",
      "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET",
      "type": "digikey"
    }
  ]
}

Triggered at 2026-05-27T18:50:44.323441Z. Branch 5b0c851c will be deleted on cleanup.

**Source:** manual run: su/alternate-formats verification @ 24f2102 (3x per repo) **Ref:** [`24f210213d4b98412292018488d65ea5fa571e4f`](https://github.com/AllSpiceIO/connections-checker/tree/24f210213d4b98412292018488d65ea5fa571e4f) **Mode:** e2e **Cache:** enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache) **Cleanup:** auto-closed after 7 days <details> <summary>Resolved config</summary> ```json { "dump_analysis_dir": "debug_dump", "libraries": [ { "ipn_column": "IPN", "mpn_column": "MPN", "path": ".allspice/library.csv", "type": "csv" }, { "digikey_client_id_env": "DIGIKEY_CLIENT_ID", "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET", "type": "digikey" } ] } ``` </details> Triggered at 2026-05-27T18:50:44.323441Z. Branch `5b0c851c` will be deleted on cleanup.

AllSpiceAlice commented 2026-05-27 20:12:15 +00:00 (Migrated from staging.allspice.dev)

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DRCY has reviewed this Design Review, and there should be a review posted below.

DRCY has reviewed this Design Review, and there should be a review posted below.

AllSpiceAlice (Migrated from staging.allspice.dev) reviewed 2026-05-27 22:33:44 +00:00

AllSpiceAlice (Migrated from staging.allspice.dev) left a comment

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DRCY Connections Checker Review

DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 398 component(s) to review, and found 13 potential issue(s) in 16 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
AK12	DDI0_RCOMP_P	DDI_RCOMP_N	❌	DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net, while pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ negative per datasheet) connects to DDI_RCOMP_P net. These connections should be reversed. Pin AK12 is labeled DDI0_RCOMP_P in the component and datasheet, indicating the positive side of the DDI compensation resistor pair (from datasheet 140-0004628, page 213) Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ in the component and datasheet, where the overline notation indicates this is the negative/complement signal (DDI0_RCOMP_N) (from datasheet 140-0004628, page 213) In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic) In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic) Resistor R217 (402 ohms) is connected between nets DDI_RCOMP_N and DDI_RCOMP_P, serving as the DDI compensation resistor (from schematic) The connections are reversed: the positive pin (AK12) connects to the negative net, and the negative pin (AK13) connects to the positive net (reasoning) To correct this error, the net connections should be swapped so that AK12 connects to DDI_RCOMP_P and AK13 connects to DDI_RCOMP_N (reasoning)
AK13	~DDI0_RCOMP	DDI_RCOMP_P	❌	DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net, while pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ negative per datasheet) connects to DDI_RCOMP_P net. These connections should be reversed. Pin AK12 is labeled DDI0_RCOMP_P in the component and datasheet, indicating the positive side of the DDI compensation resistor pair (from datasheet 140-0004628, page 213) Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ in the component and datasheet, where the overline notation indicates this is the negative/complement signal (DDI0_RCOMP_N) (from datasheet 140-0004628, page 213) In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic) In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic) Resistor R217 (402 ohms) is connected between nets DDI_RCOMP_N and DDI_RCOMP_P, serving as the DDI compensation resistor (from schematic) The connections are reversed: the positive pin (AK12) connects to the negative net, and the negative pin (AK13) connects to the positive net (reasoning) To correct this error, the net connections should be swapped so that AK12 connects to DDI_RCOMP_P and AK13 connects to DDI_RCOMP_N (reasoning)
A29	RESERVED_A29	GPIO_NC13	✅	RESERVED_A29 pin is connected to GPIO_NC13 net with a 10K pull-down resistor (R102) to ground. This is an acceptable configuration for an unused reserved GPIO pin.
B26	DDI0_BKLTCTL		✅	DDI0_BKLTCTL backlight control is unconnected, which may be acceptable if backlight control is handled externally.
B28	DDI0_VDDEN		✅	DDI0_VDDEN display power enable is unconnected, which may be acceptable if display power is controlled externally.
B30	GPIO_S0_NC12	$3N566	✅	GPIO_S0_NC12 is connected to test point TP15, which is acceptable for debug access.
C26	DDI0_DDCDATA	HDMI_DDCDAT	✅	DDI0_DDCDATA is correctly connected to HDMI_DDCDAT for HDMI DDC communication.
C27	DDI0_BKLTEN		✅	DDI0_BKLTEN backlight enable is unconnected, which is acceptable for HDMI displays.
C28	DDI0_DDCCLK	HDMI_DDCCLK	✅	DDI0_DDCCLK is correctly connected to HDMI_DDCCLK for HDMI DDC communication.
D27	DDI0_HPD	HDMI_HPD_B	✅	DDI0_HPD is correctly connected to HDMI_HPD_B through inverter U39 for hot plug detection.
G30	DDI1_DDCCLK	GND	✅	DDI1_DDCCLK is intentionally grounded to disable the DDI1 port per the 'Bay Trail-M Remove eDP Port' note.
J30	DDI1_BKLTEN		✅	DDI1_BKLTEN backlight enable is unconnected, consistent with DDI1 port being disabled.
K30	DDI1_HPD	GND	✅	DDI1_HPD is intentionally grounded to disable the DDI1 port per the 'Bay Trail-M Remove eDP Port' note.
M30	DDI1_BKLTCTL		✅	DDI1_BKLTCTL backlight control is unconnected, consistent with DDI1 port being disabled.
N30	DDI1_VDDEN		✅	DDI1_VDDEN display power enable is unconnected, consistent with DDI1 port being disabled.
P14	RESERVED_P14	MCSI_RCOMP	✅	RESERVED_P14 is connected to MCSI_RCOMP with 150-ohm compensation resistor R213 for MIPI CSI interface.
P30	DDI1_DDCDATA	DDI1_DDCDAT	✅	DDI1_DDCDATA is connected with 2.2K pull-down resistor R257, consistent with disabling the DDI1 port.
BA1	VGA_GREEN		✅	VGA_GREEN DAC output is unconnected, which is acceptable if VGA output is not used.
BA3	VGA_RED		✅	VGA_RED DAC output is unconnected, which is acceptable if VGA output is not used.
AB12	RESERVED_AB12		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AB13	RESERVED_AB13		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AB14	RESERVED_AB14		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AB2	RESERVED_AB2		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AB3	RESERVED_AB3		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AB7	RESERVED_AB7		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AB9	RESERVED_AB9		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AD4	RESERVED_AD4		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AD6	RESERVED_AD6		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AF13	RESERVED_AF13		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AF14	RESERVED_AF14		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AH13	RESERVED_AH13		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AH14	RESERVED_AH14		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AM13	RESERVED_AM13		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AM14	RESERVED_AM14		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
C29	RESERVED_C29		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
C30	RESERVED_C30		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
D28	RESERVED_D28		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
D32	RESERVED_D32		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
D34	RESERVED_D34		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
F28	RESERVED_F28		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
F32	RESERVED_F32		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
F34	RESERVED_F34		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
J28	RESERVED_J28		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
J34	RESERVED_J34		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
K28	RESERVED_K28		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
K34	RESERVED_K34		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
M32	RESERVED_M32		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
N32	RESERVED_N32		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
R1	RESERVED_R1		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
R3	RESERVED_R3		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T10	RESERVED_T10		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T12	RESERVED_T12		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T13	RESERVED_T13		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T14	RESERVED_T14		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T2	RESERVED_T2		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T3	RESERVED_T3		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T4	RESERVED_T4		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T6	RESERVED_T6		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T7	RESERVED_T7		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
T9	RESERVED_T9		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V10	RESERVED_V10		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V13	RESERVED_V13		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V14	RESERVED_V14		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V2	RESERVED_V2		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V3	RESERVED_V3		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V4	RESERVED_V4		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V6	RESERVED_V6		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
V9	RESERVED_V9		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
W1	RESERVED_W1		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
W3	RESERVED_W3		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
Y12	RESERVED_Y12		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
Y13	RESERVED_Y13		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
Y2	RESERVED_Y2		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
Y3	RESERVED_Y3		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
Y4	RESERVED_Y4		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
Y6	RESERVED_Y6		✅	Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used.
AC1	DDI1_TXN_3		✅	DDI1_TXN_3 transmit lane 3 negative is unconnected, consistent with DDI1 port being disabled.
AC3	DDI1_TXP_3		✅	DDI1_TXP_3 transmit lane 3 positive is unconnected, consistent with DDI1 port being disabled.
BC1	VGA_DDCCLK	CRT_CLK	✅	VGA_DDCCLK is correctly connected to CRT_CLK with 150-ohm termination resistor R39.
AD2	DDI1_TXN_2		✅	DDI1_TXN_2 transmit lane 2 negative is unconnected, consistent with DDI1 port being disabled.
BC2	VGA_DDCDATA	CRT_DAT	✅	VGA_DDCDATA is correctly connected to CRT_DAT with 150-ohm termination resistor R38.
AD3	DDI1_TXP_2		✅	DDI1_TXP_2 transmit lane 2 positive is unconnected, consistent with DDI1 port being disabled.
BD2	VGA_HSYNC		✅	VGA_HSYNC horizontal sync is unconnected, which is acceptable if VGA output is not used.
AF2	DDI1_TXN_1		✅	DDI1_TXN_1 transmit lane 1 negative is unconnected, consistent with DDI1 port being disabled.
AF3	DDI1_TXP_1		✅	DDI1_TXP_1 transmit lane 1 positive is unconnected, consistent with DDI1 port being disabled.
AG1	DDI1_TXN_0		✅	DDI1_TXN_0 transmit lane 0 negative is unconnected, consistent with DDI1 port being disabled.
BF2	VGA_VSYNC		✅	VGA_VSYNC vertical sync is unconnected, which is acceptable if VGA output is not used.
AG3	DDI1_TXP_0		✅	DDI1_TXP_0 transmit lane 0 positive is unconnected, consistent with DDI1 port being disabled.
AH2	RESERVED_VSS3	$3N554	✅	RESERVED_VSS3 pin is correctly connected to ground through 0-ohm resistor R43.
AH3	RESERVED_VSS2	$3N552	✅	RESERVED_VSS2 pin is correctly connected to ground through 0-ohm resistor R46.
AK2	DDI1_AUXN		✅	DDI1_AUXN auxiliary channel negative is unconnected, consistent with DDI1 port being disabled.
AK3	DDI1_AUXP		✅	DDI1_AUXP auxiliary channel positive is unconnected, consistent with DDI1 port being disabled.
AL1	DDI0_AUXN		✅	DDI0_AUXN auxiliary channel negative is unconnected, which may be acceptable if DisplayPort AUX channel is not used.
AL3	DDI0_AUXP		✅	DDI0_AUXP auxiliary channel positive is unconnected, which may be acceptable if DisplayPort AUX channel is not used.
AM2	RESERVED_VSS1	$3N589	✅	RESERVED_VSS1 pin is correctly connected to ground through 0-ohm resistor R41.
AM3	RESERVED_VSS0	$3N579	✅	RESERVED_VSS0 pin is correctly connected to ground through 0-ohm resistor R42.
AP2	DDI0_TXN_3	HDMI_CLK_DN	✅	DDI0_TXN_3 is correctly connected to HDMI_CLK_DN for HDMI clock differential pair negative.
AP3	DDI0_TXP_3	HDMI_CLK_DP	✅	DDI0_TXP_3 is correctly connected to HDMI_CLK_DP for HDMI clock differential pair positive.
AR1	DDI0_TXN_2	HDMI_TX0_DN	✅	DDI0_TXN_2 is correctly connected to HDMI_TX0_DN for HDMI data lane 0 negative.
AR3	DDI0_TXP_2	HDMI_TX0_DP	✅	DDI0_TXP_2 is correctly connected to HDMI_TX0_DP for HDMI data lane 0 positive.
AT2	DDI0_TXP_1	HDMI_TX1_DP	✅	DDI0_TXP_1 is correctly connected to HDMI_TX1_DP for HDMI data lane 1 positive.
AT3	DDI0_TXN_1	HDMI_TX1_DN	✅	DDI0_TXN_1 is correctly connected to HDMI_TX1_DN for HDMI data lane 1 negative.
AV2	DDI0_TXN_0	HDMI_TX2_DN	✅	DDI0_TXN_0 is correctly connected to HDMI_TX2_DN for HDMI data lane 2 negative.
AV3	DDI0_TXP_0	HDMI_TX2_DP	✅	DDI0_TXP_0 is correctly connected to HDMI_TX2_DP for HDMI data lane 2 positive.
AW1	VGA_IREF	$3N548	✅	VGA_IREF is correctly connected to 357-ohm reference resistor R40 to set VGA DAC output current.
AY2	VGA_BLUE		✅	VGA_BLUE DAC output is unconnected, which is acceptable if VGA output is not used.
AY3	VGA_IRTN	GND	✅	VGA_IRTN is correctly connected to ground as the DAC return current path.

U39 - SN74LVC1G14DCKR ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin is not connected in schematic. Datasheet states it should be soldered to the board but can be left electrically unconnected.
2	A	HDMI_HPD	✅	Input pin A is connected to HDMI_HPD signal from HDMI connector. This is correct for buffering the hot plug detect signal.
3	GND	GND	✅	GND pin is correctly connected to ground plane.
4	Y	HDMI_HPD_B	✅	Output pin Y is connected to HDMI_HPD_B which goes to CPU1 DDI0_HPD pin. This provides an inverted and buffered HPD signal to the processor.
5	VCC	+V1P8S	✅	VCC pin is connected to +V1P8S (1.8V) supply with nearby bypass capacitor C375 (0.1µF). This is correct per datasheet recommendations.

R40 - 357R ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$3N548	✅	357-ohm resistor connected between CPU1 VGA_IREF pin and ground to set the VGA DAC reference current.
2	2	GND	✅	357-ohm resistor connected between CPU1 VGA_IREF pin and ground to set the VGA DAC reference current.

R217 - 402R ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI_RCOMP_N	✅	402-ohm resistor correctly connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming the compensation resistor network for the display interface. The resistor itself is properly placed between the RCOMP differential pair. Note that there is an upstream issue at CPU1 pins AK12 and AK13 where the net connections are swapped, but since R217 is a symmetric passive component, this does not affect its electrical function.
2	2	DDI_RCOMP_P	✅	402-ohm resistor correctly connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming the compensation resistor network for the display interface. The resistor itself is properly placed between the RCOMP differential pair. Note that there is an upstream issue at CPU1 pins AK12 and AK13 where the net connections are swapped, but since R217 is a symmetric passive component, this does not affect its electrical function.

R213 - 150R ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCSI_RCOMP	✅	150-ohm resistor connected between MCSI_RCOMP net and ground. This provides impedance compensation for the MIPI CSI camera interface on CPU1 pin P14.
2	2	GND	✅	150-ohm resistor connected between MCSI_RCOMP net and ground. This provides impedance compensation for the MIPI CSI camera interface on CPU1 pin P14.

R257 - 2K20 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI1_DDCDAT	✅	Resistor pin 1 is connected to DDI1_DDCDAT, providing pull-down for the disabled DDI1 port.
2	2	GND	✅	Resistor pin 2 is correctly connected to ground to complete the pull-down function.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
C24	~PROCHOT	VR_HOT_L	✅	Processor hot signal, correctly pulled up with 73.2 ohm resistor.
N34	RESERVED_N34		✅	Reserved pin, correctly left unconnected.
P34	RESERVED_P34		✅	Reserved pin, correctly left unconnected.
BA12	SATA_GP0	SATA_GP0	✅	SATA general purpose signal 0, correctly pulled down with 10K resistor.
BA16	SATA_RXN_1	SATA1_RXN	✅	SATA port 1 receive negative signal, correctly AC coupled to mSATA interface.
BA18	SD2_CLK		✅	SD2 clock signal, left unconnected as SD2 interface is unused.
BA20	SD2_D2		✅	SD2 data bit 2 signal, left unconnected as SD2 interface is unused.
BA24	~MMC1_RST		✅	MMC1 reset signal, left unconnected as MMC1 interface is unused.
BA26	SD3_D3	SD3_D3	✅	SD3 data bit 3 signal, correctly connected to SD card interface.
BA30	LPE_I2S2_FRM	LPE_I2S_FRM	✅	I2S frame sync signal, correctly connected with DNI pull-up resistor.
BB3	RESERVED_BB3		✅	Reserved pin, correctly left unconnected.
BB4	RESERVED_BB4		✅	Reserved pin, correctly left unconnected.
BB5	RESERVED_VSS6	RESERVED_VSS6	✅	Reserved VSS pin, correctly connected to ground through 0 ohm resistor.
BB7	RESERVED_VSS7	RESERVED_VSS7	✅	Reserved VSS pin, correctly connected to ground through 0 ohm resistor.
BB10	RESERVED_VSS4	ICLK_SATA_TERMP	✅	Reserved VSS pin used for SATA termination, correctly connected to ground through 0 ohm resistor.
BC10	RESERVED_VSS5	ICLK_SATA_TERMN	✅	Reserved VSS pin used for SATA termination, correctly connected to ground through 0 ohm resistor.
BC18	SD2_CMD		✅	SD2 command signal, left unconnected as SD2 interface is unused.
BC24	SD3_CD#	SD3_CD#	✅	SD3 card detect and write protect pins are tied together via 0 ohm resistor. This is unusual and may not work correctly with all SD cards, but may be intentional for Bay Trail-I variant.
BD5	SD3_WP_BD5	SD3_WP	✅	SD3 card detect and write protect pins are tied together via 0 ohm resistor. This is unusual and may not work correctly with all SD cards, but may be intentional for Bay Trail-I variant.
BC30	LPE_I2S2_DATAOUT	LPE_I2S_DATOUT	✅	I2S data output signal, correctly connected with DNI pull-down and series resistor.
BD7	~PCIE_CLKREQ_1	CLKREQ1_B	✅	PCIe clock request 1 signal, correctly pulled up with 10K resistor.
BD10	SATA_TXP1	SATA1_TXP	✅	SATA port 1 transmit positive signal, correctly AC coupled to mSATA interface.
BD18	~SD2_D3_CD		✅	SD2 data bit 3 / card detect signal, left unconnected as SD2 interface is unused.
BD20	SD2_D1		✅	SD2 data bit 1 signal, left unconnected as SD2 interface is unused.
BD22	~SD3_PWREN	/SD3+PWREN	✅	SD3 power enable signal, correctly connected with test point.
BD26	SD3_D1	SD3_D1	✅	SD3 data bit 1 signal, correctly connected to SD card interface.
BD28	LPE_I2S2_DATAIN	LPE_I2S_DATIN	✅	I2S data input signal, correctly connected to I2S audio interface.
BE3	~PCIE_CLKREQ_3	mPCIe_CLKREQ3_B	✅	PCIe clock request 3 signal, correctly pulled up with 10K resistor.
BF6	SATA_TXP_0	SATA0_TXP	✅	SATA port 0 transmit positive signal, correctly AC coupled to SATA connector.
BF10	SATA_TXN_1	SATA1_TXN	✅	SATA port 1 transmit negative signal, correctly AC coupled to mSATA interface.
BF20	HDA_LPE_RCOMP	HDA_RCOMP	✅	HD Audio / Low Power Engine compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
BF22	SD3_1P8EN	SD3_1P8EN	✅	SD3 1.8V enable signal, correctly connected with test point.
BF26	SD3_RCOMP	SD3_RCOMP	✅	SD3 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
BF28	LPE_I2S2_CLK	LPE_I2S_CLK	✅	I2S clock signal, correctly connected to I2S audio interface.
BG3	~PCIE_CLKREQ_0	CLKREQ0_B	✅	PCIe clock request 0 signal, correctly pulled up with 10K resistor.
BG5	~PCIE_CLKREQ_2	LAN_CLKREQ2_B	✅	PCIe clock request 2 signal, correctly pulled up with 10K resistor.
BG7	SATA_TXN_0	SATA0_TXN	✅	SATA port 0 transmit negative signal, correctly AC coupled to SATA connector.
BG18	GPIO_S0_SC_15		✅	GPIO pin, left unconnected as this GPIO is unused.
BG19	HDA_SDI0		✅	HD Audio serial data in 0 signal, left unconnected as HD Audio interface is unused.
BG20	HDA_SDO		✅	HD Audio serial data out signal, left unconnected as HD Audio interface is unused.
BG21	HDA_SDI1		✅	HD Audio serial data in 1 signal, left unconnected as HD Audio interface is unused.
BG22	~HDA_RST		✅	HD Audio reset signal, left unconnected as HD Audio interface is unused.
BH18	GPIO_S0_SC_14		✅	GPIO pin, left unconnected as this GPIO is unused.
BH20	HDA_SYNC		✅	HD Audio sync signal, left unconnected as HD Audio interface is unused.
AK7	RESERVED_AK7		✅	Reserved pin, correctly left unconnected.
AK9	RESERVED_AK9		✅	Reserved pin, correctly left unconnected.
BJ21	HDA_CLK		✅	HD Audio clock signal, left unconnected as HD Audio interface is unused.
AP4	PCIE_TXN_3	mPCIE_TX_N	✅	PCIe lane 3 transmit negative signal, connected to mPCIe slot.
AP6	PCIE_TXP_3	mPCIE_TX_P	✅	PCIe lane 3 transmit positive signal, connected to mPCIe slot.
AP7	PCIE_RXN_3	mPCIE_RX_N	✅	PCIe lane 3 receive negative signal, connected to mPCIe slot.
AP9	PCIE_RXP_3	mPCIE_RX_P	✅	PCIe lane 3 receive positive signal, connected to mPCIe slot.
AP10	PCIE_RXN_2	PCIE_RXN2	✅	PCIe lane 2 receive negative signal, connected to LAN controller.
AP12	PCIE_RXP_2	PCIE_RXP2	✅	PCIe lane 2 receive positive signal, connected to LAN controller.
AP13	PCIE_RCOMP_N_AP13_AP13	PCIE_RCOMP_N	✅	PCIe compensation resistor negative pin, correctly connected with 402 ohm resistor to PCIE_RCOMP_P.
AP14	PCIE_RCOMP_P_AP14_AP14	PCIE_RCOMP_P	✅	PCIe compensation resistor positive pin, correctly connected with 402 ohm resistor to PCIE_RCOMP_N.
AT6	PCIE_TXN_2	PCIE_TXN2	✅	PCIe lane 2 transmit negative signal, connected to LAN controller.
AT7	PCIE_TXP_2	PCIE_TXP2	✅	PCIe lane 2 transmit positive signal, connected to LAN controller.
AT9	PCIE_RXN_1		✅	PCIe lane 1 receive negative signal, left unconnected as PCIe port 1 is unused.
AT10	PCIE_RXP_1		✅	PCIe lane 1 receive positive signal, left unconnected as PCIe port 1 is unused.
AT13	PCIE_RXN_0		✅	PCIe lane 0 receive negative signal, left unconnected as PCIe port 0 is unused.
AT14	PCIE_RXP_0		✅	PCIe lane 0 receive positive signal, left unconnected as PCIe port 0 is unused.
AT18	SATA_RCOMP_N_AT18	SATA_RCOMP_N	✅	SATA compensation resistor negative pin, correctly connected with 402 ohm resistor to SATA_RCOMP_P.
AT20	MMC1_D3		✅	MMC1 data bit 3 signal, left unconnected as MMC1 interface is unused.
AT22	MMC1_CLK		✅	MMC1 clock signal, left unconnected as MMC1 interface is unused.
AT26	MMC1_D6		✅	MMC1 data bit 6 signal, left unconnected as MMC1 interface is unused.
AT28	SD3_D0	SD3_D0	✅	SD3 data bit 0 signal, correctly connected to SD card interface.
AU16	SATA_RXP_0	SATA0_RXP	✅	SATA port 0 receive positive signal, correctly AC coupled to SATA connector.
AU18	SATA_RCOMP_P_AU18	SATA_RCOMP_P	✅	SATA compensation resistor positive pin, correctly connected with 402 ohm resistor to SATA_RCOMP_N.
AU20	MMC1_D7		✅	MMC1 data bit 7 signal, left unconnected as MMC1 interface is unused.
AU22	MMC1_D1		✅	MMC1 data bit 1 signal, left unconnected as MMC1 interface is unused.
AU26	MMC1_D5		✅	MMC1 data bit 5 signal, left unconnected as MMC1 interface is unused.
AU28	SD3_D2	SD3_D2	✅	SD3 data bit 2 signal, correctly connected to SD card interface.
AV4	PCIE_TXN_1		✅	PCIe lane 1 transmit negative signal, left unconnected as PCIe port 1 is unused.
AV6	PCIE_TXP_1		✅	PCIe lane 1 transmit positive signal, left unconnected as PCIe port 1 is unused.
AV9	RESERVED_AV9		✅	Reserved pin, correctly left unconnected.
AV10	RESERVED_AV10		✅	Reserved pin, correctly left unconnected.
AV16	SATA_RXN_0	SATA0_RXN	✅	SATA port 0 receive negative signal, correctly AC coupled to SATA connector.
AV20	MMC1_D0		✅	MMC1 data bit 0 signal, left unconnected as MMC1 interface is unused.
AV22	MMC1_D2		✅	MMC1 data bit 2 signal, left unconnected as MMC1 interface is unused.
AV26	MMC1_CMD		✅	MMC1 command signal, left unconnected as MMC1 interface is unused.
AV28	SD3_CMD	SD3_CMD	✅	SD3 command signal, correctly connected to SD card interface.
AY6	PCIE_TXN_0		✅	PCIe lane 0 transmit negative signal, left unconnected as PCIe port 0 is unused.
AY7	PCIE_TXP_0		✅	PCIe lane 0 transmit positive signal, left unconnected as PCIe port 0 is unused.
AY12	~SATA_LED	SATA_LED_B	✅	SATA LED signal, correctly connected through series resistor to LED control circuit.
AY14	SATA_GP1	SATA_GP1	✅	SATA general purpose signal 1, correctly pulled down with 10K resistor.
AY16	SATA_RXP_1	SATA1_RXP	✅	SATA port 1 receive positive signal, correctly AC coupled to mSATA interface.
AY18	MMC1_RCOMP	MMC1_RCOMP	✅	MMC1 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
AY20	SD2_D0		✅	SD2 data bit 0 signal, left unconnected as SD2 interface is unused.
AY24	MMC1_D4		✅	MMC1 data bit 4 signal, left unconnected as MMC1 interface is unused.
AY26	SD3_CLK	SD3_CLK	✅	SD3 clock signal, correctly connected to SD card interface.

J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net for signal return path.
2	2	SATA0_TXP_C	✅	SATA TX positive signal correctly routed from CPU through AC coupling capacitor C10 to connector.
3	3	SATA0_TXN_C	✅	SATA TX negative signal correctly routed from CPU through AC coupling capacitor C11 to connector.
4	4	GND	✅	Ground pin correctly connected to GND net, positioned between TX and RX differential pairs for isolation.
5	5	SATA0_RXN_C	✅	SATA RX negative signal correctly routed from connector through AC coupling capacitor C12 to CPU.
6	6	SATA0_RXP_C	✅	SATA RX positive signal correctly routed from connector through AC coupling capacitor C13 to CPU.
7	7	GND	✅	Ground pin correctly connected to GND net for signal return path.
MH1			✅	Mounting holes correctly connected to GND_EARTH for chassis ground and EMI shielding.
MH2			✅	Mounting holes correctly connected to GND_EARTH for chassis ground and EMI shielding.

C10 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXP_C	✅	Connector side of AC coupling capacitor for SATA TX positive signal.
2	2	SATA0_TXP	✅	CPU side of AC coupling capacitor for SATA TX positive signal.

C11 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXN_C	✅	Connector side of AC coupling capacitor for SATA TX negative signal.
2	2	SATA0_TXN	✅	CPU side of AC coupling capacitor for SATA TX negative signal.

C12 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXN_C	✅	Connector side of AC coupling capacitor for SATA RX negative signal.
2	2	SATA0_RXN	✅	CPU side of AC coupling capacitor for SATA RX negative signal.

C13 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXP_C	✅	Connector side of AC coupling capacitor for SATA RX positive signal.
2	2	SATA0_RXP	✅	CPU side of AC coupling capacitor for SATA RX positive signal.

C148 - 8200pF 10% 1KV 1808 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND_EARTH	✅	Chassis ground side of safety capacitor for EMI filtering, marked DNI for optional population.
2	2	GND	✅	Signal ground side of safety capacitor for EMI filtering, marked DNI for optional population.

C180 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_N	✅	Connected to mSATA_TX_N net, which carries the negative differential signal to the mSATA device receiver. This pin delivers the AC-coupled signal from the CPU transmitter.
2	2	SATA1_TXN	✅	Connected to SATA1_TXN net, which connects to CPU1 pin BF10 (SATA_TXN_1). This pin receives the negative differential signal from the CPU's SATA1 transmitter.

C177 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_N	✅	Connected to mSATA_RX_N net, which carries the negative differential signal from the mSATA device transmitter. This pin provides AC coupling for the incoming SATA signal.
2	2	SATA1_RXN	✅	Connected to SATA1_RXN net, which connects to CPU1 pin BA16 (SATA_RXN_1). This pin couples the AC-coupled signal to the CPU's SATA1 receiver.

C178 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_P	✅	Connected to mSATA_RX_P net, which carries the positive differential signal from the mSATA device transmitter. This pin provides AC coupling for the incoming SATA signal.
2	2	SATA1_RXP	✅	Connected to SATA1_RXP net, which connects to CPU1 pin AY16 (SATA_RXP_1). This pin couples the AC-coupled signal to the CPU's SATA1 receiver.

C179 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_P	✅	Connected to mSATA_TX_P net, which carries the positive differential signal to the mSATA device receiver. This pin delivers the AC-coupled signal from the CPU transmitter.
2	2	SATA1_TXP	✅	Connected to SATA1_TXP net, which connects to CPU1 pin BD10 (SATA_TXP1). This pin receives the positive differential signal from the CPU's SATA1 transmitter.

R73 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0 ohm resistor connecting CPU1 reserved pin BB10 (RESERVED_VSS4/ICLK_SATA_TERMP) to ground. This grounds a reserved VSS pin as required.
2	2	ICLK_SATA_TERMP	✅	0 ohm resistor connecting CPU1 reserved pin BB10 (RESERVED_VSS4/ICLK_SATA_TERMP) to ground. This grounds a reserved VSS pin as required.

R239 - 402 ohm 1% 1/4W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_RCOMP_N	✅	402 ohm compensation resistor connected between SATA_RCOMP_P and SATA_RCOMP_N pins of the CPU. This provides impedance compensation for the SATA interface.
2	2	SATA_RCOMP_P	✅	402 ohm compensation resistor connected between SATA_RCOMP_P and SATA_RCOMP_N pins of the CPU. This provides impedance compensation for the SATA interface.

R74 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0 ohm resistor connecting CPU1 reserved pin BC10 (RESERVED_VSS5/ICLK_SATA_TERMN) to ground. This grounds a reserved VSS pin as required.
2	2	ICLK_SATA_TERMN	✅	0 ohm resistor connecting CPU1 reserved pin BC10 (RESERVED_VSS5/ICLK_SATA_TERMN) to ground. This grounds a reserved VSS pin as required.

R191 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ0_B	✅	This 10K resistor provides a pull-up from CLKREQ0_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.
2	2	+V1P8S	✅	This 10K resistor provides a pull-up from CLKREQ0_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.

R218 - 402 ohm 1% 1/4W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PCIE_RCOMP_P	✅	This 402 ohm resistor connects between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on the Intel Atom E3825 SOC.
2	2	PCIE_RCOMP_N	✅	This 402 ohm resistor connects between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on the Intel Atom E3825 SOC.

R2 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mPCIe_CLKREQ3_B	✅	This 10K resistor provides a pull-up from mPCIe_CLKREQ3_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.
2	2	+V1P8S	✅	This 10K resistor provides a pull-up from mPCIe_CLKREQ3_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.

R190 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ1_B	✅	This 10K resistor provides a pull-up from CLKREQ1_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.
2	2	+V1P8S	✅	This 10K resistor provides a pull-up from CLKREQ1_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.

R71 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_CLKREQ2_B	✅	This 10K resistor provides a pull-up from LAN_CLKREQ2_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.
2	2	+V1P8S	✅	This 10K resistor provides a pull-up from LAN_CLKREQ2_B to +V1P8S, which is appropriate for the active-low CLKREQ signal.

R354 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SD3_WP	✅	This 0-ohm resistor connects SD3_WP (Write Protect) to SD3_CD# (Card Detect). While this is an unusual configuration in standard SD card interfaces, a schematic text note indicates Bay Trail-I has different behavior for pin BD5, suggesting this connection is intentional for this specific processor.
2	2	SD3_CD#	✅	This 0-ohm resistor connects SD3_WP (Write Protect) to SD3_CD# (Card Detect). While this is an unusual configuration in standard SD card interfaces, a schematic text note indicates Bay Trail-I has different behavior for pin BD5, suggesting this connection is intentional for this specific processor.

R258 - 49.9 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	This 49.9 ohm resistor connects SD3_RCOMP to ground, which is a standard configuration for SD interface impedance compensation.
2	2	SD3_RCOMP	✅	This 49.9 ohm resistor connects SD3_RCOMP to ground, which is a standard configuration for SD interface impedance compensation.

R242 - 49.9 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDA_RCOMP	✅	Connected to HDA_RCOMP pin (BF20) of the Intel Atom E3825 SOC. This provides impedance compensation for the High Definition Audio interface.
2	2	GND	✅	Connected to GND. This completes the compensation resistor circuit by providing the ground reference.

R240 - 49.9 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the MMC1 RCOMP impedance calibration resistor.
2	2	MMC1_RCOMP	✅	Connected to MMC1_RCOMP (CPU1 pin AY18), providing impedance calibration reference for the MMC1 interface.

R234 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP3	✅	1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0.
2	2	GND	✅	1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0.

R208 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP2	✅	1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0.
2	2	GND	✅	1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0.

R211 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1.
2	2	BOM_OP1	✅	10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1.

R400 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1.
2	2	BOM_OP4	✅	10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1.

R259 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_10_UNLOCK	✅	Connected to GPIO_S5_10_UNLOCK signal. This pin forms one end of a series resistor connecting a GPIO signal to the I2S data output.
2	2	LPE_I2S_DATOUT	✅	Connected to LPE_I2S_DATOUT, which is the I2S data output from CPU1 pin BC30. The 1K series resistor provides isolation between the GPIO and I2S signals.

R268 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_FRM	✅	Connected to LPE_I2S_FRM, the I2S frame sync signal from CPU1 pin BA30. This pin forms the pullup connection to ensure the frame sync signal has a defined high state.
2	2	+V1P8S	✅	Connected to +V1P8S power rail. This provides a 10K pullup on the I2S frame sync signal, which is standard practice for I2S interfaces.

J6 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pin 1 connects to +V1P8S power rail, providing 1.8V supply for optional pull-up configuration of SATA LED circuit.
2	2	SATA_LED_R	✅	Pin 2 connects to SATA_LED_R net, which connects through R179 to the CPU SATA LED output signal.

R179 - 220 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_LED_B	✅	Pin 1 connects to SATA_LED_B net from CPU1 pin AY12, which is the active-low SATA LED output signal.
2	2	SATA_LED_R	✅	Pin 2 connects to SATA_LED_R net, which can be pulled up to +V1P8S through jumper J6.

R72 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS6	✅	Pin 1 is connected to GND, providing a ground connection for the ICLK_SATA_TERMP net through this 0-ohm resistor.
2	2	GND	✅	Pin 2 is connected to ICLK_SATA_TERMP, which connects to CPU1 pin BB10 (RESERVED_VSS4). This grounds a reserved VSS pin on the processor.

R192 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS7	✅	Pin 1 is connected to RESERVED_VSS7, which connects to CPU1 pin BB7. This is one side of a 0-ohm resistor used to ground a reserved VSS pin.
2	2	GND	✅	Pin 2 is connected to GND, providing the ground connection for the RESERVED_VSS7 net through this 0-ohm resistor.

R255 - 73.2 ohm 1% 1/4W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR_HOT_L	✅	Connected to VR_HOT_L net, which connects to CPU1 pin C24 (P̅R̅O̅C̅H̅O̅T̅). This is the processor hot signal from the Intel Atom E3825 SOC.
2	2	+V1P0S	✅	Connected to +V1P0S (1.0V supply rail), providing pull-up voltage for the PROCHOT signal. The 73.2 ohm value is lower than typical PROCHOT pull-ups but may be specified by Intel for this processor.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A9	ILB_RTC_X2	BRTCX2	✅	ILB_RTC_X2 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor.
A13	GPIO_S5_9	SOC_USB_HOST_EN1	✅	GPIO_S5[09] is correctly connected to SOC_USB_HOST_EN1 for USB host enable control.
A17	GPIO_S5_3	mPCIE_WAKEB	✅	GPIO_S5[03] is correctly connected to mPCIE_WAKEB with optional pull-up resistor for PCIe wake signaling.
A21	PCU_SPI_MOSI	SOC_SPI_MOSI	✅	PCU_SPI_MOSI is correctly connected to SPI flash with series 0-ohm resistor for signal routing.
A25	SVID_DATA	SVID_DATA	✅	SVID_DATA is correctly connected with series resistor for voltage regulator communication.
B7	PMC_CORE_PWROK	PMC_CORE_PWROK	✅	PMC_CORE_PWROK is correctly connected with series resistor to system power good signal.
B8	ILB_RTC_EXTPAD	BVCCRTC_EXTPAD	✅	ILB_RTC_EXTPAD is correctly connected to RTC power with decoupling capacitor.
B10	~PMC_RSMRST	PMC_RSMRST	✅	PMC_RSMRST is correctly connected with pull-up, pull-down, and RC filtering, but the RC time constant may not meet the >10us requirement noted on the schematic.
B14	GPIO_S5_6	BOM_OP2	✅	GPIO_S5[06] is correctly connected to BOM_OP2 signal.
B16	GPIO_S5_1	SOC_GPIO_S5_1	✅	GPIO_S5[01] is correctly connected to SOC_GPIO_S5_1 signal.
B18	GPIO_S5_0	SOC_GPIO_S5_0	✅	GPIO_S5[00] is correctly connected to SOC_GPIO_S5_0 signal.
B22	PCU_SPI_MISO	SOC_SPI_MISO	✅	PCU_SPI_MISO is correctly connected to SPI flash with series 0-ohm resistor for signal routing.
B24	~SVID_ALERT	SVID_ALERT	✅	SVID_ALERT is correctly connected with series resistor and pull-up for voltage regulator alert signaling.
C9	ILB_RTC_X1	BRTCX1	✅	ILB_RTC_X1 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor.
C11	~ILB_RTC_TEST	ILB_RTC_TESTB	✅	ILB_RTC_TEST is correctly left unconnected as it is a test pin.
C12	~ILB_RTC_RST	RTCRST_L	✅	ILB_RTC_RST is correctly connected with pull-up resistor and decoupling capacitor for RTC reset.
C13	GPIO_S5_8	SOC_USB_HOST_EN0	✅	GPIO_S5[08] is correctly connected to SOC_USB_HOST_EN0 for USB host enable control.
C15	GPIO_S5_7	BOM_OP3	✅	GPIO_S5[07] is correctly connected to BOM_OP3 signal.
C16	GPIO_S5_5	BOM_OP1	✅	GPIO_S5[05] is correctly connected to BOM_OP1 signal.
C17	GPIO_S5_4	BOM_OP4	✅	GPIO_S5[04] is correctly connected to BOM_OP4 signal.
C18	GPIO_S5_2	SOC_GPIO_S5_2	✅	GPIO_S5[02] is correctly connected to SOC_GPIO_S5_2 signal.
C19	GPIO_S5_10	GPIO_S5_10_UNLOCK	✅	GPIO_S5[10] is correctly connected to GPIO_S5_10_UNLOCK signal.
C21	~PCU_SPI_CS_11	SOC_SPI_CS1B	✅	PCU_SPI_CS_11 is connected through DNI resistor, indicating secondary SPI chip select is not used.
C22	PCU_SPI_CLK	SOC_SPI_CLK	✅	PCU_SPI_CLK is correctly connected to SPI flash with series 0-ohm resistor and optional capacitor for signal routing.
C23	~PCU_SPI_CS_00	SOC_SPI_CS0B	✅	PCU_SPI_CS_00 is correctly connected to SPI flash with series 0-ohm resistor for signal routing.
C25	SVID_CLK	SVID_CLK-R	✅	SVID_CLK is correctly connected for voltage regulator clock signaling.
D14	TAP_TCK	XDP_H_TCK	✅	TAP_TCK is correctly connected to JTAG clock with series resistor to ground for termination.
D18	~TAP_PRDY	XDP_H_PRDYB	✅	TAP_PRDY is correctly connected to JTAG probe ready signal.
D20	PMC_ACPRESENT	PMC_ACPRESENT	✅	PMC_ACPRESENT is correctly connected with pull-up resistor for AC power detection.
D22	~PMC_SLP_S3	PMC_SLP_S3_L	✅	PMC_SLP_S3 is correctly connected through level shifter with optional pull-up for S3 sleep state signaling.
D26	PMC_SUSPWRDNACK	SUSPWRDNACK	✅	PMC_SUSPWRDNACK is correctly connected with pull-up resistor for suspend power down acknowledge.
F12	TAP_TDI	XDP_H_TDI	✅	TAP_TDI is correctly connected to JTAG data input with pull-up resistor.
F14	TAP_TMS	XDP_H_TMS	✅	TAP_TMS is correctly connected to JTAG mode select with pull-up resistor.
F16	~TAP_PREQ	XDP_H_PREQB	✅	TAP_PREQ is correctly connected to JTAG probe request signal.
F18	~PMC_SLP_S0IX	PMC_SLP_S0IX	✅	PMC_SLP_S0IX is correctly connected for S0ix low power state signaling.
F20	~PMC_PLTRST	PMC_PLTRST_R_V1P8	✅	PMC_PLTRST is correctly connected through level shifter with optional pull-up for platform reset signaling.
F22	~PMC_SLP_S4	PMC_SLP_S4_L	✅	PMC_SLP_S4 is correctly connected through level shifter with optional pull-up for S4 sleep state signaling.
F26	~PMC_WAKE_PCIE_0	PMC_PCIE_WAKE_R	✅	PMC_WAKE_PCIE_0 is correctly connected through diode with pull-ups for PCIe wake signaling.
G12	~TAP_TRST	XDP_H_TRSTB	✅	TAP_TRST is correctly connected to JTAG reset with pull-down resistor.
G16	TAP_TDO	XDP_H_TDO	✅	TAP_TDO is correctly connected to JTAG data output.
G18	~PMC_SUS_STAT	LPCPD_L	✅	PMC_SUS_STAT is correctly connected for suspend status signaling.
G24	PMC_SUSCLK0_G24	PMC_SUSCLK0	✅	PMC_SUSCLK0 is correctly connected through level shifter with optional pull-ups for suspend clock.
J18	GPIO_S5_25	XDP_H_OBSDATA_A2	✅	GPIO_S5[25] is correctly connected to XDP_H_OBSDATA_A2 for debug observation data.
J20	GPIO_S5_14	GPIO_S514_J20	✅	GPIO_S5[14] is correctly connected with pull-up resistor.
J24	GPIO_S5_17	GPIO_S5_17	✅	GPIO_S5[17] is correctly connected with pull-up resistor and jumper for configuration.
J26	~PMC_PWRBTN	PMC_PWRBTN	✅	PMC_PWRBTN is correctly connected through diode network with optional pull-up for power button input.
K18	GPIO_S5_27	EXP_GPIO1	✅	GPIO_S5[27] is correctly connected to EXP_GPIO1 for expansion GPIO.
K20	GPIO_S5_28	EXP_GPIO2	✅	GPIO_S5[28] is correctly connected to EXP_GPIO2 for expansion GPIO.
K24	GPIO_S5_22	GPIO_D2_LED_CTRL	✅	GPIO_S5[22] is correctly connected to GPIO_D2_LED_CTRL for LED control.
K26	~PMC_BATLOW	PMC_BATLOW	✅	PMC_BATLOW is correctly connected with pull-up resistor for battery low detection.
M18	GPIO_S5_26	XDP_H_OBSDATA_A3	✅	GPIO_S5[26] is correctly connected to XDP_H_OBSDATA_A3 for debug observation data.
M20	GPIO_S5_24	XDP_H_OBSDATA_A1	✅	GPIO_S5[24] is correctly connected to XDP_H_OBSDATA_A1 for debug observation data.
M22	GPIO_S5_29	EXP_GPIO3	✅	GPIO_S5[29] is correctly connected to EXP_GPIO3 for expansion GPIO.
M24	GPIO_S5_30	EXP_GPIO4	✅	GPIO_S5[30] is correctly connected to EXP_GPIO4 for expansion GPIO.
N24	GPIO_S5_23	XDP_H_OBSDATA_A0	✅	GPIO_S5[23] is correctly connected to XDP_H_OBSDATA_A0 for debug observation data.
N26	GPIO_RCOMP	GPIO_RCOMP	✅	GPIO_RCOMP is correctly connected to 49.9 ohm compensation resistor to ground.
BA28	SIO_SPI_MISO	SOC_SIO_SPI_MISO	✅	SIO_SPI_MISO is correctly connected to Serial I/O SPI master in signal.
BA34	~SIO_UART1_RTS	SIO_UART1_RTSB	✅	SIO_UART1_RTS is correctly connected to UART1 request to send signal.
AD9	RESERVED_AD9		✅	Reserved pins are correctly left unconnected per Intel guidance.
AD10	RESERVED_AD10		✅	Reserved pins are correctly left unconnected per Intel guidance.
AD12	RESERVED_AD12		✅	Reserved pins are correctly left unconnected per Intel guidance.
AD13	ICLK_RCOMP	ICLK_RCOMP	✅	ICLK_RCOMP is correctly connected to 47.5 ohm compensation resistor to ground.
AD14	ICLK_ICOMP	ICLK_ICOMP	✅	ICLK_ICOMP is correctly connected to 4.02K compensation resistor to ground.
BD32	~SIO_UART2_RTS		✅	SIO_UART2_RTS is left unconnected, which is acceptable if UART2 hardware flow control is not used.
BD34	SIO_UART2_TXD	SIO_UART2_TXD	✅	SIO_UART2_TXD is correctly connected to UART2 transmit data signal.
AF4	PCIE_CLKP_00		✅	PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as PCIe clock pair 0 is not used.
AF6	PCIE_CLKN_00		✅	PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as PCIe clock pair 0 is not used.
AF7	PCIE_CLKP_11		✅	PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as PCIe clock pair 1 is not used.
AF9	PCIE_CLKN_11		✅	PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as PCIe clock pair 1 is not used.
BF32	~SIO_UART2_CTS		✅	SIO_UART2_CTS is left unconnected, which is acceptable if UART2 hardware flow control is not used.
BF34	SIO_UART2_RXD	SIO_UART2_RXD	✅	SIO_UART2_RXD is correctly connected to UART2 receive data signal.
BG9	~PMC_RSTBTN	PMC_RSTBTN	✅	PMC_RSTBTN is left unconnected. This is unusual and should be verified, as this pin typically requires a pull-up or connection to a reset button.
AH10	ICLK_OSCOUT	XTAL25_OUT	✅	ICLK_OSCOUT is correctly connected to 25 MHz crystal output with appropriate load capacitor and feedback resistor.
AH12	ICLK_OSCIN	XTAL25_IN	✅	ICLK_OSCIN is correctly connected to 25 MHz crystal input with appropriate load capacitor and feedback resistor.
BH4	PMC_PLT_CLK_22		✅	PMC_PLT_CLK_22 is left unconnected, which is acceptable if platform clock 2 is not used.
BH5	PMC_PLT_CLK_11		✅	PMC_PLT_CLK_11 is left unconnected, which is acceptable if platform clock 1 is not used.
BH6	PMC_PLT_CLK_44		✅	PMC_PLT_CLK_44 is left unconnected, which is acceptable if platform clock 4 is not used.
BH7	PMC_PLT_CLK_00		✅	PMC_PLT_CLK_00 is left unconnected, which is acceptable if platform clock 0 is not used.
BH8	PMC_PLT_CLK_33	I2S_MCLK	✅	PMC_PLT_CLK_33 is correctly connected to I2S_MCLK for audio master clock.
AK4	PCIE_CLKN_22	PCIE_CLK-N2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to PCIe clock outputs.
AK6	PCIE_CLKP_22	PCIE_CLK-P2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to PCIe clock outputs.
BJ9	PMC_PLT_CLK_55		✅	PMC_PLT_CLK_55 is left unconnected, which is acceptable if platform clock 5 is not used.
AM4	PCIE_CLKN_33	mPCIE_REFCLK_N	✅	PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to mini-PCIe reference clock outputs.
AM6	PCIE_CLKP_33	mPCIE_REFCLK_P	✅	PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to mini-PCIe reference clock outputs.
AM9	RESERVED_AM9		✅	Reserved pins are correctly left unconnected per Intel guidance.
AM10	RESERVED_AM10		✅	Reserved pins are correctly left unconnected per Intel guidance.
AT32	SIO_PWM_11	SOC_PWM1	✅	SIO_PWM_11 is correctly connected to PWM output signal.
AT34	RESERVED		✅	Reserved pin is correctly left unconnected per Intel guidance.
AU32	SIO_PWM_00	SOC_PWM0	✅	SIO_PWM_00 is correctly connected to PWM output signal.
AU34	SIO_UART1_RXD	SIO_UART1_RXD	✅	SIO_UART1_RXD is correctly connected to UART1 receive data signal.
AV32	~SIO_SPI_CS	SOC_SIO_SPI_CS1	✅	SIO_SPI_CS is correctly connected to Serial I/O SPI chip select signal.
AV34	SIO_UART1_TXD	SIO_UART1_TXD	✅	SIO_UART1_TXD is correctly connected to UART1 transmit data signal.
AY28	SIO_SPI_MOSI	SOC_SIO_SPI_MOSI	✅	SIO_SPI_MOSI is correctly connected to Serial I/O SPI master out signal.
AY30	SIO_SPI_CLK	SOC_SIO_SPI_CLK	✅	SIO_SPI_CLK is correctly connected to Serial I/O SPI clock signal.
AY34	~SIO_UART1_CTS	SIO_UART1_CTSB	✅	SIO_UART1_CTS is correctly connected to UART1 clear to send signal.

D5 - BAT754C Schottky Diode ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
3			❌	Common cathode (C) connected to +RTCVCC, but +RTCVCC is not connected to the CPU's RTC power input (BVCCRTC_EXTPAD). This is a critical error - the RTC battery backup circuit will not function without this connection. Pin 3 connects to net +RTCVCC (from schematic) +RTCVCC connects to C286 pin 2 (1uF decoupling capacitor) and R279 pin 1 (20K resistor to RTCRST_L) (from schematic) The CPU has an RTC power pin B8 (ILB_RTC_EXTPAD) connected to net BVCCRTC_EXTPAD (from schematic) BVCCRTC_EXTPAD only connects to CPU1 pin B8 and C41 pin 1 (0.1uF decoupling capacitor) (from schematic) There is no component connecting +RTCVCC to BVCCRTC_EXTPAD on this schematic page (from schematic) The pin name 'ILB_RTC_EXTPAD' with 'EXTPAD' suffix indicates this pin expects an external power source (reasoning) The existence of a complete battery backup circuit generating +RTCVCC strongly suggests it is intended to power the RTC (reasoning) Without power to the RTC power pin, the RTC cannot function and will not maintain time when main power is removed (reasoning) A connection (0-ohm resistor or direct trace) should be added between +RTCVCC and BVCCRTC_EXTPAD to properly power the RTC (reasoning)
1			✅	Anode 1 (A1) connected to +PS_3VSB (3.3V standby power), providing primary power source for RTC through OR-ing diode configuration.
2			✅	Anode 2 (A2) connected to +VBAT_R (battery voltage through 1K current-limiting resistor R278), providing backup power source for RTC when standby power is absent.

BH1 - BATTERY HOLDER VERT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+VBAT	✅	Positive battery terminals connected in parallel to +VBAT net, which supplies battery backup power through current-limiting resistor R278.
2	P2	+VBAT	✅	Positive battery terminals connected in parallel to +VBAT net, which supplies battery backup power through current-limiting resistor R278.
3	N	GND	✅	Negative battery terminal correctly connected to ground.

Y1 - 32.768KHz Crystal ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BRTCX2	✅	Crystal pin connected to BRTCX2, which connects to CPU RTC oscillator output (ILB_RTC_X2), load capacitor C42 (18pF), and feedback resistor R76 (10M).
2	2	BRTCX1	✅	Crystal pin connected to BRTCX1, which connects to CPU RTC oscillator input (ILB_RTC_X1), load capacitor C43 (18pF), and feedback resistor R76 (10M).

Y2 - 25.00MHz Crystal ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XTAL25_IN	✅	Crystal input pin correctly connected to CPU oscillator input (ICLK_OSCIN) through XTAL25_IN net with proper 27pF load capacitor C175 to ground and 1M feedback resistor R188 to output.
2	2	GND	✅	Ground pins correctly connected to GND net for crystal shielding.
4	4	GND	✅	Ground pins correctly connected to GND net for crystal shielding.
3	3	XTAL25_OUT	✅	Crystal output pin correctly connected to CPU oscillator output (ICLK_OSCOUT) through XTAL25_OUT net with proper 27pF load capacitor C176 to ground and 1M feedback resistor R188 to input.

U19 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA power supply pin correctly connected to +V1P8A (1.8V rail).
2	A1	PMC_PLTRST_R_V1P8	✅	A1 channel correctly connected to PMC_PLTRST_R_V1P8 from CPU1 pin F20.
3	A2	PMC_SUSCLK0	✅	A2 channel correctly connected to PMC_SUSCLK0 from CPU1 pin G24.
4	A3	PMC_SLP_S4_L	✅	A3 channel correctly connected to PMC_SLP_S4_L from CPU1 pin F22.
5	A4	PMC_SLP_S3_L	✅	A4 channel correctly connected to PMC_SLP_S3_L from CPU1 pin D22.
6	GND	GND	✅	Ground pin correctly connected to GND.
7	B4	SLP_S3_L	✅	B4 channel correctly connected to SLP_S3_L, translating from A4.
8	B3	SLP_S4_L	✅	B3 channel correctly connected to SLP_S4_L, translating from A3.
9	B2	SUSCLK_3P3	✅	B2 channel correctly connected to SUSCLK_3P3, translating from A2.
10	B1	PMC_PLTRST_L	✅	B1 channel correctly connected to PMC_PLTRST_L, translating from A1.
11	VCCB	PWR_BUF1	✅	VCCB power supply pin correctly connected to PWR_BUF1, which is tied to +3VSB through R26.
12	OE	PMC_OE	✅	OE (output enable) pin correctly connected to PMC_OE with pull-up to +V1P8A through R57.

D3 - BAT54A-S Schottky Diode ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PCIE_WAKE	✅	Both pins connected to PMC_PCIE_WAKE in the 3.3V domain. The package designation 'BAT54_132_2' indicates a non-standard symbol pinout where these pins represent paralleled cathodes, despite standard BAT54A-S having pin 2 as the common anode.
2	2	PMC_PCIE_WAKE	✅	Both pins connected to PMC_PCIE_WAKE in the 3.3V domain. The package designation 'BAT54_132_2' indicates a non-standard symbol pinout where these pins represent paralleled cathodes, despite standard BAT54A-S having pin 2 as the common anode.
3	3	PMC_PCIE_WAKE_R	✅	Connected to PMC_PCIE_WAKE_R in the 1.8V domain going to the CPU. With the non-standard symbol pinout indicated by package designation 'BAT54_132_2', this pin represents the common anode, enabling proper level shifting functionality.

D10 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	3VSB_OK	✅	Anode 1 connected to 3VSB_OK signal. This allows the 3VSB power good signal to control PS_OUT_L.
A2	A2	PMC_PWRBTN	✅	Anode 2 connected to PMC_PWRBTN signal from CPU. This allows the power button signal to control PS_OUT_L.
C	C	PS_OUT_L	✅	Common cathode connected to PS_OUT_L output signal. This output is pulled low when either 3VSB_OK or PMC_PWRBTN goes low.

J7 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_17	✅	Pin 1 connects to GPIO_S5_17, which is pulled high to +V1P8S through R183 (10K) when the jumper is not installed.
2	2	GND	✅	Pin 2 connects to GND, providing the pull-down path when the jumper is installed.

R75 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pull-up resistor connected to +V1P8S power rail.
2	2	PCU_SMB_ALERT	✅	Pull-up resistor connected to PCU_SMB_ALERT signal from CPU1.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A7	USB_HSIC_RCOMP	USB_HSIC0_RCOMP	✅	USB_HSIC_RCOMP pin correctly connected to ground through a 45.3 ohm compensation resistor.
B4	USB_HSIC0_DATA		✅	USB_HSIC0_DATA and USB_HSIC0_STROBE pins are not connected, which is acceptable if USB HSIC interface is not used.
B5	USB_HSIC0_STROBE		✅	USB_HSIC0_DATA and USB_HSIC0_STROBE pins are not connected, which is acceptable if USB HSIC interface is not used.
B12	GPIO_S5_43		✅	GPIO_S5_43 pin (USB_ULPI_REFCLK) is not connected, which is acceptable if USB ULPI interface is not used.
B20	~USB_OC_11	SOC_USB_HOST_OC1	✅	USB_OC[1]# pin correctly connected with 10K pull-up resistor to +V1P8A for overcurrent detection.
C7	USB_RCOMPI	USB_RCOMP	✅	USB_RCOMPI and USB_RCOMPO pins correctly connected together to ground through a 45.3 ohm compensation resistor.
D6	USB_RCOMPO	USB_RCOMP	✅	USB_RCOMPI and USB_RCOMPO pins correctly connected together to ground through a 45.3 ohm compensation resistor.
C20	~USB_OC_00	SOC_USB_HOST_OC0	✅	USB_OC[0]# pin correctly connected with 10K pull-up resistor to +V1P8A for overcurrent detection.
D2	USB_HSIC1_STROBE		✅	USB_HSIC1_STROBE and USB_HSIC1_DATA pins are not connected, which is acceptable if USB HSIC1 interface is not used.
E2	USB_HSIC1_DATA		✅	USB_HSIC1_STROBE and USB_HSIC1_DATA pins are not connected, which is acceptable if USB HSIC1 interface is not used.
D4	USB3_RXP0	USB3_RXP0	✅	USB3 differential signal pins correctly connected for USB 3.0 operation.
E3	USB3_RXN0	USB3_RXN0	✅	USB3 differential signal pins correctly connected for USB 3.0 operation.
K6	USB3_TXP0	USB3_TXP0	✅	USB3 differential signal pins correctly connected for USB 3.0 operation.
K7	USB3_TXN0	USB3_TXN0	✅	USB3 differential signal pins correctly connected for USB 3.0 operation.
D10	ICLK_USB_TERM_1	ICLK_USB_TERM_0	✅	ICLK_USB_TERM_1 pin correctly connected to ground through a 1K termination resistor.
F10	ICLK_USB_TERMN	ICLK_USB_TERM_1	✅	ICLK_USB_TERMN pin correctly connected to ground through a 1K termination resistor.
G2	GPIO_S5_31		✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
G14	USB_DN1	USB_DN1	✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
H3	GPIO_S5_42		✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
H10	USB_DN3		✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
J3	GPIO_S5_40		✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
J12	USB_DN2	USB_HOST_DN	✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
J14	USB_DP1	USB_DP1	✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
K10	USB_DP3		✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
K12	USB_DP2	USB_HOST_DP	✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
K16	USB_DN0	USB_DN0	✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
M16	USB_DP0	USB_DP0	✅	USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected.
H4	RESERVED_H4		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
H5	RESERVED_H5		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
H7	RESERVED_H7		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
H8	RESERVED_H8		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
M4	RESERVED_M4		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
M6	RESERVED_M6		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
M7	RESERVED_M7		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
M9	RESERVED_M9		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
M10	RESERVED_M10		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
P6	RESERVED_P6		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
P7	RESERVED_P7		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
P10	RESERVED_P10		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
P12	RESERVED_P12		✅	Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise.
K2	GPIO_S5_34		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
K3	GPIO_S5_35		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
L1	GPIO_S5_33		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
L3	GPIO_S5_39		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
M2	GPIO_S5_36		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
M3	GPIO_S5_32		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
N3	GPIO_S5_37		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
P2	GPIO_S5_38		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
P3	GPIO_S5_41		✅	GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used.
M12	USB3_REXT0	USB3_REXT0	✅	USB3_REXT0 pin correctly connected to ground through a 1.24K external resistor for USB 3.0.
M13	USB_PLL_MON	USB_PLL_MON	✅	USB_PLL_MON pin connected to test point for USB PLL monitoring.
BC12	GPIO_S0_SC_56	GPIO_S0_SC_56	✅	GPIO_S0_SC_56 pin connected to off-page net, function determined by software configuration.
BC14	GPIO_S0_SC_58	HDMI_CEC	✅	GPIO_S0_SC_58 pin connected to HDMI_CEC signal for HDMI Consumer Electronics Control.
BC16	GPIO_S0_SC_61	PCU_UART3_RXD	✅	GPIO_S0_SC_61 pin correctly configured as UART3 RXD and connected through level shifter U6 to debug connector.
BD12	GPIO_S0_SC_55	GPIO_S0_SC_55	✅	GPIO_S0_SC_55 pin connected to off-page net with DNI test point.
BD14	GPIO_S0_SC_57	PCU_UART3_TXD	✅	GPIO_S0_SC_57 pin correctly configured as UART3 TXD and connected through level shifter U6 to debug connector.
BD16	GPIO_S0_SC_60		✅	GPIO_S0_SC_60 and GPIO_S0_SC_59 pins are not connected, which is acceptable if these GPIOs are not used.
BF14	GPIO_S0_SC_59		✅	GPIO_S0_SC_60 and GPIO_S0_SC_59 pins are not connected, which is acceptable if these GPIOs are not used.
BF18	LPC_RCOMP	LPC_RCOMP	✅	LPC_RCOMP pin correctly connected to ground through a 49.9 ohm compensation resistor.
BG11	~PCU_SMB_ALERT	PCU_SMB_ALERT	✅	PCU_SMB_ALERT# pin correctly connected with 10K pull-up to +V1P8S and routed through 0-ohm jumper to LAN interface.
BG12	PCU_SMB_DATA	PCU_SMB_DATA	✅	PCU_SMB_DATA pin correctly connected with 2.2K pull-up to +V1P8S and routed through level shifter U5 for voltage translation.
BG13	ILB_LPC_SERIRQ		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BG14	ILB_LPC_AD_33		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BG15	ILB_LPC_CLK_00		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BG16	~ILB_LPC_CLKRUN		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BG17	~ILB_LPC_FRAME		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BH14	ILB_LPC_CLK_11		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BH16	ILB_LPC_AD_00		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BJ13	ILB_LPC_AD_22		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BJ17	ILB_LPC_AD_11		✅	LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups.
BG23	SIO_I2C0_CLK		✅	SIO_I2C0 interface pins are not connected, which is acceptable if I2C0 is not used.
BH22	SIO_I2C0_DATA		✅	SIO_I2C0 interface pins are not connected, which is acceptable if I2C0 is not used.
BG24	SIO_I2C1_DATA	SIO_I2C1_SDA	✅	SIO_I2C1_DATA pin connected to off-page net with DNI test point for I2C1 data signal.
BG25	SIO_I2C2_DATA		✅	SIO_I2C2 interface pins are not connected, which is acceptable if I2C2 is not used.
BJ25	SIO_I2C2_CLK		✅	SIO_I2C2 interface pins are not connected, which is acceptable if I2C2 is not used.
BG26	SIO_I2C3_DATA		✅	SIO_I2C3 interface pins are not connected, which is acceptable if I2C3 is not used.
BH26	SIO_I2C3_CLK		✅	SIO_I2C3 interface pins are not connected, which is acceptable if I2C3 is not used.
BG27	SIO_I2C4_CLK		✅	SIO_I2C4 interface pins are not connected, which is acceptable if I2C4 is not used.
BF27	SIO_I2C4_DATA		✅	SIO_I2C4 interface pins are not connected, which is acceptable if I2C4 is not used.
BG28	SIO_I2C5_CLK	SI0_I2C5_SCL	✅	SIO_I2C5_CLK pin correctly connected through 22 ohm series resistor for I2C signal conditioning.
BG29	SIO_I2C6_CLK	SI0_I2C6_SCL	✅	SIO_I2C6_CLK pin correctly connected through 22 ohm series resistor for I2C signal conditioning.
BG30	GPIO_S0_SC_093	TP10_NET	✅	GPIO_S0_SC_093 pin intentionally grounded through 0-ohm resistor R261 per schematic text note.
BH10	PCU_SMB_CLK	PCU_SMB_CLK	✅	PCU_SMB_CLK pin correctly connected with 2.2K pull-up to +V1P8S and routed through level shifter U5 for voltage translation.
BH12	ILB_8254_SPKR	ILB_8254_SPKR	✅	ILB_8254_SPKR pin connected to off-page net for speaker output signal.
BH24	SIO_I2C1_CLK	SIO_I2C1_SCL	✅	SIO_I2C1_CLK pin connected to off-page net with DNI test point for I2C1 clock signal.
BH28	SIO_I2C5_DATA	SI0_I2C5_SDA	✅	SIO_I2C5_DATA pin correctly connected through 22 ohm series resistor for I2C signal conditioning.
BH30	GPIO_S0_SC_092	TP9_NET	✅	GPIO_S0_SC_092 pin intentionally grounded through 0-ohm resistor R243 per schematic text note.
BJ29	SIO_I2C6_DATA	SI0_I2C6_SDA	✅	SIO_I2C6_DATA pin correctly connected through 22 ohm series resistor for I2C signal conditioning.

U5 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DDR_SMB_CLK	✅	B2 pin correctly connected to DDR_SMB_CLK for 3.3V side clock signal translation.
2	GND	GND	✅	GND pin correctly connected to ground plane.
3	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V) supply for A-side operation.
4	A2	PCU_SMB_CLK	✅	A2 pin correctly connected to PCU_SMB_CLK for 1.8V side clock signal from CPU.
5	A1	PCU_SMB_DATA	✅	A1 pin correctly connected to PCU_SMB_DATA for 1.8V side data signal from CPU.
6	OE	PCU_SMB_BUFF_ENB	✅	OE pin correctly connected to PCU_SMB_BUFF_ENB with pull-up for buffer enable control.
7	VCCB	BUF2_PWR	✅	VCCB pin correctly connected to BUF2_PWR (3.3V) supply for B-side operation.
8	B1	DDR_SMB_DATA	✅	B1 pin correctly connected to DDR_SMB_DATA for 3.3V side data signal translation.

U6 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DBG_UART3_TXD	✅	B2 pin correctly connected to DBG_UART3_TXD for 3.3V side UART TX signal from the board to the debug connector.
2	GND	GND	✅	GND pin correctly connected to ground.
3	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V supply) for the CPU side.
4	A2	PCU_UART3_TXD	✅	A2 pin correctly connected to PCU_UART3_TXD for 1.8V side UART TX signal from the CPU.
5	A1	PCU_UART3_RXD	✅	A1 pin correctly connected to PCU_UART3_RXD for 1.8V side UART RX signal to the CPU.
6	OE	LSENB	✅	OE pin correctly connected to LSENB with pull-up to +V1P8S, enabling the level shifter by default.
7	VCCB	BUF3_PWR	✅	VCCB pin correctly connected to BUF3_PWR (3.3V supply) for the connector side.
8	B1	DBG_UART3_RXD	✅	B1 pin correctly connected to DBG_UART3_RXD for 3.3V side UART RX signal from the debug connector to the board.

R52 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LSENB	✅	Pull-up resistor connecting LSENB to +V1P8S, ensuring the level shifter enable signal defaults to high (enabled state).
2	2	+V1P8S	✅	Pull-up resistor connecting LSENB to +V1P8S, ensuring the level shifter enable signal defaults to high (enabled state).

R51 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BUF3_PWR	✅	Zero-ohm jumper connecting BUF3_PWR to +3VSB, providing power to the level shifter's B-side while allowing optional isolation or current measurement.
2	2	+3VSB	✅	Zero-ohm jumper connecting BUF3_PWR to +3VSB, providing power to the level shifter's B-side while allowing optional isolation or current measurement.

J4 - 258-0004869 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net, providing ground reference for the serial cable.
2	2		✅	Pins 2, 3, and 6 are not connected, which is correct for a basic 3-wire UART interface (GND, TX, RX only).
3	3		✅	Pins 2, 3, and 6 are not connected, which is correct for a basic 3-wire UART interface (GND, TX, RX only).
6	6		✅	Pins 2, 3, and 6 are not connected, which is correct for a basic 3-wire UART interface (GND, TX, RX only).
4	4	DBG_UART3_RXD	✅	Receive pin correctly connected to DBG_UART3_RXD, allowing the board to receive data from the external serial cable.
5	5	DBG_UART3_TXD_R	✅	Transmit pin correctly connected to DBG_UART3_TXD_R, allowing the board to transmit data to the external serial cable.

R819 - 110-0002000 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DBG_UART3_TXD	✅	Series resistor on the UART transmit line providing signal conditioning, current limiting, and EMI reduction.
2	2	DBG_UART3_TXD_R	✅	Series resistor on the UART transmit line providing signal conditioning, current limiting, and EMI reduction.

R50 - 110-0001859 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pull-down resistor on the UART receive line ensuring a defined logic level when no cable is connected.
2	2	DBG_UART3_RXD	✅	Pull-down resistor on the UART receive line ensuring a defined logic level when no cable is connected.

R77 - 110-0004472 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU1 pin A7) and GND, serving as a compensation resistor for the USB HSIC interface.
2	2	USB_HSIC0_RCOMP	✅	45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU1 pin A7) and GND, serving as a compensation resistor for the USB HSIC interface.

R185 - 110-0004472 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	45.3 ohm resistor connected between USB_RCOMP (CPU1 pins D6 and C7) and GND, serving as a compensation resistor for the USB 2.0 interface.
2	2	USB_RCOMP	✅	45.3 ohm resistor connected between USB_RCOMP (CPU1 pins D6 and C7) and GND, serving as a compensation resistor for the USB 2.0 interface.

R187 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	1K ohm resistor connected between ICLK_USB_TERM_0 (CPU1 pin D10) and GND, serving as a termination resistor for the USB interface.
2	2	ICLK_USB_TERM_0	✅	1K ohm resistor connected between ICLK_USB_TERM_0 (CPU1 pin D10) and GND, serving as a termination resistor for the USB interface.

R186 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	1K ohm resistor connected between ICLK_USB_TERM_1 (CPU1 pin F10) and GND, serving as a termination resistor for the USB interface.
2	2	ICLK_USB_TERM_1	✅	1K ohm resistor connected between ICLK_USB_TERM_1 (CPU1 pin F10) and GND, serving as a termination resistor for the USB interface.

R212 - 110-0004478 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_REXT0	✅	1.24K ohm resistor connected between USB3_REXT0 (CPU1 pin M12) and GND, serving as an external reference resistor for the USB 3.0 interface.
2	2	GND	✅	1.24K ohm resistor connected between USB3_REXT0 (CPU1 pin M12) and GND, serving as an external reference resistor for the USB 3.0 interface.

R241 - 110-0003059 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPC_RCOMP	✅	49.9 ohm resistor connected between LPC_RCOMP (CPU1 pin BF18) and GND, serving as a compensation resistor for the LPC interface.
2	2	GND	✅	49.9 ohm resistor connected between LPC_RCOMP (CPU1 pin BF18) and GND, serving as a compensation resistor for the LPC interface.

R12 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SCL	✅	Pin 1 connects to the SOC's I2C6 SCL pin (CPU1 BG29) on net SI0_I2C6_SCL.
2	2	I2C6_SCL	✅	Pin 2 connects to the external I2C6 SCL bus on net I2C6_SCL.

R11 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SDA	✅	Pin 1 connects to the SOC's I2C6 SDA pin (CPU1 BJ29) on net SI0_I2C6_SDA.
2	2	I2C6_SDA	✅	Pin 2 connects to the external I2C6 SDA bus on net I2C6_SDA.

R270 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SCL	✅	Pin 1 connects to the SOC's I2C5 SCL pin (CPU1 BG28) on net SI0_I2C5_SCL.
2	2	I2C5_SCL	✅	Pin 2 connects to the external I2C5 SCL bus on net I2C5_SCL.

R269 - 110-0001967 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SDA	✅	Pin 1 connects to the SOC's I2C5 SDA pin (CPU1 BH28) on net SI0_I2C5_SDA.
2	2	I2C5_SDA	✅	Pin 2 connects to the external I2C5 SDA bus on net I2C5_SDA.

R177 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pull-up resistor connection to +V1P8S power rail for I2C data line.
2	2	PCU_SMB_DATA	✅	Connection to PCU_SMB_DATA, the I2C data line from the CPU.

R45 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pull-up resistor connection to +V1P8S power rail for I2C clock line.
2	2	PCU_SMB_CLK	✅	Connection to PCU_SMB_CLK, the I2C clock line from the CPU.

R84 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pull-up resistor connection to +V1P8A power rail for USB overcurrent detection.
2	2	SOC_USB_HOST_OC0	✅	Connection to SOC_USB_HOST_OC0, an active-low USB overcurrent detection input on the CPU.

R97 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pull-up resistor connection to +V1P8A power rail for USB overcurrent detection.
2	2	SOC_USB_HOST_OC1	✅	Connection to SOC_USB_HOST_OC1, an active-low USB overcurrent detection input on the CPU.

R261 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TP10_NET	✅	Pin 1 connects to TP10_NET, which is connected to CPU1 GPIO_S0_SC_093 (pin BG30) and test point TP16. This provides a connection from the GPIO to the 0-ohm resistor.
2	2	GND	✅	Pin 2 connects to GND, completing the path to ground the GPIO pin through the 0-ohm resistor as intended by the design notes.

R243 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TP9_NET	✅	Pin 1 connects to TP9_NET, which is connected to CPU1 GPIO_S0_SC_092 (pin BH30) and test point TP13. This provides a connection from the GPIO to the 0-ohm resistor.
2	2	GND	✅	Pin 2 connects to GND, completing the path to ground the GPIO pin through the 0-ohm resistor as intended by the design notes.

TP1 - TEST_POINT_0.040_SMT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$9N613	✅	Test point correctly connected to CPU internal voltage monitoring pin AF30 for 1.05V core voltage measurement.

TP2 - TEST_POINT_0.040_SMT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$9N615	✅	Test point correctly connected to CPU internal voltage monitoring pin AA22 for core VCC measurement in S0IX state.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A48	DRAM_VDD_S4	+VDIMM	✅	DRAM_VDD_S4 power pin correctly connected to +VDIMM rail with appropriate decoupling capacitors.
N28	CORE_VSS_SENSE_N28	VSS_SENSE	✅	Core ground sense pin correctly connected to VSS_SENSE net for voltage regulator feedback.
P28	CORE_VCC_SENSE_P28	VCC_SENSE	✅	Core VCC sense pin correctly connected to VCC_SENSE net for voltage regulator feedback.
AA22	TP2_CORE_VCC_S0IX	$9N615	✅	Test point pin for monitoring core VCC in S0IX state, correctly connected to external test point TP2.
AA24	UNCORE_VNN_S3_AA24	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AC22	UNCORE_VNN_S3_AC22	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AC24	UNCORE_VNN_S3_AC24	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AD22	UNCORE_VNN_S3_AD22	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AD24	UNCORE_VNN_S3_AD24	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AF22	UNCORE_VNN_S3_AF22	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AF24	UNCORE_VNN_S3_AF24	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AG22	UNCORE_VNN_S3_AG22	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AG24	UNCORE_VNN_S3_AG24	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AJ22	UNCORE_VNN_S3_AJ22	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AJ24	UNCORE_VNN_S3_AJ24	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AK22	UNCORE_VNN_S3_AK22	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AK24	UNCORE_VNN_S3_AK24	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AK25	UNCORE_VNN_S3_AK25	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AK27	UNCORE_VNN_S3_AK27	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AK29	UNCORE_VNN_S3_AK29	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AK30	UNCORE_VNN_S3_AK30	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AK32	UNCORE_VNN_S3_AK32	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AM22	UNCORE_VNN_S3_AM22	+VGFX	✅	UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors.
AA27	CORE_VCC_S0IX_AA27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AA29	CORE_VCC_S0IX_AA29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AA30	CORE_VCC_S0IX_AA30	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AC27	CORE_VCC_S0IX_AC27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AC29	CORE_VCC_S0IX_AC29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AC30	CORE_VCC_S0IX_AC30	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AD27	CORE_VCC_S0IX_AD27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AD29	CORE_VCC_S0IX_AD29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AD30	CORE_VCC_S0IX_AD30	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AF27	CORE_VCC_S0IX_AF27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AF29	CORE_VCC_S0IX_AF29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AG27	CORE_VCC_S0IX_AG27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AG29	CORE_VCC_S0IX_AG29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
AG30	CORE_VCC_S0IX_AG30	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
P26	CORE_VCC_S0IX_P26	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
P27	CORE_VCC_S0IX_P27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
U27	CORE_VCC_S0IX_U27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
U29	CORE_VCC_S0IX_U29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
V27	CORE_VCC_S0IX_V27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
V29	CORE_VCC_S0IX_V29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
V30	CORE_VCC_S0IX_V30	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
Y27	CORE_VCC_S0IX_Y27	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
Y29	CORE_VCC_S0IX_Y29	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
Y30	CORE_VCC_S0IX_Y30	+VCORE	✅	CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors.
BB8	UNCORE_VNN_SENSE	VCCGT_SENSE	✅	UNCORE_VNN voltage sense pin correctly connected to VCCGT_SENSE net for voltage regulator feedback.
AD38	DRAM_VDD_S4_AD38	DRAM_VDD_CLK	✅	DRAM_VDD_S4 power pins connected to separate DRAM_VDD_CLK rail for clock power isolation, derived from +VDIMM through 0-ohm jumper R275.
AF38	DRAM_VDD_S4_AF38	DRAM_VDD_CLK	✅	DRAM_VDD_S4 power pins connected to separate DRAM_VDD_CLK rail for clock power isolation, derived from +VDIMM through 0-ohm jumper R275.
AF30	TP_CORE_V1P05_S4	$9N613	✅	Test point pin for monitoring 1.05V core voltage in S4 state, correctly connected to external test point TP1.
AK38	DRAM_VDD_S4_AK38	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
AM38	DRAM_VDD_S4_AM38	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
AV41	DRAM_VDD_S4_AV41	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
AV42	DRAM_VDD_S4_AV42	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
BB46	DRAM_VDD_S4_BB46	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
BD49	DRAM_VDD_S4_BD49	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
BD52	DRAM_VDD_S4_BD52	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
BD53	DRAM_VDD_S4_BD53	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
BF44	DRAM_VDD_S4_BF44	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
BG51	DRAM_VDD_S4_BG51	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
BJ48	DRAM_VDD_S4_BJ48	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
C51	DRAM_VDD_S4_C51	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
D44	DRAM_VDD_S4_D44	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
F49	DRAM_VDD_S4_F49	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
F52	DRAM_VDD_S4_F52	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
F53	DRAM_VDD_S4_F53	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
H46	DRAM_VDD_S4_H46	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
M41	DRAM_VDD_S4_M41	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
M42	DRAM_VDD_S4_M42	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
V38	DRAM_VDD_S4_V38	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.
Y38	DRAM_VDD_S4_Y38	+VDIMM	✅	DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors.

R275 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	0-ohm jumper connecting +VDIMM power rail to DRAM_VDD_CLK net, which supplies CPU1 pins AD38 and AF38. This appears to be an intentional design to provide separately filtered power for specific DRAM power pins.
2	2	DRAM_VDD_CLK	✅	0-ohm jumper connecting +VDIMM power rail to DRAM_VDD_CLK net, which supplies CPU1 pins AD38 and AF38. This appears to be an intentional design to provide separately filtered power for specific DRAM power pins.

CPU1 - INTEL_ATOM_E3825_SOC ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
AC32	CORE_V1P05_S3_AC32	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
Y32	CORE_V1P05_S3_Y32	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
AA33	CORE_V1P05_S3_AA33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
AF33	CORE_V1P05_S3_AF33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
AG33	CORE_V1P05_S3_AG33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
AG35	CORE_V1P05_S3_AG35	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
U33	CORE_V1P05_S3_U33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
U35	CORE_V1P05_S3_U35	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
V33	CORE_V1P05_S3_V33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628) These pins are connected to net +V1P0S in the schematic (from schematic) The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic) According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120) The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning) This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning) The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic) These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning) Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)
A7			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B4			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B5			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B7			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B8			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B10			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B12			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B14			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B16			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B18			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B20			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B22			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B24			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B26			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B28			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B30			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
D14			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
D18			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
D20			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
D22			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
D26			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
D27			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
F12			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
F14			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
F16			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
F20			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
F22			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
F26			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
G2			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
G12			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
G14			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
G16			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
G18			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
G24			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
G30			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
H3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
H10			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
J3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
J12			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
J14			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
J20			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
J26			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
J30			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K2			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K6			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K7			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K10			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K12			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K16			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K26			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
K30			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
L1			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
L3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
M2			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
M3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
M4			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
M6			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
M16			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
M30			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
N3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
N30			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
P2			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
P3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C20			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C21			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C22			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C23			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C24			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C25			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C26			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C27			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
C28			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
D4			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
E3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AL1			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AL3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AK2			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AK3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP2			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AR1			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AR3			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AT2			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AK4			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AK6			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AM4			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AM6			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP4			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP6			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP7			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP9			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP10			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
AP12			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BH20			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BJ21			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BH22			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BH24			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BH26			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BH28			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BJ25			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BJ29			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BH14			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BH16			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BJ13			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BJ17			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
BJ9			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A9			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A13			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A17			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A21			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A25			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A29			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A33			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A37			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A41			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A45			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B32			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B34			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B36			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B38			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B40			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B42			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B44			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B46			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B47			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B48			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B49			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
B50			✅	Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions.
A48			✅	DRAM_VDD_S4 power pin correctly connected to DDR3L memory power supply rail, providing 1.35V power for the memory interface.
B6	UNCORE_V1P0_G3_B6	+V1P0A	✅	UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply).
C5	UNCORE_V1P0_G3_C5	+V1P0A	✅	UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply).
U22	UNCORE_V1P0_G3_U22	+V1P0A	✅	UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply).
V22	UNCORE_V1P0_G3_V22	+V1P0A	✅	UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply).
C3	USB3_V1P0_G3_C3	+V1P0A	✅	USB3_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply).
Y19	USB3_V1P0_G3_Y19	+V1P0A	✅	USB3_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply).
F1	RESERVED_F1	$10N1595	✅	RESERVED_F1 pin is connected to test point TP4 which is marked DNI (Do Not Install). Reserved pins typically have no specific function and this connection is acceptable.
M14	USB_V1P0_S3_M14	+V1P0S	✅	USB_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
U18	USB_V1P0_S3_U18	+V1P0S	✅	USB_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
U19	USB_V1P0_S3_U19	+V1P0S	✅	USB_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
N18	USB_V3P3_G3_N18	+3VSB	✅	USB_V3P3_G3 power pins are correctly connected to +3VSB (3.3V standby supply).
P18	USB_V3P3_G3_P18	+3VSB	✅	USB_V3P3_G3 power pins are correctly connected to +3VSB (3.3V standby supply).
N20	USB_V1P8_G3_N20	+V1P8A	✅	USB_V1P8_G3 power pin is correctly connected to +V1P8A (1.8V always-on supply).
N22	PCU_V3P3_G3_N22	+3VSB	✅	PCU_V3P3_G3 power pin is correctly connected to +3VSB (3.3V standby supply).
P22	RTC_VCC_P22	+RTCVCC	✅	RTC_VCC power pin is correctly connected to +RTCVCC (RTC battery backup supply).
U16	USB_VSSA_U16	GND	✅	USB_VSSA ground pin is correctly connected to GND.
U24	UNCORE_V1P8_G3_U24	+V1P8A	✅	UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply).
U25	PMU_V1P8_G3_U25	+V1P8A	✅	UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply).
V25	PCU_V1P8_G3_V25	+V1P8A	✅	UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply).
AA18	UNCORE_V1P8_G3_AA18	+V1P8A	✅	UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply).
V18	USB_HSIC_V1P24_G3_V18	+V1P0A	✅	USB_HSIC_V1P24_G3 power pin is connected to +V1P0A (1.0V). This is acceptable when USB HSIC is not used, as indicated by a schematic note.
V24	UNCORE_V1P0_S0IX_V24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222).
Y24	UNCORE_V1P0_S0IX_Y24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222).
Y22	UNCORE_V1P0_S0IX_Y22	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222).
AN29	UNCORE_V1P0_S0IX_AN29	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222).
AN30	UNCORE_V1P0_S0IX_AN30	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222).
AF21	UNCORE_V1P0_S0IX_AF21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222).
AG21	UNCORE_V1P0_S0IX_AG21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222).
V32	SVID_V1P0_S3_V32	+V1P0S	✅	SVID_V1P0_S3 power pin is correctly connected to +V1P0S (1.0V S3 suspend supply).
AA25	UNCORE_V1P35_S0IX_F5_AA25	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3.
AD36	DRAM_V1P35_S0IX_F1_AD36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3.
AF19	UNCORE_V1P35_S0IX_F6	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3.
V36	UNCORE_V1P35_S0IX_F3_V36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3.
U36	UNCORE_V1P35_S0IX_F4_U36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3.
AG32	UNCORE_V1P35_S0IX_F2_AG32	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3.
AG19	UNCORE_V1P35_S0IX_F1_AG19	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3.
AA36	DRAM_V1P0_S0IX_AA36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
AD35	DRAM_V1P0_S0IX_AD35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
AF35	DRAM_V1P0_S0IX_AF35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
AF36	DRAM_V1P0_S0IX_AF36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
AJ36	DRAM_V1P0_S0IX_AJ36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
AK35	DRAM_V1P0_S0IX_AK35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
AK36	DRAM_V1P0_S0IX_AK36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
Y35	DRAM_V1P0_S0IX_Y35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
Y36	DRAM_V1P0_S0IX_Y36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265).
AD16	VSS_AD16	VCC_VSS_V1P2	✅	VSS ground pins are connected to VCC_VSS_V1P2 net which connects to GND through R216 (0 ohm resistor). This unusual configuration may be intentional for current sensing or isolation.
AD18	VSS_AD18	VCC_VSS_V1P2	✅	VSS ground pins are connected to VCC_VSS_V1P2 net which connects to GND through R216 (0 ohm resistor). This unusual configuration may be intentional for current sensing or isolation.
BD1	VGA_V1P35_S3_F1_BD1	VCC_CRT_V1P35	✅	VGA_V1P35_S3_F1 power pin is correctly connected to VCC_CRT_V1P35, which is derived from +V1P35S through ferrite bead FB4.
AF16	UNCORE_V1P0_S3_AF16	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AF18	UNCORE_V1P0_S3_AF18	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
G1	UNCORE_V1P0_S3_G1	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
Y18	UNCORE_V1P0_S3_Y18	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AJ18	DDI_V1P0_S0IX_AJ18	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AK19	DDI_V1P0_S0IX_AK19	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AK21	DDI_V1P0_S0IX_AK21	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AM16	DDI_V1P0_S0IX_AM16	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AJ19	ICLK_V1P35_S3_F1_AJ19	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which is derived from +V1P35S through ferrite bead FB5.
AG18	ICLK_V1P35_S3_F2	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which is derived from +V1P35S through ferrite bead FB5.
BJ6	VGA_V1P0_S3_BJ6	+V1P0S	✅	VGA_V1P0_S3 power pin is correctly connected to +V1P0S (1.0V S3 suspend supply).
AM27	LPC_V1P8V3P3_S3_AM27	+VCC3S	✅	LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V S3 suspend supply).
AN27	SD3_V1P8V3P3_S3_AN27	+VCC3S	✅	LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V S3 suspend supply).
AM30	UNCORE_V1P8_S3_AM30	+V1P8S	✅	UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S (1.8V S3 suspend supply).
AN32	UNCORE_V1P8_S3_AN32	+V1P8S	✅	UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S (1.8V S3 suspend supply).
U38	UNCORE_V1P8_S3_U38	+V1P8S	✅	UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S (1.8V S3 suspend supply).
AM32	HDA_LPE_V1P5V1P8_S3_AM32	+V1P8S	✅	HDA_LPE_V1P5V1P8_S3 power pin is correctly connected to +V1P8S (1.8V S3 suspend supply).
AN16	VSSA_AN16	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A3	VSS_A3_A3	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A5	VSS_A5_A5	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A6	VSS_A6_A6	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A11			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A15			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A19			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A23			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A27			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A31			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A35			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A39			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A43			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A47			✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A49	VSS_A49_A49	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A51	VSS_A51_A51	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
A52	VSS_A52_A52	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
B2	VSS_B2_B2	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
B52	VSS_B52_B52	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
B53	VSS_B53_B53	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BE1	VSS_BE1_BE1	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BE53	VSS_BE53_BE53	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BG1	VSS_BG1_BG1	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BG53	VSS_BG53_BG53	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BH1	VSS_BH1_BH1	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BH2	VSS_BH2_BH2	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BH52	VSS_BH52_BH52	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BH53	VSS_BH53_BH53	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BJ2	VSS_BJ2_BJ2	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BJ3	VSS_BJ3_BJ3	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BJ5	VSS_BJ5_BJ5	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BJ49	VSS_BJ49_BJ49	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BJ51	VSS_BJ51_BJ51	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
BJ52	VSS_BJ52_BJ52	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
C1	VSS_C1_C1	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
C53	VSS_C53_C53	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
E1	VSS_E1_E1	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
E53	VSS_E53_E53	GND	✅	Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216.
AN18	PCIE_SATA_V1P0_S3_AN18	+V1P0S	✅	PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AN19	SATA_V1P0_S3_AN19	+V1P0S	✅	PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AN21	PCIE_V1P0_S3_AN21	+V1P0S	✅	PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AM21	PCIE_V1P0_S3_AM21	+V1P0S	✅	PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AM18	PCIE_V1P0_S3_AM18	+V1P0S	✅	PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AK18	PCIE_V1P0_S3_AK18	+V1P0S	✅	PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply).
AN24	VGA_V3P3_S3_AN24	+VCC3S	✅	VGA_V3P3_S3 power pin is correctly connected to +VCC3S (3.3V S3 suspend supply).
AN25	GPIO_V1P0_S3_AN25	+V1P0S	✅	GPIO_V1P0_S3 power pin is correctly connected to +V1P0S (1.0V S3 suspend supply).

FB3 - FERRITE_600OHM_1.3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to +V1P35S supply rail. This pin receives the 1.35V supply voltage that will be filtered before reaching the VCC_UNCORE_V1P35 rail.
2	2	VCC_UNCORE_V1P35	✅	Output pin connected to VCC_UNCORE_V1P35 rail. This pin provides filtered 1.35V power to the uncore voltage domain of the CPU.

FB4 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to +V1P35S supply rail, providing the source voltage for the VGA 1.35V power domain.
2	2	VCC_CRT_V1P35	✅	Output pin connected to VCC_CRT_V1P35 rail which supplies the VGA power domain on CPU1. The ferrite bead provides EMI filtering between the source supply and the VGA power domain.

C164 - 22uF 20% 6.3V 0805 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin providing return path for decoupling capacitor on VCC_CRT_V1P35 rail.
2	2	VCC_CRT_V1P35	✅	Power pin connected to VCC_CRT_V1P35 rail. This 22uF bulk capacitor provides low-frequency decoupling and charge storage for the VGA 1.35V power domain.

C28 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin providing return path for decoupling capacitor on VCC_CRT_V1P35 rail.
2	2	VCC_CRT_V1P35	✅	Power pin connected to VCC_CRT_V1P35 rail. This 10uF capacitor complements C164 to provide decoupling across a wider frequency range for the VGA 1.35V power domain.

FB5 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input side of ferrite bead connected to +V1P35S main power rail. This connection is correct.
2	2	VCC_ICLK_V1P35	✅	Output side of ferrite bead connected to VCC_ICLK_V1P35, providing filtered power to CPU1 integrated clock circuitry. This connection is correct.

C26 - 1uF 10% 16V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for decoupling capacitor. This connection is correct.
2	2	VCC_ICLK_V1P35	✅	Connected to VCC_ICLK_V1P35 rail, providing local decoupling for integrated clock power. This connection is correct.

C27 - 1uF 10% 16V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for decoupling capacitor. This connection is correct.
2	2	VCC_ICLK_V1P35	✅	Connected to VCC_ICLK_V1P35 rail, providing additional local decoupling for integrated clock power. This connection is correct.

R216 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VSS_V1P2	✅	0-ohm jumper resistor connecting VCC_VSS_V1P2 net to GND. This provides a ground connection for CPU1 pins AD16 and AD18 (VSS ground pins) through a separate net topology.
2	2	GND	✅	0-ohm jumper resistor connecting VCC_VSS_V1P2 net to GND. This provides a ground connection for CPU1 pins AD16 and AD18 (VSS ground pins) through a separate net topology.

TP4 - TEST_POINT_0.040_SMT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$10N1595	✅	Test point connected to CPU1 reserved pin F1 via net $10N1595. Component is marked DNI (Do Not Install), making this connection electrically absent in production, which is acceptable for a reserved processor pin.

D7 - D5V0L1B2LP-7B ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Pin N connects to GND. This is the ground reference terminal of the bidirectional TVS diode.
P	P	+5VSB	✅	Pin P connects to +5VSB power rail for ESD/transient protection. This is the protected line terminal of the bidirectional TVS diode.

J8 - 3430-0212 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 connects to +5VSB power rail. This is the power input pin of the connector.
2	2	GND	✅	Pin 2 connects to GND. This is the ground return pin of the connector.

C153 - 0.1uF ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 connects to +5VSB power rail. This is the positive terminal of the bypass capacitor.
2	2	GND	✅	Pin 2 connects to GND. This is the negative terminal of the bypass capacitor.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A11	VSS1	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A15	VSS2	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A19	VSS3	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A23	VSS4	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A27	VSS5	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A31	VSS6	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A35	VSS7	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A39	VSS8	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A43	VSS9	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A47	VSS10	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA1	VSS11	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA3	VSS15	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA16	VSS12	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA19	VSS13	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA21	VSS14	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA32	VSS16	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA35	VSS17	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA38	VSS18	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA53	VSS19	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB4	VSS21	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB6	VSS28	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB10	VSS20	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB41	VSS22	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB45	VSS23	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB47	VSS24	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB48	VSS25	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB50	VSS26	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB51	VSS27	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC16	VSS29	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC18	VSS30	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC19	VSS31	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC21	VSS32	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC25	VSS33	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC33	VSS34	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC35	VSS35	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC36	VSS36	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC38	VSS37	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD7	VSS44	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD19	VSS38	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD21	VSS39	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD25	VSS40	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD32	VSS41	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD33	VSS42	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD47	VSS43	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE1	VSS45	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE3	VSS49	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE4	VSS50	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE6	VSS60	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE8	VSS61	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE9	VSS62	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE11	VSS46	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE12	VSS47	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE14	VSS48	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE40	VSS51	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE42	VSS52	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE43	VSS53	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE45	VSS54	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE46	VSS55	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE48	VSS56	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE50	VSS57	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE51	VSS58	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE53	VSS59	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF10	VSS63	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF12	VSS64	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF25	VSS65	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF32	VSS66	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF47	VSS67	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG16	VSS68	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG25	VSS69	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG36	VSS70	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG38	VSS71	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH4	VSS72	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH6	VSS110	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH7	VSS75	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH9	VSS76	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH41	VSS73	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH45	VSS74	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH47	VSS106	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH48	VSS107	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH50	VSS108	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH51	VSS109	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ1	VSS77	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ3	VSS83	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ16	VSS78	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ21	VSS79	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ25	VSS80	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ27	VSS81	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ29	VSS82	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ30	VSS84	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ32	VSS85	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ33	VSS86	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ35	VSS87	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ38	VSS88	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ53	VSS89	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK10	VSS90	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK14	VSS91	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK16	VSS92	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK33	VSS93	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK41	VSS94	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK44	VSS95	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM7	VSS113	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM12	VSS96	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM19	VSS97	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM24	VSS98	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM25	VSS99	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM29	VSS100	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM33	VSS101	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM35	VSS102	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM36	VSS103	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM40	VSS104	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM44	VSS111	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM51	VSS112	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN1	VSS114	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN3	VSS119	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN5	VSS131	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN6	VSS134	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN8	VSS135	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN9	VSS136	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN11	VSS115	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN12	VSS116	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN14	VSS117	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN22	VSS118	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN33	VSS120	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN35	VSS121	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN36	VSS122	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN38	VSS123	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN40	VSS124	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN42	VSS125	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN43	VSS126	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN45	VSS127	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN46	VSS128	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN48	VSS129	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN49	VSS130	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN51	VSS132	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN53	VSS133	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AP40	VSS137	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT4	VSS146	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT12	VSS138	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT16	VSS139	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT19	VSS140	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT24	VSS141	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT27	VSS142	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT30	VSS143	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT35	VSS144	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT38	VSS145	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT47	VSS147	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT52	VSS148	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU1	VSS149	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU3	VSS151	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU24	VSS150	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU30	VSS152	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU38	VSS153	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU51	VSS154	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV7	VSS167	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV12	VSS155	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV13	VSS156	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV14	VSS157	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV18	VSS158	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV19	VSS159	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV24	VSS160	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV27	VSS161	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV30	VSS162	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV35	VSS163	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV38	VSS164	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV47	VSS165	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV51	VSS166	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW3	VSS171	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW13	VSS168	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW19	VSS169	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW27	VSS170	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW35	VSS172	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY4	VSS177	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY9	VSS179	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY10	VSS173	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY22	VSS174	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY32	VSS175	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY36	VSS176	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY50	VSS178	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA14	VSS180	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA19	VSS181	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA22	VSS182	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA27	VSS183	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA32	VSS184	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA35	VSS185	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA40	VSS186	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA53	VSS187	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BB19	VSS188	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BB27	VSS189	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BB35	VSS190	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC20	VSS191	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC22	VSS192	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC26	VSS193	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC28	VSS194	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC32	VSS195	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC34	VSS196	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC42	VSS197	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD19	VSS198	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD24	VSS199	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD27	VSS200	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD30	VSS201	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD35	VSS202	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE2	VSS204	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE8	VSS206	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE19	VSS203	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE35	VSS205	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF4	VSS213	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF12	VSS207	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF16	VSS208	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF24	VSS209	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF30	VSS211	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF36	VSS212	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF38	VSS210	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG31	VSS214	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG34	VSS215	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG39	VSS216	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG42	VSS217	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG45	VSS218	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG49	VSS219	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ7	VSS230	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ11	VSS220	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ15	VSS221	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ19	VSS222	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ23	VSS223	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ27	VSS224	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ31	VSS225	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ35	VSS226	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ39	VSS227	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ43	VSS228	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ47	VSS229	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C14	VSS231	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C31	VSS232	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C34	VSS233	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C39	VSS234	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C42	VSS235	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C45	VSS236	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C49	VSS237	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D12	VSS238	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D16	VSS239	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D24	VSS240	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D30	VSS241	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D36	VSS242	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D38	VSS243	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
E8	VSS246	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
E19	VSS244	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
E35	VSS245	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F2	VSS248	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F5	VSS253	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F7	VSS254	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F19	VSS247	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F24	VSS249	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F27	VSS250	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F30	VSS251	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F35	VSS252	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G10	VSS255	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G20	VSS256	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G22	VSS257	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G26	VSS258	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G28	VSS259	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G32	VSS260	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G34	VSS261	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G42	VSS262	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
H19	VSS263	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
H27	VSS264	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
H35	VSS265	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J1	VSS266	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J16	VSS267	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J19	VSS268	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J22	VSS269	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J27	VSS270	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J32	VSS271	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J35	VSS272	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J40	VSS273	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J53	VSS274	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K4	VSS279	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K9	VSS281	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K14	VSS275	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K22	VSS276	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K32	VSS277	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K36	VSS278	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K50	VSS280	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L13	VSS282	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L19	VSS283	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L27	VSS284	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L35	VSS285	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M19	VSS286	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M26	VSS287	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M27	VSS288	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M28	VSS105	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M34	VSS289	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M35	VSS290	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M38	VSS291	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M47	VSS292	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M51	VSS293	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N1	VSS294	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N16	VSS295	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N38	VSS296	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N51	VSS297	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P4	VSS306	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P9	VSS309	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P13	VSS298	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P16	VSS299	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P19	VSS300	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P20	VSS301	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P24	VSS302	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P32	VSS303	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P35	VSS304	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P38	VSS305	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P47	VSS307	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P52	VSS308	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
T40	VSS310	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U1	VSS311	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U3	VSS316	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U5	VSS326	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U6	VSS329	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U8	VSS330	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U9	VSS331	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U11	VSS312	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U12	VSS313	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U14	VSS314	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U21	VSS315	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U30	VSS317	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U32	VSS318	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U40	VSS319	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U42	VSS320	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U43	VSS321	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U45	VSS322	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U46	VSS323	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U48	VSS324	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U49	VSS325	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U51	VSS327	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U53	VSS328	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V7	VSS340	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V12	VSS332	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V16	VSS333	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V19	VSS334	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V21	VSS335	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V35	VSS336	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V40	VSS337	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V44	VSS338	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V51	VSS339	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y7	VSS349	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y9	VSS350	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y10	VSS341	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y14	VSS342	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y16	VSS343	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y21	VSS344	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y25	VSS345	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y33	VSS346	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y41	VSS347	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y44	VSS348	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.

MEM3 - MT41K256M16HA-125:E ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
C1	VDDQ2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
R1	VDD7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
B2	VDD8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
D2	VDDQ9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
H2	VDDQ4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
K2	VDD9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
G7	VDD1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
A8	VDDQ5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
K8	VDD2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
C9	VDDQ6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
N1	VDD6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
F1	VDDQ3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
D9	VDD4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
E9	VDDQ7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
H9	VDDQ8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
N9	VDD3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
R9	VDD5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2.
A2	DQU5	M_DATA_A30	✅	DQU5 is correctly connected to M_DATA_A30.
A3	DQU7	M_DATA_A31	✅	DQU7 is correctly connected to M_DATA_A31.
A7	DQU4	M_DATA_A25	✅	DQU4 is correctly connected to M_DATA_A25.
B1	VSSQ1	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
D1	VSSQ2	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
E1	VSS1	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
G1	VSSQ3	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
M1	VSS2	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
P1	VSS3	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
T1	VSS4	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
E2	VSSQ4	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
J2	VSS5	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
B3	VSS6	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
D8	VSSQ5	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
E8	VSSQ6	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
G8	VSS7	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
J8	VSS8	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
A9	VSS9	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
B9	VSSQ7	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
F9	VSSQ8	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
G9	VSSQ9	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
M9	VSS10	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
P9	VSS11	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
T9	VSS12	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND.
B7	/DQSU	M_DQS_A_N3	✅	UDQS# is correctly connected to M_DQS_A_N3.
B8	DQU6	M_DATA_A24	✅	DQU6 is correctly connected to M_DATA_A24.
C2	DQU3	M_DATA_A27	✅	DQU3 is correctly connected to M_DATA_A27.
C3	DQU1	M_DATA_A26	✅	DQU1 is correctly connected to M_DATA_A26.
C7	DQSU	M_DQS_A_P3	✅	UDQS is correctly connected to M_DQS_A_P3.
C8	DQU2	M_DATA_A28	✅	DQU2 is correctly connected to M_DATA_A28.
D3	DMU	M_DM_A3	✅	UDM is correctly connected to M_DM_A3.
D7	DQU0	M_DATA_A29	✅	DQU0 is correctly connected to M_DATA_A29.
E3	DQL0	M_DATA_A16	✅	DQL0 is correctly connected to M_DATA_A16, forming part of the upper 16 bits of the 32-bit data bus.
E7	DML	M_DM_A2	✅	LDM is correctly connected to M_DM_A2.
F2	DQL2	M_DATA_A18	✅	DQL2 is correctly connected to M_DATA_A18.
F3	DQSL	M_DQS_A_P2	✅	LDQS is correctly connected to M_DQS_A_P2.
F7	DQL1	M_DATA_A17	✅	DQL1 is correctly connected to M_DATA_A17.
F8	DQL3	M_DATA_A19	✅	DQL3 is correctly connected to M_DATA_A19.
G2	DQL6	M_DATA_A22	✅	DQL6 is correctly connected to M_DATA_A22.
G3	/DQSL	M_DQS_A_N2	✅	LDQS# is correctly connected to M_DQS_A_N2.
H1	VREFDQ	SM_VREF_DQ1_A	✅	VREFDQ is correctly connected to SM_VREF_DQ1_A, shared with MEM2.
H3	DQL4	M_DATA_A20	✅	DQL4 is correctly connected to M_DATA_A20.
H7	DQL7	M_DATA_A23	✅	DQL7 is correctly connected to M_DATA_A23.
H8	DQL5	M_DATA_A21	✅	DQL5 is correctly connected to M_DATA_A21.
J1	NC1__ODT1_		✅	NC pins are correctly left unconnected as specified in the datasheet.
L1	NC2__/CS1_		✅	NC pins are correctly left unconnected as specified in the datasheet.
J9	NC3__CKE1_		✅	NC pins are correctly left unconnected as specified in the datasheet.
L9	NC4__ZQ1_		✅	NC pins are correctly left unconnected as specified in the datasheet.
M7	NC5		✅	NC pins are correctly left unconnected as specified in the datasheet.
J3	/RAS	M_RAS_A_L	✅	RAS# is correctly connected to M_RAS_A_L, shared with MEM2.
J7	CK	M_CLK_A_P0	✅	CK is correctly connected to M_CLK_A_P0, shared with MEM2.
K1	ODT	M_ODT_A0	✅	ODT is correctly connected to M_ODT_A0, shared with MEM2.
K3	/CAS	M_CAS_A_L	✅	CAS# is correctly connected to M_CAS_A_L, shared with MEM2.
K7	/CK	M_CLK_A_N0	✅	CK# is correctly connected to M_CLK_A_N0, shared with MEM2.
K9	CKE	M_CKE_A0	✅	CKE is correctly connected to M_CKE_A0, shared with MEM2.
L2	/CS	M_CS_A_L0	✅	CS# is correctly connected to M_CS_A_L0, shared with MEM2.
L3	/WE	M_WE_A_L	✅	WE# is correctly connected to M_WE_A_L, shared with MEM2.
L7	A10_AP_	M_MA_A10	✅	A10/AP is correctly connected to M_MA_A10, shared with MEM2.
L8	ZQ	M_ZQ2	✅	ZQ is correctly connected to M_ZQ2, which has a 240Ω resistor (R327) to ground as required.
M2	BA0	M_BS_A0	✅	BA0 is correctly connected to M_BS_A0, shared with MEM2.
M3	BA2	M_BS_A2	✅	BA2 is correctly connected to M_BS_A2, shared with MEM2.
M8	VREFCA	SM_VREF_CA1_A	✅	VREFCA is correctly connected to SM_VREF_CA1_A, shared with MEM2.
N2	A3	M_MA_A3	✅	A3 is correctly connected to M_MA_A3, shared with MEM2.
N3	A0	M_MA_A0	✅	A0 is correctly connected to M_MA_A0, shared with MEM2.
N7	A12_/BC_	M_MA_A12	✅	A12/BC# is correctly connected to M_MA_A12, shared with MEM2.
N8	BA1	M_BS_A1	✅	BA1 is correctly connected to M_BS_A1, shared with MEM2.
P2	A5	M_MA_A5	✅	A5 is correctly connected to M_MA_A5, shared with MEM2.
P3	A2	M_MA_A2	✅	A2 is correctly connected to M_MA_A2, shared with MEM2.
P7	A1	M_MA_A1	✅	A1 is correctly connected to M_MA_A1, shared with MEM2.
P8	A4	M_MA_A4	✅	A4 is correctly connected to M_MA_A4, shared with MEM2.
R2	A7	M_MA_A7	✅	A7 is correctly connected to M_MA_A7, shared with MEM2.
R3	A9	M_MA_A9	✅	A9 is correctly connected to M_MA_A9, shared with MEM2.
R7	A11	M_MA_A11	✅	A11 is correctly connected to M_MA_A11, shared with MEM2.
R8	A6	M_MA_A6	✅	A6 is correctly connected to M_MA_A6, shared with MEM2.
T2	/RESET	M_A_RST_L	✅	RESET# is correctly connected to M_A_RST_L, shared with MEM2.
T3	A13	M_MA_A13	✅	A13 is correctly connected to M_MA_A13, shared with MEM2.
T7	A14	M_MA_A14	✅	A14 is correctly connected to M_MA_A14, shared with MEM2.
T8	A8	M_MA_A8	✅	A8 is correctly connected to M_MA_A8, shared with MEM2.

MEM2 - MT41K256M16HA-125:E ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
C1	VDDQ2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
R1	VDD7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
B2	VDD8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
D2	VDDQ9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
H2	VDDQ4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
K2	VDD9	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
G7	VDD1	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
A8	VDDQ5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
K8	VDD2	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
C9	VDDQ6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
N1	VDD6	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
F1	VDDQ3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
D9	VDD4	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
E9	VDDQ7	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
H9	VDDQ8	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
N9	VDD3	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
R9	VDD5	+VDIMM	✅	Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation.
A2	DQU5	M_DATA_A15	✅	DQU5 is correctly connected to M_DATA_A15.
A3	DQU7	M_DATA_A14	✅	DQU7 is correctly connected to M_DATA_A14.
A7	DQU4	M_DATA_A13	✅	DQU4 is correctly connected to M_DATA_A13.
B1	VSSQ1	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
D1	VSSQ2	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
E1	VSS1	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
G1	VSSQ3	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
M1	VSS2	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
P1	VSS3	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
T1	VSS4	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
E2	VSSQ4	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
J2	VSS5	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
B3	VSS6	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
D8	VSSQ5	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
E8	VSSQ6	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
G8	VSS7	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
J8	VSS8	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
A9	VSS9	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
B9	VSSQ7	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
F9	VSSQ8	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
G9	VSSQ9	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
M9	VSS10	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
P9	VSS11	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
T9	VSS12	GND	✅	Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane.
B7	/DQSU	M_DQS_A_N1	✅	UDQS# (upper byte data strobe complement) is correctly connected to M_DQS_A_N1.
B8	DQU6	M_DATA_A12	✅	DQU6 is correctly connected to M_DATA_A12.
C2	DQU3	M_DATA_A11	✅	DQU3 is correctly connected to M_DATA_A11.
C3	DQU1	M_DATA_A10	✅	DQU1 is correctly connected to M_DATA_A10.
C7	DQSU	M_DQS_A_P1	✅	UDQS (upper byte data strobe positive) is correctly connected to M_DQS_A_P1.
C8	DQU2	M_DATA_A8	✅	DQU2 is correctly connected to M_DATA_A8.
D3	DMU	M_DM_A1	✅	UDM (upper byte data mask) is correctly connected to M_DM_A1.
D7	DQU0	M_DATA_A9	✅	DQU0 is correctly connected to M_DATA_A9.
E3	DQL0	M_DATA_A0	✅	DQL0 (lower byte data bit 0) is correctly connected to M_DATA_A0, forming part of the 32-bit data bus lower 16 bits.
E7	DML	M_DM_A0	✅	LDM (lower byte data mask) is correctly connected to M_DM_A0.
F2	DQL2	M_DATA_A2	✅	DQL2 is correctly connected to M_DATA_A2.
F3	DQSL	M_DQS_A_P0	✅	LDQS (lower byte data strobe positive) is correctly connected to M_DQS_A_P0.
F7	DQL1	M_DATA_A1	✅	DQL1 is correctly connected to M_DATA_A1.
F8	DQL3	M_DATA_A3	✅	DQL3 is correctly connected to M_DATA_A3.
G2	DQL6	M_DATA_A6	✅	DQL6 is correctly connected to M_DATA_A6.
G3	/DQSL	M_DQS_A_N0	✅	LDQS# (lower byte data strobe complement) is correctly connected to M_DQS_A_N0.
H1	VREFDQ	SM_VREF_DQ1_A	✅	VREFDQ (reference voltage for data) is correctly connected to SM_VREF_DQ1_A, which is generated by voltage divider R310/R325 to provide VDD/2. Shared with MEM3.
H3	DQL4	M_DATA_A4	✅	DQL4 is correctly connected to M_DATA_A4.
H7	DQL7	M_DATA_A7	✅	DQL7 is correctly connected to M_DATA_A7.
H8	DQL5	M_DATA_A5	✅	DQL5 is correctly connected to M_DATA_A5.
J1	NC1__ODT1_		✅	NC (no connect) pins are correctly left unconnected as specified in the datasheet.
L1	NC2__/CS1_		✅	NC (no connect) pins are correctly left unconnected as specified in the datasheet.
J9	NC3__CKE1_		✅	NC (no connect) pins are correctly left unconnected as specified in the datasheet.
L9	NC4__ZQ1_		✅	NC (no connect) pins are correctly left unconnected as specified in the datasheet.
M7	NC5		✅	NC (no connect) pins are correctly left unconnected as specified in the datasheet.
J3	/RAS	M_RAS_A_L	✅	RAS# (row address strobe) is correctly connected to M_RAS_A_L, shared with MEM3.
J7	CK	M_CLK_A_P0	✅	CK (differential clock positive) is correctly connected to M_CLK_A_P0, shared with MEM3.
K1	ODT	M_ODT_A0	✅	ODT (on-die termination enable) is correctly connected to M_ODT_A0, shared with MEM3.
K3	/CAS	M_CAS_A_L	✅	CAS# (column address strobe) is correctly connected to M_CAS_A_L, shared with MEM3.
K7	/CK	M_CLK_A_N0	✅	CK# (differential clock complement) is correctly connected to M_CLK_A_N0, shared with MEM3.
K9	CKE	M_CKE_A0	✅	CKE (clock enable) is correctly connected to M_CKE_A0, shared with MEM3.
L2	/CS	M_CS_A_L0	✅	CS# (chip select) is correctly connected to M_CS_A_L0, shared with MEM3.
L3	/WE	M_WE_A_L	✅	WE# (write enable) is correctly connected to M_WE_A_L, shared with MEM3.
L7	A10_AP_	M_MA_A10	✅	A10/AP (address bit 10 with auto-precharge) is correctly connected to M_MA_A10, shared with MEM3.
L8	ZQ	M_ZQ1	✅	ZQ (calibration reference) is correctly connected to M_ZQ1, which has a 240Ω resistor (R140) to ground as required by the datasheet.
M2	BA0	M_BS_A0	✅	BA0 (bank address bit 0) is correctly connected to M_BS_A0, shared with MEM3.
M3	BA2	M_BS_A2	✅	BA2 is correctly connected to M_BS_A2, shared with MEM3.
M8	VREFCA	SM_VREF_CA1_A	✅	VREFCA (reference voltage for control/address) is correctly connected to SM_VREF_CA1_A, which is generated by voltage divider R144/R326 to provide VDD/2. Shared with MEM3.
N2	A3	M_MA_A3	✅	A3 is correctly connected to M_MA_A3, shared with MEM3.
N3	A0	M_MA_A0	✅	A0 (address bit 0) is correctly connected to M_MA_A0, shared with MEM3.
N7	A12_/BC_	M_MA_A12	✅	A12/BC# (address bit 12 with burst chop) is correctly connected to M_MA_A12, shared with MEM3.
N8	BA1	M_BS_A1	✅	BA1 is correctly connected to M_BS_A1, shared with MEM3.
P2	A5	M_MA_A5	✅	A5 is correctly connected to M_MA_A5, shared with MEM3.
P3	A2	M_MA_A2	✅	A2 is correctly connected to M_MA_A2, shared with MEM3.
P7	A1	M_MA_A1	✅	A1 is correctly connected to M_MA_A1, shared with MEM3.
P8	A4	M_MA_A4	✅	A4 is correctly connected to M_MA_A4, shared with MEM3.
R2	A7	M_MA_A7	✅	A7 is correctly connected to M_MA_A7, shared with MEM3.
R3	A9	M_MA_A9	✅	A9 is correctly connected to M_MA_A9, shared with MEM3.
R7	A11	M_MA_A11	✅	A11 is correctly connected to M_MA_A11, shared with MEM3.
R8	A6	M_MA_A6	✅	A6 is correctly connected to M_MA_A6, shared with MEM3.
T2	/RESET	M_A_RST_L	✅	RESET# (active-low reset) is correctly connected to M_A_RST_L through series resistor R353. Shared with MEM3.
T3	A13	M_MA_A13	✅	A13 is correctly connected to M_MA_A13, shared with MEM3.
T7	A14	M_MA_A14	✅	A14 is correctly connected to M_MA_A14, shared with MEM3.
T8	A8	M_MA_A8	✅	A8 is correctly connected to M_MA_A8, shared with MEM3.

R144 - 110-0002058 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Connected to +VDIMM power supply, forming the upper connection of a voltage divider for VREFCA reference generation.
2	2	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A, the command/address reference voltage node for DDR3 memories MEM2 and MEM3.

R326 - 110-0002058 ✅

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⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the lower connection of a voltage divider for VREFCA reference generation.
2	2	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A, completing the voltage divider that generates VDD/2 reference voltage.

C133 - 123-0001056 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A to provide AC filtering and decoupling for the reference voltage.
2	2	GND	✅	Connected to GND to complete the bypass capacitor function for the VREFCA reference voltage.

C344 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A to provide additional AC filtering and decoupling for the reference voltage.
2	2	GND	✅	Connected to GND to complete the bypass capacitor function.

R310 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Upper resistor in VREFDQ voltage divider, connected to +VDIMM supply.
2	2	SM_VREF_DQ1_A	✅	Connected to SM_VREF_DQ1_A reference voltage net, forms voltage divider midpoint.

R325 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower resistor in VREFDQ voltage divider, connected to ground.
2	2	SM_VREF_DQ1_A	✅	Connected to SM_VREF_DQ1_A reference voltage net, forms voltage divider midpoint.

C124 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_DQ1_A	✅	Decoupling capacitor for VREFDQ reference voltage, positioned near MEM2.
2	2	GND	✅	Ground connection for decoupling capacitor.

C329 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_DQ1_A	✅	Decoupling capacitor for VREFDQ reference voltage, positioned near MEM3.
2	2	GND	✅	Ground connection for decoupling capacitor.

R327 - 110-0001971 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ2	✅	Connected to M_ZQ2 net, which connects to the ZQ (impedance calibration) pin of DDR3 memory device MEM3.
2	2	GND	✅	Connected to GND, providing the ground reference for the ZQ impedance calibration resistor.

R140 - 110-0001971 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ1	✅	Connected to M_ZQ1 net, which connects to the ZQ (impedance calibration) pin of DDR3 memory device MEM2.
2	2	GND	✅	Connected to GND, providing the ground reference for the ZQ impedance calibration resistor.

C287 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to GND, providing the ground reference for this decoupling capacitor.
2	2	+VCC3	✅	Pin 2 is correctly connected to +VCC3, providing decoupling for the 3.3V power rail. The capacitor remains populated even though nearby component U33 is DNI, which is acceptable for maintaining power rail stability.

P2 - 158-0001269 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	SD3_D2_R	✅	DAT2 receives the filtered SD data line 2 signal from FL1 channel 2 output.
2	CD/DAT3	SD3_D3_R	✅	CD/DAT3 receives the filtered SD data line 3 signal from FL1 channel 3 output.
3	CMD	SD3_CMD_R	✅	CMD receives the filtered SD command signal from FL1 channel 4 output.
4	VDD	+VCC3	✅	VDD is correctly connected to the +VCC3 power rail with appropriate decoupling capacitors.
5	CLOCK	SD3_CLK_R	✅	CLOCK receives the filtered SD clock signal from FL1 channel 5 output.
6	VSS	GND	✅	VSS is correctly connected to the ground plane.
7	DAT0	SD3_D0_R	✅	DAT0 receives the filtered SD data line 0 signal from FL1 channel 6 output.
8	DAT1	SD3_D1_R	✅	DAT1 receives the filtered SD data line 1 signal from FL1 channel 7 output.
9	GND	GND	✅	GND is correctly connected to the ground plane.
10	CD	SD3_CD_R	✅	CD receives the filtered card detect signal from FL1 channel 1 output.
11	GND3	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage.
12	GND4	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage.
15	GND7	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage.
16	GND8	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage.
13	GND5	FGND-uSD-Front	✅	GND5 and GND6 are connected to FGND-uSD-Front, which is the front frame ground for the SD card cage.
14	GND6	FGND-uSD-Front	✅	GND5 and GND6 are connected to FGND-uSD-Front, which is the front frame ground for the SD card cage.

FL1 - 3750-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CH1-IN	SD3_CD#	✅	CH1-IN receives the card detect signal SD3_CD# from the host side, which is pulled up to +V1P8S through R182.
2	CH2-IN	SD3_D2	✅	CH2-IN receives SD data line 2 (SD3_D2) from the host side, which is pulled up to +VCC3 through R174.
3	CH3-IN	SD3_D3	✅	CH3-IN receives SD data line 3 (SD3_D3) from the host side, which is pulled up to +VCC3 through R180.
4	CH4-IN	SD3_CMD	✅	CH4-IN receives the SD command line (SD3_CMD) from the host side, which is pulled up to +VCC3 through R173.
5	CH5-IN	SD3_CLK	✅	CH5-IN receives the SD clock line (SD3_CLK) from the host side, which is pulled up to +VCC3 through R157.
6	CH6-IN	SD3_D0	✅	CH6-IN receives SD data line 0 (SD3_D0) from the host side, which is pulled up to +VCC3 through R156.
7	CH7-IN	SD3_D1	✅	CH7-IN receives SD data line 1 (SD3_D1) from the host side, which is pulled up to +VCC3 through R155.
8	CH8-IN		✅	CH8-IN is not connected, as channel 8 is unused in this design.
9	CH8-OUT		✅	CH8-OUT is not connected, as channel 8 is unused in this design.
10	CH7-OUT	SD3_D1_R	✅	CH7-OUT provides the filtered SD data line 1 signal (SD3_D1_R) to the SD card connector pin 8.
11	CH6-OUT	SD3_D0_R	✅	CH6-OUT provides the filtered SD data line 0 signal (SD3_D0_R) to the SD card connector pin 7.
12	CH5-OUT	SD3_CLK_R	✅	CH5-OUT provides the filtered SD clock signal (SD3_CLK_R) to the SD card connector pin 5.
13	CH4-OUT	SD3_CMD_R	✅	CH4-OUT provides the filtered SD command signal (SD3_CMD_R) to the SD card connector pin 3.
14	CH3-OUT	SD3_D3_R	✅	CH3-OUT provides the filtered SD data line 3 signal (SD3_D3_R) to the SD card connector pin 2.
15	CH2-OUT	SD3_D2_R	✅	CH2-OUT provides the filtered SD data line 2 signal (SD3_D2_R) to the SD card connector pin 1.
16	CH1-OUT	SD3_CD_R	✅	CH1-OUT provides the filtered card detect signal (SD3_CD_R) to the SD card connector pin 10.
17	GND_PAD	GND	✅	GND_PAD is correctly connected to the ground plane.

R29 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CEC	✅	10kΩ pullup resistor on HDMI_CEC (CEC_A) line. This external pullup is redundant with the TPD12S016's internal 10kΩ pullup to VCCA.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing pullup voltage for HDMI_CEC.

R171 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	2.2kΩ pullup resistor providing enable signal for CT_HPD control pin of TPD12S016, enabling load switch and HPD by default.
2	2	HPD_ENB	✅	Connected to HPD_ENB net, which controls the CT_HPD pin of TPD12S016.

U2 - TPD12S016PW ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CEC_A	HDMI_CEC	✅	CEC_A pin connected to HDMI_CEC with external 10kΩ pullup to +V1P8S via R29. The external pullup is redundant with the internal 10kΩ pullup to VCCA.
2	SCL_A	HDMI_DDCCLK	✅	SCL_A pin connected to HDMI_DDCCLK with external 10kΩ pullup to +V1P8S via R28. The external pullup is redundant with the internal 10kΩ pullup to VCCA.
3	SDA_A	HDMI_DDCDAT	✅	SDA_A pin connected to HDMI_DDCDAT with external 10kΩ pullup to +V1P8S via R30. The external pullup is redundant with the internal 10kΩ pullup to VCCA.
4	HPD_A	HDMI_HPD	✅	HPD_A pin correctly connected to HDMI_HPD net as hot plug detect output to HDMI controller.
5	LS_OE	LS_OE	✅	LS_OE pin correctly connected to LS_OE net with 2.2kΩ pullup to +V1P8S via R172, enabling level shifters by default.
6	GND1	GND	✅	GND1 pin correctly connected to GND.
7	CEC_B	C_HDMI_CEC	✅	CEC_B pin correctly connected to C_HDMI_CEC net, which connects to HDMI connector CEC pin.
8	SCL_B	C_HDMI_SCL	✅	SCL_B pin correctly connected to C_HDMI_SCL net, which connects to HDMI connector SCL pin.
9	SDA_B	C_HDMI_SDA	✅	SDA_B pin correctly connected to C_HDMI_SDA net, which connects to HDMI connector SDA pin.
10	HPD_B	C_HDMI_HPD	✅	HPD_B pin correctly connected to C_HDMI_HPD net, which connects to HDMI connector hot plug detect pin.
11	VCC5V	+5VSB	✅	VCC5V pin correctly connected to +5VSB with 0.1µF decoupling capacitor C155.
12	CT_HPD	HPD_ENB	✅	CT_HPD pin correctly connected to HPD_ENB net with 2.2kΩ pullup to +V1P8S via R171, enabling load switch and HPD by default.
13	5V_OUT	+HDMI_CRT_VCC	✅	5V_OUT pin correctly connected to +HDMI_CRT_VCC with 4.7µF decoupling capacitor C157 and ferrite bead L7 to HDMI connector 5V pin.
14	GND2	GND	✅	GND2 pin correctly connected to GND.
15	CLK-	HDMI_OUT_CLK_DN	✅	CLK- pin correctly connected to HDMI_OUT_CLK_DN, routing through common mode choke L14 and AC coupling capacitor C401 to HDMI controller and connector.
16	CLK+	HDMI_OUT_CLK_DP	✅	CLK+ pin correctly connected to HDMI_OUT_CLK_DP, routing through common mode choke L14 and AC coupling capacitor C400 to HDMI controller and connector.
17	D0-	HDMI_OUT_TX0_DN	✅	D0- pin correctly connected to HDMI_OUT_TX0_DN, routing through common mode choke L15 and AC coupling capacitor C403 to HDMI controller and connector.
18	D0+	HDMI_OUT_TX0_DP	✅	D0+ pin correctly connected to HDMI_OUT_TX0_DP, routing through common mode choke L15 and AC coupling capacitor C402 to HDMI controller and connector.
19	GND3	GND	✅	GND3 pin correctly connected to GND.
20	D1-	HDMI_OUT_TX1_DN	✅	D1- pin correctly connected to HDMI_OUT_TX1_DN, routing through common mode choke L16 and AC coupling capacitor C405 to HDMI controller and connector.
21	D1+	HDMI_OUT_TX1_DP	✅	D1+ pin correctly connected to HDMI_OUT_TX1_DP, routing through common mode choke L16 and AC coupling capacitor C404 to HDMI controller and connector.
22	D2-	HDMI_OUT_TX2_DN	✅	D2- pin correctly connected to HDMI_OUT_TX2_DN, routing through common mode choke L17 and AC coupling capacitor C407 to HDMI controller and connector.
23	D2+	HDMI_OUT_TX2_DP	✅	D2+ pin correctly connected to HDMI_OUT_TX2_DP, routing through common mode choke L17 and AC coupling capacitor C406 to HDMI controller and connector.
24	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S with 0.1µF decoupling capacitor C17.

R172 - 110-0001984 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	2.2kΩ pullup resistor providing enable signal for LS_OE control pin of TPD12S016, enabling level shifters by default.
2	2	LS_OE	✅	Connected to LS_OE net, which controls the LS_OE pin of TPD12S016.

R30 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCDAT	✅	10kΩ pullup resistor on HDMI_DDCDAT (SDA_A) line. This external pullup is redundant with the TPD12S016's internal 10kΩ pullup to VCCA.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing pullup voltage for HDMI_DDCDAT.

R28 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCCLK	✅	10kΩ pullup resistor on HDMI_DDCCLK (SCL_A) line. This external pullup is redundant with the TPD12S016's internal 10kΩ pullup to VCCA.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing pullup voltage for HDMI_DDCCLK.

L17 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX2_C_DN	✅	Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity.
3	IN2	HDMI_TX2_C_DP	✅	Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity.
4	OUT2	HDMI_OUT_TX2_DP	✅	Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity.
6	OUT1	HDMI_OUT_TX2_DN	✅	Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity.

C406 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_DP	✅	Pin 1 connects to HDMI_TX2_DP, the source side of the AC coupling capacitor for the positive differential signal from the HDMI transmitter.
2	2	HDMI_TX2_C_DP	✅	Pin 2 connects to HDMI_TX2_C_DP, the output side of the AC coupling capacitor that feeds both the common mode choke L17 pin 3 and termination resistor R802.

C407 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_DN	✅	Pin 1 connects to HDMI_TX2_DN, the source side of the AC coupling capacitor for the negative differential signal from the HDMI transmitter.
2	2	HDMI_TX2_C_DN	✅	Pin 2 connects to HDMI_TX2_C_DN, the output side of the AC coupling capacitor that feeds both the common mode choke L17 pin 1 and termination resistor R801.

R801 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_C_DN	✅	Pin 1 connects to HDMI_TX2_C_DN, providing a termination path for the negative differential signal after AC coupling.
2	2	HDMI_TERM	✅	Pin 2 connects to HDMI_TERM, which is pulled to ground through Q101 when enabled, creating a termination network for all HDMI differential pairs.

R802 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX2_C_DP	✅	Pin 1 connects to HDMI_TX2_C_DP, providing a termination path for the positive differential signal after AC coupling.
2	2	HDMI_TERM	✅	Pin 2 connects to HDMI_TERM, which is pulled to ground through Q101 when enabled, creating a termination network for all HDMI differential pairs.

C404 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_DP	✅	Pin 1 correctly connected to HDMI_TX1_DP, the source-side positive signal of the TX1 differential pair before AC coupling.
2	2	HDMI_TX1_C_DP	✅	Pin 2 correctly connected to HDMI_TX1_C_DP, providing AC coupling to the common mode choke input (L16 pin 3) and termination network (R804).

C405 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_DN	✅	Pin 1 correctly connected to HDMI_TX1_DN, the source-side negative signal of the TX1 differential pair before AC coupling.
2	2	HDMI_TX1_C_DN	✅	Pin 2 correctly connected to HDMI_TX1_C_DN, providing AC coupling to the common mode choke input (L16 pin 1) and termination network (R803).

R803 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_C_DN	✅	Pin 1 correctly connected to HDMI_TX1_C_DN, providing termination for the negative differential signal after AC coupling.
2	2	HDMI_TERM	✅	Pin 2 correctly connected to HDMI_TERM, a common termination point that can be switched to ground via Q101 for power management or mode control.

R804 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX1_C_DP	✅	Pin 1 correctly connected to HDMI_TX1_C_DP, providing termination for the positive differential signal after AC coupling.
2	2	HDMI_TERM	✅	Pin 2 correctly connected to HDMI_TERM, providing symmetric termination with R803 for the TX1 differential pair within the switchable termination network.

L16 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX1_C_DN	✅	IN1 pin correctly connected to HDMI_TX1_C_DN, the negative line of the HDMI TX1 differential pair after AC coupling.
3	IN2	HDMI_TX1_C_DP	✅	IN2 pin correctly connected to HDMI_TX1_C_DP, the positive line of the HDMI TX1 differential pair after AC coupling.
4	OUT2	HDMI_OUT_TX1_DP	✅	OUT2 pin correctly connected to HDMI_OUT_TX1_DP, routing the positive line to the ESD protection device U2 and HDMI connector P1.
6	OUT1	HDMI_OUT_TX1_DN	✅	OUT1 pin correctly connected to HDMI_OUT_TX1_DN, routing the negative line to the ESD protection device U2 and HDMI connector P1.

C402 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_DP	✅	Pin 1 correctly connected to HDMI_TX0_DP, the source side of the AC coupling capacitor for the positive differential signal.
2	2	HDMI_TX0_C_DP	✅	Pin 2 correctly connected to HDMI_TX0_C_DP, the output side of the AC coupling capacitor feeding the common mode choke and DC bias restoration network.

C403 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_DN	✅	Pin 1 correctly connected to HDMI_TX0_DN, the source side of the AC coupling capacitor for the negative differential signal.
2	2	HDMI_TX0_C_DN	✅	Pin 2 correctly connected to HDMI_TX0_C_DN, the output side of the AC coupling capacitor feeding the common mode choke and DC bias restoration network.

R805 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_C_DN	✅	Pin 1 correctly connected to HDMI_TX0_C_DN, providing DC bias path for the AC-coupled negative differential signal.
2	2	HDMI_TERM	✅	Pin 2 correctly connected to HDMI_TERM, which provides a switchable ground reference through Q101 for DC biasing.

R806 - 1120-0119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_TX0_C_DP	✅	Pin 1 correctly connected to HDMI_TX0_C_DP, providing DC bias path for the AC-coupled positive differential signal.
2	2	HDMI_TERM	✅	Pin 2 correctly connected to HDMI_TERM, providing symmetric termination with R805.

L15 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX0_C_DN	✅	IN1 pin correctly connected to HDMI_TX0_C_DN, the negative line of the TX0 differential pair after AC coupling.
3	IN2	HDMI_TX0_C_DP	✅	IN2 pin correctly connected to HDMI_TX0_C_DP, the positive line of the TX0 differential pair after AC coupling.
4	OUT2	HDMI_OUT_TX0_DP	✅	OUT2 pin correctly connected to HDMI_OUT_TX0_DP, routing the filtered positive signal to the HDMI protection IC and connector.
6	OUT1	HDMI_OUT_TX0_DN	✅	OUT1 pin correctly connected to HDMI_OUT_TX0_DN, routing the filtered negative signal to the HDMI protection IC and connector.

L14 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_CLK_C_DN	✅	IN1 pin receives the negative side of the AC-coupled HDMI clock differential pair (HDMI_CLK_C_DN) and passes it through the common mode choke to filter common mode noise.
3	IN2	HDMI_CLK_C_DP	✅	IN2 pin receives the positive side of the AC-coupled HDMI clock differential pair (HDMI_CLK_C_DP) and passes it through the common mode choke to filter common mode noise.
4	OUT2	HDMI_OUT_CLK_DP	✅	OUT2 pin outputs the filtered positive side of the HDMI clock differential pair to the ESD protection IC (U2) and HDMI connector (P1).
6	OUT1	HDMI_OUT_CLK_DN	✅	OUT1 pin outputs the filtered negative side of the HDMI clock differential pair to the ESD protection IC (U2) and HDMI connector (P1).

P1 - 158-0004513 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	HPLG	C_HDMI_HPD	✅	HPLG (Hot Plug Detect) is correctly connected to C_HDMI_HPD, which routes through U2 (TPD12S016PW) for ESD protection and control.
2	NC		✅	Pin 2 (NC) is not connected, which is correct for micro HDMI Type D connectors where this pin is reserved.
3	DAT2+	HDMI_OUT_TX2_DP	✅	DAT2+ and DAT2- are correctly connected to HDMI_OUT_TX2_DP and HDMI_OUT_TX2_DN respectively, forming the TMDS data channel 2 differential pair with proper polarity.
5	DAT2-	HDMI_OUT_TX2_DN	✅	DAT2+ and DAT2- are correctly connected to HDMI_OUT_TX2_DP and HDMI_OUT_TX2_DN respectively, forming the TMDS data channel 2 differential pair with proper polarity.
4	DAT2_S	GND	✅	DAT2_S (shield for data pair 2) is correctly connected to GND for proper shielding of the differential pair.
6	DAT1+	HDMI_OUT_TX1_DP	✅	DAT1+ and DAT1- are correctly connected to HDMI_OUT_TX1_DP and HDMI_OUT_TX1_DN respectively, forming the TMDS data channel 1 differential pair with proper polarity.
8	DAT1-	HDMI_OUT_TX1_DN	✅	DAT1+ and DAT1- are correctly connected to HDMI_OUT_TX1_DP and HDMI_OUT_TX1_DN respectively, forming the TMDS data channel 1 differential pair with proper polarity.
7	DAT1_S	GND	✅	DAT1_S (shield for data pair 1) is correctly connected to GND for proper shielding of the differential pair.
9	DAT0+	HDMI_OUT_TX0_DP	✅	DAT0+ and DAT0- are correctly connected to HDMI_OUT_TX0_DP and HDMI_OUT_TX0_DN respectively, forming the TMDS data channel 0 differential pair with proper polarity.
11	DAT0-	HDMI_OUT_TX0_DN	✅	DAT0+ and DAT0- are correctly connected to HDMI_OUT_TX0_DP and HDMI_OUT_TX0_DN respectively, forming the TMDS data channel 0 differential pair with proper polarity.
10	DAT0_S	GND	✅	DAT0_S (shield for data pair 0) is correctly connected to GND for proper shielding of the differential pair.
12	CLK+	HDMI_OUT_CLK_DP	✅	CLK+ and CLK- are correctly connected to HDMI_OUT_CLK_DP and HDMI_OUT_CLK_DN respectively, forming the TMDS clock differential pair with proper polarity.
14	CLK-	HDMI_OUT_CLK_DN	✅	CLK+ and CLK- are correctly connected to HDMI_OUT_CLK_DP and HDMI_OUT_CLK_DN respectively, forming the TMDS clock differential pair with proper polarity.
13	CLK_S	GND	✅	CLK_S (shield for clock pair) is correctly connected to GND for proper shielding of the differential pair.
15	CEC	C_HDMI_CEC	✅	CEC (Consumer Electronics Control) is correctly connected to C_HDMI_CEC, which routes through U2 for ESD protection and level shifting, with proper pull-up resistor on the source side.
16	DDC/CEC_GND	GND	✅	DDC/CEC_GND is correctly connected to GND, providing the ground reference for DDC and CEC signals.
17	SCL	C_HDMI_SCL	✅	SCL (DDC clock) is correctly connected to C_HDMI_SCL, which routes through U2 for ESD protection and level shifting, with proper pull-up resistor on the source side.
18	SDA	C_HDMI_SDA	✅	SDA (DDC data) is correctly connected to C_HDMI_SDA, which routes through U2 for ESD protection and level shifting, with proper pull-up resistor on the source side.
19	+5V	D5_0V_HDMI	✅	+5V power pin is correctly connected to D5_0V_HDMI, which is sourced from U2 through a ferrite bead for filtering, with proper current limiting and decoupling.
20	MTG1	GND_EARTH	✅	Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground.
21	MTG2	GND_EARTH	✅	Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground.
22	MTG3	GND_EARTH	✅	Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground.
23	MTG4	GND_EARTH	✅	Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground.

C17 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin of decoupling capacitor for +V1P8S rail.
2	2	+V1P8S	✅	Power pin of decoupling capacitor connected to +V1P8S rail, which supplies U2 VCCA pin.

C155 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin of decoupling capacitor for +5VSB rail.
2	2	+5VSB	✅	Power pin of decoupling capacitor connected to +5VSB rail, which supplies U2 VCC5V pin.

L7 - 126-0001418 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+HDMI_CRT_VCC	✅	Input terminal of ferrite bead connected to +HDMI_CRT_VCC from U2 5V_OUT pin.
2	P2	D5_0V_HDMI	✅	Output terminal of ferrite bead connected to D5_0V_HDMI, which supplies 5V to the HDMI connector.

C157 - 123-0001144 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+HDMI_CRT_VCC	✅	Power pin of bulk decoupling capacitor connected to +HDMI_CRT_VCC, which is the 5V output from U2.
2	2	GND	✅	Ground pin of bulk decoupling capacitor for +HDMI_CRT_VCC rail.

R809 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$15N747	✅	Connected to Q101 gate through net $15N747, providing the gate drive path.
2	2	+VCC3	✅	Connected to +VCC3 power rail, providing gate drive voltage through the 0-ohm resistor.

Q101 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	HDMI_TERM	✅	Drain is connected to HDMI_TERM net, which connects to eight 619-ohm termination resistors (R801-R808) for HDMI differential signal pairs. When the MOSFET is ON, it provides a ground path for the termination network.
G	GATE	$15N747	✅	Gate is connected through R809 (0-ohm resistor) to +VCC3 power rail. This configuration keeps the MOSFET always ON when power is present, making the HDMI termination always active rather than switchable.
S	SOURCE	GND	✅	Source is correctly connected to GND, providing the ground reference for the N-channel MOSFET low-side switch.

C16 - 123-0004415 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	C16 is a 150pF 1KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection. It is marked DNI (Do Not Install) and is therefore not populated.
2	2	GND_EARTH	✅	C16 is a 150pF 1KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection. It is marked DNI (Do Not Install) and is therefore not populated.

C161 - 2267-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	C161 is a 1000pF 3KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection in the HDMI interface. The connection is correct and appropriate for this application.
2	2	GND_EARTH	✅	C161 is a 1000pF 3KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection in the HDMI interface. The connection is correct and appropriate for this application.

U32 - AP2172MPG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	Ground pin correctly connected to GND net, providing the return path for the device.
2	IN	+USBVCC	✅	Input power pin correctly connected to +USBVCC, which is derived from +5VSB through ferrite bead FB13 with appropriate bypass capacitors C92, C93, and C94.
3	EN1	USB_HOST_EN0	✅	Enable input for channel 1 correctly connected to USB_HOST_EN0, which is driven by level translator U4 from SOC_USB_HOST_EN0 signal. Pull-down resistor R112 is marked DNI, indicating active drive is used.
4	EN2	USB_HOST_EN1	✅	Enable input for channel 2 correctly connected to USB_HOST_EN1, which is driven by level translator U4 from SOC_USB_HOST_EN1 signal. Pull-down resistor R114 is marked DNI, indicating active drive is used.
5	OC2#	SOC_USB_HOST_OC1	✅	Overcurrent/fault flag output for channel 2 correctly connected to SOC_USB_HOST_OC1. This open-drain output reports over-current and over-temperature conditions for OUT2/OUTB. External pull-up resistor may be required but could be internal to SOC.
6	OUTB	USBP2	✅	Output power pin for channel 2 correctly connected to USBP2, which feeds VBUS2 through ferrite bead L2. VBUS2 has appropriate bypass capacitors (C103, C70, C234) and connects to USB port B.
7	OUTA	USBP1	✅	Output power pin for channel 1 correctly connected to USBP1, which feeds VBUS1 through ferrite bead L1. VBUS1 has appropriate bypass capacitors (C91, C82, C235) and connects to USB port A.
8	OC1#	SOC_USB_HOST_OC0	✅	Overcurrent/fault flag output for channel 1 correctly connected to SOC_USB_HOST_OC0. This open-drain output reports over-current and over-temperature conditions for OUT1/OUTA. External pull-up resistor may be required but could be internal to SOC.
9	GND_PAD	GND	✅	Exposed pad correctly connected to GND for thermal and electrical grounding as recommended by the datasheet.

U4 - NTS0102GT ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
7	VCCB	+USBVCC	❌	VCCB is connected to +USBVCC (5V), which exceeds the NTS0102GT maximum rating of 3.6V specified in the component attributes. This is a critical design error that violates the device's operating voltage range and could damage the device. Pin 7 (VCCB) is the B-side supply voltage pin for the level translator (reasoning) Pin 7 is connected to +USBVCC (from schematic) +USBVCC is derived from +5VSB through ferrite bead FB13 (from schematic) +5VSB is a standard 5V standby supply based on PC power supply naming conventions (reasoning) A ferrite bead provides high-frequency impedance but is essentially a DC short, so +USBVCC is approximately 5V at DC (reasoning) U32 (AP2172MPG) USB power switch has input voltage range of 2.7-5.5V and its IN pin connects to +USBVCC, confirming +USBVCC is a 5V rail (from schematic) The component voltage rating is specified as 1.2-3.6V in the VOLTAGE attribute (from schematic) VCCB is the B-side reference supply voltage and must be within the 1.2-3.6V range per the component specification (reasoning) Connecting VCCB to 5V exceeds the maximum operating voltage of 3.6V by 1.4V (reasoning) The NTS0102GT part number with 'GT' suffix indicates the standard variant with 3.6V maximum on both VCCA and VCCB, not the 'GF' variant which supports up to 5.5V on VCCB (reasoning) Operating VCCB above its maximum rating can cause permanent damage to the device or unreliable operation (reasoning) VCCB should be connected to a 3.3V supply instead of +USBVCC (5V) (reasoning) Alternatively, a 5V-tolerant level translator such as NTS0102GF or SN74LVC2T45 (which supports VCCB up to 5.5V) should be used instead of NTS0102GT (reasoning) Decoupling capacitors C92, C93, C94 (0.1uF) are present on the +USBVCC net for power supply filtering (from schematic)
1	B2	USB_HOST_EN0	✅	B2 output correctly connected to USB_HOST_EN0, which drives the enable input of USB power switch U32.
2	GND	GND	✅	Ground pin correctly connected to GND net.
3	VCCA	+V1P8A	✅	VCCA correctly connected to +V1P8A (1.8V) supply, which is within the specified 1.2-3.6V range.
4	A2	SOC_USB_HOST_EN0	✅	A2 input correctly connected to SOC_USB_HOST_EN0 signal from the SOC.
5	A1	SOC_USB_HOST_EN1	✅	A1 input correctly connected to SOC_USB_HOST_EN1 signal from the SOC.
6	OE	USB_HOST_BUFF_ENB	✅	OE pin correctly connected to USB_HOST_BUFF_ENB with pullup to +V1P8A, enabling the translator by default.
8	B1	USB_HOST_EN1	✅	B1 output correctly connected to USB_HOST_EN1, which drives the enable input of USB power switch U32.

U29 - TPD4USB30 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D1+	USB3_TX0P_C	✅	D1+ pin connected to USB3_TX0P_C, providing ESD protection for the positive USB3 transmit signal. This pin protects the signal line going to the connector.
2	D1-	USB3_TX0N_C	✅	D1- pin connected to USB3_TX0N_C, providing ESD protection for the negative USB3 transmit signal. This pin protects the signal line going to the connector.
3	GND1	GND	✅	GND1 pin correctly connected to GND, providing ground reference for the ESD protection device.
4	D2+	USB3_RX0P_C	✅	D2+ pin connected to USB3_RX0P_C, providing ESD protection for the positive USB3 receive signal. This pin protects the signal line coming from the connector.
5	D2-	USB3_RX0N_C	✅	D2- pin connected to USB3_RX0N_C, providing ESD protection for the negative USB3 receive signal. This pin protects the signal line coming from the connector.
6	NC4	USB3_RX0N_C	✅	NC4 pin connected to USB3_RX0N_C, the same net as D2- (pin 5). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration.
7	NC3	USB3_RX0P_C	✅	NC3 pin connected to USB3_RX0P_C, the same net as D2+ (pin 4). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration.
8	GND2	GND	✅	GND2 pin correctly connected to GND, providing ground reference for the ESD protection device.
9	NC2	USB3_TX0N_C	✅	NC2 pin connected to USB3_TX0N_C, the same net as D1- (pin 2). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration.
10	NC1	USB3_TX0P_C	✅	NC1 pin connected to USB3_TX0P_C, the same net as D1+ (pin 1). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration.

CHOKE1 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_RX0N_C	✅	IN1 pin connected to USB3_RX0N_C, the negative receive signal from the ESD protection device U29. This is the input side of the common mode choke for the negative differential signal.
3	IN2	USB3_RX0P_C	✅	IN2 pin connected to USB3_RX0P_C, the positive receive signal from the ESD protection device U29. This is the input side of the common mode choke for the positive differential signal.
4	OUT2	USB3_RXP0	✅	OUT2 pin connected to USB3_RXP0, the positive receive signal going to the SOC. This is the output side of the common mode choke for the positive differential signal.
6	OUT1	USB3_RXN0	✅	OUT1 pin connected to USB3_RXN0, the negative receive signal going to the SOC. This is the output side of the common mode choke for the negative differential signal.

CHOKE2 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_TX0P-R	✅	IN1 pin connected to USB3_TX0P-R, the positive transmit signal after AC coupling from the SOC. This is the input side of the common mode choke for the positive differential signal.
3	IN2	USB3_TX0N-R	✅	IN2 pin connected to USB3_TX0N-R, the negative transmit signal after AC coupling from the SOC. This is the input side of the common mode choke for the negative differential signal.
4	OUT2	USB3_TX0N_C	✅	OUT2 pin connected to USB3_TX0N_C, the negative transmit signal going to the ESD protection and connector. This is the output side of the common mode choke for the negative differential signal.
6	OUT1	USB3_TX0P_C	✅	OUT1 pin connected to USB3_TX0P_C, the positive transmit signal going to the ESD protection and connector. This is the output side of the common mode choke for the positive differential signal.

CHOKE4 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN0	✅	IN1 is connected to USB_DN0, which is the USB 2.0 D- signal from the SOC. This is the input side of one winding of the common mode choke.
3	IN2	USB_DP0	✅	IN2 is connected to USB_DP0, which is the USB 2.0 D+ signal from the SOC. This is the input side of the second winding of the common mode choke.
4	OUT2	USB_H0	✅	OUT2 is connected to USB_H0, which routes to the ESD protection device (U9) and USB connector. This is the output of the D+ signal path.
6	OUT1	USB_L0	✅	OUT1 is connected to USB_L0, which routes to the ESD protection device (U9) and USB connector. This is the output of the D- signal path.

U9 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H0	✅	D+ pin is connected to USB_H0, providing ESD protection for the USB 2.0 D+ data line. The connection is correct.
2	D-	USB_L0	✅	D- pin is connected to USB_L0, providing ESD protection for the USB 2.0 D- data line. The connection is correct.
3	ID		✅	ID pin is left unconnected, which is acceptable per the datasheet for applications where the ID pin is not used.
4	GND	GND	✅	GND pin is connected to the GND net, providing the ground reference for the ESD protection device. The connection is correct.
5	NC		✅	NC pin is not connected, which is correct as this pin is not internally connected per the datasheet.
6	VBUS	VBUS1	✅	VBUS pin is connected to VBUS1, providing ESD protection for the USB power line. The connection is correct.

CHOKE3 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN1	✅	IN1 pin receives USB_DN1 signal, which is the negative differential USB data signal for port 1.
3	IN2	USB_DP1	✅	IN2 pin receives USB_DP1 signal, which is the positive differential USB data signal for port 1.
4	OUT2	USB_H1	✅	OUT2 pin outputs the filtered USB_H1 signal (D+) to the ESD protection device U8 and USB connector.
6	OUT1	USB_L1	✅	OUT1 pin outputs the filtered USB_L1 signal (D-) to the ESD protection device U8 and USB connector.

U8 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H1	✅	D+ pin provides ESD protection for the USB D+ data line (USB_H1) for port 1.
2	D-	USB_L1	✅	D- pin provides ESD protection for the USB D- data line (USB_L1) for port 1.
3	ID		✅	ID pin is correctly left floating as it is not needed for this USB host port application.
4	GND	GND	✅	GND pin is correctly connected to the ground plane.
5	NC		✅	NC pin is correctly left unconnected as specified in the datasheet.
6	VBUS	VBUS2	✅	VBUS pin provides ESD protection for the USB power line (VBUS2) for port 1.

USB1 - 258-0004503 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUSA	VBUS1	✅	VBUSA provides power to USB port A. Connected to VBUS1 with proper power switching, filtering, and ESD protection.
2	DA-	USB_L0	✅	DA- is the USB 2.0 D- signal for port A. Connected to USB_L0 with common mode filtering and ESD protection.
3	DA+	USB_H0	✅	DA+ is the USB 2.0 D+ signal for port A. Connected to USB_H0 with common mode filtering and ESD protection.
4	GNDA	GND	✅	GNDA is the ground connection for USB port A, correctly connected to system ground.
5	SSRX-	USB3_RX0N_C	✅	SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected to USB3_RX0N_C with common mode filtering and ESD protection.
6	SSRX+	USB3_RX0P_C	✅	SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected to USB3_RX0P_C with common mode filtering and ESD protection.
7	GND_DRAIN	GND	✅	GND_DRAIN is a ground drain connection, correctly connected to system ground.
8	SSTX-	USB3_TX0N_C	✅	SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected to USB3_TX0N_C with AC coupling, common mode filtering, and ESD protection.
9	SSTX+	USB3_TX0P_C	✅	SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected to USB3_TX0P_C with AC coupling, common mode filtering, and ESD protection.
10	VBUSB	VBUS2	✅	VBUSB provides power to USB port B. Connected to VBUS2 with proper power switching, filtering, and ESD protection.
11	DB-	USB_L1	✅	DB- is the USB 2.0 D- signal for port B. Connected to USB_L1 with common mode filtering and ESD protection.
12	DB+	USB_H1	✅	DB+ is the USB 2.0 D+ signal for port B. Connected to USB_H1 with common mode filtering and ESD protection.
13	GNDB	GND	✅	GNDB is the ground connection for USB port B, correctly connected to system ground.
MH1	SHIELD1	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground.
MH2	SHIELD2	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground.
MH3	SHIELD3	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground.
MH4	SHIELD4	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground.

FB13 - 3044-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input pin connected to +5VSB power rail, providing power source for USB circuitry.
2	2	+USBVCC	✅	Output pin connected to +USBVCC rail, supplying filtered power to USB power switch and level translator.

L1 - BKP2125HS221-T ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP1	✅	Input pin connected to USBP1, the output of USB power switch channel A.
2	2	VBUS1	✅	Output pin connected to VBUS1, supplying filtered power to USB connector port A and ESD protection.

L2 - BKP2125HS221-T ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP2	✅	Input pin connected to USBP2, the output of USB power switch channel B.
2	2	VBUS2	✅	Output pin connected to VBUS2, supplying filtered power to USB connector port B and ESD protection.

J10 - 158-0004534 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
2	2	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
13	13	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
14	14	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
25	25	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
26	26	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
37	37	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
38	38	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
49	49	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
50	50	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
59	59	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
60	60	GND	✅	Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance.
3	3	mSATA_TX_P	✅	mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5) for mSATA interface.
5	5	mSATA_TX_N	✅	mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5) for mSATA interface.
4	4	mSATA_RX_P	✅	mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6) for mSATA interface.
6	6	mSATA_RX_N	✅	mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6) for mSATA interface.
7	7	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
8	8	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
19	19	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
20	20	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
31	31	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
32	32	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
43	43	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
44	44	+5VSB	✅	5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance.
9	9	mPCIE_REFCLK_P	✅	mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11) with test points TP19 and TP20.
11	11	mPCIE_REFCLK_N	✅	mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11) with test points TP19 and TP20.
10	10	USB_HOST_DP	✅	USB host differential pair (DP on pin 10, DN on pin 12) for USB interface.
12	12	USB_HOST_DN	✅	USB host differential pair (DP on pin 10, DN on pin 12) for USB interface.
15	15	mPCIE_TX_P	✅	mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17) with test points TP21 and TP22.
17	17	mPCIE_TX_N	✅	mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17) with test points TP21 and TP22.
16	16	mPCIE_RX_N	✅	mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18) for PCB routing ease, with test points TP24 and TP23.
18	18	mPCIE_RX_P	✅	mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18) for PCB routing ease, with test points TP24 and TP23.
21	21	I2C6_SCL	✅	I2C6 clock line with 10K ohm pull-up resistor R13 to +V1P8S.
22	22	mPCIE_WAKEB	✅	mPCIE wake signal (active low) for power management.
23	23	I2C6_SDA	✅	I2C6 data line with 10K ohm pull-up resistor R14 to +V1P8S.
24	24	mPCIe_CLKREQ3_B	✅	mPCIE clock request signal (active low) for power management.
27	27	EXP_GPIO1	✅	Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O.
28	28	EXP_GPIO3	✅	Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O.
29	29	EXP_GPIO2	✅	Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O.
30	30	EXP_GPIO4	✅	Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O.
33	33	XDP_H_OBSDATA_A1	✅	XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface.
34	34	XDP_H_OBSDATA_A0	✅	XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface.
35	35	XDP_H_OBSDATA_A2	✅	XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface.
36	36	XDP_H_OBSDATA_A3	✅	XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface.
39	39	XDP_H_PRDYB	✅	XDP probe ready signal (active low) for debug interface handshaking.
40	40	XDP_H_PREQB_PB	✅	XDP probe request signal (active low) with 200 ohm pull-up to +V1P8A via R3, buffered by U1 to create XDP_H_PREQB.
41	41	HOOK0	✅	Hook signal 0 connected via 1K ohm resistor R15 to PMC_RSMRST for debug/test access.
42	42	HOOK1	✅	Hook signal 1 connected via 0 ohm resistor R5 to FP_PWRBTN, with optional 4.7K pull-down R4 (DNI).
45	45	HOOK2	✅	Hook signal 2 connected via 1K ohm resistor R16 to PMC_CORE_PWROK for debug/test access.
46	46	PMC_RSTBTN	✅	PMC reset button signal with 1K ohm pull-up to +V1P8S via R6 and 0.1uF filter capacitor C1 to ground.
47	47	HOOK6	✅	Hook signal 6 connected via 1K ohm resistor R17 to PMC_PLTRST_R_V1P8 for debug/test access.
48	48	ILB_RTC_TESTB	✅	RTC test signal (active low) with 1K ohm pull-up to +RTCVCC via R7 and 1uF filter capacitor C2 to ground.
51	51	HOOK4	✅	Hook signal 4 connected via 0 ohm resistor R18 to +3VSB, providing 3.3V standby power access.
52	52	XDP_H_TRSTB	✅	XDP test reset signal (active low) for JTAG-style debug interface.
53	53	HOOK5	✅	Hook signal 5 connected via 0 ohm resistor R20 to +V1P8S, providing 1.8V standby power access.
54	54	XDP_H_TCK	✅	XDP test clock signal for JTAG-style debug interface.
55	55	+V1P8A	✅	1.8V analog power supply with 0.1uF decoupling capacitor C5 to ground.
56	56	XDP_H_TMS	✅	XDP test mode select signal for JTAG-style debug interface.
57	57	XDP_H_TDO	✅	XDP test data out signal with 51 ohm resistor R21 to +V1P8A for termination or weak pull-up.
58	58	XDP_H_TDI	✅	XDP test data in signal for JTAG-style debug interface.

U1 - SN74AUP1G34 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin is correctly left unconnected.
2	A	XDP_H_PREQB_PB	✅	Input pin A is correctly connected to XDP_H_PREQB_PB signal with a 200 ohm pull-up resistor (R3) to +V1P8A.
3	GND	GND	✅	Ground pin is correctly connected to the GND net.
4	Y	XDP_H_PREQB	✅	Output pin Y is correctly connected to the XDP_H_PREQB net.
5	VCC	+V1P8A	✅	VCC pin is correctly connected to +V1P8A (1.8V supply) with bypass capacitor C5 (0.1µF) present.

R3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XDP_H_PREQB_PB	✅	Connected to XDP_H_PREQB_PB, forming a pull-up resistor for U1 input pin 2.
2	2	+V1P8A	✅	Connected to +V1P8A, completing the pull-up resistor configuration.

R21 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A, forming a pull-up resistor for the XDP_H_TDO signal.
2	2	XDP_H_TDO	✅	Connected to XDP_H_TDO signal. The 51 ohm pull-up value is unusually low for a JTAG TDO signal but may be intentional for signal integrity in the XDP debug interface.

R14 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SDA	✅	Connected to I2C6_SDA signal line, providing pull-up functionality to +V1P8S through the 10K resistor.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing 1.8V pull-up voltage for the I2C SDA line.

R13 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SCL	✅	Connected to I2C6_SCL signal line, providing pull-up functionality to +V1P8S through the 10K resistor.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing 1.8V pull-up voltage for the I2C SCL line.

C1 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal for filtering and debouncing of the reset button input.
2	2	GND	✅	Connected to GND, providing the return path for the filter capacitor.

R6 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal, providing pull-up function for the reset button input.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing the pull-up voltage for the reset button circuit.

C2 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to GND for the bypass/filter capacitor function.
2	2	ILB_RTC_TESTB	✅	Pin 2 is correctly connected to ILB_RTC_TESTB signal for filtering purposes.

R7 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	ILB_RTC_TESTB	✅	Pin 1 is correctly connected to ILB_RTC_TESTB signal as part of a pull-up resistor configuration.
2	2	+RTCVCC	✅	Pin 2 is correctly connected to +RTCVCC to provide pull-up for the ILB_RTC_TESTB signal.

C5 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to GND, providing the ground reference for this decoupling capacitor.
2	2	+V1P8A	✅	Pin 2 is correctly connected to +V1P8A, providing decoupling for the 1.8V analog power rail.

U42 - WGI210AT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	LAN_PWR_GOOD	$18N3538	✅	LAN_PWR_GOOD output signal pulled high through R828 (10K) to +3VSB_LAN, indicating power supply status.
2	NC_SI_CLK_IN	$18N3372	✅	NC_SI_CLK_IN pulled to ground through R837 (1K), disabling the network controller serial interface clock input.
3	NC_SI_CRS_DV	$18N3374	✅	NC_SI_CRS_DV pulled to ground through R838 (1K), disabling the carrier sense/data valid signal for the serial interface.
4	JTAG_TDO		✅	JTAG_TDO left unconnected, which is acceptable when JTAG debugging is not required.
5	NC_SI_RXD1	$18N3305	✅	NC_SI_RXD1 pulled high through R826 (10K) to +3VSB_LAN, disabling receive data bit 1 of the serial interface.
6	NC_SI_RXD0	$18N3303	✅	NC_SI_RXD0 pulled high through R825 (10K) to +3VSB_LAN, disabling receive data bit 0 of the serial interface.
7	NC_SI_TX_EN	$18N3376	✅	NC_SI_TX_EN pulled to ground through R839 (1K), disabling transmit enable for the serial interface.
8	NC_SI_TXD1	$18N3301	✅	NC_SI_TXD1 pulled high through R824 (10K) to +3VSB_LAN, disabling transmit data bit 1 of the serial interface.
9	NC_SI_TXD0	$18N3299	✅	NC_SI_TXD0 pulled high through R823 (10K) to +3VSB_LAN, disabling transmit data bit 0 of the serial interface.
10	VDD3P3_10	+3VSB_LAN	✅	VDD3P3_10 connected to +3VSB_LAN power rail with appropriate decoupling capacitors.
11	VDD0P9_11	+0V9_LAN	✅	VDD0P9_11 connected to +0V9_LAN power rail with appropriate decoupling capacitors.
12	NVM_SI	$18N2399	✅	NVM_SI connected to SPI flash U43 pin 5 (SI) through series resistor R832 (33.2Ω) for signal integrity.
13	NVM_SK	$18N2397	✅	NVM_SK connected to SPI flash U43 pin 6 (SCK) through series resistor R834 (33.2Ω) for signal integrity.
14	NVM_SO	$18N3554	✅	NVM_SO connected to SPI flash U43 pin 2 (SO) through series resistor R833 (33.2Ω) for signal integrity.
15	NVM_CS_N	$18N2395	✅	NVM_CS_N connected to SPI flash U43 pin 1 (CS#) through series resistor R835 (33.2Ω) for signal integrity.
16	PE_WAKE_N	PMC_PCIE_WAKE	✅	PE_WAKE_N connected to PMC_PCIE_WAKE for PCIe wake signaling to platform management controller.
17	PE_RST_N	PMC_PLTRST_L	✅	PE_RST_N connected to PMC_PLTRST_L for PCIe reset control from platform.
18	JTAG_TMS	$18N3293	✅	JTAG_TMS pulled high through R820 (10K) to +3VSB_LAN, which is standard for JTAG interfaces.
19	JTAG_CLK	$18N3295	✅	JTAG_CLK pulled high through R821 (10K) to +3VSB_LAN, which is standard for JTAG interfaces.
20	PE_TXN	PCIE_C_RXP2	✅	PE_TXN and PE_TXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_TXN connects to PCIE_C_RXP2 and PE_TXP connects to PCIE_C_RXN2.
21	PE_TXP	PCIE_C_RXN2	✅	PE_TXN and PE_TXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_TXN connects to PCIE_C_RXP2 and PE_TXP connects to PCIE_C_RXN2.
22	NC/INTVCC		✅	NC/INTVCC pin left unconnected, which is acceptable if this is a no-connect or internal voltage pin.
23	PE_RXN	PCIE_C_TXP2	✅	PE_RXN and PE_RXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_RXN connects to PCIE_C_TXP2 and PE_RXP connects to PCIE_C_TXN2.
24	PE_RXP	PCIE_C_TXN2	✅	PE_RXN and PE_RXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_RXN connects to PCIE_C_TXP2 and PE_RXP connects to PCIE_C_TXN2.
25	PECLK_N	PCIE_CLK-N2	✅	PECLK_N connected to PCIE_CLK-N2 for PCIe reference clock negative signal with test point TP17.
26	PECLK_P	PCIE_CLK-P2	✅	PECLK_P connected to PCIE_CLK-P2 for PCIe reference clock positive signal with test point TP18.
27	VDD3P3_27	+3VSB_LAN	✅	VDD3P3_27 connected to +3VSB_LAN power rail with appropriate decoupling capacitors.
28	DEV_OFF_N	$18N3540	✅	DEV_OFF_N pulled high through R827 (10K) to +3VSB_LAN, keeping device enabled by default.
29	JTAG_TDI	$18N3297	✅	JTAG_TDI pulled high through R822 (10K) to +3VSB_LAN, which is standard for JTAG interfaces.
30	LED1	LAN-LED1	✅	LED1 connected to LAN-LED1 which drives LINK-LED-N through R843 (301Ω) to J11 LED indicator.
31	LED0	LAN-LED0	✅	LED0 connected to LAN-LED0 which drives LED indicator on J11 pin 11 with filtering capacitor C431.
32	VDD0P9_32	+0V9_LAN	✅	VDD0P9_32 connected to +0V9_LAN power rail with appropriate decoupling capacitors.
33	LED2	LAN-LED2	✅	LED2 connected to LAN-LED2 which drives 1G-LED-N through R844 (301Ω) to J11 LED indicator.
34	SMB_CLK	LAN-SMB-CLK	✅	SMB_CLK connected to LAN-SMB-CLK for SMBus clock signal used in system management.
35	SMB_ALRT_N	LAN-SMB-ALERT#	✅	SMB_ALRT_N connected to LAN-SMB-ALERT# for SMBus alert signaling (active low).
36	SMB_DATA	LAN-SMB-DATA	✅	SMB_DATA connected to LAN-SMB-DATA for SMBus data signal used in system management.
37	CBOT	$18N2590	✅	CBOT and CTOP connected through C425 (0.039uF) forming an oscillator or PLL tuning network.
40	CTOP	$18N2588	✅	CBOT and CTOP connected through C425 (0.039uF) forming an oscillator or PLL tuning network.
38	VDD0P9_OUT	+0V9_LAN	✅	VDD0P9_OUT connected to +0V9_LAN rail, providing internal 0.9V regulator output to supply other 0.9V pins.
39	VDD1P5_OUT	+1V5_LAN	✅	VDD1P5_OUT connected to +1V5_LAN rail, providing internal 1.5V regulator output to supply other 1.5V pins.
41	VDD3P3_41	+3VSB_LAN	✅	VDD3P3_41 connected to +3VSB_LAN power rail with appropriate decoupling capacitors.
42	VDD0P9_42	+0V9_LAN	✅	VDD0P9_42 connected to +0V9_LAN power rail with appropriate decoupling capacitors.
43	NC_SI_ARB_IN		✅	NC_SI_ARB_IN left unconnected, which is acceptable as the serial interface arbitration feature is not being used.
44	NC_SI_ARB_OUT		✅	NC_SI_ARB_OUT left unconnected, which is acceptable as the serial interface arbitration feature is not being used.
45	XTAL2	LAN_XTAL2	✅	XTAL2 connected to 25MHz crystal X1 pin 1 with 27pF load capacitor C253 to ground.
46	XTAL1	LAN_XTAL1	✅	XTAL1 connected to 25MHz crystal X1 pin 3 with 27pF load capacitor C252 to ground.
47	VDD1P5_47	+1V5_LAN	✅	VDD1P5_47 connected to +1V5_LAN power rail with appropriate decoupling capacitors.
48	RSET	LAN_RSET	✅	RSET connected to ground through R836 (4.99K) to set internal reference currents and voltages.
49	MDI_MINUS3/SER_N	MDI_N3	✅	MDI_MINUS3 connected to MDI_N3 differential pair negative signal, routing to RJ45 connector J11 pin 10.
50	MDI_PLUS3/SER_P	MDI_P3	✅	MDI_PLUS3 connected to MDI_P3 differential pair positive signal, routing to RJ45 connector J11 pin 9.
51	VDD3P3_51	+3VSB_LAN	✅	VDD3P3_51 connected to +3VSB_LAN power rail with appropriate decoupling capacitors.
52	MDI_MINUS2/SET_N	MDI_N2	✅	MDI_MINUS2 connected to MDI_N2 differential pair negative signal, routing to RJ45 connector J11 pin 8.
53	MDI_PLUS2	MDI_P2	✅	MDI_PLUS2 connected to MDI_P2 differential pair positive signal, routing to RJ45 connector J11 pin 7.
54	MDI_MINUS1/SRDS_SIG_DET	MDI_N1	✅	MDI_MINUS1 connected to MDI_N1 differential pair negative signal, routing to RJ45 connector J11 pin 4.
55	MDI_PLUS1/SFP_I2C_CLK	MDI_P1	✅	MDI_PLUS1 connected to MDI_P1 differential pair positive signal, routing to RJ45 connector J11 pin 3.
56	VDD1P5_56	+1V5_LAN	✅	VDD1P5_56 connected to +1V5_LAN power rail with appropriate decoupling capacitors.
57	MDI_MINUS0/SFP_I2C_DATA	MDI_N0	✅	MDI_MINUS0 connected to MDI_N0 differential pair negative signal, routing to RJ45 connector J11 pin 2.
58	MDI_PLUS0/NC	MDI_P0	✅	MDI_PLUS0 connected to MDI_P0 differential pair positive signal, routing to RJ45 connector J11 pin 1.
59	VDD0P9_59	+0V9_LAN	✅	VDD0P9_59 connected to +0V9_LAN power rail with appropriate decoupling capacitors.
60	SDP3		✅	SDP3 left unconnected, which is acceptable for unused software-defined pins.
61	SDP1/PCIE_DIS		✅	SDP1/PCIE_DIS left unconnected, which enables PCIe functionality by default.
62	SDP2		✅	SDP2 left unconnected, which is acceptable for unused software-defined pins.
63	SDP0		✅	SDP0 left unconnected, which is acceptable for unused software-defined pins.
64	VDD3P3_64	+3VSB_LAN	✅	VDD3P3_64 connected to +3VSB_LAN power rail with appropriate decoupling capacitors.
65	GND_PAD	GND	✅	GND_PAD connected to GND for thermal and electrical grounding of the package.

R848 - 1120-0359 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	R848 (33.2kΩ) provides a weak pull-up on the SI (Serial Input) line of the SPI flash to ensure a defined logic state when the line is not actively driven.
2	2	$18N2435	✅	R848 (33.2kΩ) provides a weak pull-up on the SI (Serial Input) line of the SPI flash to ensure a defined logic state when the line is not actively driven.

U43 - AT25DF081A-SSH ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	$18N2439	✅	CS# (Chip Select) is correctly connected to the Ethernet controller U42 pin 15 (NVM_CS_N) through series resistor R835 (33.2Ω).
2	SO	$18N3552	✅	SO (Serial Output) is correctly connected to the Ethernet controller U42 pin 14 (NVM_SO) through series resistor R833 (33.2Ω).
3	WP#	$18N3609	✅	WP# (Write Protect) is correctly pulled high to +3VSB_LAN through R830 (10kΩ) as recommended by the datasheet.
4	GND	GND	✅	GND is correctly connected to the ground plane.
5	SI	$18N2435	✅	SI (Serial Input) is correctly connected to the Ethernet controller U42 pin 12 (NVM_SI) through series resistor R832 (33.2Ω), with a weak pull-up R848 (33.2kΩ) to +3VSB_LAN.
6	SCK	$18N2437	✅	SCK (Serial Clock) is correctly connected to the Ethernet controller U42 pin 13 (NVM_SK) through series resistor R834 (33.2Ω).
7	HOLD#	$18N3659	✅	HOLD# is correctly pulled high to +3VSB_LAN through R831 (10kΩ) as recommended by the datasheet.
8	VCC	+3VSB_LAN	✅	VCC is correctly connected to the +3VSB_LAN power rail, which is within the specified 2.7V to 3.6V operating range.

C431 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED0	✅	EMI filter capacitor (560pF) on the LAN-LED0 signal to suppress high-frequency noise on the LED line.
2	2	GND	✅	EMI filter capacitor (560pF) on the LAN-LED0 signal to suppress high-frequency noise on the LED line.

C428 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Center tap bypass capacitor (1.0uF) for Ethernet magnetics, providing AC coupling to ground with emphasis on lower frequency filtering.
2	2	GND	✅	Center tap bypass capacitor (1.0uF) for Ethernet magnetics, providing AC coupling to ground with emphasis on lower frequency filtering.

C426 - 2222-0016 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering.
2	2	GND	✅	Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering.

J11 - 3362-0042 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	MD1+	MDI_P0	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
2	MD1-	MDI_N0	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
3	MD2+	MDI_P1	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
4	MD2-	MDI_N1	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
7	MD3+	MDI_P2	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
8	MD3-	MDI_N2	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
9	MD4+	MDI_P3	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
10	MD4-	MDI_N3	✅	MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface.
5	CT1	$18N3856	✅	Center tap connections for Ethernet transformer, properly bypassed to ground through capacitors C426, C427, and C428.
6	CT2	$18N3856	✅	Center tap connections for Ethernet transformer, properly bypassed to ground through capacitors C426, C427, and C428.
11	LED2_AC1	LAN-LED0	✅	LED2_AC1 connects to LAN-LED0 from U42 pin 31 without a visible series current limiting resistor, which may cause excessive LED current unless the connector has built-in current limiting.
12	LED2_AD1	1G-LED-N	✅	LED2_AD1 connects to 1G-LED-N, which is driven by U42 LED2 output through current limiting resistor R844 (301Ω).
13	LED1_C	LINK-LED-N	✅	LED1_C (cathode) connects to LINK-LED-N, which is driven through current limiting resistor R843 (301Ω) from U42 LED1 output.
14	LED1_A	+3VSB_LAN	✅	LED1_A (anode) connects to +3VSB_LAN power supply, providing the positive voltage for LED1.
15	SHLD1	GND_EARTH	✅	Shield connections to chassis ground (GND_EARTH) for EMI protection and ESD immunity.
16	SHLD2	GND_EARTH	✅	Shield connections to chassis ground (GND_EARTH) for EMI protection and ESD immunity.

C429 - 2220-0039 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LINK-LED-N	✅	EMI filter capacitor (560pF) on the LINK-LED-N signal to suppress high-frequency noise on the LED line.
2	2	GND	✅	EMI filter capacitor (560pF) on the LINK-LED-N signal to suppress high-frequency noise on the LED line.

R844 - 1120-0203 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED2	✅	Current limiting resistor (301Ω) for LED2, connecting U42 LED2 output to the LED signal 1G-LED-N.
2	2	1G-LED-N	✅	Current limiting resistor (301Ω) for LED2, connecting U42 LED2 output to the LED signal 1G-LED-N.

R843 - 1120-0203 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED1	✅	Current limiting resistor (301Ω) for LED1, connecting U42 LED1 output to the LED cathode signal LINK-LED-N.
2	2	LINK-LED-N	✅	Current limiting resistor (301Ω) for LED1, connecting U42 LED1 output to the LED cathode signal LINK-LED-N.

C427 - 2222-0016 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering.
2	2	GND	✅	Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering.

C430 - 2220-0039 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1G-LED-N	✅	EMI filter capacitor (560pF) on the 1G-LED-N signal to suppress high-frequency noise on the LED line.
2	2	GND	✅	EMI filter capacitor (560pF) on the 1G-LED-N signal to suppress high-frequency noise on the LED line.

X1 - 25.00MHz ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Crystal pin connected to U42 XTAL2 with 27pF load capacitor C253.
2	2	GND	✅	Ground pin connected to GND.
3	3	LAN_XTAL1	✅	Crystal pin connected to U42 XTAL1 with 27pF load capacitor C252.
4	4	GND	✅	Ground pin connected to GND.

U10 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the 1.8V reference voltage for the A-side of the level translator.
2	A1	SOC_GPIO_S5_2	✅	A1 is correctly connected to SOC_GPIO_S5_2, one of the 1.8V SOC GPIO signals to be level-translated.
3	A2	SOC_GPIO_S5_1	✅	A2 is correctly connected to SOC_GPIO_S5_1, one of the 1.8V SOC GPIO signals to be level-translated.
4	A3	SOC_GPIO_S5_0	✅	A3 is correctly connected to SOC_GPIO_S5_0, one of the 1.8V SOC GPIO signals to be level-translated.
5	A4		✅	A4 is left unconnected as the fourth channel is not used in this design.
6	GND	GND	✅	GND is correctly connected to the ground net, providing the ground reference for the device.
7	B4	GND	✅	B4 is connected to GND, which appears to be the intended configuration for the unused fourth channel.
8	B3	GPIO_S5_0	✅	B3 is correctly connected to GPIO_S5_0, the 3.3V side of the GPIO_S5_0 signal.
9	B2	GPIO_S5_1	✅	B2 is correctly connected to GPIO_S5_1, the 3.3V side of the GPIO_S5_1 signal.
10	B1	GPIO_S5_2	✅	B1 is correctly connected to GPIO_S5_2, the 3.3V side of the GPIO_S5_2 signal.
11	VCCB	+PS_3VSB	✅	VCCB is correctly connected to +PS_3VSB, providing the 3.3V standby reference voltage for the B-side of the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, a 1.8V platform reset signal that controls the output enable function.

U14 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S (1.8V supply) to provide the A-side voltage reference for the level translator.
2	A1	SOC_SIO_SPI_CLK	✅	A1 is correctly connected to SOC_SIO_SPI_CLK, the 1.8V SPI clock signal from the SOC, which pairs with B1 for level translation.
3	A2	SOC_SIO_SPI_MOSI	✅	A2 is correctly connected to SOC_SIO_SPI_MOSI, the 1.8V SPI MOSI signal from the SOC, which pairs with B2 for level translation.
4	A3	SOC_SIO_SPI_MISO	✅	A3 is correctly connected to SOC_SIO_SPI_MISO, the 1.8V SPI MISO signal from the SOC, which pairs with B3 for level translation.
5	A4	SOC_SIO_SPI_CS1	✅	A4 is correctly connected to SOC_SIO_SPI_CS1, the 1.8V SPI chip select 1 signal from the SOC, which pairs with B4 for level translation.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	SIO_SPI_CS1	✅	B4 is correctly connected to SIO_SPI_CS1, the 3.3V translated SPI chip select 1 signal, which pairs with A4 for level translation.
8	B3	SIO_SPI_MISO	✅	B3 is correctly connected to SIO_SPI_MISO, the 3.3V translated SPI MISO signal, which pairs with A3 for level translation.
9	B2	SIO_SPI_MOSI	✅	B2 is correctly connected to SIO_SPI_MOSI, the 3.3V translated SPI MOSI signal, which pairs with A2 for level translation.
10	B1	SIO_SPI_CLK	✅	B1 is correctly connected to SIO_SPI_CLK, the 3.3V translated SPI clock signal, which pairs with A1 for level translation.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB (3.3V standby supply) to provide the B-side voltage reference for the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, a 1.8V platform reset signal that enables the level translator when high.

U15 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S, providing 1.8V supply for the A-side of the level translator.
2	A1	SIO_UART1_RTSB	✅	A1 is correctly connected to SIO_UART1_RTSB, translating the UART RTS signal from 1.8V to 3.3V.
3	A2	SIO_UART1_CTSB	✅	A2 is correctly connected to SIO_UART1_CTSB, translating the UART CTS signal between 1.8V and 3.3V.
4	A3	SIO_UART1_RXD	✅	A3 is correctly connected to SIO_UART1_RXD, translating the UART receive data signal between 1.8V and 3.3V.
5	A4	SIO_UART1_TXD	✅	A4 is correctly connected to SIO_UART1_TXD, translating the UART transmit data signal from 1.8V to 3.3V.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	UART1_TXD	✅	B4 is correctly connected to UART1_TXD, providing the 3.3V level UART transmit signal to the connector.
8	B3	UART1_RXD	✅	B3 is correctly connected to UART1_RXD, receiving the 3.3V level UART receive signal from the connector.
9	B2	UART1_CTSB	✅	B2 is correctly connected to UART1_CTSB, providing the 3.3V level UART CTS signal to/from the connector.
10	B1	UART1_RTSB	✅	B1 is correctly connected to UART1_RTSB, providing the 3.3V level UART RTS signal to the connector.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB, providing 3.3V supply for the B-side of the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset.

U16 - NTS0104GU12 ❌

DRCY flagged 1 potential issues in this component.

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Pin Designator	Pin Name	Net	Correct?	Analysis
2	A1	I2S_DATIN_R	❌	I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave. Pin 2 (A1) is connected to I2S_DATIN_R net (from schematic) Pin 3 (A2) is connected to I2S_DATOUT_R net (from schematic) Pin 9 (B2) is connected to I2SDO_GPIO net (from schematic) Pin 10 (B1) is connected to I2SDI_GPIO net (from schematic) I2SDO_GPIO connects to pin 18 of JP1 header connector (from schematic) I2SDI_GPIO connects to pin 20 of JP1 header connector (from schematic) The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 (reasoning) I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device (reasoning) I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device (reasoning) I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) (reasoning) I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) (reasoning) In I2S protocol, the master's data output must connect to the slave's data input (reasoning) In I2S protocol, the master's data input must connect to the slave's data output (reasoning) Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection (reasoning) Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection (reasoning) The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) (reasoning) The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) (reasoning) To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) (reasoning)
3	A2	I2S_DATOUT_R	❌	I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave. Pin 2 (A1) is connected to I2S_DATIN_R net (from schematic) Pin 3 (A2) is connected to I2S_DATOUT_R net (from schematic) Pin 9 (B2) is connected to I2SDO_GPIO net (from schematic) Pin 10 (B1) is connected to I2SDI_GPIO net (from schematic) I2SDO_GPIO connects to pin 18 of JP1 header connector (from schematic) I2SDI_GPIO connects to pin 20 of JP1 header connector (from schematic) The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 (reasoning) I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device (reasoning) I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device (reasoning) I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) (reasoning) I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) (reasoning) In I2S protocol, the master's data output must connect to the slave's data input (reasoning) In I2S protocol, the master's data input must connect to the slave's data output (reasoning) Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection (reasoning) Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection (reasoning) The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) (reasoning) The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) (reasoning) To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) (reasoning)
9	B2	I2SDO_GPIO	❌	I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave. Pin 2 (A1) is connected to I2S_DATIN_R net (from schematic) Pin 3 (A2) is connected to I2S_DATOUT_R net (from schematic) Pin 9 (B2) is connected to I2SDO_GPIO net (from schematic) Pin 10 (B1) is connected to I2SDI_GPIO net (from schematic) I2SDO_GPIO connects to pin 18 of JP1 header connector (from schematic) I2SDI_GPIO connects to pin 20 of JP1 header connector (from schematic) The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 (reasoning) I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device (reasoning) I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device (reasoning) I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) (reasoning) I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) (reasoning) In I2S protocol, the master's data output must connect to the slave's data input (reasoning) In I2S protocol, the master's data input must connect to the slave's data output (reasoning) Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection (reasoning) Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection (reasoning) The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) (reasoning) The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) (reasoning) To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) (reasoning)
10	B1	I2SDI_GPIO	❌	I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave. Pin 2 (A1) is connected to I2S_DATIN_R net (from schematic) Pin 3 (A2) is connected to I2S_DATOUT_R net (from schematic) Pin 9 (B2) is connected to I2SDO_GPIO net (from schematic) Pin 10 (B1) is connected to I2SDI_GPIO net (from schematic) I2SDO_GPIO connects to pin 18 of JP1 header connector (from schematic) I2SDI_GPIO connects to pin 20 of JP1 header connector (from schematic) The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 (reasoning) I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device (reasoning) I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device (reasoning) I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) (reasoning) I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) (reasoning) In I2S protocol, the master's data output must connect to the slave's data input (reasoning) In I2S protocol, the master's data input must connect to the slave's data output (reasoning) Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection (reasoning) Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection (reasoning) The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) (reasoning) The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) (reasoning) To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) (reasoning)
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S (1.8V supply) with proper decoupling capacitor C352.
4	A3	I2S_FRM_R	✅	A3 is correctly connected to I2S_FRM_R, which connects through R129 to LPE_I2S_FRM and translates to B3 (I2SFRM_GPIO).
5	A4	I2S_CLK_R	✅	A4 is correctly connected to I2S_CLK_R, which connects through R127 to LPE_I2S_CLK and translates to B4 (I2SCLK_GPIO).
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	I2SCLK_GPIO	✅	B4 is correctly connected to I2SCLK_GPIO, which goes to the GPIO header. This corresponds to A4 (I2S_CLK_R).
8	B3	I2SFRM_GPIO	✅	B3 is correctly connected to I2SFRM_GPIO, which goes to the GPIO header. This corresponds to A3 (I2S_FRM_R).
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB (3.3V supply) with proper decoupling capacitor C353.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the translator when the platform is out of reset.

R127 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_CLK_R	✅	0-ohm resistor correctly connects I2S_CLK_R to LPE_I2S_CLK, maintaining the 1.8V signal level.
2	2	LPE_I2S_CLK	✅	0-ohm resistor correctly connects I2S_CLK_R to LPE_I2S_CLK, maintaining the 1.8V signal level.

R128 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_DATIN_R	✅	0-ohm resistor correctly connects I2S_DATIN_R to LPE_I2S_DATIN, maintaining the 1.8V signal level.
2	2	LPE_I2S_DATIN	✅	0-ohm resistor correctly connects I2S_DATIN_R to LPE_I2S_DATIN, maintaining the 1.8V signal level.

R129 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_FRM_R	✅	0-ohm resistor correctly connects I2S_FRM_R to LPE_I2S_FRM, maintaining the 1.8V signal level.
2	2	LPE_I2S_FRM	✅	0-ohm resistor correctly connects I2S_FRM_R to LPE_I2S_FRM, maintaining the 1.8V signal level.

R130 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_DATOUT_R	✅	0-ohm resistor correctly connects I2S_DATOUT_R to LPE_I2S_DATOUT, maintaining the 1.8V signal level.
2	2	LPE_I2S_DATOUT	✅	0-ohm resistor correctly connects I2S_DATOUT_R to LPE_I2S_DATOUT, maintaining the 1.8V signal level.

U17 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S, providing the A-side reference voltage for the level translator.
2	A1	I2S_MCLK	✅	A1 is correctly connected to I2S_MCLK, an A-side I/O signal that will be translated to I2SMCLK_GPIO on B1.
3	A2	SOC_PWM1	✅	A2 is correctly connected to SOC_PWM1, an A-side I/O signal that will be translated to PWM1 on B2.
4	A3	SOC_PWM0	✅	A3 is correctly connected to SOC_PWM0, an A-side I/O signal that will be translated to PWM0 on B3.
5	A4		✅	A4 is left unconnected as this channel is unused, which is acceptable for the level translator.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	GND	✅	B4 is correctly tied to GND as this channel is unused (A4 is not connected).
8	B3	PWM0	✅	B3 is correctly connected to PWM0, the B-side translation of SOC_PWM0 from A3.
9	B2	PWM1	✅	B2 is correctly connected to PWM1, the B-side translation of SOC_PWM1 from A2.
10	B1	I2SMCLK_GPIO	✅	B1 is correctly connected to I2SMCLK_GPIO, the B-side translation of I2S_MCLK from A1.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB, providing the B-side reference voltage for the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the translator when the platform is out of reset.

R147 - 100K ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	R147 provides a pullup from DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control during programming.
2	2	DDP_IO3L	✅	R147 provides a pullup from DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control during programming.

R163 - 10K0 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	R163 provides a pullup from SPI_CS0 to +V_SPI, keeping the flash chip deselected by default.
2	2	SPI_CS0	✅	R163 provides a pullup from SPI_CS0 to +V_SPI, keeping the flash chip deselected by default.

R164 - 10K0 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	R164 provides a pullup from SPI_WP to +V_SPI, disabling hardware write protection by default.
2	2	SPI_WP	✅	R164 provides a pullup from SPI_WP to +V_SPI, disabling hardware write protection by default.

R165 - 10K0 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	R165 provides a pullup from SPI_HOLD to +V_SPI, disabling the hold function by default.
2	2	SPI_HOLD	✅	R165 provides a pullup from SPI_HOLD to +V_SPI, disabling the hold function by default.

D8 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	DDP_VCC	✅	A1 is correctly connected to DDP_VCC, providing one source path for +V_SPI through the diode OR-ing circuit.
A2	A2	$20N2079	✅	A2 is correctly connected to the voltage selection network, providing the second source path for +V_SPI.
C	C	+V_SPI	✅	C is correctly connected to +V_SPI, providing the OR-ed output to power the SPI flash and level translator B-side.

U3 - W25Q64BVSSIG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPI_CS0	✅	CS# is correctly connected to SPI_CS0 with a 10K pull-up to +V_SPI, as recommended for proper SPI operation.
2	SO/IO1	SPI_MISO	✅	SO/IO1 is correctly connected to SPI_MISO for data output from the flash memory.
3	WP#/IO2	SPI_WP	✅	WP#/IO2 is correctly connected to SPI_WP with a 10K pull-up to +V_SPI, disabling write protection in standard SPI mode.
4	GND	GND	✅	GND is correctly connected to ground.
5	SI/IO0	SPI_MOSI	✅	SI/IO0 is correctly connected to SPI_MOSI for data input to the flash memory.
6	SCK	SPI_CLK	✅	SCK is correctly connected to SPI_CLK for the serial clock input.
7	HOLD#/IO3	SPI_HOLD	✅	HOLD#/IO3 is correctly connected to SPI_HOLD with a 10K pull-up to +V_SPI, disabling the hold function in standard SPI mode.
8	VCC	+V_SPI	✅	VCC is connected to +V_SPI which is supplied via diode OR-ing from either DDP_VCC or +3VSB. The voltage may be marginal at the low end of the acceptable range due to diode drop.

U18 - NTB0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the A-side reference voltage for the level translator.
2	A1	SOC_SPI_MOSI-R	✅	A1 is correctly connected to SOC_SPI_MOSI-R for MOSI signal translation.
3	A2	SOC_SPI_CLK-R	✅	A2 is correctly connected to SOC_SPI_CLK-R for clock signal translation.
4	A3	SOC_SPI_MISO-R	✅	A3 is correctly connected to SOC_SPI_MISO-R for MISO signal translation.
5	A4	SOC_SPI_CS0B-R	✅	A4 is correctly connected to SOC_SPI_CS0B-R for chip select signal translation.
6	GND	GND	✅	GND is correctly connected to ground.
7	B4	SPI_CS0	✅	B4 is correctly connected to SPI_CS0, translating the chip select signal to the B-side voltage level.
8	B3	SPI_MISO	✅	B3 is correctly connected to SPI_MISO, translating the MISO signal to the B-side voltage level.
9	B2	SPI_CLK	✅	B2 is correctly connected to SPI_CLK, translating the clock signal to the B-side voltage level.
10	B1	SPI_MOSI	✅	B1 is correctly connected to SPI_MOSI, translating the MOSI signal to the B-side voltage level.
11	VCCB	+V_SPI	✅	VCCB is correctly connected to +V_SPI, providing the B-side reference voltage. The voltage level is approximately 2.9-3.0V after diode drop from +3VSB.
12	OE	DDP_IO3L	✅	OE is connected to DDP_IO3L with a 100K pull-up to +V1P8A. Without the datasheet, the appropriateness of using 1.8V for OE when VCCB is 3.3V cannot be confirmed.

U40 - PCA9306DCUT ❌

DRCY flagged 1 potential issues in this component.

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Pin Designator	Pin Name	Net	Correct?	Analysis
5	SDA2	GPIO_I2C_SDA	❌	SDA2 and SCL2 pins are missing required pullup resistors to the high-voltage supply (+3VSB). The datasheet explicitly requires pullup resistors on both sides of the I2C translator for proper operation. Pin 5 (SDA2) connects to GPIO_I2C_SDA and pin 6 (SCL2) connects to GPIO_I2C_SCL (from schematic) Pin 5 is SDA2 (Serial data, high-voltage side) and pin 6 is SCL2 (Serial clock, high-voltage side) (from datasheet PCA9306DCUT, page 4) The datasheet states: 'Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)' (from datasheet PCA9306DCUT, page 10) The datasheet states: 'the I2C bus device output can be open-drain with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU' (from datasheet PCA9306DCUT, page 10) Both typical application circuits in the datasheet show pullup resistors (RPU) on SCL2 and SDA2 to VDPU (from datasheet PCA9306DCUT, page 17) No pullup resistors are present on the GPIO_I2C_SDA or GPIO_I2C_SCL nets in the schematic (from schematic) The low-voltage side has pullup resistors: R267 (10K) on I2C5_SCL to +V1P8S and R266 (10K) on I2C5_SDA to +V1P8S (from schematic) The asymmetry between low-voltage side (with pullups) and high-voltage side (without pullups) indicates a design oversight rather than intentional reliance on external pullups (reasoning) GPIO_I2C_SCL and GPIO_I2C_SDA connect to JP1 connector pins 13 and 15, which is a general-purpose expansion header (from schematic) Without pullup resistors, the I2C signals cannot be pulled high and the bus will not function correctly (reasoning) Pullup resistors (typically 2.2K to 10K depending on bus capacitance and speed per I2C specification) should be added from GPIO_I2C_SDA to +3VSB and from GPIO_I2C_SCL to +3VSB (reasoning) If external pullups are intentionally expected on the other side of connector JP1, this should be clearly documented with a note on the schematic, but no such note is present (reasoning)
6	SCL2	GPIO_I2C_SCL	❌	SDA2 and SCL2 pins are missing required pullup resistors to the high-voltage supply (+3VSB). The datasheet explicitly requires pullup resistors on both sides of the I2C translator for proper operation. Pin 5 (SDA2) connects to GPIO_I2C_SDA and pin 6 (SCL2) connects to GPIO_I2C_SCL (from schematic) Pin 5 is SDA2 (Serial data, high-voltage side) and pin 6 is SCL2 (Serial clock, high-voltage side) (from datasheet PCA9306DCUT, page 4) The datasheet states: 'Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)' (from datasheet PCA9306DCUT, page 10) The datasheet states: 'the I2C bus device output can be open-drain with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU' (from datasheet PCA9306DCUT, page 10) Both typical application circuits in the datasheet show pullup resistors (RPU) on SCL2 and SDA2 to VDPU (from datasheet PCA9306DCUT, page 17) No pullup resistors are present on the GPIO_I2C_SDA or GPIO_I2C_SCL nets in the schematic (from schematic) The low-voltage side has pullup resistors: R267 (10K) on I2C5_SCL to +V1P8S and R266 (10K) on I2C5_SDA to +V1P8S (from schematic) The asymmetry between low-voltage side (with pullups) and high-voltage side (without pullups) indicates a design oversight rather than intentional reliance on external pullups (reasoning) GPIO_I2C_SCL and GPIO_I2C_SDA connect to JP1 connector pins 13 and 15, which is a general-purpose expansion header (from schematic) Without pullup resistors, the I2C signals cannot be pulled high and the bus will not function correctly (reasoning) Pullup resistors (typically 2.2K to 10K depending on bus capacitance and speed per I2C specification) should be added from GPIO_I2C_SDA to +3VSB and from GPIO_I2C_SCL to +3VSB (reasoning) If external pullups are intentionally expected on the other side of connector JP1, this should be clearly documented with a note on the schematic, but no such note is present (reasoning)
1	GND	GND	✅	GND pin correctly connected to ground plane.
2	VREF1	+V1P8S	✅	VREF1 pin correctly connected to +V1P8S (1.8V) low-voltage reference supply.
3	SCL1	I2C5_SCL	✅	SCL1 pin correctly connected to I2C5_SCL with required pullup resistor R267 (10K) to +V1P8S.
4	SDA1	I2C5_SDA	✅	SDA1 pin correctly connected to I2C5_SDA with required pullup resistor R266 (10K) to +V1P8S.
7	VREF2	$20N1576	✅	VREF2 pin correctly connected to net $20N1576, which is pulled to +3VSB through required 200K resistor R812. VREF2 is shorted to EN pin as required.
8	EN	$20N1576	✅	EN pin correctly connected to net $20N1576, shorted with VREF2 and pulled to +3VSB through 200K resistor R812, enabling the device for voltage translation.

R812 - 200K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N1576	✅	200K resistor correctly provides required high-impedance connection between VREF2/EN (net $20N1576) and high-voltage supply (+3VSB).
2	2	+3VSB	✅	200K resistor correctly provides required high-impedance connection between VREF2/EN (net $20N1576) and high-voltage supply (+3VSB).

R266 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C5_SDA	✅	10K pullup resistor correctly provides required pullup for SDA1 (I2C5_SDA) to VREF1 (+V1P8S).
2	2	+V1P8S	✅	10K pullup resistor correctly provides required pullup for SDA1 (I2C5_SDA) to VREF1 (+V1P8S).

R267 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C5_SCL	✅	10K pullup resistor correctly provides required pullup for SCL1 (I2C5_SCL) to VREF1 (+V1P8S).
2	2	+V1P8S	✅	10K pullup resistor correctly provides required pullup for SCL1 (I2C5_SCL) to VREF1 (+V1P8S).

J1 - 258-0004612 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDP_VCC	✅	Pin 1 connected to DDP_VCC, providing power input from the DediProg programmer.
2	2	GND	✅	Pin 2 connected to GND for ground reference.
3	3	SPI_CS0	✅	Pin 3 connected to SPI_CS0 for SPI chip select.
4	4	SPI_CLK	✅	Pin 4 connected to SPI_CLK for SPI clock.
5	5	SPI_MISO	✅	Pin 5 connected to SPI_MISO for SPI data output from the flash.
6	6	SPI_MOSI	✅	Pin 6 connected to SPI_MOSI for SPI data input to the flash.
7	7		✅	Pin 7 is not connected.
8	8	DDP_IO3L	✅	Pin 8 connected to DDP_IO3L, which controls the enable of U18 translator.

J5 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Jumper pin connected to FP_PWRBTN signal for test/debug functionality.
2	2	GND	✅	Jumper pin connected to GND to allow shorting FP_PWRBTN to ground when jumper is installed.

R149 - 4.7K ohm 1% 1/10W 0402 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	❌	Pullup resistor with correct connections between +PS_5VSB and FP_PWRBTN, but component value (4.7K) does not match the datasheet recommendation of 10K noted in schematic annotations. Pin 1 is connected to net FP_PWRBTN (from schematic) Pin 2 is connected to net +PS_5VSB (from schematic) R149 serves as a pullup resistor, pulling FP_PWRBTN high to +PS_5VSB when the power button SW1 is not pressed (reasoning) The component value is 4.7K ohm per part number 110-0002058 (from schematic) Schematic text annotations at coordinates (180.34, 355.6) and (180.34, 360.68) state 'USE 10K PU' and 'DATASHEET SAYS', located near R149 at (172.72, 347.98) (from schematic) These annotations indicate the datasheet for the receiving circuit recommends a 10K pullup resistor (reasoning) With 4.7K, the current draw when the button is pressed is approximately 1.06mA (5V / 4.7K), while 10K would draw approximately 0.5mA (reasoning) The RC time constant with C154 (0.1uF) and 4.7K is 470us, compared to 1ms with the recommended 10K (reasoning) The stronger 4.7K pullup provides faster rise time and better noise immunity, but may exceed input current specifications of the receiving circuit (reasoning) The component value should be changed to 10K to match the datasheet recommendation explicitly noted on the schematic (reasoning)
2	2	+PS_5VSB	❌	Pullup resistor with correct connections between +PS_5VSB and FP_PWRBTN, but component value (4.7K) does not match the datasheet recommendation of 10K noted in schematic annotations. Pin 1 is connected to net FP_PWRBTN (from schematic) Pin 2 is connected to net +PS_5VSB (from schematic) R149 serves as a pullup resistor, pulling FP_PWRBTN high to +PS_5VSB when the power button SW1 is not pressed (reasoning) The component value is 4.7K ohm per part number 110-0002058 (from schematic) Schematic text annotations at coordinates (180.34, 355.6) and (180.34, 360.68) state 'USE 10K PU' and 'DATASHEET SAYS', located near R149 at (172.72, 347.98) (from schematic) These annotations indicate the datasheet for the receiving circuit recommends a 10K pullup resistor (reasoning) With 4.7K, the current draw when the button is pressed is approximately 1.06mA (5V / 4.7K), while 10K would draw approximately 0.5mA (reasoning) The RC time constant with C154 (0.1uF) and 4.7K is 470us, compared to 1ms with the recommended 10K (reasoning) The stronger 4.7K pullup provides faster rise time and better noise immunity, but may exceed input current specifications of the receiving circuit (reasoning) The component value should be changed to 10K to match the datasheet recommendation explicitly noted on the schematic (reasoning)

C154 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Filter capacitor correctly connected between FP_PWRBTN and GND for noise filtering and debouncing.
2	2	FP_PWRBTN	✅	Filter capacitor correctly connected between FP_PWRBTN and GND for noise filtering and debouncing.

SW1 - 3770-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Switch output connected to FP_PWRBTN signal, which is pulled up to +PS_5VSB through R149 and protected by TVS diode D9.
2	2	GND	✅	Switch ground terminal correctly connected to main GND net.
3	GND1	GND_EARTH	✅	Chassis ground pins correctly connected to GND_EARTH for EMI/ESD protection, intentionally isolated from signal GND.
4	GND2	GND_EARTH	✅	Chassis ground pins correctly connected to GND_EARTH for EMI/ESD protection, intentionally isolated from signal GND.

D9 - DIODE_TVS_5V_84W_XFDFN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	TVS diode reference terminal correctly connected to GND for bidirectional ESD protection.
P	P	FP_PWRBTN	✅	TVS diode signal terminal correctly connected to FP_PWRBTN for ESD protection of the power button input.

Q105 - FDN327N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	GPIO_LED_CONTROL	✅	Drain is connected to GPIO_LED_CONTROL net, which is shared with LED D2 anode (pin A), creating a parallel configuration. While the MOSFET connection itself is valid, the circuit topology is incorrect due to D2's connections - the LED should be in series with the MOSFET, not in parallel.
G	GATE	GPIO_D2_LED_CTRL	✅	Gate is correctly connected to GPIO_D2_LED_CTRL with a 10K pull-down resistor (R706) to GND, which is standard practice for MOSFET gate control.
S	SOURCE	GND	✅	Source is correctly connected to GND, which is the standard configuration for an N-channel MOSFET low-side switch.

D2 - 4560-0045 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GPIO_LED_CONTROL	❌	LED is connected in parallel with MOSFET Q105 instead of in series. Anode (A) connects to GPIO_LED_CONTROL net which is shared with Q105 drain, and cathode (C) connects to GND. This creates an inefficient inverted-logic configuration. The correct series topology should be: +VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND. Pin A (Anode) is connected to net GPIO_LED_CONTROL (from schematic) Pin C (Cathode) is connected to net GND (from schematic) Net GPIO_LED_CONTROL connects to Q105 pin D (drain), R746 pin 2, and C149 pin 1 (from schematic) D2 is a blue LED (part 4560-0045) with maximum voltage 3.8V (from schematic) Blue LEDs typically have forward voltage of 3.0-3.5V (reasoning) The current topology creates a parallel configuration where D2 and Q105 drain-source are both connected between GPIO_LED_CONTROL and GND (reasoning) In this parallel configuration, when Q105 is OFF (gate low), current flows from +VCC through R746 (470Ω) and D2 to GND, lighting the LED (reasoning) When Q105 is ON (gate high), Q105 pulls GPIO_LED_CONTROL low, shorting the LED path and turning it off (reasoning) This creates inverted logic: GPIO high = LED off, GPIO low = LED on (reasoning) When the LED is off (Q105 ON), current continues to flow from +VCC through R746 and Q105 to GND, wasting approximately 23mW at 3.3V or 53mW at 5V (reasoning) The standard configuration for GPIO-controlled LED with N-channel MOSFET low-side switch is series topology: +VCC → R_current_limit → LED_anode → LED_cathode → MOSFET_drain → MOSFET_source → GND (reasoning) Series configuration provides non-inverted logic (GPIO high = LED on), zero current when LED is off, and is the overwhelming industry standard (reasoning) There is no indication in schematic notes, net names, or documentation that inverted logic is intentional (reasoning) The net name 'GPIO_LED_CONTROL' suggests direct control, not inverted control (reasoning) If inverted control was intended, typical design practice would include a note or use net naming like 'GPIO_LED_CONTROL_N' or 'LED_OFF' (reasoning) The text note 'SYSTEM POWER LED - GPIO CONTROLLED' does not specify or justify inverted control (from schematic) For comparison, D1 on the same page uses standard series configuration: +PS_5VSB → D1 → R148 → GND (from schematic) The correct connections should be: D2 anode to R746 pin 2 only (on separate net from Q105), and D2 cathode to Q105 drain (on new net) (reasoning) This would create the standard series topology with non-inverted logic and zero power consumption when LED is off (reasoning)
C	CATHODE	GND	❌	LED is connected in parallel with MOSFET Q105 instead of in series. Anode (A) connects to GPIO_LED_CONTROL net which is shared with Q105 drain, and cathode (C) connects to GND. This creates an inefficient inverted-logic configuration. The correct series topology should be: +VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND. Pin A (Anode) is connected to net GPIO_LED_CONTROL (from schematic) Pin C (Cathode) is connected to net GND (from schematic) Net GPIO_LED_CONTROL connects to Q105 pin D (drain), R746 pin 2, and C149 pin 1 (from schematic) D2 is a blue LED (part 4560-0045) with maximum voltage 3.8V (from schematic) Blue LEDs typically have forward voltage of 3.0-3.5V (reasoning) The current topology creates a parallel configuration where D2 and Q105 drain-source are both connected between GPIO_LED_CONTROL and GND (reasoning) In this parallel configuration, when Q105 is OFF (gate low), current flows from +VCC through R746 (470Ω) and D2 to GND, lighting the LED (reasoning) When Q105 is ON (gate high), Q105 pulls GPIO_LED_CONTROL low, shorting the LED path and turning it off (reasoning) This creates inverted logic: GPIO high = LED off, GPIO low = LED on (reasoning) When the LED is off (Q105 ON), current continues to flow from +VCC through R746 and Q105 to GND, wasting approximately 23mW at 3.3V or 53mW at 5V (reasoning) The standard configuration for GPIO-controlled LED with N-channel MOSFET low-side switch is series topology: +VCC → R_current_limit → LED_anode → LED_cathode → MOSFET_drain → MOSFET_source → GND (reasoning) Series configuration provides non-inverted logic (GPIO high = LED on), zero current when LED is off, and is the overwhelming industry standard (reasoning) There is no indication in schematic notes, net names, or documentation that inverted logic is intentional (reasoning) The net name 'GPIO_LED_CONTROL' suggests direct control, not inverted control (reasoning) If inverted control was intended, typical design practice would include a note or use net naming like 'GPIO_LED_CONTROL_N' or 'LED_OFF' (reasoning) The text note 'SYSTEM POWER LED - GPIO CONTROLLED' does not specify or justify inverted control (from schematic) For comparison, D1 on the same page uses standard series configuration: +PS_5VSB → D1 → R148 → GND (from schematic) The correct connections should be: D2 anode to R746 pin 2 only (on separate net from Q105), and D2 cathode to Q105 drain (on new net) (reasoning) This would create the standard series topology with non-inverted logic and zero power consumption when LED is off (reasoning)

R746 - 1120-0318 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Pin 1 is correctly connected to +VCC power supply for LED current limiting.
2	2	GPIO_LED_CONTROL	✅	Pin 2 is connected to GPIO_LED_CONTROL net, which is shared with D2 anode, Q105 drain, and C149. While R746 is correctly connected to D2 anode for current limiting, the overall circuit topology is incorrect due to D2's parallel configuration with Q105.

C149 - 2.2uF 10% 10V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_LED_CONTROL	✅	Pin 1 is connected to GPIO_LED_CONTROL net. The purpose of this 2.2µF capacitor in the LED circuit is unusual - it may be intended for filtering or to create a soft turn-on/turn-off effect, though the value seems large for typical LED applications.
2	2	GND	✅	Pin 2 is correctly connected to GND, which is appropriate for a bypass or filter capacitor.

R706 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_D2_LED_CTRL	✅	Pin 1 is correctly connected to GPIO_D2_LED_CTRL, which drives the gate of Q105.
2	2	GND	✅	Pin 2 is correctly connected to GND, providing pull-down function for the MOSFET gate.

R148 - 1120-0318 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PWR_LEDR	✅	Connected to PWR_LEDR net, which connects to the cathode of LED D1. Functions as the current limiting resistor for the adapter power LED indicator.
2	2	GND	✅	Connected to GND. Completes the current path for the adapter power LED circuit.

C150 - 123-0003258 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_5VSB	✅	Connected to +PS_5VSB supply rail. Provides local decoupling for the adapter power LED circuit.
2	2	GND	✅	Connected to GND. Completes the decoupling capacitor connection across the power supply.

D1 - 4560-0045 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	+PS_5VSB	✅	Anode connected to +PS_5VSB (5V standby power). This powers the adapter power indicator LED.
C	CATHODE	PWR_LEDR	✅	Cathode connected to PWR_LEDR net, which connects through current limiting resistor R148 (470Ω) to ground. This completes the LED circuit with appropriate current limiting.

Q106 - BSS84 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	D	DC_GATE_ENB	✅	Drain pin is correctly connected to DC_GATE_ENB, which controls the gate of U36 for overvoltage protection.
G	G	$22N2300	✅	Gate pin is correctly connected to $22N2300, which is the voltage-sensed node clamped by zener D13 at 4.3V.
S	S	$22N1502	✅	Source pin is correctly connected to $22N1502, which is the filtered DC input voltage being monitored.

U36 - IRF9321 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	$22N1502	✅	Source pins S1, S2, S3 are correctly connected to $22N1502, which is the filtered DC input voltage through ferrite beads L13 and L12 from DC_IN_1.
2	S2	$22N1502	✅	Source pins S1, S2, S3 are correctly connected to $22N1502, which is the filtered DC input voltage through ferrite beads L13 and L12 from DC_IN_1.
3	S3	$22N1502	✅	Source pins S1, S2, S3 are correctly connected to $22N1502, which is the filtered DC input voltage through ferrite beads L13 and L12 from DC_IN_1.
4	G	DC_GATE_ENB	✅	Gate pin G is correctly connected to DC_GATE_ENB, which is controlled by the overvoltage protection circuit through Q106.
5	D1	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output.
6	D2	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output.
7	D3	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output.
8	D4	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output.

D13 - 4620-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Anode is correctly connected to GND for zener voltage reference operation.
C	CATHODE	$22N2300	✅	Cathode is correctly connected to $22N2300, clamping this node to 4.3V above ground for the protection circuit.

R323 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	5VSB_GATE	✅	Gate drive resistor correctly connected between 5VSB_CTRL control signal and 5VSB_GATE (gate of Q14).
2	2	5VSB_CTRL	✅	Gate drive resistor correctly connected between 5VSB_CTRL control signal and 5VSB_GATE (gate of Q14).

R324 - 100K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	5VSB_LSENB	✅	Pull-up resistor correctly connected between +10V and 5VSB_LSENB (gate of Q103).
2	2	+10V	✅	Pull-up resistor correctly connected between +10V and 5VSB_LSENB (gate of Q103).

C340 - 1.0uF ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	5VSB_GATE	✅	Gate decoupling capacitor correctly connected between 5VSB_GATE (gate of Q14) and GND.
2	2	GND	✅	Gate decoupling capacitor correctly connected between 5VSB_GATE (gate of Q14) and GND.

C341 - 1.0uF ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Gate decoupling capacitor correctly connected between GND and 5VSB_LSENB (gate of Q103).
2	2	5VSB_LSENB	✅	Gate decoupling capacitor correctly connected between GND and 5VSB_LSENB (gate of Q103).

Q14 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	5VSB_LSENB	✅	Drain pin correctly connected to 5VSB_LSENB net, which is pulled up to +10V through R324 and controls the gate of Q103.
G	GATE	5VSB_GATE	✅	Gate pin correctly connected to 5VSB_GATE control signal through R323 (10K) with C340 (1uF) providing filtering to ground.
S	SOURCE	GND	✅	Source pin correctly connected to GND, providing the return path for the low-side switch configuration.

Q103 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+5VSB	✅	Source pins correctly connected to +5VSB output rail. All three source pins are paralleled to handle the 15.3A maximum current rating.
2	S2	+5VSB	✅	Source pins correctly connected to +5VSB output rail. All three source pins are paralleled to handle the 15.3A maximum current rating.
3	S3	+5VSB	✅	Source pins correctly connected to +5VSB output rail. All three source pins are paralleled to handle the 15.3A maximum current rating.
4	G	5VSB_LSENB	✅	Gate pin correctly connected to 5VSB_LSENB control signal. The gate is driven to +10V through R324 when enabled, providing VGS of approximately 5V which is sufficient to turn on the MOSFET.
5	D1	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance.
6	D2	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance.
7	D3	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance.
8	D4	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance.

R133 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pull-up resistor correctly connected between +V1P8A and S5_ENBL to provide default high state for the enable signal.
2	2	S5_ENBL	✅	Pull-up resistor correctly connected between +V1P8A and S5_ENBL to provide default high state for the enable signal.

R321 - 1K00 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_EN_L	✅	Pull-up resistor correctly connected between +PS_5VSB and +3VSB_EN_L to provide default high state for the gate control signal.
2	2	+PS_5VSB	✅	Pull-up resistor correctly connected between +PS_5VSB and +3VSB_EN_L to provide default high state for the gate control signal.

R322 - 100K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_EN	✅	Pull-up resistor correctly connected between +10V and +3VSB_EN to provide gate drive voltage for Q104 high-side P-channel MOSFET switch.
2	2	+10V	✅	Pull-up resistor correctly connected between +10V and +3VSB_EN to provide gate drive voltage for Q104 high-side P-channel MOSFET switch.

C116 - 1.0uF ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Decoupling capacitor correctly connected between +3VSB_EN and GND to filter the gate drive signal and provide local charge storage.
2	2	+3VSB_EN	✅	Decoupling capacitor correctly connected between +3VSB_EN and GND to filter the gate drive signal and provide local charge storage.

Q104 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+3VSB	✅	Source pins S1, S2, S3 are correctly connected to +3VSB output rail. These pins carry the switched output current to the system.
2	S2	+3VSB	✅	Source pins S1, S2, S3 are correctly connected to +3VSB output rail. These pins carry the switched output current to the system.
3	S3	+3VSB	✅	Source pins S1, S2, S3 are correctly connected to +3VSB output rail. These pins carry the switched output current to the system.
4	G	+3VSB_EN	✅	Gate pin is correctly connected to +3VSB_EN control signal, which is pulled up to +10V through R322 to provide sufficient gate drive voltage for high-side switching.
5	D1	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output.
6	D2	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output.
7	D3	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output.
8	D4	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output.

D6 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB_PG	✅	Dual Schottky diode correctly configured as an OR gate to pull PMC_RSMRST high when either +PS_3VSB_PG or +3VSB_EN is high.
2	2	+3VSB_EN	✅	Dual Schottky diode correctly configured as an OR gate to pull PMC_RSMRST high when either +PS_3VSB_PG or +3VSB_EN is high.
3	3	PMC_RSMRST	✅	Dual Schottky diode correctly configured as an OR gate to pull PMC_RSMRST high when either +PS_3VSB_PG or +3VSB_EN is high.

Q11 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB_EN	✅	Drain is correctly connected to +3VSB_EN to pull the gate drive signal low when Q11 is enabled.
G	GATE	+3VSB_EN_L	✅	Gate is correctly connected to +3VSB_EN_L control signal, which is pulled up to +PS_5VSB through R321 and can be pulled low by Q4.
S	SOURCE	GND	✅	Source is correctly connected to GND, providing the reference for the low-side switch configuration.

Q4 - MMBT3904 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
B	BASE	S5_ENBL	✅	Base is correctly connected to S5_ENBL signal, which is pulled up to +V1P8A through R133 and can be pulled low by Q10.
C	COLLECTOR	+3VSB_EN_L	✅	Collector is correctly connected to +3VSB_EN_L to pull the control signal low when Q4 is enabled.
E	EMITTER	GND	✅	Emitter is correctly connected to GND, providing the reference for the NPN transistor configuration.

U13 - NB670 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
10	BST	PS3_BST	❌	BST pin bootstrap circuit uses non-standard topology with 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. While the capacitor value (0.1µF) matches datasheet recommendation, the series resistance deviates from datasheet typical application which shows direct capacitor connection between BST and SW pins. Pin 10 (BST) is connected to net PS3_BST (from schematic) PS3_BST connects to R291 pin 1, R291 pin 2 connects to $22N1498, and C306 connects between $22N1498 and PS3VSB_PHASE (SW node) (from schematic) The bootstrap circuit path is: BST -> R291 (4.7Ω) -> C306 (0.1µF) -> SW (from schematic) BST is the bootstrap pin requiring a capacitor between SW and BST pins to form a floating supply across the high-side switch driver (from datasheet NB670, page 5) Datasheet typical application shows 100nF bootstrap capacitor connected directly between BST and SW with no series resistance (from datasheet NB670, page 18) Datasheet layout guidelines recommend keeping BST voltage path (BST, C3, and SW) as short as possible (from datasheet NB670, page 16) The minimum off-time is 350ns typical, and typical switching period at 500kHz is 2µs (from datasheet NB670, page 3) The 4.7Ω resistor with 0.1µF capacitor creates a time constant of 470ns (reasoning) While some designs use small resistors (<1Ω) in bootstrap circuits for inrush current limiting or EMI reduction, 4.7Ω is significantly higher than typical values (reasoning) The series resistance adds impedance to the bootstrap charging path, which could impede proper charging especially at higher input voltages with shorter off-times (reasoning) The circuit deviates from the datasheet recommended topology without documented justification (reasoning) Recommendation: Remove R291 and connect C306 directly between BST (pin 10) and SW (pins 8/9/15/16) per datasheet typical application, or if series resistance is required for specific EMI/inrush reasons, reduce R291 to <1Ω and document the design rationale (reasoning)
1	VIN	PS5VSB_VIN	✅	VIN pin correctly connected to PS5VSB_VIN input rail with appropriate input capacitors for decoupling.
2	PGND	GND	✅	PGND pin correctly connected to ground plane.
3	N/C		✅	N/C pin correctly left unconnected as specified in datasheet.
4	PG	+PS_3VSB_PG	✅	PG pin correctly connected with 100kΩ pull-up resistor to PS3_VCC as recommended by datasheet.
5	CLK	$22N1411	✅	CLK pin correctly connected to charge pump circuit through net $22N1411.
6	LDO	PS3_LDO	✅	LDO pin correctly connected to 10uF decoupling capacitor C95, exceeding minimum 4.7uF requirement.
7	VOUT	+PS_3VSB	✅	VOUT pin correctly connected to output rail +PS_3VSB with appropriate output capacitors.
8	SW1	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3.
9	SW2	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3.
15	SW3	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3.
16	SW4	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3.
11	VCC	PS3_VCC	✅	VCC pin correctly connected to 1uF decoupling capacitor C97, meeting minimum requirement.
12	ENLDO		✅	ENLDO pin correctly left floating to enable LDO by default as recommended by datasheet.
13	EN	PS3_EN	✅	EN pin correctly connected with 499kΩ pull-up resistor R109 to PS5VSB_VIN for automatic start-up.
14	AGND	GND	✅	AGND pin correctly connected to ground plane.

L3 - 125-0004501 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3VSB_PHASE	✅	Inductor pin 1 correctly connected to PS3VSB_PHASE switch node from U13 pins 8, 9, 15, 16.
2	2	+PS_3VSB	✅	Inductor pin 2 correctly connected to +PS_3VSB output rail (3.3V).

R291 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3_BST	✅	4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor. This is part of the non-standard bootstrap topology identified at U13 pin 10.
2	2	$22N1498	✅	4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor. This is part of the non-standard bootstrap topology identified at U13 pin 10.

C95 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3_LDO	✅	10µF LDO output decoupling capacitor correctly connected between PS3_LDO (U13 pin 6) and GND, exceeding the minimum 4.7µF requirement.
2	2	GND	✅	10µF LDO output decoupling capacitor correctly connected between PS3_LDO (U13 pin 6) and GND, exceeding the minimum 4.7µF requirement.

C97 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3_VCC	✅	1µF VCC decoupling capacitor correctly connected between PS3_VCC (U13 pin 11) and GND, meeting the minimum requirement.
2	2	GND	✅	1µF VCC decoupling capacitor correctly connected between PS3_VCC (U13 pin 11) and GND, meeting the minimum requirement.

R119 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB_PG	✅	100kΩ pull-up resistor correctly connected between +PS_3VSB_PG (U13 pin 4) and PS3_VCC for open-drain PG output.
2	2	PS3_VCC	✅	100kΩ pull-up resistor correctly connected between +PS_3VSB_PG (U13 pin 4) and PS3_VCC for open-drain PG output.

C306 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3VSB_PHASE	✅	0.1µF bootstrap capacitor with correct value but connected through non-standard topology with series resistor R291. This is part of the bootstrap circuit issue identified at U13 pin 10.
2	2	$22N1498	✅	0.1µF bootstrap capacitor with correct value but connected through non-standard topology with series resistor R291. This is part of the bootstrap circuit issue identified at U13 pin 10.

R109 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3_EN	✅	499kΩ pull-up resistor correctly connected between PS3_EN (U13 pin 13) and PS5VSB_VIN for EN pin.
2	2	PS5VSB_VIN	✅	499kΩ pull-up resistor correctly connected between PS3_EN (U13 pin 13) and PS5VSB_VIN for EN pin.

C85 - 0.1uF capacitor ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3_EN	✅	C85 is marked DNI (Do Not Install) so it is not electrically present. Datasheet recommends 10nF capacitor from EN to GND for noise filtering, but absence may be intentional design choice.
2	2	GND	✅	C85 is marked DNI (Do Not Install) so it is not electrically present. Datasheet recommends 10nF capacitor from EN to GND for noise filtering, but absence may be intentional design choice.

C323 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0.1uF decoupling capacitor between GND and +PS_5VSB, providing local power supply filtering for U35.
2	2	+PS_5VSB	✅	0.1uF decoupling capacitor between GND and +PS_5VSB, providing local power supply filtering for U35.

R289 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS_OUT_L	✅	1K pull-up resistor between PS_OUT_L and +PS_3VSB, marked DNI (Do Not Install). Component is electrically absent from the circuit.
2	2	+PS_3VSB	✅	1K pull-up resistor between PS_OUT_L and +PS_3VSB, marked DNI (Do Not Install). Component is electrically absent from the circuit.

R288 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	5VSB_CTRL	✅	1K pull-up resistor between 5VSB_CTRL and +PS_5VSB, setting default state for U35 SYS5VSB_OFF output.
2	2	+PS_5VSB	✅	1K pull-up resistor between 5VSB_CTRL and +PS_5VSB, setting default state for U35 SYS5VSB_OFF output.

U35 - NCT3012S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DeepS5_Sel	S5_SEL	✅	DeepS5_Sel pin connected to S5_SEL net with 2.2K pull-up resistor R307 to +PS_5VSB. This pin likely selects between different S5 sleep modes for EuP compliance.
2	VSB	+PS_5VSB	✅	VSB pin connected to +PS_5VSB power rail with local decoupling capacitor C323 (0.1uF) to ground. This is the power supply input for the IC.
3	PS_IN#	PB_RES	✅	PS_IN# pin connected to PB_RES net with 33 ohm series resistor R308 to FP_PWRBTN. This is the power button input with current limiting and noise filtering.
4	SLP_S5#	SLP_S4_L	✅	SLP_S5# pin connected to SLP_S4_L net. This is an active-low sleep state input signal from the system.
5	SDA	DDR_SMB_DATA	✅	SDA pin connected to DDR_SMB_DATA net. This is the I2C/SMBus data line for communication with DDR memory modules.
6	SCLK	DDR_SMB_CLK	✅	SCLK pin connected to DDR_SMB_CLK net. This is the I2C/SMBus clock line for communication with DDR memory modules.
7	PS_OUT#	PS_OUT_L	✅	PS_OUT# pin connected to PS_OUT_L net. This is the active-low power supply output control signal. R289 pull-up is DNI.
8	SYS5VSB_OFF	5VSB_CTRL	✅	SYS5VSB_OFF pin connected to 5VSB_CTRL net with 1K pull-up resistor R288 to +PS_5VSB. This output controls 5VSB enable/disable for EuP compliance. Text notes indicate Low=EuP Disable, High=EuP Enable.
9	GND	GND	✅	GND pin connected to ground net. This is the ground reference for the IC.

R307 - 2221-0023 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	S5_SEL	✅	2.2K pull-up resistor between S5_SEL and +PS_5VSB, setting default high state for U35 DeepS5_Sel input.
2	2	+PS_5VSB	✅	2.2K pull-up resistor between S5_SEL and +PS_5VSB, setting default high state for U35 DeepS5_Sel input.

R308 - 110-0002012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PB_RES	✅	33 ohm series resistor between PB_RES and FP_PWRBTN, providing current limiting and noise filtering for power button input.
2	2	FP_PWRBTN	✅	33 ohm series resistor between PB_RES and FP_PWRBTN, providing current limiting and noise filtering for power button input.

Q12 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN	✅	Drain connected to SYS_EN net, which drives the gates of Q6 and Q13. This MOSFET acts as a pull-down switch controlled by SYS_EN_GATE.
G	GATE	SYS_EN_GATE	✅	Gate connected to SYS_EN_GATE, which is controlled by Q7 and R142. This controls when Q12 pulls down SYS_EN.
S	SOURCE	GND	✅	Source connected to GND. This is the correct configuration for an N-channel MOSFET pull-down switch.

Q7 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN_GATE	✅	Drain connected to SYS_EN_GATE net, which drives the gate of Q12. This MOSFET acts as a pull-down switch controlled by SLP_S3_L.
G	GATE	SLP_S3_L	✅	Gate connected to SLP_S3_L control signal. This controls when Q7 pulls down SYS_EN_GATE.
S	SOURCE	GND	✅	Source connected to GND. This is the correct configuration for an N-channel MOSFET pull-down switch.

Q6 - RXR035N03 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB	✅	Drain pin connected to +3VSB input power rail (nominally 3.3V). This is the input side of the high-side switch configuration.
G	GATE	SYS_EN	✅	Gate pin connected to SYS_EN control signal, which is pulled to +10V through R340 (100K) when enabled. VGS of approximately 6.7V when on provides adequate gate drive.
S	SOURCE	+VCC3	✅	Source pin connected to +VCC3 output rail (nominally 3.3V). This is the output side of the high-side switch, supplying 300mA per the design notes.

Q13 - RXR035N03 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+5VSB	✅	Drain pin connected to +5VSB input power rail (nominally 5V). This is the input side of the high-side switch configuration.
G	GATE	SYS_EN	✅	Gate pin connected to SYS_EN control signal, which is pulled to +10V through R340 (100K) when enabled. VGS of approximately 5V when on provides adequate gate drive.
S	SOURCE	+VCC	✅	Source pin connected to +VCC output rail (nominally 5V). This is the output side of the high-side switch, supplying 600mA per the design notes.

C367 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Connected to +VCC output rail. This is the positive terminal of the output decoupling capacitor. The 6.3V voltage rating provides marginal but acceptable margin for the 5V rail.
2	2	GND	✅	Connected to GND. This is the negative terminal of the output decoupling capacitor.

C115 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Connected to +VCC3 output rail. This is the positive terminal of the output decoupling capacitor.
2	2	GND	✅	Connected to GND. This is the negative terminal of the output decoupling capacitor.

Q2 - BAV99-7-F-S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	+PS_5VSB	✅	Anode 1 connected to +PS_5VSB power rail. This provides the upper clamp voltage reference for the protection circuit.
2	A2	$22N1417	✅	Anode 2 connected to intermediate node $22N1417. This node is shared with Q9 pin 1 and provides coupling between the two diode arrays.
3	C	$22N1419	✅	Common cathode connected to net $22N1419, which is AC coupled to the clock signal through C72.

Q9 - BAV99-7-F-S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	$22N1417	✅	Anode 1 connected to intermediate node $22N1417, shared with Q2 pin 2. This creates a coupling between the two clamping circuits.
2	A2	+10V	✅	Anode 2 connected to +10V power rail. This provides the upper clamp voltage reference at a higher voltage than Q2.
3	C	$22N1467	✅	Common cathode connected to net $22N1467, which is AC coupled to the clock signal through C283.

Q10 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	S5_ENBL	✅	Drain pin correctly connected to S5_ENBL net, which drives the base of Q4 through pull-up resistor R133. Functions as the output of a low-side switch controlling the +3VSB enable signal.
G	GATE	5VSB_CTRL	✅	Gate pin correctly connected to 5VSB_CTRL signal from U35 pin 8 (SYS5VSB_OFF). Includes 1K pull-up to +PS_5VSB and 10K resistor to 5VSB_GATE for proper gate drive.
S	SOURCE	GND	✅	Source pin correctly connected to GND, providing the reference point for the N-channel MOSFET in a low-side switch configuration.

U25 - NCP81109GMNTXG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT pin connected to VR_HOT_L net. This is a thermal alert output that signals when junction temperature exceeds the warning threshold.
2	SDIO	$23N2429	✅	SDIO pin connected to SVID data interface through R80 (16.9Ω) series resistor. Pull-up resistor R85 is DNI, suggesting external pull-ups are provided.
3	ALERT	$23N2431	✅	ALERT pin connected to SVID alert interface through R62 (0Ω). Pull-up resistor R86 is DNI, suggesting external pull-ups are provided.
4	SCLK	$23N2430	✅	SCLK pin connected to SVID clock interface through R81 (20.0Ω) series resistor. Pull-up resistor R87 is DNI, suggesting external pull-ups are provided.
5	GND	AGND-VCORE	✅	Analog ground pins (GND, GND1, GND_PAD) all connected to AGND-VCORE, which connects to GND through R37 (0Ω) providing star ground connection.
32	GND1	AGND-VCORE	✅	Analog ground pins (GND, GND1, GND_PAD) all connected to AGND-VCORE, which connects to GND through R37 (0Ω) providing star ground connection.
49	GND_PAD	AGND-VCORE	✅	Analog ground pins (GND, GND1, GND_PAD) all connected to AGND-VCORE, which connects to GND through R37 (0Ω) providing star ground connection.
6	VR_RDY	$23N3753	✅	VR_RDY pin connected through R79 (0Ω) to VCORE_PG power good signal with pull-up to +VCC3.
7	VIN1	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
11	VIN2	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
12	VIN3	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
13	VIN4	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
14	VIN5	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
15	VIN6	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
16	VIN7	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
17	VIN8	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
50	VIN_PAD	+5VSB_SW	✅	Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors.
8	BST	$23N3711	✅	BST pin connected to bootstrap network with R154 (2.20Ω) and C50 (0.22µF) for high-side gate driver supply.
9	GH		✅	GH pin is the high-side gate driver output. Connection to external MOSFETs cannot be fully verified from this schematic page.
10	SW1	$23N3731	✅	SW1 pin connected to switch node with bootstrap capacitor C50 for gate driver supply.
18	SW2	VCORE-SW	✅	Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output.
25	SW3	VCORE-SW	✅	Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output.
26	SW4	VCORE-SW	✅	Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output.
27	SW5	VCORE-SW	✅	Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output.
28	SW6	VCORE-SW	✅	Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output.
29	SW7	VCORE-SW	✅	Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output.
51	SW_PAD	VCORE-SW	✅	Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output.
19	PGND1	GND	✅	Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path.
20	PGND2	GND	✅	Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path.
21	PGND3	GND	✅	Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path.
22	PGND4	GND	✅	Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path.
23	PGND5	GND	✅	Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path.
24	PGND6	GND	✅	Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path.
30	GL		✅	GL pin is the low-side gate driver output. Connection to external MOSFETs cannot be fully verified from this schematic page.
31	VBOOT	$23N3477	✅	VBOOT pin connected through R70 (88.7kΩ) to AGND-VCORE to set boot voltage to 1.1V and I2C address to 0x0 per text note.
33	VCCP	$23N3625	✅	VCCP pin connected to +5VSB through R845 (1.00Ω) with C48 (4.7µF) decoupling for charge pump supply.
34	TSENSE	$23N3665	✅	TSENSE pin connected to temperature sensing network with TH2 (100kΩ thermistor) and R131 (14.0kΩ) forming voltage divider.
35	IMAX	$23N3681	✅	IMAX pin connected through R105 (44.2kΩ) to AGND-VCORE to set maximum current limit to 14A per text note.
36	IOUT	$23N3683	✅	IOUT pin connected through R146 (16.5kΩ) to AGND-VCORE with C47 (470pF) filtering for output current monitoring.
37	ILIM	VCORE-ILIM	✅	ILIM pin connected to current limit network with R95 (15.0kΩ) to VCORE-CSCOMP for current limit setting.
38	CSCOMP	VCORE-CSCOMP	✅	CSCOMP pin connected to current sense compensation network with C39 (470pF) and C40 (2200pF) to VCORE-CSSUM, plus temperature-dependent limiting via TH1.
39	CSSUM	VCORE-CSSUM	✅	CSSUM pin connected to current sense sum network with DCR sensing through R107 (100kΩ) to switch node via SP3.
40	CSREF	VCORE-CSREF	✅	CSREF pin connected to current sense reference network with R108 (10.0Ω) to output voltage via SP4 and C45 (1000pF) filtering.
41	FREQ	$23N2930	✅	FREQ pin connected through R93 (18.7kΩ) to AGND-VCORE to set switching frequency to 650kHz per text note.
42	COMP	VCORE-COMP	✅	COMP pin connected to voltage loop compensation network with Type III compensation using C35 (47pF) and C37 (2200pF).
43	FB	VCORE-FB	✅	FB pin connected to feedback network with R88 (3.01kΩ), R89 (1.00kΩ), and compensation capacitors for voltage regulation.
44	DIFFOUT	VCORE-DIFFOUT	✅	DIFFOUT pin connected to differential amplifier output network with R89 (1.00kΩ), R90 (47Ω), and C36 (220pF).
45	VSN	VR-VCORE-VSN	✅	VSN pin connected to negative remote sense with R65 (10.0Ω) filtering and R64 (0Ω) allowing connection to VSS_SENSE.
46	VSP	VR-VCORE-VSP	✅	VSP pin connected to positive remote sense with R92 (100Ω) to +VCORE and R63 (0Ω) allowing connection to VCC_SENSE.
47	VCC	$23N3860	✅	VCC pin connected to +5VSB through R166 (2.20Ω) with C24 (1.0µF) decoupling for main IC supply.
48	EN	$23N5607	✅	EN pin connected to +VCC through R849 (0Ω) with R851 (10.0kΩ) pull-down and C433 (0.1µF) filtering for enable control.

L18 - 3120-0266 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Pin 1 connects to the switching node VCORE-SW from the buck converter controller U25. This is the correct input connection for the output filter inductor.
2	2	+VCORE	✅	Pin 2 connects to the output voltage rail +VCORE. This is the correct output connection for the filter inductor.

L8 - 3120-0183 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 connects to the +5VSB input supply. This is the correct source connection for an input filter inductor.
2	2	+5VSB_SW	✅	Pin 2 connects to +5VSB_SW, which supplies the VCORE controller U25. This is the correct load connection for the input filter inductor.

R88 - 1120-0032 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2824	✅	Connected to internal compensation node $23N2824, forming part of a Type III compensation network with C37.
2	2	VCORE-FB	✅	Connected to VCORE-FB feedback net, completing the compensation network path to the FB pin of U25.

R89 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB, providing a DC path from the feedback node to the differential output.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT, forming a resistive path to U25 pin 44 for differential sensing.

R90 - 1121-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2818	✅	Connected to internal node $23N2818, which is part of the AC coupling path from FB through C36.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT, completing the AC-coupled path to the differential output pin.

C35 - 2220-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP, the compensation pin of the voltage regulator U25.
2	2	VCORE-FB	✅	Connected to VCORE-FB, providing direct high-frequency compensation between COMP and FB pins.

C36 - 2220-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB, providing AC coupling from the feedback node.
2	2	$23N2818	✅	Connected to internal node $23N2818, forming a series AC path with R90 to DIFFOUT.

C37 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP, forming part of the Type III compensation network.
2	2	$23N2824	✅	Connected to internal node $23N2824, forming a series RC compensation path with R88.

SP3 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	PCB bridge short connecting the switching node (VCORE-SW) to the current sense network ($23N3209) for DCR-based current measurement. This is a correct implementation of inductor DCR current sensing.
2	2	$23N3209	✅	PCB bridge short connecting the switching node (VCORE-SW) to the current sense network ($23N3209) for DCR-based current measurement. This is a correct implementation of inductor DCR current sensing.

TH1 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Thermistor connected between CSCOMP and the divider node ($23N3115), providing temperature-dependent current limiting. Connection is correct.
2	2	$23N3115	✅	Thermistor connected between CSCOMP and the divider node ($23N3115), providing temperature-dependent current limiting. Connection is correct.

R92 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	100 ohm resistor providing local +VCORE reference for the positive remote sense path. Connects +VCORE to VSP of U25.
2	2	VR-VCORE-VSP	✅	100 ohm resistor providing local +VCORE reference for the positive remote sense path. Connects +VCORE to VSP of U25.

R91 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	100 ohm resistor providing local ground reference for the negative remote sense path. Connects GND to the negative sense node which feeds VSN through R65.
2	2	$23N2860	✅	100 ohm resistor providing local ground reference for the negative remote sense path. Connects GND to the negative sense node which feeds VSN through R65.

R63 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_SENSE	✅	0 ohm jumper enabling remote positive voltage sensing from VCC_SENSE point. When populated, allows sensing at the load rather than at the regulator output.
2	2	VR-VCORE-VSP	✅	0 ohm jumper enabling remote positive voltage sensing from VCC_SENSE point. When populated, allows sensing at the load rather than at the regulator output.

R64 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VSS_SENSE	✅	0 ohm jumper enabling remote negative voltage sensing from VSS_SENSE point. When populated, allows sensing at the load ground rather than local ground.
2	2	$23N2860	✅	0 ohm jumper enabling remote negative voltage sensing from VSS_SENSE point. When populated, allows sensing at the load ground rather than local ground.

R65 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2860	✅	10 ohm series resistor connecting the negative sense node to VSN input of U25. Creates asymmetry with positive sense path, likely intentional for filtering or stability.
2	2	VR-VCORE-VSN	✅	10 ohm series resistor connecting the negative sense node to VSN input of U25. Creates asymmetry with positive sense path, likely intentional for filtering or stability.

R131 - 1120-0055 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to the thermistor network junction, forming a parallel path with TH2 to limit maximum resistance and set the temperature sensing range.
2	2	GND	✅	Connected to GND, providing the ground reference for the parallel resistor path.

R78 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	Connected to TSENSE pin of U25 and bypass capacitor C46, serving as the input to the temperature sensing network.
2	2	$23N3662	✅	Connected to the thermistor network junction, completing the series path from TSENSE to the temperature sensing elements.

TH2 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to the thermistor network junction with R131 and R78, forming the temperature-dependent voltage divider node for the TSENSE circuit.
2	2	GND	✅	Connected to GND, providing the ground reference for the temperature sensing voltage divider.

C46 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	Connected to TSENSE pin of U25, providing noise filtering and stability for the temperature sensing input.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE, providing proper analog ground reference for the bypass capacitor to minimize noise coupling.

R80 - 1120-0329 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Pin 1 connects to the external SVID_DATA-R signal. This is the input side of the series resistor for the SVID data line.
2	2	$23N2429	✅	Pin 2 connects to U25 pin 2 (SDIO) through net $23N2429. This is the controller side of the series resistor.

R81 - 1120-0099 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Pin 1 connects to the external SVID_CLK-R signal. This is the input side of the series resistor for the SVID clock line.
2	2	$23N2430	✅	Pin 2 connects to U25 pin 4 (SCLK) through net $23N2430. This is the controller side of the series resistor.

R62 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Pin 1 connects to the external SVID_ALERT-R signal. This is the input side of the series resistor (0 ohm jumper) for the SVID alert line.
2	2	$23N2431	✅	Pin 2 connects to U25 pin 3 (ALERT) through net $23N2431. This is the controller side of the series resistor.

C50 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3733	✅	Connected to R154 pin 2, receiving the bootstrap supply through the current-limiting resistor.
2	2	$23N3731	✅	Connected to U25 pin 10 (SW1), completing the bootstrap circuit between BST and SW pins.

R154 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3711	✅	Connected to U25 pin 8 (BST) as part of the bootstrap circuit for the high-side gate driver.
2	2	$23N3733	✅	Connected to C50 pin 1, forming the intermediate node between the bootstrap resistor and capacitor.

R93 - 1120-0351 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2930	✅	Connected to U25 pin 41 (FREQ) to set the switching frequency of the NCP81109 controller.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE (analog ground) to complete the frequency setting resistor configuration.

R146 - 1120-0338 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3683	✅	Connected to U25 pin 36 (IOUT) for output current monitoring. This resistor scales the current monitor output signal.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE, providing the ground reference for the current monitor circuit.

R105 - 1120-0115 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3681	✅	Connected to U25 pin 35 (IMAX) to set the maximum current limit. The design note indicates a target of 14A, but datasheet verification is needed to confirm the 44.2K value achieves this.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE, providing the ground reference for the current limit setting circuit.

C47 - 2220-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3683	✅	Connected to U25 pin 36 (IOUT) for filtering the current monitor output signal.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE, providing the ground reference for the filter capacitor.

C433 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N5607	✅	Connected to the enable pin (pin 48) of U25 through net $23N5607. This pin provides filtering for the enable signal.
2	2	GND	✅	Connected to GND. This pin provides the ground reference for the filter capacitor.

R851 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N5607	✅	Connected to the enable pin (pin 48) of U25 through net $23N5607. This pin provides the pull-down function for the enable circuit.
2	2	GND	✅	Connected to GND. This pin provides the ground reference for the pull-down resistor.

R849 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Connected to +VCC control voltage. This pin sources the enable signal for the regulator.
2	2	$23N5607	✅	Connected to the enable pin (pin 48) of U25 through net $23N5607. This pin drives the enable input of the NCP81109GMNTXG regulator.

R167 - 1120-0052 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Pin 1 connects to +VCC3 supply rail, providing pull-up voltage for the power good signal. This connection is correct.
2	2	VCORE_PG	✅	Pin 2 connects to VCORE_PG net, providing pull-up for the power good signal. This connection is correct.

R79 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Pin 1 connects to VCORE_PG net, which is the power good signal for the VCORE regulator. This connection is correct.
2	2	$23N3753	✅	Pin 2 connects to U25 pin 6 (VR_RDY), which is the voltage regulator ready output. This connection is correct.

C25 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Pin 1 connects to VCORE_PG net for filtering. This connection is correct.
2	2	GND	✅	Pin 2 connects to GND, providing filtering to ground for the power good signal. This connection is correct.

D4 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Incorrect part variant used. BAT54A has common anode configuration (pin 3 = anode, pins 1&2 = cathodes) which creates an AND gate, but the circuit requires common cathode configuration (BAT54C) for proper OR gate operation of power good signals.
2	2	VGFX_PG	✅	Incorrect part variant used. BAT54A has common anode configuration (pin 3 = anode, pins 1&2 = cathodes) which creates an AND gate, but the circuit requires common cathode configuration (BAT54C) for proper OR gate operation of power good signals.
3	3	VCORE_GFX_PG	✅	Incorrect part variant used. BAT54A has common anode configuration (pin 3 = anode, pins 1&2 = cathodes) which creates an AND gate, but the circuit requires common cathode configuration (BAT54C) for proper OR gate operation of power good signals.

R94 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_GFX_PG	✅	Connected to VCORE_GFX_PG combined power good signal. Pull-up resistor configuration is correct for OR gate, but effectiveness depends on correct diode part selection.
2	2	+VCC3	✅	Connected to +VCC3 supply rail. Correct connection for pull-up resistor function.

C65 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Correct connection for decoupling capacitor.
2	2	VCORE_GFX_PG	✅	Connected to VCORE_GFX_PG combined power good signal. Provides filtering on the digital signal.

R166 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail. This is the input side of the series resistor feeding the VCC pin of the controller.
2	2	$23N3860	✅	Connected to net $23N3860 which feeds the VCC pin of U25 and is decoupled by C24. This provides filtered power to the controller IC.

C24 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3860	✅	Connected to net $23N3860, the VCC supply node for U25. Provides decoupling for the controller IC's main supply voltage.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE, the analog ground for the VCORE regulator. This is the correct ground reference for the analog supply of the controller.

R845 - 1130-0193 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail. This is the input side of the series resistor feeding the VCCP pin of the controller.
2	2	$23N3625	✅	Connected to net $23N3625 which feeds the VCCP pin of U25 and is decoupled by C48. This provides filtered power to the charge pump circuitry.

C48 - 2232-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3625	✅	Connected to net $23N3625, the VCCP supply node for U25. Provides decoupling for the controller's charge pump supply voltage.
2	2	GND	✅	Connected to GND, the power ground. This is the correct ground reference for the charge pump supply which is part of the power stage.

R70 - 1120-0289 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3477	✅	Connected to VBOOT pin (pin 31) of U25 via net $23N3477. This resistor is part of a configuration circuit to set VBOOT to 1.1V for address configuration.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE (analog ground for the VCORE regulator section). This provides the ground reference for the VBOOT configuration circuit.

R37 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0-ohm jumper connecting power ground (GND) to analog ground (AGND-VCORE) at a single point. This is correct practice for mixed-signal power supply designs.
2	2	AGND-VCORE	✅	0-ohm jumper connecting power ground (GND) to analog ground (AGND-VCORE) at a single point. This is correct practice for mixed-signal power supply designs.

C87 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N			✅	Negative terminal correctly connected to GND for output filtering.
P			✅	Positive terminal correctly connected to +VCORE output rail for bulk capacitance.

C89 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.
2	2	GND	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.

C88 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.
2	2	GND	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.

C102 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.
2	2	GND	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.

R853 - 1130-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Resistor correctly connected between +VCORE and GND, likely serving as a pre-load or damping resistor.
2	2	GND	✅	Resistor correctly connected between +VCORE and GND, likely serving as a pre-load or damping resistor.

C90 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.
2	2	GND	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.

C101 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.
2	2	GND	✅	Ceramic output capacitor correctly connected between +VCORE and GND for output filtering.

U26 - NCP81109GMNTXG ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
9	GH		❌	GH (pin 9) and GL (pin 30) show no net connections. This is a critical error as these gate driver outputs must be connected to drive external MOSFETs. Pin 9 (GH) and pin 30 (GL) both show empty string for net connections (from schematic) GH is the high-side gate driver output and GL is the low-side gate driver output (reasoning) Pin 8 (BST) is connected to a bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) that connects to switch node pin 10 (SW1) (from schematic) The presence of a bootstrap circuit is definitive evidence that external MOSFETs are required, as bootstrap circuits are only needed to provide gate drive voltage for external high-side MOSFETs (reasoning) The controller has separate power ground pins (PGND1-PGND6 on pins 19-24) distinct from signal ground, which is typical for controllers with external MOSFETs (from schematic) Multiple switch node pins (SW1-SW7) and separate gate driver outputs indicate a multiphase controller with external power stage (reasoning) Text note 'IMAX = 24A' near the inductor area suggests high current capability requiring external MOSFETs (from schematic) If MOSFETs were integrated, there would be no need for external gate driver pins, bootstrap circuit, or separate power ground pins (reasoning) The empty net names suggest missing connections rather than off-page connections, as other nets in the design have proper net names (reasoning) Without connections to GH and GL, the external MOSFETs cannot be driven and the converter will not function (reasoning)
30	GL		❌	GH (pin 9) and GL (pin 30) show no net connections. This is a critical error as these gate driver outputs must be connected to drive external MOSFETs. Pin 9 (GH) and pin 30 (GL) both show empty string for net connections (from schematic) GH is the high-side gate driver output and GL is the low-side gate driver output (reasoning) Pin 8 (BST) is connected to a bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) that connects to switch node pin 10 (SW1) (from schematic) The presence of a bootstrap circuit is definitive evidence that external MOSFETs are required, as bootstrap circuits are only needed to provide gate drive voltage for external high-side MOSFETs (reasoning) The controller has separate power ground pins (PGND1-PGND6 on pins 19-24) distinct from signal ground, which is typical for controllers with external MOSFETs (from schematic) Multiple switch node pins (SW1-SW7) and separate gate driver outputs indicate a multiphase controller with external power stage (reasoning) Text note 'IMAX = 24A' near the inductor area suggests high current capability requiring external MOSFETs (from schematic) If MOSFETs were integrated, there would be no need for external gate driver pins, bootstrap circuit, or separate power ground pins (reasoning) The empty net names suggest missing connections rather than off-page connections, as other nets in the design have proper net names (reasoning) Without connections to GH and GL, the external MOSFETs cannot be driven and the converter will not function (reasoning)
1	VRHOT	VR_HOT_L	✅	VRHOT pin correctly connected to VR_HOT_L for thermal alert signaling.
2	SDIO	$24N3490	✅	SDIO pin correctly connected to SVID data line with series resistor and pull-up.
3	ALERT	$24N3492	✅	ALERT pin correctly connected to SVID alert line through 0Ω resistor.
4	SCLK	$24N3491	✅	SCLK pin correctly connected to SVID clock line with series resistor and pull-up.
5	GND	AGND-VGFX	✅	GND pin correctly connected to analog ground with 0Ω jumper to main ground.
6	VR_RDY	$24N3598	✅	VR_RDY pin correctly connected as power good output with pull-up and filtering.
7	VIN1	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
11	VIN2	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
12	VIN3	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
13	VIN4	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
14	VIN5	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
15	VIN6	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
16	VIN7	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
17	VIN8	+5VSB_SW	✅	VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling.
8	BST	$24N3593	✅	BST pin correctly connected to bootstrap circuit for high-side gate driver.
10	SW1	$24N3595	✅	SW1 pin correctly connected to switch node with bootstrap capacitor.
18	SW2	VGFX-SW	✅	SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation.
25	SW3	VGFX-SW	✅	SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation.
26	SW4	VGFX-SW	✅	SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation.
27	SW5	VGFX-SW	✅	SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation.
28	SW6	VGFX-SW	✅	SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation.
29	SW7	VGFX-SW	✅	SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation.
19	PGND1	GND	✅	PGND1-PGND6 pins correctly connected to main ground plane.
20	PGND2	GND	✅	PGND1-PGND6 pins correctly connected to main ground plane.
21	PGND3	GND	✅	PGND1-PGND6 pins correctly connected to main ground plane.
22	PGND4	GND	✅	PGND1-PGND6 pins correctly connected to main ground plane.
23	PGND5	GND	✅	PGND1-PGND6 pins correctly connected to main ground plane.
24	PGND6	GND	✅	PGND1-PGND6 pins correctly connected to main ground plane.
31	VBOOT	$24N3564	✅	VBOOT pin correctly configured with resistor to ground for voltage setting and I2C address.
32	GND1	AGND-VGFX	✅	GND1 pin correctly connected to analog ground.
33	VCCP	$24N3578	✅	VCCP pin correctly powered from +5VSB through series resistor with decoupling.
34	TSENSE	$24N3584	✅	TSENSE pin correctly configured with thermistor network for temperature monitoring.
35	IMAX	$24N3588	✅	IMAX pin correctly configured with resistor to set maximum current limit to 14A.
36	IOUT	$24N3589	✅	IOUT pin correctly configured for output current monitoring with resistor and filter capacitor.
37	ILIM	VGFX-ILIM	✅	ILIM pin correctly connected to current limit compensation network.
38	CSCOMP	VGFX-CSCOMP	✅	CSCOMP pin correctly configured with temperature-compensated current sense network.
39	CSSUM	VGFX-CSSUM	✅	CSSUM pin correctly connected to summed current sense network with compensation.
40	CSREF	VGFX-CSREF	✅	CSREF pin correctly connected to output voltage through resistor for current sense reference.
41	FREQ	$24N3542	✅	FREQ pin correctly configured with resistor to set switching frequency to 650kHz.
42	COMP	VGFX-COMP	✅	COMP pin correctly configured with voltage loop compensation network.
43	FB	VGFX-FB	✅	FB pin correctly configured with feedback divider and compensation network.
44	DIFFOUT	VGFX-DIFFOUT	✅	DIFFOUT pin correctly connected to differential amplifier network for remote sensing.
45	VSN	VR-VGFX-VSN	✅	VSN pin correctly configured for negative remote voltage sensing with DAC feed-forward.
46	VSP	VR-VGFX-VSP	✅	VSP pin correctly configured for positive remote voltage sensing.
47	VCC	$24N3610	✅	VCC pin correctly powered from +5VSB through series resistor with decoupling.
48	EN	$24N6011	✅	EN pin correctly configured with pull-down for enable control.
49	GND_PAD	AGND-VGFX	✅	GND_PAD correctly connected to analog ground for thermal and electrical performance.
50	VIN_PAD	+5VSB_SW	✅	VIN_PAD correctly connected to input power supply for current distribution.
51	SW_PAD	VGFX-SW	✅	SW_PAD correctly connected to switch node for current distribution.

L4 - 3120-0266 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Inductor input correctly connected to switch node VGFX-SW.
2	2	+VGFX	✅	Inductor output correctly connected to +VGFX output rail with adequate bulk and ceramic capacitance.

C76 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	Positive terminal correctly connected to +VGFX output rail.
2	N	GND	✅	Negative terminal correctly connected to ground.

C77 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	Positive terminal correctly connected to +VGFX output rail.
2	N	GND	✅	Negative terminal correctly connected to ground.

TH4 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	Thermistor correctly connected to temperature sense network for U26 TSENSE pin.
2	2	GND	✅	Thermistor correctly connected to ground to complete voltage divider.

TH3 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Thermistor correctly connected to current sense compensation network for temperature compensation.
2	2	$24N3557	✅	Thermistor correctly connected to intermediate node in compensation network.

R224 - 1130-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSSUM	✅	Resistor connects CSSUM pin to the switch node for DCR (DC resistance) current sensing.
2	2	$24N3558	✅	Resistor connects CSSUM pin to the switch node for DCR (DC resistance) current sensing.

R223 - 1120-0037 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3557	✅	Resistor completes the current sense compensation divider network, connecting the intermediate node to CSSUM pin.
2	2	VGFX-CSSUM	✅	Resistor completes the current sense compensation divider network, connecting the intermediate node to CSSUM pin.

R205 - 1120-0282 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Resistor connects CSCOMP pin to an intermediate node in the current sense compensation network, working with thermistor TH3 for temperature compensation.
2	2	$24N3557	✅	Resistor connects CSCOMP pin to an intermediate node in the current sense compensation network, working with thermistor TH3 for temperature compensation.

R207 - 1120-0115 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3588	✅	Resistor connects IMAX pin to analog ground to set the maximum current limit. Text note indicates target of 14A.
2	2	AGND-VGFX	✅	Resistor connects IMAX pin to analog ground to set the maximum current limit. Text note indicates target of 14A.

R225 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	Low-value resistor connects CSREF pin to the output voltage for DCR current sensing reference.
2	2	$24N3559	✅	Low-value resistor connects CSREF pin to the output voltage for DCR current sensing reference.

R227 - 1120-0338 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3589	✅	Resistor connects IOUT pin to analog ground for current monitoring, with C184 in parallel for filtering.
2	2	AGND-VGFX	✅	Resistor connects IOUT pin to analog ground for current monitoring, with C184 in parallel for filtering.

C113 - 2220-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Compensation capacitor connected between CSCOMP and CSSUM pins for current loop stability.
2	2	VGFX-CSSUM	✅	Compensation capacitor connected between CSCOMP and CSSUM pins for current loop stability.

C167 - 2220-0035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	Filter capacitor connected between CSREF pin and ground for current sense reference filtering.
2	2	GND	✅	Filter capacitor connected between CSREF pin and ground for current sense reference filtering.

R204 - 1120-0029 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-ILIM	✅	Resistor connects ILIM pin to CSCOMP pin of the controller, forming part of the current limit compensation network.
2	2	VGFX-CSCOMP	✅	Resistor connects ILIM pin to CSCOMP pin of the controller, forming part of the current limit compensation network.

C166 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Additional compensation capacitor in parallel with C113 between CSCOMP and CSSUM pins.
2	2	VGFX-CSSUM	✅	Additional compensation capacitor in parallel with C113 between CSCOMP and CSSUM pins.

R850 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	0Ω jumper resistor connecting +VCC power rail to the enable pin (EN, pin 48) of U26 voltage regulator through net $24N6011. This enables the regulator when +VCC is present.
2	2	$24N6011	✅	0Ω jumper resistor connecting +VCC power rail to the enable pin (EN, pin 48) of U26 voltage regulator through net $24N6011. This enables the regulator when +VCC is present.

R852 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	10kΩ pull-down resistor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This ensures the enable pin is at a defined low state when +VCC is absent or during power-up.
2	2	GND	✅	10kΩ pull-down resistor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This ensures the enable pin is at a defined low state when +VCC is absent or during power-up.

C434 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	0.1µF decoupling capacitor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This provides noise filtering to prevent false triggering of the enable input.
2	2	GND	✅	0.1µF decoupling capacitor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This provides noise filtering to prevent false triggering of the enable input.

SP2 - PCB_BRIDGE_SHORT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to VGFX-SW switching node. This short provides a connection from the switching node to the current sense sum circuit.
2	2	$24N3558	✅	Connected to $24N3558 which leads to VGFX-CSSUM through R224. This completes the current sense sum connection.

R231 - 1141-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to VGFX-SW switching node. This is the input to an RC snubber network.
2	2	$24N3623	✅	Connected to intermediate net $24N3623 which connects to C187, completing the RC snubber to ground.

C187 - 2240-0005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3623	✅	Connected to intermediate net $24N3623 from R231, forming the capacitive element of the RC snubber.
2	2	GND	✅	Connected to GND, completing the snubber path from switching node to ground.

SP1 - PCB_BRIDGE_SHORT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Connected to +VGFX output. This short provides a connection from the output to the current sense reference circuit.
2	2	$24N3559	✅	Connected to $24N3559 which leads to VGFX-CSREF through R225. This completes the current sense reference connection.

R854 - 1130-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Connected to +VGFX output voltage. This resistor provides a minimum load for the DC/DC converter.
2	2	GND	✅	Connected to GND, completing the minimum load path.

R228 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3593	✅	Connected to U26 pin 8 (BST) for bootstrap circuit. This connection is correct for providing bootstrap power to the high-side gate driver.
2	2	$24N3596	✅	Connected through C186 to U26 pin 10 (SW1). This forms the bootstrap circuit with R228 limiting inrush current to the bootstrap capacitor.

C186 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3596	✅	Connected through R228 to U26 pin 8 (BST). This is the positive terminal of the bootstrap capacitor.
2	2	$24N3595	✅	Connected to U26 pin 10 (SW1). This is the negative terminal of the bootstrap capacitor, correctly connected to the switch node.

C60 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Connected to VGFX_PG net, providing filtering for the power good signal.
2	2	GND	✅	Connected to GND, providing the return path for the bypass capacitor.

R230 - 1120-0052 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Connected to +VCC3 power rail, providing pull-up voltage for the power good signal.
2	2	VGFX_PG	✅	Connected to VGFX_PG net, pulling up the power good signal to +VCC3.

R184 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Connected to VGFX_PG net, which is the power good signal output from the voltage regulator.
2	2	$24N3598	✅	Connected to U26 pin 6 (VR_RDY), the voltage regulator ready output signal.

R203 - 1120-0351 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3542	✅	Pin 1 connects to the FREQ pin (pin 41) of U26 (NCP81109GMNTXG voltage regulator) to set the switching frequency. A nearby text note indicates the target frequency is 650 kHz.
2	2	AGND-VGFX	✅	Pin 2 connects to AGND-VGFX, which is the analog ground for the VGFX power domain, providing the ground reference for the frequency-setting resistor.

R170 - 1120-0009 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3564	❌	R170 is configured as a pull-down resistor from VBOOT to ground. However, a text note indicates VBOOT should be 1.1V to set ADDR to 0x1, which is inconsistent with a pull-down to ground. Pin 1 is connected to net $24N3564, which connects to U26 pin 31 (VBOOT) (from schematic) Pin 2 is connected to AGND-VGFX (analog ground) (from schematic) R170 is a 100K resistor configured as a pull-down from VBOOT to ground (reasoning) A text note on the schematic states 'VBOOT = 1.1V ADDR = 0x1' (from schematic) The text note indicates that to achieve address 0x1, VBOOT should be at 1.1V (reasoning) A pull-down resistor to ground would set VBOOT to approximately 0V, not 1.1V (reasoning) The pull-down configuration is inconsistent with the text note requirement of VBOOT = 1.1V for address 0x1 (reasoning) Without the NCP81109GMNTXG datasheet, the exact VBOOT configuration requirements cannot be verified (reasoning) To set VBOOT to 1.1V, a pull-up to a 1.1V supply or a voltage divider would be needed instead of a pull-down (reasoning) The design team should verify the intended address setting and update either the circuit or the text note to resolve the inconsistency (reasoning)
2	2	AGND-VGFX	❌	R170 is configured as a pull-down resistor from VBOOT to ground. However, a text note indicates VBOOT should be 1.1V to set ADDR to 0x1, which is inconsistent with a pull-down to ground. Pin 1 is connected to net $24N3564, which connects to U26 pin 31 (VBOOT) (from schematic) Pin 2 is connected to AGND-VGFX (analog ground) (from schematic) R170 is a 100K resistor configured as a pull-down from VBOOT to ground (reasoning) A text note on the schematic states 'VBOOT = 1.1V ADDR = 0x1' (from schematic) The text note indicates that to achieve address 0x1, VBOOT should be at 1.1V (reasoning) A pull-down resistor to ground would set VBOOT to approximately 0V, not 1.1V (reasoning) The pull-down configuration is inconsistent with the text note requirement of VBOOT = 1.1V for address 0x1 (reasoning) Without the NCP81109GMNTXG datasheet, the exact VBOOT configuration requirements cannot be verified (reasoning) To set VBOOT to 1.1V, a pull-up to a 1.1V supply or a voltage divider would be needed instead of a pull-down (reasoning) The design team should verify the intended address setting and update either the circuit or the text note to resolve the inconsistency (reasoning)

C168 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	Connected to TSENSE pin of U26 via net $24N3584. Provides filtering for the temperature sensing circuit.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX, providing a ground reference for the TSENSE filter capacitor.

R178 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	Connected to TSENSE pin of U26 via net $24N3584. Acts as a 0-ohm series connection between TSENSE and the temperature sensing network.
2	2	$24N3583	✅	Connected to the temperature sensing network via net $24N3583, which includes thermistor TH4 and parallel resistor R226.

R226 - 1120-0055 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	Connected to the temperature sensing network via net $24N3583, in parallel with thermistor TH4.
2	2	GND	✅	Connected to GND, completing the temperature sensing voltage divider network.

R66 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0-ohm jumper connecting main power ground (GND) to analog ground (AGND-VGFX), providing single-point ground connection for the DC-DC converter.
2	2	AGND-VGFX	✅	0-ohm jumper connecting main power ground (GND) to analog ground (AGND-VGFX), providing single-point ground connection for the DC-DC converter.

U41 - RT8207 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
12	TON	$25N1081	❌	TON pin has incorrect resistor value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency. Current value results in ~500kHz operation. Pin 12 (TON) is connected to net $25N1081 (from schematic) Net $25N1081 connects to R816 (464K to +5VSB) and C378 (0.1uF to GND, DNI) (from schematic) Schematic note specifies 'Rton=806K, F=285KHz' as design requirement (from schematic) With R816=464K, VVDDQ=1.35V, VIN=5V: tON = 3.85p × 464K × 1.35 / 4.5 = 537ns (reasoning) Calculated switching frequency with 464K is f = 1.35 / (5 × 537n) = 503kHz (reasoning) With specified 806K: tON = 3.85p × 806K × 1.35 / 4.5 = 933ns, f = 289kHz (reasoning) Actual resistor value of 464K does not meet the design constraint of 806K for 285kHz operation (reasoning) R816 should be changed to 806K to meet the specified switching frequency (reasoning)
1	VTTGND	GND	✅	VTTGND pin correctly connected to ground plane for VTT LDO power ground.
2	VTTSNS	+VDIMM_VTT	✅	VTTSNS pin correctly connected to +VDIMM_VTT output for remote voltage sensing.
3	GND	GND	✅	GND pin correctly connected to ground plane for analog ground.
4	MODE	GND	✅	MODE pin connected to ground. Function uncertain as this pin is not documented in the RT8207P datasheet, suggesting a different package variant.
5	VTTREF	$25N769	✅	VTTREF pin correctly connected to buffered reference output with 0.22uF bypass capacitor C342.
6	DEM	$25N1291	✅	DEM pin connected to voltage divider with 10K pull-up to +5VSB and 10K pull-down (DNI). Function uncertain as this pin is not in RT8207P datasheet.
8	VDDQ	+VDIMM	✅	VDDQ pin correctly connected to +VDIMM output for reference input and discharge control.
9	FB	$25N987	✅	FB pin correctly configured with resistive voltage divider (R814=8.06K, R815=10K) and compensation capacitor (C382=22pF) for 1.35V output.
10	S3	EN_VTT	✅	S3 pin correctly connected to EN_VTT signal through 0-ohm resistor R302 from SLP_S3_L for VTT power state control.
11	S5	EN_VDDQ	✅	S5 pin correctly connected to EN_VDDQ signal through 0-ohm resistor R300 from SLP_S4_L for VDDQ power state control.
13	PGOOD	DRAM_PWROK	✅	PGOOD pin correctly connected to DRAM_PWROK open-drain output with 10K pull-up resistor R124 to +VDIMM.
14	VDD	$25N1195	✅	VDD pin correctly connected to +5VSB through RC filter (R813=2.2Ω, C380=1uF). Resistor value is lower than datasheet recommendation of 5.1Ω but likely intentional.
15	VDDP	+5VSB	✅	VDDP pin correctly connected to +5VSB supply with 1uF bypass capacitor C379.
16	CS	$25N1238	✅	CS pin correctly configured with 3.83K resistor R817 from VDD for current limit threshold setting.
18	PGND	GND	✅	PGND pin correctly connected to ground plane for low-side MOSFET power ground.
19	LGATE	$25N901	✅	LGATE pin correctly connected to Q102 pin 8 (Q2G) for low-side MOSFET gate drive.
20	PHASE	DDR_PHASE	✅	PHASE pin correctly connected to switching node with output inductor L11 and bootstrap capacitor C309.
21	UGATE	$25N897	✅	UGATE pin correctly connected to Q102 pin 1 (Q1G) for high-side MOSFET gate drive.
22	BOOT	$25N771	✅	BOOT pin correctly connected to bootstrap network with C309 (0.1µF) and optional series resistor R298 (4.7Ω) for gate drive, matching the datasheet typical application values.
23	VLDOIN	+VDIMM	✅	VLDOIN pin correctly connected to +VDIMM for VTT LDO power supply and tracking discharge mode.
24	VTT	+VDIMM_VTT	✅	VTT pin correctly connected to +VDIMM_VTT output rail with appropriate output capacitors.
25	GND_PAD	GND	✅	GND_PAD (exposed pad) correctly connected to ground plane for thermal dissipation.

R814 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	R814 forms the upper resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L.
2	2	$25N987	✅	R814 forms the upper resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L.

R815 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N987	✅	R815 forms the lower resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L.
2	2	GND	✅	R815 forms the lower resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L.

C382 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	C382 provides compensation for the feedback loop of the voltage regulator.
2	2	$25N987	✅	C382 provides compensation for the feedback loop of the voltage regulator.

R816 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	❌	On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead. R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) (from schematic) Schematic note specifies 'Rton=806K, F=285KHz' as design requirement (from schematic) With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz (reasoning) With specified 806K: calculated frequency is ~289kHz, matching the design target (reasoning) The 464K value does not meet the design constraint of 285kHz operation (reasoning) R816 should be changed to 806K to achieve the specified 285kHz switching frequency (reasoning)
2	2	$25N1081	❌	On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead. R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) (from schematic) Schematic note specifies 'Rton=806K, F=285KHz' as design requirement (from schematic) With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz (reasoning) With specified 806K: calculated frequency is ~289kHz, matching the design target (reasoning) The 464K value does not meet the design constraint of 285kHz operation (reasoning) R816 should be changed to 806K to achieve the specified 285kHz switching frequency (reasoning)

R817 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	R817 sets the current limit threshold to approximately 11A for the VDDQ output.
2	2	$25N1238	✅	R817 sets the current limit threshold to approximately 11A for the VDDQ output.

C342 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	C342 provides bypass capacitance for VTTREF, using 0.22µF which is larger than the 33nF recommended by the datasheet but should provide adequate filtering.
2	2	$25N769	✅	C342 provides bypass capacitance for VTTREF, using 0.22µF which is larger than the 33nF recommended by the datasheet but should provide adequate filtering.

R810 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1291	✅	R810 provides a pull-up to +5VSB for the DEM pin, configuring the diode emulation mode operation.
2	2	+5VSB	✅	R810 provides a pull-up to +5VSB for the DEM pin, configuring the diode emulation mode operation.

R813 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	R813 provides filtering for the VDD supply, using 2.2 ohms instead of the 5.1 ohms recommended by the datasheet, which provides less filtering but also less voltage drop.
2	2	+5VSB	✅	R813 provides filtering for the VDD supply, using 2.2 ohms instead of the 5.1 ohms recommended by the datasheet, which provides less filtering but also less voltage drop.

C379 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	C379 provides input bypass capacitance for the +5VSB supply.
2	2	+5VSB	✅	C379 provides input bypass capacitance for the +5VSB supply.

C380 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	C380 provides bypass capacitance for the VDD supply, matching the 1µF recommendation from the datasheet.
2	2	$25N1195	✅	C380 provides bypass capacitance for the VDD supply, matching the 1µF recommendation from the datasheet.

R298 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N771	✅	R298 (4.7Ω) is correctly placed in series between the controller BOOT pin and the bootstrap capacitor to limit inrush current and provide damping.
2	2	DDR_BST	✅	R298 (4.7Ω) is correctly placed in series between the controller BOOT pin and the bootstrap capacitor to limit inrush current and provide damping.

C309 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_PHASE	✅	C309 (0.1uF) is correctly configured as the bootstrap capacitor between the phase node and the BOOT supply.
2	2	DDR_BST	✅	C309 (0.1uF) is correctly configured as the bootstrap capacitor between the phase node and the BOOT supply.

Q102 - FDMS3604S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	Q1G	$25N897	✅	Q1G (gate of control FET Q1) is correctly connected to the upper gate drive signal from the controller.
2	VIN_A	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (drain pins of control FET Q1) are correctly connected to the input voltage rail DDR3L_VIN.
3	VIN_B	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (drain pins of control FET Q1) are correctly connected to the input voltage rail DDR3L_VIN.
4	VIN_C	DDR3L_VIN	✅	VIN_A, VIN_B, VIN_C (drain pins of control FET Q1) are correctly connected to the input voltage rail DDR3L_VIN.
5	PGND_A	GND	✅	PGND_A, PGND_B, PGND_C (source pins of sync FET Q2) are correctly connected to ground.
6	PGND_B	GND	✅	PGND_A, PGND_B, PGND_C (source pins of sync FET Q2) are correctly connected to ground.
7	PGND_C	GND	✅	PGND_A, PGND_B, PGND_C (source pins of sync FET Q2) are correctly connected to ground.
8	Q2G	$25N901	✅	Q2G (gate of sync FET Q2) is correctly connected to the lower gate drive signal from the controller.
9	PHASE	DDR_PHASE	✅	PHASE (switch node) is correctly connected to the output inductor, bootstrap capacitor, and controller phase feedback.

C129 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VDIMM	✅	C129 is correctly connected as an output filter capacitor between +VDIMM and GND. However, its 2V voltage rating for a 1.35V output provides only 48% margin (0.65V), which is below the typical 2× margin guideline.
2	N	GND	✅	C129 is correctly connected as an output filter capacitor between +VDIMM and GND. However, its 2V voltage rating for a 1.35V output provides only 48% margin (0.65V), which is below the typical 2× margin guideline.

C127 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Negative terminal of bulk input capacitor connected to ground.
2	2	DDR3L_VIN	✅	Positive terminal of bulk input capacitor connected to DDR3L_VIN.

C126 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Negative terminal of bulk input capacitor connected to ground.
2	2	DDR3L_VIN	✅	Positive terminal of bulk input capacitor connected to DDR3L_VIN.

C328 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Negative terminal of bulk input capacitor connected to ground.
2	2	DDR3L_VIN	✅	Positive terminal of bulk input capacitor connected to DDR3L_VIN.

C327 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Negative terminal of high-frequency decoupling capacitor connected to ground.
2	2	DDR3L_VIN	✅	Positive terminal of high-frequency decoupling capacitor connected to DDR3L_VIN.

L5 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input side of ferrite bead connected to +5VSB supply rail.
2	2	DDR3L_VIN	✅	Output side of ferrite bead connected to DDR3L_VIN, the filtered input to the DDR voltage regulator.

C128 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Negative terminal of bulk input capacitor connected to ground.
2	2	DDR3L_VIN	✅	Positive terminal of bulk input capacitor connected to DDR3L_VIN.

L6 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input side of ferrite bead connected to +5VSB supply rail.
2	2	DDR3L_VIN	✅	Output side of ferrite bead connected to DDR3L_VIN, the filtered input to the DDR voltage regulator.

C361 - 2232-0012 ✅

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ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM_VTT	✅	Connected to +VDIMM_VTT rail, providing bulk decoupling capacitance for the DDR VTT termination voltage.
2	2	GND	✅	Connected to GND, completing the decoupling path for the +VDIMM_VTT rail.

C362 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM_VTT	✅	Connected to +VDIMM_VTT rail in parallel with C361, providing additional bulk decoupling capacitance.
2	2	GND	✅	Connected to GND, completing the decoupling path for the +VDIMM_VTT rail.

C343 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the return path for high-frequency decoupling.
2	2	+VDIMM_VTT	✅	Connected to +VDIMM_VTT rail, providing high-frequency decoupling for the DDR VTT termination voltage.

R23 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pin 1 is correctly connected to +V1P8S (VOUT of U21), providing the pull-up voltage source.
2	2	+V1P8S_PGD	✅	Pin 2 is correctly connected to +V1P8S_PGD (PGOOD pin of U21), completing the pull-up resistor configuration.

R24 - 110-0002560 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pin 1 is correctly connected to +V1P8S (VOUT of U21), forming the upper resistor of the feedback divider.
2	2	+V1P8S_FB	✅	Pin 2 is correctly connected to +V1P8S_FB (ADJ pin of U21), forming the feedback node of the divider.

R22 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1P8V_EN	✅	Pin 1 is correctly connected to 1P8V_EN, which is the enable signal source.
2	2	+V1P8S_EN	✅	Pin 2 is correctly connected to +V1P8S_EN, which connects to U21's enable pin.

R25 - 110-0004490 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to GND, forming the lower resistor of the feedback divider.
2	2	+V1P8S_FB	✅	Pin 2 is correctly connected to +V1P8S_FB (ADJ pin of U21), forming the feedback node of the divider.

U21 - APL5933 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P8S_PGD	✅	PGOOD pin is correctly connected to +V1P8S_PGD net with a 4.7K pull-up resistor (R23) to the output voltage +V1P8S.
2	EN	+V1P8S_EN	✅	EN pin is correctly connected through R22 (0 ohm jumper) to the 1P8V_EN enable signal, which is pulled up to +VCC through R125 (4.7K).
3	VIN	+PS_3VSB	✅	VIN pin is correctly connected to the +PS_3VSB input power supply rail.
4	VDD	+PS_3VSB	✅	VDD pin is correctly connected to the +PS_3VSB input power supply rail, same as VIN.
5	NC		✅	NC pin is correctly left unconnected as specified.
6	VOUT	+V1P8S	✅	VOUT pin is correctly connected to the +V1P8S output rail with appropriate bypass capacitors C8 (10uF), C4 (0.1uF), and C7 (22uF).
7	ADJ	+V1P8S_FB	✅	ADJ pin is correctly connected to the feedback divider network consisting of R24 (12.1K) and R25 (9.53K), which sets the output voltage to approximately 1.8V.
8	GND1	GND	✅	GND1 and GND2 pins are both correctly connected to the GND net.
9	GND2	GND	✅	GND1 and GND2 pins are both correctly connected to the GND net.

R134 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	Connected to V1P0S_PG power good signal from U38 pin 7. This is the input side of the gate drive resistor that controls Q5.
2	2	1P35V_EN	✅	Connected to 1P35V_EN which drives the gate of Q5. This is the output side of the gate drive resistor. The 1K value provides appropriate gate current limiting and switching speed control.

R120 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Connected to +V1P35S output rail from Q5 source. This is the input side of the power good sense resistor.
2	2	1P35V_PWG	✅	Connected to 1P35V_PWG signal which drives the base of Q3 for power sequencing logic. This is the output side of the power good sense resistor.

Q5 - RXR035N03 ✅

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📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+VDIMM	✅	Drain pin correctly connected to +VDIMM input power rail. This is the input side of the high-side load switch.
G	GATE	1P35V_EN	✅	Gate pin correctly connected to 1P35V_EN control signal through R134. The gate drive voltage must be sufficient to provide VGS > 2V as noted on the schematic.
S	SOURCE	+V1P35S	✅	Source pin correctly connected to +V1P35S output rail. This is the output side of the high-side load switch providing 1.35V to downstream circuits.

U38 - APL5912KAC-TRGS-X ❌

DRCY flagged 1 potential issues in this component.

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Pin Designator	Pin Name	Net	Correct?	Analysis
5	VIN-2	+VDIMM	❌	VIN-1 and VIN-2 pins connected to +VDIMM, but circuit has fundamental design flaws preventing operation: (1) Circular startup dependency - U38 requires +VDIMM to operate, but +VDIMM is only available after U38 asserts power good to enable Q5, (2) Q5 current rating insufficient (3.5A max vs 4.9A required), (3) Q5 voltage drop excessive, leaving insufficient input voltage for regulation. Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic) +VDIMM is sourced from +V1P35S (1.35V) through Q5, an N-channel MOSFET (RXR035N03) (from schematic) Q5 gate (1P35V_EN) is controlled by U38's power good output (V1P0S_PG) through R134 (1K) (from schematic) This creates a circular dependency: U38 needs +VDIMM to start up and generate V1P0S_PG, but +VDIMM is only available when Q5 is enabled by V1P0S_PG (reasoning) At startup with Q5 off, the body diode would conduct from +V1P35S to +VDIMM, providing approximately 1.35V - 0.7V = 0.65V (reasoning) With only 0.65V input, U38 cannot regulate a 1.0V output, preventing circuit startup (reasoning) Schematic note near Q5 specifies 'Id MAX = 3.5 Amps' for Q5's maximum drain current (from schematic) Text notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic) The required 4.9A exceeds Q5's 3.5A rating by 40%, making Q5 severely undersized (reasoning) Schematic notes specify Q5 Rds(on) as 'VGS=5V Rds(on)=90m MAX' (from schematic) With gate driven to approximately 5V and source at 1.35V, Vgs = 3.65V, resulting in Rds(on) higher than the specified 90mΩ at Vgs=5V (reasoning) At 4.9A with Rds(on) ≈ 100mΩ, voltage drop across Q5 is approximately 0.49V (reasoning) +VDIMM would be only 1.35V - 0.49V = 0.86V, which is insufficient for U38 to regulate a 1.0V output (negative dropout voltage) (reasoning) The circuit has three critical design errors: (1) circular startup dependency preventing initial operation, (2) Q5 current rating insufficient for the load, (3) excessive voltage drop across Q5 preventing proper regulation even if startup were possible (reasoning) Input decoupling capacitor C118 (10uF) is present on +VDIMM (from schematic)
9	VIN-1	+VDIMM	❌	VIN-1 and VIN-2 pins connected to +VDIMM, but circuit has fundamental design flaws preventing operation: (1) Circular startup dependency - U38 requires +VDIMM to operate, but +VDIMM is only available after U38 asserts power good to enable Q5, (2) Q5 current rating insufficient (3.5A max vs 4.9A required), (3) Q5 voltage drop excessive, leaving insufficient input voltage for regulation. Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic) +VDIMM is sourced from +V1P35S (1.35V) through Q5, an N-channel MOSFET (RXR035N03) (from schematic) Q5 gate (1P35V_EN) is controlled by U38's power good output (V1P0S_PG) through R134 (1K) (from schematic) This creates a circular dependency: U38 needs +VDIMM to start up and generate V1P0S_PG, but +VDIMM is only available when Q5 is enabled by V1P0S_PG (reasoning) At startup with Q5 off, the body diode would conduct from +V1P35S to +VDIMM, providing approximately 1.35V - 0.7V = 0.65V (reasoning) With only 0.65V input, U38 cannot regulate a 1.0V output, preventing circuit startup (reasoning) Schematic note near Q5 specifies 'Id MAX = 3.5 Amps' for Q5's maximum drain current (from schematic) Text notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic) The required 4.9A exceeds Q5's 3.5A rating by 40%, making Q5 severely undersized (reasoning) Schematic notes specify Q5 Rds(on) as 'VGS=5V Rds(on)=90m MAX' (from schematic) With gate driven to approximately 5V and source at 1.35V, Vgs = 3.65V, resulting in Rds(on) higher than the specified 90mΩ at Vgs=5V (reasoning) At 4.9A with Rds(on) ≈ 100mΩ, voltage drop across Q5 is approximately 0.49V (reasoning) +VDIMM would be only 1.35V - 0.49V = 0.86V, which is insufficient for U38 to regulate a 1.0V output (negative dropout voltage) (reasoning) The circuit has three critical design errors: (1) circular startup dependency preventing initial operation, (2) Q5 current rating insufficient for the load, (3) excessive voltage drop across Q5 preventing proper regulation even if startup were possible (reasoning) Input decoupling capacitor C118 (10uF) is present on +VDIMM (from schematic)
1	GND	GND	✅	GND pin correctly connected to ground reference.
2	FB	FB_V1P0S	✅	FB pin correctly connected to feedback network for 1.025V output voltage.
3	VOUT-2	+V1P0S	✅	VOUT-1 and VOUT-2 pins correctly connected together to +V1P0S output rail.
4	VOUT-1	+V1P0S	✅	VOUT-1 and VOUT-2 pins correctly connected together to +V1P0S output rail.
6	VCNTL	VCNTL_V1P0S	✅	VCNTL pin connected to soft-start network with 10 ohm resistor to +VCC and 1uF capacitor to ground. Configuration appears reasonable but should be verified against datasheet.
7	POK	V1P0S_PG	✅	POK pin correctly connected to power good output with pull-up resistor and used for downstream sequencing.
8	EN	1P0V_EN	✅	EN pin correctly connected to enable signal from graphics core power good through 0-ohm jumper.

R150 - 110-0002560 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	R150 is correctly configured as the upper feedback resistor (R1) in the voltage divider for U20's adjustable output voltage.
2	2	+V1P8A	✅	R150 is correctly configured as the upper feedback resistor (R1) in the voltage divider for U20's adjustable output voltage.

R153 - 110-0002726 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	R153 is correctly configured as the lower feedback resistor (R2) in the voltage divider for U20's adjustable output voltage.
2	2	GND	✅	R153 is correctly configured as the lower feedback resistor (R2) in the voltage divider for U20's adjustable output voltage.

R151 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	R151 is correctly configured as a 0-ohm jumper to provide power sequencing from U24's power good signal to U20's enable input.
2	2	+V1P8A_EN	✅	R151 is correctly configured as a 0-ohm jumper to provide power sequencing from U24's power good signal to U20's enable input.

U20 - NCP606 ✅

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📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN1	+PS_3VSB	✅	VIN1 is correctly connected to +PS_3VSB input power supply.
2	GND	GND	✅	GND is correctly connected to ground.
3	EN	+V1P8A_EN	✅	EN is correctly connected to +V1P8A_EN for power sequencing control.
4	VOUT	+V1P8A	✅	VOUT is correctly connected to +V1P8A output rail with adequate output capacitance.
5	SENSE/ADJ	+V1P8A_FB	✅	SENSE/ADJ is correctly connected to feedback divider network for 1.8V output voltage.
6	VIN2	+PS_3VSB	✅	VIN2 is correctly connected to +PS_3VSB input power supply.
7	GND_PAD	GND	✅	GND_PAD (exposed pad) is correctly connected to ground.

R33 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB	✅	Power-good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin for open-drain output.
2	2	+V1P0A_PWRGD	✅	Power-good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin for open-drain output.

R32 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Enable pull-up resistor correctly connected between +5VSB and EN pin, ensuring enable threshold is met.
2	2	+V1P0A_ENABLE	✅	Enable pull-up resistor correctly connected between +5VSB and EN pin, ensuring enable threshold is met.

U24 - APL5933 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P0A_PWRGD	✅	PGOOD output is correctly connected to power sequencing logic with appropriate pull-up resistor R33 to +PS_3VSB.
2	EN	+V1P0A_ENABLE	✅	EN input is correctly pulled up to +5VSB through R32 with decoupling capacitor C20, meeting the >1.1V enable threshold requirement.
3	VIN	+PS_3VSB	✅	VIN input is correctly connected to +PS_3VSB supply with adequate input bypass capacitors.
4	VDD	+PS_3VSB	✅	VDD control supply is correctly connected to +PS_3VSB, same as VIN.
5	NC		✅	NC pin is correctly left unconnected.
6	VOUT	+V1P0A	✅	VOUT is correctly connected to +V1P0A rail with appropriate output capacitors C21 (22uF) and C22 (0.1uF).
7	ADJ	+V1P0A_FB	✅	ADJ feedback pin is correctly connected to resistor divider formed by R34 (6.04K) and R35 (23.7K), setting output voltage to approximately 1.0V.
8	GND1	GND	✅	Both ground pins are correctly connected to GND net.
9	GND2	GND	✅	Both ground pins are correctly connected to GND net.

R35 - 110-0004494 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Lower feedback resistor correctly connected between ADJ pin and GND, setting output voltage to 1.0V with R34.
2	2	GND	✅	Lower feedback resistor correctly connected between ADJ pin and GND, setting output voltage to 1.0V with R34.

R34 - 110-0003781 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Upper feedback resistor correctly connected between ADJ pin and VOUT, setting output voltage to 1.0V with R35.
2	2	+V1P0A	✅	Upper feedback resistor correctly connected between ADJ pin and VOUT, setting output voltage to 1.0V with R35.

D11 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	Anode 1 connected to +V1P0A_PWRGD power good signal.
2	2	SLP_S3_L	✅	Anode 2 connected to SLP_S3_L sleep state signal.
3	3	PSGOOD	✅	Common cathode connected to PSGOOD signal, forming a diode OR gate output.

Q3 - MBT3904 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter 1 (E1) correctly connected to GND for NPN transistor operation.
2	B1	1P35V_PWG	✅	Base 1 (B1) connected to 1P35V_PWG signal, pulled up to +V1P35S through R120 (10K).
3	C2	1P8V_EN	✅	Collector 2 (C2) connected to 1P8V_EN output, pulled up to +VCC through R125 (4.7K).
4	E2	GND	✅	Emitter 2 (E2) correctly connected to GND for NPN transistor operation.
5	B2	1P5V_EN_B	✅	Base 2 (B2) connected to 1P5V_EN_B signal, which is also connected to pin 6 (C1), forming a feedback path.
6	C1	1P5V_EN_B	✅	Collector 1 (C1) connected to 1P5V_EN_B signal, which also connects to pin 5 (B2), forming a two-stage switching circuit.

Q1 - MBT3904 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter 1 (E1) correctly connected to GND for NPN transistor operation.
2	B1	PSGOOD	✅	Base 1 (B1) connected to PSGOOD signal, which is driven by diode OR gate D11 and pulled up through R206 (200K) to +V1P8S.
3	C2	SYS_PWRGD	✅	Collector 2 (C2) connected to SYS_PWRGD output, pulled up to +VCC3 through R61 (20K).
4	E2	GND	✅	Emitter 2 (E2) correctly connected to GND for NPN transistor operation.
5	B2	PSPUP	✅	Base 2 (B2) connected to PSPUP signal, which is also connected to pin 6 (C1), forming a feedback path.
6	C1	PSPUP	✅	Collector 1 (C1) connected to PSPUP signal, which also connects to pin 5 (B2), forming a two-stage switching circuit.

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• R151, R192, R216, R22, R243, R261, R293, R300, R302, R306, R353, R354, R48, R51, R72, R73, R74 (110-0001853): 📤 Upload a datasheet
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• R120, R124, R190, R191, R2, R211, R220, R221, R268, R319, R400, R706, R71, R75, R84, R97 (110-0001875): 📤 Upload a datasheet
• R134, R186, R187, R208, R234, R259 (110-0001923): 📤 Upload a datasheet
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• R125, R126, R144, R149, R23, R310, R32, R325, R326, R33 (110-0002058): 📤 Upload a datasheet
• R222, R265, R275 (110-0002124): 📤 Upload a datasheet
• R150, R24 (110-0002560): 📤 Upload a datasheet
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• R240, R241, R242, R258 (110-0003059): 📤 Upload a datasheet
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• FB3 (126-0001423): 📤 Upload a datasheet
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• D3 (130-0004403): 📤 Upload a datasheet
• Y1 (145-0004789): 📤 Upload a datasheet
• X1, Y2 (145-0004792): 📤 Upload a datasheet
• P2 (158-0001269): 📤 Upload a datasheet
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• C28 (2232-0012): 📤 Upload a datasheet
• J5, J6, J7 (258-0002513): 📤 Upload a datasheet
• USB1 (258-0004503): 📤 Upload a datasheet
• J1 (258-0004612): 📤 Upload a datasheet
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• L8 (3120-0183): 📤 Upload a datasheet
• L18, L4 (3120-0266): 📤 Upload a datasheet
• CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17 (3142-0014): 📤 Upload a datasheet
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• SW1 (3770-0026): 📤 Upload a datasheet
• TH1, TH2, TH3, TH4 (3880-0004): 📤 Upload a datasheet
• U42 (4300-0071): 📤 Upload a datasheet
• U5, U6 (4327-0009): 📤 Upload a datasheet
• U19 (4327-0010): 📤 Upload a datasheet
• D10, D5 (4536-0009): 📤 Upload a datasheet
• D1, D2 (4560-0045): 📤 Upload a datasheet
• D13 (4620-0026): 📤 Upload a datasheet
• TP1, TP17, TP18, TP2 (999-0000003): 📤 Upload a datasheet
• SP1, SP2, SP3, SP4 (999-0000005): 📤 Upload a datasheet
• U3 (AD42): 📤 Upload a datasheet
• U38 (APL5912KAC-TRGS-X): 📤 Upload a datasheet
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• D11, D4, D6 (BAT54A-S): 📤 Upload a datasheet
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• U10, U14, U15, U16, U17 (NTS0104GU12): 📤 Upload a datasheet
• U29 (TPD4USB30): 📤 Upload a datasheet

_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 398 component(s) to review, and found 13 potential issue(s) in 16 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary><b>Component Details</b></summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AK12 | DDI0_RCOMP_P | DDI_RCOMP_N | ❌ | <details><summary>DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net, while pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ negative per datasheet) connects to DDI_RCOMP_P net. These connections should be reversed.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,31.55,45.57,39.05" aspect-ratio="1.29" } <ul><li>Pin AK12 is labeled DDI0_RCOMP_P in the component and datasheet, indicating the positive side of the DDI compensation resistor pair <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ in the component and datasheet, where the overline notation indicates this is the negative/complement signal (DDI0_RCOMP_N) <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>In the schematic, pin AK12 connects to net DDI_RCOMP_N <em>(from schematic)</em></li><li>In the schematic, pin AK13 connects to net DDI_RCOMP_P <em>(from schematic)</em></li><li>Resistor R217 (402 ohms) is connected between nets DDI_RCOMP_N and DDI_RCOMP_P, serving as the DDI compensation resistor <em>(from schematic)</em></li><li>The connections are reversed: the positive pin (AK12) connects to the negative net, and the negative pin (AK13) connects to the positive net <em>(reasoning)</em></li><li>To correct this error, the net connections should be swapped so that AK12 connects to DDI_RCOMP_P and AK13 connects to DDI_RCOMP_N <em>(reasoning)</em></li></ul></details> | | AK13 | ~DDI0_RCOMP | DDI_RCOMP_P | ❌ | <details><summary>DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net, while pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ negative per datasheet) connects to DDI_RCOMP_P net. These connections should be reversed.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,38.46" aspect-ratio="1.29" } <ul><li>Pin AK12 is labeled DDI0_RCOMP_P in the component and datasheet, indicating the positive side of the DDI compensation resistor pair <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ in the component and datasheet, where the overline notation indicates this is the negative/complement signal (DDI0_RCOMP_N) <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</em></li><li>In the schematic, pin AK12 connects to net DDI_RCOMP_N <em>(from schematic)</em></li><li>In the schematic, pin AK13 connects to net DDI_RCOMP_P <em>(from schematic)</em></li><li>Resistor R217 (402 ohms) is connected between nets DDI_RCOMP_N and DDI_RCOMP_P, serving as the DDI compensation resistor <em>(from schematic)</em></li><li>The connections are reversed: the positive pin (AK12) connects to the negative net, and the negative pin (AK13) connects to the positive net <em>(reasoning)</em></li><li>To correct this error, the net connections should be swapped so that AK12 connects to DDI_RCOMP_P and AK13 connects to DDI_RCOMP_N <em>(reasoning)</em></li></ul></details> | | A29 | RESERVED_A29 | GPIO_NC13 | ✅ | RESERVED_A29 pin is connected to GPIO_NC13 net with a 10K pull-down resistor (R102) to ground. This is an acceptable configuration for an unused reserved GPIO pin. | | B26 | DDI0_BKLTCTL | | ✅ | DDI0_BKLTCTL backlight control is unconnected, which may be acceptable if backlight control is handled externally. | | B28 | DDI0_VDDEN | | ✅ | DDI0_VDDEN display power enable is unconnected, which may be acceptable if display power is controlled externally. | | B30 | GPIO_S0_NC12 | $3N566 | ✅ | GPIO_S0_NC12 is connected to test point TP15, which is acceptable for debug access. | | C26 | DDI0_DDCDATA | HDMI_DDCDAT | ✅ | DDI0_DDCDATA is correctly connected to HDMI_DDCDAT for HDMI DDC communication. | | C27 | DDI0_BKLTEN | | ✅ | DDI0_BKLTEN backlight enable is unconnected, which is acceptable for HDMI displays. | | C28 | DDI0_DDCCLK | HDMI_DDCCLK | ✅ | DDI0_DDCCLK is correctly connected to HDMI_DDCCLK for HDMI DDC communication. | | D27 | DDI0_HPD | HDMI_HPD_B | ✅ | DDI0_HPD is correctly connected to HDMI_HPD_B through inverter U39 for hot plug detection. | | G30 | DDI1_DDCCLK | GND | ✅ | DDI1_DDCCLK is intentionally grounded to disable the DDI1 port per the 'Bay Trail-M Remove eDP Port' note. | | J30 | DDI1_BKLTEN | | ✅ | DDI1_BKLTEN backlight enable is unconnected, consistent with DDI1 port being disabled. | | K30 | DDI1_HPD | GND | ✅ | DDI1_HPD is intentionally grounded to disable the DDI1 port per the 'Bay Trail-M Remove eDP Port' note. | | M30 | DDI1_BKLTCTL | | ✅ | DDI1_BKLTCTL backlight control is unconnected, consistent with DDI1 port being disabled. | | N30 | DDI1_VDDEN | | ✅ | DDI1_VDDEN display power enable is unconnected, consistent with DDI1 port being disabled. | | P14 | RESERVED_P14 | MCSI_RCOMP | ✅ | RESERVED_P14 is connected to MCSI_RCOMP with 150-ohm compensation resistor R213 for MIPI CSI interface. | | P30 | DDI1_DDCDATA | DDI1_DDCDAT | ✅ | DDI1_DDCDATA is connected with 2.2K pull-down resistor R257, consistent with disabling the DDI1 port. | | BA1 | VGA_GREEN | | ✅ | VGA_GREEN DAC output is unconnected, which is acceptable if VGA output is not used. | | BA3 | VGA_RED | | ✅ | VGA_RED DAC output is unconnected, which is acceptable if VGA output is not used. | | AB12 | RESERVED_AB12 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AB13 | RESERVED_AB13 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AB14 | RESERVED_AB14 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AB2 | RESERVED_AB2 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AB3 | RESERVED_AB3 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AB7 | RESERVED_AB7 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AB9 | RESERVED_AB9 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AD4 | RESERVED_AD4 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AD6 | RESERVED_AD6 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AF13 | RESERVED_AF13 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AF14 | RESERVED_AF14 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AH13 | RESERVED_AH13 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AH14 | RESERVED_AH14 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AM13 | RESERVED_AM13 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AM14 | RESERVED_AM14 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | C29 | RESERVED_C29 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | C30 | RESERVED_C30 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | D28 | RESERVED_D28 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | D32 | RESERVED_D32 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | D34 | RESERVED_D34 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | F28 | RESERVED_F28 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | F32 | RESERVED_F32 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | F34 | RESERVED_F34 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | J28 | RESERVED_J28 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | J34 | RESERVED_J34 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | K28 | RESERVED_K28 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | K34 | RESERVED_K34 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | M32 | RESERVED_M32 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | N32 | RESERVED_N32 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | R1 | RESERVED_R1 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | R3 | RESERVED_R3 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T10 | RESERVED_T10 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T12 | RESERVED_T12 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T13 | RESERVED_T13 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T14 | RESERVED_T14 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T2 | RESERVED_T2 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T3 | RESERVED_T3 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T4 | RESERVED_T4 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T6 | RESERVED_T6 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T7 | RESERVED_T7 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | T9 | RESERVED_T9 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V10 | RESERVED_V10 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V13 | RESERVED_V13 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V14 | RESERVED_V14 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V2 | RESERVED_V2 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V3 | RESERVED_V3 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V4 | RESERVED_V4 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V6 | RESERVED_V6 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | V9 | RESERVED_V9 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | W1 | RESERVED_W1 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | W3 | RESERVED_W3 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | Y12 | RESERVED_Y12 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | Y13 | RESERVED_Y13 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | Y2 | RESERVED_Y2 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | Y3 | RESERVED_Y3 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | Y4 | RESERVED_Y4 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | Y6 | RESERVED_Y6 | | ✅ | Reserved pins and display interface pins (DDI0, DDI1, VGA). Reserved pins are appropriately left unconnected. Display interface pins are connected to their respective interfaces: DDI0 to HDMI, VGA analog outputs and sync signals to VGA interface, and DDI1 transmit pins left unconnected as DDI1 is not used. | | AC1 | DDI1_TXN_3 | | ✅ | DDI1_TXN_3 transmit lane 3 negative is unconnected, consistent with DDI1 port being disabled. | | AC3 | DDI1_TXP_3 | | ✅ | DDI1_TXP_3 transmit lane 3 positive is unconnected, consistent with DDI1 port being disabled. | | BC1 | VGA_DDCCLK | CRT_CLK | ✅ | VGA_DDCCLK is correctly connected to CRT_CLK with 150-ohm termination resistor R39. | | AD2 | DDI1_TXN_2 | | ✅ | DDI1_TXN_2 transmit lane 2 negative is unconnected, consistent with DDI1 port being disabled. | | BC2 | VGA_DDCDATA | CRT_DAT | ✅ | VGA_DDCDATA is correctly connected to CRT_DAT with 150-ohm termination resistor R38. | | AD3 | DDI1_TXP_2 | | ✅ | DDI1_TXP_2 transmit lane 2 positive is unconnected, consistent with DDI1 port being disabled. | | BD2 | VGA_HSYNC | | ✅ | VGA_HSYNC horizontal sync is unconnected, which is acceptable if VGA output is not used. | | AF2 | DDI1_TXN_1 | | ✅ | DDI1_TXN_1 transmit lane 1 negative is unconnected, consistent with DDI1 port being disabled. | | AF3 | DDI1_TXP_1 | | ✅ | DDI1_TXP_1 transmit lane 1 positive is unconnected, consistent with DDI1 port being disabled. | | AG1 | DDI1_TXN_0 | | ✅ | DDI1_TXN_0 transmit lane 0 negative is unconnected, consistent with DDI1 port being disabled. | | BF2 | VGA_VSYNC | | ✅ | VGA_VSYNC vertical sync is unconnected, which is acceptable if VGA output is not used. | | AG3 | DDI1_TXP_0 | | ✅ | DDI1_TXP_0 transmit lane 0 positive is unconnected, consistent with DDI1 port being disabled. | | AH2 | RESERVED_VSS3 | $3N554 | ✅ | RESERVED_VSS3 pin is correctly connected to ground through 0-ohm resistor R43. | | AH3 | RESERVED_VSS2 | $3N552 | ✅ | RESERVED_VSS2 pin is correctly connected to ground through 0-ohm resistor R46. | | AK2 | DDI1_AUXN | | ✅ | DDI1_AUXN auxiliary channel negative is unconnected, consistent with DDI1 port being disabled. | | AK3 | DDI1_AUXP | | ✅ | DDI1_AUXP auxiliary channel positive is unconnected, consistent with DDI1 port being disabled. | | AL1 | DDI0_AUXN | | ✅ | DDI0_AUXN auxiliary channel negative is unconnected, which may be acceptable if DisplayPort AUX channel is not used. | | AL3 | DDI0_AUXP | | ✅ | DDI0_AUXP auxiliary channel positive is unconnected, which may be acceptable if DisplayPort AUX channel is not used. | | AM2 | RESERVED_VSS1 | $3N589 | ✅ | RESERVED_VSS1 pin is correctly connected to ground through 0-ohm resistor R41. | | AM3 | RESERVED_VSS0 | $3N579 | ✅ | RESERVED_VSS0 pin is correctly connected to ground through 0-ohm resistor R42. | | AP2 | DDI0_TXN_3 | HDMI_CLK_DN | ✅ | DDI0_TXN_3 is correctly connected to HDMI_CLK_DN for HDMI clock differential pair negative. | | AP3 | DDI0_TXP_3 | HDMI_CLK_DP | ✅ | DDI0_TXP_3 is correctly connected to HDMI_CLK_DP for HDMI clock differential pair positive. | | AR1 | DDI0_TXN_2 | HDMI_TX0_DN | ✅ | DDI0_TXN_2 is correctly connected to HDMI_TX0_DN for HDMI data lane 0 negative. | | AR3 | DDI0_TXP_2 | HDMI_TX0_DP | ✅ | DDI0_TXP_2 is correctly connected to HDMI_TX0_DP for HDMI data lane 0 positive. | | AT2 | DDI0_TXP_1 | HDMI_TX1_DP | ✅ | DDI0_TXP_1 is correctly connected to HDMI_TX1_DP for HDMI data lane 1 positive. | | AT3 | DDI0_TXN_1 | HDMI_TX1_DN | ✅ | DDI0_TXN_1 is correctly connected to HDMI_TX1_DN for HDMI data lane 1 negative. | | AV2 | DDI0_TXN_0 | HDMI_TX2_DN | ✅ | DDI0_TXN_0 is correctly connected to HDMI_TX2_DN for HDMI data lane 2 negative. | | AV3 | DDI0_TXP_0 | HDMI_TX2_DP | ✅ | DDI0_TXP_0 is correctly connected to HDMI_TX2_DP for HDMI data lane 2 positive. | | AW1 | VGA_IREF | $3N548 | ✅ | VGA_IREF is correctly connected to 357-ohm reference resistor R40 to set VGA DAC output current. | | AY2 | VGA_BLUE | | ✅ | VGA_BLUE DAC output is unconnected, which is acceptable if VGA output is not used. | | AY3 | VGA_IRTN | GND | ✅ | VGA_IRTN is correctly connected to ground as the DAC return current path. | </details> <details> <summary><b>U39</b> - SN74LVC1G14DCKR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf?ts=1753365169590&ref_url=https%25253A%25252F%25252Fwww.ti.com%25252Fproduct%25252FSN74LVC1G14) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/SN74LVC1G14DCKR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin is not connected in schematic. Datasheet states it should be soldered to the board but can be left electrically unconnected. | | 2 | A | HDMI_HPD | ✅ | Input pin A is connected to HDMI_HPD signal from HDMI connector. This is correct for buffering the hot plug detect signal. | | 3 | GND | GND | ✅ | GND pin is correctly connected to ground plane. | | 4 | Y | HDMI_HPD_B | ✅ | Output pin Y is connected to HDMI_HPD_B which goes to CPU1 DDI0_HPD pin. This provides an inverted and buffered HPD signal to the processor. | | 5 | VCC | +V1P8S | ✅ | VCC pin is connected to +V1P8S (1.8V) supply with nearby bypass capacitor C375 (0.1µF). This is correct per datasheet recommendations. | </details> <details> <summary><b>R40</b> - 357R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004695) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N548 | ✅ | 357-ohm resistor connected between CPU1 VGA_IREF pin and ground to set the VGA DAC reference current. | | 2 | 2 | GND | ✅ | 357-ohm resistor connected between CPU1 VGA_IREF pin and ground to set the VGA DAC reference current. | </details> <details> <summary><b>R217</b> - 402R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI_RCOMP_N | ✅ | 402-ohm resistor correctly connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming the compensation resistor network for the display interface. The resistor itself is properly placed between the RCOMP differential pair. Note that there is an upstream issue at CPU1 pins AK12 and AK13 where the net connections are swapped, but since R217 is a symmetric passive component, this does not affect its electrical function. | | 2 | 2 | DDI_RCOMP_P | ✅ | 402-ohm resistor correctly connected between DDI_RCOMP_N and DDI_RCOMP_P nets, forming the compensation resistor network for the display interface. The resistor itself is properly placed between the RCOMP differential pair. Note that there is an upstream issue at CPU1 pins AK12 and AK13 where the net connections are swapped, but since R217 is a symmetric passive component, this does not affect its electrical function. | </details> <details> <summary><b>R213</b> - 150R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCSI_RCOMP | ✅ | 150-ohm resistor connected between MCSI_RCOMP net and ground. This provides impedance compensation for the MIPI CSI camera interface on CPU1 pin P14. | | 2 | 2 | GND | ✅ | 150-ohm resistor connected between MCSI_RCOMP net and ground. This provides impedance compensation for the MIPI CSI camera interface on CPU1 pin P14. | </details> <details> <summary><b>R257</b> - 2K20 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI1_DDCDAT | ✅ | Resistor pin 1 is connected to DDI1_DDCDAT, providing pull-down for the disabled DDI1 port. | | 2 | 2 | GND | ✅ | Resistor pin 2 is correctly connected to ground to complete the pull-down function. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C24 | ~PROCHOT | VR_HOT_L | ✅ | Processor hot signal, correctly pulled up with 73.2 ohm resistor. | | N34 | RESERVED_N34 | | ✅ | Reserved pin, correctly left unconnected. | | P34 | RESERVED_P34 | | ✅ | Reserved pin, correctly left unconnected. | | BA12 | SATA_GP0 | SATA_GP0 | ✅ | SATA general purpose signal 0, correctly pulled down with 10K resistor. | | BA16 | SATA_RXN_1 | SATA1_RXN | ✅ | SATA port 1 receive negative signal, correctly AC coupled to mSATA interface. | | BA18 | SD2_CLK | | ✅ | SD2 clock signal, left unconnected as SD2 interface is unused. | | BA20 | SD2_D2 | | ✅ | SD2 data bit 2 signal, left unconnected as SD2 interface is unused. | | BA24 | ~MMC1_RST | | ✅ | MMC1 reset signal, left unconnected as MMC1 interface is unused. | | BA26 | SD3_D3 | SD3_D3 | ✅ | SD3 data bit 3 signal, correctly connected to SD card interface. | | BA30 | LPE_I2S2_FRM | LPE_I2S_FRM | ✅ | I2S frame sync signal, correctly connected with DNI pull-up resistor. | | BB3 | RESERVED_BB3 | | ✅ | Reserved pin, correctly left unconnected. | | BB4 | RESERVED_BB4 | | ✅ | Reserved pin, correctly left unconnected. | | BB5 | RESERVED_VSS6 | RESERVED_VSS6 | ✅ | Reserved VSS pin, correctly connected to ground through 0 ohm resistor. | | BB7 | RESERVED_VSS7 | RESERVED_VSS7 | ✅ | Reserved VSS pin, correctly connected to ground through 0 ohm resistor. | | BB10 | RESERVED_VSS4 | ICLK_SATA_TERMP | ✅ | Reserved VSS pin used for SATA termination, correctly connected to ground through 0 ohm resistor. | | BC10 | RESERVED_VSS5 | ICLK_SATA_TERMN | ✅ | Reserved VSS pin used for SATA termination, correctly connected to ground through 0 ohm resistor. | | BC18 | SD2_CMD | | ✅ | SD2 command signal, left unconnected as SD2 interface is unused. | | BC24 | SD3_CD# | SD3_CD# | ✅ | SD3 card detect and write protect pins are tied together via 0 ohm resistor. This is unusual and may not work correctly with all SD cards, but may be intentional for Bay Trail-I variant. | | BD5 | SD3_WP_BD5 | SD3_WP | ✅ | SD3 card detect and write protect pins are tied together via 0 ohm resistor. This is unusual and may not work correctly with all SD cards, but may be intentional for Bay Trail-I variant. | | BC30 | LPE_I2S2_DATAOUT | LPE_I2S_DATOUT | ✅ | I2S data output signal, correctly connected with DNI pull-down and series resistor. | | BD7 | ~PCIE_CLKREQ_1 | CLKREQ1_B | ✅ | PCIe clock request 1 signal, correctly pulled up with 10K resistor. | | BD10 | SATA_TXP1 | SATA1_TXP | ✅ | SATA port 1 transmit positive signal, correctly AC coupled to mSATA interface. | | BD18 | ~SD2_D3_CD | | ✅ | SD2 data bit 3 / card detect signal, left unconnected as SD2 interface is unused. | | BD20 | SD2_D1 | | ✅ | SD2 data bit 1 signal, left unconnected as SD2 interface is unused. | | BD22 | ~SD3_PWREN | /SD3+PWREN | ✅ | SD3 power enable signal, correctly connected with test point. | | BD26 | SD3_D1 | SD3_D1 | ✅ | SD3 data bit 1 signal, correctly connected to SD card interface. | | BD28 | LPE_I2S2_DATAIN | LPE_I2S_DATIN | ✅ | I2S data input signal, correctly connected to I2S audio interface. | | BE3 | ~PCIE_CLKREQ_3 | mPCIe_CLKREQ3_B | ✅ | PCIe clock request 3 signal, correctly pulled up with 10K resistor. | | BF6 | SATA_TXP_0 | SATA0_TXP | ✅ | SATA port 0 transmit positive signal, correctly AC coupled to SATA connector. | | BF10 | SATA_TXN_1 | SATA1_TXN | ✅ | SATA port 1 transmit negative signal, correctly AC coupled to mSATA interface. | | BF20 | HDA_LPE_RCOMP | HDA_RCOMP | ✅ | HD Audio / Low Power Engine compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | BF22 | SD3_1P8EN | SD3_1P8EN | ✅ | SD3 1.8V enable signal, correctly connected with test point. | | BF26 | SD3_RCOMP | SD3_RCOMP | ✅ | SD3 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | BF28 | LPE_I2S2_CLK | LPE_I2S_CLK | ✅ | I2S clock signal, correctly connected to I2S audio interface. | | BG3 | ~PCIE_CLKREQ_0 | CLKREQ0_B | ✅ | PCIe clock request 0 signal, correctly pulled up with 10K resistor. | | BG5 | ~PCIE_CLKREQ_2 | LAN_CLKREQ2_B | ✅ | PCIe clock request 2 signal, correctly pulled up with 10K resistor. | | BG7 | SATA_TXN_0 | SATA0_TXN | ✅ | SATA port 0 transmit negative signal, correctly AC coupled to SATA connector. | | BG18 | GPIO_S0_SC_15 | | ✅ | GPIO pin, left unconnected as this GPIO is unused. | | BG19 | HDA_SDI0 | | ✅ | HD Audio serial data in 0 signal, left unconnected as HD Audio interface is unused. | | BG20 | HDA_SDO | | ✅ | HD Audio serial data out signal, left unconnected as HD Audio interface is unused. | | BG21 | HDA_SDI1 | | ✅ | HD Audio serial data in 1 signal, left unconnected as HD Audio interface is unused. | | BG22 | ~HDA_RST | | ✅ | HD Audio reset signal, left unconnected as HD Audio interface is unused. | | BH18 | GPIO_S0_SC_14 | | ✅ | GPIO pin, left unconnected as this GPIO is unused. | | BH20 | HDA_SYNC | | ✅ | HD Audio sync signal, left unconnected as HD Audio interface is unused. | | AK7 | RESERVED_AK7 | | ✅ | Reserved pin, correctly left unconnected. | | AK9 | RESERVED_AK9 | | ✅ | Reserved pin, correctly left unconnected. | | BJ21 | HDA_CLK | | ✅ | HD Audio clock signal, left unconnected as HD Audio interface is unused. | | AP4 | PCIE_TXN_3 | mPCIE_TX_N | ✅ | PCIe lane 3 transmit negative signal, connected to mPCIe slot. | | AP6 | PCIE_TXP_3 | mPCIE_TX_P | ✅ | PCIe lane 3 transmit positive signal, connected to mPCIe slot. | | AP7 | PCIE_RXN_3 | mPCIE_RX_N | ✅ | PCIe lane 3 receive negative signal, connected to mPCIe slot. | | AP9 | PCIE_RXP_3 | mPCIE_RX_P | ✅ | PCIe lane 3 receive positive signal, connected to mPCIe slot. | | AP10 | PCIE_RXN_2 | PCIE_RXN2 | ✅ | PCIe lane 2 receive negative signal, connected to LAN controller. | | AP12 | PCIE_RXP_2 | PCIE_RXP2 | ✅ | PCIe lane 2 receive positive signal, connected to LAN controller. | | AP13 | PCIE_RCOMP_N_AP13_AP13 | PCIE_RCOMP_N | ✅ | PCIe compensation resistor negative pin, correctly connected with 402 ohm resistor to PCIE_RCOMP_P. | | AP14 | PCIE_RCOMP_P_AP14_AP14 | PCIE_RCOMP_P | ✅ | PCIe compensation resistor positive pin, correctly connected with 402 ohm resistor to PCIE_RCOMP_N. | | AT6 | PCIE_TXN_2 | PCIE_TXN2 | ✅ | PCIe lane 2 transmit negative signal, connected to LAN controller. | | AT7 | PCIE_TXP_2 | PCIE_TXP2 | ✅ | PCIe lane 2 transmit positive signal, connected to LAN controller. | | AT9 | PCIE_RXN_1 | | ✅ | PCIe lane 1 receive negative signal, left unconnected as PCIe port 1 is unused. | | AT10 | PCIE_RXP_1 | | ✅ | PCIe lane 1 receive positive signal, left unconnected as PCIe port 1 is unused. | | AT13 | PCIE_RXN_0 | | ✅ | PCIe lane 0 receive negative signal, left unconnected as PCIe port 0 is unused. | | AT14 | PCIE_RXP_0 | | ✅ | PCIe lane 0 receive positive signal, left unconnected as PCIe port 0 is unused. | | AT18 | SATA_RCOMP_N_AT18 | SATA_RCOMP_N | ✅ | SATA compensation resistor negative pin, correctly connected with 402 ohm resistor to SATA_RCOMP_P. | | AT20 | MMC1_D3 | | ✅ | MMC1 data bit 3 signal, left unconnected as MMC1 interface is unused. | | AT22 | MMC1_CLK | | ✅ | MMC1 clock signal, left unconnected as MMC1 interface is unused. | | AT26 | MMC1_D6 | | ✅ | MMC1 data bit 6 signal, left unconnected as MMC1 interface is unused. | | AT28 | SD3_D0 | SD3_D0 | ✅ | SD3 data bit 0 signal, correctly connected to SD card interface. | | AU16 | SATA_RXP_0 | SATA0_RXP | ✅ | SATA port 0 receive positive signal, correctly AC coupled to SATA connector. | | AU18 | SATA_RCOMP_P_AU18 | SATA_RCOMP_P | ✅ | SATA compensation resistor positive pin, correctly connected with 402 ohm resistor to SATA_RCOMP_N. | | AU20 | MMC1_D7 | | ✅ | MMC1 data bit 7 signal, left unconnected as MMC1 interface is unused. | | AU22 | MMC1_D1 | | ✅ | MMC1 data bit 1 signal, left unconnected as MMC1 interface is unused. | | AU26 | MMC1_D5 | | ✅ | MMC1 data bit 5 signal, left unconnected as MMC1 interface is unused. | | AU28 | SD3_D2 | SD3_D2 | ✅ | SD3 data bit 2 signal, correctly connected to SD card interface. | | AV4 | PCIE_TXN_1 | | ✅ | PCIe lane 1 transmit negative signal, left unconnected as PCIe port 1 is unused. | | AV6 | PCIE_TXP_1 | | ✅ | PCIe lane 1 transmit positive signal, left unconnected as PCIe port 1 is unused. | | AV9 | RESERVED_AV9 | | ✅ | Reserved pin, correctly left unconnected. | | AV10 | RESERVED_AV10 | | ✅ | Reserved pin, correctly left unconnected. | | AV16 | SATA_RXN_0 | SATA0_RXN | ✅ | SATA port 0 receive negative signal, correctly AC coupled to SATA connector. | | AV20 | MMC1_D0 | | ✅ | MMC1 data bit 0 signal, left unconnected as MMC1 interface is unused. | | AV22 | MMC1_D2 | | ✅ | MMC1 data bit 2 signal, left unconnected as MMC1 interface is unused. | | AV26 | MMC1_CMD | | ✅ | MMC1 command signal, left unconnected as MMC1 interface is unused. | | AV28 | SD3_CMD | SD3_CMD | ✅ | SD3 command signal, correctly connected to SD card interface. | | AY6 | PCIE_TXN_0 | | ✅ | PCIe lane 0 transmit negative signal, left unconnected as PCIe port 0 is unused. | | AY7 | PCIE_TXP_0 | | ✅ | PCIe lane 0 transmit positive signal, left unconnected as PCIe port 0 is unused. | | AY12 | ~SATA_LED | SATA_LED_B | ✅ | SATA LED signal, correctly connected through series resistor to LED control circuit. | | AY14 | SATA_GP1 | SATA_GP1 | ✅ | SATA general purpose signal 1, correctly pulled down with 10K resistor. | | AY16 | SATA_RXP_1 | SATA1_RXP | ✅ | SATA port 1 receive positive signal, correctly AC coupled to mSATA interface. | | AY18 | MMC1_RCOMP | MMC1_RCOMP | ✅ | MMC1 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | AY20 | SD2_D0 | | ✅ | SD2 data bit 0 signal, left unconnected as SD2 interface is unused. | | AY24 | MMC1_D4 | | ✅ | MMC1 data bit 4 signal, left unconnected as MMC1 interface is unused. | | AY26 | SD3_CLK | SD3_CLK | ✅ | SD3 clock signal, correctly connected to SD card interface. | </details> <details> <summary><b>J3</b> - HDR_7POS_SER_GOLD_SATA_R/A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-67490-001.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0003610) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net for signal return path. | | 2 | 2 | SATA0_TXP_C | ✅ | SATA TX positive signal correctly routed from CPU through AC coupling capacitor C10 to connector. | | 3 | 3 | SATA0_TXN_C | ✅ | SATA TX negative signal correctly routed from CPU through AC coupling capacitor C11 to connector. | | 4 | 4 | GND | ✅ | Ground pin correctly connected to GND net, positioned between TX and RX differential pairs for isolation. | | 5 | 5 | SATA0_RXN_C | ✅ | SATA RX negative signal correctly routed from connector through AC coupling capacitor C12 to CPU. | | 6 | 6 | SATA0_RXP_C | ✅ | SATA RX positive signal correctly routed from connector through AC coupling capacitor C13 to CPU. | | 7 | 7 | GND | ✅ | Ground pin correctly connected to GND net for signal return path. | | MH1 | | | ✅ | Mounting holes correctly connected to GND_EARTH for chassis ground and EMI shielding. | | MH2 | | | ✅ | Mounting holes correctly connected to GND_EARTH for chassis ground and EMI shielding. | </details> <details> <summary><b>C10</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXP_C | ✅ | Connector side of AC coupling capacitor for SATA TX positive signal. | | 2 | 2 | SATA0_TXP | ✅ | CPU side of AC coupling capacitor for SATA TX positive signal. | </details> <details> <summary><b>C11</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXN_C | ✅ | Connector side of AC coupling capacitor for SATA TX negative signal. | | 2 | 2 | SATA0_TXN | ✅ | CPU side of AC coupling capacitor for SATA TX negative signal. | </details> <details> <summary><b>C12</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXN_C | ✅ | Connector side of AC coupling capacitor for SATA RX negative signal. | | 2 | 2 | SATA0_RXN | ✅ | CPU side of AC coupling capacitor for SATA RX negative signal. | </details> <details> <summary><b>C13</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXP_C | ✅ | Connector side of AC coupling capacitor for SATA RX positive signal. | | 2 | 2 | SATA0_RXP | ✅ | CPU side of AC coupling capacitor for SATA RX positive signal. | </details> <details> <summary><b>C148</b> - 8200pF 10% 1KV 1808 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0004408) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND_EARTH | ✅ | Chassis ground side of safety capacitor for EMI filtering, marked DNI for optional population. | | 2 | 2 | GND | ✅ | Signal ground side of safety capacitor for EMI filtering, marked DNI for optional population. | </details> <details> <summary><b>C180</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_N | ✅ | Connected to mSATA_TX_N net, which carries the negative differential signal to the mSATA device receiver. This pin delivers the AC-coupled signal from the CPU transmitter. | | 2 | 2 | SATA1_TXN | ✅ | Connected to SATA1_TXN net, which connects to CPU1 pin BF10 (SATA_TXN_1). This pin receives the negative differential signal from the CPU's SATA1 transmitter. | </details> <details> <summary><b>C177</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_N | ✅ | Connected to mSATA_RX_N net, which carries the negative differential signal from the mSATA device transmitter. This pin provides AC coupling for the incoming SATA signal. | | 2 | 2 | SATA1_RXN | ✅ | Connected to SATA1_RXN net, which connects to CPU1 pin BA16 (SATA_RXN_1). This pin couples the AC-coupled signal to the CPU's SATA1 receiver. | </details> <details> <summary><b>C178</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_P | ✅ | Connected to mSATA_RX_P net, which carries the positive differential signal from the mSATA device transmitter. This pin provides AC coupling for the incoming SATA signal. | | 2 | 2 | SATA1_RXP | ✅ | Connected to SATA1_RXP net, which connects to CPU1 pin AY16 (SATA_RXP_1). This pin couples the AC-coupled signal to the CPU's SATA1 receiver. | </details> <details> <summary><b>C179</b> - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_P | ✅ | Connected to mSATA_TX_P net, which carries the positive differential signal to the mSATA device receiver. This pin delivers the AC-coupled signal from the CPU transmitter. | | 2 | 2 | SATA1_TXP | ✅ | Connected to SATA1_TXP net, which connects to CPU1 pin BD10 (SATA_TXP1). This pin receives the positive differential signal from the CPU's SATA1 transmitter. | </details> <details> <summary><b>R73</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0 ohm resistor connecting CPU1 reserved pin BB10 (RESERVED_VSS4/ICLK_SATA_TERMP) to ground. This grounds a reserved VSS pin as required. | | 2 | 2 | ICLK_SATA_TERMP | ✅ | 0 ohm resistor connecting CPU1 reserved pin BB10 (RESERVED_VSS4/ICLK_SATA_TERMP) to ground. This grounds a reserved VSS pin as required. | </details> <details> <summary><b>R239</b> - 402 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_RCOMP_N | ✅ | 402 ohm compensation resistor connected between SATA_RCOMP_P and SATA_RCOMP_N pins of the CPU. This provides impedance compensation for the SATA interface. | | 2 | 2 | SATA_RCOMP_P | ✅ | 402 ohm compensation resistor connected between SATA_RCOMP_P and SATA_RCOMP_N pins of the CPU. This provides impedance compensation for the SATA interface. | </details> <details> <summary><b>R74</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0 ohm resistor connecting CPU1 reserved pin BC10 (RESERVED_VSS5/ICLK_SATA_TERMN) to ground. This grounds a reserved VSS pin as required. | | 2 | 2 | ICLK_SATA_TERMN | ✅ | 0 ohm resistor connecting CPU1 reserved pin BC10 (RESERVED_VSS5/ICLK_SATA_TERMN) to ground. This grounds a reserved VSS pin as required. | </details> <details> <summary><b>R191</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ0_B | ✅ | This 10K resistor provides a pull-up from CLKREQ0_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | | 2 | 2 | +V1P8S | ✅ | This 10K resistor provides a pull-up from CLKREQ0_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | </details> <details> <summary><b>R218</b> - 402 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PCIE_RCOMP_P | ✅ | This 402 ohm resistor connects between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on the Intel Atom E3825 SOC. | | 2 | 2 | PCIE_RCOMP_N | ✅ | This 402 ohm resistor connects between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on the Intel Atom E3825 SOC. | </details> <details> <summary><b>R2</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mPCIe_CLKREQ3_B | ✅ | This 10K resistor provides a pull-up from mPCIe_CLKREQ3_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | | 2 | 2 | +V1P8S | ✅ | This 10K resistor provides a pull-up from mPCIe_CLKREQ3_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | </details> <details> <summary><b>R190</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ1_B | ✅ | This 10K resistor provides a pull-up from CLKREQ1_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | | 2 | 2 | +V1P8S | ✅ | This 10K resistor provides a pull-up from CLKREQ1_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | </details> <details> <summary><b>R71</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_CLKREQ2_B | ✅ | This 10K resistor provides a pull-up from LAN_CLKREQ2_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | | 2 | 2 | +V1P8S | ✅ | This 10K resistor provides a pull-up from LAN_CLKREQ2_B to +V1P8S, which is appropriate for the active-low CLKREQ signal. | </details> <details> <summary><b>R354</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SD3_WP | ✅ | This 0-ohm resistor connects SD3_WP (Write Protect) to SD3_CD# (Card Detect). While this is an unusual configuration in standard SD card interfaces, a schematic text note indicates Bay Trail-I has different behavior for pin BD5, suggesting this connection is intentional for this specific processor. | | 2 | 2 | SD3_CD# | ✅ | This 0-ohm resistor connects SD3_WP (Write Protect) to SD3_CD# (Card Detect). While this is an unusual configuration in standard SD card interfaces, a schematic text note indicates Bay Trail-I has different behavior for pin BD5, suggesting this connection is intentional for this specific processor. | </details> <details> <summary><b>R258</b> - 49.9 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | This 49.9 ohm resistor connects SD3_RCOMP to ground, which is a standard configuration for SD interface impedance compensation. | | 2 | 2 | SD3_RCOMP | ✅ | This 49.9 ohm resistor connects SD3_RCOMP to ground, which is a standard configuration for SD interface impedance compensation. | </details> <details> <summary><b>R242</b> - 49.9 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDA_RCOMP | ✅ | Connected to HDA_RCOMP pin (BF20) of the Intel Atom E3825 SOC. This provides impedance compensation for the High Definition Audio interface. | | 2 | 2 | GND | ✅ | Connected to GND. This completes the compensation resistor circuit by providing the ground reference. | </details> <details> <summary><b>R240</b> - 49.9 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the MMC1 RCOMP impedance calibration resistor. | | 2 | 2 | MMC1_RCOMP | ✅ | Connected to MMC1_RCOMP (CPU1 pin AY18), providing impedance calibration reference for the MMC1 interface. | </details> <details> <summary><b>R234</b> - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP3 | ✅ | 1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0. | | 2 | 2 | GND | ✅ | 1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0. | </details> <details> <summary><b>R208</b> - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP2 | ✅ | 1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0. | | 2 | 2 | GND | ✅ | 1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0. | </details> <details> <summary><b>R211</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1. | | 2 | 2 | BOM_OP1 | ✅ | 10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1. | </details> <details> <summary><b>R400</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1. | | 2 | 2 | BOM_OP4 | ✅ | 10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1. | </details> <details> <summary><b>R259</b> - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_10_UNLOCK | ✅ | Connected to GPIO_S5_10_UNLOCK signal. This pin forms one end of a series resistor connecting a GPIO signal to the I2S data output. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | Connected to LPE_I2S_DATOUT, which is the I2S data output from CPU1 pin BC30. The 1K series resistor provides isolation between the GPIO and I2S signals. | </details> <details> <summary><b>R268</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_FRM | ✅ | Connected to LPE_I2S_FRM, the I2S frame sync signal from CPU1 pin BA30. This pin forms the pullup connection to ensure the frame sync signal has a defined high state. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail. This provides a 10K pullup on the I2S frame sync signal, which is standard practice for I2S interfaces. | </details> <details> <summary><b>J6</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pin 1 connects to +V1P8S power rail, providing 1.8V supply for optional pull-up configuration of SATA LED circuit. | | 2 | 2 | SATA_LED_R | ✅ | Pin 2 connects to SATA_LED_R net, which connects through R179 to the CPU SATA LED output signal. | </details> <details> <summary><b>R179</b> - 220 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001960) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_LED_B | ✅ | Pin 1 connects to SATA_LED_B net from CPU1 pin AY12, which is the active-low SATA LED output signal. | | 2 | 2 | SATA_LED_R | ✅ | Pin 2 connects to SATA_LED_R net, which can be pulled up to +V1P8S through jumper J6. | </details> <details> <summary><b>R72</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS6 | ✅ | Pin 1 is connected to GND, providing a ground connection for the ICLK_SATA_TERMP net through this 0-ohm resistor. | | 2 | 2 | GND | ✅ | Pin 2 is connected to ICLK_SATA_TERMP, which connects to CPU1 pin BB10 (RESERVED_VSS4). This grounds a reserved VSS pin on the processor. | </details> <details> <summary><b>R192</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS7 | ✅ | Pin 1 is connected to RESERVED_VSS7, which connects to CPU1 pin BB7. This is one side of a 0-ohm resistor used to ground a reserved VSS pin. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, providing the ground connection for the RESERVED_VSS7 net through this 0-ohm resistor. | </details> <details> <summary><b>R255</b> - 73.2 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004474) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR_HOT_L | ✅ | Connected to VR_HOT_L net, which connects to CPU1 pin C24 (P̅R̅O̅C̅H̅O̅T̅). This is the processor hot signal from the Intel Atom E3825 SOC. | | 2 | 2 | +V1P0S | ✅ | Connected to +V1P0S (1.0V supply rail), providing pull-up voltage for the PROCHOT signal. The 73.2 ohm value is lower than typical PROCHOT pull-ups but may be specified by Intel for this processor. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A9 | ILB_RTC_X2 | BRTCX2 | ✅ | ILB_RTC_X2 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor. | | A13 | GPIO_S5_9 | SOC_USB_HOST_EN1 | ✅ | GPIO_S5[09] is correctly connected to SOC_USB_HOST_EN1 for USB host enable control. | | A17 | GPIO_S5_3 | mPCIE_WAKEB | ✅ | GPIO_S5[03] is correctly connected to mPCIE_WAKEB with optional pull-up resistor for PCIe wake signaling. | | A21 | PCU_SPI_MOSI | SOC_SPI_MOSI | ✅ | PCU_SPI_MOSI is correctly connected to SPI flash with series 0-ohm resistor for signal routing. | | A25 | SVID_DATA | SVID_DATA | ✅ | SVID_DATA is correctly connected with series resistor for voltage regulator communication. | | B7 | PMC_CORE_PWROK | PMC_CORE_PWROK | ✅ | PMC_CORE_PWROK is correctly connected with series resistor to system power good signal. | | B8 | ILB_RTC_EXTPAD | BVCCRTC_EXTPAD | ✅ | ILB_RTC_EXTPAD is correctly connected to RTC power with decoupling capacitor. | | B10 | ~PMC_RSMRST | PMC_RSMRST | ✅ | PMC_RSMRST is correctly connected with pull-up, pull-down, and RC filtering, but the RC time constant may not meet the >10us requirement noted on the schematic. | | B14 | GPIO_S5_6 | BOM_OP2 | ✅ | GPIO_S5[06] is correctly connected to BOM_OP2 signal. | | B16 | GPIO_S5_1 | SOC_GPIO_S5_1 | ✅ | GPIO_S5[01] is correctly connected to SOC_GPIO_S5_1 signal. | | B18 | GPIO_S5_0 | SOC_GPIO_S5_0 | ✅ | GPIO_S5[00] is correctly connected to SOC_GPIO_S5_0 signal. | | B22 | PCU_SPI_MISO | SOC_SPI_MISO | ✅ | PCU_SPI_MISO is correctly connected to SPI flash with series 0-ohm resistor for signal routing. | | B24 | ~SVID_ALERT | SVID_ALERT | ✅ | SVID_ALERT is correctly connected with series resistor and pull-up for voltage regulator alert signaling. | | C9 | ILB_RTC_X1 | BRTCX1 | ✅ | ILB_RTC_X1 is correctly connected to the 32.768 kHz RTC crystal with appropriate load capacitor and feedback resistor. | | C11 | ~ILB_RTC_TEST | ILB_RTC_TESTB | ✅ | ILB_RTC_TEST is correctly left unconnected as it is a test pin. | | C12 | ~ILB_RTC_RST | RTCRST_L | ✅ | ILB_RTC_RST is correctly connected with pull-up resistor and decoupling capacitor for RTC reset. | | C13 | GPIO_S5_8 | SOC_USB_HOST_EN0 | ✅ | GPIO_S5[08] is correctly connected to SOC_USB_HOST_EN0 for USB host enable control. | | C15 | GPIO_S5_7 | BOM_OP3 | ✅ | GPIO_S5[07] is correctly connected to BOM_OP3 signal. | | C16 | GPIO_S5_5 | BOM_OP1 | ✅ | GPIO_S5[05] is correctly connected to BOM_OP1 signal. | | C17 | GPIO_S5_4 | BOM_OP4 | ✅ | GPIO_S5[04] is correctly connected to BOM_OP4 signal. | | C18 | GPIO_S5_2 | SOC_GPIO_S5_2 | ✅ | GPIO_S5[02] is correctly connected to SOC_GPIO_S5_2 signal. | | C19 | GPIO_S5_10 | GPIO_S5_10_UNLOCK | ✅ | GPIO_S5[10] is correctly connected to GPIO_S5_10_UNLOCK signal. | | C21 | ~PCU_SPI_CS_11 | SOC_SPI_CS1B | ✅ | PCU_SPI_CS_11 is connected through DNI resistor, indicating secondary SPI chip select is not used. | | C22 | PCU_SPI_CLK | SOC_SPI_CLK | ✅ | PCU_SPI_CLK is correctly connected to SPI flash with series 0-ohm resistor and optional capacitor for signal routing. | | C23 | ~PCU_SPI_CS_00 | SOC_SPI_CS0B | ✅ | PCU_SPI_CS_00 is correctly connected to SPI flash with series 0-ohm resistor for signal routing. | | C25 | SVID_CLK | SVID_CLK-R | ✅ | SVID_CLK is correctly connected for voltage regulator clock signaling. | | D14 | TAP_TCK | XDP_H_TCK | ✅ | TAP_TCK is correctly connected to JTAG clock with series resistor to ground for termination. | | D18 | ~TAP_PRDY | XDP_H_PRDYB | ✅ | TAP_PRDY is correctly connected to JTAG probe ready signal. | | D20 | PMC_ACPRESENT | PMC_ACPRESENT | ✅ | PMC_ACPRESENT is correctly connected with pull-up resistor for AC power detection. | | D22 | ~PMC_SLP_S3 | PMC_SLP_S3_L | ✅ | PMC_SLP_S3 is correctly connected through level shifter with optional pull-up for S3 sleep state signaling. | | D26 | PMC_SUSPWRDNACK | SUSPWRDNACK | ✅ | PMC_SUSPWRDNACK is correctly connected with pull-up resistor for suspend power down acknowledge. | | F12 | TAP_TDI | XDP_H_TDI | ✅ | TAP_TDI is correctly connected to JTAG data input with pull-up resistor. | | F14 | TAP_TMS | XDP_H_TMS | ✅ | TAP_TMS is correctly connected to JTAG mode select with pull-up resistor. | | F16 | ~TAP_PREQ | XDP_H_PREQB | ✅ | TAP_PREQ is correctly connected to JTAG probe request signal. | | F18 | ~PMC_SLP_S0IX | PMC_SLP_S0IX | ✅ | PMC_SLP_S0IX is correctly connected for S0ix low power state signaling. | | F20 | ~PMC_PLTRST | PMC_PLTRST_R_V1P8 | ✅ | PMC_PLTRST is correctly connected through level shifter with optional pull-up for platform reset signaling. | | F22 | ~PMC_SLP_S4 | PMC_SLP_S4_L | ✅ | PMC_SLP_S4 is correctly connected through level shifter with optional pull-up for S4 sleep state signaling. | | F26 | ~PMC_WAKE_PCIE_0 | PMC_PCIE_WAKE_R | ✅ | PMC_WAKE_PCIE_0 is correctly connected through diode with pull-ups for PCIe wake signaling. | | G12 | ~TAP_TRST | XDP_H_TRSTB | ✅ | TAP_TRST is correctly connected to JTAG reset with pull-down resistor. | | G16 | TAP_TDO | XDP_H_TDO | ✅ | TAP_TDO is correctly connected to JTAG data output. | | G18 | ~PMC_SUS_STAT | LPCPD_L | ✅ | PMC_SUS_STAT is correctly connected for suspend status signaling. | | G24 | PMC_SUSCLK0_G24 | PMC_SUSCLK0 | ✅ | PMC_SUSCLK0 is correctly connected through level shifter with optional pull-ups for suspend clock. | | J18 | GPIO_S5_25 | XDP_H_OBSDATA_A2 | ✅ | GPIO_S5[25] is correctly connected to XDP_H_OBSDATA_A2 for debug observation data. | | J20 | GPIO_S5_14 | GPIO_S514_J20 | ✅ | GPIO_S5[14] is correctly connected with pull-up resistor. | | J24 | GPIO_S5_17 | GPIO_S5_17 | ✅ | GPIO_S5[17] is correctly connected with pull-up resistor and jumper for configuration. | | J26 | ~PMC_PWRBTN | PMC_PWRBTN | ✅ | PMC_PWRBTN is correctly connected through diode network with optional pull-up for power button input. | | K18 | GPIO_S5_27 | EXP_GPIO1 | ✅ | GPIO_S5[27] is correctly connected to EXP_GPIO1 for expansion GPIO. | | K20 | GPIO_S5_28 | EXP_GPIO2 | ✅ | GPIO_S5[28] is correctly connected to EXP_GPIO2 for expansion GPIO. | | K24 | GPIO_S5_22 | GPIO_D2_LED_CTRL | ✅ | GPIO_S5[22] is correctly connected to GPIO_D2_LED_CTRL for LED control. | | K26 | ~PMC_BATLOW | PMC_BATLOW | ✅ | PMC_BATLOW is correctly connected with pull-up resistor for battery low detection. | | M18 | GPIO_S5_26 | XDP_H_OBSDATA_A3 | ✅ | GPIO_S5[26] is correctly connected to XDP_H_OBSDATA_A3 for debug observation data. | | M20 | GPIO_S5_24 | XDP_H_OBSDATA_A1 | ✅ | GPIO_S5[24] is correctly connected to XDP_H_OBSDATA_A1 for debug observation data. | | M22 | GPIO_S5_29 | EXP_GPIO3 | ✅ | GPIO_S5[29] is correctly connected to EXP_GPIO3 for expansion GPIO. | | M24 | GPIO_S5_30 | EXP_GPIO4 | ✅ | GPIO_S5[30] is correctly connected to EXP_GPIO4 for expansion GPIO. | | N24 | GPIO_S5_23 | XDP_H_OBSDATA_A0 | ✅ | GPIO_S5[23] is correctly connected to XDP_H_OBSDATA_A0 for debug observation data. | | N26 | GPIO_RCOMP | GPIO_RCOMP | ✅ | GPIO_RCOMP is correctly connected to 49.9 ohm compensation resistor to ground. | | BA28 | SIO_SPI_MISO | SOC_SIO_SPI_MISO | ✅ | SIO_SPI_MISO is correctly connected to Serial I/O SPI master in signal. | | BA34 | ~SIO_UART1_RTS | SIO_UART1_RTSB | ✅ | SIO_UART1_RTS is correctly connected to UART1 request to send signal. | | AD9 | RESERVED_AD9 | | ✅ | Reserved pins are correctly left unconnected per Intel guidance. | | AD10 | RESERVED_AD10 | | ✅ | Reserved pins are correctly left unconnected per Intel guidance. | | AD12 | RESERVED_AD12 | | ✅ | Reserved pins are correctly left unconnected per Intel guidance. | | AD13 | ICLK_RCOMP | ICLK_RCOMP | ✅ | ICLK_RCOMP is correctly connected to 47.5 ohm compensation resistor to ground. | | AD14 | ICLK_ICOMP | ICLK_ICOMP | ✅ | ICLK_ICOMP is correctly connected to 4.02K compensation resistor to ground. | | BD32 | ~SIO_UART2_RTS | | ✅ | SIO_UART2_RTS is left unconnected, which is acceptable if UART2 hardware flow control is not used. | | BD34 | SIO_UART2_TXD | SIO_UART2_TXD | ✅ | SIO_UART2_TXD is correctly connected to UART2 transmit data signal. | | AF4 | PCIE_CLKP_00 | | ✅ | PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as PCIe clock pair 0 is not used. | | AF6 | PCIE_CLKN_00 | | ✅ | PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as PCIe clock pair 0 is not used. | | AF7 | PCIE_CLKP_11 | | ✅ | PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as PCIe clock pair 1 is not used. | | AF9 | PCIE_CLKN_11 | | ✅ | PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as PCIe clock pair 1 is not used. | | BF32 | ~SIO_UART2_CTS | | ✅ | SIO_UART2_CTS is left unconnected, which is acceptable if UART2 hardware flow control is not used. | | BF34 | SIO_UART2_RXD | SIO_UART2_RXD | ✅ | SIO_UART2_RXD is correctly connected to UART2 receive data signal. | | BG9 | ~PMC_RSTBTN | PMC_RSTBTN | ✅ | PMC_RSTBTN is left unconnected. This is unusual and should be verified, as this pin typically requires a pull-up or connection to a reset button. | | AH10 | ICLK_OSCOUT | XTAL25_OUT | ✅ | ICLK_OSCOUT is correctly connected to 25 MHz crystal output with appropriate load capacitor and feedback resistor. | | AH12 | ICLK_OSCIN | XTAL25_IN | ✅ | ICLK_OSCIN is correctly connected to 25 MHz crystal input with appropriate load capacitor and feedback resistor. | | BH4 | PMC_PLT_CLK_22 | | ✅ | PMC_PLT_CLK_22 is left unconnected, which is acceptable if platform clock 2 is not used. | | BH5 | PMC_PLT_CLK_11 | | ✅ | PMC_PLT_CLK_11 is left unconnected, which is acceptable if platform clock 1 is not used. | | BH6 | PMC_PLT_CLK_44 | | ✅ | PMC_PLT_CLK_44 is left unconnected, which is acceptable if platform clock 4 is not used. | | BH7 | PMC_PLT_CLK_00 | | ✅ | PMC_PLT_CLK_00 is left unconnected, which is acceptable if platform clock 0 is not used. | | BH8 | PMC_PLT_CLK_33 | I2S_MCLK | ✅ | PMC_PLT_CLK_33 is correctly connected to I2S_MCLK for audio master clock. | | AK4 | PCIE_CLKN_22 | PCIE_CLK-N2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to PCIe clock outputs. | | AK6 | PCIE_CLKP_22 | PCIE_CLK-P2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to PCIe clock outputs. | | BJ9 | PMC_PLT_CLK_55 | | ✅ | PMC_PLT_CLK_55 is left unconnected, which is acceptable if platform clock 5 is not used. | | AM4 | PCIE_CLKN_33 | mPCIE_REFCLK_N | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to mini-PCIe reference clock outputs. | | AM6 | PCIE_CLKP_33 | mPCIE_REFCLK_P | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to mini-PCIe reference clock outputs. | | AM9 | RESERVED_AM9 | | ✅ | Reserved pins are correctly left unconnected per Intel guidance. | | AM10 | RESERVED_AM10 | | ✅ | Reserved pins are correctly left unconnected per Intel guidance. | | AT32 | SIO_PWM_11 | SOC_PWM1 | ✅ | SIO_PWM_11 is correctly connected to PWM output signal. | | AT34 | RESERVED | | ✅ | Reserved pin is correctly left unconnected per Intel guidance. | | AU32 | SIO_PWM_00 | SOC_PWM0 | ✅ | SIO_PWM_00 is correctly connected to PWM output signal. | | AU34 | SIO_UART1_RXD | SIO_UART1_RXD | ✅ | SIO_UART1_RXD is correctly connected to UART1 receive data signal. | | AV32 | ~SIO_SPI_CS | SOC_SIO_SPI_CS1 | ✅ | SIO_SPI_CS is correctly connected to Serial I/O SPI chip select signal. | | AV34 | SIO_UART1_TXD | SIO_UART1_TXD | ✅ | SIO_UART1_TXD is correctly connected to UART1 transmit data signal. | | AY28 | SIO_SPI_MOSI | SOC_SIO_SPI_MOSI | ✅ | SIO_SPI_MOSI is correctly connected to Serial I/O SPI master out signal. | | AY30 | SIO_SPI_CLK | SOC_SIO_SPI_CLK | ✅ | SIO_SPI_CLK is correctly connected to Serial I/O SPI clock signal. | | AY34 | ~SIO_UART1_CTS | SIO_UART1_CTSB | ✅ | SIO_UART1_CTS is correctly connected to UART1 clear to send signal. | </details> <details> <summary><b>D5</b> - BAT754C Schottky Diode ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 3 | | | ❌ | <details><summary>Common cathode (C) connected to +RTCVCC, but +RTCVCC is not connected to the CPU's RTC power input (BVCCRTC_EXTPAD). This is a critical error - the RTC battery backup circuit will not function without this connection.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="c66f35d31fb1590e57a5" diff-visibility="full" variant="default" view-coords="18.53,68.60,26.03,76.10" aspect-ratio="1.29" } <ul><li>Pin 3 connects to net +RTCVCC <em>(from schematic)</em></li><li>+RTCVCC connects to C286 pin 2 (1uF decoupling capacitor) and R279 pin 1 (20K resistor to RTCRST_L) <em>(from schematic)</em></li><li>The CPU has an RTC power pin B8 (ILB_RTC_EXTPAD) connected to net BVCCRTC_EXTPAD <em>(from schematic)</em></li><li>BVCCRTC_EXTPAD only connects to CPU1 pin B8 and C41 pin 1 (0.1uF decoupling capacitor) <em>(from schematic)</em></li><li>There is no component connecting +RTCVCC to BVCCRTC_EXTPAD on this schematic page <em>(from schematic)</em></li><li>The pin name &#x27;ILB_RTC_EXTPAD&#x27; with &#x27;EXTPAD&#x27; suffix indicates this pin expects an external power source <em>(reasoning)</em></li><li>The existence of a complete battery backup circuit generating +RTCVCC strongly suggests it is intended to power the RTC <em>(reasoning)</em></li><li>Without power to the RTC power pin, the RTC cannot function and will not maintain time when main power is removed <em>(reasoning)</em></li><li>A connection (0-ohm resistor or direct trace) should be added between +RTCVCC and BVCCRTC_EXTPAD to properly power the RTC <em>(reasoning)</em></li></ul></details> | | 1 | | | ✅ | Anode 1 (A1) connected to +PS_3VSB (3.3V standby power), providing primary power source for RTC through OR-ing diode configuration. | | 2 | | | ✅ | Anode 2 (A2) connected to +VBAT_R (battery voltage through 1K current-limiting resistor R278), providing backup power source for RTC when standby power is absent. | </details> <details> <summary><b>BH1</b> - BATTERY HOLDER VERT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/353-0003073) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +VBAT | ✅ | Positive battery terminals connected in parallel to +VBAT net, which supplies battery backup power through current-limiting resistor R278. | | 2 | P2 | +VBAT | ✅ | Positive battery terminals connected in parallel to +VBAT net, which supplies battery backup power through current-limiting resistor R278. | | 3 | N | GND | ✅ | Negative battery terminal correctly connected to ground. | </details> <details> <summary><b>Y1</b> - 32.768KHz Crystal ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/145-0004789) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BRTCX2 | ✅ | Crystal pin connected to BRTCX2, which connects to CPU RTC oscillator output (ILB_RTC_X2), load capacitor C42 (18pF), and feedback resistor R76 (10M). | | 2 | 2 | BRTCX1 | ✅ | Crystal pin connected to BRTCX1, which connects to CPU RTC oscillator input (ILB_RTC_X1), load capacitor C43 (18pF), and feedback resistor R76 (10M). | </details> <details> <summary><b>Y2</b> - 25.00MHz Crystal ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XTAL25_IN | ✅ | Crystal input pin correctly connected to CPU oscillator input (ICLK_OSCIN) through XTAL25_IN net with proper 27pF load capacitor C175 to ground and 1M feedback resistor R188 to output. | | 2 | 2 | GND | ✅ | Ground pins correctly connected to GND net for crystal shielding. | | 4 | 4 | GND | ✅ | Ground pins correctly connected to GND net for crystal shielding. | | 3 | 3 | XTAL25_OUT | ✅ | Crystal output pin correctly connected to CPU oscillator output (ICLK_OSCOUT) through XTAL25_OUT net with proper 27pF load capacitor C176 to ground and 1M feedback resistor R188 to input. | </details> <details> <summary><b>U19</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA power supply pin correctly connected to +V1P8A (1.8V rail). | | 2 | A1 | PMC_PLTRST_R_V1P8 | ✅ | A1 channel correctly connected to PMC_PLTRST_R_V1P8 from CPU1 pin F20. | | 3 | A2 | PMC_SUSCLK0 | ✅ | A2 channel correctly connected to PMC_SUSCLK0 from CPU1 pin G24. | | 4 | A3 | PMC_SLP_S4_L | ✅ | A3 channel correctly connected to PMC_SLP_S4_L from CPU1 pin F22. | | 5 | A4 | PMC_SLP_S3_L | ✅ | A4 channel correctly connected to PMC_SLP_S3_L from CPU1 pin D22. | | 6 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 7 | B4 | SLP_S3_L | ✅ | B4 channel correctly connected to SLP_S3_L, translating from A4. | | 8 | B3 | SLP_S4_L | ✅ | B3 channel correctly connected to SLP_S4_L, translating from A3. | | 9 | B2 | SUSCLK_3P3 | ✅ | B2 channel correctly connected to SUSCLK_3P3, translating from A2. | | 10 | B1 | PMC_PLTRST_L | ✅ | B1 channel correctly connected to PMC_PLTRST_L, translating from A1. | | 11 | VCCB | PWR_BUF1 | ✅ | VCCB power supply pin correctly connected to PWR_BUF1, which is tied to +3VSB through R26. | | 12 | OE | PMC_OE | ✅ | OE (output enable) pin correctly connected to PMC_OE with pull-up to +V1P8A through R57. | </details> <details> <summary><b>D3</b> - BAT54A-S Schottky Diode ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE | ✅ | Both pins connected to PMC_PCIE_WAKE in the 3.3V domain. The package designation 'BAT54_132_2' indicates a non-standard symbol pinout where these pins represent paralleled cathodes, despite standard BAT54A-S having pin 2 as the common anode. | | 2 | 2 | PMC_PCIE_WAKE | ✅ | Both pins connected to PMC_PCIE_WAKE in the 3.3V domain. The package designation 'BAT54_132_2' indicates a non-standard symbol pinout where these pins represent paralleled cathodes, despite standard BAT54A-S having pin 2 as the common anode. | | 3 | 3 | PMC_PCIE_WAKE_R | ✅ | Connected to PMC_PCIE_WAKE_R in the 1.8V domain going to the CPU. With the non-standard symbol pinout indicated by package designation 'BAT54_132_2', this pin represents the common anode, enabling proper level shifting functionality. | </details> <details> <summary><b>D10</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | 3VSB_OK | ✅ | Anode 1 connected to 3VSB_OK signal. This allows the 3VSB power good signal to control PS_OUT_L. | | A2 | A2 | PMC_PWRBTN | ✅ | Anode 2 connected to PMC_PWRBTN signal from CPU. This allows the power button signal to control PS_OUT_L. | | C | C | PS_OUT_L | ✅ | Common cathode connected to PS_OUT_L output signal. This output is pulled low when either 3VSB_OK or PMC_PWRBTN goes low. | </details> <details> <summary><b>J7</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_17 | ✅ | Pin 1 connects to GPIO_S5_17, which is pulled high to +V1P8S through R183 (10K) when the jumper is not installed. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the pull-down path when the jumper is installed. | </details> <details> <summary><b>R75</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor connected to +V1P8S power rail. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Pull-up resistor connected to PCU_SMB_ALERT signal from CPU1. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A7 | USB_HSIC_RCOMP | USB_HSIC0_RCOMP | ✅ | USB_HSIC_RCOMP pin correctly connected to ground through a 45.3 ohm compensation resistor. | | B4 | USB_HSIC0_DATA | | ✅ | USB_HSIC0_DATA and USB_HSIC0_STROBE pins are not connected, which is acceptable if USB HSIC interface is not used. | | B5 | USB_HSIC0_STROBE | | ✅ | USB_HSIC0_DATA and USB_HSIC0_STROBE pins are not connected, which is acceptable if USB HSIC interface is not used. | | B12 | GPIO_S5_43 | | ✅ | GPIO_S5_43 pin (USB_ULPI_REFCLK) is not connected, which is acceptable if USB ULPI interface is not used. | | B20 | ~USB_OC_11 | SOC_USB_HOST_OC1 | ✅ | USB_OC[1]# pin correctly connected with 10K pull-up resistor to +V1P8A for overcurrent detection. | | C7 | USB_RCOMPI | USB_RCOMP | ✅ | USB_RCOMPI and USB_RCOMPO pins correctly connected together to ground through a 45.3 ohm compensation resistor. | | D6 | USB_RCOMPO | USB_RCOMP | ✅ | USB_RCOMPI and USB_RCOMPO pins correctly connected together to ground through a 45.3 ohm compensation resistor. | | C20 | ~USB_OC_00 | SOC_USB_HOST_OC0 | ✅ | USB_OC[0]# pin correctly connected with 10K pull-up resistor to +V1P8A for overcurrent detection. | | D2 | USB_HSIC1_STROBE | | ✅ | USB_HSIC1_STROBE and USB_HSIC1_DATA pins are not connected, which is acceptable if USB HSIC1 interface is not used. | | E2 | USB_HSIC1_DATA | | ✅ | USB_HSIC1_STROBE and USB_HSIC1_DATA pins are not connected, which is acceptable if USB HSIC1 interface is not used. | | D4 | USB3_RXP0 | USB3_RXP0 | ✅ | USB3 differential signal pins correctly connected for USB 3.0 operation. | | E3 | USB3_RXN0 | USB3_RXN0 | ✅ | USB3 differential signal pins correctly connected for USB 3.0 operation. | | K6 | USB3_TXP0 | USB3_TXP0 | ✅ | USB3 differential signal pins correctly connected for USB 3.0 operation. | | K7 | USB3_TXN0 | USB3_TXN0 | ✅ | USB3 differential signal pins correctly connected for USB 3.0 operation. | | D10 | ICLK_USB_TERM_1 | ICLK_USB_TERM_0 | ✅ | ICLK_USB_TERM_1 pin correctly connected to ground through a 1K termination resistor. | | F10 | ICLK_USB_TERMN | ICLK_USB_TERM_1 | ✅ | ICLK_USB_TERMN pin correctly connected to ground through a 1K termination resistor. | | G2 | GPIO_S5_31 | | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | G14 | USB_DN1 | USB_DN1 | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | H3 | GPIO_S5_42 | | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | H10 | USB_DN3 | | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | J3 | GPIO_S5_40 | | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | J12 | USB_DN2 | USB_HOST_DN | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | J14 | USB_DP1 | USB_DP1 | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | K10 | USB_DP3 | | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | K12 | USB_DP2 | USB_HOST_DP | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | K16 | USB_DN0 | USB_DN0 | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | M16 | USB_DP0 | USB_DP0 | ✅ | USB data pins correctly connected for USB 2.0 ports 0, 1, and 2. Port 3 is not connected. | | H4 | RESERVED_H4 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | H5 | RESERVED_H5 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | H7 | RESERVED_H7 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | H8 | RESERVED_H8 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | M4 | RESERVED_M4 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | M6 | RESERVED_M6 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | M7 | RESERVED_M7 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | M9 | RESERVED_M9 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | M10 | RESERVED_M10 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | P6 | RESERVED_P6 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | P7 | RESERVED_P7 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | P10 | RESERVED_P10 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | P12 | RESERVED_P12 | | ✅ | Reserved pins are not connected, which is correct per standard practice unless datasheet specifies otherwise. | | K2 | GPIO_S5_34 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | K3 | GPIO_S5_35 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | L1 | GPIO_S5_33 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | L3 | GPIO_S5_39 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | M2 | GPIO_S5_36 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | M3 | GPIO_S5_32 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | N3 | GPIO_S5_37 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | P2 | GPIO_S5_38 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | P3 | GPIO_S5_41 | | ✅ | GPIO_S5 pins (USB_ULPI_DATA and USB_ULPI_NXT) are not connected, which is acceptable if USB ULPI interface is not used. | | M12 | USB3_REXT0 | USB3_REXT0 | ✅ | USB3_REXT0 pin correctly connected to ground through a 1.24K external resistor for USB 3.0. | | M13 | USB_PLL_MON | USB_PLL_MON | ✅ | USB_PLL_MON pin connected to test point for USB PLL monitoring. | | BC12 | GPIO_S0_SC_56 | GPIO_S0_SC_56 | ✅ | GPIO_S0_SC_56 pin connected to off-page net, function determined by software configuration. | | BC14 | GPIO_S0_SC_58 | HDMI_CEC | ✅ | GPIO_S0_SC_58 pin connected to HDMI_CEC signal for HDMI Consumer Electronics Control. | | BC16 | GPIO_S0_SC_61 | PCU_UART3_RXD | ✅ | GPIO_S0_SC_61 pin correctly configured as UART3 RXD and connected through level shifter U6 to debug connector. | | BD12 | GPIO_S0_SC_55 | GPIO_S0_SC_55 | ✅ | GPIO_S0_SC_55 pin connected to off-page net with DNI test point. | | BD14 | GPIO_S0_SC_57 | PCU_UART3_TXD | ✅ | GPIO_S0_SC_57 pin correctly configured as UART3 TXD and connected through level shifter U6 to debug connector. | | BD16 | GPIO_S0_SC_60 | | ✅ | GPIO_S0_SC_60 and GPIO_S0_SC_59 pins are not connected, which is acceptable if these GPIOs are not used. | | BF14 | GPIO_S0_SC_59 | | ✅ | GPIO_S0_SC_60 and GPIO_S0_SC_59 pins are not connected, which is acceptable if these GPIOs are not used. | | BF18 | LPC_RCOMP | LPC_RCOMP | ✅ | LPC_RCOMP pin correctly connected to ground through a 49.9 ohm compensation resistor. | | BG11 | ~PCU_SMB_ALERT | PCU_SMB_ALERT | ✅ | PCU_SMB_ALERT# pin correctly connected with 10K pull-up to +V1P8S and routed through 0-ohm jumper to LAN interface. | | BG12 | PCU_SMB_DATA | PCU_SMB_DATA | ✅ | PCU_SMB_DATA pin correctly connected with 2.2K pull-up to +V1P8S and routed through level shifter U5 for voltage translation. | | BG13 | ILB_LPC_SERIRQ | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BG14 | ILB_LPC_AD_33 | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BG15 | ILB_LPC_CLK_00 | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BG16 | ~ILB_LPC_CLKRUN | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BG17 | ~ILB_LPC_FRAME | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BH14 | ILB_LPC_CLK_11 | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BH16 | ILB_LPC_AD_00 | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BJ13 | ILB_LPC_AD_22 | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BJ17 | ILB_LPC_AD_11 | | ✅ | LPC interface pins are not connected, which is acceptable if LPC bus is not used. Datasheet indicates these pins have internal pull-ups. | | BG23 | SIO_I2C0_CLK | | ✅ | SIO_I2C0 interface pins are not connected, which is acceptable if I2C0 is not used. | | BH22 | SIO_I2C0_DATA | | ✅ | SIO_I2C0 interface pins are not connected, which is acceptable if I2C0 is not used. | | BG24 | SIO_I2C1_DATA | SIO_I2C1_SDA | ✅ | SIO_I2C1_DATA pin connected to off-page net with DNI test point for I2C1 data signal. | | BG25 | SIO_I2C2_DATA | | ✅ | SIO_I2C2 interface pins are not connected, which is acceptable if I2C2 is not used. | | BJ25 | SIO_I2C2_CLK | | ✅ | SIO_I2C2 interface pins are not connected, which is acceptable if I2C2 is not used. | | BG26 | SIO_I2C3_DATA | | ✅ | SIO_I2C3 interface pins are not connected, which is acceptable if I2C3 is not used. | | BH26 | SIO_I2C3_CLK | | ✅ | SIO_I2C3 interface pins are not connected, which is acceptable if I2C3 is not used. | | BG27 | SIO_I2C4_CLK | | ✅ | SIO_I2C4 interface pins are not connected, which is acceptable if I2C4 is not used. | | BF27 | SIO_I2C4_DATA | | ✅ | SIO_I2C4 interface pins are not connected, which is acceptable if I2C4 is not used. | | BG28 | SIO_I2C5_CLK | SI0_I2C5_SCL | ✅ | SIO_I2C5_CLK pin correctly connected through 22 ohm series resistor for I2C signal conditioning. | | BG29 | SIO_I2C6_CLK | SI0_I2C6_SCL | ✅ | SIO_I2C6_CLK pin correctly connected through 22 ohm series resistor for I2C signal conditioning. | | BG30 | GPIO_S0_SC_093 | TP10_NET | ✅ | GPIO_S0_SC_093 pin intentionally grounded through 0-ohm resistor R261 per schematic text note. | | BH10 | PCU_SMB_CLK | PCU_SMB_CLK | ✅ | PCU_SMB_CLK pin correctly connected with 2.2K pull-up to +V1P8S and routed through level shifter U5 for voltage translation. | | BH12 | ILB_8254_SPKR | ILB_8254_SPKR | ✅ | ILB_8254_SPKR pin connected to off-page net for speaker output signal. | | BH24 | SIO_I2C1_CLK | SIO_I2C1_SCL | ✅ | SIO_I2C1_CLK pin connected to off-page net with DNI test point for I2C1 clock signal. | | BH28 | SIO_I2C5_DATA | SI0_I2C5_SDA | ✅ | SIO_I2C5_DATA pin correctly connected through 22 ohm series resistor for I2C signal conditioning. | | BH30 | GPIO_S0_SC_092 | TP9_NET | ✅ | GPIO_S0_SC_092 pin intentionally grounded through 0-ohm resistor R243 per schematic text note. | | BJ29 | SIO_I2C6_DATA | SI0_I2C6_SDA | ✅ | SIO_I2C6_DATA pin correctly connected through 22 ohm series resistor for I2C signal conditioning. | </details> <details> <summary><b>U5</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DDR_SMB_CLK | ✅ | B2 pin correctly connected to DDR_SMB_CLK for 3.3V side clock signal translation. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V) supply for A-side operation. | | 4 | A2 | PCU_SMB_CLK | ✅ | A2 pin correctly connected to PCU_SMB_CLK for 1.8V side clock signal from CPU. | | 5 | A1 | PCU_SMB_DATA | ✅ | A1 pin correctly connected to PCU_SMB_DATA for 1.8V side data signal from CPU. | | 6 | OE | PCU_SMB_BUFF_ENB | ✅ | OE pin correctly connected to PCU_SMB_BUFF_ENB with pull-up for buffer enable control. | | 7 | VCCB | BUF2_PWR | ✅ | VCCB pin correctly connected to BUF2_PWR (3.3V) supply for B-side operation. | | 8 | B1 | DDR_SMB_DATA | ✅ | B1 pin correctly connected to DDR_SMB_DATA for 3.3V side data signal translation. | </details> <details> <summary><b>U6</b> - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DBG_UART3_TXD | ✅ | B2 pin correctly connected to DBG_UART3_TXD for 3.3V side UART TX signal from the board to the debug connector. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply) for the CPU side. | | 4 | A2 | PCU_UART3_TXD | ✅ | A2 pin correctly connected to PCU_UART3_TXD for 1.8V side UART TX signal from the CPU. | | 5 | A1 | PCU_UART3_RXD | ✅ | A1 pin correctly connected to PCU_UART3_RXD for 1.8V side UART RX signal to the CPU. | | 6 | OE | LSENB | ✅ | OE pin correctly connected to LSENB with pull-up to +V1P8S, enabling the level shifter by default. | | 7 | VCCB | BUF3_PWR | ✅ | VCCB pin correctly connected to BUF3_PWR (3.3V supply) for the connector side. | | 8 | B1 | DBG_UART3_RXD | ✅ | B1 pin correctly connected to DBG_UART3_RXD for 3.3V side UART RX signal from the debug connector to the board. | </details> <details> <summary><b>R52</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LSENB | ✅ | Pull-up resistor connecting LSENB to +V1P8S, ensuring the level shifter enable signal defaults to high (enabled state). | | 2 | 2 | +V1P8S | ✅ | Pull-up resistor connecting LSENB to +V1P8S, ensuring the level shifter enable signal defaults to high (enabled state). | </details> <details> <summary><b>R51</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF3_PWR | ✅ | Zero-ohm jumper connecting BUF3_PWR to +3VSB, providing power to the level shifter's B-side while allowing optional isolation or current measurement. | | 2 | 2 | +3VSB | ✅ | Zero-ohm jumper connecting BUF3_PWR to +3VSB, providing power to the level shifter's B-side while allowing optional isolation or current measurement. | </details> <details> <summary><b>J4</b> - 258-0004869 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0004869) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net, providing ground reference for the serial cable. | | 2 | 2 | | ✅ | Pins 2, 3, and 6 are not connected, which is correct for a basic 3-wire UART interface (GND, TX, RX only). | | 3 | 3 | | ✅ | Pins 2, 3, and 6 are not connected, which is correct for a basic 3-wire UART interface (GND, TX, RX only). | | 6 | 6 | | ✅ | Pins 2, 3, and 6 are not connected, which is correct for a basic 3-wire UART interface (GND, TX, RX only). | | 4 | 4 | DBG_UART3_RXD | ✅ | Receive pin correctly connected to DBG_UART3_RXD, allowing the board to receive data from the external serial cable. | | 5 | 5 | DBG_UART3_TXD_R | ✅ | Transmit pin correctly connected to DBG_UART3_TXD_R, allowing the board to transmit data to the external serial cable. | </details> <details> <summary><b>R819</b> - 110-0002000 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002000) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DBG_UART3_TXD | ✅ | Series resistor on the UART transmit line providing signal conditioning, current limiting, and EMI reduction. | | 2 | 2 | DBG_UART3_TXD_R | ✅ | Series resistor on the UART transmit line providing signal conditioning, current limiting, and EMI reduction. | </details> <details> <summary><b>R50</b> - 110-0001859 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001859) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pull-down resistor on the UART receive line ensuring a defined logic level when no cable is connected. | | 2 | 2 | DBG_UART3_RXD | ✅ | Pull-down resistor on the UART receive line ensuring a defined logic level when no cable is connected. | </details> <details> <summary><b>R77</b> - 110-0004472 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU1 pin A7) and GND, serving as a compensation resistor for the USB HSIC interface. | | 2 | 2 | USB_HSIC0_RCOMP | ✅ | 45.3 ohm resistor connected between USB_HSIC0_RCOMP (CPU1 pin A7) and GND, serving as a compensation resistor for the USB HSIC interface. | </details> <details> <summary><b>R185</b> - 110-0004472 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 45.3 ohm resistor connected between USB_RCOMP (CPU1 pins D6 and C7) and GND, serving as a compensation resistor for the USB 2.0 interface. | | 2 | 2 | USB_RCOMP | ✅ | 45.3 ohm resistor connected between USB_RCOMP (CPU1 pins D6 and C7) and GND, serving as a compensation resistor for the USB 2.0 interface. | </details> <details> <summary><b>R187</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 1K ohm resistor connected between ICLK_USB_TERM_0 (CPU1 pin D10) and GND, serving as a termination resistor for the USB interface. | | 2 | 2 | ICLK_USB_TERM_0 | ✅ | 1K ohm resistor connected between ICLK_USB_TERM_0 (CPU1 pin D10) and GND, serving as a termination resistor for the USB interface. | </details> <details> <summary><b>R186</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 1K ohm resistor connected between ICLK_USB_TERM_1 (CPU1 pin F10) and GND, serving as a termination resistor for the USB interface. | | 2 | 2 | ICLK_USB_TERM_1 | ✅ | 1K ohm resistor connected between ICLK_USB_TERM_1 (CPU1 pin F10) and GND, serving as a termination resistor for the USB interface. | </details> <details> <summary><b>R212</b> - 110-0004478 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004478) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_REXT0 | ✅ | 1.24K ohm resistor connected between USB3_REXT0 (CPU1 pin M12) and GND, serving as an external reference resistor for the USB 3.0 interface. | | 2 | 2 | GND | ✅ | 1.24K ohm resistor connected between USB3_REXT0 (CPU1 pin M12) and GND, serving as an external reference resistor for the USB 3.0 interface. | </details> <details> <summary><b>R241</b> - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPC_RCOMP | ✅ | 49.9 ohm resistor connected between LPC_RCOMP (CPU1 pin BF18) and GND, serving as a compensation resistor for the LPC interface. | | 2 | 2 | GND | ✅ | 49.9 ohm resistor connected between LPC_RCOMP (CPU1 pin BF18) and GND, serving as a compensation resistor for the LPC interface. | </details> <details> <summary><b>R12</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SCL | ✅ | Pin 1 connects to the SOC's I2C6 SCL pin (CPU1 BG29) on net SI0_I2C6_SCL. | | 2 | 2 | I2C6_SCL | ✅ | Pin 2 connects to the external I2C6 SCL bus on net I2C6_SCL. | </details> <details> <summary><b>R11</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SDA | ✅ | Pin 1 connects to the SOC's I2C6 SDA pin (CPU1 BJ29) on net SI0_I2C6_SDA. | | 2 | 2 | I2C6_SDA | ✅ | Pin 2 connects to the external I2C6 SDA bus on net I2C6_SDA. | </details> <details> <summary><b>R270</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SCL | ✅ | Pin 1 connects to the SOC's I2C5 SCL pin (CPU1 BG28) on net SI0_I2C5_SCL. | | 2 | 2 | I2C5_SCL | ✅ | Pin 2 connects to the external I2C5 SCL bus on net I2C5_SCL. | </details> <details> <summary><b>R269</b> - 110-0001967 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001967) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SDA | ✅ | Pin 1 connects to the SOC's I2C5 SDA pin (CPU1 BH28) on net SI0_I2C5_SDA. | | 2 | 2 | I2C5_SDA | ✅ | Pin 2 connects to the external I2C5 SDA bus on net I2C5_SDA. | </details> <details> <summary><b>R177</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor connection to +V1P8S power rail for I2C data line. | | 2 | 2 | PCU_SMB_DATA | ✅ | Connection to PCU_SMB_DATA, the I2C data line from the CPU. | </details> <details> <summary><b>R45</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor connection to +V1P8S power rail for I2C clock line. | | 2 | 2 | PCU_SMB_CLK | ✅ | Connection to PCU_SMB_CLK, the I2C clock line from the CPU. | </details> <details> <summary><b>R84</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pull-up resistor connection to +V1P8A power rail for USB overcurrent detection. | | 2 | 2 | SOC_USB_HOST_OC0 | ✅ | Connection to SOC_USB_HOST_OC0, an active-low USB overcurrent detection input on the CPU. | </details> <details> <summary><b>R97</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pull-up resistor connection to +V1P8A power rail for USB overcurrent detection. | | 2 | 2 | SOC_USB_HOST_OC1 | ✅ | Connection to SOC_USB_HOST_OC1, an active-low USB overcurrent detection input on the CPU. | </details> <details> <summary><b>R261</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP10_NET | ✅ | Pin 1 connects to TP10_NET, which is connected to CPU1 GPIO_S0_SC_093 (pin BG30) and test point TP16. This provides a connection from the GPIO to the 0-ohm resistor. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, completing the path to ground the GPIO pin through the 0-ohm resistor as intended by the design notes. | </details> <details> <summary><b>R243</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP9_NET | ✅ | Pin 1 connects to TP9_NET, which is connected to CPU1 GPIO_S0_SC_092 (pin BH30) and test point TP13. This provides a connection from the GPIO to the 0-ohm resistor. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, completing the path to ground the GPIO pin through the 0-ohm resistor as intended by the design notes. | </details> <details> <summary><b>TP1</b> - TEST_POINT_0.040_SMT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/999-0000003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $9N613 | ✅ | Test point correctly connected to CPU internal voltage monitoring pin AF30 for 1.05V core voltage measurement. | </details> <details> <summary><b>TP2</b> - TEST_POINT_0.040_SMT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/999-0000003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $9N615 | ✅ | Test point correctly connected to CPU internal voltage monitoring pin AA22 for core VCC measurement in S0IX state. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A48 | DRAM_VDD_S4 | +VDIMM | ✅ | DRAM_VDD_S4 power pin correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | N28 | CORE_VSS_SENSE_N28 | VSS_SENSE | ✅ | Core ground sense pin correctly connected to VSS_SENSE net for voltage regulator feedback. | | P28 | CORE_VCC_SENSE_P28 | VCC_SENSE | ✅ | Core VCC sense pin correctly connected to VCC_SENSE net for voltage regulator feedback. | | AA22 | TP2_CORE_VCC_S0IX | $9N615 | ✅ | Test point pin for monitoring core VCC in S0IX state, correctly connected to external test point TP2. | | AA24 | UNCORE_VNN_S3_AA24 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AC22 | UNCORE_VNN_S3_AC22 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AC24 | UNCORE_VNN_S3_AC24 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AD22 | UNCORE_VNN_S3_AD22 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AD24 | UNCORE_VNN_S3_AD24 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AF22 | UNCORE_VNN_S3_AF22 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AF24 | UNCORE_VNN_S3_AF24 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AG22 | UNCORE_VNN_S3_AG22 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AG24 | UNCORE_VNN_S3_AG24 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AJ22 | UNCORE_VNN_S3_AJ22 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AJ24 | UNCORE_VNN_S3_AJ24 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AK22 | UNCORE_VNN_S3_AK22 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AK24 | UNCORE_VNN_S3_AK24 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AK25 | UNCORE_VNN_S3_AK25 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AK27 | UNCORE_VNN_S3_AK27 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AK29 | UNCORE_VNN_S3_AK29 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AK30 | UNCORE_VNN_S3_AK30 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AK32 | UNCORE_VNN_S3_AK32 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AM22 | UNCORE_VNN_S3_AM22 | +VGFX | ✅ | UNCORE_VNN_S3 power pins correctly connected to +VGFX rail with appropriate decoupling capacitors. | | AA27 | CORE_VCC_S0IX_AA27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AA29 | CORE_VCC_S0IX_AA29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AA30 | CORE_VCC_S0IX_AA30 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AC27 | CORE_VCC_S0IX_AC27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AC29 | CORE_VCC_S0IX_AC29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AC30 | CORE_VCC_S0IX_AC30 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AD27 | CORE_VCC_S0IX_AD27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AD29 | CORE_VCC_S0IX_AD29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AD30 | CORE_VCC_S0IX_AD30 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AF27 | CORE_VCC_S0IX_AF27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AF29 | CORE_VCC_S0IX_AF29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AG27 | CORE_VCC_S0IX_AG27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AG29 | CORE_VCC_S0IX_AG29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | AG30 | CORE_VCC_S0IX_AG30 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | P26 | CORE_VCC_S0IX_P26 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | P27 | CORE_VCC_S0IX_P27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | U27 | CORE_VCC_S0IX_U27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | U29 | CORE_VCC_S0IX_U29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | V27 | CORE_VCC_S0IX_V27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | V29 | CORE_VCC_S0IX_V29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | V30 | CORE_VCC_S0IX_V30 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | Y27 | CORE_VCC_S0IX_Y27 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | Y29 | CORE_VCC_S0IX_Y29 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | Y30 | CORE_VCC_S0IX_Y30 | +VCORE | ✅ | CORE_VCC_S0IX power pins correctly connected to +VCORE rail with appropriate decoupling capacitors. | | BB8 | UNCORE_VNN_SENSE | VCCGT_SENSE | ✅ | UNCORE_VNN voltage sense pin correctly connected to VCCGT_SENSE net for voltage regulator feedback. | | AD38 | DRAM_VDD_S4_AD38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 power pins connected to separate DRAM_VDD_CLK rail for clock power isolation, derived from +VDIMM through 0-ohm jumper R275. | | AF38 | DRAM_VDD_S4_AF38 | DRAM_VDD_CLK | ✅ | DRAM_VDD_S4 power pins connected to separate DRAM_VDD_CLK rail for clock power isolation, derived from +VDIMM through 0-ohm jumper R275. | | AF30 | TP_CORE_V1P05_S4 | $9N613 | ✅ | Test point pin for monitoring 1.05V core voltage in S4 state, correctly connected to external test point TP1. | | AK38 | DRAM_VDD_S4_AK38 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | AM38 | DRAM_VDD_S4_AM38 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | AV41 | DRAM_VDD_S4_AV41 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | AV42 | DRAM_VDD_S4_AV42 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | BB46 | DRAM_VDD_S4_BB46 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | BD49 | DRAM_VDD_S4_BD49 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | BD52 | DRAM_VDD_S4_BD52 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | BD53 | DRAM_VDD_S4_BD53 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | BF44 | DRAM_VDD_S4_BF44 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | BG51 | DRAM_VDD_S4_BG51 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | BJ48 | DRAM_VDD_S4_BJ48 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | C51 | DRAM_VDD_S4_C51 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | D44 | DRAM_VDD_S4_D44 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | F49 | DRAM_VDD_S4_F49 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | F52 | DRAM_VDD_S4_F52 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | F53 | DRAM_VDD_S4_F53 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | H46 | DRAM_VDD_S4_H46 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | M41 | DRAM_VDD_S4_M41 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | M42 | DRAM_VDD_S4_M42 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | V38 | DRAM_VDD_S4_V38 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | | Y38 | DRAM_VDD_S4_Y38 | +VDIMM | ✅ | DRAM_VDD_S4 power pins correctly connected to +VDIMM rail with appropriate decoupling capacitors. | </details> <details> <summary><b>R275</b> - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | 0-ohm jumper connecting +VDIMM power rail to DRAM_VDD_CLK net, which supplies CPU1 pins AD38 and AF38. This appears to be an intentional design to provide separately filtered power for specific DRAM power pins. | | 2 | 2 | DRAM_VDD_CLK | ✅ | 0-ohm jumper connecting +VDIMM power rail to DRAM_VDD_CLK net, which supplies CPU1 pins AD38 and AF38. This appears to be an intentional design to provide separately filtered power for specific DRAM power pins. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AC32 | CORE_V1P05_S3_AC32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,41.55,44.21,49.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | Y32 | CORE_V1P05_S3_Y32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,42.13,44.21,49.63" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | AA33 | CORE_V1P05_S3_AA33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,33.31,44.21,40.81" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | AF33 | CORE_V1P05_S3_AF33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,28.61,61.48,36.11" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | AG33 | CORE_V1P05_S3_AG33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.20,61.48,36.70" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | AG35 | CORE_V1P05_S3_AG35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.79,61.48,37.29" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | U33 | CORE_V1P05_S3_U33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.37,61.48,37.87" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | U35 | CORE_V1P05_S3_U35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.96,61.48,38.46" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | V33 | CORE_V1P05_S3_V33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,31.55,61.48,39.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</em></li><li>These pins are connected to net +V1P0S in the schematic <em>(from schematic)</em></li><li>The +V1P0S net provides 1.0V according to the power rail naming convention <em>(from schematic)</em></li><li>According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A <em>(from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</em></li><li>The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V <em>(reasoning)</em></li><li>This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail <em>(reasoning)</em></li><li>The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available <em>(from schematic)</em></li><li>These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification <em>(reasoning)</em></li><li>Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot <em>(reasoning)</em></li></ul></details> | | A7 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B4 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B5 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B7 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B8 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B10 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B12 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B14 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B16 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B18 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B20 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B22 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B24 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B26 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B28 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B30 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | D14 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | D18 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | D20 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | D22 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | D26 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | D27 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | F12 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | F14 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | F16 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | F20 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | F22 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | F26 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | G2 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | G12 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | G14 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | G16 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | G18 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | G24 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | G30 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | H3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | H10 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | J3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | J12 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | J14 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | J20 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | J26 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | J30 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K2 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K6 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K7 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K10 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K12 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K16 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K26 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | K30 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | L1 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | L3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | M2 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | M3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | M4 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | M6 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | M16 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | M30 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | N3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | N30 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | P2 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | P3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C20 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C21 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C22 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C23 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C24 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C25 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C26 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C27 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | C28 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | D4 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | E3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AL1 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AL3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AK2 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AK3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP2 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AR1 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AR3 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AT2 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AK4 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AK6 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AM4 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AM6 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP4 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP6 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP7 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP9 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP10 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | AP12 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BH20 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BJ21 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BH22 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BH24 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BH26 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BH28 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BJ25 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BJ29 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BH14 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BH16 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BJ13 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BJ17 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | BJ9 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A9 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A13 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A17 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A21 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A25 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A29 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A33 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A37 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A41 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A45 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B32 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B34 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B36 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B38 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B40 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B42 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B44 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B46 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B47 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B48 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B49 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | B50 | | | ✅ | Signal pins for various interfaces including USB HSIC/2.0/3.0, JTAG, power management, display (DDI/VGA), PCIe, HD Audio, I2C, LPC, GPIO, SPI, and DDR3L memory. Connections follow standard interface requirements and pin naming conventions. | | A48 | | | ✅ | DRAM_VDD_S4 power pin correctly connected to DDR3L memory power supply rail, providing 1.35V power for the memory interface. | | B6 | UNCORE_V1P0_G3_B6 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply). | | C5 | UNCORE_V1P0_G3_C5 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply). | | U22 | UNCORE_V1P0_G3_U22 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply). | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | UNCORE_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply). | | C3 | USB3_V1P0_G3_C3 | +V1P0A | ✅ | USB3_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply). | | Y19 | USB3_V1P0_G3_Y19 | +V1P0A | ✅ | USB3_V1P0_G3 power pins are correctly connected to +V1P0A (1.0V always-on supply). | | F1 | RESERVED_F1 | $10N1595 | ✅ | RESERVED_F1 pin is connected to test point TP4 which is marked DNI (Do Not Install). Reserved pins typically have no specific function and this connection is acceptable. | | M14 | USB_V1P0_S3_M14 | +V1P0S | ✅ | USB_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | U18 | USB_V1P0_S3_U18 | +V1P0S | ✅ | USB_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | U19 | USB_V1P0_S3_U19 | +V1P0S | ✅ | USB_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | N18 | USB_V3P3_G3_N18 | +3VSB | ✅ | USB_V3P3_G3 power pins are correctly connected to +3VSB (3.3V standby supply). | | P18 | USB_V3P3_G3_P18 | +3VSB | ✅ | USB_V3P3_G3 power pins are correctly connected to +3VSB (3.3V standby supply). | | N20 | USB_V1P8_G3_N20 | +V1P8A | ✅ | USB_V1P8_G3 power pin is correctly connected to +V1P8A (1.8V always-on supply). | | N22 | PCU_V3P3_G3_N22 | +3VSB | ✅ | PCU_V3P3_G3 power pin is correctly connected to +3VSB (3.3V standby supply). | | P22 | RTC_VCC_P22 | +RTCVCC | ✅ | RTC_VCC power pin is correctly connected to +RTCVCC (RTC battery backup supply). | | U16 | USB_VSSA_U16 | GND | ✅ | USB_VSSA ground pin is correctly connected to GND. | | U24 | UNCORE_V1P8_G3_U24 | +V1P8A | ✅ | UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply). | | U25 | PMU_V1P8_G3_U25 | +V1P8A | ✅ | UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply). | | V25 | PCU_V1P8_G3_V25 | +V1P8A | ✅ | UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply). | | AA18 | UNCORE_V1P8_G3_AA18 | +V1P8A | ✅ | UNCORE_V1P8_G3, PCU_V1P8_G3, and PMU_V1P8_G3 power pins are correctly connected to +V1P8A (1.8V always-on supply). | | V18 | USB_HSIC_V1P24_G3_V18 | +V1P0A | ✅ | USB_HSIC_V1P24_G3 power pin is connected to +V1P0A (1.0V). This is acceptable when USB HSIC is not used, as indicated by a schematic note. | | V24 | UNCORE_V1P0_S0IX_V24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222). | | Y24 | UNCORE_V1P0_S0IX_Y24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222). | | Y22 | UNCORE_V1P0_S0IX_Y22 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222). | | AN29 | UNCORE_V1P0_S0IX_AN29 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222). | | AN30 | UNCORE_V1P0_S0IX_AN30 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222). | | AF21 | UNCORE_V1P0_S0IX_AF21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222). | | AG21 | UNCORE_V1P0_S0IX_AG21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which is derived from +V1P0S through a 0-ohm jumper (R222). | | V32 | SVID_V1P0_S3_V32 | +V1P0S | ✅ | SVID_V1P0_S3 power pin is correctly connected to +V1P0S (1.0V S3 suspend supply). | | AA25 | UNCORE_V1P35_S0IX_F5_AA25 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3. | | AD36 | DRAM_V1P35_S0IX_F1_AD36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3. | | AF19 | UNCORE_V1P35_S0IX_F6 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3. | | V36 | UNCORE_V1P35_S0IX_F3_V36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3. | | U36 | UNCORE_V1P35_S0IX_F4_U36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3. | | AG32 | UNCORE_V1P35_S0IX_F2_AG32 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3. | | AG19 | UNCORE_V1P35_S0IX_F1_AG19 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX power pins are correctly connected to VCC_UNCORE_V1P35, which is derived from +V1P35S through ferrite bead FB3. | | AA36 | DRAM_V1P0_S0IX_AA36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | AD35 | DRAM_V1P0_S0IX_AD35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | AF35 | DRAM_V1P0_S0IX_AF35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | AF36 | DRAM_V1P0_S0IX_AF36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | AJ36 | DRAM_V1P0_S0IX_AJ36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | AK35 | DRAM_V1P0_S0IX_AK35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | AK36 | DRAM_V1P0_S0IX_AK36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | Y35 | DRAM_V1P0_S0IX_Y35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | Y36 | DRAM_V1P0_S0IX_Y36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which is derived from +V1P0S through a 0-ohm jumper (R265). | | AD16 | VSS_AD16 | VCC_VSS_V1P2 | ✅ | VSS ground pins are connected to VCC_VSS_V1P2 net which connects to GND through R216 (0 ohm resistor). This unusual configuration may be intentional for current sensing or isolation. | | AD18 | VSS_AD18 | VCC_VSS_V1P2 | ✅ | VSS ground pins are connected to VCC_VSS_V1P2 net which connects to GND through R216 (0 ohm resistor). This unusual configuration may be intentional for current sensing or isolation. | | BD1 | VGA_V1P35_S3_F1_BD1 | VCC_CRT_V1P35 | ✅ | VGA_V1P35_S3_F1 power pin is correctly connected to VCC_CRT_V1P35, which is derived from +V1P35S through ferrite bead FB4. | | AF16 | UNCORE_V1P0_S3_AF16 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AF18 | UNCORE_V1P0_S3_AF18 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | G1 | UNCORE_V1P0_S3_G1 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | Y18 | UNCORE_V1P0_S3_Y18 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AJ18 | DDI_V1P0_S0IX_AJ18 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AK19 | DDI_V1P0_S0IX_AK19 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AK21 | DDI_V1P0_S0IX_AK21 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AM16 | DDI_V1P0_S0IX_AM16 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AJ19 | ICLK_V1P35_S3_F1_AJ19 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which is derived from +V1P35S through ferrite bead FB5. | | AG18 | ICLK_V1P35_S3_F2 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which is derived from +V1P35S through ferrite bead FB5. | | BJ6 | VGA_V1P0_S3_BJ6 | +V1P0S | ✅ | VGA_V1P0_S3 power pin is correctly connected to +V1P0S (1.0V S3 suspend supply). | | AM27 | LPC_V1P8V3P3_S3_AM27 | +VCC3S | ✅ | LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V S3 suspend supply). | | AN27 | SD3_V1P8V3P3_S3_AN27 | +VCC3S | ✅ | LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V S3 suspend supply). | | AM30 | UNCORE_V1P8_S3_AM30 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S (1.8V S3 suspend supply). | | AN32 | UNCORE_V1P8_S3_AN32 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S (1.8V S3 suspend supply). | | U38 | UNCORE_V1P8_S3_U38 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S (1.8V S3 suspend supply). | | AM32 | HDA_LPE_V1P5V1P8_S3_AM32 | +V1P8S | ✅ | HDA_LPE_V1P5V1P8_S3 power pin is correctly connected to +V1P8S (1.8V S3 suspend supply). | | AN16 | VSSA_AN16 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A3 | VSS_A3_A3 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A5 | VSS_A5_A5 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A6 | VSS_A6_A6 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A11 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A15 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A19 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A23 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A27 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A31 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A35 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A39 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A43 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A47 | | | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A49 | VSS_A49_A49 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A51 | VSS_A51_A51 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | A52 | VSS_A52_A52 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | B2 | VSS_B2_B2 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | B52 | VSS_B52_B52 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | B53 | VSS_B53_B53 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BE1 | VSS_BE1_BE1 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BE53 | VSS_BE53_BE53 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BG1 | VSS_BG1_BG1 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BG53 | VSS_BG53_BG53 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BH1 | VSS_BH1_BH1 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BH2 | VSS_BH2_BH2 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BH52 | VSS_BH52_BH52 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BH53 | VSS_BH53_BH53 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BJ2 | VSS_BJ2_BJ2 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BJ3 | VSS_BJ3_BJ3 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BJ5 | VSS_BJ5_BJ5 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BJ49 | VSS_BJ49_BJ49 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BJ51 | VSS_BJ51_BJ51 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | BJ52 | VSS_BJ52_BJ52 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | C1 | VSS_C1_C1 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | C53 | VSS_C53_C53 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | E1 | VSS_E1_E1 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | E53 | VSS_E53_E53 | GND | ✅ | Ground pins (VSS, USB_VSSA, VSSA) correctly connected to GND net, providing proper ground reference for the SoC. Note that pins AD16 and AD18 are also VSS pins but are connected to GND through a separate net VCC_VSS_V1P2 via 0-ohm resistor R216. | | AN18 | PCIE_SATA_V1P0_S3_AN18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AN19 | SATA_V1P0_S3_AN19 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AN21 | PCIE_V1P0_S3_AN21 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AM21 | PCIE_V1P0_S3_AM21 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AM18 | PCIE_V1P0_S3_AM18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AK18 | PCIE_V1P0_S3_AK18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, PCIE_V1P0_S3, and SATA_V1P0_S3 power pins are correctly connected to +V1P0S (1.0V S3 suspend supply). | | AN24 | VGA_V3P3_S3_AN24 | +VCC3S | ✅ | VGA_V3P3_S3 power pin is correctly connected to +VCC3S (3.3V S3 suspend supply). | | AN25 | GPIO_V1P0_S3_AN25 | +V1P0S | ✅ | GPIO_V1P0_S3 power pin is correctly connected to +V1P0S (1.0V S3 suspend supply). | </details> <details> <summary><b>FB3</b> - FERRITE_600OHM_1.3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/126-0001423) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to +V1P35S supply rail. This pin receives the 1.35V supply voltage that will be filtered before reaching the VCC_UNCORE_V1P35 rail. | | 2 | 2 | VCC_UNCORE_V1P35 | ✅ | Output pin connected to VCC_UNCORE_V1P35 rail. This pin provides filtered 1.35V power to the uncore voltage domain of the CPU. | </details> <details> <summary><b>FB4</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to +V1P35S supply rail, providing the source voltage for the VGA 1.35V power domain. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Output pin connected to VCC_CRT_V1P35 rail which supplies the VGA power domain on CPU1. The ferrite bead provides EMI filtering between the source supply and the VGA power domain. | </details> <details> <summary><b>C164</b> - 22uF 20% 6.3V 0805 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin providing return path for decoupling capacitor on VCC_CRT_V1P35 rail. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Power pin connected to VCC_CRT_V1P35 rail. This 22uF bulk capacitor provides low-frequency decoupling and charge storage for the VGA 1.35V power domain. | </details> <details> <summary><b>C28</b> ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin providing return path for decoupling capacitor on VCC_CRT_V1P35 rail. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Power pin connected to VCC_CRT_V1P35 rail. This 10uF capacitor complements C164 to provide decoupling across a wider frequency range for the VGA 1.35V power domain. | </details> <details> <summary><b>FB5</b> - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input side of ferrite bead connected to +V1P35S main power rail. This connection is correct. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Output side of ferrite bead connected to VCC_ICLK_V1P35, providing filtered power to CPU1 integrated clock circuitry. This connection is correct. | </details> <details> <summary><b>C26</b> - 1uF 10% 16V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for decoupling capacitor. This connection is correct. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Connected to VCC_ICLK_V1P35 rail, providing local decoupling for integrated clock power. This connection is correct. | </details> <details> <summary><b>C27</b> - 1uF 10% 16V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for decoupling capacitor. This connection is correct. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Connected to VCC_ICLK_V1P35 rail, providing additional local decoupling for integrated clock power. This connection is correct. | </details> <details> <summary><b>R216</b> - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VSS_V1P2 | ✅ | 0-ohm jumper resistor connecting VCC_VSS_V1P2 net to GND. This provides a ground connection for CPU1 pins AD16 and AD18 (VSS ground pins) through a separate net topology. | | 2 | 2 | GND | ✅ | 0-ohm jumper resistor connecting VCC_VSS_V1P2 net to GND. This provides a ground connection for CPU1 pins AD16 and AD18 (VSS ground pins) through a separate net topology. | </details> <details> <summary><b>TP4</b> - TEST_POINT_0.040_SMT ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $10N1595 | ✅ | Test point connected to CPU1 reserved pin F1 via net $10N1595. Component is marked DNI (Do Not Install), making this connection electrically absent in production, which is acceptable for a reserved processor pin. | </details> <details> <summary><b>D7</b> - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N connects to GND. This is the ground reference terminal of the bidirectional TVS diode. | | P | P | +5VSB | ✅ | Pin P connects to +5VSB power rail for ESD/transient protection. This is the protected line terminal of the bidirectional TVS diode. | </details> <details> <summary><b>J8</b> - 3430-0212 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3430-0212) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to +5VSB power rail. This is the power input pin of the connector. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This is the ground return pin of the connector. | </details> <details> <summary><b>C153</b> - 0.1uF ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to +5VSB power rail. This is the positive terminal of the bypass capacitor. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This is the negative terminal of the bypass capacitor. | </details> <details> <summary><b>CPU1</b> - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A11 | VSS1 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A15 | VSS2 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A19 | VSS3 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A23 | VSS4 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A27 | VSS5 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A31 | VSS6 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A35 | VSS7 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A39 | VSS8 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A43 | VSS9 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A47 | VSS10 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA1 | VSS11 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA3 | VSS15 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA16 | VSS12 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA19 | VSS13 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA21 | VSS14 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA32 | VSS16 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA35 | VSS17 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA38 | VSS18 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA53 | VSS19 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB4 | VSS21 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB6 | VSS28 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB10 | VSS20 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB41 | VSS22 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB45 | VSS23 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB47 | VSS24 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB48 | VSS25 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB50 | VSS26 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB51 | VSS27 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC16 | VSS29 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC18 | VSS30 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC19 | VSS31 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC21 | VSS32 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC25 | VSS33 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC33 | VSS34 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC35 | VSS35 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC36 | VSS36 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC38 | VSS37 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD7 | VSS44 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD19 | VSS38 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD21 | VSS39 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD25 | VSS40 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD32 | VSS41 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD33 | VSS42 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD47 | VSS43 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE1 | VSS45 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE3 | VSS49 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE4 | VSS50 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE6 | VSS60 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE8 | VSS61 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE9 | VSS62 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE11 | VSS46 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE12 | VSS47 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE14 | VSS48 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE40 | VSS51 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE42 | VSS52 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE43 | VSS53 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE45 | VSS54 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE46 | VSS55 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE48 | VSS56 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE50 | VSS57 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE51 | VSS58 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE53 | VSS59 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF10 | VSS63 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF12 | VSS64 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF25 | VSS65 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF32 | VSS66 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF47 | VSS67 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG16 | VSS68 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG25 | VSS69 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG36 | VSS70 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG38 | VSS71 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH4 | VSS72 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH6 | VSS110 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH7 | VSS75 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH9 | VSS76 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH41 | VSS73 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH45 | VSS74 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH47 | VSS106 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH48 | VSS107 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH50 | VSS108 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH51 | VSS109 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ1 | VSS77 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ3 | VSS83 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ16 | VSS78 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ21 | VSS79 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ25 | VSS80 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ27 | VSS81 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ29 | VSS82 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ30 | VSS84 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ32 | VSS85 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ33 | VSS86 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ35 | VSS87 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ38 | VSS88 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ53 | VSS89 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK10 | VSS90 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK14 | VSS91 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK16 | VSS92 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK33 | VSS93 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK41 | VSS94 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK44 | VSS95 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM7 | VSS113 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM12 | VSS96 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM19 | VSS97 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM24 | VSS98 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM25 | VSS99 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM29 | VSS100 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM33 | VSS101 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM35 | VSS102 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM36 | VSS103 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM40 | VSS104 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM44 | VSS111 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM51 | VSS112 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN1 | VSS114 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN3 | VSS119 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN5 | VSS131 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN6 | VSS134 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN8 | VSS135 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN9 | VSS136 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN11 | VSS115 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN12 | VSS116 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN14 | VSS117 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN22 | VSS118 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN33 | VSS120 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN35 | VSS121 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN36 | VSS122 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN38 | VSS123 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN40 | VSS124 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN42 | VSS125 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN43 | VSS126 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN45 | VSS127 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN46 | VSS128 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN48 | VSS129 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN49 | VSS130 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN51 | VSS132 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN53 | VSS133 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AP40 | VSS137 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT4 | VSS146 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT12 | VSS138 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT16 | VSS139 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT19 | VSS140 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT24 | VSS141 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT27 | VSS142 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT30 | VSS143 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT35 | VSS144 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT38 | VSS145 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT47 | VSS147 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT52 | VSS148 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU1 | VSS149 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU3 | VSS151 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU24 | VSS150 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU30 | VSS152 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU38 | VSS153 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU51 | VSS154 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV7 | VSS167 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV12 | VSS155 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV13 | VSS156 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV14 | VSS157 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV18 | VSS158 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV19 | VSS159 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV24 | VSS160 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV27 | VSS161 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV30 | VSS162 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV35 | VSS163 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV38 | VSS164 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV47 | VSS165 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV51 | VSS166 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW3 | VSS171 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW13 | VSS168 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW19 | VSS169 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW27 | VSS170 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW35 | VSS172 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY4 | VSS177 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY9 | VSS179 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY10 | VSS173 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY22 | VSS174 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY32 | VSS175 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY36 | VSS176 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY50 | VSS178 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA14 | VSS180 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA19 | VSS181 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA22 | VSS182 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA27 | VSS183 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA32 | VSS184 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA35 | VSS185 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA40 | VSS186 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA53 | VSS187 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BB19 | VSS188 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BB27 | VSS189 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BB35 | VSS190 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC20 | VSS191 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC22 | VSS192 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC26 | VSS193 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC28 | VSS194 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC32 | VSS195 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC34 | VSS196 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC42 | VSS197 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD19 | VSS198 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD24 | VSS199 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD27 | VSS200 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD30 | VSS201 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD35 | VSS202 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE2 | VSS204 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE8 | VSS206 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE19 | VSS203 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE35 | VSS205 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF4 | VSS213 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF12 | VSS207 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF16 | VSS208 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF24 | VSS209 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF30 | VSS211 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF36 | VSS212 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF38 | VSS210 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG31 | VSS214 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG34 | VSS215 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG39 | VSS216 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG42 | VSS217 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG45 | VSS218 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG49 | VSS219 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ7 | VSS230 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ11 | VSS220 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ15 | VSS221 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ19 | VSS222 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ23 | VSS223 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ27 | VSS224 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ31 | VSS225 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ35 | VSS226 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ39 | VSS227 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ43 | VSS228 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ47 | VSS229 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C14 | VSS231 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C31 | VSS232 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C34 | VSS233 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C39 | VSS234 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C42 | VSS235 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C45 | VSS236 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C49 | VSS237 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D12 | VSS238 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D16 | VSS239 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D24 | VSS240 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D30 | VSS241 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D36 | VSS242 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D38 | VSS243 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | E8 | VSS246 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | E19 | VSS244 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | E35 | VSS245 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F2 | VSS248 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F5 | VSS253 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F7 | VSS254 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F19 | VSS247 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F24 | VSS249 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F27 | VSS250 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F30 | VSS251 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F35 | VSS252 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G10 | VSS255 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G20 | VSS256 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G22 | VSS257 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G26 | VSS258 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G28 | VSS259 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G32 | VSS260 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G34 | VSS261 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G42 | VSS262 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | H19 | VSS263 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | H27 | VSS264 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | H35 | VSS265 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J1 | VSS266 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J16 | VSS267 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J19 | VSS268 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J22 | VSS269 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J27 | VSS270 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J32 | VSS271 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J35 | VSS272 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J40 | VSS273 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J53 | VSS274 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K4 | VSS279 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K9 | VSS281 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K14 | VSS275 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K22 | VSS276 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K32 | VSS277 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K36 | VSS278 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K50 | VSS280 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L13 | VSS282 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L19 | VSS283 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L27 | VSS284 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L35 | VSS285 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M19 | VSS286 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M26 | VSS287 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M27 | VSS288 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M28 | VSS105 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M34 | VSS289 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M35 | VSS290 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M38 | VSS291 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M47 | VSS292 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M51 | VSS293 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N1 | VSS294 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N16 | VSS295 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N38 | VSS296 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N51 | VSS297 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P4 | VSS306 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P9 | VSS309 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P13 | VSS298 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P16 | VSS299 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P19 | VSS300 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P20 | VSS301 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P24 | VSS302 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P32 | VSS303 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P35 | VSS304 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P38 | VSS305 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P47 | VSS307 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P52 | VSS308 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | T40 | VSS310 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U1 | VSS311 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U3 | VSS316 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U5 | VSS326 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U6 | VSS329 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U8 | VSS330 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U9 | VSS331 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U11 | VSS312 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U12 | VSS313 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U14 | VSS314 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U21 | VSS315 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U30 | VSS317 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U32 | VSS318 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U40 | VSS319 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U42 | VSS320 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U43 | VSS321 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U45 | VSS322 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U46 | VSS323 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U48 | VSS324 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U49 | VSS325 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U51 | VSS327 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U53 | VSS328 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V7 | VSS340 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V12 | VSS332 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V16 | VSS333 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V19 | VSS334 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V21 | VSS335 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V35 | VSS336 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V40 | VSS337 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V44 | VSS338 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V51 | VSS339 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y7 | VSS349 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y9 | VSS350 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y10 | VSS341 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y14 | VSS342 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y16 | VSS343 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y21 | VSS344 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y25 | VSS345 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y33 | VSS346 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y41 | VSS347 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y44 | VSS348 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | </details> <details> <summary><b>MEM3</b> - MT41K256M16HA-125:E ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | C1 | VDDQ2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | R1 | VDD7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | B2 | VDD8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | D2 | VDDQ9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | H2 | VDDQ4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | K2 | VDD9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | G7 | VDD1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | A8 | VDDQ5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | K8 | VDD2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | C9 | VDDQ6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | N1 | VDD6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | F1 | VDDQ3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | D9 | VDD4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | E9 | VDDQ7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | H9 | VDDQ8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | N9 | VDD3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | R9 | VDD5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail, same as MEM2. | | A2 | DQU5 | M_DATA_A30 | ✅ | DQU5 is correctly connected to M_DATA_A30. | | A3 | DQU7 | M_DATA_A31 | ✅ | DQU7 is correctly connected to M_DATA_A31. | | A7 | DQU4 | M_DATA_A25 | ✅ | DQU4 is correctly connected to M_DATA_A25. | | B1 | VSSQ1 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | D1 | VSSQ2 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | E1 | VSS1 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | G1 | VSSQ3 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | M1 | VSS2 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | P1 | VSS3 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | T1 | VSS4 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | E2 | VSSQ4 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | J2 | VSS5 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | B3 | VSS6 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | D8 | VSSQ5 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | E8 | VSSQ6 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | G8 | VSS7 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | J8 | VSS8 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | A9 | VSS9 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | B9 | VSSQ7 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | F9 | VSSQ8 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | G9 | VSSQ9 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | M9 | VSS10 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | P9 | VSS11 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | T9 | VSS12 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. | | B7 | /DQSU | M_DQS_A_N3 | ✅ | UDQS# is correctly connected to M_DQS_A_N3. | | B8 | DQU6 | M_DATA_A24 | ✅ | DQU6 is correctly connected to M_DATA_A24. | | C2 | DQU3 | M_DATA_A27 | ✅ | DQU3 is correctly connected to M_DATA_A27. | | C3 | DQU1 | M_DATA_A26 | ✅ | DQU1 is correctly connected to M_DATA_A26. | | C7 | DQSU | M_DQS_A_P3 | ✅ | UDQS is correctly connected to M_DQS_A_P3. | | C8 | DQU2 | M_DATA_A28 | ✅ | DQU2 is correctly connected to M_DATA_A28. | | D3 | DMU | M_DM_A3 | ✅ | UDM is correctly connected to M_DM_A3. | | D7 | DQU0 | M_DATA_A29 | ✅ | DQU0 is correctly connected to M_DATA_A29. | | E3 | DQL0 | M_DATA_A16 | ✅ | DQL0 is correctly connected to M_DATA_A16, forming part of the upper 16 bits of the 32-bit data bus. | | E7 | DML | M_DM_A2 | ✅ | LDM is correctly connected to M_DM_A2. | | F2 | DQL2 | M_DATA_A18 | ✅ | DQL2 is correctly connected to M_DATA_A18. | | F3 | DQSL | M_DQS_A_P2 | ✅ | LDQS is correctly connected to M_DQS_A_P2. | | F7 | DQL1 | M_DATA_A17 | ✅ | DQL1 is correctly connected to M_DATA_A17. | | F8 | DQL3 | M_DATA_A19 | ✅ | DQL3 is correctly connected to M_DATA_A19. | | G2 | DQL6 | M_DATA_A22 | ✅ | DQL6 is correctly connected to M_DATA_A22. | | G3 | /DQSL | M_DQS_A_N2 | ✅ | LDQS# is correctly connected to M_DQS_A_N2. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ is correctly connected to SM_VREF_DQ1_A, shared with MEM2. | | H3 | DQL4 | M_DATA_A20 | ✅ | DQL4 is correctly connected to M_DATA_A20. | | H7 | DQL7 | M_DATA_A23 | ✅ | DQL7 is correctly connected to M_DATA_A23. | | H8 | DQL5 | M_DATA_A21 | ✅ | DQL5 is correctly connected to M_DATA_A21. | | J1 | NC1__ODT1_ | | ✅ | NC pins are correctly left unconnected as specified in the datasheet. | | L1 | NC2__/CS1_ | | ✅ | NC pins are correctly left unconnected as specified in the datasheet. | | J9 | NC3__CKE1_ | | ✅ | NC pins are correctly left unconnected as specified in the datasheet. | | L9 | NC4__ZQ1_ | | ✅ | NC pins are correctly left unconnected as specified in the datasheet. | | M7 | NC5 | | ✅ | NC pins are correctly left unconnected as specified in the datasheet. | | J3 | /RAS | M_RAS_A_L | ✅ | RAS# is correctly connected to M_RAS_A_L, shared with MEM2. | | J7 | CK | M_CLK_A_P0 | ✅ | CK is correctly connected to M_CLK_A_P0, shared with MEM2. | | K1 | ODT | M_ODT_A0 | ✅ | ODT is correctly connected to M_ODT_A0, shared with MEM2. | | K3 | /CAS | M_CAS_A_L | ✅ | CAS# is correctly connected to M_CAS_A_L, shared with MEM2. | | K7 | /CK | M_CLK_A_N0 | ✅ | CK# is correctly connected to M_CLK_A_N0, shared with MEM2. | | K9 | CKE | M_CKE_A0 | ✅ | CKE is correctly connected to M_CKE_A0, shared with MEM2. | | L2 | /CS | M_CS_A_L0 | ✅ | CS# is correctly connected to M_CS_A_L0, shared with MEM2. | | L3 | /WE | M_WE_A_L | ✅ | WE# is correctly connected to M_WE_A_L, shared with MEM2. | | L7 | A10_AP_ | M_MA_A10 | ✅ | A10/AP is correctly connected to M_MA_A10, shared with MEM2. | | L8 | ZQ | M_ZQ2 | ✅ | ZQ is correctly connected to M_ZQ2, which has a 240Ω resistor (R327) to ground as required. | | M2 | BA0 | M_BS_A0 | ✅ | BA0 is correctly connected to M_BS_A0, shared with MEM2. | | M3 | BA2 | M_BS_A2 | ✅ | BA2 is correctly connected to M_BS_A2, shared with MEM2. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA is correctly connected to SM_VREF_CA1_A, shared with MEM2. | | N2 | A3 | M_MA_A3 | ✅ | A3 is correctly connected to M_MA_A3, shared with MEM2. | | N3 | A0 | M_MA_A0 | ✅ | A0 is correctly connected to M_MA_A0, shared with MEM2. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | A12/BC# is correctly connected to M_MA_A12, shared with MEM2. | | N8 | BA1 | M_BS_A1 | ✅ | BA1 is correctly connected to M_BS_A1, shared with MEM2. | | P2 | A5 | M_MA_A5 | ✅ | A5 is correctly connected to M_MA_A5, shared with MEM2. | | P3 | A2 | M_MA_A2 | ✅ | A2 is correctly connected to M_MA_A2, shared with MEM2. | | P7 | A1 | M_MA_A1 | ✅ | A1 is correctly connected to M_MA_A1, shared with MEM2. | | P8 | A4 | M_MA_A4 | ✅ | A4 is correctly connected to M_MA_A4, shared with MEM2. | | R2 | A7 | M_MA_A7 | ✅ | A7 is correctly connected to M_MA_A7, shared with MEM2. | | R3 | A9 | M_MA_A9 | ✅ | A9 is correctly connected to M_MA_A9, shared with MEM2. | | R7 | A11 | M_MA_A11 | ✅ | A11 is correctly connected to M_MA_A11, shared with MEM2. | | R8 | A6 | M_MA_A6 | ✅ | A6 is correctly connected to M_MA_A6, shared with MEM2. | | T2 | /RESET | M_A_RST_L | ✅ | RESET# is correctly connected to M_A_RST_L, shared with MEM2. | | T3 | A13 | M_MA_A13 | ✅ | A13 is correctly connected to M_MA_A13, shared with MEM2. | | T7 | A14 | M_MA_A14 | ✅ | A14 is correctly connected to M_MA_A14, shared with MEM2. | | T8 | A8 | M_MA_A8 | ✅ | A8 is correctly connected to M_MA_A8, shared with MEM2. | </details> <details> <summary><b>MEM2</b> - MT41K256M16HA-125:E ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | C1 | VDDQ2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | R1 | VDD7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | B2 | VDD8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | D2 | VDDQ9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | H2 | VDDQ4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | K2 | VDD9 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | G7 | VDD1 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | A8 | VDDQ5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | K8 | VDD2 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | C9 | VDDQ6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | N1 | VDD6 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | F1 | VDDQ3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | D9 | VDD4 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | E9 | VDDQ7 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | H9 | VDDQ8 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | N9 | VDD3 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | R9 | VDD5 | +VDIMM | ✅ | Power supply pins (VDD and VDDQ) are correctly connected to +VDIMM rail. All power pins are tied together as required for DDR3L operation. | | A2 | DQU5 | M_DATA_A15 | ✅ | DQU5 is correctly connected to M_DATA_A15. | | A3 | DQU7 | M_DATA_A14 | ✅ | DQU7 is correctly connected to M_DATA_A14. | | A7 | DQU4 | M_DATA_A13 | ✅ | DQU4 is correctly connected to M_DATA_A13. | | B1 | VSSQ1 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | D1 | VSSQ2 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | E1 | VSS1 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | G1 | VSSQ3 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | M1 | VSS2 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | P1 | VSS3 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | T1 | VSS4 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | E2 | VSSQ4 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | J2 | VSS5 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | B3 | VSS6 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | D8 | VSSQ5 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | E8 | VSSQ6 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | G8 | VSS7 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | J8 | VSS8 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | A9 | VSS9 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | B9 | VSSQ7 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | F9 | VSSQ8 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | G9 | VSSQ9 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | M9 | VSS10 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | P9 | VSS11 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | T9 | VSS12 | GND | ✅ | Ground pins (VSS and VSSQ) are correctly connected to GND. All ground pins are properly tied to the ground plane. | | B7 | /DQSU | M_DQS_A_N1 | ✅ | UDQS# (upper byte data strobe complement) is correctly connected to M_DQS_A_N1. | | B8 | DQU6 | M_DATA_A12 | ✅ | DQU6 is correctly connected to M_DATA_A12. | | C2 | DQU3 | M_DATA_A11 | ✅ | DQU3 is correctly connected to M_DATA_A11. | | C3 | DQU1 | M_DATA_A10 | ✅ | DQU1 is correctly connected to M_DATA_A10. | | C7 | DQSU | M_DQS_A_P1 | ✅ | UDQS (upper byte data strobe positive) is correctly connected to M_DQS_A_P1. | | C8 | DQU2 | M_DATA_A8 | ✅ | DQU2 is correctly connected to M_DATA_A8. | | D3 | DMU | M_DM_A1 | ✅ | UDM (upper byte data mask) is correctly connected to M_DM_A1. | | D7 | DQU0 | M_DATA_A9 | ✅ | DQU0 is correctly connected to M_DATA_A9. | | E3 | DQL0 | M_DATA_A0 | ✅ | DQL0 (lower byte data bit 0) is correctly connected to M_DATA_A0, forming part of the 32-bit data bus lower 16 bits. | | E7 | DML | M_DM_A0 | ✅ | LDM (lower byte data mask) is correctly connected to M_DM_A0. | | F2 | DQL2 | M_DATA_A2 | ✅ | DQL2 is correctly connected to M_DATA_A2. | | F3 | DQSL | M_DQS_A_P0 | ✅ | LDQS (lower byte data strobe positive) is correctly connected to M_DQS_A_P0. | | F7 | DQL1 | M_DATA_A1 | ✅ | DQL1 is correctly connected to M_DATA_A1. | | F8 | DQL3 | M_DATA_A3 | ✅ | DQL3 is correctly connected to M_DATA_A3. | | G2 | DQL6 | M_DATA_A6 | ✅ | DQL6 is correctly connected to M_DATA_A6. | | G3 | /DQSL | M_DQS_A_N0 | ✅ | LDQS# (lower byte data strobe complement) is correctly connected to M_DQS_A_N0. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ (reference voltage for data) is correctly connected to SM_VREF_DQ1_A, which is generated by voltage divider R310/R325 to provide VDD/2. Shared with MEM3. | | H3 | DQL4 | M_DATA_A4 | ✅ | DQL4 is correctly connected to M_DATA_A4. | | H7 | DQL7 | M_DATA_A7 | ✅ | DQL7 is correctly connected to M_DATA_A7. | | H8 | DQL5 | M_DATA_A5 | ✅ | DQL5 is correctly connected to M_DATA_A5. | | J1 | NC1__ODT1_ | | ✅ | NC (no connect) pins are correctly left unconnected as specified in the datasheet. | | L1 | NC2__/CS1_ | | ✅ | NC (no connect) pins are correctly left unconnected as specified in the datasheet. | | J9 | NC3__CKE1_ | | ✅ | NC (no connect) pins are correctly left unconnected as specified in the datasheet. | | L9 | NC4__ZQ1_ | | ✅ | NC (no connect) pins are correctly left unconnected as specified in the datasheet. | | M7 | NC5 | | ✅ | NC (no connect) pins are correctly left unconnected as specified in the datasheet. | | J3 | /RAS | M_RAS_A_L | ✅ | RAS# (row address strobe) is correctly connected to M_RAS_A_L, shared with MEM3. | | J7 | CK | M_CLK_A_P0 | ✅ | CK (differential clock positive) is correctly connected to M_CLK_A_P0, shared with MEM3. | | K1 | ODT | M_ODT_A0 | ✅ | ODT (on-die termination enable) is correctly connected to M_ODT_A0, shared with MEM3. | | K3 | /CAS | M_CAS_A_L | ✅ | CAS# (column address strobe) is correctly connected to M_CAS_A_L, shared with MEM3. | | K7 | /CK | M_CLK_A_N0 | ✅ | CK# (differential clock complement) is correctly connected to M_CLK_A_N0, shared with MEM3. | | K9 | CKE | M_CKE_A0 | ✅ | CKE (clock enable) is correctly connected to M_CKE_A0, shared with MEM3. | | L2 | /CS | M_CS_A_L0 | ✅ | CS# (chip select) is correctly connected to M_CS_A_L0, shared with MEM3. | | L3 | /WE | M_WE_A_L | ✅ | WE# (write enable) is correctly connected to M_WE_A_L, shared with MEM3. | | L7 | A10_AP_ | M_MA_A10 | ✅ | A10/AP (address bit 10 with auto-precharge) is correctly connected to M_MA_A10, shared with MEM3. | | L8 | ZQ | M_ZQ1 | ✅ | ZQ (calibration reference) is correctly connected to M_ZQ1, which has a 240Ω resistor (R140) to ground as required by the datasheet. | | M2 | BA0 | M_BS_A0 | ✅ | BA0 (bank address bit 0) is correctly connected to M_BS_A0, shared with MEM3. | | M3 | BA2 | M_BS_A2 | ✅ | BA2 is correctly connected to M_BS_A2, shared with MEM3. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA (reference voltage for control/address) is correctly connected to SM_VREF_CA1_A, which is generated by voltage divider R144/R326 to provide VDD/2. Shared with MEM3. | | N2 | A3 | M_MA_A3 | ✅ | A3 is correctly connected to M_MA_A3, shared with MEM3. | | N3 | A0 | M_MA_A0 | ✅ | A0 (address bit 0) is correctly connected to M_MA_A0, shared with MEM3. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | A12/BC# (address bit 12 with burst chop) is correctly connected to M_MA_A12, shared with MEM3. | | N8 | BA1 | M_BS_A1 | ✅ | BA1 is correctly connected to M_BS_A1, shared with MEM3. | | P2 | A5 | M_MA_A5 | ✅ | A5 is correctly connected to M_MA_A5, shared with MEM3. | | P3 | A2 | M_MA_A2 | ✅ | A2 is correctly connected to M_MA_A2, shared with MEM3. | | P7 | A1 | M_MA_A1 | ✅ | A1 is correctly connected to M_MA_A1, shared with MEM3. | | P8 | A4 | M_MA_A4 | ✅ | A4 is correctly connected to M_MA_A4, shared with MEM3. | | R2 | A7 | M_MA_A7 | ✅ | A7 is correctly connected to M_MA_A7, shared with MEM3. | | R3 | A9 | M_MA_A9 | ✅ | A9 is correctly connected to M_MA_A9, shared with MEM3. | | R7 | A11 | M_MA_A11 | ✅ | A11 is correctly connected to M_MA_A11, shared with MEM3. | | R8 | A6 | M_MA_A6 | ✅ | A6 is correctly connected to M_MA_A6, shared with MEM3. | | T2 | /RESET | M_A_RST_L | ✅ | RESET# (active-low reset) is correctly connected to M_A_RST_L through series resistor R353. Shared with MEM3. | | T3 | A13 | M_MA_A13 | ✅ | A13 is correctly connected to M_MA_A13, shared with MEM3. | | T7 | A14 | M_MA_A14 | ✅ | A14 is correctly connected to M_MA_A14, shared with MEM3. | | T8 | A8 | M_MA_A8 | ✅ | A8 is correctly connected to M_MA_A8, shared with MEM3. | </details> <details> <summary><b>R144</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM power supply, forming the upper connection of a voltage divider for VREFCA reference generation. | | 2 | 2 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A, the command/address reference voltage node for DDR3 memories MEM2 and MEM3. | </details> <details> <summary><b>R326</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the lower connection of a voltage divider for VREFCA reference generation. | | 2 | 2 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A, completing the voltage divider that generates VDD/2 reference voltage. | </details> <details> <summary><b>C133</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A to provide AC filtering and decoupling for the reference voltage. | | 2 | 2 | GND | ✅ | Connected to GND to complete the bypass capacitor function for the VREFCA reference voltage. | </details> <details> <summary><b>C344</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A to provide additional AC filtering and decoupling for the reference voltage. | | 2 | 2 | GND | ✅ | Connected to GND to complete the bypass capacitor function. | </details> <details> <summary><b>R310</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Upper resistor in VREFDQ voltage divider, connected to +VDIMM supply. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A reference voltage net, forms voltage divider midpoint. | </details> <details> <summary><b>R325</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower resistor in VREFDQ voltage divider, connected to ground. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A reference voltage net, forms voltage divider midpoint. | </details> <details> <summary><b>C124</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Decoupling capacitor for VREFDQ reference voltage, positioned near MEM2. | | 2 | 2 | GND | ✅ | Ground connection for decoupling capacitor. | </details> <details> <summary><b>C329</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Decoupling capacitor for VREFDQ reference voltage, positioned near MEM3. | | 2 | 2 | GND | ✅ | Ground connection for decoupling capacitor. | </details> <details> <summary><b>R327</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001971) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ2 | ✅ | Connected to M_ZQ2 net, which connects to the ZQ (impedance calibration) pin of DDR3 memory device MEM3. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the ZQ impedance calibration resistor. | </details> <details> <summary><b>R140</b> - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001971) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ1 | ✅ | Connected to M_ZQ1 net, which connects to the ZQ (impedance calibration) pin of DDR3 memory device MEM2. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the ZQ impedance calibration resistor. | </details> <details> <summary><b>C287</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to GND, providing the ground reference for this decoupling capacitor. | | 2 | 2 | +VCC3 | ✅ | Pin 2 is correctly connected to +VCC3, providing decoupling for the 3.3V power rail. The capacitor remains populated even though nearby component U33 is DNI, which is acceptable for maintaining power rail stability. | </details> <details> <summary><b>P2</b> - 158-0001269 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/158-0001269) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | SD3_D2_R | ✅ | DAT2 receives the filtered SD data line 2 signal from FL1 channel 2 output. | | 2 | CD/DAT3 | SD3_D3_R | ✅ | CD/DAT3 receives the filtered SD data line 3 signal from FL1 channel 3 output. | | 3 | CMD | SD3_CMD_R | ✅ | CMD receives the filtered SD command signal from FL1 channel 4 output. | | 4 | VDD | +VCC3 | ✅ | VDD is correctly connected to the +VCC3 power rail with appropriate decoupling capacitors. | | 5 | CLOCK | SD3_CLK_R | ✅ | CLOCK receives the filtered SD clock signal from FL1 channel 5 output. | | 6 | VSS | GND | ✅ | VSS is correctly connected to the ground plane. | | 7 | DAT0 | SD3_D0_R | ✅ | DAT0 receives the filtered SD data line 0 signal from FL1 channel 6 output. | | 8 | DAT1 | SD3_D1_R | ✅ | DAT1 receives the filtered SD data line 1 signal from FL1 channel 7 output. | | 9 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 10 | CD | SD3_CD_R | ✅ | CD receives the filtered card detect signal from FL1 channel 1 output. | | 11 | GND3 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage. | | 12 | GND4 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage. | | 15 | GND7 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage. | | 16 | GND8 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD, which is the frame ground for the SD card cage. | | 13 | GND5 | FGND-uSD-Front | ✅ | GND5 and GND6 are connected to FGND-uSD-Front, which is the front frame ground for the SD card cage. | | 14 | GND6 | FGND-uSD-Front | ✅ | GND5 and GND6 are connected to FGND-uSD-Front, which is the front frame ground for the SD card cage. | </details> <details> <summary><b>FL1</b> - 3750-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3750-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CH1-IN | SD3_CD# | ✅ | CH1-IN receives the card detect signal SD3_CD# from the host side, which is pulled up to +V1P8S through R182. | | 2 | CH2-IN | SD3_D2 | ✅ | CH2-IN receives SD data line 2 (SD3_D2) from the host side, which is pulled up to +VCC3 through R174. | | 3 | CH3-IN | SD3_D3 | ✅ | CH3-IN receives SD data line 3 (SD3_D3) from the host side, which is pulled up to +VCC3 through R180. | | 4 | CH4-IN | SD3_CMD | ✅ | CH4-IN receives the SD command line (SD3_CMD) from the host side, which is pulled up to +VCC3 through R173. | | 5 | CH5-IN | SD3_CLK | ✅ | CH5-IN receives the SD clock line (SD3_CLK) from the host side, which is pulled up to +VCC3 through R157. | | 6 | CH6-IN | SD3_D0 | ✅ | CH6-IN receives SD data line 0 (SD3_D0) from the host side, which is pulled up to +VCC3 through R156. | | 7 | CH7-IN | SD3_D1 | ✅ | CH7-IN receives SD data line 1 (SD3_D1) from the host side, which is pulled up to +VCC3 through R155. | | 8 | CH8-IN | | ✅ | CH8-IN is not connected, as channel 8 is unused in this design. | | 9 | CH8-OUT | | ✅ | CH8-OUT is not connected, as channel 8 is unused in this design. | | 10 | CH7-OUT | SD3_D1_R | ✅ | CH7-OUT provides the filtered SD data line 1 signal (SD3_D1_R) to the SD card connector pin 8. | | 11 | CH6-OUT | SD3_D0_R | ✅ | CH6-OUT provides the filtered SD data line 0 signal (SD3_D0_R) to the SD card connector pin 7. | | 12 | CH5-OUT | SD3_CLK_R | ✅ | CH5-OUT provides the filtered SD clock signal (SD3_CLK_R) to the SD card connector pin 5. | | 13 | CH4-OUT | SD3_CMD_R | ✅ | CH4-OUT provides the filtered SD command signal (SD3_CMD_R) to the SD card connector pin 3. | | 14 | CH3-OUT | SD3_D3_R | ✅ | CH3-OUT provides the filtered SD data line 3 signal (SD3_D3_R) to the SD card connector pin 2. | | 15 | CH2-OUT | SD3_D2_R | ✅ | CH2-OUT provides the filtered SD data line 2 signal (SD3_D2_R) to the SD card connector pin 1. | | 16 | CH1-OUT | SD3_CD_R | ✅ | CH1-OUT provides the filtered card detect signal (SD3_CD_R) to the SD card connector pin 10. | | 17 | GND_PAD | GND | ✅ | GND_PAD is correctly connected to the ground plane. | </details> <details> <summary><b>R29</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CEC | ✅ | 10kΩ pullup resistor on HDMI_CEC (CEC_A) line. This external pullup is redundant with the TPD12S016's internal 10kΩ pullup to VCCA. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing pullup voltage for HDMI_CEC. | </details> <details> <summary><b>R171</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 2.2kΩ pullup resistor providing enable signal for CT_HPD control pin of TPD12S016, enabling load switch and HPD by default. | | 2 | 2 | HPD_ENB | ✅ | Connected to HPD_ENB net, which controls the CT_HPD pin of TPD12S016. | </details> <details> <summary><b>U2</b> - TPD12S016PW ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/TPD12S016PW) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CEC_A | HDMI_CEC | ✅ | CEC_A pin connected to HDMI_CEC with external 10kΩ pullup to +V1P8S via R29. The external pullup is redundant with the internal 10kΩ pullup to VCCA. | | 2 | SCL_A | HDMI_DDCCLK | ✅ | SCL_A pin connected to HDMI_DDCCLK with external 10kΩ pullup to +V1P8S via R28. The external pullup is redundant with the internal 10kΩ pullup to VCCA. | | 3 | SDA_A | HDMI_DDCDAT | ✅ | SDA_A pin connected to HDMI_DDCDAT with external 10kΩ pullup to +V1P8S via R30. The external pullup is redundant with the internal 10kΩ pullup to VCCA. | | 4 | HPD_A | HDMI_HPD | ✅ | HPD_A pin correctly connected to HDMI_HPD net as hot plug detect output to HDMI controller. | | 5 | LS_OE | LS_OE | ✅ | LS_OE pin correctly connected to LS_OE net with 2.2kΩ pullup to +V1P8S via R172, enabling level shifters by default. | | 6 | GND1 | GND | ✅ | GND1 pin correctly connected to GND. | | 7 | CEC_B | C_HDMI_CEC | ✅ | CEC_B pin correctly connected to C_HDMI_CEC net, which connects to HDMI connector CEC pin. | | 8 | SCL_B | C_HDMI_SCL | ✅ | SCL_B pin correctly connected to C_HDMI_SCL net, which connects to HDMI connector SCL pin. | | 9 | SDA_B | C_HDMI_SDA | ✅ | SDA_B pin correctly connected to C_HDMI_SDA net, which connects to HDMI connector SDA pin. | | 10 | HPD_B | C_HDMI_HPD | ✅ | HPD_B pin correctly connected to C_HDMI_HPD net, which connects to HDMI connector hot plug detect pin. | | 11 | VCC5V | +5VSB | ✅ | VCC5V pin correctly connected to +5VSB with 0.1µF decoupling capacitor C155. | | 12 | CT_HPD | HPD_ENB | ✅ | CT_HPD pin correctly connected to HPD_ENB net with 2.2kΩ pullup to +V1P8S via R171, enabling load switch and HPD by default. | | 13 | 5V_OUT | +HDMI_CRT_VCC | ✅ | 5V_OUT pin correctly connected to +HDMI_CRT_VCC with 4.7µF decoupling capacitor C157 and ferrite bead L7 to HDMI connector 5V pin. | | 14 | GND2 | GND | ✅ | GND2 pin correctly connected to GND. | | 15 | CLK- | HDMI_OUT_CLK_DN | ✅ | CLK- pin correctly connected to HDMI_OUT_CLK_DN, routing through common mode choke L14 and AC coupling capacitor C401 to HDMI controller and connector. | | 16 | CLK+ | HDMI_OUT_CLK_DP | ✅ | CLK+ pin correctly connected to HDMI_OUT_CLK_DP, routing through common mode choke L14 and AC coupling capacitor C400 to HDMI controller and connector. | | 17 | D0- | HDMI_OUT_TX0_DN | ✅ | D0- pin correctly connected to HDMI_OUT_TX0_DN, routing through common mode choke L15 and AC coupling capacitor C403 to HDMI controller and connector. | | 18 | D0+ | HDMI_OUT_TX0_DP | ✅ | D0+ pin correctly connected to HDMI_OUT_TX0_DP, routing through common mode choke L15 and AC coupling capacitor C402 to HDMI controller and connector. | | 19 | GND3 | GND | ✅ | GND3 pin correctly connected to GND. | | 20 | D1- | HDMI_OUT_TX1_DN | ✅ | D1- pin correctly connected to HDMI_OUT_TX1_DN, routing through common mode choke L16 and AC coupling capacitor C405 to HDMI controller and connector. | | 21 | D1+ | HDMI_OUT_TX1_DP | ✅ | D1+ pin correctly connected to HDMI_OUT_TX1_DP, routing through common mode choke L16 and AC coupling capacitor C404 to HDMI controller and connector. | | 22 | D2- | HDMI_OUT_TX2_DN | ✅ | D2- pin correctly connected to HDMI_OUT_TX2_DN, routing through common mode choke L17 and AC coupling capacitor C407 to HDMI controller and connector. | | 23 | D2+ | HDMI_OUT_TX2_DP | ✅ | D2+ pin correctly connected to HDMI_OUT_TX2_DP, routing through common mode choke L17 and AC coupling capacitor C406 to HDMI controller and connector. | | 24 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S with 0.1µF decoupling capacitor C17. | </details> <details> <summary><b>R172</b> - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 2.2kΩ pullup resistor providing enable signal for LS_OE control pin of TPD12S016, enabling level shifters by default. | | 2 | 2 | LS_OE | ✅ | Connected to LS_OE net, which controls the LS_OE pin of TPD12S016. | </details> <details> <summary><b>R30</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCDAT | ✅ | 10kΩ pullup resistor on HDMI_DDCDAT (SDA_A) line. This external pullup is redundant with the TPD12S016's internal 10kΩ pullup to VCCA. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing pullup voltage for HDMI_DDCDAT. | </details> <details> <summary><b>R28</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCCLK | ✅ | 10kΩ pullup resistor on HDMI_DDCCLK (SCL_A) line. This external pullup is redundant with the TPD12S016's internal 10kΩ pullup to VCCA. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing pullup voltage for HDMI_DDCCLK. | </details> <details> <summary><b>L17</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX2_C_DN | ✅ | Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity. | | 3 | IN2 | HDMI_TX2_C_DP | ✅ | Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity. | | 4 | OUT2 | HDMI_OUT_TX2_DP | ✅ | Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity. | | 6 | OUT1 | HDMI_OUT_TX2_DN | ✅ | Common mode choke for HDMI TX2 differential pair. The negative signal (DN) passes through pins 1 (IN1) to 6 (OUT1), and the positive signal (DP) passes through pins 3 (IN2) to 4 (OUT2), maintaining correct differential pair polarity. | </details> <details> <summary><b>C406</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_DP | ✅ | Pin 1 connects to HDMI_TX2_DP, the source side of the AC coupling capacitor for the positive differential signal from the HDMI transmitter. | | 2 | 2 | HDMI_TX2_C_DP | ✅ | Pin 2 connects to HDMI_TX2_C_DP, the output side of the AC coupling capacitor that feeds both the common mode choke L17 pin 3 and termination resistor R802. | </details> <details> <summary><b>C407</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_DN | ✅ | Pin 1 connects to HDMI_TX2_DN, the source side of the AC coupling capacitor for the negative differential signal from the HDMI transmitter. | | 2 | 2 | HDMI_TX2_C_DN | ✅ | Pin 2 connects to HDMI_TX2_C_DN, the output side of the AC coupling capacitor that feeds both the common mode choke L17 pin 1 and termination resistor R801. | </details> <details> <summary><b>R801</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DN | ✅ | Pin 1 connects to HDMI_TX2_C_DN, providing a termination path for the negative differential signal after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Pin 2 connects to HDMI_TERM, which is pulled to ground through Q101 when enabled, creating a termination network for all HDMI differential pairs. | </details> <details> <summary><b>R802</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX2_C_DP | ✅ | Pin 1 connects to HDMI_TX2_C_DP, providing a termination path for the positive differential signal after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Pin 2 connects to HDMI_TERM, which is pulled to ground through Q101 when enabled, creating a termination network for all HDMI differential pairs. | </details> <details> <summary><b>C404</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_DP | ✅ | Pin 1 correctly connected to HDMI_TX1_DP, the source-side positive signal of the TX1 differential pair before AC coupling. | | 2 | 2 | HDMI_TX1_C_DP | ✅ | Pin 2 correctly connected to HDMI_TX1_C_DP, providing AC coupling to the common mode choke input (L16 pin 3) and termination network (R804). | </details> <details> <summary><b>C405</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_DN | ✅ | Pin 1 correctly connected to HDMI_TX1_DN, the source-side negative signal of the TX1 differential pair before AC coupling. | | 2 | 2 | HDMI_TX1_C_DN | ✅ | Pin 2 correctly connected to HDMI_TX1_C_DN, providing AC coupling to the common mode choke input (L16 pin 1) and termination network (R803). | </details> <details> <summary><b>R803</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DN | ✅ | Pin 1 correctly connected to HDMI_TX1_C_DN, providing termination for the negative differential signal after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Pin 2 correctly connected to HDMI_TERM, a common termination point that can be switched to ground via Q101 for power management or mode control. | </details> <details> <summary><b>R804</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX1_C_DP | ✅ | Pin 1 correctly connected to HDMI_TX1_C_DP, providing termination for the positive differential signal after AC coupling. | | 2 | 2 | HDMI_TERM | ✅ | Pin 2 correctly connected to HDMI_TERM, providing symmetric termination with R803 for the TX1 differential pair within the switchable termination network. | </details> <details> <summary><b>L16</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX1_C_DN | ✅ | IN1 pin correctly connected to HDMI_TX1_C_DN, the negative line of the HDMI TX1 differential pair after AC coupling. | | 3 | IN2 | HDMI_TX1_C_DP | ✅ | IN2 pin correctly connected to HDMI_TX1_C_DP, the positive line of the HDMI TX1 differential pair after AC coupling. | | 4 | OUT2 | HDMI_OUT_TX1_DP | ✅ | OUT2 pin correctly connected to HDMI_OUT_TX1_DP, routing the positive line to the ESD protection device U2 and HDMI connector P1. | | 6 | OUT1 | HDMI_OUT_TX1_DN | ✅ | OUT1 pin correctly connected to HDMI_OUT_TX1_DN, routing the negative line to the ESD protection device U2 and HDMI connector P1. | </details> <details> <summary><b>C402</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_DP | ✅ | Pin 1 correctly connected to HDMI_TX0_DP, the source side of the AC coupling capacitor for the positive differential signal. | | 2 | 2 | HDMI_TX0_C_DP | ✅ | Pin 2 correctly connected to HDMI_TX0_C_DP, the output side of the AC coupling capacitor feeding the common mode choke and DC bias restoration network. | </details> <details> <summary><b>C403</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_DN | ✅ | Pin 1 correctly connected to HDMI_TX0_DN, the source side of the AC coupling capacitor for the negative differential signal. | | 2 | 2 | HDMI_TX0_C_DN | ✅ | Pin 2 correctly connected to HDMI_TX0_C_DN, the output side of the AC coupling capacitor feeding the common mode choke and DC bias restoration network. | </details> <details> <summary><b>R805</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DN | ✅ | Pin 1 correctly connected to HDMI_TX0_C_DN, providing DC bias path for the AC-coupled negative differential signal. | | 2 | 2 | HDMI_TERM | ✅ | Pin 2 correctly connected to HDMI_TERM, which provides a switchable ground reference through Q101 for DC biasing. | </details> <details> <summary><b>R806</b> - 1120-0119 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_TX0_C_DP | ✅ | Pin 1 correctly connected to HDMI_TX0_C_DP, providing DC bias path for the AC-coupled positive differential signal. | | 2 | 2 | HDMI_TERM | ✅ | Pin 2 correctly connected to HDMI_TERM, providing symmetric termination with R805. | </details> <details> <summary><b>L15</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX0_C_DN | ✅ | IN1 pin correctly connected to HDMI_TX0_C_DN, the negative line of the TX0 differential pair after AC coupling. | | 3 | IN2 | HDMI_TX0_C_DP | ✅ | IN2 pin correctly connected to HDMI_TX0_C_DP, the positive line of the TX0 differential pair after AC coupling. | | 4 | OUT2 | HDMI_OUT_TX0_DP | ✅ | OUT2 pin correctly connected to HDMI_OUT_TX0_DP, routing the filtered positive signal to the HDMI protection IC and connector. | | 6 | OUT1 | HDMI_OUT_TX0_DN | ✅ | OUT1 pin correctly connected to HDMI_OUT_TX0_DN, routing the filtered negative signal to the HDMI protection IC and connector. | </details> <details> <summary><b>L14</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_CLK_C_DN | ✅ | IN1 pin receives the negative side of the AC-coupled HDMI clock differential pair (HDMI_CLK_C_DN) and passes it through the common mode choke to filter common mode noise. | | 3 | IN2 | HDMI_CLK_C_DP | ✅ | IN2 pin receives the positive side of the AC-coupled HDMI clock differential pair (HDMI_CLK_C_DP) and passes it through the common mode choke to filter common mode noise. | | 4 | OUT2 | HDMI_OUT_CLK_DP | ✅ | OUT2 pin outputs the filtered positive side of the HDMI clock differential pair to the ESD protection IC (U2) and HDMI connector (P1). | | 6 | OUT1 | HDMI_OUT_CLK_DN | ✅ | OUT1 pin outputs the filtered negative side of the HDMI clock differential pair to the ESD protection IC (U2) and HDMI connector (P1). | </details> <details> <summary><b>P1</b> - 158-0004513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/158-0004513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | HPLG | C_HDMI_HPD | ✅ | HPLG (Hot Plug Detect) is correctly connected to C_HDMI_HPD, which routes through U2 (TPD12S016PW) for ESD protection and control. | | 2 | NC | | ✅ | Pin 2 (NC) is not connected, which is correct for micro HDMI Type D connectors where this pin is reserved. | | 3 | DAT2+ | HDMI_OUT_TX2_DP | ✅ | DAT2+ and DAT2- are correctly connected to HDMI_OUT_TX2_DP and HDMI_OUT_TX2_DN respectively, forming the TMDS data channel 2 differential pair with proper polarity. | | 5 | DAT2- | HDMI_OUT_TX2_DN | ✅ | DAT2+ and DAT2- are correctly connected to HDMI_OUT_TX2_DP and HDMI_OUT_TX2_DN respectively, forming the TMDS data channel 2 differential pair with proper polarity. | | 4 | DAT2_S | GND | ✅ | DAT2_S (shield for data pair 2) is correctly connected to GND for proper shielding of the differential pair. | | 6 | DAT1+ | HDMI_OUT_TX1_DP | ✅ | DAT1+ and DAT1- are correctly connected to HDMI_OUT_TX1_DP and HDMI_OUT_TX1_DN respectively, forming the TMDS data channel 1 differential pair with proper polarity. | | 8 | DAT1- | HDMI_OUT_TX1_DN | ✅ | DAT1+ and DAT1- are correctly connected to HDMI_OUT_TX1_DP and HDMI_OUT_TX1_DN respectively, forming the TMDS data channel 1 differential pair with proper polarity. | | 7 | DAT1_S | GND | ✅ | DAT1_S (shield for data pair 1) is correctly connected to GND for proper shielding of the differential pair. | | 9 | DAT0+ | HDMI_OUT_TX0_DP | ✅ | DAT0+ and DAT0- are correctly connected to HDMI_OUT_TX0_DP and HDMI_OUT_TX0_DN respectively, forming the TMDS data channel 0 differential pair with proper polarity. | | 11 | DAT0- | HDMI_OUT_TX0_DN | ✅ | DAT0+ and DAT0- are correctly connected to HDMI_OUT_TX0_DP and HDMI_OUT_TX0_DN respectively, forming the TMDS data channel 0 differential pair with proper polarity. | | 10 | DAT0_S | GND | ✅ | DAT0_S (shield for data pair 0) is correctly connected to GND for proper shielding of the differential pair. | | 12 | CLK+ | HDMI_OUT_CLK_DP | ✅ | CLK+ and CLK- are correctly connected to HDMI_OUT_CLK_DP and HDMI_OUT_CLK_DN respectively, forming the TMDS clock differential pair with proper polarity. | | 14 | CLK- | HDMI_OUT_CLK_DN | ✅ | CLK+ and CLK- are correctly connected to HDMI_OUT_CLK_DP and HDMI_OUT_CLK_DN respectively, forming the TMDS clock differential pair with proper polarity. | | 13 | CLK_S | GND | ✅ | CLK_S (shield for clock pair) is correctly connected to GND for proper shielding of the differential pair. | | 15 | CEC | C_HDMI_CEC | ✅ | CEC (Consumer Electronics Control) is correctly connected to C_HDMI_CEC, which routes through U2 for ESD protection and level shifting, with proper pull-up resistor on the source side. | | 16 | DDC/CEC_GND | GND | ✅ | DDC/CEC_GND is correctly connected to GND, providing the ground reference for DDC and CEC signals. | | 17 | SCL | C_HDMI_SCL | ✅ | SCL (DDC clock) is correctly connected to C_HDMI_SCL, which routes through U2 for ESD protection and level shifting, with proper pull-up resistor on the source side. | | 18 | SDA | C_HDMI_SDA | ✅ | SDA (DDC data) is correctly connected to C_HDMI_SDA, which routes through U2 for ESD protection and level shifting, with proper pull-up resistor on the source side. | | 19 | +5V | D5_0V_HDMI | ✅ | +5V power pin is correctly connected to D5_0V_HDMI, which is sourced from U2 through a ferrite bead for filtering, with proper current limiting and decoupling. | | 20 | MTG1 | GND_EARTH | ✅ | Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground. | | 21 | MTG2 | GND_EARTH | ✅ | Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground. | | 22 | MTG3 | GND_EARTH | ✅ | Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground. | | 23 | MTG4 | GND_EARTH | ✅ | Mounting tabs MTG1-4 are correctly connected to GND_EARTH (chassis ground), with proper high-voltage isolation capacitors between GND_EARTH and signal ground. | </details> <details> <summary><b>C17</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin of decoupling capacitor for +V1P8S rail. | | 2 | 2 | +V1P8S | ✅ | Power pin of decoupling capacitor connected to +V1P8S rail, which supplies U2 VCCA pin. | </details> <details> <summary><b>C155</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin of decoupling capacitor for +5VSB rail. | | 2 | 2 | +5VSB | ✅ | Power pin of decoupling capacitor connected to +5VSB rail, which supplies U2 VCC5V pin. | </details> <details> <summary><b>L7</b> - 126-0001418 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/ferriteBeadInductortypefilter/ENFA0003_PDF_FERRITEBEADINDUCTORTYPEFILTER?lastModifiedDatetime=20250707190934) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BLM18KG221SN1D) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +HDMI_CRT_VCC | ✅ | Input terminal of ferrite bead connected to +HDMI_CRT_VCC from U2 5V_OUT pin. | | 2 | P2 | D5_0V_HDMI | ✅ | Output terminal of ferrite bead connected to D5_0V_HDMI, which supplies 5V to the HDMI connector. | </details> <details> <summary><b>C157</b> - 123-0001144 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +HDMI_CRT_VCC | ✅ | Power pin of bulk decoupling capacitor connected to +HDMI_CRT_VCC, which is the 5V output from U2. | | 2 | 2 | GND | ✅ | Ground pin of bulk decoupling capacitor for +HDMI_CRT_VCC rail. | </details> <details> <summary><b>R809</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $15N747 | ✅ | Connected to Q101 gate through net $15N747, providing the gate drive path. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 power rail, providing gate drive voltage through the 0-ohm resistor. | </details> <details> <summary><b>Q101</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | HDMI_TERM | ✅ | Drain is connected to HDMI_TERM net, which connects to eight 619-ohm termination resistors (R801-R808) for HDMI differential signal pairs. When the MOSFET is ON, it provides a ground path for the termination network. | | G | GATE | $15N747 | ✅ | Gate is connected through R809 (0-ohm resistor) to +VCC3 power rail. This configuration keeps the MOSFET always ON when power is present, making the HDMI termination always active rather than switchable. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, providing the ground reference for the N-channel MOSFET low-side switch. | </details> <details> <summary><b>C16</b> - 123-0004415 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | C16 is a 150pF 1KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection. It is marked DNI (Do Not Install) and is therefore not populated. | | 2 | 2 | GND_EARTH | ✅ | C16 is a 150pF 1KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection. It is marked DNI (Do Not Install) and is therefore not populated. | </details> <details> <summary><b>C161</b> - 2267-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | C161 is a 1000pF 3KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection in the HDMI interface. The connection is correct and appropriate for this application. | | 2 | 2 | GND_EARTH | ✅ | C161 is a 1000pF 3KV Y-capacitor connecting GND to GND_EARTH for EMI filtering and ESD protection in the HDMI interface. The connection is correct and appropriate for this application. | </details> <details> <summary><b>U32</b> - AP2172MPG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP2162_72.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/AP2172MPG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net, providing the return path for the device. | | 2 | IN | +USBVCC | ✅ | Input power pin correctly connected to +USBVCC, which is derived from +5VSB through ferrite bead FB13 with appropriate bypass capacitors C92, C93, and C94. | | 3 | EN1 | USB_HOST_EN0 | ✅ | Enable input for channel 1 correctly connected to USB_HOST_EN0, which is driven by level translator U4 from SOC_USB_HOST_EN0 signal. Pull-down resistor R112 is marked DNI, indicating active drive is used. | | 4 | EN2 | USB_HOST_EN1 | ✅ | Enable input for channel 2 correctly connected to USB_HOST_EN1, which is driven by level translator U4 from SOC_USB_HOST_EN1 signal. Pull-down resistor R114 is marked DNI, indicating active drive is used. | | 5 | OC2# | SOC_USB_HOST_OC1 | ✅ | Overcurrent/fault flag output for channel 2 correctly connected to SOC_USB_HOST_OC1. This open-drain output reports over-current and over-temperature conditions for OUT2/OUTB. External pull-up resistor may be required but could be internal to SOC. | | 6 | OUTB | USBP2 | ✅ | Output power pin for channel 2 correctly connected to USBP2, which feeds VBUS2 through ferrite bead L2. VBUS2 has appropriate bypass capacitors (C103, C70, C234) and connects to USB port B. | | 7 | OUTA | USBP1 | ✅ | Output power pin for channel 1 correctly connected to USBP1, which feeds VBUS1 through ferrite bead L1. VBUS1 has appropriate bypass capacitors (C91, C82, C235) and connects to USB port A. | | 8 | OC1# | SOC_USB_HOST_OC0 | ✅ | Overcurrent/fault flag output for channel 1 correctly connected to SOC_USB_HOST_OC0. This open-drain output reports over-current and over-temperature conditions for OUT1/OUTA. External pull-up resistor may be required but could be internal to SOC. | | 9 | GND_PAD | GND | ✅ | Exposed pad correctly connected to GND for thermal and electrical grounding as recommended by the datasheet. | </details> <details> <summary><b>U4</b> - NTS0102GT ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 7 | VCCB | +USBVCC | ❌ | <details><summary>VCCB is connected to +USBVCC (5V), which exceeds the NTS0102GT maximum rating of 3.6V specified in the component attributes. This is a critical design error that violates the device's operating voltage range and could damage the device.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="41.02,68.01,48.52,75.51" aspect-ratio="1.29" } <ul><li>Pin 7 (VCCB) is the B-side supply voltage pin for the level translator <em>(reasoning)</em></li><li>Pin 7 is connected to +USBVCC <em>(from schematic)</em></li><li>+USBVCC is derived from +5VSB through ferrite bead FB13 <em>(from schematic)</em></li><li>+5VSB is a standard 5V standby supply based on PC power supply naming conventions <em>(reasoning)</em></li><li>A ferrite bead provides high-frequency impedance but is essentially a DC short, so +USBVCC is approximately 5V at DC <em>(reasoning)</em></li><li>U32 (AP2172MPG) USB power switch has input voltage range of 2.7-5.5V and its IN pin connects to +USBVCC, confirming +USBVCC is a 5V rail <em>(from schematic)</em></li><li>The component voltage rating is specified as 1.2-3.6V in the VOLTAGE attribute <em>(from schematic)</em></li><li>VCCB is the B-side reference supply voltage and must be within the 1.2-3.6V range per the component specification <em>(reasoning)</em></li><li>Connecting VCCB to 5V exceeds the maximum operating voltage of 3.6V by 1.4V <em>(reasoning)</em></li><li>The NTS0102GT part number with &#x27;GT&#x27; suffix indicates the standard variant with 3.6V maximum on both VCCA and VCCB, not the &#x27;GF&#x27; variant which supports up to 5.5V on VCCB <em>(reasoning)</em></li><li>Operating VCCB above its maximum rating can cause permanent damage to the device or unreliable operation <em>(reasoning)</em></li><li>VCCB should be connected to a 3.3V supply instead of +USBVCC (5V) <em>(reasoning)</em></li><li>Alternatively, a 5V-tolerant level translator such as NTS0102GF or SN74LVC2T45 (which supports VCCB up to 5.5V) should be used instead of NTS0102GT <em>(reasoning)</em></li><li>Decoupling capacitors C92, C93, C94 (0.1uF) are present on the +USBVCC net for power supply filtering <em>(from schematic)</em></li></ul></details> | | 1 | B2 | USB_HOST_EN0 | ✅ | B2 output correctly connected to USB_HOST_EN0, which drives the enable input of USB power switch U32. | | 2 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 3 | VCCA | +V1P8A | ✅ | VCCA correctly connected to +V1P8A (1.8V) supply, which is within the specified 1.2-3.6V range. | | 4 | A2 | SOC_USB_HOST_EN0 | ✅ | A2 input correctly connected to SOC_USB_HOST_EN0 signal from the SOC. | | 5 | A1 | SOC_USB_HOST_EN1 | ✅ | A1 input correctly connected to SOC_USB_HOST_EN1 signal from the SOC. | | 6 | OE | USB_HOST_BUFF_ENB | ✅ | OE pin correctly connected to USB_HOST_BUFF_ENB with pullup to +V1P8A, enabling the translator by default. | | 8 | B1 | USB_HOST_EN1 | ✅ | B1 output correctly connected to USB_HOST_EN1, which drives the enable input of USB power switch U32. | </details> <details> <summary><b>U29</b> - TPD4USB30 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/TPD4USB30) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D1+ | USB3_TX0P_C | ✅ | D1+ pin connected to USB3_TX0P_C, providing ESD protection for the positive USB3 transmit signal. This pin protects the signal line going to the connector. | | 2 | D1- | USB3_TX0N_C | ✅ | D1- pin connected to USB3_TX0N_C, providing ESD protection for the negative USB3 transmit signal. This pin protects the signal line going to the connector. | | 3 | GND1 | GND | ✅ | GND1 pin correctly connected to GND, providing ground reference for the ESD protection device. | | 4 | D2+ | USB3_RX0P_C | ✅ | D2+ pin connected to USB3_RX0P_C, providing ESD protection for the positive USB3 receive signal. This pin protects the signal line coming from the connector. | | 5 | D2- | USB3_RX0N_C | ✅ | D2- pin connected to USB3_RX0N_C, providing ESD protection for the negative USB3 receive signal. This pin protects the signal line coming from the connector. | | 6 | NC4 | USB3_RX0N_C | ✅ | NC4 pin connected to USB3_RX0N_C, the same net as D2- (pin 5). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration. | | 7 | NC3 | USB3_RX0P_C | ✅ | NC3 pin connected to USB3_RX0P_C, the same net as D2+ (pin 4). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration. | | 8 | GND2 | GND | ✅ | GND2 pin correctly connected to GND, providing ground reference for the ESD protection device. | | 9 | NC2 | USB3_TX0N_C | ✅ | NC2 pin connected to USB3_TX0N_C, the same net as D1- (pin 2). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration. | | 10 | NC1 | USB3_TX0P_C | ✅ | NC1 pin connected to USB3_TX0P_C, the same net as D1+ (pin 1). While labeled as no-connect, this connection may provide enhanced ESD protection or be part of the device's intended configuration. | </details> <details> <summary><b>CHOKE1</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_RX0N_C | ✅ | IN1 pin connected to USB3_RX0N_C, the negative receive signal from the ESD protection device U29. This is the input side of the common mode choke for the negative differential signal. | | 3 | IN2 | USB3_RX0P_C | ✅ | IN2 pin connected to USB3_RX0P_C, the positive receive signal from the ESD protection device U29. This is the input side of the common mode choke for the positive differential signal. | | 4 | OUT2 | USB3_RXP0 | ✅ | OUT2 pin connected to USB3_RXP0, the positive receive signal going to the SOC. This is the output side of the common mode choke for the positive differential signal. | | 6 | OUT1 | USB3_RXN0 | ✅ | OUT1 pin connected to USB3_RXN0, the negative receive signal going to the SOC. This is the output side of the common mode choke for the negative differential signal. | </details> <details> <summary><b>CHOKE2</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_TX0P-R | ✅ | IN1 pin connected to USB3_TX0P-R, the positive transmit signal after AC coupling from the SOC. This is the input side of the common mode choke for the positive differential signal. | | 3 | IN2 | USB3_TX0N-R | ✅ | IN2 pin connected to USB3_TX0N-R, the negative transmit signal after AC coupling from the SOC. This is the input side of the common mode choke for the negative differential signal. | | 4 | OUT2 | USB3_TX0N_C | ✅ | OUT2 pin connected to USB3_TX0N_C, the negative transmit signal going to the ESD protection and connector. This is the output side of the common mode choke for the negative differential signal. | | 6 | OUT1 | USB3_TX0P_C | ✅ | OUT1 pin connected to USB3_TX0P_C, the positive transmit signal going to the ESD protection and connector. This is the output side of the common mode choke for the positive differential signal. | </details> <details> <summary><b>CHOKE4</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN0 | ✅ | IN1 is connected to USB_DN0, which is the USB 2.0 D- signal from the SOC. This is the input side of one winding of the common mode choke. | | 3 | IN2 | USB_DP0 | ✅ | IN2 is connected to USB_DP0, which is the USB 2.0 D+ signal from the SOC. This is the input side of the second winding of the common mode choke. | | 4 | OUT2 | USB_H0 | ✅ | OUT2 is connected to USB_H0, which routes to the ESD protection device (U9) and USB connector. This is the output of the D+ signal path. | | 6 | OUT1 | USB_L0 | ✅ | OUT1 is connected to USB_L0, which routes to the ESD protection device (U9) and USB connector. This is the output of the D- signal path. | </details> <details> <summary><b>U9</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H0 | ✅ | D+ pin is connected to USB_H0, providing ESD protection for the USB 2.0 D+ data line. The connection is correct. | | 2 | D- | USB_L0 | ✅ | D- pin is connected to USB_L0, providing ESD protection for the USB 2.0 D- data line. The connection is correct. | | 3 | ID | | ✅ | ID pin is left unconnected, which is acceptable per the datasheet for applications where the ID pin is not used. | | 4 | GND | GND | ✅ | GND pin is connected to the GND net, providing the ground reference for the ESD protection device. The connection is correct. | | 5 | NC | | ✅ | NC pin is not connected, which is correct as this pin is not internally connected per the datasheet. | | 6 | VBUS | VBUS1 | ✅ | VBUS pin is connected to VBUS1, providing ESD protection for the USB power line. The connection is correct. | </details> <details> <summary><b>CHOKE3</b> - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN1 | ✅ | IN1 pin receives USB_DN1 signal, which is the negative differential USB data signal for port 1. | | 3 | IN2 | USB_DP1 | ✅ | IN2 pin receives USB_DP1 signal, which is the positive differential USB data signal for port 1. | | 4 | OUT2 | USB_H1 | ✅ | OUT2 pin outputs the filtered USB_H1 signal (D+) to the ESD protection device U8 and USB connector. | | 6 | OUT1 | USB_L1 | ✅ | OUT1 pin outputs the filtered USB_L1 signal (D-) to the ESD protection device U8 and USB connector. | </details> <details> <summary><b>U8</b> - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H1 | ✅ | D+ pin provides ESD protection for the USB D+ data line (USB_H1) for port 1. | | 2 | D- | USB_L1 | ✅ | D- pin provides ESD protection for the USB D- data line (USB_L1) for port 1. | | 3 | ID | | ✅ | ID pin is correctly left floating as it is not needed for this USB host port application. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the ground plane. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as specified in the datasheet. | | 6 | VBUS | VBUS2 | ✅ | VBUS pin provides ESD protection for the USB power line (VBUS2) for port 1. | </details> <details> <summary><b>USB1</b> - 258-0004503 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0004503) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUSA | VBUS1 | ✅ | VBUSA provides power to USB port A. Connected to VBUS1 with proper power switching, filtering, and ESD protection. | | 2 | DA- | USB_L0 | ✅ | DA- is the USB 2.0 D- signal for port A. Connected to USB_L0 with common mode filtering and ESD protection. | | 3 | DA+ | USB_H0 | ✅ | DA+ is the USB 2.0 D+ signal for port A. Connected to USB_H0 with common mode filtering and ESD protection. | | 4 | GNDA | GND | ✅ | GNDA is the ground connection for USB port A, correctly connected to system ground. | | 5 | SSRX- | USB3_RX0N_C | ✅ | SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected to USB3_RX0N_C with common mode filtering and ESD protection. | | 6 | SSRX+ | USB3_RX0P_C | ✅ | SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected to USB3_RX0P_C with common mode filtering and ESD protection. | | 7 | GND_DRAIN | GND | ✅ | GND_DRAIN is a ground drain connection, correctly connected to system ground. | | 8 | SSTX- | USB3_TX0N_C | ✅ | SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected to USB3_TX0N_C with AC coupling, common mode filtering, and ESD protection. | | 9 | SSTX+ | USB3_TX0P_C | ✅ | SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected to USB3_TX0P_C with AC coupling, common mode filtering, and ESD protection. | | 10 | VBUSB | VBUS2 | ✅ | VBUSB provides power to USB port B. Connected to VBUS2 with proper power switching, filtering, and ESD protection. | | 11 | DB- | USB_L1 | ✅ | DB- is the USB 2.0 D- signal for port B. Connected to USB_L1 with common mode filtering and ESD protection. | | 12 | DB+ | USB_H1 | ✅ | DB+ is the USB 2.0 D+ signal for port B. Connected to USB_H1 with common mode filtering and ESD protection. | | 13 | GNDB | GND | ✅ | GNDB is the ground connection for USB port B, correctly connected to system ground. | | MH1 | SHIELD1 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground. | | MH2 | SHIELD2 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground. | | MH3 | SHIELD3 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground. | | MH4 | SHIELD4 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI/ESD protection. An optional high-voltage capacitor C211 (DNI) provides isolation from main ground. | </details> <details> <summary><b>FB13</b> - 3044-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3044-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input pin connected to +5VSB power rail, providing power source for USB circuitry. | | 2 | 2 | +USBVCC | ✅ | Output pin connected to +USBVCC rail, supplying filtered power to USB power switch and level translator. | </details> <details> <summary><b>L1</b> - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP1 | ✅ | Input pin connected to USBP1, the output of USB power switch channel A. | | 2 | 2 | VBUS1 | ✅ | Output pin connected to VBUS1, supplying filtered power to USB connector port A and ESD protection. | </details> <details> <summary><b>L2</b> - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP2 | ✅ | Input pin connected to USBP2, the output of USB power switch channel B. | | 2 | 2 | VBUS2 | ✅ | Output pin connected to VBUS2, supplying filtered power to USB connector port B and ESD protection. | </details> <details> <summary><b>J10</b> - 158-0004534 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/158-0004534) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 2 | 2 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 13 | 13 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 14 | 14 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 25 | 25 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 26 | 26 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 37 | 37 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 38 | 38 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 49 | 49 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 50 | 50 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 59 | 59 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 60 | 60 | GND | ✅ | Ground pins connected to GND net. Multiple ground pins provide good current return paths and reduce ground impedance. | | 3 | 3 | mSATA_TX_P | ✅ | mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5) for mSATA interface. | | 5 | 5 | mSATA_TX_N | ✅ | mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5) for mSATA interface. | | 4 | 4 | mSATA_RX_P | ✅ | mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6) for mSATA interface. | | 6 | 6 | mSATA_RX_N | ✅ | mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6) for mSATA interface. | | 7 | 7 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 8 | 8 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 19 | 19 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 20 | 20 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 31 | 31 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 32 | 32 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 43 | 43 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 44 | 44 | +5VSB | ✅ | 5V standby power pins connected to +5VSB net. Multiple power pins provide adequate current capacity and reduce power distribution impedance. | | 9 | 9 | mPCIE_REFCLK_P | ✅ | mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11) with test points TP19 and TP20. | | 11 | 11 | mPCIE_REFCLK_N | ✅ | mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11) with test points TP19 and TP20. | | 10 | 10 | USB_HOST_DP | ✅ | USB host differential pair (DP on pin 10, DN on pin 12) for USB interface. | | 12 | 12 | USB_HOST_DN | ✅ | USB host differential pair (DP on pin 10, DN on pin 12) for USB interface. | | 15 | 15 | mPCIE_TX_P | ✅ | mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17) with test points TP21 and TP22. | | 17 | 17 | mPCIE_TX_N | ✅ | mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17) with test points TP21 and TP22. | | 16 | 16 | mPCIE_RX_N | ✅ | mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18) for PCB routing ease, with test points TP24 and TP23. | | 18 | 18 | mPCIE_RX_P | ✅ | mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18) for PCB routing ease, with test points TP24 and TP23. | | 21 | 21 | I2C6_SCL | ✅ | I2C6 clock line with 10K ohm pull-up resistor R13 to +V1P8S. | | 22 | 22 | mPCIE_WAKEB | ✅ | mPCIE wake signal (active low) for power management. | | 23 | 23 | I2C6_SDA | ✅ | I2C6 data line with 10K ohm pull-up resistor R14 to +V1P8S. | | 24 | 24 | mPCIe_CLKREQ3_B | ✅ | mPCIE clock request signal (active low) for power management. | | 27 | 27 | EXP_GPIO1 | ✅ | Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O. | | 28 | 28 | EXP_GPIO3 | ✅ | Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O. | | 29 | 29 | EXP_GPIO2 | ✅ | Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O. | | 30 | 30 | EXP_GPIO4 | ✅ | Expansion GPIO signals (GPIO1 on pin 27, GPIO3 on pin 28, GPIO2 on pin 29, GPIO4 on pin 30) for general-purpose I/O. | | 33 | 33 | XDP_H_OBSDATA_A1 | ✅ | XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface. | | 34 | 34 | XDP_H_OBSDATA_A0 | ✅ | XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface. | | 35 | 35 | XDP_H_OBSDATA_A2 | ✅ | XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface. | | 36 | 36 | XDP_H_OBSDATA_A3 | ✅ | XDP observation data signals (OBSDATA_A1 on pin 33, OBSDATA_A0 on pin 34, OBSDATA_A2 on pin 35, OBSDATA_A3 on pin 36) for debug interface. | | 39 | 39 | XDP_H_PRDYB | ✅ | XDP probe ready signal (active low) for debug interface handshaking. | | 40 | 40 | XDP_H_PREQB_PB | ✅ | XDP probe request signal (active low) with 200 ohm pull-up to +V1P8A via R3, buffered by U1 to create XDP_H_PREQB. | | 41 | 41 | HOOK0 | ✅ | Hook signal 0 connected via 1K ohm resistor R15 to PMC_RSMRST for debug/test access. | | 42 | 42 | HOOK1 | ✅ | Hook signal 1 connected via 0 ohm resistor R5 to FP_PWRBTN, with optional 4.7K pull-down R4 (DNI). | | 45 | 45 | HOOK2 | ✅ | Hook signal 2 connected via 1K ohm resistor R16 to PMC_CORE_PWROK for debug/test access. | | 46 | 46 | PMC_RSTBTN | ✅ | PMC reset button signal with 1K ohm pull-up to +V1P8S via R6 and 0.1uF filter capacitor C1 to ground. | | 47 | 47 | HOOK6 | ✅ | Hook signal 6 connected via 1K ohm resistor R17 to PMC_PLTRST_R_V1P8 for debug/test access. | | 48 | 48 | ILB_RTC_TESTB | ✅ | RTC test signal (active low) with 1K ohm pull-up to +RTCVCC via R7 and 1uF filter capacitor C2 to ground. | | 51 | 51 | HOOK4 | ✅ | Hook signal 4 connected via 0 ohm resistor R18 to +3VSB, providing 3.3V standby power access. | | 52 | 52 | XDP_H_TRSTB | ✅ | XDP test reset signal (active low) for JTAG-style debug interface. | | 53 | 53 | HOOK5 | ✅ | Hook signal 5 connected via 0 ohm resistor R20 to +V1P8S, providing 1.8V standby power access. | | 54 | 54 | XDP_H_TCK | ✅ | XDP test clock signal for JTAG-style debug interface. | | 55 | 55 | +V1P8A | ✅ | 1.8V analog power supply with 0.1uF decoupling capacitor C5 to ground. | | 56 | 56 | XDP_H_TMS | ✅ | XDP test mode select signal for JTAG-style debug interface. | | 57 | 57 | XDP_H_TDO | ✅ | XDP test data out signal with 51 ohm resistor R21 to +V1P8A for termination or weak pull-up. | | 58 | 58 | XDP_H_TDI | ✅ | XDP test data in signal for JTAG-style debug interface. | </details> <details> <summary><b>U1</b> - SN74AUP1G34 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](http://www.ti.com/lit/gpn/SN74AUP1G34) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/SN74AUP1G34) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin is correctly left unconnected. | | 2 | A | XDP_H_PREQB_PB | ✅ | Input pin A is correctly connected to XDP_H_PREQB_PB signal with a 200 ohm pull-up resistor (R3) to +V1P8A. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | XDP_H_PREQB | ✅ | Output pin Y is correctly connected to the XDP_H_PREQB net. | | 5 | VCC | +V1P8A | ✅ | VCC pin is correctly connected to +V1P8A (1.8V supply) with bypass capacitor C5 (0.1µF) present. | </details> <details> <summary><b>R3</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XDP_H_PREQB_PB | ✅ | Connected to XDP_H_PREQB_PB, forming a pull-up resistor for U1 input pin 2. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A, completing the pull-up resistor configuration. | </details> <details> <summary><b>R21</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A, forming a pull-up resistor for the XDP_H_TDO signal. | | 2 | 2 | XDP_H_TDO | ✅ | Connected to XDP_H_TDO signal. The 51 ohm pull-up value is unusually low for a JTAG TDO signal but may be intentional for signal integrity in the XDP debug interface. | </details> <details> <summary><b>R14</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SDA | ✅ | Connected to I2C6_SDA signal line, providing pull-up functionality to +V1P8S through the 10K resistor. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing 1.8V pull-up voltage for the I2C SDA line. | </details> <details> <summary><b>R13</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SCL | ✅ | Connected to I2C6_SCL signal line, providing pull-up functionality to +V1P8S through the 10K resistor. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing 1.8V pull-up voltage for the I2C SCL line. | </details> <details> <summary><b>C1</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal for filtering and debouncing of the reset button input. | | 2 | 2 | GND | ✅ | Connected to GND, providing the return path for the filter capacitor. | </details> <details> <summary><b>R6</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal, providing pull-up function for the reset button input. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing the pull-up voltage for the reset button circuit. | </details> <details> <summary><b>C2</b> - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to GND for the bypass/filter capacitor function. | | 2 | 2 | ILB_RTC_TESTB | ✅ | Pin 2 is correctly connected to ILB_RTC_TESTB signal for filtering purposes. | </details> <details> <summary><b>R7</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | ILB_RTC_TESTB | ✅ | Pin 1 is correctly connected to ILB_RTC_TESTB signal as part of a pull-up resistor configuration. | | 2 | 2 | +RTCVCC | ✅ | Pin 2 is correctly connected to +RTCVCC to provide pull-up for the ILB_RTC_TESTB signal. | </details> <details> <summary><b>C5</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to GND, providing the ground reference for this decoupling capacitor. | | 2 | 2 | +V1P8A | ✅ | Pin 2 is correctly connected to +V1P8A, providing decoupling for the 1.8V analog power rail. | </details> <details> <summary><b>U42</b> - WGI210AT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4300-0071) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | LAN_PWR_GOOD | $18N3538 | ✅ | LAN_PWR_GOOD output signal pulled high through R828 (10K) to +3VSB_LAN, indicating power supply status. | | 2 | NC_SI_CLK_IN | $18N3372 | ✅ | NC_SI_CLK_IN pulled to ground through R837 (1K), disabling the network controller serial interface clock input. | | 3 | NC_SI_CRS_DV | $18N3374 | ✅ | NC_SI_CRS_DV pulled to ground through R838 (1K), disabling the carrier sense/data valid signal for the serial interface. | | 4 | JTAG_TDO | | ✅ | JTAG_TDO left unconnected, which is acceptable when JTAG debugging is not required. | | 5 | NC_SI_RXD1 | $18N3305 | ✅ | NC_SI_RXD1 pulled high through R826 (10K) to +3VSB_LAN, disabling receive data bit 1 of the serial interface. | | 6 | NC_SI_RXD0 | $18N3303 | ✅ | NC_SI_RXD0 pulled high through R825 (10K) to +3VSB_LAN, disabling receive data bit 0 of the serial interface. | | 7 | NC_SI_TX_EN | $18N3376 | ✅ | NC_SI_TX_EN pulled to ground through R839 (1K), disabling transmit enable for the serial interface. | | 8 | NC_SI_TXD1 | $18N3301 | ✅ | NC_SI_TXD1 pulled high through R824 (10K) to +3VSB_LAN, disabling transmit data bit 1 of the serial interface. | | 9 | NC_SI_TXD0 | $18N3299 | ✅ | NC_SI_TXD0 pulled high through R823 (10K) to +3VSB_LAN, disabling transmit data bit 0 of the serial interface. | | 10 | VDD3P3_10 | +3VSB_LAN | ✅ | VDD3P3_10 connected to +3VSB_LAN power rail with appropriate decoupling capacitors. | | 11 | VDD0P9_11 | +0V9_LAN | ✅ | VDD0P9_11 connected to +0V9_LAN power rail with appropriate decoupling capacitors. | | 12 | NVM_SI | $18N2399 | ✅ | NVM_SI connected to SPI flash U43 pin 5 (SI) through series resistor R832 (33.2Ω) for signal integrity. | | 13 | NVM_SK | $18N2397 | ✅ | NVM_SK connected to SPI flash U43 pin 6 (SCK) through series resistor R834 (33.2Ω) for signal integrity. | | 14 | NVM_SO | $18N3554 | ✅ | NVM_SO connected to SPI flash U43 pin 2 (SO) through series resistor R833 (33.2Ω) for signal integrity. | | 15 | NVM_CS_N | $18N2395 | ✅ | NVM_CS_N connected to SPI flash U43 pin 1 (CS#) through series resistor R835 (33.2Ω) for signal integrity. | | 16 | PE_WAKE_N | PMC_PCIE_WAKE | ✅ | PE_WAKE_N connected to PMC_PCIE_WAKE for PCIe wake signaling to platform management controller. | | 17 | PE_RST_N | PMC_PLTRST_L | ✅ | PE_RST_N connected to PMC_PLTRST_L for PCIe reset control from platform. | | 18 | JTAG_TMS | $18N3293 | ✅ | JTAG_TMS pulled high through R820 (10K) to +3VSB_LAN, which is standard for JTAG interfaces. | | 19 | JTAG_CLK | $18N3295 | ✅ | JTAG_CLK pulled high through R821 (10K) to +3VSB_LAN, which is standard for JTAG interfaces. | | 20 | PE_TXN | PCIE_C_RXP2 | ✅ | PE_TXN and PE_TXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_TXN connects to PCIE_C_RXP2 and PE_TXP connects to PCIE_C_RXN2. | | 21 | PE_TXP | PCIE_C_RXN2 | ✅ | PE_TXN and PE_TXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_TXN connects to PCIE_C_RXP2 and PE_TXP connects to PCIE_C_RXN2. | | 22 | NC/INTVCC | | ✅ | NC/INTVCC pin left unconnected, which is acceptable if this is a no-connect or internal voltage pin. | | 23 | PE_RXN | PCIE_C_TXP2 | ✅ | PE_RXN and PE_RXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_RXN connects to PCIE_C_TXP2 and PE_RXP connects to PCIE_C_TXN2. | | 24 | PE_RXP | PCIE_C_TXN2 | ✅ | PE_RXN and PE_RXP are intentionally swapped (polarity inverted) as documented in schematic note for PCIe layout optimization. PE_RXN connects to PCIE_C_TXP2 and PE_RXP connects to PCIE_C_TXN2. | | 25 | PECLK_N | PCIE_CLK-N2 | ✅ | PECLK_N connected to PCIE_CLK-N2 for PCIe reference clock negative signal with test point TP17. | | 26 | PECLK_P | PCIE_CLK-P2 | ✅ | PECLK_P connected to PCIE_CLK-P2 for PCIe reference clock positive signal with test point TP18. | | 27 | VDD3P3_27 | +3VSB_LAN | ✅ | VDD3P3_27 connected to +3VSB_LAN power rail with appropriate decoupling capacitors. | | 28 | DEV_OFF_N | $18N3540 | ✅ | DEV_OFF_N pulled high through R827 (10K) to +3VSB_LAN, keeping device enabled by default. | | 29 | JTAG_TDI | $18N3297 | ✅ | JTAG_TDI pulled high through R822 (10K) to +3VSB_LAN, which is standard for JTAG interfaces. | | 30 | LED1 | LAN-LED1 | ✅ | LED1 connected to LAN-LED1 which drives LINK-LED-N through R843 (301Ω) to J11 LED indicator. | | 31 | LED0 | LAN-LED0 | ✅ | LED0 connected to LAN-LED0 which drives LED indicator on J11 pin 11 with filtering capacitor C431. | | 32 | VDD0P9_32 | +0V9_LAN | ✅ | VDD0P9_32 connected to +0V9_LAN power rail with appropriate decoupling capacitors. | | 33 | LED2 | LAN-LED2 | ✅ | LED2 connected to LAN-LED2 which drives 1G-LED-N through R844 (301Ω) to J11 LED indicator. | | 34 | SMB_CLK | LAN-SMB-CLK | ✅ | SMB_CLK connected to LAN-SMB-CLK for SMBus clock signal used in system management. | | 35 | SMB_ALRT_N | LAN-SMB-ALERT# | ✅ | SMB_ALRT_N connected to LAN-SMB-ALERT# for SMBus alert signaling (active low). | | 36 | SMB_DATA | LAN-SMB-DATA | ✅ | SMB_DATA connected to LAN-SMB-DATA for SMBus data signal used in system management. | | 37 | CBOT | $18N2590 | ✅ | CBOT and CTOP connected through C425 (0.039uF) forming an oscillator or PLL tuning network. | | 40 | CTOP | $18N2588 | ✅ | CBOT and CTOP connected through C425 (0.039uF) forming an oscillator or PLL tuning network. | | 38 | VDD0P9_OUT | +0V9_LAN | ✅ | VDD0P9_OUT connected to +0V9_LAN rail, providing internal 0.9V regulator output to supply other 0.9V pins. | | 39 | VDD1P5_OUT | +1V5_LAN | ✅ | VDD1P5_OUT connected to +1V5_LAN rail, providing internal 1.5V regulator output to supply other 1.5V pins. | | 41 | VDD3P3_41 | +3VSB_LAN | ✅ | VDD3P3_41 connected to +3VSB_LAN power rail with appropriate decoupling capacitors. | | 42 | VDD0P9_42 | +0V9_LAN | ✅ | VDD0P9_42 connected to +0V9_LAN power rail with appropriate decoupling capacitors. | | 43 | NC_SI_ARB_IN | | ✅ | NC_SI_ARB_IN left unconnected, which is acceptable as the serial interface arbitration feature is not being used. | | 44 | NC_SI_ARB_OUT | | ✅ | NC_SI_ARB_OUT left unconnected, which is acceptable as the serial interface arbitration feature is not being used. | | 45 | XTAL2 | LAN_XTAL2 | ✅ | XTAL2 connected to 25MHz crystal X1 pin 1 with 27pF load capacitor C253 to ground. | | 46 | XTAL1 | LAN_XTAL1 | ✅ | XTAL1 connected to 25MHz crystal X1 pin 3 with 27pF load capacitor C252 to ground. | | 47 | VDD1P5_47 | +1V5_LAN | ✅ | VDD1P5_47 connected to +1V5_LAN power rail with appropriate decoupling capacitors. | | 48 | RSET | LAN_RSET | ✅ | RSET connected to ground through R836 (4.99K) to set internal reference currents and voltages. | | 49 | MDI_MINUS3/SER_N | MDI_N3 | ✅ | MDI_MINUS3 connected to MDI_N3 differential pair negative signal, routing to RJ45 connector J11 pin 10. | | 50 | MDI_PLUS3/SER_P | MDI_P3 | ✅ | MDI_PLUS3 connected to MDI_P3 differential pair positive signal, routing to RJ45 connector J11 pin 9. | | 51 | VDD3P3_51 | +3VSB_LAN | ✅ | VDD3P3_51 connected to +3VSB_LAN power rail with appropriate decoupling capacitors. | | 52 | MDI_MINUS2/SET_N | MDI_N2 | ✅ | MDI_MINUS2 connected to MDI_N2 differential pair negative signal, routing to RJ45 connector J11 pin 8. | | 53 | MDI_PLUS2 | MDI_P2 | ✅ | MDI_PLUS2 connected to MDI_P2 differential pair positive signal, routing to RJ45 connector J11 pin 7. | | 54 | MDI_MINUS1/SRDS_SIG_DET | MDI_N1 | ✅ | MDI_MINUS1 connected to MDI_N1 differential pair negative signal, routing to RJ45 connector J11 pin 4. | | 55 | MDI_PLUS1/SFP_I2C_CLK | MDI_P1 | ✅ | MDI_PLUS1 connected to MDI_P1 differential pair positive signal, routing to RJ45 connector J11 pin 3. | | 56 | VDD1P5_56 | +1V5_LAN | ✅ | VDD1P5_56 connected to +1V5_LAN power rail with appropriate decoupling capacitors. | | 57 | MDI_MINUS0/SFP_I2C_DATA | MDI_N0 | ✅ | MDI_MINUS0 connected to MDI_N0 differential pair negative signal, routing to RJ45 connector J11 pin 2. | | 58 | MDI_PLUS0/NC | MDI_P0 | ✅ | MDI_PLUS0 connected to MDI_P0 differential pair positive signal, routing to RJ45 connector J11 pin 1. | | 59 | VDD0P9_59 | +0V9_LAN | ✅ | VDD0P9_59 connected to +0V9_LAN power rail with appropriate decoupling capacitors. | | 60 | SDP3 | | ✅ | SDP3 left unconnected, which is acceptable for unused software-defined pins. | | 61 | SDP1/PCIE_DIS | | ✅ | SDP1/PCIE_DIS left unconnected, which enables PCIe functionality by default. | | 62 | SDP2 | | ✅ | SDP2 left unconnected, which is acceptable for unused software-defined pins. | | 63 | SDP0 | | ✅ | SDP0 left unconnected, which is acceptable for unused software-defined pins. | | 64 | VDD3P3_64 | +3VSB_LAN | ✅ | VDD3P3_64 connected to +3VSB_LAN power rail with appropriate decoupling capacitors. | | 65 | GND_PAD | GND | ✅ | GND_PAD connected to GND for thermal and electrical grounding of the package. | </details> <details> <summary><b>R848</b> - 1120-0359 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | R848 (33.2kΩ) provides a weak pull-up on the SI (Serial Input) line of the SPI flash to ensure a defined logic state when the line is not actively driven. | | 2 | 2 | $18N2435 | ✅ | R848 (33.2kΩ) provides a weak pull-up on the SI (Serial Input) line of the SPI flash to ensure a defined logic state when the line is not actively driven. | </details> <details> <summary><b>U43</b> - AT25DF081A-SSH ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25df081a-datasheet?language=en) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4356-0082) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | $18N2439 | ✅ | CS# (Chip Select) is correctly connected to the Ethernet controller U42 pin 15 (NVM_CS_N) through series resistor R835 (33.2Ω). | | 2 | SO | $18N3552 | ✅ | SO (Serial Output) is correctly connected to the Ethernet controller U42 pin 14 (NVM_SO) through series resistor R833 (33.2Ω). | | 3 | WP# | $18N3609 | ✅ | WP# (Write Protect) is correctly pulled high to +3VSB_LAN through R830 (10kΩ) as recommended by the datasheet. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 5 | SI | $18N2435 | ✅ | SI (Serial Input) is correctly connected to the Ethernet controller U42 pin 12 (NVM_SI) through series resistor R832 (33.2Ω), with a weak pull-up R848 (33.2kΩ) to +3VSB_LAN. | | 6 | SCK | $18N2437 | ✅ | SCK (Serial Clock) is correctly connected to the Ethernet controller U42 pin 13 (NVM_SK) through series resistor R834 (33.2Ω). | | 7 | HOLD# | $18N3659 | ✅ | HOLD# is correctly pulled high to +3VSB_LAN through R831 (10kΩ) as recommended by the datasheet. | | 8 | VCC | +3VSB_LAN | ✅ | VCC is correctly connected to the +3VSB_LAN power rail, which is within the specified 2.7V to 3.6V operating range. | </details> <details> <summary><b>C431</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED0 | ✅ | EMI filter capacitor (560pF) on the LAN-LED0 signal to suppress high-frequency noise on the LED line. | | 2 | 2 | GND | ✅ | EMI filter capacitor (560pF) on the LAN-LED0 signal to suppress high-frequency noise on the LED line. | </details> <details> <summary><b>C428</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap bypass capacitor (1.0uF) for Ethernet magnetics, providing AC coupling to ground with emphasis on lower frequency filtering. | | 2 | 2 | GND | ✅ | Center tap bypass capacitor (1.0uF) for Ethernet magnetics, providing AC coupling to ground with emphasis on lower frequency filtering. | </details> <details> <summary><b>C426</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering. | | 2 | 2 | GND | ✅ | Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering. | </details> <details> <summary><b>J11</b> - 3362-0042 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3362-0042) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | MD1+ | MDI_P0 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 2 | MD1- | MDI_N0 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 3 | MD2+ | MDI_P1 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 4 | MD2- | MDI_N1 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 7 | MD3+ | MDI_P2 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 8 | MD3- | MDI_N2 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 9 | MD4+ | MDI_P3 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 10 | MD4- | MDI_N3 | ✅ | MDI differential pairs connecting to Ethernet PHY U42. Four pairs (MDI_P0/N0, MDI_P1/N1, MDI_P2/N2, MDI_P3/N3) provide the Ethernet physical layer interface. | | 5 | CT1 | $18N3856 | ✅ | Center tap connections for Ethernet transformer, properly bypassed to ground through capacitors C426, C427, and C428. | | 6 | CT2 | $18N3856 | ✅ | Center tap connections for Ethernet transformer, properly bypassed to ground through capacitors C426, C427, and C428. | | 11 | LED2_AC1 | LAN-LED0 | ✅ | LED2_AC1 connects to LAN-LED0 from U42 pin 31 without a visible series current limiting resistor, which may cause excessive LED current unless the connector has built-in current limiting. | | 12 | LED2_AD1 | 1G-LED-N | ✅ | LED2_AD1 connects to 1G-LED-N, which is driven by U42 LED2 output through current limiting resistor R844 (301Ω). | | 13 | LED1_C | LINK-LED-N | ✅ | LED1_C (cathode) connects to LINK-LED-N, which is driven through current limiting resistor R843 (301Ω) from U42 LED1 output. | | 14 | LED1_A | +3VSB_LAN | ✅ | LED1_A (anode) connects to +3VSB_LAN power supply, providing the positive voltage for LED1. | | 15 | SHLD1 | GND_EARTH | ✅ | Shield connections to chassis ground (GND_EARTH) for EMI protection and ESD immunity. | | 16 | SHLD2 | GND_EARTH | ✅ | Shield connections to chassis ground (GND_EARTH) for EMI protection and ESD immunity. | </details> <details> <summary><b>C429</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LINK-LED-N | ✅ | EMI filter capacitor (560pF) on the LINK-LED-N signal to suppress high-frequency noise on the LED line. | | 2 | 2 | GND | ✅ | EMI filter capacitor (560pF) on the LINK-LED-N signal to suppress high-frequency noise on the LED line. | </details> <details> <summary><b>R844</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED2 | ✅ | Current limiting resistor (301Ω) for LED2, connecting U42 LED2 output to the LED signal 1G-LED-N. | | 2 | 2 | 1G-LED-N | ✅ | Current limiting resistor (301Ω) for LED2, connecting U42 LED2 output to the LED signal 1G-LED-N. | </details> <details> <summary><b>R843</b> - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED1 | ✅ | Current limiting resistor (301Ω) for LED1, connecting U42 LED1 output to the LED cathode signal LINK-LED-N. | | 2 | 2 | LINK-LED-N | ✅ | Current limiting resistor (301Ω) for LED1, connecting U42 LED1 output to the LED cathode signal LINK-LED-N. | </details> <details> <summary><b>C427</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering. | | 2 | 2 | GND | ✅ | Center tap bypass capacitor (0.1uF) for Ethernet magnetics, providing AC coupling to ground for common-mode filtering. | </details> <details> <summary><b>C430</b> - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1G-LED-N | ✅ | EMI filter capacitor (560pF) on the 1G-LED-N signal to suppress high-frequency noise on the LED line. | | 2 | 2 | GND | ✅ | EMI filter capacitor (560pF) on the 1G-LED-N signal to suppress high-frequency noise on the LED line. | </details> <details> <summary><b>X1</b> - 25.00MHz ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Crystal pin connected to U42 XTAL2 with 27pF load capacitor C253. | | 2 | 2 | GND | ✅ | Ground pin connected to GND. | | 3 | 3 | LAN_XTAL1 | ✅ | Crystal pin connected to U42 XTAL1 with 27pF load capacitor C252. | | 4 | 4 | GND | ✅ | Ground pin connected to GND. | </details> <details> <summary><b>U10</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the 1.8V reference voltage for the A-side of the level translator. | | 2 | A1 | SOC_GPIO_S5_2 | ✅ | A1 is correctly connected to SOC_GPIO_S5_2, one of the 1.8V SOC GPIO signals to be level-translated. | | 3 | A2 | SOC_GPIO_S5_1 | ✅ | A2 is correctly connected to SOC_GPIO_S5_1, one of the 1.8V SOC GPIO signals to be level-translated. | | 4 | A3 | SOC_GPIO_S5_0 | ✅ | A3 is correctly connected to SOC_GPIO_S5_0, one of the 1.8V SOC GPIO signals to be level-translated. | | 5 | A4 | | ✅ | A4 is left unconnected as the fourth channel is not used in this design. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net, providing the ground reference for the device. | | 7 | B4 | GND | ✅ | B4 is connected to GND, which appears to be the intended configuration for the unused fourth channel. | | 8 | B3 | GPIO_S5_0 | ✅ | B3 is correctly connected to GPIO_S5_0, the 3.3V side of the GPIO_S5_0 signal. | | 9 | B2 | GPIO_S5_1 | ✅ | B2 is correctly connected to GPIO_S5_1, the 3.3V side of the GPIO_S5_1 signal. | | 10 | B1 | GPIO_S5_2 | ✅ | B1 is correctly connected to GPIO_S5_2, the 3.3V side of the GPIO_S5_2 signal. | | 11 | VCCB | +PS_3VSB | ✅ | VCCB is correctly connected to +PS_3VSB, providing the 3.3V standby reference voltage for the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, a 1.8V platform reset signal that controls the output enable function. | </details> <details> <summary><b>U14</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S (1.8V supply) to provide the A-side voltage reference for the level translator. | | 2 | A1 | SOC_SIO_SPI_CLK | ✅ | A1 is correctly connected to SOC_SIO_SPI_CLK, the 1.8V SPI clock signal from the SOC, which pairs with B1 for level translation. | | 3 | A2 | SOC_SIO_SPI_MOSI | ✅ | A2 is correctly connected to SOC_SIO_SPI_MOSI, the 1.8V SPI MOSI signal from the SOC, which pairs with B2 for level translation. | | 4 | A3 | SOC_SIO_SPI_MISO | ✅ | A3 is correctly connected to SOC_SIO_SPI_MISO, the 1.8V SPI MISO signal from the SOC, which pairs with B3 for level translation. | | 5 | A4 | SOC_SIO_SPI_CS1 | ✅ | A4 is correctly connected to SOC_SIO_SPI_CS1, the 1.8V SPI chip select 1 signal from the SOC, which pairs with B4 for level translation. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SIO_SPI_CS1 | ✅ | B4 is correctly connected to SIO_SPI_CS1, the 3.3V translated SPI chip select 1 signal, which pairs with A4 for level translation. | | 8 | B3 | SIO_SPI_MISO | ✅ | B3 is correctly connected to SIO_SPI_MISO, the 3.3V translated SPI MISO signal, which pairs with A3 for level translation. | | 9 | B2 | SIO_SPI_MOSI | ✅ | B2 is correctly connected to SIO_SPI_MOSI, the 3.3V translated SPI MOSI signal, which pairs with A2 for level translation. | | 10 | B1 | SIO_SPI_CLK | ✅ | B1 is correctly connected to SIO_SPI_CLK, the 3.3V translated SPI clock signal, which pairs with A1 for level translation. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB (3.3V standby supply) to provide the B-side voltage reference for the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, a 1.8V platform reset signal that enables the level translator when high. | </details> <details> <summary><b>U15</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing 1.8V supply for the A-side of the level translator. | | 2 | A1 | SIO_UART1_RTSB | ✅ | A1 is correctly connected to SIO_UART1_RTSB, translating the UART RTS signal from 1.8V to 3.3V. | | 3 | A2 | SIO_UART1_CTSB | ✅ | A2 is correctly connected to SIO_UART1_CTSB, translating the UART CTS signal between 1.8V and 3.3V. | | 4 | A3 | SIO_UART1_RXD | ✅ | A3 is correctly connected to SIO_UART1_RXD, translating the UART receive data signal between 1.8V and 3.3V. | | 5 | A4 | SIO_UART1_TXD | ✅ | A4 is correctly connected to SIO_UART1_TXD, translating the UART transmit data signal from 1.8V to 3.3V. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | UART1_TXD | ✅ | B4 is correctly connected to UART1_TXD, providing the 3.3V level UART transmit signal to the connector. | | 8 | B3 | UART1_RXD | ✅ | B3 is correctly connected to UART1_RXD, receiving the 3.3V level UART receive signal from the connector. | | 9 | B2 | UART1_CTSB | ✅ | B2 is correctly connected to UART1_CTSB, providing the 3.3V level UART CTS signal to/from the connector. | | 10 | B1 | UART1_RTSB | ✅ | B1 is correctly connected to UART1_RTSB, providing the 3.3V level UART RTS signal to the connector. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing 3.3V supply for the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset. | </details> <details> <summary><b>U16</b> - NTS0104GU12 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | A1 | I2S_DATIN_R | ❌ | <details><summary>I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="70.11,63.30,77.61,70.80" aspect-ratio="1.29" } <ul><li>Pin 2 (A1) is connected to I2S_DATIN_R net <em>(from schematic)</em></li><li>Pin 3 (A2) is connected to I2S_DATOUT_R net <em>(from schematic)</em></li><li>Pin 9 (B2) is connected to I2SDO_GPIO net <em>(from schematic)</em></li><li>Pin 10 (B1) is connected to I2SDI_GPIO net <em>(from schematic)</em></li><li>I2SDO_GPIO connects to pin 18 of JP1 header connector <em>(from schematic)</em></li><li>I2SDI_GPIO connects to pin 20 of JP1 header connector <em>(from schematic)</em></li><li>The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 <em>(reasoning)</em></li><li>I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device <em>(reasoning)</em></li><li>I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device <em>(reasoning)</em></li><li>I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) <em>(reasoning)</em></li><li>I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data output must connect to the slave&#x27;s data input <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data input must connect to the slave&#x27;s data output <em>(reasoning)</em></li><li>Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection <em>(reasoning)</em></li><li>Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection <em>(reasoning)</em></li><li>The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) <em>(reasoning)</em></li><li>The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) <em>(reasoning)</em></li><li>To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) <em>(reasoning)</em></li></ul></details> | | 3 | A2 | I2S_DATOUT_R | ❌ | <details><summary>I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="70.11,63.89,77.61,71.39" aspect-ratio="1.29" } <ul><li>Pin 2 (A1) is connected to I2S_DATIN_R net <em>(from schematic)</em></li><li>Pin 3 (A2) is connected to I2S_DATOUT_R net <em>(from schematic)</em></li><li>Pin 9 (B2) is connected to I2SDO_GPIO net <em>(from schematic)</em></li><li>Pin 10 (B1) is connected to I2SDI_GPIO net <em>(from schematic)</em></li><li>I2SDO_GPIO connects to pin 18 of JP1 header connector <em>(from schematic)</em></li><li>I2SDI_GPIO connects to pin 20 of JP1 header connector <em>(from schematic)</em></li><li>The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 <em>(reasoning)</em></li><li>I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device <em>(reasoning)</em></li><li>I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device <em>(reasoning)</em></li><li>I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) <em>(reasoning)</em></li><li>I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data output must connect to the slave&#x27;s data input <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data input must connect to the slave&#x27;s data output <em>(reasoning)</em></li><li>Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection <em>(reasoning)</em></li><li>Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection <em>(reasoning)</em></li><li>The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) <em>(reasoning)</em></li><li>The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) <em>(reasoning)</em></li><li>To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) <em>(reasoning)</em></li></ul></details> | | 9 | B2 | I2SDO_GPIO | ❌ | <details><summary>I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="65.56,63.89,73.06,71.39" aspect-ratio="1.29" } <ul><li>Pin 2 (A1) is connected to I2S_DATIN_R net <em>(from schematic)</em></li><li>Pin 3 (A2) is connected to I2S_DATOUT_R net <em>(from schematic)</em></li><li>Pin 9 (B2) is connected to I2SDO_GPIO net <em>(from schematic)</em></li><li>Pin 10 (B1) is connected to I2SDI_GPIO net <em>(from schematic)</em></li><li>I2SDO_GPIO connects to pin 18 of JP1 header connector <em>(from schematic)</em></li><li>I2SDI_GPIO connects to pin 20 of JP1 header connector <em>(from schematic)</em></li><li>The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 <em>(reasoning)</em></li><li>I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device <em>(reasoning)</em></li><li>I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device <em>(reasoning)</em></li><li>I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) <em>(reasoning)</em></li><li>I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data output must connect to the slave&#x27;s data input <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data input must connect to the slave&#x27;s data output <em>(reasoning)</em></li><li>Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection <em>(reasoning)</em></li><li>Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection <em>(reasoning)</em></li><li>The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) <em>(reasoning)</em></li><li>The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) <em>(reasoning)</em></li><li>To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) <em>(reasoning)</em></li></ul></details> | | 10 | B1 | I2SDI_GPIO | ❌ | <details><summary>I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="65.56,63.30,73.06,70.80" aspect-ratio="1.29" } <ul><li>Pin 2 (A1) is connected to I2S_DATIN_R net <em>(from schematic)</em></li><li>Pin 3 (A2) is connected to I2S_DATOUT_R net <em>(from schematic)</em></li><li>Pin 9 (B2) is connected to I2SDO_GPIO net <em>(from schematic)</em></li><li>Pin 10 (B1) is connected to I2SDI_GPIO net <em>(from schematic)</em></li><li>I2SDO_GPIO connects to pin 18 of JP1 header connector <em>(from schematic)</em></li><li>I2SDI_GPIO connects to pin 20 of JP1 header connector <em>(from schematic)</em></li><li>The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 <em>(reasoning)</em></li><li>I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device <em>(reasoning)</em></li><li>I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device <em>(reasoning)</em></li><li>I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) <em>(reasoning)</em></li><li>I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data output must connect to the slave&#x27;s data input <em>(reasoning)</em></li><li>In I2S protocol, the master&#x27;s data input must connect to the slave&#x27;s data output <em>(reasoning)</em></li><li>Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection <em>(reasoning)</em></li><li>Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection <em>(reasoning)</em></li><li>The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) <em>(reasoning)</em></li><li>The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) <em>(reasoning)</em></li><li>To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) <em>(reasoning)</em></li></ul></details> | | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S (1.8V supply) with proper decoupling capacitor C352. | | 4 | A3 | I2S_FRM_R | ✅ | A3 is correctly connected to I2S_FRM_R, which connects through R129 to LPE_I2S_FRM and translates to B3 (I2SFRM_GPIO). | | 5 | A4 | I2S_CLK_R | ✅ | A4 is correctly connected to I2S_CLK_R, which connects through R127 to LPE_I2S_CLK and translates to B4 (I2SCLK_GPIO). | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | I2SCLK_GPIO | ✅ | B4 is correctly connected to I2SCLK_GPIO, which goes to the GPIO header. This corresponds to A4 (I2S_CLK_R). | | 8 | B3 | I2SFRM_GPIO | ✅ | B3 is correctly connected to I2SFRM_GPIO, which goes to the GPIO header. This corresponds to A3 (I2S_FRM_R). | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB (3.3V supply) with proper decoupling capacitor C353. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the translator when the platform is out of reset. | </details> <details> <summary><b>R127</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_CLK_R | ✅ | 0-ohm resistor correctly connects I2S_CLK_R to LPE_I2S_CLK, maintaining the 1.8V signal level. | | 2 | 2 | LPE_I2S_CLK | ✅ | 0-ohm resistor correctly connects I2S_CLK_R to LPE_I2S_CLK, maintaining the 1.8V signal level. | </details> <details> <summary><b>R128</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_DATIN_R | ✅ | 0-ohm resistor correctly connects I2S_DATIN_R to LPE_I2S_DATIN, maintaining the 1.8V signal level. | | 2 | 2 | LPE_I2S_DATIN | ✅ | 0-ohm resistor correctly connects I2S_DATIN_R to LPE_I2S_DATIN, maintaining the 1.8V signal level. | </details> <details> <summary><b>R129</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_FRM_R | ✅ | 0-ohm resistor correctly connects I2S_FRM_R to LPE_I2S_FRM, maintaining the 1.8V signal level. | | 2 | 2 | LPE_I2S_FRM | ✅ | 0-ohm resistor correctly connects I2S_FRM_R to LPE_I2S_FRM, maintaining the 1.8V signal level. | </details> <details> <summary><b>R130</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_DATOUT_R | ✅ | 0-ohm resistor correctly connects I2S_DATOUT_R to LPE_I2S_DATOUT, maintaining the 1.8V signal level. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | 0-ohm resistor correctly connects I2S_DATOUT_R to LPE_I2S_DATOUT, maintaining the 1.8V signal level. | </details> <details> <summary><b>U17</b> - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing the A-side reference voltage for the level translator. | | 2 | A1 | I2S_MCLK | ✅ | A1 is correctly connected to I2S_MCLK, an A-side I/O signal that will be translated to I2SMCLK_GPIO on B1. | | 3 | A2 | SOC_PWM1 | ✅ | A2 is correctly connected to SOC_PWM1, an A-side I/O signal that will be translated to PWM1 on B2. | | 4 | A3 | SOC_PWM0 | ✅ | A3 is correctly connected to SOC_PWM0, an A-side I/O signal that will be translated to PWM0 on B3. | | 5 | A4 | | ✅ | A4 is left unconnected as this channel is unused, which is acceptable for the level translator. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | GND | ✅ | B4 is correctly tied to GND as this channel is unused (A4 is not connected). | | 8 | B3 | PWM0 | ✅ | B3 is correctly connected to PWM0, the B-side translation of SOC_PWM0 from A3. | | 9 | B2 | PWM1 | ✅ | B2 is correctly connected to PWM1, the B-side translation of SOC_PWM1 from A2. | | 10 | B1 | I2SMCLK_GPIO | ✅ | B1 is correctly connected to I2SMCLK_GPIO, the B-side translation of I2S_MCLK from A1. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing the B-side reference voltage for the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the translator when the platform is out of reset. | </details> <details> <summary><b>R147</b> - 100K ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | R147 provides a pullup from DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control during programming. | | 2 | 2 | DDP_IO3L | ✅ | R147 provides a pullup from DDP_IO3L to +V1P8A, enabling the voltage translator U18 by default while allowing external control during programming. | </details> <details> <summary><b>R163</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | R163 provides a pullup from SPI_CS0 to +V_SPI, keeping the flash chip deselected by default. | | 2 | 2 | SPI_CS0 | ✅ | R163 provides a pullup from SPI_CS0 to +V_SPI, keeping the flash chip deselected by default. | </details> <details> <summary><b>R164</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | R164 provides a pullup from SPI_WP to +V_SPI, disabling hardware write protection by default. | | 2 | 2 | SPI_WP | ✅ | R164 provides a pullup from SPI_WP to +V_SPI, disabling hardware write protection by default. | </details> <details> <summary><b>R165</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | R165 provides a pullup from SPI_HOLD to +V_SPI, disabling the hold function by default. | | 2 | 2 | SPI_HOLD | ✅ | R165 provides a pullup from SPI_HOLD to +V_SPI, disabling the hold function by default. | </details> <details> <summary><b>D8</b> - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | DDP_VCC | ✅ | A1 is correctly connected to DDP_VCC, providing one source path for +V_SPI through the diode OR-ing circuit. | | A2 | A2 | $20N2079 | ✅ | A2 is correctly connected to the voltage selection network, providing the second source path for +V_SPI. | | C | C | +V_SPI | ✅ | C is correctly connected to +V_SPI, providing the OR-ed output to power the SPI flash and level translator B-side. | </details> <details> <summary><b>U3</b> - W25Q64BVSSIG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/653/W25Q64BV.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/W25Q64BVSSIG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPI_CS0 | ✅ | CS# is correctly connected to SPI_CS0 with a 10K pull-up to +V_SPI, as recommended for proper SPI operation. | | 2 | SO/IO1 | SPI_MISO | ✅ | SO/IO1 is correctly connected to SPI_MISO for data output from the flash memory. | | 3 | WP#/IO2 | SPI_WP | ✅ | WP#/IO2 is correctly connected to SPI_WP with a 10K pull-up to +V_SPI, disabling write protection in standard SPI mode. | | 4 | GND | GND | ✅ | GND is correctly connected to ground. | | 5 | SI/IO0 | SPI_MOSI | ✅ | SI/IO0 is correctly connected to SPI_MOSI for data input to the flash memory. | | 6 | SCK | SPI_CLK | ✅ | SCK is correctly connected to SPI_CLK for the serial clock input. | | 7 | HOLD#/IO3 | SPI_HOLD | ✅ | HOLD#/IO3 is correctly connected to SPI_HOLD with a 10K pull-up to +V_SPI, disabling the hold function in standard SPI mode. | | 8 | VCC | +V_SPI | ✅ | VCC is connected to +V_SPI which is supplied via diode OR-ing from either DDP_VCC or +3VSB. The voltage may be marginal at the low end of the acceptable range due to diode drop. | </details> <details> <summary><b>U18</b> - NTB0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTB0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the A-side reference voltage for the level translator. | | 2 | A1 | SOC_SPI_MOSI-R | ✅ | A1 is correctly connected to SOC_SPI_MOSI-R for MOSI signal translation. | | 3 | A2 | SOC_SPI_CLK-R | ✅ | A2 is correctly connected to SOC_SPI_CLK-R for clock signal translation. | | 4 | A3 | SOC_SPI_MISO-R | ✅ | A3 is correctly connected to SOC_SPI_MISO-R for MISO signal translation. | | 5 | A4 | SOC_SPI_CS0B-R | ✅ | A4 is correctly connected to SOC_SPI_CS0B-R for chip select signal translation. | | 6 | GND | GND | ✅ | GND is correctly connected to ground. | | 7 | B4 | SPI_CS0 | ✅ | B4 is correctly connected to SPI_CS0, translating the chip select signal to the B-side voltage level. | | 8 | B3 | SPI_MISO | ✅ | B3 is correctly connected to SPI_MISO, translating the MISO signal to the B-side voltage level. | | 9 | B2 | SPI_CLK | ✅ | B2 is correctly connected to SPI_CLK, translating the clock signal to the B-side voltage level. | | 10 | B1 | SPI_MOSI | ✅ | B1 is correctly connected to SPI_MOSI, translating the MOSI signal to the B-side voltage level. | | 11 | VCCB | +V_SPI | ✅ | VCCB is correctly connected to +V_SPI, providing the B-side reference voltage. The voltage level is approximately 2.9-3.0V after diode drop from +3VSB. | | 12 | OE | DDP_IO3L | ✅ | OE is connected to DDP_IO3L with a 100K pull-up to +V1P8A. Without the datasheet, the appropriateness of using 1.8V for OE when VCCB is 3.3V cannot be confirmed. | </details> <details> <summary><b>U40</b> - PCA9306DCUT ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fpca9306) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/PCA9306DCUT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | SDA2 | GPIO_I2C_SDA | ❌ | <details><summary>SDA2 and SCL2 pins are missing required pullup resistors to the high-voltage supply (+3VSB). The datasheet explicitly requires pullup resistors on both sides of the I2C translator for proper operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,77.42,31.26,84.92" aspect-ratio="1.29" } <ul><li>Pin 5 (SDA2) connects to GPIO_I2C_SDA and pin 6 (SCL2) connects to GPIO_I2C_SCL <em>(from schematic)</em></li><li>Pin 5 is SDA2 (Serial data, high-voltage side) and pin 6 is SCL2 (Serial clock, high-voltage side) <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</em></li><li>The datasheet states: &#x27;Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>The datasheet states: &#x27;the I2C bus device output can be open-drain with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>Both typical application circuits in the datasheet show pullup resistors (RPU) on SCL2 and SDA2 to VDPU <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17">PCA9306DCUT</a>, page 17)</em></li><li>No pullup resistors are present on the GPIO_I2C_SDA or GPIO_I2C_SCL nets in the schematic <em>(from schematic)</em></li><li>The low-voltage side has pullup resistors: R267 (10K) on I2C5_SCL to +V1P8S and R266 (10K) on I2C5_SDA to +V1P8S <em>(from schematic)</em></li><li>The asymmetry between low-voltage side (with pullups) and high-voltage side (without pullups) indicates a design oversight rather than intentional reliance on external pullups <em>(reasoning)</em></li><li>GPIO_I2C_SCL and GPIO_I2C_SDA connect to JP1 connector pins 13 and 15, which is a general-purpose expansion header <em>(from schematic)</em></li><li>Without pullup resistors, the I2C signals cannot be pulled high and the bus will not function correctly <em>(reasoning)</em></li><li>Pullup resistors (typically 2.2K to 10K depending on bus capacitance and speed per I2C specification) should be added from GPIO_I2C_SDA to +3VSB and from GPIO_I2C_SCL to +3VSB <em>(reasoning)</em></li><li>If external pullups are intentionally expected on the other side of connector JP1, this should be clearly documented with a note on the schematic, but no such note is present <em>(reasoning)</em></li></ul></details> | | 6 | SCL2 | GPIO_I2C_SCL | ❌ | <details><summary>SDA2 and SCL2 pins are missing required pullup resistors to the high-voltage supply (+3VSB). The datasheet explicitly requires pullup resistors on both sides of the I2C translator for proper operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.33" aspect-ratio="1.29" } <ul><li>Pin 5 (SDA2) connects to GPIO_I2C_SDA and pin 6 (SCL2) connects to GPIO_I2C_SCL <em>(from schematic)</em></li><li>Pin 5 is SDA2 (Serial data, high-voltage side) and pin 6 is SCL2 (Serial clock, high-voltage side) <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</em></li><li>The datasheet states: &#x27;Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>The datasheet states: &#x27;the I2C bus device output can be open-drain with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU&#x27; <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</em></li><li>Both typical application circuits in the datasheet show pullup resistors (RPU) on SCL2 and SDA2 to VDPU <em>(from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17">PCA9306DCUT</a>, page 17)</em></li><li>No pullup resistors are present on the GPIO_I2C_SDA or GPIO_I2C_SCL nets in the schematic <em>(from schematic)</em></li><li>The low-voltage side has pullup resistors: R267 (10K) on I2C5_SCL to +V1P8S and R266 (10K) on I2C5_SDA to +V1P8S <em>(from schematic)</em></li><li>The asymmetry between low-voltage side (with pullups) and high-voltage side (without pullups) indicates a design oversight rather than intentional reliance on external pullups <em>(reasoning)</em></li><li>GPIO_I2C_SCL and GPIO_I2C_SDA connect to JP1 connector pins 13 and 15, which is a general-purpose expansion header <em>(from schematic)</em></li><li>Without pullup resistors, the I2C signals cannot be pulled high and the bus will not function correctly <em>(reasoning)</em></li><li>Pullup resistors (typically 2.2K to 10K depending on bus capacitance and speed per I2C specification) should be added from GPIO_I2C_SDA to +3VSB and from GPIO_I2C_SCL to +3VSB <em>(reasoning)</em></li><li>If external pullups are intentionally expected on the other side of connector JP1, this should be clearly documented with a note on the schematic, but no such note is present <em>(reasoning)</em></li></ul></details> | | 1 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 2 | VREF1 | +V1P8S | ✅ | VREF1 pin correctly connected to +V1P8S (1.8V) low-voltage reference supply. | | 3 | SCL1 | I2C5_SCL | ✅ | SCL1 pin correctly connected to I2C5_SCL with required pullup resistor R267 (10K) to +V1P8S. | | 4 | SDA1 | I2C5_SDA | ✅ | SDA1 pin correctly connected to I2C5_SDA with required pullup resistor R266 (10K) to +V1P8S. | | 7 | VREF2 | $20N1576 | ✅ | VREF2 pin correctly connected to net $20N1576, which is pulled to +3VSB through required 200K resistor R812. VREF2 is shorted to EN pin as required. | | 8 | EN | $20N1576 | ✅ | EN pin correctly connected to net $20N1576, shorted with VREF2 and pulled to +3VSB through 200K resistor R812, enabling the device for voltage translation. | </details> <details> <summary><b>R812</b> - 200K ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N1576 | ✅ | 200K resistor correctly provides required high-impedance connection between VREF2/EN (net $20N1576) and high-voltage supply (+3VSB). | | 2 | 2 | +3VSB | ✅ | 200K resistor correctly provides required high-impedance connection between VREF2/EN (net $20N1576) and high-voltage supply (+3VSB). | </details> <details> <summary><b>R266</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C5_SDA | ✅ | 10K pullup resistor correctly provides required pullup for SDA1 (I2C5_SDA) to VREF1 (+V1P8S). | | 2 | 2 | +V1P8S | ✅ | 10K pullup resistor correctly provides required pullup for SDA1 (I2C5_SDA) to VREF1 (+V1P8S). | </details> <details> <summary><b>R267</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C5_SCL | ✅ | 10K pullup resistor correctly provides required pullup for SCL1 (I2C5_SCL) to VREF1 (+V1P8S). | | 2 | 2 | +V1P8S | ✅ | 10K pullup resistor correctly provides required pullup for SCL1 (I2C5_SCL) to VREF1 (+V1P8S). | </details> <details> <summary><b>J1</b> - 258-0004612 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0004612) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDP_VCC | ✅ | Pin 1 connected to DDP_VCC, providing power input from the DediProg programmer. | | 2 | 2 | GND | ✅ | Pin 2 connected to GND for ground reference. | | 3 | 3 | SPI_CS0 | ✅ | Pin 3 connected to SPI_CS0 for SPI chip select. | | 4 | 4 | SPI_CLK | ✅ | Pin 4 connected to SPI_CLK for SPI clock. | | 5 | 5 | SPI_MISO | ✅ | Pin 5 connected to SPI_MISO for SPI data output from the flash. | | 6 | 6 | SPI_MOSI | ✅ | Pin 6 connected to SPI_MOSI for SPI data input to the flash. | | 7 | 7 | | ✅ | Pin 7 is not connected. | | 8 | 8 | DDP_IO3L | ✅ | Pin 8 connected to DDP_IO3L, which controls the enable of U18 translator. | </details> <details> <summary><b>J5</b> - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Jumper pin connected to FP_PWRBTN signal for test/debug functionality. | | 2 | 2 | GND | ✅ | Jumper pin connected to GND to allow shorting FP_PWRBTN to ground when jumper is installed. | </details> <details> <summary><b>R149</b> - 4.7K ohm 1% 1/10W 0402 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ❌ | <details><summary>Pullup resistor with correct connections between +PS_5VSB and FP_PWRBTN, but component value (4.7K) does not match the datasheet recommendation of 10K noted in schematic annotations.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="26.71,15.08,34.21,22.58" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net FP_PWRBTN <em>(from schematic)</em></li><li>Pin 2 is connected to net +PS_5VSB <em>(from schematic)</em></li><li>R149 serves as a pullup resistor, pulling FP_PWRBTN high to +PS_5VSB when the power button SW1 is not pressed <em>(reasoning)</em></li><li>The component value is 4.7K ohm per part number 110-0002058 <em>(from schematic)</em></li><li>Schematic text annotations at coordinates (180.34, 355.6) and (180.34, 360.68) state &#x27;USE 10K PU&#x27; and &#x27;DATASHEET SAYS&#x27;, located near R149 at (172.72, 347.98) <em>(from schematic)</em></li><li>These annotations indicate the datasheet for the receiving circuit recommends a 10K pullup resistor <em>(reasoning)</em></li><li>With 4.7K, the current draw when the button is pressed is approximately 1.06mA (5V / 4.7K), while 10K would draw approximately 0.5mA <em>(reasoning)</em></li><li>The RC time constant with C154 (0.1uF) and 4.7K is 470us, compared to 1ms with the recommended 10K <em>(reasoning)</em></li><li>The stronger 4.7K pullup provides faster rise time and better noise immunity, but may exceed input current specifications of the receiving circuit <em>(reasoning)</em></li><li>The component value should be changed to 10K to match the datasheet recommendation explicitly noted on the schematic <em>(reasoning)</em></li></ul></details> | | 2 | 2 | +PS_5VSB | ❌ | <details><summary>Pullup resistor with correct connections between +PS_5VSB and FP_PWRBTN, but component value (4.7K) does not match the datasheet recommendation of 10K noted in schematic annotations.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="26.71,13.91,34.21,21.41" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net FP_PWRBTN <em>(from schematic)</em></li><li>Pin 2 is connected to net +PS_5VSB <em>(from schematic)</em></li><li>R149 serves as a pullup resistor, pulling FP_PWRBTN high to +PS_5VSB when the power button SW1 is not pressed <em>(reasoning)</em></li><li>The component value is 4.7K ohm per part number 110-0002058 <em>(from schematic)</em></li><li>Schematic text annotations at coordinates (180.34, 355.6) and (180.34, 360.68) state &#x27;USE 10K PU&#x27; and &#x27;DATASHEET SAYS&#x27;, located near R149 at (172.72, 347.98) <em>(from schematic)</em></li><li>These annotations indicate the datasheet for the receiving circuit recommends a 10K pullup resistor <em>(reasoning)</em></li><li>With 4.7K, the current draw when the button is pressed is approximately 1.06mA (5V / 4.7K), while 10K would draw approximately 0.5mA <em>(reasoning)</em></li><li>The RC time constant with C154 (0.1uF) and 4.7K is 470us, compared to 1ms with the recommended 10K <em>(reasoning)</em></li><li>The stronger 4.7K pullup provides faster rise time and better noise immunity, but may exceed input current specifications of the receiving circuit <em>(reasoning)</em></li><li>The component value should be changed to 10K to match the datasheet recommendation explicitly noted on the schematic <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>C154</b> - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Filter capacitor correctly connected between FP_PWRBTN and GND for noise filtering and debouncing. | | 2 | 2 | FP_PWRBTN | ✅ | Filter capacitor correctly connected between FP_PWRBTN and GND for noise filtering and debouncing. | </details> <details> <summary><b>SW1</b> - 3770-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3770-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Switch output connected to FP_PWRBTN signal, which is pulled up to +PS_5VSB through R149 and protected by TVS diode D9. | | 2 | 2 | GND | ✅ | Switch ground terminal correctly connected to main GND net. | | 3 | GND1 | GND_EARTH | ✅ | Chassis ground pins correctly connected to GND_EARTH for EMI/ESD protection, intentionally isolated from signal GND. | | 4 | GND2 | GND_EARTH | ✅ | Chassis ground pins correctly connected to GND_EARTH for EMI/ESD protection, intentionally isolated from signal GND. | </details> <details> <summary><b>D9</b> - DIODE_TVS_5V_84W_XFDFN ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | TVS diode reference terminal correctly connected to GND for bidirectional ESD protection. | | P | P | FP_PWRBTN | ✅ | TVS diode signal terminal correctly connected to FP_PWRBTN for ESD protection of the power button input. | </details> <details> <summary><b>Q105</b> - FDN327N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/FDN327N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | GPIO_LED_CONTROL | ✅ | Drain is connected to GPIO_LED_CONTROL net, which is shared with LED D2 anode (pin A), creating a parallel configuration. While the MOSFET connection itself is valid, the circuit topology is incorrect due to D2's connections - the LED should be in series with the MOSFET, not in parallel. | | G | GATE | GPIO_D2_LED_CTRL | ✅ | Gate is correctly connected to GPIO_D2_LED_CTRL with a 10K pull-down resistor (R706) to GND, which is standard practice for MOSFET gate control. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, which is the standard configuration for an N-channel MOSFET low-side switch. | </details> <details> <summary><b>D2</b> - 4560-0045 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GPIO_LED_CONTROL | ❌ | <details><summary>LED is connected in parallel with MOSFET Q105 instead of in series. Anode (A) connects to GPIO_LED_CONTROL net which is shared with Q105 drain, and cathode (C) connects to GND. This creates an inefficient inverted-logic configuration. The correct series topology should be: +VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="61.02,35.08,68.52,42.58" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net GPIO_LED_CONTROL <em>(from schematic)</em></li><li>Pin C (Cathode) is connected to net GND <em>(from schematic)</em></li><li>Net GPIO_LED_CONTROL connects to Q105 pin D (drain), R746 pin 2, and C149 pin 1 <em>(from schematic)</em></li><li>D2 is a blue LED (part 4560-0045) with maximum voltage 3.8V <em>(from schematic)</em></li><li>Blue LEDs typically have forward voltage of 3.0-3.5V <em>(reasoning)</em></li><li>The current topology creates a parallel configuration where D2 and Q105 drain-source are both connected between GPIO_LED_CONTROL and GND <em>(reasoning)</em></li><li>In this parallel configuration, when Q105 is OFF (gate low), current flows from +VCC through R746 (470Ω) and D2 to GND, lighting the LED <em>(reasoning)</em></li><li>When Q105 is ON (gate high), Q105 pulls GPIO_LED_CONTROL low, shorting the LED path and turning it off <em>(reasoning)</em></li><li>This creates inverted logic: GPIO high = LED off, GPIO low = LED on <em>(reasoning)</em></li><li>When the LED is off (Q105 ON), current continues to flow from +VCC through R746 and Q105 to GND, wasting approximately 23mW at 3.3V or 53mW at 5V <em>(reasoning)</em></li><li>The standard configuration for GPIO-controlled LED with N-channel MOSFET low-side switch is series topology: +VCC → R_current_limit → LED_anode → LED_cathode → MOSFET_drain → MOSFET_source → GND <em>(reasoning)</em></li><li>Series configuration provides non-inverted logic (GPIO high = LED on), zero current when LED is off, and is the overwhelming industry standard <em>(reasoning)</em></li><li>There is no indication in schematic notes, net names, or documentation that inverted logic is intentional <em>(reasoning)</em></li><li>The net name &#x27;GPIO_LED_CONTROL&#x27; suggests direct control, not inverted control <em>(reasoning)</em></li><li>If inverted control was intended, typical design practice would include a note or use net naming like &#x27;GPIO_LED_CONTROL_N&#x27; or &#x27;LED_OFF&#x27; <em>(reasoning)</em></li><li>The text note &#x27;SYSTEM POWER LED - GPIO CONTROLLED&#x27; does not specify or justify inverted control <em>(from schematic)</em></li><li>For comparison, D1 on the same page uses standard series configuration: +PS_5VSB → D1 → R148 → GND <em>(from schematic)</em></li><li>The correct connections should be: D2 anode to R746 pin 2 only (on separate net from Q105), and D2 cathode to Q105 drain (on new net) <em>(reasoning)</em></li><li>This would create the standard series topology with non-inverted logic and zero power consumption when LED is off <em>(reasoning)</em></li></ul></details> | | C | CATHODE | GND | ❌ | <details><summary>LED is connected in parallel with MOSFET Q105 instead of in series. Anode (A) connects to GPIO_LED_CONTROL net which is shared with Q105 drain, and cathode (C) connects to GND. This creates an inefficient inverted-logic configuration. The correct series topology should be: +VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="62.84,35.08,70.34,42.58" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net GPIO_LED_CONTROL <em>(from schematic)</em></li><li>Pin C (Cathode) is connected to net GND <em>(from schematic)</em></li><li>Net GPIO_LED_CONTROL connects to Q105 pin D (drain), R746 pin 2, and C149 pin 1 <em>(from schematic)</em></li><li>D2 is a blue LED (part 4560-0045) with maximum voltage 3.8V <em>(from schematic)</em></li><li>Blue LEDs typically have forward voltage of 3.0-3.5V <em>(reasoning)</em></li><li>The current topology creates a parallel configuration where D2 and Q105 drain-source are both connected between GPIO_LED_CONTROL and GND <em>(reasoning)</em></li><li>In this parallel configuration, when Q105 is OFF (gate low), current flows from +VCC through R746 (470Ω) and D2 to GND, lighting the LED <em>(reasoning)</em></li><li>When Q105 is ON (gate high), Q105 pulls GPIO_LED_CONTROL low, shorting the LED path and turning it off <em>(reasoning)</em></li><li>This creates inverted logic: GPIO high = LED off, GPIO low = LED on <em>(reasoning)</em></li><li>When the LED is off (Q105 ON), current continues to flow from +VCC through R746 and Q105 to GND, wasting approximately 23mW at 3.3V or 53mW at 5V <em>(reasoning)</em></li><li>The standard configuration for GPIO-controlled LED with N-channel MOSFET low-side switch is series topology: +VCC → R_current_limit → LED_anode → LED_cathode → MOSFET_drain → MOSFET_source → GND <em>(reasoning)</em></li><li>Series configuration provides non-inverted logic (GPIO high = LED on), zero current when LED is off, and is the overwhelming industry standard <em>(reasoning)</em></li><li>There is no indication in schematic notes, net names, or documentation that inverted logic is intentional <em>(reasoning)</em></li><li>The net name &#x27;GPIO_LED_CONTROL&#x27; suggests direct control, not inverted control <em>(reasoning)</em></li><li>If inverted control was intended, typical design practice would include a note or use net naming like &#x27;GPIO_LED_CONTROL_N&#x27; or &#x27;LED_OFF&#x27; <em>(reasoning)</em></li><li>The text note &#x27;SYSTEM POWER LED - GPIO CONTROLLED&#x27; does not specify or justify inverted control <em>(from schematic)</em></li><li>For comparison, D1 on the same page uses standard series configuration: +PS_5VSB → D1 → R148 → GND <em>(from schematic)</em></li><li>The correct connections should be: D2 anode to R746 pin 2 only (on separate net from Q105), and D2 cathode to Q105 drain (on new net) <em>(reasoning)</em></li><li>This would create the standard series topology with non-inverted logic and zero power consumption when LED is off <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R746</b> - 1120-0318 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/1120-0318) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Pin 1 is correctly connected to +VCC power supply for LED current limiting. | | 2 | 2 | GPIO_LED_CONTROL | ✅ | Pin 2 is connected to GPIO_LED_CONTROL net, which is shared with D2 anode, Q105 drain, and C149. While R746 is correctly connected to D2 anode for current limiting, the overall circuit topology is incorrect due to D2's parallel configuration with Q105. | </details> <details> <summary><b>C149</b> - 2.2uF 10% 10V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0003258) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_LED_CONTROL | ✅ | Pin 1 is connected to GPIO_LED_CONTROL net. The purpose of this 2.2µF capacitor in the LED circuit is unusual - it may be intended for filtering or to create a soft turn-on/turn-off effect, though the value seems large for typical LED applications. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND, which is appropriate for a bypass or filter capacitor. | </details> <details> <summary><b>R706</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_D2_LED_CTRL | ✅ | Pin 1 is correctly connected to GPIO_D2_LED_CTRL, which drives the gate of Q105. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND, providing pull-down function for the MOSFET gate. | </details> <details> <summary><b>R148</b> - 1120-0318 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/1120-0318) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PWR_LEDR | ✅ | Connected to PWR_LEDR net, which connects to the cathode of LED D1. Functions as the current limiting resistor for the adapter power LED indicator. | | 2 | 2 | GND | ✅ | Connected to GND. Completes the current path for the adapter power LED circuit. | </details> <details> <summary><b>C150</b> - 123-0003258 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0003258) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Connected to +PS_5VSB supply rail. Provides local decoupling for the adapter power LED circuit. | | 2 | 2 | GND | ✅ | Connected to GND. Completes the decoupling capacitor connection across the power supply. | </details> <details> <summary><b>D1</b> - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | +PS_5VSB | ✅ | Anode connected to +PS_5VSB (5V standby power). This powers the adapter power indicator LED. | | C | CATHODE | PWR_LEDR | ✅ | Cathode connected to PWR_LEDR net, which connects through current limiting resistor R148 (470Ω) to ground. This completes the LED circuit with appropriate current limiting. | </details> <details> <summary><b>Q106</b> - BSS84 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/bss84-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BSS84) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | D | DC_GATE_ENB | ✅ | Drain pin is correctly connected to DC_GATE_ENB, which controls the gate of U36 for overvoltage protection. | | G | G | $22N2300 | ✅ | Gate pin is correctly connected to $22N2300, which is the voltage-sensed node clamped by zener D13 at 4.3V. | | S | S | $22N1502 | ✅ | Source pin is correctly connected to $22N1502, which is the filtered DC input voltage being monitored. | </details> <details> <summary><b>U36</b> - IRF9321 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.umw-ic.com/static/pdf/b379d167af492bcd72ba51c793d83236.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/IRF9321) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | $22N1502 | ✅ | Source pins S1, S2, S3 are correctly connected to $22N1502, which is the filtered DC input voltage through ferrite beads L13 and L12 from DC_IN_1. | | 2 | S2 | $22N1502 | ✅ | Source pins S1, S2, S3 are correctly connected to $22N1502, which is the filtered DC input voltage through ferrite beads L13 and L12 from DC_IN_1. | | 3 | S3 | $22N1502 | ✅ | Source pins S1, S2, S3 are correctly connected to $22N1502, which is the filtered DC input voltage through ferrite beads L13 and L12 from DC_IN_1. | | 4 | G | DC_GATE_ENB | ✅ | Gate pin G is correctly connected to DC_GATE_ENB, which is controlled by the overvoltage protection circuit through Q106. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_5VSB, which is the protected 5V standby output. | </details> <details> <summary><b>D13</b> - 4620-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4620-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode is correctly connected to GND for zener voltage reference operation. | | C | CATHODE | $22N2300 | ✅ | Cathode is correctly connected to $22N2300, clamping this node to 4.3V above ground for the protection circuit. | </details> <details> <summary><b>R323</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 5VSB_GATE | ✅ | Gate drive resistor correctly connected between 5VSB_CTRL control signal and 5VSB_GATE (gate of Q14). | | 2 | 2 | 5VSB_CTRL | ✅ | Gate drive resistor correctly connected between 5VSB_CTRL control signal and 5VSB_GATE (gate of Q14). | </details> <details> <summary><b>R324</b> - 100K ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 5VSB_LSENB | ✅ | Pull-up resistor correctly connected between +10V and 5VSB_LSENB (gate of Q103). | | 2 | 2 | +10V | ✅ | Pull-up resistor correctly connected between +10V and 5VSB_LSENB (gate of Q103). | </details> <details> <summary><b>C340</b> - 1.0uF ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 5VSB_GATE | ✅ | Gate decoupling capacitor correctly connected between 5VSB_GATE (gate of Q14) and GND. | | 2 | 2 | GND | ✅ | Gate decoupling capacitor correctly connected between 5VSB_GATE (gate of Q14) and GND. | </details> <details> <summary><b>C341</b> - 1.0uF ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Gate decoupling capacitor correctly connected between GND and 5VSB_LSENB (gate of Q103). | | 2 | 2 | 5VSB_LSENB | ✅ | Gate decoupling capacitor correctly connected between GND and 5VSB_LSENB (gate of Q103). | </details> <details> <summary><b>Q14</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | 5VSB_LSENB | ✅ | Drain pin correctly connected to 5VSB_LSENB net, which is pulled up to +10V through R324 and controls the gate of Q103. | | G | GATE | 5VSB_GATE | ✅ | Gate pin correctly connected to 5VSB_GATE control signal through R323 (10K) with C340 (1uF) providing filtering to ground. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND, providing the return path for the low-side switch configuration. | </details> <details> <summary><b>Q103</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. All three source pins are paralleled to handle the 15.3A maximum current rating. | | 2 | S2 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. All three source pins are paralleled to handle the 15.3A maximum current rating. | | 3 | S3 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. All three source pins are paralleled to handle the 15.3A maximum current rating. | | 4 | G | 5VSB_LSENB | ✅ | Gate pin correctly connected to 5VSB_LSENB control signal. The gate is driven to +10V through R324 when enabled, providing VGS of approximately 5V which is sufficient to turn on the MOSFET. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. All four drain pins are paralleled to handle the high current and minimize resistance. | </details> <details> <summary><b>R133</b> - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pull-up resistor correctly connected between +V1P8A and S5_ENBL to provide default high state for the enable signal. | | 2 | 2 | S5_ENBL | ✅ | Pull-up resistor correctly connected between +V1P8A and S5_ENBL to provide default high state for the enable signal. | </details> <details> <summary><b>R321</b> - 1K00 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_EN_L | ✅ | Pull-up resistor correctly connected between +PS_5VSB and +3VSB_EN_L to provide default high state for the gate control signal. | | 2 | 2 | +PS_5VSB | ✅ | Pull-up resistor correctly connected between +PS_5VSB and +3VSB_EN_L to provide default high state for the gate control signal. | </details> <details> <summary><b>R322</b> - 100K ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_EN | ✅ | Pull-up resistor correctly connected between +10V and +3VSB_EN to provide gate drive voltage for Q104 high-side P-channel MOSFET switch. | | 2 | 2 | +10V | ✅ | Pull-up resistor correctly connected between +10V and +3VSB_EN to provide gate drive voltage for Q104 high-side P-channel MOSFET switch. | </details> <details> <summary><b>C116</b> - 1.0uF ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor correctly connected between +3VSB_EN and GND to filter the gate drive signal and provide local charge storage. | | 2 | 2 | +3VSB_EN | ✅ | Decoupling capacitor correctly connected between +3VSB_EN and GND to filter the gate drive signal and provide local charge storage. | </details> <details> <summary><b>Q104</b> - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +3VSB | ✅ | Source pins S1, S2, S3 are correctly connected to +3VSB output rail. These pins carry the switched output current to the system. | | 2 | S2 | +3VSB | ✅ | Source pins S1, S2, S3 are correctly connected to +3VSB output rail. These pins carry the switched output current to the system. | | 3 | S3 | +3VSB | ✅ | Source pins S1, S2, S3 are correctly connected to +3VSB output rail. These pins carry the switched output current to the system. | | 4 | G | +3VSB_EN | ✅ | Gate pin is correctly connected to +3VSB_EN control signal, which is pulled up to +10V through R322 to provide sufficient gate drive voltage for high-side switching. | | 5 | D1 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output. | | 6 | D2 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output. | | 7 | D3 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output. | | 8 | D4 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input rail. These pins receive power from the 3.3V buck converter output. | </details> <details> <summary><b>D6</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB_PG | ✅ | Dual Schottky diode correctly configured as an OR gate to pull PMC_RSMRST high when either +PS_3VSB_PG or +3VSB_EN is high. | | 2 | 2 | +3VSB_EN | ✅ | Dual Schottky diode correctly configured as an OR gate to pull PMC_RSMRST high when either +PS_3VSB_PG or +3VSB_EN is high. | | 3 | 3 | PMC_RSMRST | ✅ | Dual Schottky diode correctly configured as an OR gate to pull PMC_RSMRST high when either +PS_3VSB_PG or +3VSB_EN is high. | </details> <details> <summary><b>Q11</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB_EN | ✅ | Drain is correctly connected to +3VSB_EN to pull the gate drive signal low when Q11 is enabled. | | G | GATE | +3VSB_EN_L | ✅ | Gate is correctly connected to +3VSB_EN_L control signal, which is pulled up to +PS_5VSB through R321 and can be pulled low by Q4. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, providing the reference for the low-side switch configuration. | </details> <details> <summary><b>Q4</b> - MMBT3904 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/MMBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B | BASE | S5_ENBL | ✅ | Base is correctly connected to S5_ENBL signal, which is pulled up to +V1P8A through R133 and can be pulled low by Q10. | | C | COLLECTOR | +3VSB_EN_L | ✅ | Collector is correctly connected to +3VSB_EN_L to pull the control signal low when Q4 is enabled. | | E | EMITTER | GND | ✅ | Emitter is correctly connected to GND, providing the reference for the NPN transistor configuration. | </details> <details> <summary><b>U13</b> - NB670 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NB670) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | BST | PS3_BST | ❌ | <details><summary>BST pin bootstrap circuit uses non-standard topology with 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. While the capacitor value (0.1µF) matches datasheet recommendation, the series resistance deviates from datasheet typical application which shows direct capacitor connection between BST and SW pins.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="61.70,20.38,69.20,27.88" aspect-ratio="1.29" } <ul><li>Pin 10 (BST) is connected to net PS3_BST <em>(from schematic)</em></li><li>PS3_BST connects to R291 pin 1, R291 pin 2 connects to $22N1498, and C306 connects between $22N1498 and PS3VSB_PHASE (SW node) <em>(from schematic)</em></li><li>The bootstrap circuit path is: BST -&gt; R291 (4.7Ω) -&gt; C306 (0.1µF) -&gt; SW <em>(from schematic)</em></li><li>BST is the bootstrap pin requiring a capacitor between SW and BST pins to form a floating supply across the high-side switch driver <em>(from datasheet <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=5">NB670</a>, page 5)</em></li><li>Datasheet typical application shows 100nF bootstrap capacitor connected directly between BST and SW with no series resistance <em>(from datasheet <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=18">NB670</a>, page 18)</em></li><li>Datasheet layout guidelines recommend keeping BST voltage path (BST, C3, and SW) as short as possible <em>(from datasheet <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=16">NB670</a>, page 16)</em></li><li>The minimum off-time is 350ns typical, and typical switching period at 500kHz is 2µs <em>(from datasheet <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=3">NB670</a>, page 3)</em></li><li>The 4.7Ω resistor with 0.1µF capacitor creates a time constant of 470ns <em>(reasoning)</em></li><li>While some designs use small resistors (&lt;1Ω) in bootstrap circuits for inrush current limiting or EMI reduction, 4.7Ω is significantly higher than typical values <em>(reasoning)</em></li><li>The series resistance adds impedance to the bootstrap charging path, which could impede proper charging especially at higher input voltages with shorter off-times <em>(reasoning)</em></li><li>The circuit deviates from the datasheet recommended topology without documented justification <em>(reasoning)</em></li><li>Recommendation: Remove R291 and connect C306 directly between BST (pin 10) and SW (pins 8/9/15/16) per datasheet typical application, or if series resistance is required for specific EMI/inrush reasons, reduce R291 to &lt;1Ω and document the design rationale <em>(reasoning)</em></li></ul></details> | | 1 | VIN | PS5VSB_VIN | ✅ | VIN pin correctly connected to PS5VSB_VIN input rail with appropriate input capacitors for decoupling. | | 2 | PGND | GND | ✅ | PGND pin correctly connected to ground plane. | | 3 | N/C | | ✅ | N/C pin correctly left unconnected as specified in datasheet. | | 4 | PG | +PS_3VSB_PG | ✅ | PG pin correctly connected with 100kΩ pull-up resistor to PS3_VCC as recommended by datasheet. | | 5 | CLK | $22N1411 | ✅ | CLK pin correctly connected to charge pump circuit through net $22N1411. | | 6 | LDO | PS3_LDO | ✅ | LDO pin correctly connected to 10uF decoupling capacitor C95, exceeding minimum 4.7uF requirement. | | 7 | VOUT | +PS_3VSB | ✅ | VOUT pin correctly connected to output rail +PS_3VSB with appropriate output capacitors. | | 8 | SW1 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3. | | 9 | SW2 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3. | | 15 | SW3 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3. | | 16 | SW4 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switch node and to inductor L3. | | 11 | VCC | PS3_VCC | ✅ | VCC pin correctly connected to 1uF decoupling capacitor C97, meeting minimum requirement. | | 12 | ENLDO | | ✅ | ENLDO pin correctly left floating to enable LDO by default as recommended by datasheet. | | 13 | EN | PS3_EN | ✅ | EN pin correctly connected with 499kΩ pull-up resistor R109 to PS5VSB_VIN for automatic start-up. | | 14 | AGND | GND | ✅ | AGND pin correctly connected to ground plane. | </details> <details> <summary><b>L3</b> - 125-0004501 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/125-0004501) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | Inductor pin 1 correctly connected to PS3VSB_PHASE switch node from U13 pins 8, 9, 15, 16. | | 2 | 2 | +PS_3VSB | ✅ | Inductor pin 2 correctly connected to +PS_3VSB output rail (3.3V). | </details> <details> <summary><b>R291</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3_BST | ✅ | 4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor. This is part of the non-standard bootstrap topology identified at U13 pin 10. | | 2 | 2 | $22N1498 | ✅ | 4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor. This is part of the non-standard bootstrap topology identified at U13 pin 10. | </details> <details> <summary><b>C95</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3_LDO | ✅ | 10µF LDO output decoupling capacitor correctly connected between PS3_LDO (U13 pin 6) and GND, exceeding the minimum 4.7µF requirement. | | 2 | 2 | GND | ✅ | 10µF LDO output decoupling capacitor correctly connected between PS3_LDO (U13 pin 6) and GND, exceeding the minimum 4.7µF requirement. | </details> <details> <summary><b>C97</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3_VCC | ✅ | 1µF VCC decoupling capacitor correctly connected between PS3_VCC (U13 pin 11) and GND, meeting the minimum requirement. | | 2 | 2 | GND | ✅ | 1µF VCC decoupling capacitor correctly connected between PS3_VCC (U13 pin 11) and GND, meeting the minimum requirement. | </details> <details> <summary><b>R119</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB_PG | ✅ | 100kΩ pull-up resistor correctly connected between +PS_3VSB_PG (U13 pin 4) and PS3_VCC for open-drain PG output. | | 2 | 2 | PS3_VCC | ✅ | 100kΩ pull-up resistor correctly connected between +PS_3VSB_PG (U13 pin 4) and PS3_VCC for open-drain PG output. | </details> <details> <summary><b>C306</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | 0.1µF bootstrap capacitor with correct value but connected through non-standard topology with series resistor R291. This is part of the bootstrap circuit issue identified at U13 pin 10. | | 2 | 2 | $22N1498 | ✅ | 0.1µF bootstrap capacitor with correct value but connected through non-standard topology with series resistor R291. This is part of the bootstrap circuit issue identified at U13 pin 10. | </details> <details> <summary><b>R109</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3_EN | ✅ | 499kΩ pull-up resistor correctly connected between PS3_EN (U13 pin 13) and PS5VSB_VIN for EN pin. | | 2 | 2 | PS5VSB_VIN | ✅ | 499kΩ pull-up resistor correctly connected between PS3_EN (U13 pin 13) and PS5VSB_VIN for EN pin. | </details> <details> <summary><b>C85</b> - 0.1uF capacitor ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3_EN | ✅ | C85 is marked DNI (Do Not Install) so it is not electrically present. Datasheet recommends 10nF capacitor from EN to GND for noise filtering, but absence may be intentional design choice. | | 2 | 2 | GND | ✅ | C85 is marked DNI (Do Not Install) so it is not electrically present. Datasheet recommends 10nF capacitor from EN to GND for noise filtering, but absence may be intentional design choice. | </details> <details> <summary><b>C323</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0.1uF decoupling capacitor between GND and +PS_5VSB, providing local power supply filtering for U35. | | 2 | 2 | +PS_5VSB | ✅ | 0.1uF decoupling capacitor between GND and +PS_5VSB, providing local power supply filtering for U35. | </details> <details> <summary><b>R289</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS_OUT_L | ✅ | 1K pull-up resistor between PS_OUT_L and +PS_3VSB, marked DNI (Do Not Install). Component is electrically absent from the circuit. | | 2 | 2 | +PS_3VSB | ✅ | 1K pull-up resistor between PS_OUT_L and +PS_3VSB, marked DNI (Do Not Install). Component is electrically absent from the circuit. | </details> <details> <summary><b>R288</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 5VSB_CTRL | ✅ | 1K pull-up resistor between 5VSB_CTRL and +PS_5VSB, setting default state for U35 SYS5VSB_OFF output. | | 2 | 2 | +PS_5VSB | ✅ | 1K pull-up resistor between 5VSB_CTRL and +PS_5VSB, setting default state for U35 SYS5VSB_OFF output. | </details> <details> <summary><b>U35</b> - NCT3012S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NCT3012S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DeepS5_Sel | S5_SEL | ✅ | DeepS5_Sel pin connected to S5_SEL net with 2.2K pull-up resistor R307 to +PS_5VSB. This pin likely selects between different S5 sleep modes for EuP compliance. | | 2 | VSB | +PS_5VSB | ✅ | VSB pin connected to +PS_5VSB power rail with local decoupling capacitor C323 (0.1uF) to ground. This is the power supply input for the IC. | | 3 | PS_IN# | PB_RES | ✅ | PS_IN# pin connected to PB_RES net with 33 ohm series resistor R308 to FP_PWRBTN. This is the power button input with current limiting and noise filtering. | | 4 | SLP_S5# | SLP_S4_L | ✅ | SLP_S5# pin connected to SLP_S4_L net. This is an active-low sleep state input signal from the system. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA pin connected to DDR_SMB_DATA net. This is the I2C/SMBus data line for communication with DDR memory modules. | | 6 | SCLK | DDR_SMB_CLK | ✅ | SCLK pin connected to DDR_SMB_CLK net. This is the I2C/SMBus clock line for communication with DDR memory modules. | | 7 | PS_OUT# | PS_OUT_L | ✅ | PS_OUT# pin connected to PS_OUT_L net. This is the active-low power supply output control signal. R289 pull-up is DNI. | | 8 | SYS5VSB_OFF | 5VSB_CTRL | ✅ | SYS5VSB_OFF pin connected to 5VSB_CTRL net with 1K pull-up resistor R288 to +PS_5VSB. This output controls 5VSB enable/disable for EuP compliance. Text notes indicate Low=EuP Disable, High=EuP Enable. | | 9 | GND | GND | ✅ | GND pin connected to ground net. This is the ground reference for the IC. | </details> <details> <summary><b>R307</b> - 2221-0023 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | S5_SEL | ✅ | 2.2K pull-up resistor between S5_SEL and +PS_5VSB, setting default high state for U35 DeepS5_Sel input. | | 2 | 2 | +PS_5VSB | ✅ | 2.2K pull-up resistor between S5_SEL and +PS_5VSB, setting default high state for U35 DeepS5_Sel input. | </details> <details> <summary><b>R308</b> - 110-0002012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PB_RES | ✅ | 33 ohm series resistor between PB_RES and FP_PWRBTN, providing current limiting and noise filtering for power button input. | | 2 | 2 | FP_PWRBTN | ✅ | 33 ohm series resistor between PB_RES and FP_PWRBTN, providing current limiting and noise filtering for power button input. | </details> <details> <summary><b>Q12</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN | ✅ | Drain connected to SYS_EN net, which drives the gates of Q6 and Q13. This MOSFET acts as a pull-down switch controlled by SYS_EN_GATE. | | G | GATE | SYS_EN_GATE | ✅ | Gate connected to SYS_EN_GATE, which is controlled by Q7 and R142. This controls when Q12 pulls down SYS_EN. | | S | SOURCE | GND | ✅ | Source connected to GND. This is the correct configuration for an N-channel MOSFET pull-down switch. | </details> <details> <summary><b>Q7</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN_GATE | ✅ | Drain connected to SYS_EN_GATE net, which drives the gate of Q12. This MOSFET acts as a pull-down switch controlled by SLP_S3_L. | | G | GATE | SLP_S3_L | ✅ | Gate connected to SLP_S3_L control signal. This controls when Q7 pulls down SYS_EN_GATE. | | S | SOURCE | GND | ✅ | Source connected to GND. This is the correct configuration for an N-channel MOSFET pull-down switch. | </details> <details> <summary><b>Q6</b> - RXR035N03 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB | ✅ | Drain pin connected to +3VSB input power rail (nominally 3.3V). This is the input side of the high-side switch configuration. | | G | GATE | SYS_EN | ✅ | Gate pin connected to SYS_EN control signal, which is pulled to +10V through R340 (100K) when enabled. VGS of approximately 6.7V when on provides adequate gate drive. | | S | SOURCE | +VCC3 | ✅ | Source pin connected to +VCC3 output rail (nominally 3.3V). This is the output side of the high-side switch, supplying 300mA per the design notes. | </details> <details> <summary><b>Q13</b> - RXR035N03 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +5VSB | ✅ | Drain pin connected to +5VSB input power rail (nominally 5V). This is the input side of the high-side switch configuration. | | G | GATE | SYS_EN | ✅ | Gate pin connected to SYS_EN control signal, which is pulled to +10V through R340 (100K) when enabled. VGS of approximately 5V when on provides adequate gate drive. | | S | SOURCE | +VCC | ✅ | Source pin connected to +VCC output rail (nominally 5V). This is the output side of the high-side switch, supplying 600mA per the design notes. | </details> <details> <summary><b>C367</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC output rail. This is the positive terminal of the output decoupling capacitor. The 6.3V voltage rating provides marginal but acceptable margin for the 5V rail. | | 2 | 2 | GND | ✅ | Connected to GND. This is the negative terminal of the output decoupling capacitor. | </details> <details> <summary><b>C115</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 output rail. This is the positive terminal of the output decoupling capacitor. | | 2 | 2 | GND | ✅ | Connected to GND. This is the negative terminal of the output decoupling capacitor. | </details> <details> <summary><b>Q2</b> - BAV99-7-F-S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | +PS_5VSB | ✅ | Anode 1 connected to +PS_5VSB power rail. This provides the upper clamp voltage reference for the protection circuit. | | 2 | A2 | $22N1417 | ✅ | Anode 2 connected to intermediate node $22N1417. This node is shared with Q9 pin 1 and provides coupling between the two diode arrays. | | 3 | C | $22N1419 | ✅ | Common cathode connected to net $22N1419, which is AC coupled to the clock signal through C72. | </details> <details> <summary><b>Q9</b> - BAV99-7-F-S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | $22N1417 | ✅ | Anode 1 connected to intermediate node $22N1417, shared with Q2 pin 2. This creates a coupling between the two clamping circuits. | | 2 | A2 | +10V | ✅ | Anode 2 connected to +10V power rail. This provides the upper clamp voltage reference at a higher voltage than Q2. | | 3 | C | $22N1467 | ✅ | Common cathode connected to net $22N1467, which is AC coupled to the clock signal through C283. | </details> <details> <summary><b>Q10</b> - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | S5_ENBL | ✅ | Drain pin correctly connected to S5_ENBL net, which drives the base of Q4 through pull-up resistor R133. Functions as the output of a low-side switch controlling the +3VSB enable signal. | | G | GATE | 5VSB_CTRL | ✅ | Gate pin correctly connected to 5VSB_CTRL signal from U35 pin 8 (SYS5VSB_OFF). Includes 1K pull-up to +PS_5VSB and 10K resistor to 5VSB_GATE for proper gate drive. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND, providing the reference point for the N-channel MOSFET in a low-side switch configuration. | </details> <details> <summary><b>U25</b> - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin connected to VR_HOT_L net. This is a thermal alert output that signals when junction temperature exceeds the warning threshold. | | 2 | SDIO | $23N2429 | ✅ | SDIO pin connected to SVID data interface through R80 (16.9Ω) series resistor. Pull-up resistor R85 is DNI, suggesting external pull-ups are provided. | | 3 | ALERT | $23N2431 | ✅ | ALERT pin connected to SVID alert interface through R62 (0Ω). Pull-up resistor R86 is DNI, suggesting external pull-ups are provided. | | 4 | SCLK | $23N2430 | ✅ | SCLK pin connected to SVID clock interface through R81 (20.0Ω) series resistor. Pull-up resistor R87 is DNI, suggesting external pull-ups are provided. | | 5 | GND | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) all connected to AGND-VCORE, which connects to GND through R37 (0Ω) providing star ground connection. | | 32 | GND1 | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) all connected to AGND-VCORE, which connects to GND through R37 (0Ω) providing star ground connection. | | 49 | GND_PAD | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) all connected to AGND-VCORE, which connects to GND through R37 (0Ω) providing star ground connection. | | 6 | VR_RDY | $23N3753 | ✅ | VR_RDY pin connected through R79 (0Ω) to VCORE_PG power good signal with pull-up to +VCC3. | | 7 | VIN1 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 11 | VIN2 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 12 | VIN3 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 13 | VIN4 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 14 | VIN5 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 15 | VIN6 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 16 | VIN7 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 17 | VIN8 | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 50 | VIN_PAD | +5VSB_SW | ✅ | Input voltage pins (VIN1-VIN8, VIN_PAD) all connected to +5VSB_SW with adequate input decoupling capacitors. | | 8 | BST | $23N3711 | ✅ | BST pin connected to bootstrap network with R154 (2.20Ω) and C50 (0.22µF) for high-side gate driver supply. | | 9 | GH | | ✅ | GH pin is the high-side gate driver output. Connection to external MOSFETs cannot be fully verified from this schematic page. | | 10 | SW1 | $23N3731 | ✅ | SW1 pin connected to switch node with bootstrap capacitor C50 for gate driver supply. | | 18 | SW2 | VCORE-SW | ✅ | Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output. | | 25 | SW3 | VCORE-SW | ✅ | Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output. | | 26 | SW4 | VCORE-SW | ✅ | Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output. | | 27 | SW5 | VCORE-SW | ✅ | Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output. | | 28 | SW6 | VCORE-SW | ✅ | Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output. | | 29 | SW7 | VCORE-SW | ✅ | Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output. | | 51 | SW_PAD | VCORE-SW | ✅ | Switch node pins (SW2-SW7, SW_PAD) all connected to VCORE-SW, which connects through L18 (470nH) to +VCORE output. | | 19 | PGND1 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path. | | 20 | PGND2 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path. | | 21 | PGND3 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path. | | 22 | PGND4 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path. | | 23 | PGND5 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path. | | 24 | PGND6 | GND | ✅ | Power ground pins (PGND1-PGND6) all connected to GND for low-impedance power return path. | | 30 | GL | | ✅ | GL pin is the low-side gate driver output. Connection to external MOSFETs cannot be fully verified from this schematic page. | | 31 | VBOOT | $23N3477 | ✅ | VBOOT pin connected through R70 (88.7kΩ) to AGND-VCORE to set boot voltage to 1.1V and I2C address to 0x0 per text note. | | 33 | VCCP | $23N3625 | ✅ | VCCP pin connected to +5VSB through R845 (1.00Ω) with C48 (4.7µF) decoupling for charge pump supply. | | 34 | TSENSE | $23N3665 | ✅ | TSENSE pin connected to temperature sensing network with TH2 (100kΩ thermistor) and R131 (14.0kΩ) forming voltage divider. | | 35 | IMAX | $23N3681 | ✅ | IMAX pin connected through R105 (44.2kΩ) to AGND-VCORE to set maximum current limit to 14A per text note. | | 36 | IOUT | $23N3683 | ✅ | IOUT pin connected through R146 (16.5kΩ) to AGND-VCORE with C47 (470pF) filtering for output current monitoring. | | 37 | ILIM | VCORE-ILIM | ✅ | ILIM pin connected to current limit network with R95 (15.0kΩ) to VCORE-CSCOMP for current limit setting. | | 38 | CSCOMP | VCORE-CSCOMP | ✅ | CSCOMP pin connected to current sense compensation network with C39 (470pF) and C40 (2200pF) to VCORE-CSSUM, plus temperature-dependent limiting via TH1. | | 39 | CSSUM | VCORE-CSSUM | ✅ | CSSUM pin connected to current sense sum network with DCR sensing through R107 (100kΩ) to switch node via SP3. | | 40 | CSREF | VCORE-CSREF | ✅ | CSREF pin connected to current sense reference network with R108 (10.0Ω) to output voltage via SP4 and C45 (1000pF) filtering. | | 41 | FREQ | $23N2930 | ✅ | FREQ pin connected through R93 (18.7kΩ) to AGND-VCORE to set switching frequency to 650kHz per text note. | | 42 | COMP | VCORE-COMP | ✅ | COMP pin connected to voltage loop compensation network with Type III compensation using C35 (47pF) and C37 (2200pF). | | 43 | FB | VCORE-FB | ✅ | FB pin connected to feedback network with R88 (3.01kΩ), R89 (1.00kΩ), and compensation capacitors for voltage regulation. | | 44 | DIFFOUT | VCORE-DIFFOUT | ✅ | DIFFOUT pin connected to differential amplifier output network with R89 (1.00kΩ), R90 (47Ω), and C36 (220pF). | | 45 | VSN | VR-VCORE-VSN | ✅ | VSN pin connected to negative remote sense with R65 (10.0Ω) filtering and R64 (0Ω) allowing connection to VSS_SENSE. | | 46 | VSP | VR-VCORE-VSP | ✅ | VSP pin connected to positive remote sense with R92 (100Ω) to +VCORE and R63 (0Ω) allowing connection to VCC_SENSE. | | 47 | VCC | $23N3860 | ✅ | VCC pin connected to +5VSB through R166 (2.20Ω) with C24 (1.0µF) decoupling for main IC supply. | | 48 | EN | $23N5607 | ✅ | EN pin connected to +VCC through R849 (0Ω) with R851 (10.0kΩ) pull-down and C433 (0.1µF) filtering for enable control. | </details> <details> <summary><b>L18</b> - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Pin 1 connects to the switching node VCORE-SW from the buck converter controller U25. This is the correct input connection for the output filter inductor. | | 2 | 2 | +VCORE | ✅ | Pin 2 connects to the output voltage rail +VCORE. This is the correct output connection for the filter inductor. | </details> <details> <summary><b>L8</b> - 3120-0183 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3120-0183) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to the +5VSB input supply. This is the correct source connection for an input filter inductor. | | 2 | 2 | +5VSB_SW | ✅ | Pin 2 connects to +5VSB_SW, which supplies the VCORE controller U25. This is the correct load connection for the input filter inductor. | </details> <details> <summary><b>R88</b> - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2824 | ✅ | Connected to internal compensation node $23N2824, forming part of a Type III compensation network with C37. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB feedback net, completing the compensation network path to the FB pin of U25. | </details> <details> <summary><b>R89</b> - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB, providing a DC path from the feedback node to the differential output. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT, forming a resistive path to U25 pin 44 for differential sensing. | </details> <details> <summary><b>R90</b> - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2818 | ✅ | Connected to internal node $23N2818, which is part of the AC coupling path from FB through C36. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT, completing the AC-coupled path to the differential output pin. | </details> <details> <summary><b>C35</b> - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP, the compensation pin of the voltage regulator U25. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB, providing direct high-frequency compensation between COMP and FB pins. | </details> <details> <summary><b>C36</b> - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB, providing AC coupling from the feedback node. | | 2 | 2 | $23N2818 | ✅ | Connected to internal node $23N2818, forming a series AC path with R90 to DIFFOUT. | </details> <details> <summary><b>C37</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP, forming part of the Type III compensation network. | | 2 | 2 | $23N2824 | ✅ | Connected to internal node $23N2824, forming a series RC compensation path with R88. | </details> <details> <summary><b>SP3</b> - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | PCB bridge short connecting the switching node (VCORE-SW) to the current sense network ($23N3209) for DCR-based current measurement. This is a correct implementation of inductor DCR current sensing. | | 2 | 2 | $23N3209 | ✅ | PCB bridge short connecting the switching node (VCORE-SW) to the current sense network ($23N3209) for DCR-based current measurement. This is a correct implementation of inductor DCR current sensing. | </details> <details> <summary><b>TH1</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Thermistor connected between CSCOMP and the divider node ($23N3115), providing temperature-dependent current limiting. Connection is correct. | | 2 | 2 | $23N3115 | ✅ | Thermistor connected between CSCOMP and the divider node ($23N3115), providing temperature-dependent current limiting. Connection is correct. | </details> <details> <summary><b>R92</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | 100 ohm resistor providing local +VCORE reference for the positive remote sense path. Connects +VCORE to VSP of U25. | | 2 | 2 | VR-VCORE-VSP | ✅ | 100 ohm resistor providing local +VCORE reference for the positive remote sense path. Connects +VCORE to VSP of U25. | </details> <details> <summary><b>R91</b> - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 100 ohm resistor providing local ground reference for the negative remote sense path. Connects GND to the negative sense node which feeds VSN through R65. | | 2 | 2 | $23N2860 | ✅ | 100 ohm resistor providing local ground reference for the negative remote sense path. Connects GND to the negative sense node which feeds VSN through R65. | </details> <details> <summary><b>R63</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_SENSE | ✅ | 0 ohm jumper enabling remote positive voltage sensing from VCC_SENSE point. When populated, allows sensing at the load rather than at the regulator output. | | 2 | 2 | VR-VCORE-VSP | ✅ | 0 ohm jumper enabling remote positive voltage sensing from VCC_SENSE point. When populated, allows sensing at the load rather than at the regulator output. | </details> <details> <summary><b>R64</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VSS_SENSE | ✅ | 0 ohm jumper enabling remote negative voltage sensing from VSS_SENSE point. When populated, allows sensing at the load ground rather than local ground. | | 2 | 2 | $23N2860 | ✅ | 0 ohm jumper enabling remote negative voltage sensing from VSS_SENSE point. When populated, allows sensing at the load ground rather than local ground. | </details> <details> <summary><b>R65</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | 10 ohm series resistor connecting the negative sense node to VSN input of U25. Creates asymmetry with positive sense path, likely intentional for filtering or stability. | | 2 | 2 | VR-VCORE-VSN | ✅ | 10 ohm series resistor connecting the negative sense node to VSN input of U25. Creates asymmetry with positive sense path, likely intentional for filtering or stability. | </details> <details> <summary><b>R131</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to the thermistor network junction, forming a parallel path with TH2 to limit maximum resistance and set the temperature sensing range. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the parallel resistor path. | </details> <details> <summary><b>R78</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | Connected to TSENSE pin of U25 and bypass capacitor C46, serving as the input to the temperature sensing network. | | 2 | 2 | $23N3662 | ✅ | Connected to the thermistor network junction, completing the series path from TSENSE to the temperature sensing elements. | </details> <details> <summary><b>TH2</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to the thermistor network junction with R131 and R78, forming the temperature-dependent voltage divider node for the TSENSE circuit. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the temperature sensing voltage divider. | </details> <details> <summary><b>C46</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | Connected to TSENSE pin of U25, providing noise filtering and stability for the temperature sensing input. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing proper analog ground reference for the bypass capacitor to minimize noise coupling. | </details> <details> <summary><b>R80</b> - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Pin 1 connects to the external SVID_DATA-R signal. This is the input side of the series resistor for the SVID data line. | | 2 | 2 | $23N2429 | ✅ | Pin 2 connects to U25 pin 2 (SDIO) through net $23N2429. This is the controller side of the series resistor. | </details> <details> <summary><b>R81</b> - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Pin 1 connects to the external SVID_CLK-R signal. This is the input side of the series resistor for the SVID clock line. | | 2 | 2 | $23N2430 | ✅ | Pin 2 connects to U25 pin 4 (SCLK) through net $23N2430. This is the controller side of the series resistor. | </details> <details> <summary><b>R62</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Pin 1 connects to the external SVID_ALERT-R signal. This is the input side of the series resistor (0 ohm jumper) for the SVID alert line. | | 2 | 2 | $23N2431 | ✅ | Pin 2 connects to U25 pin 3 (ALERT) through net $23N2431. This is the controller side of the series resistor. | </details> <details> <summary><b>C50</b> - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3733 | ✅ | Connected to R154 pin 2, receiving the bootstrap supply through the current-limiting resistor. | | 2 | 2 | $23N3731 | ✅ | Connected to U25 pin 10 (SW1), completing the bootstrap circuit between BST and SW pins. | </details> <details> <summary><b>R154</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3711 | ✅ | Connected to U25 pin 8 (BST) as part of the bootstrap circuit for the high-side gate driver. | | 2 | 2 | $23N3733 | ✅ | Connected to C50 pin 1, forming the intermediate node between the bootstrap resistor and capacitor. | </details> <details> <summary><b>R93</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2930 | ✅ | Connected to U25 pin 41 (FREQ) to set the switching frequency of the NCP81109 controller. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE (analog ground) to complete the frequency setting resistor configuration. | </details> <details> <summary><b>R146</b> - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3683 | ✅ | Connected to U25 pin 36 (IOUT) for output current monitoring. This resistor scales the current monitor output signal. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing the ground reference for the current monitor circuit. | </details> <details> <summary><b>R105</b> - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3681 | ✅ | Connected to U25 pin 35 (IMAX) to set the maximum current limit. The design note indicates a target of 14A, but datasheet verification is needed to confirm the 44.2K value achieves this. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing the ground reference for the current limit setting circuit. | </details> <details> <summary><b>C47</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3683 | ✅ | Connected to U25 pin 36 (IOUT) for filtering the current monitor output signal. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, providing the ground reference for the filter capacitor. | </details> <details> <summary><b>C433</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ✅ | Connected to the enable pin (pin 48) of U25 through net $23N5607. This pin provides filtering for the enable signal. | | 2 | 2 | GND | ✅ | Connected to GND. This pin provides the ground reference for the filter capacitor. | </details> <details> <summary><b>R851</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ✅ | Connected to the enable pin (pin 48) of U25 through net $23N5607. This pin provides the pull-down function for the enable circuit. | | 2 | 2 | GND | ✅ | Connected to GND. This pin provides the ground reference for the pull-down resistor. | </details> <details> <summary><b>R849</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC control voltage. This pin sources the enable signal for the regulator. | | 2 | 2 | $23N5607 | ✅ | Connected to the enable pin (pin 48) of U25 through net $23N5607. This pin drives the enable input of the NCP81109GMNTXG regulator. | </details> <details> <summary><b>R167</b> - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Pin 1 connects to +VCC3 supply rail, providing pull-up voltage for the power good signal. This connection is correct. | | 2 | 2 | VCORE_PG | ✅ | Pin 2 connects to VCORE_PG net, providing pull-up for the power good signal. This connection is correct. | </details> <details> <summary><b>R79</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Pin 1 connects to VCORE_PG net, which is the power good signal for the VCORE regulator. This connection is correct. | | 2 | 2 | $23N3753 | ✅ | Pin 2 connects to U25 pin 6 (VR_RDY), which is the voltage regulator ready output. This connection is correct. | </details> <details> <summary><b>C25</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Pin 1 connects to VCORE_PG net for filtering. This connection is correct. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing filtering to ground for the power good signal. This connection is correct. | </details> <details> <summary><b>D4</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Incorrect part variant used. BAT54A has common anode configuration (pin 3 = anode, pins 1&2 = cathodes) which creates an AND gate, but the circuit requires common cathode configuration (BAT54C) for proper OR gate operation of power good signals. | | 2 | 2 | VGFX_PG | ✅ | Incorrect part variant used. BAT54A has common anode configuration (pin 3 = anode, pins 1&2 = cathodes) which creates an AND gate, but the circuit requires common cathode configuration (BAT54C) for proper OR gate operation of power good signals. | | 3 | 3 | VCORE_GFX_PG | ✅ | Incorrect part variant used. BAT54A has common anode configuration (pin 3 = anode, pins 1&2 = cathodes) which creates an AND gate, but the circuit requires common cathode configuration (BAT54C) for proper OR gate operation of power good signals. | </details> <details> <summary><b>R94</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | Connected to VCORE_GFX_PG combined power good signal. Pull-up resistor configuration is correct for OR gate, but effectiveness depends on correct diode part selection. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 supply rail. Correct connection for pull-up resistor function. | </details> <details> <summary><b>C65</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Correct connection for decoupling capacitor. | | 2 | 2 | VCORE_GFX_PG | ✅ | Connected to VCORE_GFX_PG combined power good signal. Provides filtering on the digital signal. | </details> <details> <summary><b>R166</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This is the input side of the series resistor feeding the VCC pin of the controller. | | 2 | 2 | $23N3860 | ✅ | Connected to net $23N3860 which feeds the VCC pin of U25 and is decoupled by C24. This provides filtered power to the controller IC. | </details> <details> <summary><b>C24</b> - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3860 | ✅ | Connected to net $23N3860, the VCC supply node for U25. Provides decoupling for the controller IC's main supply voltage. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE, the analog ground for the VCORE regulator. This is the correct ground reference for the analog supply of the controller. | </details> <details> <summary><b>R845</b> - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This is the input side of the series resistor feeding the VCCP pin of the controller. | | 2 | 2 | $23N3625 | ✅ | Connected to net $23N3625 which feeds the VCCP pin of U25 and is decoupled by C48. This provides filtered power to the charge pump circuitry. | </details> <details> <summary><b>C48</b> - 2232-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3625 | ✅ | Connected to net $23N3625, the VCCP supply node for U25. Provides decoupling for the controller's charge pump supply voltage. | | 2 | 2 | GND | ✅ | Connected to GND, the power ground. This is the correct ground reference for the charge pump supply which is part of the power stage. | </details> <details> <summary><b>R70</b> - 1120-0289 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3477 | ✅ | Connected to VBOOT pin (pin 31) of U25 via net $23N3477. This resistor is part of a configuration circuit to set VBOOT to 1.1V for address configuration. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE (analog ground for the VCORE regulator section). This provides the ground reference for the VBOOT configuration circuit. | </details> <details> <summary><b>R37</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0-ohm jumper connecting power ground (GND) to analog ground (AGND-VCORE) at a single point. This is correct practice for mixed-signal power supply designs. | | 2 | 2 | AGND-VCORE | ✅ | 0-ohm jumper connecting power ground (GND) to analog ground (AGND-VCORE) at a single point. This is correct practice for mixed-signal power supply designs. | </details> <details> <summary><b>C87</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | | | ✅ | Negative terminal correctly connected to GND for output filtering. | | P | | | ✅ | Positive terminal correctly connected to +VCORE output rail for bulk capacitance. | </details> <details> <summary><b>C89</b> - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | | 2 | 2 | GND | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | </details> <details> <summary><b>C88</b> - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | | 2 | 2 | GND | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | </details> <details> <summary><b>C102</b> - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | | 2 | 2 | GND | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | </details> <details> <summary><b>R853</b> - 1130-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Resistor correctly connected between +VCORE and GND, likely serving as a pre-load or damping resistor. | | 2 | 2 | GND | ✅ | Resistor correctly connected between +VCORE and GND, likely serving as a pre-load or damping resistor. | </details> <details> <summary><b>C90</b> - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | | 2 | 2 | GND | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | </details> <details> <summary><b>C101</b> - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | | 2 | 2 | GND | ✅ | Ceramic output capacitor correctly connected between +VCORE and GND for output filtering. | </details> <details> <summary><b>U26</b> - NCP81109GMNTXG ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 9 | GH | | ❌ | <details><summary>GH (pin 9) and GL (pin 30) show no net connections. This is a critical error as these gate driver outputs must be connected to drive external MOSFETs.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="37.39,41.25,44.89,48.75" aspect-ratio="1.29" } <ul><li>Pin 9 (GH) and pin 30 (GL) both show empty string for net connections <em>(from schematic)</em></li><li>GH is the high-side gate driver output and GL is the low-side gate driver output <em>(reasoning)</em></li><li>Pin 8 (BST) is connected to a bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) that connects to switch node pin 10 (SW1) <em>(from schematic)</em></li><li>The presence of a bootstrap circuit is definitive evidence that external MOSFETs are required, as bootstrap circuits are only needed to provide gate drive voltage for external high-side MOSFETs <em>(reasoning)</em></li><li>The controller has separate power ground pins (PGND1-PGND6 on pins 19-24) distinct from signal ground, which is typical for controllers with external MOSFETs <em>(from schematic)</em></li><li>Multiple switch node pins (SW1-SW7) and separate gate driver outputs indicate a multiphase controller with external power stage <em>(reasoning)</em></li><li>Text note &#x27;IMAX = 24A&#x27; near the inductor area suggests high current capability requiring external MOSFETs <em>(from schematic)</em></li><li>If MOSFETs were integrated, there would be no need for external gate driver pins, bootstrap circuit, or separate power ground pins <em>(reasoning)</em></li><li>The empty net names suggest missing connections rather than off-page connections, as other nets in the design have proper net names <em>(reasoning)</em></li><li>Without connections to GH and GL, the external MOSFETs cannot be driven and the converter will not function <em>(reasoning)</em></li></ul></details> | | 30 | GL | | ❌ | <details><summary>GH (pin 9) and GL (pin 30) show no net connections. This is a critical error as these gate driver outputs must be connected to drive external MOSFETs.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="47.39,39.49,54.89,46.99" aspect-ratio="1.29" } <ul><li>Pin 9 (GH) and pin 30 (GL) both show empty string for net connections <em>(from schematic)</em></li><li>GH is the high-side gate driver output and GL is the low-side gate driver output <em>(reasoning)</em></li><li>Pin 8 (BST) is connected to a bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) that connects to switch node pin 10 (SW1) <em>(from schematic)</em></li><li>The presence of a bootstrap circuit is definitive evidence that external MOSFETs are required, as bootstrap circuits are only needed to provide gate drive voltage for external high-side MOSFETs <em>(reasoning)</em></li><li>The controller has separate power ground pins (PGND1-PGND6 on pins 19-24) distinct from signal ground, which is typical for controllers with external MOSFETs <em>(from schematic)</em></li><li>Multiple switch node pins (SW1-SW7) and separate gate driver outputs indicate a multiphase controller with external power stage <em>(reasoning)</em></li><li>Text note &#x27;IMAX = 24A&#x27; near the inductor area suggests high current capability requiring external MOSFETs <em>(from schematic)</em></li><li>If MOSFETs were integrated, there would be no need for external gate driver pins, bootstrap circuit, or separate power ground pins <em>(reasoning)</em></li><li>The empty net names suggest missing connections rather than off-page connections, as other nets in the design have proper net names <em>(reasoning)</em></li><li>Without connections to GH and GL, the external MOSFETs cannot be driven and the converter will not function <em>(reasoning)</em></li></ul></details> | | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin correctly connected to VR_HOT_L for thermal alert signaling. | | 2 | SDIO | $24N3490 | ✅ | SDIO pin correctly connected to SVID data line with series resistor and pull-up. | | 3 | ALERT | $24N3492 | ✅ | ALERT pin correctly connected to SVID alert line through 0Ω resistor. | | 4 | SCLK | $24N3491 | ✅ | SCLK pin correctly connected to SVID clock line with series resistor and pull-up. | | 5 | GND | AGND-VGFX | ✅ | GND pin correctly connected to analog ground with 0Ω jumper to main ground. | | 6 | VR_RDY | $24N3598 | ✅ | VR_RDY pin correctly connected as power good output with pull-up and filtering. | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 pins correctly connected to +5VSB_SW input supply with adequate decoupling. | | 8 | BST | $24N3593 | ✅ | BST pin correctly connected to bootstrap circuit for high-side gate driver. | | 10 | SW1 | $24N3595 | ✅ | SW1 pin correctly connected to switch node with bootstrap capacitor. | | 18 | SW2 | VGFX-SW | ✅ | SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation. | | 25 | SW3 | VGFX-SW | ✅ | SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation. | | 26 | SW4 | VGFX-SW | ✅ | SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation. | | 27 | SW5 | VGFX-SW | ✅ | SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation. | | 28 | SW6 | VGFX-SW | ✅ | SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation. | | 29 | SW7 | VGFX-SW | ✅ | SW2-SW7 pins correctly connected to common switch node VGFX-SW for multiphase operation. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 pins correctly connected to main ground plane. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 pins correctly connected to main ground plane. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 pins correctly connected to main ground plane. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 pins correctly connected to main ground plane. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 pins correctly connected to main ground plane. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 pins correctly connected to main ground plane. | | 31 | VBOOT | $24N3564 | ✅ | VBOOT pin correctly configured with resistor to ground for voltage setting and I2C address. | | 32 | GND1 | AGND-VGFX | ✅ | GND1 pin correctly connected to analog ground. | | 33 | VCCP | $24N3578 | ✅ | VCCP pin correctly powered from +5VSB through series resistor with decoupling. | | 34 | TSENSE | $24N3584 | ✅ | TSENSE pin correctly configured with thermistor network for temperature monitoring. | | 35 | IMAX | $24N3588 | ✅ | IMAX pin correctly configured with resistor to set maximum current limit to 14A. | | 36 | IOUT | $24N3589 | ✅ | IOUT pin correctly configured for output current monitoring with resistor and filter capacitor. | | 37 | ILIM | VGFX-ILIM | ✅ | ILIM pin correctly connected to current limit compensation network. | | 38 | CSCOMP | VGFX-CSCOMP | ✅ | CSCOMP pin correctly configured with temperature-compensated current sense network. | | 39 | CSSUM | VGFX-CSSUM | ✅ | CSSUM pin correctly connected to summed current sense network with compensation. | | 40 | CSREF | VGFX-CSREF | ✅ | CSREF pin correctly connected to output voltage through resistor for current sense reference. | | 41 | FREQ | $24N3542 | ✅ | FREQ pin correctly configured with resistor to set switching frequency to 650kHz. | | 42 | COMP | VGFX-COMP | ✅ | COMP pin correctly configured with voltage loop compensation network. | | 43 | FB | VGFX-FB | ✅ | FB pin correctly configured with feedback divider and compensation network. | | 44 | DIFFOUT | VGFX-DIFFOUT | ✅ | DIFFOUT pin correctly connected to differential amplifier network for remote sensing. | | 45 | VSN | VR-VGFX-VSN | ✅ | VSN pin correctly configured for negative remote voltage sensing with DAC feed-forward. | | 46 | VSP | VR-VGFX-VSP | ✅ | VSP pin correctly configured for positive remote voltage sensing. | | 47 | VCC | $24N3610 | ✅ | VCC pin correctly powered from +5VSB through series resistor with decoupling. | | 48 | EN | $24N6011 | ✅ | EN pin correctly configured with pull-down for enable control. | | 49 | GND_PAD | AGND-VGFX | ✅ | GND_PAD correctly connected to analog ground for thermal and electrical performance. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN_PAD correctly connected to input power supply for current distribution. | | 51 | SW_PAD | VGFX-SW | ✅ | SW_PAD correctly connected to switch node for current distribution. | </details> <details> <summary><b>L4</b> - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Inductor input correctly connected to switch node VGFX-SW. | | 2 | 2 | +VGFX | ✅ | Inductor output correctly connected to +VGFX output rail with adequate bulk and ceramic capacitance. | </details> <details> <summary><b>C76</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal correctly connected to +VGFX output rail. | | 2 | N | GND | ✅ | Negative terminal correctly connected to ground. | </details> <details> <summary><b>C77</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | Positive terminal correctly connected to +VGFX output rail. | | 2 | N | GND | ✅ | Negative terminal correctly connected to ground. | </details> <details> <summary><b>TH4</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | Thermistor correctly connected to temperature sense network for U26 TSENSE pin. | | 2 | 2 | GND | ✅ | Thermistor correctly connected to ground to complete voltage divider. | </details> <details> <summary><b>TH3</b> - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Thermistor correctly connected to current sense compensation network for temperature compensation. | | 2 | 2 | $24N3557 | ✅ | Thermistor correctly connected to intermediate node in compensation network. | </details> <details> <summary><b>R224</b> - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSSUM | ✅ | Resistor connects CSSUM pin to the switch node for DCR (DC resistance) current sensing. | | 2 | 2 | $24N3558 | ✅ | Resistor connects CSSUM pin to the switch node for DCR (DC resistance) current sensing. | </details> <details> <summary><b>R223</b> - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3557 | ✅ | Resistor completes the current sense compensation divider network, connecting the intermediate node to CSSUM pin. | | 2 | 2 | VGFX-CSSUM | ✅ | Resistor completes the current sense compensation divider network, connecting the intermediate node to CSSUM pin. | </details> <details> <summary><b>R205</b> - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Resistor connects CSCOMP pin to an intermediate node in the current sense compensation network, working with thermistor TH3 for temperature compensation. | | 2 | 2 | $24N3557 | ✅ | Resistor connects CSCOMP pin to an intermediate node in the current sense compensation network, working with thermistor TH3 for temperature compensation. | </details> <details> <summary><b>R207</b> - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3588 | ✅ | Resistor connects IMAX pin to analog ground to set the maximum current limit. Text note indicates target of 14A. | | 2 | 2 | AGND-VGFX | ✅ | Resistor connects IMAX pin to analog ground to set the maximum current limit. Text note indicates target of 14A. | </details> <details> <summary><b>R225</b> - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Low-value resistor connects CSREF pin to the output voltage for DCR current sensing reference. | | 2 | 2 | $24N3559 | ✅ | Low-value resistor connects CSREF pin to the output voltage for DCR current sensing reference. | </details> <details> <summary><b>R227</b> - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | Resistor connects IOUT pin to analog ground for current monitoring, with C184 in parallel for filtering. | | 2 | 2 | AGND-VGFX | ✅ | Resistor connects IOUT pin to analog ground for current monitoring, with C184 in parallel for filtering. | </details> <details> <summary><b>C113</b> - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Compensation capacitor connected between CSCOMP and CSSUM pins for current loop stability. | | 2 | 2 | VGFX-CSSUM | ✅ | Compensation capacitor connected between CSCOMP and CSSUM pins for current loop stability. | </details> <details> <summary><b>C167</b> - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Filter capacitor connected between CSREF pin and ground for current sense reference filtering. | | 2 | 2 | GND | ✅ | Filter capacitor connected between CSREF pin and ground for current sense reference filtering. | </details> <details> <summary><b>R204</b> - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-ILIM | ✅ | Resistor connects ILIM pin to CSCOMP pin of the controller, forming part of the current limit compensation network. | | 2 | 2 | VGFX-CSCOMP | ✅ | Resistor connects ILIM pin to CSCOMP pin of the controller, forming part of the current limit compensation network. | </details> <details> <summary><b>C166</b> - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Additional compensation capacitor in parallel with C113 between CSCOMP and CSSUM pins. | | 2 | 2 | VGFX-CSSUM | ✅ | Additional compensation capacitor in parallel with C113 between CSCOMP and CSSUM pins. | </details> <details> <summary><b>R850</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | 0Ω jumper resistor connecting +VCC power rail to the enable pin (EN, pin 48) of U26 voltage regulator through net $24N6011. This enables the regulator when +VCC is present. | | 2 | 2 | $24N6011 | ✅ | 0Ω jumper resistor connecting +VCC power rail to the enable pin (EN, pin 48) of U26 voltage regulator through net $24N6011. This enables the regulator when +VCC is present. | </details> <details> <summary><b>R852</b> - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | 10kΩ pull-down resistor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This ensures the enable pin is at a defined low state when +VCC is absent or during power-up. | | 2 | 2 | GND | ✅ | 10kΩ pull-down resistor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This ensures the enable pin is at a defined low state when +VCC is absent or during power-up. | </details> <details> <summary><b>C434</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | 0.1µF decoupling capacitor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This provides noise filtering to prevent false triggering of the enable input. | | 2 | 2 | GND | ✅ | 0.1µF decoupling capacitor connecting the enable pin (EN, pin 48) of U26 to ground through net $24N6011. This provides noise filtering to prevent false triggering of the enable input. | </details> <details> <summary><b>SP2</b> - PCB_BRIDGE_SHORT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to VGFX-SW switching node. This short provides a connection from the switching node to the current sense sum circuit. | | 2 | 2 | $24N3558 | ✅ | Connected to $24N3558 which leads to VGFX-CSSUM through R224. This completes the current sense sum connection. | </details> <details> <summary><b>R231</b> - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to VGFX-SW switching node. This is the input to an RC snubber network. | | 2 | 2 | $24N3623 | ✅ | Connected to intermediate net $24N3623 which connects to C187, completing the RC snubber to ground. | </details> <details> <summary><b>C187</b> - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3623 | ✅ | Connected to intermediate net $24N3623 from R231, forming the capacitive element of the RC snubber. | | 2 | 2 | GND | ✅ | Connected to GND, completing the snubber path from switching node to ground. | </details> <details> <summary><b>SP1</b> - PCB_BRIDGE_SHORT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Connected to +VGFX output. This short provides a connection from the output to the current sense reference circuit. | | 2 | 2 | $24N3559 | ✅ | Connected to $24N3559 which leads to VGFX-CSREF through R225. This completes the current sense reference connection. | </details> <details> <summary><b>R854</b> - 1130-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Connected to +VGFX output voltage. This resistor provides a minimum load for the DC/DC converter. | | 2 | 2 | GND | ✅ | Connected to GND, completing the minimum load path. | </details> <details> <summary><b>R228</b> - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3593 | ✅ | Connected to U26 pin 8 (BST) for bootstrap circuit. This connection is correct for providing bootstrap power to the high-side gate driver. | | 2 | 2 | $24N3596 | ✅ | Connected through C186 to U26 pin 10 (SW1). This forms the bootstrap circuit with R228 limiting inrush current to the bootstrap capacitor. | </details> <details> <summary><b>C186</b> - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3596 | ✅ | Connected through R228 to U26 pin 8 (BST). This is the positive terminal of the bootstrap capacitor. | | 2 | 2 | $24N3595 | ✅ | Connected to U26 pin 10 (SW1). This is the negative terminal of the bootstrap capacitor, correctly connected to the switch node. | </details> <details> <summary><b>C60</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG net, providing filtering for the power good signal. | | 2 | 2 | GND | ✅ | Connected to GND, providing the return path for the bypass capacitor. | </details> <details> <summary><b>R230</b> - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 power rail, providing pull-up voltage for the power good signal. | | 2 | 2 | VGFX_PG | ✅ | Connected to VGFX_PG net, pulling up the power good signal to +VCC3. | </details> <details> <summary><b>R184</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG net, which is the power good signal output from the voltage regulator. | | 2 | 2 | $24N3598 | ✅ | Connected to U26 pin 6 (VR_RDY), the voltage regulator ready output signal. | </details> <details> <summary><b>R203</b> - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3542 | ✅ | Pin 1 connects to the FREQ pin (pin 41) of U26 (NCP81109GMNTXG voltage regulator) to set the switching frequency. A nearby text note indicates the target frequency is 650 kHz. | | 2 | 2 | AGND-VGFX | ✅ | Pin 2 connects to AGND-VGFX, which is the analog ground for the VGFX power domain, providing the ground reference for the frequency-setting resistor. | </details> <details> <summary><b>R170</b> - 1120-0009 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3564 | ❌ | <details><summary>R170 is configured as a pull-down resistor from VBOOT to ground. However, a text note indicates VBOOT should be 1.1V to set ADDR to 0x1, which is inconsistent with a pull-down to ground.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="54.66,40.08,62.16,47.58" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net $24N3564, which connects to U26 pin 31 (VBOOT) <em>(from schematic)</em></li><li>Pin 2 is connected to AGND-VGFX (analog ground) <em>(from schematic)</em></li><li>R170 is a 100K resistor configured as a pull-down from VBOOT to ground <em>(reasoning)</em></li><li>A text note on the schematic states &#x27;VBOOT = 1.1V ADDR = 0x1&#x27; <em>(from schematic)</em></li><li>The text note indicates that to achieve address 0x1, VBOOT should be at 1.1V <em>(reasoning)</em></li><li>A pull-down resistor to ground would set VBOOT to approximately 0V, not 1.1V <em>(reasoning)</em></li><li>The pull-down configuration is inconsistent with the text note requirement of VBOOT = 1.1V for address 0x1 <em>(reasoning)</em></li><li>Without the NCP81109GMNTXG datasheet, the exact VBOOT configuration requirements cannot be verified <em>(reasoning)</em></li><li>To set VBOOT to 1.1V, a pull-up to a 1.1V supply or a voltage divider would be needed instead of a pull-down <em>(reasoning)</em></li><li>The design team should verify the intended address setting and update either the circuit or the text note to resolve the inconsistency <em>(reasoning)</em></li></ul></details> | | 2 | 2 | AGND-VGFX | ❌ | <details><summary>R170 is configured as a pull-down resistor from VBOOT to ground. However, a text note indicates VBOOT should be 1.1V to set ADDR to 0x1, which is inconsistent with a pull-down to ground.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="54.66,41.84,62.16,49.34" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net $24N3564, which connects to U26 pin 31 (VBOOT) <em>(from schematic)</em></li><li>Pin 2 is connected to AGND-VGFX (analog ground) <em>(from schematic)</em></li><li>R170 is a 100K resistor configured as a pull-down from VBOOT to ground <em>(reasoning)</em></li><li>A text note on the schematic states &#x27;VBOOT = 1.1V ADDR = 0x1&#x27; <em>(from schematic)</em></li><li>The text note indicates that to achieve address 0x1, VBOOT should be at 1.1V <em>(reasoning)</em></li><li>A pull-down resistor to ground would set VBOOT to approximately 0V, not 1.1V <em>(reasoning)</em></li><li>The pull-down configuration is inconsistent with the text note requirement of VBOOT = 1.1V for address 0x1 <em>(reasoning)</em></li><li>Without the NCP81109GMNTXG datasheet, the exact VBOOT configuration requirements cannot be verified <em>(reasoning)</em></li><li>To set VBOOT to 1.1V, a pull-up to a 1.1V supply or a voltage divider would be needed instead of a pull-down <em>(reasoning)</em></li><li>The design team should verify the intended address setting and update either the circuit or the text note to resolve the inconsistency <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>C168</b> - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | Connected to TSENSE pin of U26 via net $24N3584. Provides filtering for the temperature sensing circuit. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, providing a ground reference for the TSENSE filter capacitor. | </details> <details> <summary><b>R178</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | Connected to TSENSE pin of U26 via net $24N3584. Acts as a 0-ohm series connection between TSENSE and the temperature sensing network. | | 2 | 2 | $24N3583 | ✅ | Connected to the temperature sensing network via net $24N3583, which includes thermistor TH4 and parallel resistor R226. | </details> <details> <summary><b>R226</b> - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | Connected to the temperature sensing network via net $24N3583, in parallel with thermistor TH4. | | 2 | 2 | GND | ✅ | Connected to GND, completing the temperature sensing voltage divider network. | </details> <details> <summary><b>R66</b> - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0-ohm jumper connecting main power ground (GND) to analog ground (AGND-VGFX), providing single-point ground connection for the DC-DC converter. | | 2 | 2 | AGND-VGFX | ✅ | 0-ohm jumper connecting main power ground (GND) to analog ground (AGND-VGFX), providing single-point ground connection for the DC-DC converter. | </details> <details> <summary><b>U41</b> - RT8207 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.richtek.com/SaveDownload.aspx?specid=RT8207P) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/RT8207) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 12 | TON | $25N1081 | ❌ | <details><summary>TON pin has incorrect resistor value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency. Current value results in ~500kHz operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="38.98,39.78,46.48,47.28" aspect-ratio="1.29" } <ul><li>Pin 12 (TON) is connected to net $25N1081 <em>(from schematic)</em></li><li>Net $25N1081 connects to R816 (464K to +5VSB) and C378 (0.1uF to GND, DNI) <em>(from schematic)</em></li><li>Schematic note specifies &#x27;Rton=806K, F=285KHz&#x27; as design requirement <em>(from schematic)</em></li><li>With R816=464K, VVDDQ=1.35V, VIN=5V: tON = 3.85p × 464K × 1.35 / 4.5 = 537ns <em>(reasoning)</em></li><li>Calculated switching frequency with 464K is f = 1.35 / (5 × 537n) = 503kHz <em>(reasoning)</em></li><li>With specified 806K: tON = 3.85p × 806K × 1.35 / 4.5 = 933ns, f = 289kHz <em>(reasoning)</em></li><li>Actual resistor value of 464K does not meet the design constraint of 806K for 285kHz operation <em>(reasoning)</em></li><li>R816 should be changed to 806K to meet the specified switching frequency <em>(reasoning)</em></li></ul></details> | | 1 | VTTGND | GND | ✅ | VTTGND pin correctly connected to ground plane for VTT LDO power ground. | | 2 | VTTSNS | +VDIMM_VTT | ✅ | VTTSNS pin correctly connected to +VDIMM_VTT output for remote voltage sensing. | | 3 | GND | GND | ✅ | GND pin correctly connected to ground plane for analog ground. | | 4 | MODE | GND | ✅ | MODE pin connected to ground. Function uncertain as this pin is not documented in the RT8207P datasheet, suggesting a different package variant. | | 5 | VTTREF | $25N769 | ✅ | VTTREF pin correctly connected to buffered reference output with 0.22uF bypass capacitor C342. | | 6 | DEM | $25N1291 | ✅ | DEM pin connected to voltage divider with 10K pull-up to +5VSB and 10K pull-down (DNI). Function uncertain as this pin is not in RT8207P datasheet. | | 8 | VDDQ | +VDIMM | ✅ | VDDQ pin correctly connected to +VDIMM output for reference input and discharge control. | | 9 | FB | $25N987 | ✅ | FB pin correctly configured with resistive voltage divider (R814=8.06K, R815=10K) and compensation capacitor (C382=22pF) for 1.35V output. | | 10 | S3 | EN_VTT | ✅ | S3 pin correctly connected to EN_VTT signal through 0-ohm resistor R302 from SLP_S3_L for VTT power state control. | | 11 | S5 | EN_VDDQ | ✅ | S5 pin correctly connected to EN_VDDQ signal through 0-ohm resistor R300 from SLP_S4_L for VDDQ power state control. | | 13 | PGOOD | DRAM_PWROK | ✅ | PGOOD pin correctly connected to DRAM_PWROK open-drain output with 10K pull-up resistor R124 to +VDIMM. | | 14 | VDD | $25N1195 | ✅ | VDD pin correctly connected to +5VSB through RC filter (R813=2.2Ω, C380=1uF). Resistor value is lower than datasheet recommendation of 5.1Ω but likely intentional. | | 15 | VDDP | +5VSB | ✅ | VDDP pin correctly connected to +5VSB supply with 1uF bypass capacitor C379. | | 16 | CS | $25N1238 | ✅ | CS pin correctly configured with 3.83K resistor R817 from VDD for current limit threshold setting. | | 18 | PGND | GND | ✅ | PGND pin correctly connected to ground plane for low-side MOSFET power ground. | | 19 | LGATE | $25N901 | ✅ | LGATE pin correctly connected to Q102 pin 8 (Q2G) for low-side MOSFET gate drive. | | 20 | PHASE | DDR_PHASE | ✅ | PHASE pin correctly connected to switching node with output inductor L11 and bootstrap capacitor C309. | | 21 | UGATE | $25N897 | ✅ | UGATE pin correctly connected to Q102 pin 1 (Q1G) for high-side MOSFET gate drive. | | 22 | BOOT | $25N771 | ✅ | BOOT pin correctly connected to bootstrap network with C309 (0.1µF) and optional series resistor R298 (4.7Ω) for gate drive, matching the datasheet typical application values. | | 23 | VLDOIN | +VDIMM | ✅ | VLDOIN pin correctly connected to +VDIMM for VTT LDO power supply and tracking discharge mode. | | 24 | VTT | +VDIMM_VTT | ✅ | VTT pin correctly connected to +VDIMM_VTT output rail with appropriate output capacitors. | | 25 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) correctly connected to ground plane for thermal dissipation. | </details> <details> <summary><b>R814</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | R814 forms the upper resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L. | | 2 | 2 | $25N987 | ✅ | R814 forms the upper resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L. | </details> <details> <summary><b>R815</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N987 | ✅ | R815 forms the lower resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L. | | 2 | 2 | GND | ✅ | R815 forms the lower resistor of the feedback divider network to set the output voltage to 1.35V for DDR3L. | </details> <details> <summary><b>C382</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | C382 provides compensation for the feedback loop of the voltage regulator. | | 2 | 2 | $25N987 | ✅ | C382 provides compensation for the feedback loop of the voltage regulator. | </details> <details> <summary><b>R816</b> ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ❌ | <details><summary>On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,35.08,35.12,42.58" aspect-ratio="1.29" } <ul><li>R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) <em>(from schematic)</em></li><li>Schematic note specifies &#x27;Rton=806K, F=285KHz&#x27; as design requirement <em>(from schematic)</em></li><li>With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz <em>(reasoning)</em></li><li>With specified 806K: calculated frequency is ~289kHz, matching the design target <em>(reasoning)</em></li><li>The 464K value does not meet the design constraint of 285kHz operation <em>(reasoning)</em></li><li>R816 should be changed to 806K to achieve the specified 285kHz switching frequency <em>(reasoning)</em></li></ul></details> | | 2 | 2 | $25N1081 | ❌ | <details><summary>On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,36.84,35.12,44.34" aspect-ratio="1.29" } <ul><li>R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) <em>(from schematic)</em></li><li>Schematic note specifies &#x27;Rton=806K, F=285KHz&#x27; as design requirement <em>(from schematic)</em></li><li>With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz <em>(reasoning)</em></li><li>With specified 806K: calculated frequency is ~289kHz, matching the design target <em>(reasoning)</em></li><li>The 464K value does not meet the design constraint of 285kHz operation <em>(reasoning)</em></li><li>R816 should be changed to 806K to achieve the specified 285kHz switching frequency <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>R817</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | R817 sets the current limit threshold to approximately 11A for the VDDQ output. | | 2 | 2 | $25N1238 | ✅ | R817 sets the current limit threshold to approximately 11A for the VDDQ output. | </details> <details> <summary><b>C342</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | C342 provides bypass capacitance for VTTREF, using 0.22µF which is larger than the 33nF recommended by the datasheet but should provide adequate filtering. | | 2 | 2 | $25N769 | ✅ | C342 provides bypass capacitance for VTTREF, using 0.22µF which is larger than the 33nF recommended by the datasheet but should provide adequate filtering. | </details> <details> <summary><b>R810</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1291 | ✅ | R810 provides a pull-up to +5VSB for the DEM pin, configuring the diode emulation mode operation. | | 2 | 2 | +5VSB | ✅ | R810 provides a pull-up to +5VSB for the DEM pin, configuring the diode emulation mode operation. | </details> <details> <summary><b>R813</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | R813 provides filtering for the VDD supply, using 2.2 ohms instead of the 5.1 ohms recommended by the datasheet, which provides less filtering but also less voltage drop. | | 2 | 2 | +5VSB | ✅ | R813 provides filtering for the VDD supply, using 2.2 ohms instead of the 5.1 ohms recommended by the datasheet, which provides less filtering but also less voltage drop. | </details> <details> <summary><b>C379</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | C379 provides input bypass capacitance for the +5VSB supply. | | 2 | 2 | +5VSB | ✅ | C379 provides input bypass capacitance for the +5VSB supply. | </details> <details> <summary><b>C380</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | C380 provides bypass capacitance for the VDD supply, matching the 1µF recommendation from the datasheet. | | 2 | 2 | $25N1195 | ✅ | C380 provides bypass capacitance for the VDD supply, matching the 1µF recommendation from the datasheet. | </details> <details> <summary><b>R298</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N771 | ✅ | R298 (4.7Ω) is correctly placed in series between the controller BOOT pin and the bootstrap capacitor to limit inrush current and provide damping. | | 2 | 2 | DDR_BST | ✅ | R298 (4.7Ω) is correctly placed in series between the controller BOOT pin and the bootstrap capacitor to limit inrush current and provide damping. | </details> <details> <summary><b>C309</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | C309 (0.1uF) is correctly configured as the bootstrap capacitor between the phase node and the BOOT supply. | | 2 | 2 | DDR_BST | ✅ | C309 (0.1uF) is correctly configured as the bootstrap capacitor between the phase node and the BOOT supply. | </details> <details> <summary><b>Q102</b> - FDMS3604S ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pub/Collateral/FDMS3604S-D.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/FDMS3604S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Q1G | $25N897 | ✅ | Q1G (gate of control FET Q1) is correctly connected to the upper gate drive signal from the controller. | | 2 | VIN_A | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (drain pins of control FET Q1) are correctly connected to the input voltage rail DDR3L_VIN. | | 3 | VIN_B | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (drain pins of control FET Q1) are correctly connected to the input voltage rail DDR3L_VIN. | | 4 | VIN_C | DDR3L_VIN | ✅ | VIN_A, VIN_B, VIN_C (drain pins of control FET Q1) are correctly connected to the input voltage rail DDR3L_VIN. | | 5 | PGND_A | GND | ✅ | PGND_A, PGND_B, PGND_C (source pins of sync FET Q2) are correctly connected to ground. | | 6 | PGND_B | GND | ✅ | PGND_A, PGND_B, PGND_C (source pins of sync FET Q2) are correctly connected to ground. | | 7 | PGND_C | GND | ✅ | PGND_A, PGND_B, PGND_C (source pins of sync FET Q2) are correctly connected to ground. | | 8 | Q2G | $25N901 | ✅ | Q2G (gate of sync FET Q2) is correctly connected to the lower gate drive signal from the controller. | | 9 | PHASE | DDR_PHASE | ✅ | PHASE (switch node) is correctly connected to the output inductor, bootstrap capacitor, and controller phase feedback. | </details> <details> <summary><b>C129</b> - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VDIMM | ✅ | C129 is correctly connected as an output filter capacitor between +VDIMM and GND. However, its 2V voltage rating for a 1.35V output provides only 48% margin (0.65V), which is below the typical 2× margin guideline. | | 2 | N | GND | ✅ | C129 is correctly connected as an output filter capacitor between +VDIMM and GND. However, its 2V voltage rating for a 1.35V output provides only 48% margin (0.65V), which is below the typical 2× margin guideline. | </details> <details> <summary><b>C127</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Negative terminal of bulk input capacitor connected to ground. | | 2 | 2 | DDR3L_VIN | ✅ | Positive terminal of bulk input capacitor connected to DDR3L_VIN. | </details> <details> <summary><b>C126</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Negative terminal of bulk input capacitor connected to ground. | | 2 | 2 | DDR3L_VIN | ✅ | Positive terminal of bulk input capacitor connected to DDR3L_VIN. | </details> <details> <summary><b>C328</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Negative terminal of bulk input capacitor connected to ground. | | 2 | 2 | DDR3L_VIN | ✅ | Positive terminal of bulk input capacitor connected to DDR3L_VIN. | </details> <details> <summary><b>C327</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Negative terminal of high-frequency decoupling capacitor connected to ground. | | 2 | 2 | DDR3L_VIN | ✅ | Positive terminal of high-frequency decoupling capacitor connected to DDR3L_VIN. | </details> <details> <summary><b>L5</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input side of ferrite bead connected to +5VSB supply rail. | | 2 | 2 | DDR3L_VIN | ✅ | Output side of ferrite bead connected to DDR3L_VIN, the filtered input to the DDR voltage regulator. | </details> <details> <summary><b>C128</b> - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Negative terminal of bulk input capacitor connected to ground. | | 2 | 2 | DDR3L_VIN | ✅ | Positive terminal of bulk input capacitor connected to DDR3L_VIN. | </details> <details> <summary><b>L6</b> - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input side of ferrite bead connected to +5VSB supply rail. | | 2 | 2 | DDR3L_VIN | ✅ | Output side of ferrite bead connected to DDR3L_VIN, the filtered input to the DDR voltage regulator. | </details> <details> <summary><b>C361</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT rail, providing bulk decoupling capacitance for the DDR VTT termination voltage. | | 2 | 2 | GND | ✅ | Connected to GND, completing the decoupling path for the +VDIMM_VTT rail. | </details> <details> <summary><b>C362</b> - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT rail in parallel with C361, providing additional bulk decoupling capacitance. | | 2 | 2 | GND | ✅ | Connected to GND, completing the decoupling path for the +VDIMM_VTT rail. | </details> <details> <summary><b>C343</b> - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the return path for high-frequency decoupling. | | 2 | 2 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT rail, providing high-frequency decoupling for the DDR VTT termination voltage. | </details> <details> <summary><b>R23</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pin 1 is correctly connected to +V1P8S (VOUT of U21), providing the pull-up voltage source. | | 2 | 2 | +V1P8S_PGD | ✅ | Pin 2 is correctly connected to +V1P8S_PGD (PGOOD pin of U21), completing the pull-up resistor configuration. | </details> <details> <summary><b>R24</b> - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pin 1 is correctly connected to +V1P8S (VOUT of U21), forming the upper resistor of the feedback divider. | | 2 | 2 | +V1P8S_FB | ✅ | Pin 2 is correctly connected to +V1P8S_FB (ADJ pin of U21), forming the feedback node of the divider. | </details> <details> <summary><b>R22</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V_EN | ✅ | Pin 1 is correctly connected to 1P8V_EN, which is the enable signal source. | | 2 | 2 | +V1P8S_EN | ✅ | Pin 2 is correctly connected to +V1P8S_EN, which connects to U21's enable pin. | </details> <details> <summary><b>R25</b> - 110-0004490 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004490) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to GND, forming the lower resistor of the feedback divider. | | 2 | 2 | +V1P8S_FB | ✅ | Pin 2 is correctly connected to +V1P8S_FB (ADJ pin of U21), forming the feedback node of the divider. | </details> <details> <summary><b>U21</b> - APL5933 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/APL5933) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P8S_PGD | ✅ | PGOOD pin is correctly connected to +V1P8S_PGD net with a 4.7K pull-up resistor (R23) to the output voltage +V1P8S. | | 2 | EN | +V1P8S_EN | ✅ | EN pin is correctly connected through R22 (0 ohm jumper) to the 1P8V_EN enable signal, which is pulled up to +VCC through R125 (4.7K). | | 3 | VIN | +PS_3VSB | ✅ | VIN pin is correctly connected to the +PS_3VSB input power supply rail. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin is correctly connected to the +PS_3VSB input power supply rail, same as VIN. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as specified. | | 6 | VOUT | +V1P8S | ✅ | VOUT pin is correctly connected to the +V1P8S output rail with appropriate bypass capacitors C8 (10uF), C4 (0.1uF), and C7 (22uF). | | 7 | ADJ | +V1P8S_FB | ✅ | ADJ pin is correctly connected to the feedback divider network consisting of R24 (12.1K) and R25 (9.53K), which sets the output voltage to approximately 1.8V. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins are both correctly connected to the GND net. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins are both correctly connected to the GND net. | </details> <details> <summary><b>R134</b> - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | Connected to V1P0S_PG power good signal from U38 pin 7. This is the input side of the gate drive resistor that controls Q5. | | 2 | 2 | 1P35V_EN | ✅ | Connected to 1P35V_EN which drives the gate of Q5. This is the output side of the gate drive resistor. The 1K value provides appropriate gate current limiting and switching speed control. | </details> <details> <summary><b>R120</b> - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Connected to +V1P35S output rail from Q5 source. This is the input side of the power good sense resistor. | | 2 | 2 | 1P35V_PWG | ✅ | Connected to 1P35V_PWG signal which drives the base of Q3 for power sequencing logic. This is the output side of the power good sense resistor. | </details> <details> <summary><b>Q5</b> - RXR035N03 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +VDIMM | ✅ | Drain pin correctly connected to +VDIMM input power rail. This is the input side of the high-side load switch. | | G | GATE | 1P35V_EN | ✅ | Gate pin correctly connected to 1P35V_EN control signal through R134. The gate drive voltage must be sufficient to provide VGS > 2V as noted on the schematic. | | S | SOURCE | +V1P35S | ✅ | Source pin correctly connected to +V1P35S output rail. This is the output side of the high-side load switch providing 1.35V to downstream circuits. | </details> <details> <summary><b>U38</b> - APL5912KAC-TRGS-X ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/APL5912KAC-TRGS-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | VIN-2 | +VDIMM | ❌ | <details><summary>VIN-1 and VIN-2 pins connected to +VDIMM, but circuit has fundamental design flaws preventing operation: (1) Circular startup dependency - U38 requires +VDIMM to operate, but +VDIMM is only available after U38 asserts power good to enable Q5, (2) Q5 current rating insufficient (3.5A max vs 4.9A required), (3) Q5 voltage drop excessive, leaving insufficient input voltage for regulation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="20.80,18.61,28.30,26.11" aspect-ratio="1.29" } <ul><li>Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net <em>(from schematic)</em></li><li>+VDIMM is sourced from +V1P35S (1.35V) through Q5, an N-channel MOSFET (RXR035N03) <em>(from schematic)</em></li><li>Q5 gate (1P35V_EN) is controlled by U38&#x27;s power good output (V1P0S_PG) through R134 (1K) <em>(from schematic)</em></li><li>This creates a circular dependency: U38 needs +VDIMM to start up and generate V1P0S_PG, but +VDIMM is only available when Q5 is enabled by V1P0S_PG <em>(reasoning)</em></li><li>At startup with Q5 off, the body diode would conduct from +V1P35S to +VDIMM, providing approximately 1.35V - 0.7V = 0.65V <em>(reasoning)</em></li><li>With only 0.65V input, U38 cannot regulate a 1.0V output, preventing circuit startup <em>(reasoning)</em></li><li>Schematic note near Q5 specifies &#x27;Id MAX = 3.5 Amps&#x27; for Q5&#x27;s maximum drain current <em>(from schematic)</em></li><li>Text notes indicate load currents of &#x27;V1.05 : 1.3A&#x27; and &#x27;V1.0 : 3.6A&#x27;, totaling 4.9A <em>(from schematic)</em></li><li>The required 4.9A exceeds Q5&#x27;s 3.5A rating by 40%, making Q5 severely undersized <em>(reasoning)</em></li><li>Schematic notes specify Q5 Rds(on) as &#x27;VGS=5V Rds(on)=90m MAX&#x27; <em>(from schematic)</em></li><li>With gate driven to approximately 5V and source at 1.35V, Vgs = 3.65V, resulting in Rds(on) higher than the specified 90mΩ at Vgs=5V <em>(reasoning)</em></li><li>At 4.9A with Rds(on) ≈ 100mΩ, voltage drop across Q5 is approximately 0.49V <em>(reasoning)</em></li><li>+VDIMM would be only 1.35V - 0.49V = 0.86V, which is insufficient for U38 to regulate a 1.0V output (negative dropout voltage) <em>(reasoning)</em></li><li>The circuit has three critical design errors: (1) circular startup dependency preventing initial operation, (2) Q5 current rating insufficient for the load, (3) excessive voltage drop across Q5 preventing proper regulation even if startup were possible <em>(reasoning)</em></li><li>Input decoupling capacitor C118 (10uF) is present on +VDIMM <em>(from schematic)</em></li></ul></details> | | 9 | VIN-1 | +VDIMM | ❌ | <details><summary>VIN-1 and VIN-2 pins connected to +VDIMM, but circuit has fundamental design flaws preventing operation: (1) Circular startup dependency - U38 requires +VDIMM to operate, but +VDIMM is only available after U38 asserts power good to enable Q5, (2) Q5 current rating insufficient (3.5A max vs 4.9A required), (3) Q5 voltage drop excessive, leaving insufficient input voltage for regulation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="18.53,23.32,26.03,30.82" aspect-ratio="1.29" } <ul><li>Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net <em>(from schematic)</em></li><li>+VDIMM is sourced from +V1P35S (1.35V) through Q5, an N-channel MOSFET (RXR035N03) <em>(from schematic)</em></li><li>Q5 gate (1P35V_EN) is controlled by U38&#x27;s power good output (V1P0S_PG) through R134 (1K) <em>(from schematic)</em></li><li>This creates a circular dependency: U38 needs +VDIMM to start up and generate V1P0S_PG, but +VDIMM is only available when Q5 is enabled by V1P0S_PG <em>(reasoning)</em></li><li>At startup with Q5 off, the body diode would conduct from +V1P35S to +VDIMM, providing approximately 1.35V - 0.7V = 0.65V <em>(reasoning)</em></li><li>With only 0.65V input, U38 cannot regulate a 1.0V output, preventing circuit startup <em>(reasoning)</em></li><li>Schematic note near Q5 specifies &#x27;Id MAX = 3.5 Amps&#x27; for Q5&#x27;s maximum drain current <em>(from schematic)</em></li><li>Text notes indicate load currents of &#x27;V1.05 : 1.3A&#x27; and &#x27;V1.0 : 3.6A&#x27;, totaling 4.9A <em>(from schematic)</em></li><li>The required 4.9A exceeds Q5&#x27;s 3.5A rating by 40%, making Q5 severely undersized <em>(reasoning)</em></li><li>Schematic notes specify Q5 Rds(on) as &#x27;VGS=5V Rds(on)=90m MAX&#x27; <em>(from schematic)</em></li><li>With gate driven to approximately 5V and source at 1.35V, Vgs = 3.65V, resulting in Rds(on) higher than the specified 90mΩ at Vgs=5V <em>(reasoning)</em></li><li>At 4.9A with Rds(on) ≈ 100mΩ, voltage drop across Q5 is approximately 0.49V <em>(reasoning)</em></li><li>+VDIMM would be only 1.35V - 0.49V = 0.86V, which is insufficient for U38 to regulate a 1.0V output (negative dropout voltage) <em>(reasoning)</em></li><li>The circuit has three critical design errors: (1) circular startup dependency preventing initial operation, (2) Q5 current rating insufficient for the load, (3) excessive voltage drop across Q5 preventing proper regulation even if startup were possible <em>(reasoning)</em></li><li>Input decoupling capacitor C118 (10uF) is present on +VDIMM <em>(from schematic)</em></li></ul></details> | | 1 | GND | GND | ✅ | GND pin correctly connected to ground reference. | | 2 | FB | FB_V1P0S | ✅ | FB pin correctly connected to feedback network for 1.025V output voltage. | | 3 | VOUT-2 | +V1P0S | ✅ | VOUT-1 and VOUT-2 pins correctly connected together to +V1P0S output rail. | | 4 | VOUT-1 | +V1P0S | ✅ | VOUT-1 and VOUT-2 pins correctly connected together to +V1P0S output rail. | | 6 | VCNTL | VCNTL_V1P0S | ✅ | VCNTL pin connected to soft-start network with 10 ohm resistor to +VCC and 1uF capacitor to ground. Configuration appears reasonable but should be verified against datasheet. | | 7 | POK | V1P0S_PG | ✅ | POK pin correctly connected to power good output with pull-up resistor and used for downstream sequencing. | | 8 | EN | 1P0V_EN | ✅ | EN pin correctly connected to enable signal from graphics core power good through 0-ohm jumper. | </details> <details> <summary><b>R150</b> - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R150 is correctly configured as the upper feedback resistor (R1) in the voltage divider for U20's adjustable output voltage. | | 2 | 2 | +V1P8A | ✅ | R150 is correctly configured as the upper feedback resistor (R1) in the voltage divider for U20's adjustable output voltage. | </details> <details> <summary><b>R153</b> - 110-0002726 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002726) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | R153 is correctly configured as the lower feedback resistor (R2) in the voltage divider for U20's adjustable output voltage. | | 2 | 2 | GND | ✅ | R153 is correctly configured as the lower feedback resistor (R2) in the voltage divider for U20's adjustable output voltage. | </details> <details> <summary><b>R151</b> - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | R151 is correctly configured as a 0-ohm jumper to provide power sequencing from U24's power good signal to U20's enable input. | | 2 | 2 | +V1P8A_EN | ✅ | R151 is correctly configured as a 0-ohm jumper to provide power sequencing from U24's power good signal to U20's enable input. | </details> <details> <summary><b>U20</b> - NCP606 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncp605-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NCP606) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN1 | +PS_3VSB | ✅ | VIN1 is correctly connected to +PS_3VSB input power supply. | | 2 | GND | GND | ✅ | GND is correctly connected to ground. | | 3 | EN | +V1P8A_EN | ✅ | EN is correctly connected to +V1P8A_EN for power sequencing control. | | 4 | VOUT | +V1P8A | ✅ | VOUT is correctly connected to +V1P8A output rail with adequate output capacitance. | | 5 | SENSE/ADJ | +V1P8A_FB | ✅ | SENSE/ADJ is correctly connected to feedback divider network for 1.8V output voltage. | | 6 | VIN2 | +PS_3VSB | ✅ | VIN2 is correctly connected to +PS_3VSB input power supply. | | 7 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) is correctly connected to ground. | </details> <details> <summary><b>R33</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | Power-good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin for open-drain output. | | 2 | 2 | +V1P0A_PWRGD | ✅ | Power-good pull-up resistor correctly connected between +PS_3VSB and PGOOD pin for open-drain output. | </details> <details> <summary><b>R32</b> - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Enable pull-up resistor correctly connected between +5VSB and EN pin, ensuring enable threshold is met. | | 2 | 2 | +V1P0A_ENABLE | ✅ | Enable pull-up resistor correctly connected between +5VSB and EN pin, ensuring enable threshold is met. | </details> <details> <summary><b>U24</b> - APL5933 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/APL5933) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P0A_PWRGD | ✅ | PGOOD output is correctly connected to power sequencing logic with appropriate pull-up resistor R33 to +PS_3VSB. | | 2 | EN | +V1P0A_ENABLE | ✅ | EN input is correctly pulled up to +5VSB through R32 with decoupling capacitor C20, meeting the >1.1V enable threshold requirement. | | 3 | VIN | +PS_3VSB | ✅ | VIN input is correctly connected to +PS_3VSB supply with adequate input bypass capacitors. | | 4 | VDD | +PS_3VSB | ✅ | VDD control supply is correctly connected to +PS_3VSB, same as VIN. | | 5 | NC | | ✅ | NC pin is correctly left unconnected. | | 6 | VOUT | +V1P0A | ✅ | VOUT is correctly connected to +V1P0A rail with appropriate output capacitors C21 (22uF) and C22 (0.1uF). | | 7 | ADJ | +V1P0A_FB | ✅ | ADJ feedback pin is correctly connected to resistor divider formed by R34 (6.04K) and R35 (23.7K), setting output voltage to approximately 1.0V. | | 8 | GND1 | GND | ✅ | Both ground pins are correctly connected to GND net. | | 9 | GND2 | GND | ✅ | Both ground pins are correctly connected to GND net. | </details> <details> <summary><b>R35</b> - 110-0004494 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004494) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Lower feedback resistor correctly connected between ADJ pin and GND, setting output voltage to 1.0V with R34. | | 2 | 2 | GND | ✅ | Lower feedback resistor correctly connected between ADJ pin and GND, setting output voltage to 1.0V with R34. | </details> <details> <summary><b>R34</b> - 110-0003781 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0003781) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Upper feedback resistor correctly connected between ADJ pin and VOUT, setting output voltage to 1.0V with R35. | | 2 | 2 | +V1P0A | ✅ | Upper feedback resistor correctly connected between ADJ pin and VOUT, setting output voltage to 1.0V with R35. | </details> <details> <summary><b>D11</b> - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | Anode 1 connected to +V1P0A_PWRGD power good signal. | | 2 | 2 | SLP_S3_L | ✅ | Anode 2 connected to SLP_S3_L sleep state signal. | | 3 | 3 | PSGOOD | ✅ | Common cathode connected to PSGOOD signal, forming a diode OR gate output. | </details> <details> <summary><b>Q3</b> - MBT3904 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/MBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter 1 (E1) correctly connected to GND for NPN transistor operation. | | 2 | B1 | 1P35V_PWG | ✅ | Base 1 (B1) connected to 1P35V_PWG signal, pulled up to +V1P35S through R120 (10K). | | 3 | C2 | 1P8V_EN | ✅ | Collector 2 (C2) connected to 1P8V_EN output, pulled up to +VCC through R125 (4.7K). | | 4 | E2 | GND | ✅ | Emitter 2 (E2) correctly connected to GND for NPN transistor operation. | | 5 | B2 | 1P5V_EN_B | ✅ | Base 2 (B2) connected to 1P5V_EN_B signal, which is also connected to pin 6 (C1), forming a feedback path. | | 6 | C1 | 1P5V_EN_B | ✅ | Collector 1 (C1) connected to 1P5V_EN_B signal, which also connects to pin 5 (B2), forming a two-stage switching circuit. | </details> <details> <summary><b>Q1</b> - MBT3904 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/MBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter 1 (E1) correctly connected to GND for NPN transistor operation. | | 2 | B1 | PSGOOD | ✅ | Base 1 (B1) connected to PSGOOD signal, which is driven by diode OR gate D11 and pulled up through R206 (200K) to +V1P8S. | | 3 | C2 | SYS_PWRGD | ✅ | Collector 2 (C2) connected to SYS_PWRGD output, pulled up to +VCC3 through R61 (20K). | | 4 | E2 | GND | ✅ | Emitter 2 (E2) correctly connected to GND for NPN transistor operation. | | 5 | B2 | PSPUP | ✅ | Base 2 (B2) connected to PSPUP signal, which is also connected to pin 6 (C1), forming a feedback path. | | 6 | C1 | PSPUP | ✅ | Collector 1 (C1) connected to PSPUP signal, which also connects to pin 5 (B2), forming a two-stage switching circuit. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **R151, R192, R216, R22, R243, R261, R293, R300, R302, R306, R353, R354, R48, R51, R72, R73, R74** (110-0001853): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001853) - **R50** (110-0001859): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001859) - **R120, R124, R190, R191, R2, R211, R220, R221, R268, R319, R400, R706, R71, R75, R84, R97** (110-0001875): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001875) - **R134, R186, R187, R208, R234, R259** (110-0001923): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001923) - **R206** (110-0001951): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001951) - **R60, R61** (110-0001957): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001957) - **R179** (110-0001960): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001960) - **R11, R12, R269, R270** (110-0001967): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001967) - **R140, R327** (110-0001971): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001971) - **R177, R257, R44, R45, R47, R49, R52** (110-0001984): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0001984) - **R819** (110-0002000): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002000) - **R136** (110-0002029): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002029) - **R125, R126, R144, R149, R23, R310, R32, R325, R326, R33** (110-0002058): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058) - **R222, R265, R275** (110-0002124): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002124) - **R150, R24** (110-0002560): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002560) - **R213** (110-0002631): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002631) - **R153** (110-0002726): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002726) - **R240, R241, R242, R258** (110-0003059): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0003059) - **R34** (110-0003781): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0003781) - **R185, R77** (110-0004472): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004472) - **R255** (110-0004474): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004474) - **R217, R218, R239** (110-0004476): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004476) - **R212** (110-0004478): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004478) - **R25** (110-0004490): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004490) - **R35** (110-0004494): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004494) - **R135** (110-0004498): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004498) - **R40** (110-0004695): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0004695) - **R320** (1120-0022): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/1120-0022) - **R148, R746** (1120-0318): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/1120-0318) - **R840, R841, R842** (1121-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/1121-0001) - **C10, C11, C12, C13, C177, C178, C179, C180** (123-0001038): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001038) - **C154, C205, C206, C207, C208** (123-0001056): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001056) - **C164, C201, C224, C225** (123-0001176): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0001176) - **C149, C150** (123-0003258): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0003258) - **C148** (123-0004408): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0004408) - **C76, C77, C87** (123-0005035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/123-0005035) - **L11** (125-0004454): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/125-0004454) - **L3** (125-0004501): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/125-0004501) - **FB3** (126-0001423): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/126-0001423) - **FB4, FB5, L5, L6** (126-0004457): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/126-0004457) - **D3** (130-0004403): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/130-0004403) - **Y1** (145-0004789): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/145-0004789) - **X1, Y2** (145-0004792): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/145-0004792) - **P2** (158-0001269): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/158-0001269) - **P1** (158-0004513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/158-0004513) - **J10** (158-0004534): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/158-0004534) - **C28** (2232-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/2232-0012) - **J5, J6, J7** (258-0002513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0002513) - **USB1** (258-0004503): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0004503) - **J1** (258-0004612): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0004612) - **J4** (258-0004869): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0004869) - **JP1** (258-0005019): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/258-0005019) - **FB12** (3044-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3044-0010) - **FB13** (3044-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3044-0012) - **L8** (3120-0183): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3120-0183) - **L18, L4** (3120-0266): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3120-0266) - **CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17** (3142-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3142-0014) - **J11** (3362-0042): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3362-0042) - **J8** (3430-0212): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3430-0212) - **BH1** (353-0003073): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/353-0003073) - **FL1** (3750-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3750-0010) - **SW1** (3770-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3770-0026) - **TH1, TH2, TH3, TH4** (3880-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/3880-0004) - **U42** (4300-0071): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4300-0071) - **U5, U6** (4327-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4327-0009) - **U19** (4327-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4327-0010) - **D10, D5** (4536-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4536-0009) - **D1, D2** (4560-0045): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4560-0045) - **D13** (4620-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4620-0026) - **TP1, TP17, TP18, TP2** (999-0000003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/999-0000003) - **SP1, SP2, SP3, SP4** (999-0000005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/999-0000005) - **U3** (AD42): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/AD42) - **U38** (APL5912KAC-TRGS-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/APL5912KAC-TRGS-X) - **U21, U24** (APL5933): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/APL5933) - **D11, D4, D6** (BAT54A-S): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAT54A-S) - **D8** (BAT754C): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAT754C) - **Q2, Q9** (BAV99-7-F-S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BAV99-7-F-S-X) - **L1, L2** (BKP2125HS221-T): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/BKP2125HS221-T) - **U25, U26** (NCP81109GMNTXG): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NCP81109GMNTXG) - **U35** (NCT3012S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NCT3012S-X) - **U18** (NTB0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTB0104GU12) - **U4, U7** (NTS0102GT): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0102GT) - **U10, U14, U15, U16, U17** (NTS0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0104GU12) - **U29** (TPD4USB30): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/TPD4USB30) </details> _{^{Note: DRCY uses AI. Please verify the outputs.}}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component CPU1, pins AK12, AK13: DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net, while pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ negative per datasheet) connects to DDI_RCOMP_P net. These connections should be reversed.

• Pin AK12 is labeled DDI0_RCOMP_P in the component and datasheet, indicating the positive side of the DDI compensation resistor pair (from datasheet 140-0004628, page 213)
• Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ in the component and datasheet, where the overline notation indicates this is the negative/complement signal (DDI0_RCOMP_N) (from datasheet 140-0004628, page 213)
• In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic)
• In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic)
• Resistor R217 (402 ohms) is connected between nets DDI_RCOMP_N and DDI_RCOMP_P, serving as the DDI compensation resistor (from schematic)
• The connections are reversed: the positive pin (AK12) connects to the negative net, and the negative pin (AK13) connects to the positive net (reasoning)
• To correct this error, the net connections should be swapped so that AK12 connects to DDI_RCOMP_P and AK13 connects to DDI_RCOMP_N (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AK12, AK13`: DDI0_RCOMP pins are swapped. Pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net, while pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ negative per datasheet) connects to DDI_RCOMP_P net. These connections should be reversed.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,39.05" aspect-ratio="1.29" } - Pin AK12 is labeled DDI0_RCOMP_P in the component and datasheet, indicating the positive side of the DDI compensation resistor pair *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213>), page 213)* - Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ in the component and datasheet, where the overline notation indicates this is the negative/complement signal (DDI0_RCOMP_N) *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213>), page 213)* - In the schematic, pin AK12 connects to net DDI_RCOMP_N *(from schematic)* - In the schematic, pin AK13 connects to net DDI_RCOMP_P *(from schematic)* - Resistor R217 (402 ohms) is connected between nets DDI_RCOMP_N and DDI_RCOMP_P, serving as the DDI compensation resistor *(from schematic)* - The connections are reversed: the positive pin (AK12) connects to the negative net, and the negative pin (AK13) connects to the positive net *(reasoning)* - To correct this error, the net connections should be swapped so that AK12 connects to DDI_RCOMP_P and AK13 connects to DDI_RCOMP_N *(reasoning)* _{Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component D5, pin 3: Common cathode (C) connected to +RTCVCC, but +RTCVCC is not connected to the CPU's RTC power input (BVCCRTC_EXTPAD). This is a critical error - the RTC battery backup circuit will not function without this connection.

• Pin 3 connects to net +RTCVCC (from schematic)
• +RTCVCC connects to C286 pin 2 (1uF decoupling capacitor) and R279 pin 1 (20K resistor to RTCRST_L) (from schematic)
• The CPU has an RTC power pin B8 (ILB_RTC_EXTPAD) connected to net BVCCRTC_EXTPAD (from schematic)
• BVCCRTC_EXTPAD only connects to CPU1 pin B8 and C41 pin 1 (0.1uF decoupling capacitor) (from schematic)
• There is no component connecting +RTCVCC to BVCCRTC_EXTPAD on this schematic page (from schematic)
• The pin name 'ILB_RTC_EXTPAD' with 'EXTPAD' suffix indicates this pin expects an external power source (reasoning)
• The existence of a complete battery backup circuit generating +RTCVCC strongly suggests it is intended to power the RTC (reasoning)
• Without power to the RTC power pin, the RTC cannot function and will not maintain time when main power is removed (reasoning)
• A connection (0-ohm resistor or direct trace) should be added between +RTCVCC and BVCCRTC_EXTPAD to properly power the RTC (reasoning)

_{Upload a datasheet: 📤 D5}

[🚨 Error] **Component `D5`, pin `3`: Common cathode (C) connected to +RTCVCC, but +RTCVCC is not connected to the CPU's RTC power input (BVCCRTC_EXTPAD). This is a critical error - the RTC battery backup circuit will not function without this connection.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="c66f35d31fb1590e57a5" diff-visibility="full" variant="default" view-coords="18.53,68.60,26.03,76.10" aspect-ratio="1.29" } - Pin 3 connects to net +RTCVCC *(from schematic)* - +RTCVCC connects to C286 pin 2 (1uF decoupling capacitor) and R279 pin 1 (20K resistor to RTCRST_L) *(from schematic)* - The CPU has an RTC power pin B8 (ILB_RTC_EXTPAD) connected to net BVCCRTC_EXTPAD *(from schematic)* - BVCCRTC_EXTPAD only connects to CPU1 pin B8 and C41 pin 1 (0.1uF decoupling capacitor) *(from schematic)* - There is no component connecting +RTCVCC to BVCCRTC_EXTPAD on this schematic page *(from schematic)* - The pin name &#x27;ILB_RTC_EXTPAD&#x27; with &#x27;EXTPAD&#x27; suffix indicates this pin expects an external power source *(reasoning)* - The existence of a complete battery backup circuit generating +RTCVCC strongly suggests it is intended to power the RTC *(reasoning)* - Without power to the RTC power pin, the RTC cannot function and will not maintain time when main power is removed *(reasoning)* - A connection (0-ohm resistor or direct trace) should be added between +RTCVCC and BVCCRTC_EXTPAD to properly power the RTC *(reasoning)* _{Upload a datasheet: [📤 D5](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4536-0009)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component CPU1, pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33: CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.

• Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet (from datasheet 140-0004628)
• These pins are connected to net +V1P0S in the schematic (from schematic)
• The +V1P0S net provides 1.0V according to the power rail naming convention (from schematic)
• According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A (from datasheet 140-0004628, page 120)
• The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V (reasoning)
• This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail (reasoning)
• The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available (from schematic)
• These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification (reasoning)
• Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33`: CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) but should be connected to +V1P05S (1.05V). This is a critical voltage error that exceeds the specified tolerance.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,28.61,61.48,49.63" aspect-ratio="1.29" } - Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are labeled CORE_V1P05_S3 in the datasheet *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - These pins are connected to net +V1P0S in the schematic *(from schematic)* - The +V1P0S net provides 1.0V according to the power rail naming convention *(from schematic)* - According to the datasheet, CORE_V1P05_S3 rail requires 1.05V ±2% DC, ±3% AC with maximum current of 1.3A *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/5cce29a752c903f6a6787fca1e97751371b816ac/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120>), page 120)* - The voltage difference between 1.0V and 1.05V is 50mV, which represents a 4.76% deviation from the nominal 1.05V *(reasoning)* - This 4.76% deviation exceeds the specified ±2% DC tolerance for the CORE_V1P05_S3 rail *(reasoning)* - The schematic shows a separate +V1P05S net exists on the page, indicating the correct voltage rail is available *(from schematic)* - These CORE_V1P05_S3 pins should be connected to the +V1P05S net instead of +V1P0S to meet the datasheet voltage specification *(reasoning)* - Operating the processor core at 1.0V instead of the required 1.05V may cause instability, malfunction, or failure to boot *(reasoning)* _{Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/140-0004628)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component U4, pin 7: VCCB is connected to +USBVCC (5V), which exceeds the NTS0102GT maximum rating of 3.6V specified in the component attributes. This is a critical design error that violates the device's operating voltage range and could damage the device.

• Pin 7 (VCCB) is the B-side supply voltage pin for the level translator (reasoning)
• Pin 7 is connected to +USBVCC (from schematic)
• +USBVCC is derived from +5VSB through ferrite bead FB13 (from schematic)
• +5VSB is a standard 5V standby supply based on PC power supply naming conventions (reasoning)
• A ferrite bead provides high-frequency impedance but is essentially a DC short, so +USBVCC is approximately 5V at DC (reasoning)
• U32 (AP2172MPG) USB power switch has input voltage range of 2.7-5.5V and its IN pin connects to +USBVCC, confirming +USBVCC is a 5V rail (from schematic)
• The component voltage rating is specified as 1.2-3.6V in the VOLTAGE attribute (from schematic)
• VCCB is the B-side reference supply voltage and must be within the 1.2-3.6V range per the component specification (reasoning)
• Connecting VCCB to 5V exceeds the maximum operating voltage of 3.6V by 1.4V (reasoning)
• The NTS0102GT part number with 'GT' suffix indicates the standard variant with 3.6V maximum on both VCCA and VCCB, not the 'GF' variant which supports up to 5.5V on VCCB (reasoning)
• Operating VCCB above its maximum rating can cause permanent damage to the device or unreliable operation (reasoning)
• VCCB should be connected to a 3.3V supply instead of +USBVCC (5V) (reasoning)
• Alternatively, a 5V-tolerant level translator such as NTS0102GF or SN74LVC2T45 (which supports VCCB up to 5.5V) should be used instead of NTS0102GT (reasoning)
• Decoupling capacitors C92, C93, C94 (0.1uF) are present on the +USBVCC net for power supply filtering (from schematic)

_{Upload a datasheet: 📤 U4}

[🚨 Error] **Component `U4`, pin `7`: VCCB is connected to +USBVCC (5V), which exceeds the NTS0102GT maximum rating of 3.6V specified in the component attributes. This is a critical design error that violates the device's operating voltage range and could damage the device.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="41.02,68.01,48.52,75.51" aspect-ratio="1.29" } - Pin 7 (VCCB) is the B-side supply voltage pin for the level translator *(reasoning)* - Pin 7 is connected to +USBVCC *(from schematic)* - +USBVCC is derived from +5VSB through ferrite bead FB13 *(from schematic)* - +5VSB is a standard 5V standby supply based on PC power supply naming conventions *(reasoning)* - A ferrite bead provides high-frequency impedance but is essentially a DC short, so +USBVCC is approximately 5V at DC *(reasoning)* - U32 (AP2172MPG) USB power switch has input voltage range of 2.7-5.5V and its IN pin connects to +USBVCC, confirming +USBVCC is a 5V rail *(from schematic)* - The component voltage rating is specified as 1.2-3.6V in the VOLTAGE attribute *(from schematic)* - VCCB is the B-side reference supply voltage and must be within the 1.2-3.6V range per the component specification *(reasoning)* - Connecting VCCB to 5V exceeds the maximum operating voltage of 3.6V by 1.4V *(reasoning)* - The NTS0102GT part number with &#x27;GT&#x27; suffix indicates the standard variant with 3.6V maximum on both VCCA and VCCB, not the &#x27;GF&#x27; variant which supports up to 5.5V on VCCB *(reasoning)* - Operating VCCB above its maximum rating can cause permanent damage to the device or unreliable operation *(reasoning)* - VCCB should be connected to a 3.3V supply instead of +USBVCC (5V) *(reasoning)* - Alternatively, a 5V-tolerant level translator such as NTS0102GF or SN74LVC2T45 (which supports VCCB up to 5.5V) should be used instead of NTS0102GT *(reasoning)* - Decoupling capacitors C92, C93, C94 (0.1uF) are present on the +USBVCC net for power supply filtering *(from schematic)* _{Upload a datasheet: [📤 U4](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0102GT)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component U16, pins 2, 3, 9, 10: I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave.

• Pin 2 (A1) is connected to I2S_DATIN_R net (from schematic)
• Pin 3 (A2) is connected to I2S_DATOUT_R net (from schematic)
• Pin 9 (B2) is connected to I2SDO_GPIO net (from schematic)
• Pin 10 (B1) is connected to I2SDI_GPIO net (from schematic)
• I2SDO_GPIO connects to pin 18 of JP1 header connector (from schematic)
• I2SDI_GPIO connects to pin 20 of JP1 header connector (from schematic)
• The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 (reasoning)
• I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device (reasoning)
• I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device (reasoning)
• I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) (reasoning)
• I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) (reasoning)
• In I2S protocol, the master's data output must connect to the slave's data input (reasoning)
• In I2S protocol, the master's data input must connect to the slave's data output (reasoning)
• Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection (reasoning)
• Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection (reasoning)
• The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) (reasoning)
• The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) (reasoning)
• To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) (reasoning)

_{Upload a datasheet: 📤 U16}

[🚨 Error] **Component `U16`, pins `2, 3, 9, 10`: I2S data signals are swapped. Pin 2 (A1) connects I2S_DATIN_R to I2SDI_GPIO (B1), and pin 3 (A2) connects I2S_DATOUT_R to I2SDO_GPIO (B2). This creates an incorrect output-to-output and input-to-input connection between the I2S master and slave.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="65.56,63.30,77.61,71.39" aspect-ratio="1.29" } - Pin 2 (A1) is connected to I2S_DATIN_R net *(from schematic)* - Pin 3 (A2) is connected to I2S_DATOUT_R net *(from schematic)* - Pin 9 (B2) is connected to I2SDO_GPIO net *(from schematic)* - Pin 10 (B1) is connected to I2SDI_GPIO net *(from schematic)* - I2SDO_GPIO connects to pin 18 of JP1 header connector *(from schematic)* - I2SDI_GPIO connects to pin 20 of JP1 header connector *(from schematic)* - The NTS0104GU12 level translator pairs A1 with B1 and A2 with B2 *(reasoning)* - I2S_DATIN_R is the data input to the SOC/LPE master, receiving data from the external slave device *(reasoning)* - I2S_DATOUT_R is the data output from the SOC/LPE master, transmitting data to the external slave device *(reasoning)* - I2SDI_GPIO is the data input to the external I2S slave device (Serial Data In) *(reasoning)* - I2SDO_GPIO is the data output from the external I2S slave device (Serial Data Out) *(reasoning)* - In I2S protocol, the master&#x27;s data output must connect to the slave&#x27;s data input *(reasoning)* - In I2S protocol, the master&#x27;s data input must connect to the slave&#x27;s data output *(reasoning)* - Current connection has I2S_DATOUT_R (master output) connected to I2SDO_GPIO (slave output), creating an output-to-output connection *(reasoning)* - Current connection has I2S_DATIN_R (master input) connected to I2SDI_GPIO (slave input), creating an input-to-input connection *(reasoning)* - The correct connection should be I2S_DATOUT_R to I2SDI_GPIO (master TX to slave RX) *(reasoning)* - The correct connection should be I2S_DATIN_R to I2SDO_GPIO (master RX to slave TX) *(reasoning)* - To fix this issue, swap the signals on pins 2 and 3: connect I2S_DATOUT_R to pin 2 (A1) and I2S_DATIN_R to pin 3 (A2) *(reasoning)* _{Upload a datasheet: [📤 U16](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NTS0104GU12)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component U40, pins 5, 6: SDA2 and SCL2 pins are missing required pullup resistors to the high-voltage supply (+3VSB). The datasheet explicitly requires pullup resistors on both sides of the I2C translator for proper operation.

• Pin 5 (SDA2) connects to GPIO_I2C_SDA and pin 6 (SCL2) connects to GPIO_I2C_SCL (from schematic)
• Pin 5 is SDA2 (Serial data, high-voltage side) and pin 6 is SCL2 (Serial clock, high-voltage side) (from datasheet PCA9306DCUT, page 4)
• The datasheet states: 'Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)' (from datasheet PCA9306DCUT, page 10)
• The datasheet states: 'the I2C bus device output can be open-drain with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU' (from datasheet PCA9306DCUT, page 10)
• Both typical application circuits in the datasheet show pullup resistors (RPU) on SCL2 and SDA2 to VDPU (from datasheet PCA9306DCUT, page 17)
• No pullup resistors are present on the GPIO_I2C_SDA or GPIO_I2C_SCL nets in the schematic (from schematic)
• The low-voltage side has pullup resistors: R267 (10K) on I2C5_SCL to +V1P8S and R266 (10K) on I2C5_SDA to +V1P8S (from schematic)
• The asymmetry between low-voltage side (with pullups) and high-voltage side (without pullups) indicates a design oversight rather than intentional reliance on external pullups (reasoning)
• GPIO_I2C_SCL and GPIO_I2C_SDA connect to JP1 connector pins 13 and 15, which is a general-purpose expansion header (from schematic)
• Without pullup resistors, the I2C signals cannot be pulled high and the bus will not function correctly (reasoning)
• Pullup resistors (typically 2.2K to 10K depending on bus capacitance and speed per I2C specification) should be added from GPIO_I2C_SDA to +3VSB and from GPIO_I2C_SCL to +3VSB (reasoning)
• If external pullups are intentionally expected on the other side of connector JP1, this should be clearly documented with a note on the schematic, but no such note is present (reasoning)

_{Replace a datasheet: 📤 U40}

[🚨 Error] **Component `U40`, pins `5, 6`: SDA2 and SCL2 pins are missing required pullup resistors to the high-voltage supply (+3VSB). The datasheet explicitly requires pullup resistors on both sides of the I2C translator for proper operation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.92" aspect-ratio="1.29" } - Pin 5 (SDA2) connects to GPIO_I2C_SDA and pin 6 (SCL2) connects to GPIO_I2C_SCL *(from schematic)* - Pin 5 is SDA2 (Serial data, high-voltage side) and pin 6 is SCL2 (Serial clock, high-voltage side) *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4>), page 4)* - The datasheet states: &#x27;Open-drain I/O ports require external pullup resistors to respective supply voltages (VREF1 for side 1, VDPU for side 2)&#x27; *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10>), page 10)* - The datasheet states: &#x27;the I2C bus device output can be open-drain with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU&#x27; *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10>), page 10)* - Both typical application circuits in the datasheet show pullup resistors (RPU) on SCL2 and SDA2 to VDPU *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17>), page 17)* - No pullup resistors are present on the GPIO_I2C_SDA or GPIO_I2C_SCL nets in the schematic *(from schematic)* - The low-voltage side has pullup resistors: R267 (10K) on I2C5_SCL to +V1P8S and R266 (10K) on I2C5_SDA to +V1P8S *(from schematic)* - The asymmetry between low-voltage side (with pullups) and high-voltage side (without pullups) indicates a design oversight rather than intentional reliance on external pullups *(reasoning)* - GPIO_I2C_SCL and GPIO_I2C_SDA connect to JP1 connector pins 13 and 15, which is a general-purpose expansion header *(from schematic)* - Without pullup resistors, the I2C signals cannot be pulled high and the bus will not function correctly *(reasoning)* - Pullup resistors (typically 2.2K to 10K depending on bus capacitance and speed per I2C specification) should be added from GPIO_I2C_SDA to +3VSB and from GPIO_I2C_SCL to +3VSB *(reasoning)* - If external pullups are intentionally expected on the other side of connector JP1, this should be clearly documented with a note on the schematic, but no such note is present *(reasoning)* _{Replace a datasheet: [📤 U40](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/PCA9306DCUT)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[⚠️ Warning] Component R149, pins 1, 2: Pullup resistor with correct connections between +PS_5VSB and FP_PWRBTN, but component value (4.7K) does not match the datasheet recommendation of 10K noted in schematic annotations.

• Pin 1 is connected to net FP_PWRBTN (from schematic)
• Pin 2 is connected to net +PS_5VSB (from schematic)
• R149 serves as a pullup resistor, pulling FP_PWRBTN high to +PS_5VSB when the power button SW1 is not pressed (reasoning)
• The component value is 4.7K ohm per part number 110-0002058 (from schematic)
• Schematic text annotations at coordinates (180.34, 355.6) and (180.34, 360.68) state 'USE 10K PU' and 'DATASHEET SAYS', located near R149 at (172.72, 347.98) (from schematic)
• These annotations indicate the datasheet for the receiving circuit recommends a 10K pullup resistor (reasoning)
• With 4.7K, the current draw when the button is pressed is approximately 1.06mA (5V / 4.7K), while 10K would draw approximately 0.5mA (reasoning)
• The RC time constant with C154 (0.1uF) and 4.7K is 470us, compared to 1ms with the recommended 10K (reasoning)
• The stronger 4.7K pullup provides faster rise time and better noise immunity, but may exceed input current specifications of the receiving circuit (reasoning)
• The component value should be changed to 10K to match the datasheet recommendation explicitly noted on the schematic (reasoning)

_{Upload a datasheet: 📤 R149}

[⚠️ Warning] **Component `R149`, pins `1, 2`: Pullup resistor with correct connections between +PS_5VSB and FP_PWRBTN, but component value (4.7K) does not match the datasheet recommendation of 10K noted in schematic annotations.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="26.71,13.91,34.21,22.58" aspect-ratio="1.29" } - Pin 1 is connected to net FP_PWRBTN *(from schematic)* - Pin 2 is connected to net +PS_5VSB *(from schematic)* - R149 serves as a pullup resistor, pulling FP_PWRBTN high to +PS_5VSB when the power button SW1 is not pressed *(reasoning)* - The component value is 4.7K ohm per part number 110-0002058 *(from schematic)* - Schematic text annotations at coordinates (180.34, 355.6) and (180.34, 360.68) state &#x27;USE 10K PU&#x27; and &#x27;DATASHEET SAYS&#x27;, located near R149 at (172.72, 347.98) *(from schematic)* - These annotations indicate the datasheet for the receiving circuit recommends a 10K pullup resistor *(reasoning)* - With 4.7K, the current draw when the button is pressed is approximately 1.06mA (5V / 4.7K), while 10K would draw approximately 0.5mA *(reasoning)* - The RC time constant with C154 (0.1uF) and 4.7K is 470us, compared to 1ms with the recommended 10K *(reasoning)* - The stronger 4.7K pullup provides faster rise time and better noise immunity, but may exceed input current specifications of the receiving circuit *(reasoning)* - The component value should be changed to 10K to match the datasheet recommendation explicitly noted on the schematic *(reasoning)* _{Upload a datasheet: [📤 R149](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/110-0002058)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component D2, pins A, C: LED is connected in parallel with MOSFET Q105 instead of in series. Anode (A) connects to GPIO_LED_CONTROL net which is shared with Q105 drain, and cathode (C) connects to GND. This creates an inefficient inverted-logic configuration. The correct series topology should be: +VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND.

• Pin A (Anode) is connected to net GPIO_LED_CONTROL (from schematic)
• Pin C (Cathode) is connected to net GND (from schematic)
• Net GPIO_LED_CONTROL connects to Q105 pin D (drain), R746 pin 2, and C149 pin 1 (from schematic)
• D2 is a blue LED (part 4560-0045) with maximum voltage 3.8V (from schematic)
• Blue LEDs typically have forward voltage of 3.0-3.5V (reasoning)
• The current topology creates a parallel configuration where D2 and Q105 drain-source are both connected between GPIO_LED_CONTROL and GND (reasoning)
• In this parallel configuration, when Q105 is OFF (gate low), current flows from +VCC through R746 (470Ω) and D2 to GND, lighting the LED (reasoning)
• When Q105 is ON (gate high), Q105 pulls GPIO_LED_CONTROL low, shorting the LED path and turning it off (reasoning)
• This creates inverted logic: GPIO high = LED off, GPIO low = LED on (reasoning)
• When the LED is off (Q105 ON), current continues to flow from +VCC through R746 and Q105 to GND, wasting approximately 23mW at 3.3V or 53mW at 5V (reasoning)
• The standard configuration for GPIO-controlled LED with N-channel MOSFET low-side switch is series topology: +VCC → R_current_limit → LED_anode → LED_cathode → MOSFET_drain → MOSFET_source → GND (reasoning)
• Series configuration provides non-inverted logic (GPIO high = LED on), zero current when LED is off, and is the overwhelming industry standard (reasoning)
• There is no indication in schematic notes, net names, or documentation that inverted logic is intentional (reasoning)
• The net name 'GPIO_LED_CONTROL' suggests direct control, not inverted control (reasoning)
• If inverted control was intended, typical design practice would include a note or use net naming like 'GPIO_LED_CONTROL_N' or 'LED_OFF' (reasoning)
• The text note 'SYSTEM POWER LED - GPIO CONTROLLED' does not specify or justify inverted control (from schematic)
• For comparison, D1 on the same page uses standard series configuration: +PS_5VSB → D1 → R148 → GND (from schematic)
• The correct connections should be: D2 anode to R746 pin 2 only (on separate net from Q105), and D2 cathode to Q105 drain (on new net) (reasoning)
• This would create the standard series topology with non-inverted logic and zero power consumption when LED is off (reasoning)

_{Upload a datasheet: 📤 D2}

[🚨 Error] **Component `D2`, pins `A, C`: LED is connected in parallel with MOSFET Q105 instead of in series. Anode (A) connects to GPIO_LED_CONTROL net which is shared with Q105 drain, and cathode (C) connects to GND. This creates an inefficient inverted-logic configuration. The correct series topology should be: +VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="61.02,35.08,70.34,42.58" aspect-ratio="1.29" } - Pin A (Anode) is connected to net GPIO_LED_CONTROL *(from schematic)* - Pin C (Cathode) is connected to net GND *(from schematic)* - Net GPIO_LED_CONTROL connects to Q105 pin D (drain), R746 pin 2, and C149 pin 1 *(from schematic)* - D2 is a blue LED (part 4560-0045) with maximum voltage 3.8V *(from schematic)* - Blue LEDs typically have forward voltage of 3.0-3.5V *(reasoning)* - The current topology creates a parallel configuration where D2 and Q105 drain-source are both connected between GPIO_LED_CONTROL and GND *(reasoning)* - In this parallel configuration, when Q105 is OFF (gate low), current flows from +VCC through R746 (470Ω) and D2 to GND, lighting the LED *(reasoning)* - When Q105 is ON (gate high), Q105 pulls GPIO_LED_CONTROL low, shorting the LED path and turning it off *(reasoning)* - This creates inverted logic: GPIO high = LED off, GPIO low = LED on *(reasoning)* - When the LED is off (Q105 ON), current continues to flow from +VCC through R746 and Q105 to GND, wasting approximately 23mW at 3.3V or 53mW at 5V *(reasoning)* - The standard configuration for GPIO-controlled LED with N-channel MOSFET low-side switch is series topology: +VCC → R_current_limit → LED_anode → LED_cathode → MOSFET_drain → MOSFET_source → GND *(reasoning)* - Series configuration provides non-inverted logic (GPIO high = LED on), zero current when LED is off, and is the overwhelming industry standard *(reasoning)* - There is no indication in schematic notes, net names, or documentation that inverted logic is intentional *(reasoning)* - The net name &#x27;GPIO_LED_CONTROL&#x27; suggests direct control, not inverted control *(reasoning)* - If inverted control was intended, typical design practice would include a note or use net naming like &#x27;GPIO_LED_CONTROL_N&#x27; or &#x27;LED_OFF&#x27; *(reasoning)* - The text note &#x27;SYSTEM POWER LED - GPIO CONTROLLED&#x27; does not specify or justify inverted control *(from schematic)* - For comparison, D1 on the same page uses standard series configuration: +PS_5VSB → D1 → R148 → GND *(from schematic)* - The correct connections should be: D2 anode to R746 pin 2 only (on separate net from Q105), and D2 cathode to Q105 drain (on new net) *(reasoning)* - This would create the standard series topology with non-inverted logic and zero power consumption when LED is off *(reasoning)* _{Upload a datasheet: [📤 D2](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/4560-0045)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component U13, pin 10: BST pin bootstrap circuit uses non-standard topology with 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. While the capacitor value (0.1µF) matches datasheet recommendation, the series resistance deviates from datasheet typical application which shows direct capacitor connection between BST and SW pins.

• Pin 10 (BST) is connected to net PS3_BST (from schematic)
• PS3_BST connects to R291 pin 1, R291 pin 2 connects to $22N1498, and C306 connects between $22N1498 and PS3VSB_PHASE (SW node) (from schematic)
• The bootstrap circuit path is: BST -> R291 (4.7Ω) -> C306 (0.1µF) -> SW (from schematic)
• BST is the bootstrap pin requiring a capacitor between SW and BST pins to form a floating supply across the high-side switch driver (from datasheet NB670, page 5)
• Datasheet typical application shows 100nF bootstrap capacitor connected directly between BST and SW with no series resistance (from datasheet NB670, page 18)
• Datasheet layout guidelines recommend keeping BST voltage path (BST, C3, and SW) as short as possible (from datasheet NB670, page 16)
• The minimum off-time is 350ns typical, and typical switching period at 500kHz is 2µs (from datasheet NB670, page 3)
• The 4.7Ω resistor with 0.1µF capacitor creates a time constant of 470ns (reasoning)
• While some designs use small resistors (<1Ω) in bootstrap circuits for inrush current limiting or EMI reduction, 4.7Ω is significantly higher than typical values (reasoning)
• The series resistance adds impedance to the bootstrap charging path, which could impede proper charging especially at higher input voltages with shorter off-times (reasoning)
• The circuit deviates from the datasheet recommended topology without documented justification (reasoning)
• Recommendation: Remove R291 and connect C306 directly between BST (pin 10) and SW (pins 8/9/15/16) per datasheet typical application, or if series resistance is required for specific EMI/inrush reasons, reduce R291 to <1Ω and document the design rationale (reasoning)

_{Replace a datasheet: 📤 U13}

[🚨 Error] **Component `U13`, pin `10`: BST pin bootstrap circuit uses non-standard topology with 4.7Ω series resistor R291 between BST and bootstrap capacitor C306. While the capacitor value (0.1µF) matches datasheet recommendation, the series resistance deviates from datasheet typical application which shows direct capacitor connection between BST and SW pins.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="33298e469e09ec60c397" diff-visibility="full" variant="default" view-coords="61.70,20.38,69.20,27.88" aspect-ratio="1.29" } - Pin 10 (BST) is connected to net PS3_BST *(from schematic)* - PS3_BST connects to R291 pin 1, R291 pin 2 connects to $22N1498, and C306 connects between $22N1498 and PS3VSB_PHASE (SW node) *(from schematic)* - The bootstrap circuit path is: BST -&gt; R291 (4.7Ω) -&gt; C306 (0.1µF) -&gt; SW *(from schematic)* - BST is the bootstrap pin requiring a capacitor between SW and BST pins to form a floating supply across the high-side switch driver *(from datasheet [NB670](<https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=5>), page 5)* - Datasheet typical application shows 100nF bootstrap capacitor connected directly between BST and SW with no series resistance *(from datasheet [NB670](<https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=18>), page 18)* - Datasheet layout guidelines recommend keeping BST voltage path (BST, C3, and SW) as short as possible *(from datasheet [NB670](<https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=16>), page 16)* - The minimum off-time is 350ns typical, and typical switching period at 500kHz is 2µs *(from datasheet [NB670](<https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379#page=3>), page 3)* - The 4.7Ω resistor with 0.1µF capacitor creates a time constant of 470ns *(reasoning)* - While some designs use small resistors (&lt;1Ω) in bootstrap circuits for inrush current limiting or EMI reduction, 4.7Ω is significantly higher than typical values *(reasoning)* - The series resistance adds impedance to the bootstrap charging path, which could impede proper charging especially at higher input voltages with shorter off-times *(reasoning)* - The circuit deviates from the datasheet recommended topology without documented justification *(reasoning)* - Recommendation: Remove R291 and connect C306 directly between BST (pin 10) and SW (pins 8/9/15/16) per datasheet typical application, or if series resistance is required for specific EMI/inrush reasons, reduce R291 to &lt;1Ω and document the design rationale *(reasoning)* _{Replace a datasheet: [📤 U13](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NB670)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component U26, pins 9, 30: GH (pin 9) and GL (pin 30) show no net connections. This is a critical error as these gate driver outputs must be connected to drive external MOSFETs.

• Pin 9 (GH) and pin 30 (GL) both show empty string for net connections (from schematic)
• GH is the high-side gate driver output and GL is the low-side gate driver output (reasoning)
• Pin 8 (BST) is connected to a bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) that connects to switch node pin 10 (SW1) (from schematic)
• The presence of a bootstrap circuit is definitive evidence that external MOSFETs are required, as bootstrap circuits are only needed to provide gate drive voltage for external high-side MOSFETs (reasoning)
• The controller has separate power ground pins (PGND1-PGND6 on pins 19-24) distinct from signal ground, which is typical for controllers with external MOSFETs (from schematic)
• Multiple switch node pins (SW1-SW7) and separate gate driver outputs indicate a multiphase controller with external power stage (reasoning)
• Text note 'IMAX = 24A' near the inductor area suggests high current capability requiring external MOSFETs (from schematic)
• If MOSFETs were integrated, there would be no need for external gate driver pins, bootstrap circuit, or separate power ground pins (reasoning)
• The empty net names suggest missing connections rather than off-page connections, as other nets in the design have proper net names (reasoning)
• Without connections to GH and GL, the external MOSFETs cannot be driven and the converter will not function (reasoning)

_{Upload a datasheet: 📤 U26}

[🚨 Error] **Component `U26`, pins `9, 30`: GH (pin 9) and GL (pin 30) show no net connections. This is a critical error as these gate driver outputs must be connected to drive external MOSFETs.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="37.39,39.49,54.89,48.75" aspect-ratio="1.29" } - Pin 9 (GH) and pin 30 (GL) both show empty string for net connections *(from schematic)* - GH is the high-side gate driver output and GL is the low-side gate driver output *(reasoning)* - Pin 8 (BST) is connected to a bootstrap circuit consisting of R228 (2.20Ω) and C186 (0.22µF) that connects to switch node pin 10 (SW1) *(from schematic)* - The presence of a bootstrap circuit is definitive evidence that external MOSFETs are required, as bootstrap circuits are only needed to provide gate drive voltage for external high-side MOSFETs *(reasoning)* - The controller has separate power ground pins (PGND1-PGND6 on pins 19-24) distinct from signal ground, which is typical for controllers with external MOSFETs *(from schematic)* - Multiple switch node pins (SW1-SW7) and separate gate driver outputs indicate a multiphase controller with external power stage *(reasoning)* - Text note &#x27;IMAX = 24A&#x27; near the inductor area suggests high current capability requiring external MOSFETs *(from schematic)* - If MOSFETs were integrated, there would be no need for external gate driver pins, bootstrap circuit, or separate power ground pins *(reasoning)* - The empty net names suggest missing connections rather than off-page connections, as other nets in the design have proper net names *(reasoning)* - Without connections to GH and GL, the external MOSFETs cannot be driven and the converter will not function *(reasoning)* _{Upload a datasheet: [📤 U26](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/NCP81109GMNTXG)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component R170, pins 1, 2: R170 is configured as a pull-down resistor from VBOOT to ground. However, a text note indicates VBOOT should be 1.1V to set ADDR to 0x1, which is inconsistent with a pull-down to ground.

• Pin 1 is connected to net $24N3564, which connects to U26 pin 31 (VBOOT) (from schematic)
• Pin 2 is connected to AGND-VGFX (analog ground) (from schematic)
• R170 is a 100K resistor configured as a pull-down from VBOOT to ground (reasoning)
• A text note on the schematic states 'VBOOT = 1.1V ADDR = 0x1' (from schematic)
• The text note indicates that to achieve address 0x1, VBOOT should be at 1.1V (reasoning)
• A pull-down resistor to ground would set VBOOT to approximately 0V, not 1.1V (reasoning)
• The pull-down configuration is inconsistent with the text note requirement of VBOOT = 1.1V for address 0x1 (reasoning)
• Without the NCP81109GMNTXG datasheet, the exact VBOOT configuration requirements cannot be verified (reasoning)
• To set VBOOT to 1.1V, a pull-up to a 1.1V supply or a voltage divider would be needed instead of a pull-down (reasoning)
• The design team should verify the intended address setting and update either the circuit or the text note to resolve the inconsistency (reasoning)

[🚨 Error] **Component `R170`, pins `1, 2`: R170 is configured as a pull-down resistor from VBOOT to ground. However, a text note indicates VBOOT should be 1.1V to set ADDR to 0x1, which is inconsistent with a pull-down to ground.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="54.66,40.08,62.16,49.34" aspect-ratio="1.29" } - Pin 1 is connected to net $24N3564, which connects to U26 pin 31 (VBOOT) *(from schematic)* - Pin 2 is connected to AGND-VGFX (analog ground) *(from schematic)* - R170 is a 100K resistor configured as a pull-down from VBOOT to ground *(reasoning)* - A text note on the schematic states &#x27;VBOOT = 1.1V ADDR = 0x1&#x27; *(from schematic)* - The text note indicates that to achieve address 0x1, VBOOT should be at 1.1V *(reasoning)* - A pull-down resistor to ground would set VBOOT to approximately 0V, not 1.1V *(reasoning)* - The pull-down configuration is inconsistent with the text note requirement of VBOOT = 1.1V for address 0x1 *(reasoning)* - Without the NCP81109GMNTXG datasheet, the exact VBOOT configuration requirements cannot be verified *(reasoning)* - To set VBOOT to 1.1V, a pull-up to a 1.1V supply or a voltage divider would be needed instead of a pull-down *(reasoning)* - The design team should verify the intended address setting and update either the circuit or the text note to resolve the inconsistency *(reasoning)*

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component R816, pins 1, 2: On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead.

• R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) (from schematic)
• Schematic note specifies 'Rton=806K, F=285KHz' as design requirement (from schematic)
• With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz (reasoning)
• With specified 806K: calculated frequency is ~289kHz, matching the design target (reasoning)
• The 464K value does not meet the design constraint of 285kHz operation (reasoning)
• R816 should be changed to 806K to achieve the specified 285kHz switching frequency (reasoning)

All affected pins

Component U41, pin `12`: TON pin has incorrect resistor value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency. Current value results in ~500kHz operation.

• Pin 12 (TON) is connected to net $25N1081 (from schematic)
• Net $25N1081 connects to R816 (464K to +5VSB) and C378 (0.1uF to GND, DNI) (from schematic)
• Schematic note specifies 'Rton=806K, F=285KHz' as design requirement (from schematic)
• With R816=464K, VVDDQ=1.35V, VIN=5V: tON = 3.85p × 464K × 1.35 / 4.5 = 537ns (reasoning)
• Calculated switching frequency with 464K is f = 1.35 / (5 × 537n) = 503kHz (reasoning)
• With specified 806K: tON = 3.85p × 806K × 1.35 / 4.5 = 933ns, f = 289kHz (reasoning)
• Actual resistor value of 464K does not meet the design constraint of 806K for 285kHz operation (reasoning)
• R816 should be changed to 806K to meet the specified switching frequency (reasoning)

Component R816, pins `1, 2`: On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead.

• R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) (from schematic)
• Schematic note specifies 'Rton=806K, F=285KHz' as design requirement (from schematic)
• With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz (reasoning)
• With specified 806K: calculated frequency is ~289kHz, matching the design target (reasoning)
• The 464K value does not meet the design constraint of 285kHz operation (reasoning)
• R816 should be changed to 806K to achieve the specified 285kHz switching frequency (reasoning)

Datasheets: 📄 U41

_{Replace a datasheet: 📤 U41}

[🚨 Error] **Component `R816`, pins `1, 2`: On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,35.08,35.12,44.34" aspect-ratio="1.29" } - R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) *(from schematic)* - Schematic note specifies &#x27;Rton=806K, F=285KHz&#x27; as design requirement *(from schematic)* - With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz *(reasoning)* - With specified 806K: calculated frequency is ~289kHz, matching the design target *(reasoning)* - The 464K value does not meet the design constraint of 285kHz operation *(reasoning)* - R816 should be changed to 806K to achieve the specified 285kHz switching frequency *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U41</code>, pin `12`: TON pin has incorrect resistor value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency. Current value results in ~500kHz operation.</summary> - Pin 12 (TON) is connected to net $25N1081 *(from schematic)* - Net $25N1081 connects to R816 (464K to +5VSB) and C378 (0.1uF to GND, DNI) *(from schematic)* - Schematic note specifies &#x27;Rton=806K, F=285KHz&#x27; as design requirement *(from schematic)* - With R816=464K, VVDDQ=1.35V, VIN=5V: tON = 3.85p × 464K × 1.35 / 4.5 = 537ns *(reasoning)* - Calculated switching frequency with 464K is f = 1.35 / (5 × 537n) = 503kHz *(reasoning)* - With specified 806K: tON = 3.85p × 806K × 1.35 / 4.5 = 933ns, f = 289kHz *(reasoning)* - Actual resistor value of 464K does not meet the design constraint of 806K for 285kHz operation *(reasoning)* - R816 should be changed to 806K to meet the specified switching frequency *(reasoning)* </details> <details> <summary>Component <code>R816</code>, pins `1, 2`: On-time setting resistor has incorrect value. R816 is 464K but schematic note specifies 806K for 285kHz switching frequency, resulting in ~500kHz instead.</summary> - R816 is 464K resistor connecting +5VSB (pin 1) to TON pin (pin 2) *(from schematic)* - Schematic note specifies &#x27;Rton=806K, F=285KHz&#x27; as design requirement *(from schematic)* - With R816=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is ~503kHz *(reasoning)* - With specified 806K: calculated frequency is ~289kHz, matching the design target *(reasoning)* - The 464K value does not meet the design constraint of 285kHz operation *(reasoning)* - R816 should be changed to 806K to achieve the specified 285kHz switching frequency *(reasoning)* </details> </details> Datasheets: [📄 U41](https://www.richtek.com/SaveDownload.aspx?specid=RT8207P) _{Replace a datasheet: [📤 U41](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/RT8207)}

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented 2026-05-27 22:33:44 +00:00

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[🚨 Error] Component U38, pins 5, 9: VIN-1 and VIN-2 pins connected to +VDIMM, but circuit has fundamental design flaws preventing operation: (1) Circular startup dependency - U38 requires +VDIMM to operate, but +VDIMM is only available after U38 asserts power good to enable Q5, (2) Q5 current rating insufficient (3.5A max vs 4.9A required), (3) Q5 voltage drop excessive, leaving insufficient input voltage for regulation.

• Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic)
• +VDIMM is sourced from +V1P35S (1.35V) through Q5, an N-channel MOSFET (RXR035N03) (from schematic)
• Q5 gate (1P35V_EN) is controlled by U38's power good output (V1P0S_PG) through R134 (1K) (from schematic)
• This creates a circular dependency: U38 needs +VDIMM to start up and generate V1P0S_PG, but +VDIMM is only available when Q5 is enabled by V1P0S_PG (reasoning)
• At startup with Q5 off, the body diode would conduct from +V1P35S to +VDIMM, providing approximately 1.35V - 0.7V = 0.65V (reasoning)
• With only 0.65V input, U38 cannot regulate a 1.0V output, preventing circuit startup (reasoning)
• Schematic note near Q5 specifies 'Id MAX = 3.5 Amps' for Q5's maximum drain current (from schematic)
• Text notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic)
• The required 4.9A exceeds Q5's 3.5A rating by 40%, making Q5 severely undersized (reasoning)
• Schematic notes specify Q5 Rds(on) as 'VGS=5V Rds(on)=90m MAX' (from schematic)
• With gate driven to approximately 5V and source at 1.35V, Vgs = 3.65V, resulting in Rds(on) higher than the specified 90mΩ at Vgs=5V (reasoning)
• At 4.9A with Rds(on) ≈ 100mΩ, voltage drop across Q5 is approximately 0.49V (reasoning)
• +VDIMM would be only 1.35V - 0.49V = 0.86V, which is insufficient for U38 to regulate a 1.0V output (negative dropout voltage) (reasoning)
• The circuit has three critical design errors: (1) circular startup dependency preventing initial operation, (2) Q5 current rating insufficient for the load, (3) excessive voltage drop across Q5 preventing proper regulation even if startup were possible (reasoning)
• Input decoupling capacitor C118 (10uF) is present on +VDIMM (from schematic)

_{Upload a datasheet: 📤 U38}

[🚨 Error] **Component `U38`, pins `5, 9`: VIN-1 and VIN-2 pins connected to +VDIMM, but circuit has fundamental design flaws preventing operation: (1) Circular startup dependency - U38 requires +VDIMM to operate, but +VDIMM is only available after U38 asserts power good to enable Q5, (2) Q5 current rating insufficient (3.5A max vs 4.9A required), (3) Q5 voltage drop excessive, leaving insufficient input voltage for regulation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...5cce29a752c903f6a6787fca1e97751371b816ac" pr="195" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="18.53,18.61,28.30,30.82" aspect-ratio="1.29" } - Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net *(from schematic)* - +VDIMM is sourced from +V1P35S (1.35V) through Q5, an N-channel MOSFET (RXR035N03) *(from schematic)* - Q5 gate (1P35V_EN) is controlled by U38&#x27;s power good output (V1P0S_PG) through R134 (1K) *(from schematic)* - This creates a circular dependency: U38 needs +VDIMM to start up and generate V1P0S_PG, but +VDIMM is only available when Q5 is enabled by V1P0S_PG *(reasoning)* - At startup with Q5 off, the body diode would conduct from +V1P35S to +VDIMM, providing approximately 1.35V - 0.7V = 0.65V *(reasoning)* - With only 0.65V input, U38 cannot regulate a 1.0V output, preventing circuit startup *(reasoning)* - Schematic note near Q5 specifies &#x27;Id MAX = 3.5 Amps&#x27; for Q5&#x27;s maximum drain current *(from schematic)* - Text notes indicate load currents of &#x27;V1.05 : 1.3A&#x27; and &#x27;V1.0 : 3.6A&#x27;, totaling 4.9A *(from schematic)* - The required 4.9A exceeds Q5&#x27;s 3.5A rating by 40%, making Q5 severely undersized *(reasoning)* - Schematic notes specify Q5 Rds(on) as &#x27;VGS=5V Rds(on)=90m MAX&#x27; *(from schematic)* - With gate driven to approximately 5V and source at 1.35V, Vgs = 3.65V, resulting in Rds(on) higher than the specified 90mΩ at Vgs=5V *(reasoning)* - At 4.9A with Rds(on) ≈ 100mΩ, voltage drop across Q5 is approximately 0.49V *(reasoning)* - +VDIMM would be only 1.35V - 0.49V = 0.86V, which is insufficient for U38 to regulate a 1.0V output (negative dropout voltage) *(reasoning)* - The circuit has three critical design errors: (1) circular startup dependency preventing initial operation, (2) Q5 current rating insufficient for the load, (3) excessive voltage drop across Q5 preventing proper regulation even if startup were possible *(reasoning)* - Input decoupling capacitor C118 (10uF) is present on +VDIMM *(from schematic)* _{Upload a datasheet: [📤 U38](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/5b0c851c/.allspice/datasheets/APL5912KAC-TRGS-X)}

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Reference: NoIndexTests/E2E-Turbot-BOMGEN#195

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