E2E @ 24f21021 - manual run: su/alternate-formats verification @ 24f2102 (3x per repo) #196

Closed

shrikanthup wants to merge 2 commits from refs/pull/196/head into main

shrikanthup commented

2026-05-27 21:20:03 +00:00

(Migrated from staging.allspice.dev)

Source: manual run: su/alternate-formats verification @ 24f2102 (3x per repo)
Ref: 24f210213d4b98412292018488d65ea5fa571e4f
Mode: e2e
Cache: enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache)
Cleanup: auto-closed after 7 days

Resolved config

{
  "dump_analysis_dir": "debug_dump",
  "libraries": [
    {
      "ipn_column": "IPN",
      "mpn_column": "MPN",
      "path": ".allspice/library.csv",
      "type": "csv"
    },
    {
      "digikey_client_id_env": "DIGIKEY_CLIENT_ID",
      "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET",
      "type": "digikey"
    }
  ]
}

Triggered at 2026-05-27T21:20:00.315792Z. Branch 58364de5 will be deleted on cleanup.

**Source:** manual run: su/alternate-formats verification @ 24f2102 (3x per repo) **Ref:** [`24f210213d4b98412292018488d65ea5fa571e4f`](https://github.com/AllSpiceIO/connections-checker/tree/24f210213d4b98412292018488d65ea5fa571e4f) **Mode:** e2e **Cache:** enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache) **Cleanup:** auto-closed after 7 days <details> <summary>Resolved config</summary> ```json { "dump_analysis_dir": "debug_dump", "libraries": [ { "ipn_column": "IPN", "mpn_column": "MPN", "path": ".allspice/library.csv", "type": "csv" }, { "digikey_client_id_env": "DIGIKEY_CLIENT_ID", "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET", "type": "digikey" } ] } ``` </details> Triggered at 2026-05-27T21:20:00.315792Z. Branch `58364de5` will be deleted on cleanup.

AllSpiceAlice commented

2026-05-27 21:43:31 +00:00

(Migrated from staging.allspice.dev)

DRCY has reviewed this Design Review, and there should be a review posted below.

AllSpiceAlice (Migrated from staging.allspice.dev) reviewed 2026-05-28 00:08:45 +00:00

AllSpiceAlice (Migrated from staging.allspice.dev) left a comment

DRCY Connections Checker Review

DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 355 component(s) to review, and found 8 potential issue(s) in 9 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
AK12	DDI0_RCOMP_P	DDI_RCOMP_N	❌	DDI0_RCOMP pins are swapped. Pin AK13 uses overline notation (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅) indicating negative polarity but connects to DDI_RCOMP_P net, while pin AK12 labeled DDI0_RCOMP_P (positive) connects to DDI_RCOMP_N net. Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in the schematic (from schematic) Pin AK12 is labeled DDI0_RCOMP_P in the schematic (from schematic) Pin AK13 connects to net DDI_RCOMP_P (from schematic) Pin AK12 connects to net DDI_RCOMP_N (from schematic) Overline notation in electronics indicates negative, inverted, or complement signals (reasoning) The _P suffix in pin names indicates positive polarity (reasoning) Pin AK12 is described as DDI0_RCOMP_P (positive) in the datasheet (from datasheet 140-0004628) Pin AK13 with overline notation should be the negative RCOMP signal (reasoning) The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning) The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning) The connections should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning) R217 (402 ohm) correctly connects between the two RCOMP nets, but the CPU pin assignments need correction (from schematic)
AK13	~DDI0_RCOMP	DDI_RCOMP_P	❌	DDI0_RCOMP pins are swapped. Pin AK13 uses overline notation (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅) indicating negative polarity but connects to DDI_RCOMP_P net, while pin AK12 labeled DDI0_RCOMP_P (positive) connects to DDI_RCOMP_N net. Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in the schematic (from schematic) Pin AK12 is labeled DDI0_RCOMP_P in the schematic (from schematic) Pin AK13 connects to net DDI_RCOMP_P (from schematic) Pin AK12 connects to net DDI_RCOMP_N (from schematic) Overline notation in electronics indicates negative, inverted, or complement signals (reasoning) The _P suffix in pin names indicates positive polarity (reasoning) Pin AK12 is described as DDI0_RCOMP_P (positive) in the datasheet (from datasheet 140-0004628) Pin AK13 with overline notation should be the negative RCOMP signal (reasoning) The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning) The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning) The connections should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning) R217 (402 ohm) correctly connects between the two RCOMP nets, but the CPU pin assignments need correction (from schematic)
A29	RESERVED_A29	GPIO_NC13	✅	RESERVED_A29 pin connected to GPIO_NC13 with 10K pull-down resistor to ground. This configuration prevents the unused GPIO from floating.
B26	DDI0_BKLTCTL		✅	DDI0_BKLTCTL backlight control pin for display port 0, left unconnected. This is acceptable for HDMI which doesn't require backlight control.
B28	DDI0_VDDEN		✅	DDI0_VDDEN display power enable pin for display port 0, left unconnected. This is acceptable for HDMI which doesn't require this control signal.
B30	GPIO_S0_NC12	$3N566	✅	GPIO_S0_NC12 pin connected to test point TP15. This provides access to the GPIO signal for testing or debugging.
C26	DDI0_DDCDATA	HDMI_DDCDAT	✅	DDI0_DDCDATA pin connected to HDMI_DDCDAT for HDMI DDC data communication.
C27	DDI0_BKLTEN		✅	DDI0_BKLTEN backlight enable pin for display port 0, left unconnected. This is acceptable for HDMI which doesn't require backlight enable.
C28	DDI0_DDCCLK	HDMI_DDCCLK	✅	DDI0_DDCCLK pin connected to HDMI_DDCCLK for HDMI DDC clock communication.
D27	DDI0_HPD	HDMI_HPD_B	✅	DDI0_HPD pin connected to HDMI_HPD_B, which is the inverted output of HDMI_HPD through Schmitt trigger U39. The inversion may be intentional depending on system requirements.
G30	DDI1_DDCCLK	GND	✅	DDI1_DDCCLK pin connected directly to ground. This disables DDC communication on display port 1 as part of the intentionally disabled DDI1 interface.
J30	DDI1_BKLTEN		✅	DDI1_BKLTEN backlight enable pin for display port 1, left unconnected as part of disabled DDI1 interface.
K30	DDI1_HPD	GND	✅	DDI1_HPD pin connected directly to ground. This prevents hot plug detection on display port 1 as part of the intentionally disabled DDI1 interface.
M30	DDI1_BKLTCTL		✅	DDI1_BKLTCTL backlight control pin for display port 1, left unconnected as part of disabled DDI1 interface.
N30	DDI1_VDDEN		✅	DDI1_VDDEN display power enable pin for display port 1, left unconnected as part of disabled DDI1 interface.
P14	RESERVED_P14	MCSI_RCOMP	✅	RESERVED_P14 pin connected to MCSI_RCOMP with 150-ohm termination resistor to ground, providing compensation for MIPI CSI interface on Bay Trail-I variant.
P30	DDI1_DDCDATA	DDI1_DDCDAT	✅	DDI1_DDCDATA pin connected to DDI1_DDCDAT with 2.2K pull-down resistor to ground. This provides a weak pull-down for the disabled DDI1 interface.
BA1	VGA_GREEN		✅	VGA_GREEN analog output pin left unconnected, indicating VGA interface is not used in this design.
BA3	VGA_RED		✅	VGA_RED analog output pin left unconnected, indicating VGA interface is not used in this design.
AB12	RESERVED_AB12		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AB13	RESERVED_AB13		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AB14	RESERVED_AB14		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AB2	RESERVED_AB2		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AB3	RESERVED_AB3		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AB7	RESERVED_AB7		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AB9	RESERVED_AB9		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AD4	RESERVED_AD4		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AD6	RESERVED_AD6		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AF13	RESERVED_AF13		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AF14	RESERVED_AF14		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AH13	RESERVED_AH13		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AH14	RESERVED_AH14		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AM13	RESERVED_AM13		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AM14	RESERVED_AM14		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
C29	RESERVED_C29		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
C30	RESERVED_C30		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
D28	RESERVED_D28		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
D32	RESERVED_D32		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
D34	RESERVED_D34		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
F28	RESERVED_F28		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
F32	RESERVED_F32		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
F34	RESERVED_F34		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
J28	RESERVED_J28		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
J34	RESERVED_J34		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
K28	RESERVED_K28		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
K34	RESERVED_K34		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
M32	RESERVED_M32		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
N32	RESERVED_N32		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
R1	RESERVED_R1		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
R3	RESERVED_R3		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T2	RESERVED_T2		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T3	RESERVED_T3		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T4	RESERVED_T4		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T6	RESERVED_T6		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T7	RESERVED_T7		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T9	RESERVED_T9		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T10	RESERVED_T10		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T12	RESERVED_T12		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T13	RESERVED_T13		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
T14	RESERVED_T14		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V10	RESERVED_V10		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V13	RESERVED_V13		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V14	RESERVED_V14		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V2	RESERVED_V2		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V3	RESERVED_V3		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V4	RESERVED_V4		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V6	RESERVED_V6		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
V9	RESERVED_V9		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
W1	RESERVED_W1		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
W3	RESERVED_W3		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
Y12	RESERVED_Y12		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
Y13	RESERVED_Y13		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
Y2	RESERVED_Y2		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
Y3	RESERVED_Y3		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
Y4	RESERVED_Y4		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
Y6	RESERVED_Y6		✅	Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration.
AC1	DDI1_TXN_3		✅	DDI1_TXN_3 and DDI1_TXP_3 differential transmit pair for display port 1 lane 3, left unconnected as part of disabled DDI1 interface.
AC3	DDI1_TXP_3		✅	DDI1_TXN_3 and DDI1_TXP_3 differential transmit pair for display port 1 lane 3, left unconnected as part of disabled DDI1 interface.
BC1	VGA_DDCCLK	CRT_CLK	✅	VGA_DDCCLK pin connected to CRT_CLK with 150-ohm termination resistor to ground.
AD2	DDI1_TXN_2		✅	DDI1_TXN_2 and DDI1_TXP_2 differential transmit pair for display port 1 lane 2, left unconnected as part of disabled DDI1 interface.
AD3	DDI1_TXP_2		✅	DDI1_TXN_2 and DDI1_TXP_2 differential transmit pair for display port 1 lane 2, left unconnected as part of disabled DDI1 interface.
BC2	VGA_DDCDATA	CRT_DAT	✅	VGA_DDCDATA pin connected to CRT_DAT with 150-ohm termination resistor to ground.
BD2	VGA_HSYNC		✅	VGA_HSYNC horizontal sync output pin left unconnected, indicating VGA interface is not used in this design.
AF2	DDI1_TXN_1		✅	DDI1_TXN_1 and DDI1_TXP_1 differential transmit pair for display port 1 lane 1, left unconnected as part of disabled DDI1 interface.
AF3	DDI1_TXP_1		✅	DDI1_TXN_1 and DDI1_TXP_1 differential transmit pair for display port 1 lane 1, left unconnected as part of disabled DDI1 interface.
AG1	DDI1_TXN_0		✅	DDI1_TXN_0 and DDI1_TXP_0 differential transmit pair for display port 1 lane 0, left unconnected as part of disabled DDI1 interface.
AG3	DDI1_TXP_0		✅	DDI1_TXN_0 and DDI1_TXP_0 differential transmit pair for display port 1 lane 0, left unconnected as part of disabled DDI1 interface.
BF2	VGA_VSYNC		✅	VGA_VSYNC vertical sync output pin left unconnected, indicating VGA interface is not used in this design.
AH2	RESERVED_VSS3	$3N554	✅	RESERVED_VSS3 pin connected through 0-ohm resistor R43 to ground, providing optional ground connection.
AH3	RESERVED_VSS2	$3N552	✅	RESERVED_VSS2 pin connected through 0-ohm resistor R46 to ground, providing optional ground connection.
AK2	DDI1_AUXN		✅	DDI1_AUXN and DDI1_AUXP auxiliary channel pins for display port 1, left unconnected as part of disabled DDI1 interface.
AK3	DDI1_AUXP		✅	DDI1_AUXN and DDI1_AUXP auxiliary channel pins for display port 1, left unconnected as part of disabled DDI1 interface.
AL1	DDI0_AUXN		✅	DDI0_AUXN and DDI0_AUXP auxiliary channel pins for display port 0, left unconnected. These are typically used for DisplayPort but not for HDMI.
AL3	DDI0_AUXP		✅	DDI0_AUXN and DDI0_AUXP auxiliary channel pins for display port 0, left unconnected. These are typically used for DisplayPort but not for HDMI.
AM2	RESERVED_VSS1	$3N589	✅	RESERVED_VSS1 pin connected through 0-ohm resistor R41 to ground, providing optional ground connection.
AM3	RESERVED_VSS0	$3N579	✅	RESERVED_VSS0 pin connected through 0-ohm resistor R42 to ground, providing optional ground connection.
AP2	DDI0_TXN_3	HDMI_CLK_DN	✅	DDI0_TXN_3 and DDI0_TXP_3 differential transmit pair connected to HDMI_CLK_DN and HDMI_CLK_DP for HDMI clock output.
AP3	DDI0_TXP_3	HDMI_CLK_DP	✅	DDI0_TXN_3 and DDI0_TXP_3 differential transmit pair connected to HDMI_CLK_DN and HDMI_CLK_DP for HDMI clock output.
AR1	DDI0_TXN_2	HDMI_TX0_DN	✅	DDI0_TXN_2 and DDI0_TXP_2 differential transmit pair connected to HDMI_TX0_DN and HDMI_TX0_DP for HDMI data lane 0.
AR3	DDI0_TXP_2	HDMI_TX0_DP	✅	DDI0_TXN_2 and DDI0_TXP_2 differential transmit pair connected to HDMI_TX0_DN and HDMI_TX0_DP for HDMI data lane 0.
AT2	DDI0_TXP_1	HDMI_TX1_DP	✅	DDI0_TXP_1 and DDI0_TXN_1 differential transmit pair connected to HDMI_TX1_DP and HDMI_TX1_DN for HDMI data lane 1.
AT3	DDI0_TXN_1	HDMI_TX1_DN	✅	DDI0_TXP_1 and DDI0_TXN_1 differential transmit pair connected to HDMI_TX1_DP and HDMI_TX1_DN for HDMI data lane 1.
AV2	DDI0_TXN_0	HDMI_TX2_DN	✅	DDI0_TXN_0 and DDI0_TXP_0 differential transmit pair connected to HDMI_TX2_DN and HDMI_TX2_DP for HDMI data lane 2.
AV3	DDI0_TXP_0	HDMI_TX2_DP	✅	DDI0_TXN_0 and DDI0_TXP_0 differential transmit pair connected to HDMI_TX2_DN and HDMI_TX2_DP for HDMI data lane 2.
AW1	VGA_IREF	$3N548	✅	VGA_IREF pin connected through 357-ohm resistor R40 to ground, setting the reference current for VGA DAC.
AY2	VGA_BLUE		✅	VGA_BLUE analog output pin left unconnected, indicating VGA interface is not used in this design.
AY3	VGA_IRTN	GND	✅	VGA_IRTN pin connected directly to ground, providing return path for VGA DAC reference current.

U39 - SN74LVC1G14DCKR ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	No Connect pin is unconnected, which is acceptable per datasheet specifications.
2	A	HDMI_HPD	✅	Input pin A is connected to HDMI_HPD signal, which is the hot plug detect from the HDMI connector. This input is inverted and conditioned by the Schmitt-trigger.
3	GND	GND	✅	Ground pin is correctly connected to GND.
4	Y	HDMI_HPD_B	✅	Output pin Y is connected to HDMI_HPD_B, which feeds the CPU's DDI0_HPD input. The inverted and conditioned hot plug detect signal is correctly routed to the display controller.
5	VCC	+V1P8S	✅	VCC pin is correctly connected to +V1P8S (1.8V supply), which is within the device's operating range of 1.65V to 5.5V. Bypass capacitor C375 (0.1µF) is present nearby.

R38 - 150 ohm 1% 1/16W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_DAT	✅	150Ω resistor connected between VGA_DDCDATA (CRT_DAT) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2.
2	2	GND	✅	150Ω resistor connected between VGA_DDCDATA (CRT_DAT) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2.

R39 - 150 ohm 1% 1/16W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_CLK	✅	150Ω resistor connected between VGA_DDCCLK (CRT_CLK) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2.
2	2	GND	✅	150Ω resistor connected between VGA_DDCCLK (CRT_CLK) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2.

R40 - RES_357R_1/10W_1%_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$3N548	✅	R40 is a 357Ω resistor connected between VGA_IREF and ground to set the VGA DAC reference current.
2	2	GND	✅	R40 is a 357Ω resistor connected between VGA_IREF and ground to set the VGA DAC reference current.

R257 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI1_DDCDAT	✅	Connected to DDI1_DDCDAT signal from CPU1 pin P30.
2	2	GND	✅	Connected to ground to provide pull-down termination.

R217 - 402 ohm 1% 1/4W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI_RCOMP_N	✅	R217 correctly provides 402-ohm compensation resistance between DDI_RCOMP_N and DDI_RCOMP_P nets. The resistor specification and connection between the two nets is correct; the issue exists at the CPU pin level where the nets are swapped.
2	2	DDI_RCOMP_P	✅	R217 correctly provides 402-ohm compensation resistance between DDI_RCOMP_N and DDI_RCOMP_P nets. The resistor specification and connection between the two nets is correct; the issue exists at the CPU pin level where the nets are swapped.

R213 - 150 ohm 1% 1/16W 0402 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCSI_RCOMP	✅	R213 correctly connects MCSI_RCOMP to GND with 150-ohm resistance, providing impedance calibration for the MIPI CSI interface.
2	2	GND	✅	R213 correctly connects MCSI_RCOMP to GND with 150-ohm resistance, providing impedance calibration for the MIPI CSI interface.

CPU1 - INTEL_ATOM_E3825_SOC ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
C24	~PROCHOT	VR_HOT_L	✅	Processor hot thermal alert signal, correctly pulled up with 73.2 ohm resistor.
N34	RESERVED_N34		✅	Reserved pin, correctly left unconnected per datasheet requirements.
P34	RESERVED_P34		✅	Reserved pin, correctly left unconnected per datasheet requirements.
BA12	SATA_GP0	SATA_GP0	✅	SATA general purpose signal 0, correctly pulled down with 10K resistor as it is not used.
BA16	SATA_RXN_1	SATA1_RXN	✅	SATA port 1 receive negative, correctly AC-coupled with 0.01uF capacitor to mSATA interface.
BA18	SD2_CLK		✅	SD2 clock signal, not connected as SD2 interface is not used.
BA20	SD2_D2		✅	SD2 data bit 2, not connected as SD2 interface is not used.
BA24	~MMC1_RST		✅	MMC1 reset signal, not connected as MMC1 interface is not used.
BA26	SD3_D3	SD3_D3	✅	SD3 data bit 3, connected to SD card interface.
BA30	LPE_I2S2_FRM	LPE_I2S_FRM	✅	I2S frame sync signal from Low Power Engine, correctly pulled up with 10K resistor.
BB3	RESERVED_BB3		✅	Reserved pin, correctly left unconnected per datasheet requirements.
BB4	RESERVED_BB4		✅	Reserved pin, correctly left unconnected per datasheet requirements.
BB5	RESERVED_VSS6	RESERVED_VSS6	✅	Reserved VSS pin, correctly connected to ground through 0 ohm resistor.
BB7	RESERVED_VSS7	RESERVED_VSS7	✅	Reserved VSS pin, correctly connected to ground through 0 ohm resistor.
BB10	RESERVED_VSS4	ICLK_SATA_TERMP	✅	Reserved VSS pin used for SATA clock termination positive, connected to ground through 0 ohm resistor.
BC10	RESERVED_VSS5	ICLK_SATA_TERMN	✅	Reserved VSS pin used for SATA clock termination negative, connected to ground through 0 ohm resistor.
BC18	SD2_CMD		✅	SD2 command signal, not connected as SD2 interface is not used.
BC24	SD3_CD#	SD3_CD#	✅	SD3 card detect signal, connected through 0 ohm resistor to SD3_WP pin in an unusual configuration.
BC30	LPE_I2S2_DATAOUT	LPE_I2S_DATOUT	✅	I2S data output from Low Power Engine, connected through 1K resistor to GPIO unlock signal.
BD5	SD3_WP_BD5	SD3_WP	✅	SD3 write protect signal, connected through 0 ohm resistor to SD3_CD# in an unusual configuration specific to Bay Trail-I.
BD7	~PCIE_CLKREQ_1	CLKREQ1_B	✅	PCIe clock request 1 signal, correctly pulled up with 10K resistor.
BD10	SATA_TXP1	SATA1_TXP	✅	SATA port 1 transmit positive, correctly AC-coupled with 0.01uF capacitor to mSATA interface.
BD18	~SD2_D3_CD		✅	SD2 data bit 3 / card detect signal, not connected as SD2 interface is not used.
BD20	SD2_D1		✅	SD2 data bit 1, not connected as SD2 interface is not used.
BD22	~SD3_PWREN	/SD3+PWREN	✅	SD3 power enable signal, connected to test point for monitoring.
BD26	SD3_D1	SD3_D1	✅	SD3 data bit 1, connected to SD card interface.
BD28	LPE_I2S2_DATAIN	LPE_I2S_DATIN	✅	I2S data input to Low Power Engine, connected to audio interface.
BE3	~PCIE_CLKREQ_3	mPCIe_CLKREQ3_B	✅	PCIe clock request 3 signal for mini PCIe, correctly pulled up with 10K resistor.
BF6	SATA_TXP_0	SATA0_TXP	✅	SATA port 0 transmit positive, correctly AC-coupled with 0.01uF capacitor to connector.
BF10	SATA_TXN_1	SATA1_TXN	✅	SATA port 1 transmit negative, correctly AC-coupled with 0.01uF capacitor to mSATA interface.
BF20	HDA_LPE_RCOMP	HDA_RCOMP	✅	HD Audio / Low Power Engine compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
BF22	SD3_1P8EN	SD3_1P8EN	✅	SD3 1.8V enable signal, connected to test point for monitoring.
BF26	SD3_RCOMP	SD3_RCOMP	✅	SD3 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
BF28	LPE_I2S2_CLK	LPE_I2S_CLK	✅	I2S clock signal from Low Power Engine, connected to audio interface.
BG3	~PCIE_CLKREQ_0	CLKREQ0_B	✅	PCIe clock request 0 signal, correctly pulled up with 10K resistor.
BG5	~PCIE_CLKREQ_2	LAN_CLKREQ2_B	✅	PCIe clock request 2 signal for LAN, correctly pulled up with 10K resistor.
BG7	SATA_TXN_0	SATA0_TXN	✅	SATA port 0 transmit negative, correctly AC-coupled with 0.01uF capacitor to connector.
BG18	GPIO_S0_SC_15		✅	GPIO pin, not connected as it is not used.
BG19	HDA_SDI0		✅	HD Audio serial data input 0, not connected as HD Audio interface is not used.
BG20	HDA_SDO		✅	HD Audio serial data output, not connected as HD Audio interface is not used.
BG21	HDA_SDI1		✅	HD Audio serial data input 1, not connected as HD Audio interface is not used.
BG22	~HDA_RST		✅	HD Audio reset signal, not connected as HD Audio interface is not used.
BH18	GPIO_S0_SC_14		✅	GPIO pin, not connected as it is not used.
BH20	HDA_SYNC		✅	HD Audio sync signal, not connected as HD Audio interface is not used.
AK7	RESERVED_AK7		✅	Reserved pin, correctly left unconnected per datasheet requirements.
AK9	RESERVED_AK9		✅	Reserved pin, correctly left unconnected per datasheet requirements.
BJ21	HDA_CLK		✅	HD Audio clock signal, not connected as HD Audio interface is not used.
AP4	PCIE_TXN_3	mPCIE_TX_N	✅	PCIe transmit negative for lane 3, connected to mini PCIe slot.
AP6	PCIE_TXP_3	mPCIE_TX_P	✅	PCIe transmit positive for lane 3, connected to mini PCIe slot.
AP7	PCIE_RXN_3	mPCIE_RX_N	✅	PCIe receive negative for lane 3, connected to mini PCIe slot.
AP9	PCIE_RXP_3	mPCIE_RX_P	✅	PCIe receive positive for lane 3, connected to mini PCIe slot.
AP10	PCIE_RXN_2	PCIE_RXN2	✅	PCIe receive negative for lane 2, connected to LAN interface.
AP12	PCIE_RXP_2	PCIE_RXP2	✅	PCIe receive positive for lane 2, connected to LAN interface.
AP13	PCIE_RCOMP_N_AP13_AP13	PCIE_RCOMP_N	✅	PCIe compensation resistor negative pin, correctly connected with 402 ohm resistor to positive pin.
AP14	PCIE_RCOMP_P_AP14_AP14	PCIE_RCOMP_P	✅	PCIe compensation resistor positive pin, correctly connected with 402 ohm resistor to negative pin.
AT6	PCIE_TXN_2	PCIE_TXN2	✅	PCIe transmit negative for lane 2, connected to LAN interface.
AT7	PCIE_TXP_2	PCIE_TXP2	✅	PCIe transmit positive for lane 2, connected to LAN interface.
AT9	PCIE_RXN_1		✅	PCIe receive negative for lane 1, not connected as PCIe lane 1 is not used.
AT10	PCIE_RXP_1		✅	PCIe receive positive for lane 1, not connected as PCIe lane 1 is not used.
AT13	PCIE_RXN_0		✅	PCIe receive negative for lane 0, not connected as PCIe lane 0 is not used.
AT14	PCIE_RXP_0		✅	PCIe receive positive for lane 0, not connected as PCIe lane 0 is not used.
AT18	SATA_RCOMP_N_AT18	SATA_RCOMP_N	✅	SATA compensation resistor negative pin, correctly connected with 402 ohm resistor to positive pin.
AT20	MMC1_D3		✅	MMC1 data bit 3, not connected as MMC1 interface is not used.
AT22	MMC1_CLK		✅	MMC1 clock signal, not connected as MMC1 interface is not used.
AT26	MMC1_D6		✅	MMC1 data bit 6, not connected as MMC1 interface is not used.
AT28	SD3_D0	SD3_D0	✅	SD3 data bit 0, connected to SD card interface.
AU16	SATA_RXP_0	SATA0_RXP	✅	SATA port 0 receive positive, correctly AC-coupled with 0.01uF capacitor to connector.
AU18	SATA_RCOMP_P_AU18	SATA_RCOMP_P	✅	SATA compensation resistor positive pin, correctly connected with 402 ohm resistor to negative pin.
AU20	MMC1_D7		✅	MMC1 data bit 7, not connected as MMC1 interface is not used.
AU22	MMC1_D1		✅	MMC1 data bit 1, not connected as MMC1 interface is not used.
AU26	MMC1_D5		✅	MMC1 data bit 5, not connected as MMC1 interface is not used.
AU28	SD3_D2	SD3_D2	✅	SD3 data bit 2, connected to SD card interface.
AV4	PCIE_TXN_1		✅	PCIe transmit negative for lane 1, not connected as PCIe lane 1 is not used.
AV6	PCIE_TXP_1		✅	PCIe transmit positive for lane 1, not connected as PCIe lane 1 is not used.
AV9	RESERVED_AV9		✅	Reserved pin, correctly left unconnected per datasheet requirements.
AV10	RESERVED_AV10		✅	Reserved pin, correctly left unconnected per datasheet requirements.
AV16	SATA_RXN_0	SATA0_RXN	✅	SATA port 0 receive negative, correctly AC-coupled with 0.01uF capacitor to connector.
AV20	MMC1_D0		✅	MMC1 data bit 0, not connected as MMC1 interface is not used.
AV22	MMC1_D2		✅	MMC1 data bit 2, not connected as MMC1 interface is not used.
AV26	MMC1_CMD		✅	MMC1 command signal, not connected as MMC1 interface is not used.
AV28	SD3_CMD	SD3_CMD	✅	SD3 command signal, connected to SD card interface.
AY6	PCIE_TXN_0		✅	PCIe transmit negative for lane 0, not connected as PCIe lane 0 is not used.
AY7	PCIE_TXP_0		✅	PCIe transmit positive for lane 0, not connected as PCIe lane 0 is not used.
AY12	~SATA_LED	SATA_LED_B	✅	SATA activity LED signal, correctly connected through current-limiting resistor to LED driver circuit.
AY14	SATA_GP1	SATA_GP1	✅	SATA general purpose signal 1, correctly pulled down with 10K resistor as it is not used.
AY16	SATA_RXP_1	SATA1_RXP	✅	SATA port 1 receive positive, correctly AC-coupled with 0.01uF capacitor to mSATA interface.
AY18	MMC1_RCOMP	MMC1_RCOMP	✅	MMC1 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground.
AY20	SD2_D0		✅	SD2 data bit 0, not connected as SD2 interface is not used.
AY24	MMC1_D4		✅	MMC1 data bit 4, not connected as MMC1 interface is not used.
AY26	SD3_CLK	SD3_CLK	✅	SD3 clock signal, connected to SD card interface.

J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins for SATA signal connector, correctly connected to circuit ground (GND).
4	4	GND	✅	Ground pins for SATA signal connector, correctly connected to circuit ground (GND).
7	7	GND	✅	Ground pins for SATA signal connector, correctly connected to circuit ground (GND).
2	2	SATA0_TXP_C	✅	TX differential pair (A+/A-) correctly connected through AC coupling capacitors to CPU SATA0 transmit pins.
3	3	SATA0_TXN_C	✅	TX differential pair (A+/A-) correctly connected through AC coupling capacitors to CPU SATA0 transmit pins.
5	5	SATA0_RXN_C	✅	RX differential pair (B-/B+) correctly connected through AC coupling capacitors to CPU SATA0 receive pins.
6	6	SATA0_RXP_C	✅	RX differential pair (B-/B+) correctly connected through AC coupling capacitors to CPU SATA0 receive pins.
8	MH1	GND_EARTH	✅	Mounting holes MH1 and MH2 correctly connected to chassis ground (GND_EARTH) for EMI shielding and ESD protection.
9	MH2	GND_EARTH	✅	Mounting holes MH1 and MH2 correctly connected to chassis ground (GND_EARTH) for EMI shielding and ESD protection.

C177 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_N	✅	AC coupling capacitor connecting mSATA_RX_N to SATA1_RXN. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive negative input.
2	2	SATA1_RXN	✅	AC coupling capacitor connecting mSATA_RX_N to SATA1_RXN. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive negative input.

C178 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_P	✅	AC coupling capacitor connecting mSATA_RX_P to SATA1_RXP. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive positive input.
2	2	SATA1_RXP	✅	AC coupling capacitor connecting mSATA_RX_P to SATA1_RXP. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive positive input.

C180 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_N	✅	AC coupling capacitor connecting mSATA_TX_N to SATA1_TXN. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit negative output to the mSATA device.
2	2	SATA1_TXN	✅	AC coupling capacitor connecting mSATA_TX_N to SATA1_TXN. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit negative output to the mSATA device.

C179 - 0.01uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_P	✅	AC coupling capacitor connecting mSATA_TX_P to SATA1_TXP. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit positive output to the mSATA device.
2	2	SATA1_TXP	✅	AC coupling capacitor connecting mSATA_TX_P to SATA1_TXP. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit positive output to the mSATA device.

R190 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ1_B	✅	This 10K ohm resistor provides a pull-up from the active-low CLKREQ1_B signal to +V1P8S power rail.
2	2	+V1P8S	✅	This 10K ohm resistor provides a pull-up from the active-low CLKREQ1_B signal to +V1P8S power rail.

R2 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mPCIe_CLKREQ3_B	✅	This 10K ohm resistor provides a pull-up from the active-low mPCIe_CLKREQ3_B signal to +V1P8S power rail.
2	2	+V1P8S	✅	This 10K ohm resistor provides a pull-up from the active-low mPCIe_CLKREQ3_B signal to +V1P8S power rail.

R191 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ0_B	✅	This 10K ohm resistor provides a pull-up from the active-low CLKREQ0_B signal to +V1P8S power rail.
2	2	+V1P8S	✅	This 10K ohm resistor provides a pull-up from the active-low CLKREQ0_B signal to +V1P8S power rail.

R71 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_CLKREQ2_B	✅	This 10K ohm resistor provides a pull-up from the active-low LAN_CLKREQ2_B signal to +V1P8S power rail.
2	2	+V1P8S	✅	This 10K ohm resistor provides a pull-up from the active-low LAN_CLKREQ2_B signal to +V1P8S power rail.

R218 - 402 ohm 1% 1/4W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PCIE_RCOMP_P	✅	This 402 ohm resistor is connected between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on CPU1.
2	2	PCIE_RCOMP_N	✅	This 402 ohm resistor is connected between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on CPU1.

R354 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SD3_WP	✅	This 0-ohm resistor connects SD3_WP (write protect) to SD3_CD# (card detect) signals. While this ties together two typically independent SD card interface signals, the connection appears to be an intentional design choice specific to the Bay Trail-I processor implementation, as indicated by schematic notes.
2	2	SD3_CD#	✅	This 0-ohm resistor connects SD3_WP (write protect) to SD3_CD# (card detect) signals. While this ties together two typically independent SD card interface signals, the connection appears to be an intentional design choice specific to the Bay Trail-I processor implementation, as indicated by schematic notes.

R258 - 49.9 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to GND as the reference for the RCOMP resistor.
2	2	SD3_RCOMP	✅	Pin 2 is correctly connected to SD3_RCOMP on the CPU, providing impedance compensation for the SD3 interface.

R242 - 49.9 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDA_RCOMP	✅	Connected to HDA_RCOMP pin (BF20) of the Intel Atom E3825 SOC. This provides impedance compensation for the High Definition Audio interface.
2	2	GND	✅	Connected to GND. This completes the compensation resistor circuit by providing the ground reference.

R240 - 49.9 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This provides the ground reference for the RCOMP impedance calibration resistor.
2	2	MMC1_RCOMP	✅	Connected to MMC1_RCOMP (CPU1 pin AY18). This provides impedance calibration for the MMC1 interface.

R208 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP2	✅	1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0.
2	2	GND	✅	1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0.

R234 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP3	✅	1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0.
2	2	GND	✅	1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0.

R211 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1.
2	2	BOM_OP1	✅	10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1.

R400 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1.
2	2	BOM_OP4	✅	10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1.

R268 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_FRM	✅	Connected to LPE_I2S_FRM, which is the I2S frame sync signal from CPU1 pin BA30 (LPE_I2S2_FRM). This pin provides the pullup connection point for the frame sync signal.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing a 10K pull-up for the I2S frame sync signal. This ensures the signal has a defined state.

R259 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_10_UNLOCK	✅	Connected to GPIO_S5_10_UNLOCK signal. This pin provides one end of a series resistor that appears to interface between a GPIO signal and the I2S data output.
2	2	LPE_I2S_DATOUT	✅	Connected to LPE_I2S_DATOUT, which is the I2S data output signal from CPU1 pin BC30 (LPE_I2S2_DATAOUT). The 1K series resistor allows GPIO_S5_10_UNLOCK to interface with this signal.

R179 - 220 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_LED_B	✅	Connected to SATA_LED_B net from CPU1 pin AY12 (active-low SATA LED output). Serves as current limiting resistor for SATA LED driver.
2	2	SATA_LED_R	✅	Connected to SATA_LED_R net, which connects to jumper J6. Provides connection to +V1P8S power rail when jumper is installed.

J6 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S power rail. Provides power source for SATA LED circuit when jumper is installed.
2	2	SATA_LED_R	✅	Connected to SATA_LED_R net, which connects through R179 to the CPU SATA LED output. Completes the SATA LED driver circuit when jumper is installed.

R72 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS6	✅	Pin 1 is connected to GND, providing a ground connection for the ICLK_SATA_TERMP net through this 0-ohm resistor.
2	2	GND	✅	Pin 2 is connected to ICLK_SATA_TERMP, which connects to CPU1 pin BB10 (RESERVED_VSS4). This grounds a reserved VSS pin on the processor.

R192 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS7	✅	Pin 1 is connected to RESERVED_VSS7, which connects to CPU1 pin BB7. This is one side of a 0-ohm resistor used to ground a reserved VSS pin.
2	2	GND	✅	Pin 2 is connected to GND, providing the ground connection for the RESERVED_VSS7 net through this 0-ohm resistor.

R220 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the pull-down resistor on SATA_GP0.
2	2	SATA_GP0	✅	Connected to SATA_GP0, providing a 10K ohm pull-down to ground for the SATA general purpose GPIO pin on the CPU.

R221 - 10K0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the pull-down resistor on SATA_GP1.
2	2	SATA_GP1	✅	Connected to SATA_GP1, providing a 10K ohm pull-down to ground for the SATA general purpose GPIO pin on the CPU.

R255 - 73.2 ohm 1% 1/4W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR_HOT_L	✅	Connected to VR_HOT_L net, which connects to CPU1 pin C24 (P̅R̅O̅C̅H̅O̅T̅). This is the processor hot signal from the Intel Atom E3825 SOC.
2	2	+V1P0S	✅	Connected to +V1P0S (1.0V supply rail), providing pull-up voltage for the PROCHOT signal. The 73.2 ohm value is lower than typical PROCHOT pull-ups but may be specified by Intel for this processor.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A9	ILB_RTC_X2	BRTCX2	✅	ILB_RTC_X2 (RTC crystal pin 2) connects to the 32.768kHz crystal with proper load capacitor and feedback resistor.
A17	GPIO_S5_3	mPCIE_WAKEB	✅	GPIO_S5_3 is connected to mPCIE_WAKEB for mini PCIe wake signaling with a DNI pull-up resistor.
A21	PCU_SPI_MOSI	SOC_SPI_MOSI	✅	PCU_SPI_MOSI (SPI master out slave in) connects through a 0 ohm series resistor to the SPI flash interface.
A25	SVID_DATA	SVID_DATA	✅	SVID_DATA (Serial VID data) connects through a 16.9 ohm series resistor to the voltage regulator interface for dynamic voltage control.
B7	PMC_CORE_PWROK	PMC_CORE_PWROK	✅	PMC_CORE_PWROK (core power OK signal) connects through a 0 ohm resistor to SYS_PWRGD with an optional DNI decoupling capacitor.
B8	ILB_RTC_EXTPAD	BVCCRTC_EXTPAD	✅	ILB_RTC_EXTPAD (RTC external pad for battery backup) has proper decoupling capacitor to ground.
B10	~PMC_RSMRST	PMC_RSMRST	✅	PMC_RSMRST# (resume reset, active low) has proper pull-up to +3VSB and pull-down to GND with filtering capacitor.
B18	GPIO_S5_0	SOC_GPIO_S5_0	✅	GPIO_S5 pins 0-2 are connected to platform-specific GPIO signals.
B16	GPIO_S5_1	SOC_GPIO_S5_1	✅	GPIO_S5 pins 0-2 are connected to platform-specific GPIO signals.
C18	GPIO_S5_2	SOC_GPIO_S5_2	✅	GPIO_S5 pins 0-2 are connected to platform-specific GPIO signals.
B22	PCU_SPI_MISO	SOC_SPI_MISO	✅	PCU_SPI_MISO (SPI master in slave out) connects through a 0 ohm series resistor to the SPI flash interface.
B24	~SVID_ALERT	SVID_ALERT	✅	SVID_ALERT# (Serial VID alert, active low) connects through a 20 ohm series resistor with a 69.8 ohm pull-up to +V1P0S for voltage regulator alert signaling.
C9	ILB_RTC_X1	BRTCX1	✅	ILB_RTC_X1 (RTC crystal pin 1) connects to the 32.768kHz crystal with proper load capacitor and feedback resistor.
C11	~ILB_RTC_TEST	ILB_RTC_TESTB	✅	ILB_RTC_TEST# (RTC test mode, active low) is left floating, which is acceptable per datasheet guidance.
C12	~ILB_RTC_RST	RTCRST_L	✅	ILB_RTC_RST (active low) has a proper pull-up resistor to +RTCVCC and decoupling capacitor, ensuring correct RTC reset operation.
C13	GPIO_S5_8	SOC_USB_HOST_EN0	✅	GPIO_S5 pins 8-9 are connected to USB host enable signals for USB port power control.
A13	GPIO_S5_9	SOC_USB_HOST_EN1	✅	GPIO_S5 pins 8-9 are connected to USB host enable signals for USB port power control.
C17	GPIO_S5_4	BOM_OP4	✅	GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration.
C16	GPIO_S5_5	BOM_OP1	✅	GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration.
B14	GPIO_S5_6	BOM_OP2	✅	GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration.
C15	GPIO_S5_7	BOM_OP3	✅	GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration.
C19	GPIO_S5_10	GPIO_S5_10_UNLOCK	✅	GPIO_S5_10 is connected to GPIO_S5_10_UNLOCK signal for platform-specific functionality.
C21	~PCU_SPI_CS_11	SOC_SPI_CS1B	✅	PCU_SPI_CS_11# (SPI chip select 1, active low) connects through a DNI 0 ohm resistor, indicating this chip select is not used.
C22	PCU_SPI_CLK	SOC_SPI_CLK	✅	PCU_SPI_CLK (SPI clock) connects through a 0 ohm series resistor to the SPI flash interface, with an optional DNI capacitor for filtering.
C23	~PCU_SPI_CS_00	SOC_SPI_CS0B	✅	PCU_SPI_CS_00# (SPI chip select 0, active low) connects through a 0 ohm series resistor to the SPI flash interface.
C25	SVID_CLK	SVID_CLK-R	✅	SVID_CLK (Serial VID clock) is connected to the voltage regulator interface for dynamic voltage control.
D14	TAP_TCK	XDP_H_TCK	✅	TAP_TCK (JTAG test clock) has a 51 ohm pull-down resistor to ground, which is appropriate for JTAG interface.
D18	~TAP_PRDY	XDP_H_PRDYB	✅	TAP_PRDY# (JTAG probe ready, active low) is connected to the debug header for JTAG communication.
D20	PMC_ACPRESENT	PMC_ACPRESENT	✅	PMC_ACPRESENT (AC power present indicator) has a 2.2K pull-up to +V1P8A.
D22	~PMC_SLP_S3	PMC_SLP_S3_L	✅	PMC_SLP_S3# (sleep S3 state indicator, active low) connects through a level shifter to translate from 1.8V to 3.3V domain.
D26	PMC_SUSPWRDNACK	SUSPWRDNACK	✅	PMC_SUSPWRDNACK (suspend power down acknowledge) has a 10K pull-up to +V1P8A and connects to a DNI test point.
F12	TAP_TDI	XDP_H_TDI	✅	TAP_TDI (JTAG test data in) has a 51 ohm pull-up resistor to +V1P8A, which is appropriate for JTAG interface.
F14	TAP_TMS	XDP_H_TMS	✅	TAP_TMS (JTAG test mode select) has a 51 ohm pull-up resistor to +V1P8A, which is appropriate for JTAG interface.
F16	~TAP_PREQ	XDP_H_PREQB	✅	TAP_PREQ# (JTAG probe request, active low) is connected to the debug header for JTAG communication.
F18	~PMC_SLP_S0IX	PMC_SLP_S0IX	✅	PMC_SLP_S0IX# (sleep S0ix state indicator, active low) connects to a DNI test point for monitoring.
F20	~PMC_PLTRST	PMC_PLTRST_R_V1P8	✅	PMC_PLTRST# (platform reset output, active low) connects through a level shifter to translate from 1.8V to 3.3V domain.
F22	~PMC_SLP_S4	PMC_SLP_S4_L	✅	PMC_SLP_S4# (sleep S4 state indicator, active low) connects through a level shifter to translate from 1.8V to 3.3V domain.
F26	~PMC_WAKE_PCIE_0	PMC_PCIE_WAKE_R	✅	PMC_WAKE_PCIE_0# (PCIe wake signal, active low) connects through a diode circuit with 1K pull-up for level translation from 3.3V to 1.8V.
G12	~TAP_TRST	XDP_H_TRSTB	✅	TAP_TRST# (JTAG test reset, active low) has a 51 ohm pull-down resistor to ground, which is appropriate for JTAG interface.
G16	TAP_TDO	XDP_H_TDO	✅	TAP_TDO (JTAG test data out) is connected to the debug header without termination, which is correct for an output signal.
G18	~PMC_SUS_STAT	LPCPD_L	✅	PMC_SUS_STAT# (suspend status, active low) connects to a DNI test point for monitoring.
G24	PMC_SUSCLK0_G24	PMC_SUSCLK0	✅	PMC_SUSCLK0 (suspend clock 0) connects through a level shifter to translate from 1.8V to 3.3V domain with a DNI pull-up.
J20	GPIO_S5_14	GPIO_S514_J20	✅	GPIO_S5_14 has a 10K pull-up to +V1P8A for platform-specific functionality.
J24	GPIO_S5_17	GPIO_S5_17	✅	GPIO_S5_17 connects to a jumper and has a 10K pull-up to +V1P8S for configuration purposes.
J26	~PMC_PWRBTN	PMC_PWRBTN	✅	PMC_PWRBTN# (power button input, active low) connects to a power button circuit with diode OR logic and has a DNI pull-up resistor.
K24	GPIO_S5_22	GPIO_D2_LED_CTRL	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
N24	GPIO_S5_23	XDP_H_OBSDATA_A0	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
M20	GPIO_S5_24	XDP_H_OBSDATA_A1	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
J18	GPIO_S5_25	XDP_H_OBSDATA_A2	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
M18	GPIO_S5_26	XDP_H_OBSDATA_A3	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
K18	GPIO_S5_27	EXP_GPIO1	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
K20	GPIO_S5_28	EXP_GPIO2	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
M22	GPIO_S5_29	EXP_GPIO3	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
M24	GPIO_S5_30	EXP_GPIO4	✅	GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO.
K26	~PMC_BATLOW	PMC_BATLOW	✅	PMC_BATLOW# (battery low indicator, active low) has a 20K pull-up to +V1P8A.
N26	GPIO_RCOMP	GPIO_RCOMP	✅	GPIO_RCOMP connects to a 49.9 ohm compensation resistor to ground, which matches the datasheet requirement for GPIO compensation.
BA28	SIO_SPI_MISO	SOC_SIO_SPI_MISO	✅	SIO_SPI_MISO (SIO SPI master in slave out) is connected to the Serial I/O SPI interface.
BA34	~SIO_UART1_RTS	SIO_UART1_RTSB	✅	SIO_UART1_RTS# (UART1 request to send, active low) is connected to the UART1 interface for hardware flow control.
AD9	RESERVED_AD9		✅	Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins.
AD10	RESERVED_AD10		✅	Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins.
AD12	RESERVED_AD12		✅	Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins.
AT34	RESERVED		✅	Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins.
AM10	RESERVED_AM10		✅	Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins.
AM9	RESERVED_AM9		✅	Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins.
AD13	ICLK_RCOMP	ICLK_RCOMP	✅	ICLK_RCOMP connects to a 47.5 ohm compensation resistor to ground, which matches the datasheet requirement for integrated clock compensation.
AD14	ICLK_ICOMP	ICLK_ICOMP	✅	ICLK_ICOMP connects to a 4.02K compensation resistor to ground, which matches the datasheet requirement for integrated clock compensation.
BD34	SIO_UART2_TXD	SIO_UART2_TXD	✅	SIO_UART2_TXD (UART2 transmit data) is connected to the UART2 interface.
AF6	PCIE_CLKN_00		✅	PCIE_CLKN_00 and PCIE_CLKP_00 are unconnected, indicating PCIe port 0 is not used in this design.
AF4	PCIE_CLKP_00		✅	PCIE_CLKN_00 and PCIE_CLKP_00 are unconnected, indicating PCIe port 0 is not used in this design.
AF9	PCIE_CLKN_11		✅	PCIE_CLKN_11 and PCIE_CLKP_11 are unconnected, indicating PCIe port 1 is not used in this design.
AF7	PCIE_CLKP_11		✅	PCIE_CLKN_11 and PCIE_CLKP_11 are unconnected, indicating PCIe port 1 is not used in this design.
BF32	~SIO_UART2_CTS		✅	SIO_UART2_CTS# and SIO_UART2_RTS# (UART2 flow control, active low) are unconnected, indicating hardware flow control is not used for UART2.
BD32	~SIO_UART2_RTS		✅	SIO_UART2_CTS# and SIO_UART2_RTS# (UART2 flow control, active low) are unconnected, indicating hardware flow control is not used for UART2.
BF34	SIO_UART2_RXD	SIO_UART2_RXD	✅	SIO_UART2_RXD (UART2 receive data) is connected to the UART2 interface.
BG9	~PMC_RSTBTN	PMC_RSTBTN	✅	PMC_RSTBTN# (reset button input, active low) is connected to the platform reset button circuit.
AH10	ICLK_OSCOUT	XTAL25_OUT	✅	ICLK_OSCOUT connects to the output of the 25MHz crystal oscillator with 27pF load capacitors. The load capacitance is slightly higher than the 18pF specified in the datasheet but should be acceptable with PCB stray capacitance.
AH12	ICLK_OSCIN	XTAL25_IN	✅	ICLK_OSCIN connects to the input of the 25MHz crystal oscillator with proper load capacitors and feedback resistor.
BH7	PMC_PLT_CLK_00		✅	Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design.
BH4	PMC_PLT_CLK_22		✅	Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design.
BH5	PMC_PLT_CLK_11		✅	Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design.
BH6	PMC_PLT_CLK_44		✅	Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design.
BJ9	PMC_PLT_CLK_55		✅	Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design.
BH8	PMC_PLT_CLK_33	I2S_MCLK	✅	PMC_PLT_CLK_33 is connected to I2S_MCLK, providing a 25MHz master clock for I2S audio interface.
AK4	PCIE_CLKN_22	PCIE_CLK-N2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 provide differential PCIe reference clock for port 2.
AK6	PCIE_CLKP_22	PCIE_CLK-P2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 provide differential PCIe reference clock for port 2.
AM4	PCIE_CLKN_33	mPCIE_REFCLK_N	✅	PCIE_CLKN_33 and PCIE_CLKP_33 provide differential PCIe reference clock for port 3, used for mini PCIe interface.
AM6	PCIE_CLKP_33	mPCIE_REFCLK_P	✅	PCIE_CLKN_33 and PCIE_CLKP_33 provide differential PCIe reference clock for port 3, used for mini PCIe interface.
AT32	SIO_PWM_11	SOC_PWM1	✅	SIO_PWM_11 (PWM output 1) is connected to the PWM interface.
AU32	SIO_PWM_00	SOC_PWM0	✅	SIO_PWM_00 (PWM output 0) is connected to the PWM interface.
AU34	SIO_UART1_RXD	SIO_UART1_RXD	✅	SIO_UART1_RXD (UART1 receive data) is connected to the UART1 interface.
AV32	~SIO_SPI_CS	SOC_SIO_SPI_CS1	✅	SIO_SPI_CS# (SIO SPI chip select, active low) is connected to the Serial I/O SPI interface.
AV34	SIO_UART1_TXD	SIO_UART1_TXD	✅	SIO_UART1_TXD (UART1 transmit data) is connected to the UART1 interface.
AY28	SIO_SPI_MOSI	SOC_SIO_SPI_MOSI	✅	SIO_SPI_MOSI (SIO SPI master out slave in) is connected to the Serial I/O SPI interface.
AY30	SIO_SPI_CLK	SOC_SIO_SPI_CLK	✅	SIO_SPI_CLK (SIO SPI clock) is connected to the Serial I/O SPI interface.
AY34	~SIO_UART1_CTS	SIO_UART1_CTSB	✅	SIO_UART1_CTS# (UART1 clear to send, active low) is connected to the UART1 interface for hardware flow control.

U19 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the 1.8V supply for the A-side of the level shifter.
2	A1	PMC_PLTRST_R_V1P8	✅	A1 is correctly connected to PMC_PLTRST_R_V1P8, the 1.8V side of the platform reset signal from the CPU.
3	A2	PMC_SUSCLK0	✅	A2 is correctly connected to PMC_SUSCLK0, the 1.8V side of the suspend clock signal from the CPU.
4	A3	PMC_SLP_S4_L	✅	A3 is correctly connected to PMC_SLP_S4_L, the 1.8V side of the S4 sleep state signal from the CPU.
5	A4	PMC_SLP_S3_L	✅	A4 is correctly connected to PMC_SLP_S3_L, the 1.8V side of the S3 sleep state signal from the CPU.
6	GND	GND	✅	GND is correctly connected to the ground plane.
7	B4	SLP_S3_L	✅	B4 is correctly connected to SLP_S3_L, the 3.3V side of the S3 sleep state signal.
8	B3	SLP_S4_L	✅	B3 is correctly connected to SLP_S4_L, the 3.3V side of the S4 sleep state signal.
9	B2	SUSCLK_3P3	✅	B2 is correctly connected to SUSCLK_3P3, the 3.3V side of the suspend clock signal.
10	B1	PMC_PLTRST_L	✅	B1 is correctly connected to PMC_PLTRST_L, the 3.3V side of the platform reset signal.
11	VCCB	PWR_BUF1	✅	VCCB is correctly connected to PWR_BUF1, which is derived from +3VSB through R26 (0 ohm), providing the 3.3V supply for the B-side.
12	OE	PMC_OE	✅	OE is correctly connected to PMC_OE with a pull-up resistor R57 (2.2K) to +V1P8A, enabling the level shifter by default.

Y1 - 32.768KHz, ABRACON ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BRTCX2	✅	Crystal pin 1 connected to BRTCX2, which connects to CPU RTC oscillator output pin ILB_RTC_X2. Includes 18pF load capacitor C42 to ground and 10M feedback resistor R76 to pin 2.
2	2	BRTCX1	✅	Crystal pin 2 connected to BRTCX1, which connects to CPU RTC oscillator input pin ILB_RTC_X1. Includes 18pF load capacitor C43 to ground and 10M feedback resistor R76 to pin 1.

BH1 - BATTERY HOLDER VERT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+VBAT	✅	Both positive terminals of the battery holder connected together to +VBAT net. This net connects through R278 (1K current limiting resistor) to the battery backup OR-ing circuit.
2	P2	+VBAT	✅	Both positive terminals of the battery holder connected together to +VBAT net. This net connects through R278 (1K current limiting resistor) to the battery backup OR-ing circuit.
3	N	GND	✅	Negative terminal of battery holder correctly connected to GND.

Y2 - 25.00MHz crystal ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XTAL25_IN	✅	Crystal pin connected to CPU main oscillator input with appropriate load capacitor.
2	2	GND	✅	Ground pins connected to system ground.
4	4	GND	✅	Ground pins connected to system ground.
3	3	XTAL25_OUT	✅	Crystal pin connected to CPU main oscillator output with appropriate load capacitor.

D3 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PCIE_WAKE	✅	Both anode pins are connected to PMC_PCIE_WAKE net, which is pulled to +3VSB (3.3V) through R27 (2.2K). This parallel connection is intentional for the BAT54A-S dual Schottky diode configuration.
2	2	PMC_PCIE_WAKE	✅	Both anode pins are connected to PMC_PCIE_WAKE net, which is pulled to +3VSB (3.3V) through R27 (2.2K). This parallel connection is intentional for the BAT54A-S dual Schottky diode configuration.
3	3	PMC_PCIE_WAKE_R	✅	Cathode pin connected to PMC_PCIE_WAKE_R net, which connects to CPU pin F26 (PMC_WAKE_PCIE_0) and is pulled to +V1P8A (1.8V) through R253 (1K). This provides the output of the wake signal circuit to the CPU.

D5 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	+PS_3VSB	✅	Anode pin connected to +PS_3VSB (3.3V standby power), serving as the primary power source for the RTC backup circuit.
A2	A2	+VBAT_R	✅	Anode pin connected to +VBAT_R (battery voltage through R278 1K resistor), serving as the backup power source for the RTC when primary power is unavailable.
C	C	+RTCVCC	✅	Common cathode pin connected to +RTCVCC, which powers the RTC circuit. The OR-ing diode configuration automatically selects the higher voltage source between +PS_3VSB and +VBAT_R.

D10 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	3VSB_OK	✅	Anode pin connected to 3VSB_OK signal, which is pulled to +3VSB (3.3V) through R162 (1K). This serves as one input to the power button OR-ing circuit.
A2	A2	PMC_PWRBTN	✅	Anode pin connected to PMC_PWRBTN signal from CPU1 pin J26 (active-low power button input). R161 (20K pull-up to +V1P8A) is marked DNI, so the pin relies on CPU internal pull-up.
C	C	PS_OUT_L	✅	Common cathode pin connected to PS_OUT_L output signal. The OR-ing diode configuration combines 3VSB_OK and PMC_PWRBTN signals for power control logic.

R183 - 10K pull-up ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pin 1 connects to +V1P8S (1.8V standby rail), providing the pull-up voltage source for GPIO_S5_17.
2	2	GPIO_S5_17	✅	Pin 2 connects to GPIO_S5_17, which goes to CPU1 pin J24 and J7 pin 1. This provides the pull-up function for the GPIO signal.

J7 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_17	✅	Pin 1 connects to GPIO_S5_17, which is pulled high to +V1P8S through R183 (10K) and connects to CPU1 pin J24. This forms the signal side of a jumper configuration.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the jumper. When a jumper is installed, it pulls GPIO_S5_17 to ground.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A7	USB_HSIC_RCOMP	USB_HSIC0_RCOMP	✅	USB_HSIC_RCOMP is correctly connected to ground through a 45.3 ohm resistor for USB HSIC impedance calibration.
B4	USB_HSIC0_DATA		✅	USB_HSIC0_DATA is left unconnected, which is acceptable if USB HSIC port 0 is not used in this design.
B5	USB_HSIC0_STROBE		✅	USB_HSIC0_STROBE is left unconnected, which is acceptable if USB HSIC port 0 is not used in this design.
B12	GPIO_S5_43		✅	GPIO_S5_43 (USB_ULPI_REFCLK) is left unconnected, which is acceptable if USB ULPI is not used in this design.
B20	~USB_OC_11	SOC_USB_HOST_OC1	✅	USB_OC[1]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection on port 1.
C7	USB_RCOMPI	USB_RCOMP	✅	USB_RCOMPI is correctly connected to the same net as USB_RCOMPO with a 45.3 ohm resistor to ground for USB impedance calibration.
C20	~USB_OC_00	SOC_USB_HOST_OC0	✅	USB_OC[0]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection on port 0.
D2	USB_HSIC1_STROBE		✅	USB_HSIC1_STROBE is left unconnected, which is acceptable if USB HSIC port 1 is not used in this design.
D4	USB3_RXP0	USB3_RXP0	✅	USB3_RXP0 is correctly connected as part of the USB 3.0 differential receive pair for port 0.
D6	USB_RCOMPO	USB_RCOMP	✅	USB_RCOMPO is correctly connected to the same net as USB_RCOMPI with a 45.3 ohm resistor to ground for USB impedance calibration.
D10	ICLK_USB_TERM_1	ICLK_USB_TERM_0	✅	ICLK_USB_TERM_1 is correctly connected to ground through a 1K resistor for USB termination.
E2	USB_HSIC1_DATA		✅	USB_HSIC1_DATA is left unconnected, which is acceptable if USB HSIC port 1 is not used in this design.
E3	USB3_RXN0	USB3_RXN0	✅	USB3_RXN0 is correctly connected as part of the USB 3.0 differential receive pair for port 0.
F10	ICLK_USB_TERMN	ICLK_USB_TERM_1	✅	ICLK_USB_TERMN is correctly connected to ground through a 1K resistor for USB termination.
G2	GPIO_S5_31		✅	GPIO_S5_31 is left unconnected, which is acceptable if this GPIO is not needed in the design.
G14	USB_DN1	USB_DN1	✅	USB_DN1 is correctly connected as part of the USB 2.0 differential data pair for port 1.
H3	GPIO_S5_42		✅	GPIO_S5_42 is left unconnected, which is acceptable if this GPIO is not needed in the design.
H4	RESERVED_H4		✅	RESERVED_H4 is correctly left unconnected as it is a reserved pin.
H5	RESERVED_H5		✅	RESERVED_H5 is correctly left unconnected as it is a reserved pin.
H7	RESERVED_H7		✅	RESERVED_H7 is correctly left unconnected as it is a reserved pin.
H8	RESERVED_H8		✅	RESERVED_H8 is correctly left unconnected as it is a reserved pin.
H10	USB_DN3		✅	USB_DN3 is left unconnected, which is acceptable if USB port 3 is not used in this design.
J3	GPIO_S5_40		✅	GPIO_S5_40 is left unconnected, which is acceptable if this GPIO is not needed in the design.
J12	USB_DN2	USB_HOST_DN	✅	USB_DN2 is correctly connected as part of the USB 2.0 differential data pair for port 2.
J14	USB_DP1	USB_DP1	✅	USB_DP1 is correctly connected as part of the USB 2.0 differential data pair for port 1.
K2	GPIO_S5_34		✅	GPIO_S5_34 is left unconnected, which is acceptable if this GPIO is not needed in the design.
K3	GPIO_S5_35		✅	GPIO_S5_35 is left unconnected, which is acceptable if this GPIO is not needed in the design.
K6	USB3_TXP0	USB3_TXP0	✅	USB3_TXP0 is correctly connected as part of the USB 3.0 differential transmit pair for port 0.
K7	USB3_TXN0	USB3_TXN0	✅	USB3_TXN0 is correctly connected as part of the USB 3.0 differential transmit pair for port 0.
K10	USB_DP3		✅	USB_DP3 is left unconnected, which is acceptable if USB port 3 is not used in this design.
K12	USB_DP2	USB_HOST_DP	✅	USB_DP2 is correctly connected as part of the USB 2.0 differential data pair for port 2.
K16	USB_DN0	USB_DN0	✅	USB_DN0 is correctly connected as part of the USB 2.0 differential data pair for port 0.
L1	GPIO_S5_33		✅	GPIO_S5_33 is left unconnected, which is acceptable if this GPIO is not needed in the design.
L3	GPIO_S5_39		✅	GPIO_S5_39 is left unconnected, which is acceptable if this GPIO is not needed in the design.
M2	GPIO_S5_36		✅	GPIO_S5_36 is left unconnected, which is acceptable if this GPIO is not needed in the design.
M3	GPIO_S5_32		✅	GPIO_S5_32 is left unconnected, which is acceptable if this GPIO is not needed in the design.
M4	RESERVED_M4		✅	RESERVED_M4 is correctly left unconnected as it is a reserved pin.
M6	RESERVED_M6		✅	RESERVED_M6 is correctly left unconnected as it is a reserved pin.
M7	RESERVED_M7		✅	RESERVED_M7 is correctly left unconnected as it is a reserved pin.
M9	RESERVED_M9		✅	RESERVED_M9 is correctly left unconnected as it is a reserved pin.
M10	RESERVED_M10		✅	RESERVED_M10 is correctly left unconnected as it is a reserved pin.
M12	USB3_REXT0	USB3_REXT0	✅	USB3_REXT0 is correctly connected to ground through a 1.24K resistor for USB 3.0 impedance calibration.
M13	USB_PLL_MON	USB_PLL_MON	✅	USB_PLL_MON is correctly connected to a test point for USB PLL monitoring.
M16	USB_DP0	USB_DP0	✅	USB_DP0 is correctly connected as part of the USB 2.0 differential data pair for port 0.
N3	GPIO_S5_37		✅	GPIO_S5_37 is left unconnected, which is acceptable if this GPIO is not needed in the design.
P2	GPIO_S5_38		✅	GPIO_S5_38 is left unconnected, which is acceptable if this GPIO is not needed in the design.
P3	GPIO_S5_41		✅	GPIO_S5_41 is left unconnected, which is acceptable if this GPIO is not needed in the design.
P6	RESERVED_P6		✅	RESERVED_P6 is correctly left unconnected as it is a reserved pin.
P7	RESERVED_P7		✅	RESERVED_P7 is correctly left unconnected as it is a reserved pin.
P10	RESERVED_P10		✅	RESERVED_P10 is correctly left unconnected as it is a reserved pin.
P12	RESERVED_P12		✅	RESERVED_P12 is correctly left unconnected as it is a reserved pin.
BC12	GPIO_S0_SC_56	GPIO_S0_SC_56	✅	GPIO_S0_SC_56 is left unconnected, which is acceptable if this GPIO is not needed in the design.
BC14	GPIO_S0_SC_58	HDMI_CEC	✅	GPIO_S0_SC_58 is configured for HDMI_CEC but left floating, which is acceptable if HDMI CEC is not used.
BC16	GPIO_S0_SC_61	PCU_UART3_RXD	✅	GPIO_S0_SC_61 is correctly configured as PCU_UART3_RXD and connected through level shifter U6 to the debug UART connector J4.
BD12	GPIO_S0_SC_55	GPIO_S0_SC_55	✅	GPIO_S0_SC_55 is connected to a test point (DNI) for monitoring purposes.
BD14	GPIO_S0_SC_57	PCU_UART3_TXD	✅	GPIO_S0_SC_57 is correctly configured as PCU_UART3_TXD and connected through level shifter U6 to the debug UART connector J4.
BD16	GPIO_S0_SC_60		✅	GPIO_S0_SC_60 is left unconnected, which is acceptable if this GPIO is not needed in the design.
BF14	GPIO_S0_SC_59		✅	GPIO_S0_SC_59 is left unconnected, which is acceptable if this GPIO is not needed in the design.
BF18	LPC_RCOMP	LPC_RCOMP	✅	LPC_RCOMP is correctly connected to ground through a 49.9 ohm resistor for LPC bus impedance calibration.
BF27	SIO_I2C4_DATA		✅	SIO_I2C4_DATA is left unconnected, which is acceptable if I2C port 4 is not used in this design.
BG11	~PCU_SMB_ALERT	PCU_SMB_ALERT	✅	PCU_SMB_ALERT# is correctly connected with a 10K pull-up resistor to +V1P8S and routed through a 0 ohm jumper to LAN-SMB-ALERT#.
BG12	PCU_SMB_DATA	PCU_SMB_DATA	✅	PCU_SMB_DATA is correctly connected with a 2.2K pull-up resistor and routed through level shifter U5 to DDR_SMB_DATA.
BG13	ILB_LPC_SERIRQ		✅	ILB_LPC_SERIRQ is left unconnected, which is acceptable if the LPC interface is not used in this design.
BG14	ILB_LPC_AD_33		✅	ILB_LPC_AD_33 is left unconnected, which is acceptable if the LPC interface is not used in this design.
BG15	ILB_LPC_CLK_00		✅	ILB_LPC_CLK_00 is left unconnected, which is acceptable if the LPC interface is not used in this design.
BG16	~ILB_LPC_CLKRUN		✅	ILB_LPC_CLKRUN# is left unconnected, which is acceptable if the LPC interface is not used in this design.
BG17	~ILB_LPC_FRAME		✅	ILB_LPC_FRAME# is left unconnected, which is acceptable if the LPC interface is not used in this design.
BG23	SIO_I2C0_CLK		✅	SIO_I2C0_CLK is left unconnected, which is acceptable if I2C port 0 is not used in this design.
BG24	SIO_I2C1_DATA	SIO_I2C1_SDA	✅	SIO_I2C1_DATA is correctly connected to SIO_I2C1_SDA with a test point for monitoring.
BG25	SIO_I2C2_DATA		✅	SIO_I2C2_DATA is left unconnected, which is acceptable if I2C port 2 is not used in this design.
BG26	SIO_I2C3_DATA		✅	SIO_I2C3_DATA is left unconnected, which is acceptable if I2C port 3 is not used in this design.
BG27	SIO_I2C4_CLK		✅	SIO_I2C4_CLK is left unconnected, which is acceptable if I2C port 4 is not used in this design.
BG28	SIO_I2C5_CLK	SI0_I2C5_SCL	✅	SIO_I2C5_CLK is correctly connected through a 22 ohm series resistor to I2C5_SCL for signal integrity.
BG29	SIO_I2C6_CLK	SI0_I2C6_SCL	✅	SIO_I2C6_CLK is correctly connected through a 22 ohm series resistor to I2C6_SCL for signal integrity.
BG30	GPIO_S0_SC_093	TP10_NET	✅	GPIO_S0_SC_093 is intentionally grounded through a 0 ohm resistor as indicated by the schematic note.
BH10	PCU_SMB_CLK	PCU_SMB_CLK	✅	PCU_SMB_CLK is correctly connected with a 2.2K pull-up resistor and routed through level shifter U5 to DDR_SMB_CLK.
BH12	ILB_8254_SPKR	ILB_8254_SPKR	✅	ILB_8254_SPKR is left floating, which is acceptable if the PC speaker output is not used in this design.
BH14	ILB_LPC_CLK_11		✅	ILB_LPC_CLK_11 is left unconnected, which is acceptable if the LPC interface is not used in this design.
BH16	ILB_LPC_AD_00		✅	ILB_LPC_AD_00 is left unconnected, which is acceptable if the LPC interface is not used in this design.
BH22	SIO_I2C0_DATA		✅	SIO_I2C0_DATA is left unconnected, which is acceptable if I2C port 0 is not used in this design.
BH24	SIO_I2C1_CLK	SIO_I2C1_SCL	✅	SIO_I2C1_CLK is correctly connected to SIO_I2C1_SCL with a test point for monitoring.
BH26	SIO_I2C3_CLK		✅	SIO_I2C3_CLK is left unconnected, which is acceptable if I2C port 3 is not used in this design.
BH28	SIO_I2C5_DATA	SI0_I2C5_SDA	✅	SIO_I2C5_DATA is correctly connected through a 22 ohm series resistor to I2C5_SDA for signal integrity.
BH30	GPIO_S0_SC_092	TP9_NET	✅	GPIO_S0_SC_092 is intentionally grounded through a 0 ohm resistor as indicated by the schematic note.
BJ13	ILB_LPC_AD_22		✅	ILB_LPC_AD_22 is left unconnected, which is acceptable if the LPC interface is not used in this design.
BJ17	ILB_LPC_AD_11		✅	ILB_LPC_AD_11 is left unconnected, which is acceptable if the LPC interface is not used in this design.
BJ25	SIO_I2C2_CLK		✅	SIO_I2C2_CLK is left unconnected, which is acceptable if I2C port 2 is not used in this design.
BJ29	SIO_I2C6_DATA	SI0_I2C6_SDA	✅	SIO_I2C6_DATA is correctly connected through a 22 ohm series resistor to I2C6_SDA for signal integrity.

U5 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DDR_SMB_CLK	✅	B2 pin correctly connected to DDR_SMB_CLK on the 3.3V side of the level translator.
2	GND	GND	✅	GND pin correctly connected to ground.
3	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S for the low voltage side supply.
4	A2	PCU_SMB_CLK	✅	A2 pin correctly connected to PCU_SMB_CLK on the 1.8V side of the level translator.
5	A1	PCU_SMB_DATA	✅	A1 pin correctly connected to PCU_SMB_DATA on the 1.8V side of the level translator.
6	OE	PCU_SMB_BUFF_ENB	✅	OE pin correctly connected to PCU_SMB_BUFF_ENB with pull-up to enable the translator.
7	VCCB	BUF2_PWR	✅	VCCB pin correctly connected to BUF2_PWR for the high voltage side supply.
8	B1	DDR_SMB_DATA	✅	B1 pin correctly connected to DDR_SMB_DATA on the 3.3V side of the level translator.

R52 - 2.2K ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LSENB	✅	Pull-up resistor correctly configured to enable U6 level shifter by default while allowing external control.
2	2	+V1P8S	✅	Pull-up resistor correctly configured to enable U6 level shifter by default while allowing external control.

R51 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BUF3_PWR	✅	Zero-ohm jumper correctly connects BUF3_PWR to +3VSB, providing the B-side voltage supply for U6 with design flexibility.
2	2	+3VSB	✅	Zero-ohm jumper correctly connects BUF3_PWR to +3VSB, providing the B-side voltage supply for U6 with design flexibility.

U6 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DBG_UART3_TXD	✅	B2 pin correctly connected to DBG_UART3_TXD, which routes the CPU's transmit data to the debug connector after level shifting from 1.8V to 3.3V.
2	GND	GND	✅	GND pin correctly connected to ground plane.
3	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V) supply with appropriate decoupling.
4	A2	PCU_UART3_TXD	✅	A2 pin correctly connected to PCU_UART3_TXD from the CPU, forming the A-side of the UART transmit channel.
5	A1	PCU_UART3_RXD	✅	A1 pin correctly connected to PCU_UART3_RXD from the CPU, forming the A-side of the UART receive channel.
6	OE	LSENB	✅	OE pin correctly connected to LSENB with a 2.2K pull-up to +V1P8S, enabling the device by default while allowing external control.
7	VCCB	BUF3_PWR	✅	VCCB pin correctly connected to BUF3_PWR (+3VSB via R51) with appropriate decoupling.
8	B1	DBG_UART3_RXD	✅	B1 pin correctly connected to DBG_UART3_RXD, which receives data from the debug connector after level shifting from 3.3V to 1.8V.

J4 - SIP6_RA ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net.
2	2		✅	Pin 2 is not connected, likely intended for CTS (Clear To Send) which is not used in this design.
3	3		✅	Pin 3 is unconnected but should be connected to +3VSB to provide 3.3V power for maximum compatibility with standard USB-to-TTL serial cables.
4	4	DBG_UART3_RXD	✅	UART receive pin correctly connected through level shifter U6 with 100K pull-down resistor R50.
5	5	DBG_UART3_TXD_R	✅	UART transmit pin correctly connected through 330 ohm series resistor R819 and level shifter U6.
6	6		✅	Pin 6 is not connected, likely intended for RTS (Request To Send) which is not used in this design.

R819 - 330 ohm series on UART3_TXD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DBG_UART3_TXD	✅	Connected to DBG_UART3_TXD from level shifter U6 output (pin 1, B2).
2	2	DBG_UART3_TXD_R	✅	Connected to DBG_UART3_TXD_R going to connector J4 pin 5 for transmission to the serial cable.

R50 - 100K pull-down on DBG_UART3_RXD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND to provide the ground reference for the pull-down function.
2	2	DBG_UART3_RXD	✅	Connected to DBG_UART3_RXD to pull the receive line low when no cable is connected, preventing floating input conditions.

R186 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for USB clock termination resistor. Correctly connected to GND.
2	2	ICLK_USB_TERM_1	✅	Connected to ICLK_USB_TERM_1 net which connects to CPU1 pin F10 (ICLK_USB_TERMN). There is a naming discrepancy between the CPU pin name (ICLK_USB_TERMN) and the net name (ICLK_USB_TERM_1).

R187 - RES_1Kohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground connection for USB clock termination resistor. Correctly connected to GND.
2	2	ICLK_USB_TERM_0	✅	Connected to ICLK_USB_TERM_0 net which connects to CPU1 pin D10 (ICLK_USB_TERM_1). There is a naming discrepancy between the CPU pin name (ICLK_USB_TERM_1) and the net name (ICLK_USB_TERM_0).

R11 - 22 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SDA	✅	Series resistor on I2C6 SDA line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity.
2	2	I2C6_SDA	✅	External side of series resistor on I2C6 SDA line, connected to the I2C bus that routes off-page.

R12 - 22 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C6_SCL	✅	Series resistor on I2C6 SCL line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity.
2	2	I2C6_SCL	✅	External side of series resistor on I2C6 SCL line, connected to the I2C bus that routes off-page.

R269 - 22 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SDA	✅	Series resistor on I2C5 SDA line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity.
2	2	I2C5_SDA	✅	External side of series resistor on I2C5 SDA line, connected to the I2C bus that routes off-page.

R270 - 22 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SI0_I2C5_SCL	✅	Series resistor on I2C5 SCL line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity.
2	2	I2C5_SCL	✅	External side of series resistor on I2C5 SCL line, connected to the I2C bus that routes off-page.

R75 - 10K pull-up on PCU_SMB_ALERT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S supply to provide pull-up voltage for the SMBus alert signal.
2	2	PCU_SMB_ALERT	✅	Connected to PCU_SMB_ALERT signal, providing a 10K pull-up for the active-low SMBus alert signal from the CPU.

R842 - 0 ohm jumper for SMB alert routing ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-SMB-ALERT#	✅	Connected to LAN-SMB-ALERT# net, allowing optional connection of LAN SMBus alert to CPU SMBus alert.
2	2	PCU_SMB_ALERT	✅	Connected to PCU_SMB_ALERT net, allowing the CPU's SMBus alert to be optionally connected to the LAN SMBus alert.

R841 - 0 ohm jumper DDR_SMB_CLK to LAN-SMB-CLK ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_CLK	✅	0 ohm jumper connecting DDR_SMB_CLK to LAN-SMB-CLK, allowing the SMBus clock line from the level shifter U5 to be shared with a LAN SMBus interface.
2	2	LAN-SMB-CLK	✅	0 ohm jumper connecting DDR_SMB_CLK to LAN-SMB-CLK, allowing the SMBus clock line from the level shifter U5 to be shared with a LAN SMBus interface.

R840 - 0 ohm jumper DDR_SMB_DATA to LAN-SMB-DATA ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_DATA	✅	0 ohm jumper connecting DDR_SMB_DATA to LAN-SMB-DATA, allowing the SMBus data line from the level shifter U5 to be shared with a LAN SMBus interface.
2	2	LAN-SMB-DATA	✅	0 ohm jumper connecting DDR_SMB_DATA to LAN-SMB-DATA, allowing the SMBus data line from the level shifter U5 to be shared with a LAN SMBus interface.

R97 - 10K pull-up on SOC_USB_HOST_OC1 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A power rail to provide pull-up voltage for the USB overcurrent detection signal.
2	2	SOC_USB_HOST_OC1	✅	Connected to SOC_USB_HOST_OC1, an active-low USB overcurrent detection signal from the CPU.

R84 - 10K pull-up on SOC_USB_HOST_OC0 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A power rail to provide pull-up voltage for the USB overcurrent detection signal.
2	2	SOC_USB_HOST_OC0	✅	Connected to SOC_USB_HOST_OC0, an active-low USB overcurrent detection signal from the CPU.

R243 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TP9_NET	✅	0 ohm resistor connecting GPIO_S0_SC_092 (via TP9_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes.
2	2	GND	✅	0 ohm resistor connecting GPIO_S0_SC_092 (via TP9_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes.

R261 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TP10_NET	✅	0 ohm resistor connecting GPIO_S0_SC_093 (via TP10_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes.
2	2	GND	✅	0 ohm resistor connecting GPIO_S0_SC_093 (via TP10_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes.

CPU1 - INTEL_ATOM_E3825_SOC ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A48	DRAM_VDD_S4	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AK38	DRAM_VDD_S4_AK38	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AM38	DRAM_VDD_S4_AM38	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AV41	DRAM_VDD_S4_AV41	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
AV42	DRAM_VDD_S4_AV42	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BB46	DRAM_VDD_S4_BB46	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BD49	DRAM_VDD_S4_BD49	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BD52	DRAM_VDD_S4_BD52	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BD53	DRAM_VDD_S4_BD53	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BF44	DRAM_VDD_S4_BF44	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BG51	DRAM_VDD_S4_BG51	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
BJ48	DRAM_VDD_S4_BJ48	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
C51	DRAM_VDD_S4_C51	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
D44	DRAM_VDD_S4_D44	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
F49	DRAM_VDD_S4_F49	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
F52	DRAM_VDD_S4_F52	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
F53	DRAM_VDD_S4_F53	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
H46	DRAM_VDD_S4_H46	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
M41	DRAM_VDD_S4_M41	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
M42	DRAM_VDD_S4_M42	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
V38	DRAM_VDD_S4_V38	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
Y38	DRAM_VDD_S4_Y38	+VDIMM	✅	DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface.
N28	CORE_VSS_SENSE_N28	VSS_SENSE	✅	Core ground sense pin connected to VSS_SENSE net. This pin provides ground reference feedback for the VCC voltage regulator.
P28	CORE_VCC_SENSE_P28	VCC_SENSE	✅	Core voltage sense pin connected to VCC_SENSE net. This pin provides voltage feedback for the VCC voltage regulator.
AA22	TP2_CORE_VCC_S0IX	$9N615	✅	Core voltage test point connection. This pin is connected to internal net $9N615 which connects to test point TP2 (marked DNI).
AA24	UNCORE_VNN_S3_AA24	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AC22	UNCORE_VNN_S3_AC22	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AC24	UNCORE_VNN_S3_AC24	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AD22	UNCORE_VNN_S3_AD22	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AD24	UNCORE_VNN_S3_AD24	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AF22	UNCORE_VNN_S3_AF22	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AF24	UNCORE_VNN_S3_AF24	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AG22	UNCORE_VNN_S3_AG22	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AG24	UNCORE_VNN_S3_AG24	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AJ22	UNCORE_VNN_S3_AJ22	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AJ24	UNCORE_VNN_S3_AJ24	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AK22	UNCORE_VNN_S3_AK22	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AK24	UNCORE_VNN_S3_AK24	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AK25	UNCORE_VNN_S3_AK25	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AK27	UNCORE_VNN_S3_AK27	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AK29	UNCORE_VNN_S3_AK29	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AK30	UNCORE_VNN_S3_AK30	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AK32	UNCORE_VNN_S3_AK32	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AM22	UNCORE_VNN_S3_AM22	+VGFX	✅	Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic.
AA27	CORE_VCC_S0IX_AA27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AA29	CORE_VCC_S0IX_AA29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AA30	CORE_VCC_S0IX_AA30	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AC27	CORE_VCC_S0IX_AC27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AC29	CORE_VCC_S0IX_AC29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AC30	CORE_VCC_S0IX_AC30	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AD27	CORE_VCC_S0IX_AD27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AD29	CORE_VCC_S0IX_AD29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AD30	CORE_VCC_S0IX_AD30	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AF27	CORE_VCC_S0IX_AF27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AF29	CORE_VCC_S0IX_AF29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AG27	CORE_VCC_S0IX_AG27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AG29	CORE_VCC_S0IX_AG29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
AG30	CORE_VCC_S0IX_AG30	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
P26	CORE_VCC_S0IX_P26	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
P27	CORE_VCC_S0IX_P27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
U27	CORE_VCC_S0IX_U27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
U29	CORE_VCC_S0IX_U29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
V27	CORE_VCC_S0IX_V27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
V29	CORE_VCC_S0IX_V29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
V30	CORE_VCC_S0IX_V30	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
Y27	CORE_VCC_S0IX_Y27	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
Y29	CORE_VCC_S0IX_Y29	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
Y30	CORE_VCC_S0IX_Y30	+VCORE	✅	Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores.
BB8	UNCORE_VNN_SENSE	VCCGT_SENSE	✅	Uncore voltage sense pin connected to VCCGT_SENSE net. This pin provides voltage feedback for the VNN voltage regulator.
AD38	DRAM_VDD_S4_AD38	DRAM_VDD_CLK	✅	DDR3L memory power supply pins connected to DRAM_VDD_CLK rail, which connects to +VDIMM through 0-ohm resistor R275. This separation may be for noise isolation or measurement purposes.
AF38	DRAM_VDD_S4_AF38	DRAM_VDD_CLK	✅	DDR3L memory power supply pins connected to DRAM_VDD_CLK rail, which connects to +VDIMM through 0-ohm resistor R275. This separation may be for noise isolation or measurement purposes.
AF30	TP_CORE_V1P05_S4	$9N613	✅	Core voltage test point connection. This pin is connected to internal net $9N613 which connects to test point TP1 (marked DNI).

R275 - 0 ohm JMPR 1/10W 0603 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Connected to +VDIMM, the main DRAM power supply rail. This pin serves as the input side of the 0-ohm jumper.
2	2	DRAM_VDD_CLK	✅	Connected to DRAM_VDD_CLK, a separate DRAM clock power rail. This pin serves as the output side of the 0-ohm jumper, connecting the clock power pins to the main DRAM supply.

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
AC32	CORE_V1P05_S3_AC32	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
Y32	CORE_V1P05_S3_Y32	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
AA33	CORE_V1P05_S3_AA33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
AF33	CORE_V1P05_S3_AF33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
AG33	CORE_V1P05_S3_AG33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
AG35	CORE_V1P05_S3_AG35	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
U33	CORE_V1P05_S3_U33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
U35	CORE_V1P05_S3_U35	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
V33	CORE_V1P05_S3_V33	+V1P0S	❌	CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification. Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic) These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213) The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120) The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119) The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning) A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic) Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic) Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic) Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning) These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)
A3	VSS_A3_A3	GND	✅	VSS ground pins are correctly connected to GND.
A5	VSS_A5_A5	GND	✅	VSS ground pins are correctly connected to GND.
A6	VSS_A6_A6	GND	✅	VSS ground pins are correctly connected to GND.
A49	VSS_A49_A49	GND	✅	VSS ground pins are correctly connected to GND.
A51	VSS_A51_A51	GND	✅	VSS ground pins are correctly connected to GND.
A52	VSS_A52_A52	GND	✅	VSS ground pins are correctly connected to GND.
B2	VSS_B2_B2	GND	✅	VSS ground pins are correctly connected to GND.
B52	VSS_B52_B52	GND	✅	VSS ground pins are correctly connected to GND.
B53	VSS_B53_B53	GND	✅	VSS ground pins are correctly connected to GND.
BE1	VSS_BE1_BE1	GND	✅	VSS ground pins are correctly connected to GND.
BE53	VSS_BE53_BE53	GND	✅	VSS ground pins are correctly connected to GND.
BG1	VSS_BG1_BG1	GND	✅	VSS ground pins are correctly connected to GND.
BG53	VSS_BG53_BG53	GND	✅	VSS ground pins are correctly connected to GND.
BH1	VSS_BH1_BH1	GND	✅	VSS ground pins are correctly connected to GND.
BH2	VSS_BH2_BH2	GND	✅	VSS ground pins are correctly connected to GND.
BH52	VSS_BH52_BH52	GND	✅	VSS ground pins are correctly connected to GND.
BH53	VSS_BH53_BH53	GND	✅	VSS ground pins are correctly connected to GND.
BJ2	VSS_BJ2_BJ2	GND	✅	VSS ground pins are correctly connected to GND.
BJ3	VSS_BJ3_BJ3	GND	✅	VSS ground pins are correctly connected to GND.
BJ5	VSS_BJ5_BJ5	GND	✅	VSS ground pins are correctly connected to GND.
BJ49	VSS_BJ49_BJ49	GND	✅	VSS ground pins are correctly connected to GND.
BJ51	VSS_BJ51_BJ51	GND	✅	VSS ground pins are correctly connected to GND.
BJ52	VSS_BJ52_BJ52	GND	✅	VSS ground pins are correctly connected to GND.
C1	VSS_C1_C1	GND	✅	VSS ground pins are correctly connected to GND.
C53	VSS_C53_C53	GND	✅	VSS ground pins are correctly connected to GND.
E1	VSS_E1_E1	GND	✅	VSS ground pins are correctly connected to GND.
E53	VSS_E53_E53	GND	✅	VSS ground pins are correctly connected to GND.
B6	UNCORE_V1P0_G3_B6	+V1P0A	✅	UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors.
C5	UNCORE_V1P0_G3_C5	+V1P0A	✅	UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors.
U22	UNCORE_V1P0_G3_U22	+V1P0A	✅	UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors.
V22	UNCORE_V1P0_G3_V22	+V1P0A	✅	UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors.
C3	USB3_V1P0_G3_C3	+V1P0A	✅	UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors.
Y19	USB3_V1P0_G3_Y19	+V1P0A	✅	UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors.
F1	RESERVED_F1	$10N1595	✅	RESERVED pin is connected to test point TP4 on net $10N1595. Reserved pins should typically be left unconnected or grounded; connection to a test point may be for factory test purposes but should be verified.
M14	USB_V1P0_S3_M14	+V1P0S	✅	USB_V1P0_S3 power pins are correctly connected to +V1P0S supply.
U18	USB_V1P0_S3_U18	+V1P0S	✅	USB_V1P0_S3 power pins are correctly connected to +V1P0S supply.
U19	USB_V1P0_S3_U19	+V1P0S	✅	USB_V1P0_S3 power pins are correctly connected to +V1P0S supply.
N18	USB_V3P3_G3_N18	+3VSB	✅	USB_V3P3_G3 power pins are correctly connected to +3VSB supply with appropriate decoupling capacitors.
P18	USB_V3P3_G3_P18	+3VSB	✅	USB_V3P3_G3 power pins are correctly connected to +3VSB supply with appropriate decoupling capacitors.
N20	USB_V1P8_G3_N20	+V1P8A	✅	USB_V1P8_G3 power pin is correctly connected to +V1P8A supply.
N22	PCU_V3P3_G3_N22	+3VSB	✅	PCU_V3P3_G3 power pin is correctly connected to +3VSB supply with appropriate decoupling capacitors.
P22	RTC_VCC_P22	+RTCVCC	✅	RTC_VCC power pin is correctly connected to +RTCVCC supply with 0.1µF decoupling capacitor C212.
U16	USB_VSSA_U16	GND	✅	USB_VSSA and VSSA ground pins are correctly connected to GND.
AN16	VSSA_AN16	GND	✅	USB_VSSA and VSSA ground pins are correctly connected to GND.
U24	UNCORE_V1P8_G3_U24	+V1P8A	✅	UNCORE_V1P8_G3 power pins are correctly connected to +V1P8A supply with appropriate decoupling capacitors.
AA18	UNCORE_V1P8_G3_AA18	+V1P8A	✅	UNCORE_V1P8_G3 power pins are correctly connected to +V1P8A supply with appropriate decoupling capacitors.
U25	PMU_V1P8_G3_U25	+V1P8A	✅	PMU_V1P8_G3 power pin is correctly connected to +V1P8A supply with decoupling capacitor C236 placed nearby.
V18	USB_HSIC_V1P24_G3_V18	+V1P0A	✅	USB_HSIC_V1P24_G3 power pin is connected to +V1P0A (1.0V) instead of the specified 1.24V. This is acceptable per text note indicating USB HSIC is not used and the pin can connect to V1P0A in this configuration.
V24	UNCORE_V1P0_S0IX_V24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling.
Y24	UNCORE_V1P0_S0IX_Y24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling.
Y22	UNCORE_V1P0_S0IX_Y22	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling.
AN29	UNCORE_V1P0_S0IX_AN29	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling.
AN30	UNCORE_V1P0_S0IX_AN30	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling.
AF21	UNCORE_V1P0_S0IX_AF21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling.
AG21	UNCORE_V1P0_S0IX_AG21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling.
V25	PCU_V1P8_G3_V25	+V1P8A	✅	PCU_V1P8_G3 power pin is correctly connected to +V1P8A supply with decoupling capacitor C196 placed nearby.
V32	SVID_V1P0_S3_V32	+V1P0S	✅	SVID_V1P0_S3 power pin is correctly connected to +V1P0S supply.
AA25	UNCORE_V1P35_S0IX_F5_AA25	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling.
AF19	UNCORE_V1P35_S0IX_F6	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling.
V36	UNCORE_V1P35_S0IX_F3_V36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling.
U36	UNCORE_V1P35_S0IX_F4_U36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling.
AG32	UNCORE_V1P35_S0IX_F2_AG32	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling.
AG19	UNCORE_V1P35_S0IX_F1_AG19	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling.
AD36	DRAM_V1P35_S0IX_F1_AD36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling.
AA36	DRAM_V1P0_S0IX_AA36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
AD35	DRAM_V1P0_S0IX_AD35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
AF35	DRAM_V1P0_S0IX_AF35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
AF36	DRAM_V1P0_S0IX_AF36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
AJ36	DRAM_V1P0_S0IX_AJ36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
AK35	DRAM_V1P0_S0IX_AK35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
AK36	DRAM_V1P0_S0IX_AK36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
Y35	DRAM_V1P0_S0IX_Y35	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
Y36	DRAM_V1P0_S0IX_Y36	VCC_DRAM	✅	DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling.
AD16	VSS_AD16	VCC_VSS_V1P2	✅	VSS_AD16 and VSS_AD18 pins are connected to VCC_VSS_V1P2 which connects to GND through 0-ohm resistor R216. This configuration allows grounding when MIPI CSI is not used, as indicated by text notes.
AD18	VSS_AD18	VCC_VSS_V1P2	✅	VSS_AD16 and VSS_AD18 pins are connected to VCC_VSS_V1P2 which connects to GND through 0-ohm resistor R216. This configuration allows grounding when MIPI CSI is not used, as indicated by text notes.
BD1	VGA_V1P35_S3_F1_BD1	VCC_CRT_V1P35	✅	VGA_V1P35_S3_F1 power pin is correctly connected to VCC_CRT_V1P35, which derives from +V1P35S through ferrite bead FB4 with appropriate decoupling.
AF16	UNCORE_V1P0_S3_AF16	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AF18	UNCORE_V1P0_S3_AF18	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
G1	UNCORE_V1P0_S3_G1	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
Y18	UNCORE_V1P0_S3_Y18	+V1P0S	✅	UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AJ18	DDI_V1P0_S0IX_AJ18	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby.
AK19	DDI_V1P0_S0IX_AK19	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby.
AK21	DDI_V1P0_S0IX_AK21	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby.
AM16	DDI_V1P0_S0IX_AM16	+V1P0S	✅	DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby.
AJ19	ICLK_V1P35_S3_F1_AJ19	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which derives from +V1P35S through ferrite bead FB5 with appropriate decoupling.
AG18	ICLK_V1P35_S3_F2	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which derives from +V1P35S through ferrite bead FB5 with appropriate decoupling.
BJ6	VGA_V1P0_S3_BJ6	+V1P0S	✅	VGA_V1P0_S3 power pin is correctly connected to +V1P0S supply.
AM27	LPC_V1P8V3P3_S3_AM27	+VCC3S	✅	LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V), indicating the design uses 3.3V I/O for LPC and SD interfaces.
AN27	SD3_V1P8V3P3_S3_AN27	+VCC3S	✅	LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V), indicating the design uses 3.3V I/O for LPC and SD interfaces.
AM30	UNCORE_V1P8_S3_AM30	+V1P8S	✅	UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S supply with appropriate decoupling capacitors.
AN32	UNCORE_V1P8_S3_AN32	+V1P8S	✅	UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S supply with appropriate decoupling capacitors.
U38	UNCORE_V1P8_S3_U38	+V1P8S	✅	UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S supply with appropriate decoupling capacitors.
AM32	HDA_LPE_V1P5V1P8_S3_AM32	+V1P8S	✅	HDA_LPE_V1P5V1P8_S3 power pin is correctly connected to +V1P8S, indicating the design uses LPE (Low Power Engine) audio at 1.8V rather than HD Audio at 1.5V.
AN18	PCIE_SATA_V1P0_S3_AN18	+V1P0S	✅	PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AN19	SATA_V1P0_S3_AN19	+V1P0S	✅	PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AN21	PCIE_V1P0_S3_AN21	+V1P0S	✅	PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AM21	PCIE_V1P0_S3_AM21	+V1P0S	✅	PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AM18	PCIE_V1P0_S3_AM18	+V1P0S	✅	PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AK18	PCIE_V1P0_S3_AK18	+V1P0S	✅	PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply.
AN24	VGA_V3P3_S3_AN24	+VCC3S	✅	VGA_V3P3_S3 power pin is correctly connected to +VCC3S supply.
AN25	GPIO_V1P0_S3_AN25	+V1P0S	✅	GPIO_V1P0_S3 power pin is correctly connected to +V1P0S supply.

FB3 - FERRITE_600OHM_1.3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin correctly connected to +V1P35S source power rail. This is the unfiltered input side of the ferrite bead.
2	2	VCC_UNCORE_V1P35	✅	Output pin correctly connected to VCC_UNCORE_V1P35, supplying filtered power to CPU1 UNCORE domain with appropriate decoupling.

FB4 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to +V1P35S supply rail. This is the unfiltered 1.35V input to the ferrite bead.
2	2	VCC_CRT_V1P35	✅	Output pin connected to VCC_CRT_V1P35, providing filtered 1.35V power to the VGA/CRT section of CPU1 pin BD1.

C164 - 22uF 20% 6.3V 0805 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net for decoupling capacitor function.
2	2	VCC_CRT_V1P35	✅	Power pin connected to VCC_CRT_V1P35, providing bulk decoupling for the VGA 1.35V rail.

C28 - 2232-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net for decoupling capacitor function.
2	2	VCC_CRT_V1P35	✅	Power pin connected to VCC_CRT_V1P35, providing additional bulk decoupling for the VGA 1.35V rail.

C26 - 1uF 10% 16V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin of decoupling capacitor for VCC_ICLK_V1P35 rail.
2	2	VCC_ICLK_V1P35	✅	Power pin connected to VCC_ICLK_V1P35, providing decoupling for the CPU ICLK domain.

C27 - 1uF 10% 16V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin of decoupling capacitor for VCC_ICLK_V1P35 rail.
2	2	VCC_ICLK_V1P35	✅	Power pin connected to VCC_ICLK_V1P35, providing decoupling for the CPU ICLK domain.

FB5 - FERRITE_120OHM_3A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input pin connected to +V1P35S supply rail. This is the input side of the ferrite bead that filters power for the ICLK domain.
2	2	VCC_ICLK_V1P35	✅	Output pin connected to VCC_ICLK_V1P35 net. This supplies filtered 1.35V power to the CPU ICLK domain.

R222 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	0-ohm jumper connecting +V1P0S supply to VCC_VIS_V1P0 rail, providing power to the VIS/graphics portion of the CPU. Current requirement is 2.1A based on nearby text notes.
2	2	VCC_VIS_V1P0	✅	0-ohm jumper connecting +V1P0S supply to VCC_VIS_V1P0 rail, providing power to the VIS/graphics portion of the CPU. Current requirement is 2.1A based on nearby text notes.

R265 - 0 ohm JMPR 1/10W 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	0-ohm jumper connecting +V1P0S supply to VCC_DRAM rail, providing power to the DRAM interface of the CPU. Current requirement is 900mA.
2	2	VCC_DRAM	✅	0-ohm jumper connecting +V1P0S supply to VCC_DRAM rail, providing power to the DRAM interface of the CPU. Current requirement is 900mA.

R216 - RES_0Ohm_1%_1/10W_0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VSS_V1P2	✅	0-ohm resistor connecting VCC_VSS_V1P2 net to GND, grounding special VSS pins (AD16, AD18) of the CPU when MIPI/CSI interface is not used.
2	2	GND	✅	0-ohm resistor connecting VCC_VSS_V1P2 net to GND, grounding special VSS pins (AD16, AD18) of the CPU when MIPI/CSI interface is not used.

C153 - 0.1uF ✅

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ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to +5VSB for decoupling the standby power rail.
2	2	GND	✅	Pin 2 is connected to GND, completing the decoupling capacitor connection.

D7 - D5V0L1B2LP-7B ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Pin N is connected to GND, providing the ground reference for the bidirectional TVS diode protecting the +5VSB rail.
P	P	+5VSB	✅	Pin P is connected to +5VSB, the protected power rail for this TVS diode.

J8 - 3430-0212 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 provides +5VSB power input to the board. This connector is an alternative to J2 which is marked DNI.
2	2	GND	✅	Pin 2 provides ground reference for the +5VSB power input.

CPU1 - INTEL_ATOM_E3825_SOC ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A11	VSS1	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A15	VSS2	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A19	VSS3	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A23	VSS4	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A27	VSS5	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A31	VSS6	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A35	VSS7	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A39	VSS8	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A43	VSS9	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
A47	VSS10	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA1	VSS11	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA3	VSS15	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA12			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA16	VSS12	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA19	VSS13	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA21	VSS14	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA32	VSS16	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA35	VSS17	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA38	VSS18	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AA53	VSS19	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB4	VSS21	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB6	VSS28	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB10	VSS20	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB41	VSS22	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB45	VSS23	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB47	VSS24	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB48	VSS25	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB50	VSS26	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AB51	VSS27	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC16	VSS29	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC18	VSS30	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC19	VSS31	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC21	VSS32	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC25	VSS33	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC33	VSS34	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC35	VSS35	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC36	VSS36	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AC38	VSS37	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AD7	VSS44	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AD19	VSS38	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AD21	VSS39	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AD25	VSS40	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AD32	VSS41	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AD33	VSS42	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AD47	VSS43	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE1	VSS45	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE3	VSS49	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE4	VSS50	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE6	VSS60	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE8	VSS61	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE9	VSS62	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE11	VSS46	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE12	VSS47	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE14	VSS48	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE40	VSS51	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE42	VSS52	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE43	VSS53	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE45	VSS54	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE46	VSS55	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE48	VSS56	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE50	VSS57	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE51	VSS58	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AE53	VSS59	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AF10	VSS63	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AF12	VSS64	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AF25	VSS65	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AF32	VSS66	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AF47	VSS67	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AG16	VSS68	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AG25	VSS69	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AG36	VSS70	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AG38	VSS71	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AG71			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH4	VSS72	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH6	VSS110	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH7	VSS75	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH9	VSS76	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH41	VSS73	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH45	VSS74	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH47	VSS106	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH48	VSS107	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH50	VSS108	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH51	VSS109	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH74			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH75			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH76			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH106			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH107			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH108			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH109			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AH110			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ1	VSS77	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ3	VSS83	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ16	VSS78	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ21	VSS79	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ25	VSS80	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ27	VSS81	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ29	VSS82	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ30	VSS84	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ32	VSS85	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ33	VSS86	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ35	VSS87	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ38	VSS88	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ53	VSS89	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ77			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ78			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ79			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ80			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ81			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ82			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ83			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ84			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ85			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ86			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ87			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ88			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AJ89			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK10	VSS90	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK14	VSS91	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK16	VSS92	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK33	VSS93	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK41	VSS94	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK44	VSS95	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK90			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK91			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK92			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK93			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK94			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AK95			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM7	VSS113	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM12	VSS96	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM19	VSS97	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM24	VSS98	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM25	VSS99	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM29	VSS100	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM33	VSS101	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM35	VSS102	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM36	VSS103	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM40	VSS104	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM44	VSS111	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM51	VSS112	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM96			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM97			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM98			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM99			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM100			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM101			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM102			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AM103			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN1	VSS114	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN3	VSS119	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN5	VSS131	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN6	VSS134	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN8	VSS135	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN9	VSS136	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN11	VSS115	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN12	VSS116	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN14	VSS117	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN22	VSS118	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN33	VSS120	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN35	VSS121	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN36	VSS122	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN38	VSS123	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN40	VSS124	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN42	VSS125	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN43	VSS126	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN45	VSS127	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN46	VSS128	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN48	VSS129	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN49	VSS130	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN51	VSS132	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN53	VSS133	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN114			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN115			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN116			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN117			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN118			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN119			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN120			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN121			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN122			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN123			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN124			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN125			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN126			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN127			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN128			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN129			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN130			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN131			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN132			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN133			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN134			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN135			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AN136			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AP40	VSS137	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AP137			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT4	VSS146	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT12	VSS138	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT16	VSS139	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT19	VSS140	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT24	VSS141	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT27	VSS142	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT30	VSS143	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT35	VSS144	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT38	VSS145	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT47	VSS147	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT52	VSS148	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT138			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT139			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AT140			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AU1	VSS149	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AU3	VSS151	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AU24	VSS150	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AU30	VSS152	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AU38	VSS153	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AU51	VSS154	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AU52			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV7	VSS167	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV12	VSS155	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV13	VSS156	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV14	VSS157	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV18	VSS158	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV19	VSS159	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV24	VSS160	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV27	VSS161	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV30	VSS162	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV35	VSS163	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV38	VSS164	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV47	VSS165	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AV51	VSS166	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AW3	VSS171	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AW13	VSS168	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AW19	VSS169	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AW27	VSS170	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AW35	VSS172	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AY4	VSS177	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AY9	VSS179	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AY10	VSS173	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AY22	VSS174	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AY32	VSS175	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AY36	VSS176	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
AY50	VSS178	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA14	VSS180	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA19	VSS181	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA22	VSS182	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA27	VSS183	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA32	VSS184	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA35	VSS185	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA40	VSS186	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BA53	VSS187	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BB19	VSS188	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BB27	VSS189	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BB35	VSS190	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BC20	VSS191	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BC22	VSS192	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BC26	VSS193	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BC28	VSS194	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BC32	VSS195	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BC34	VSS196	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BC42	VSS197	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BD19	VSS198	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BD24	VSS199	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BD27	VSS200	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BD30	VSS201	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BD35	VSS202	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BE2	VSS204	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BE8	VSS206	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BE19	VSS203	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BE35	VSS205	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BF4	VSS213	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BF12	VSS207	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BF16	VSS208	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BF24	VSS209	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BF30	VSS211	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BF36	VSS212	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BF38	VSS210	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BG31	VSS214	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BG34	VSS215	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BG39	VSS216	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BG42	VSS217	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BG45	VSS218	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BG49	VSS219	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ7	VSS230	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ11	VSS220	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ15	VSS221	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ19	VSS222	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ23	VSS223	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ27	VSS224	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ31	VSS225	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ35	VSS226	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ39	VSS227	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ43	VSS228	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
BJ47	VSS229	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C14	VSS231	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C21			✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C31	VSS232	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C34	VSS233	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C39	VSS234	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C42	VSS235	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C45	VSS236	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
C49	VSS237	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
D12	VSS238	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
D16	VSS239	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
D24	VSS240	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
D30	VSS241	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
D36	VSS242	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
D38	VSS243	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
E8	VSS246	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
E19	VSS244	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
E35	VSS245	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F2	VSS248	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F5	VSS253	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F7	VSS254	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F19	VSS247	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F24	VSS249	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F27	VSS250	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F30	VSS251	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
F35	VSS252	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G10	VSS255	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G20	VSS256	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G22	VSS257	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G26	VSS258	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G28	VSS259	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G32	VSS260	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G34	VSS261	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
G42	VSS262	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
H19	VSS263	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
H27	VSS264	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
H35	VSS265	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J1	VSS266	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J16	VSS267	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J19	VSS268	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J22	VSS269	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J27	VSS270	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J32	VSS271	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J35	VSS272	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J40	VSS273	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
J53	VSS274	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
K4	VSS279	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
K9	VSS281	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
K14	VSS275	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
K22	VSS276	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
K32	VSS277	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
K36	VSS278	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
K50	VSS280	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
L13	VSS282	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
L19	VSS283	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
L27	VSS284	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
L35	VSS285	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M19	VSS286	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M26	VSS287	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M27	VSS288	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M28	VSS105	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M34	VSS289	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M35	VSS290	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M38	VSS291	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M47	VSS292	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
M51	VSS293	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
N1	VSS294	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
N16	VSS295	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
N38	VSS296	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
N51	VSS297	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P4	VSS306	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P9	VSS309	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P13	VSS298	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P16	VSS299	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P19	VSS300	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P20	VSS301	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P24	VSS302	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P32	VSS303	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P35	VSS304	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P38	VSS305	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P47	VSS307	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
P52	VSS308	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
T40	VSS310	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U1	VSS311	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U3	VSS316	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U5	VSS326	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U6	VSS329	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U8	VSS330	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U9	VSS331	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U11	VSS312	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U12	VSS313	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U14	VSS314	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U21	VSS315	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U30	VSS317	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U32	VSS318	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U40	VSS319	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U42	VSS320	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U43	VSS321	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U45	VSS322	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U46	VSS323	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U48	VSS324	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U49	VSS325	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U51	VSS327	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
U53	VSS328	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V7	VSS340	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V12	VSS332	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V16	VSS333	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V19	VSS334	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V21	VSS335	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V35	VSS336	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V40	VSS337	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V44	VSS338	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
V51	VSS339	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y7	VSS349	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y9	VSS350	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y10	VSS341	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y14	VSS342	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y16	VSS343	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y21	VSS344	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y25	VSS345	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y33	VSS346	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y41	VSS347	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.
Y44	VSS348	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation.

MEM2 - MT41K256M16HA-125:E ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
C1	VDDQ2	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
R1	VDD7	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
B2	VDD8	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
D2	VDDQ9	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
H2	VDDQ4	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
K2	VDD9	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
G7	VDD1	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
A8	VDDQ5	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
K8	VDD2	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
C9	VDDQ6	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
N1	VDD6	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
F1	VDDQ3	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
D9	VDD4	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
E9	VDDQ7	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
H9	VDDQ8	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
N9	VDD3	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
R9	VDD5	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
B1	VSSQ1	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
D1	VSSQ2	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
E1	VSS1	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
G1	VSSQ3	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
M1	VSS2	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
P1	VSS3	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
T1	VSS4	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
E2	VSSQ4	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
J2	VSS5	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
B3	VSS6	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
D8	VSSQ5	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
E8	VSSQ6	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
G8	VSS7	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
J8	VSS8	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
A9	VSS9	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
B9	VSSQ7	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
F9	VSSQ8	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
G9	VSSQ9	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
M9	VSS10	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
P9	VSS11	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
T9	VSS12	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
C7	DQSU	M_DQS_A_P1	✅	Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P1 and M_DQS_A_N1, providing the strobe signal for the upper byte data.
B7	/DQSU	M_DQS_A_N1	✅	Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P1 and M_DQS_A_N1, providing the strobe signal for the upper byte data.
D3	DMU	M_DM_A1	✅	Upper byte data mask pin UDM is connected to M_DM_A1, providing write data masking capability for the upper byte.
D7	DQU0	M_DATA_A9	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
C3	DQU1	M_DATA_A10	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
C8	DQU2	M_DATA_A8	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
C2	DQU3	M_DATA_A11	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
A7	DQU4	M_DATA_A13	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
A2	DQU5	M_DATA_A15	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
B8	DQU6	M_DATA_A12	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
A3	DQU7	M_DATA_A14	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device.
E3	DQL0	M_DATA_A0	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
F7	DQL1	M_DATA_A1	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
F2	DQL2	M_DATA_A2	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
F8	DQL3	M_DATA_A3	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
H3	DQL4	M_DATA_A4	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
H8	DQL5	M_DATA_A5	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
G2	DQL6	M_DATA_A6	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
H7	DQL7	M_DATA_A7	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device.
E7	DML	M_DM_A0	✅	Lower byte data mask pin LDM is connected to M_DM_A0, providing write data masking capability for the lower byte.
F3	DQSL	M_DQS_A_P0	✅	Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P0 and M_DQS_A_N0, providing the strobe signal for the lower byte data.
G3	/DQSL	M_DQS_A_N0	✅	Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P0 and M_DQS_A_N0, providing the strobe signal for the lower byte data.
H1	VREFDQ	SM_VREF_DQ1_A	✅	Reference voltage pin VREFDQ is connected to SM_VREF_DQ1_A, which is generated by a resistor divider (R310 and R325) to provide VDD×0.5 reference for data signals.
J1	NC1__ODT1_		✅	No connect pins are left unconnected as specified by the datasheet.
L1	NC2__/CS1_		✅	No connect pins are left unconnected as specified by the datasheet.
J9	NC3__CKE1_		✅	No connect pins are left unconnected as specified by the datasheet.
L9	NC4__ZQ1_		✅	No connect pins are left unconnected as specified by the datasheet.
M7	NC5		✅	No connect pins are left unconnected as specified by the datasheet.
J3	/RAS	M_RAS_A_L	✅	Row address strobe pin RAS# is connected to M_RAS_A_L, providing the row address strobe command input.
J7	CK	M_CLK_A_P0	✅	Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device.
K7	/CK	M_CLK_A_N0	✅	Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device.
K1	ODT	M_ODT_A0	✅	On-die termination enable pin ODT is connected to M_ODT_A0, controlling the termination resistance for DQ, DQS, and DM signals.
K3	/CAS	M_CAS_A_L	✅	Column address strobe pin CAS# is connected to M_CAS_A_L, providing the column address strobe command input.
K9	CKE	M_CKE_A0	✅	Clock enable pin CKE is connected to M_CKE_A0, controlling the device's clock enable state.
L2	/CS	M_CS_A_L0	✅	Chip select pin CS# is connected to M_CS_A_L0, enabling/disabling the command decoder for this device.
L3	/WE	M_WE_A_L	✅	Write enable pin WE# is connected to M_WE_A_L, providing the write enable command input.
L8	ZQ	M_ZQ1	✅	ZQ calibration pin is connected to M_ZQ1, which has a 240 ohm resistor (R140) to ground for output driver and ODT calibration.
M2	BA0	M_BS_A0	✅	Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs.
N8	BA1	M_BS_A1	✅	Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs.
M3	BA2	M_BS_A2	✅	Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs.
M8	VREFCA	SM_VREF_CA1_A	✅	Reference voltage pin VREFCA is connected to SM_VREF_CA1_A, which is generated by a resistor divider (R144 and R326) to provide VDD×0.5 reference for control, command, and address signals.
N3	A0	M_MA_A0	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P7	A1	M_MA_A1	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P3	A2	M_MA_A2	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
N2	A3	M_MA_A3	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P8	A4	M_MA_A4	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P2	A5	M_MA_A5	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R8	A6	M_MA_A6	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R2	A7	M_MA_A7	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T8	A8	M_MA_A8	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R3	A9	M_MA_A9	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
L7	A10_AP_	M_MA_A10	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R7	A11	M_MA_A11	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
N7	A12_/BC_	M_MA_A12	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T3	A13	M_MA_A13	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T7	A14	M_MA_A14	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T2	/RESET	M_A_RST_L	✅	Reset pin RESET# is connected to M_A_RST_L, which is shared with MEM3 and has an optional series resistor (R353) and DNI capacitor (C374) for signal conditioning.

MEM3 - MT41K256M16HA-125:E ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
C1	VDDQ2	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
R1	VDD7	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
B2	VDD8	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
D2	VDDQ9	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
H2	VDDQ4	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
K2	VDD9	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
G7	VDD1	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
A8	VDDQ5	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
K8	VDD2	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
C9	VDDQ6	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
N1	VDD6	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
F1	VDDQ3	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
D9	VDD4	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
E9	VDDQ7	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
H9	VDDQ8	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
N9	VDD3	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
R9	VDD5	+VDIMM	✅	All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device.
B1	VSSQ1	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
D1	VSSQ2	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
E1	VSS1	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
G1	VSSQ3	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
M1	VSS2	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
P1	VSS3	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
T1	VSS4	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
E2	VSSQ4	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
J2	VSS5	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
B3	VSS6	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
D8	VSSQ5	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
E8	VSSQ6	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
G8	VSS7	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
J8	VSS8	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
A9	VSS9	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
B9	VSSQ7	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
F9	VSSQ8	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
G9	VSSQ9	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
M9	VSS10	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
P9	VSS11	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
T9	VSS12	GND	✅	All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device.
C7	DQSU	M_DQS_A_P3	✅	Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P3 and M_DQS_A_N3, providing the strobe signal for the upper byte data.
B7	/DQSU	M_DQS_A_N3	✅	Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P3 and M_DQS_A_N3, providing the strobe signal for the upper byte data.
D3	DMU	M_DM_A3	✅	Upper byte data mask pin UDM is connected to M_DM_A3, providing write data masking capability for the upper byte.
D7	DQU0	M_DATA_A29	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
C3	DQU1	M_DATA_A26	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
C8	DQU2	M_DATA_A28	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
C2	DQU3	M_DATA_A27	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
A7	DQU4	M_DATA_A25	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
A2	DQU5	M_DATA_A30	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
B8	DQU6	M_DATA_A24	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
A3	DQU7	M_DATA_A31	✅	Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus.
E3	DQL0	M_DATA_A16	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
F7	DQL1	M_DATA_A17	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
F2	DQL2	M_DATA_A18	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
F8	DQL3	M_DATA_A19	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
H3	DQL4	M_DATA_A20	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
H8	DQL5	M_DATA_A21	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
G2	DQL6	M_DATA_A22	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
H7	DQL7	M_DATA_A23	✅	Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus.
E7	DML	M_DM_A2	✅	Lower byte data mask pin LDM is connected to M_DM_A2, providing write data masking capability for the lower byte.
F3	DQSL	M_DQS_A_P2	✅	Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P2 and M_DQS_A_N2, providing the strobe signal for the lower byte data.
G3	/DQSL	M_DQS_A_N2	✅	Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P2 and M_DQS_A_N2, providing the strobe signal for the lower byte data.
H1	VREFDQ	SM_VREF_DQ1_A	✅	Reference voltage pin VREFDQ is connected to SM_VREF_DQ1_A, which is generated by a resistor divider (R310 and R325) to provide VDD×0.5 reference for data signals.
J1	NC1__ODT1_		✅	No connect pins are left unconnected as specified by the datasheet.
L1	NC2__/CS1_		✅	No connect pins are left unconnected as specified by the datasheet.
J9	NC3__CKE1_		✅	No connect pins are left unconnected as specified by the datasheet.
L9	NC4__ZQ1_		✅	No connect pins are left unconnected as specified by the datasheet.
M7	NC5		✅	No connect pins are left unconnected as specified by the datasheet.
J3	/RAS	M_RAS_A_L	✅	Row address strobe pin RAS# is connected to M_RAS_A_L, providing the row address strobe command input.
J7	CK	M_CLK_A_P0	✅	Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device.
K7	/CK	M_CLK_A_N0	✅	Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device.
K1	ODT	M_ODT_A0	✅	On-die termination enable pin ODT is connected to M_ODT_A0, controlling the termination resistance for DQ, DQS, and DM signals.
K3	/CAS	M_CAS_A_L	✅	Column address strobe pin CAS# is connected to M_CAS_A_L, providing the column address strobe command input.
K9	CKE	M_CKE_A0	✅	Clock enable pin CKE is connected to M_CKE_A0, controlling the device's clock enable state.
L2	/CS	M_CS_A_L0	✅	Chip select pin CS# is connected to M_CS_A_L0, enabling/disabling the command decoder for this device.
L3	/WE	M_WE_A_L	✅	Write enable pin WE# is connected to M_WE_A_L, providing the write enable command input.
L8	ZQ	M_ZQ2	✅	ZQ calibration pin is connected to M_ZQ2, which has a 240 ohm resistor (R327) to ground for output driver and ODT calibration.
M2	BA0	M_BS_A0	✅	Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs.
N8	BA1	M_BS_A1	✅	Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs.
M3	BA2	M_BS_A2	✅	Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs.
M8	VREFCA	SM_VREF_CA1_A	✅	Reference voltage pin VREFCA is connected to SM_VREF_CA1_A, which is generated by a resistor divider (R144 and R326) to provide VDD×0.5 reference for control, command, and address signals.
N3	A0	M_MA_A0	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P7	A1	M_MA_A1	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P3	A2	M_MA_A2	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
N2	A3	M_MA_A3	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P8	A4	M_MA_A4	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
P2	A5	M_MA_A5	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R8	A6	M_MA_A6	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R2	A7	M_MA_A7	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T8	A8	M_MA_A8	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R3	A9	M_MA_A9	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
L7	A10_AP_	M_MA_A10	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
R7	A11	M_MA_A11	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
N7	A12_/BC_	M_MA_A12	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T3	A13	M_MA_A13	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T7	A14	M_MA_A14	✅	Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs.
T2	/RESET	M_A_RST_L	✅	Reset pin RESET# is connected to M_A_RST_L, which is shared with MEM2 and has an optional series resistor (R353) and DNI capacitor (C374) for signal conditioning.

R353 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_A_DRAMRST_L	✅	Pin 1 connects to M_A_DRAMRST_L, which is the DRAM reset signal source. Pin 2 connects to M_A_RST_L, which routes to the /RESET pins of DDR3 memory chips MEM2 and MEM3.
2	2	M_A_RST_L	✅	Pin 2 connects to M_A_RST_L, which routes to the /RESET pins (T2) of DDR3 memory chips MEM2 and MEM3, and to a DNI capacitor C374.

P2 - 158-0001269 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	SD3_D2_R	✅	DAT2 is correctly connected to the filtered SD3_D2_R signal from the passive filter.
2	CD/DAT3	SD3_D3_R	✅	CD/DAT3 is correctly connected to the filtered SD3_D3_R signal from the passive filter.
3	CMD	SD3_CMD_R	✅	CMD is correctly connected to the filtered SD3_CMD_R signal from the passive filter.
4	VDD	+VCC3	✅	VDD is correctly connected to +VCC3 with appropriate decoupling capacitors.
5	CLOCK	SD3_CLK_R	✅	CLOCK is correctly connected to the filtered SD3_CLK_R signal from the passive filter.
6	VSS	GND	✅	VSS is correctly connected to ground.
7	DAT0	SD3_D0_R	✅	DAT0 is correctly connected to the filtered SD3_D0_R signal from the passive filter.
8	DAT1	SD3_D1_R	✅	DAT1 is correctly connected to the filtered SD3_D1_R signal from the passive filter.
9	GND	GND	✅	GND is correctly connected to ground.
10	CD	SD3_CD_R	✅	CD is correctly connected to the filtered SD3_CD_R signal from the passive filter.
11	GND3	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections.
12	GND4	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections.
15	GND7	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections.
16	GND8	FGND-uSD	✅	GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections.
13	GND5	FGND-uSD-Front	✅	GND5 and GND6 are connected to FGND-uSD-Front for front frame ground connections.
14	GND6	FGND-uSD-Front	✅	GND5 and GND6 are connected to FGND-uSD-Front for front frame ground connections.

FL1 - 3750-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CH1-IN	SD3_CD#	✅	CH1-IN receives the card detect signal SD3_CD# with a 100K pull-up to +V1P8S and filters it to the connector.
2	CH2-IN	SD3_D2	✅	CH2-IN receives SD3_D2 with a 100K pull-up to +VCC3 and filters it to the connector.
3	CH3-IN	SD3_D3	✅	CH3-IN receives SD3_D3 with a 100K pull-up to +VCC3 and filters it to the connector.
4	CH4-IN	SD3_CMD	✅	CH4-IN receives SD3_CMD with a 100K pull-up to +VCC3 and filters it to the connector.
5	CH5-IN	SD3_CLK	✅	CH5-IN receives SD3_CLK with a 100K pull-up to +VCC3 and filters it to the connector.
6	CH6-IN	SD3_D0	✅	CH6-IN receives SD3_D0 with a 100K pull-up to +VCC3 and filters it to the connector.
7	CH7-IN	SD3_D1	✅	CH7-IN receives SD3_D1 with a 100K pull-up to +VCC3 and filters it to the connector.
8	CH8-IN		✅	CH8-IN is not connected, leaving channel 8 unused.
9	CH8-OUT		✅	CH8-OUT is not connected, corresponding to the unused channel 8.
10	CH7-OUT	SD3_D1_R	✅	CH7-OUT provides the filtered SD3_D1_R signal to the SD card connector DAT1 pin.
11	CH6-OUT	SD3_D0_R	✅	CH6-OUT provides the filtered SD3_D0_R signal to the SD card connector DAT0 pin.
12	CH5-OUT	SD3_CLK_R	✅	CH5-OUT provides the filtered SD3_CLK_R signal to the SD card connector CLOCK pin.
13	CH4-OUT	SD3_CMD_R	✅	CH4-OUT provides the filtered SD3_CMD_R signal to the SD card connector CMD pin.
14	CH3-OUT	SD3_D3_R	✅	CH3-OUT provides the filtered SD3_D3_R signal to the SD card connector CD/DAT3 pin.
15	CH2-OUT	SD3_D2_R	✅	CH2-OUT provides the filtered SD3_D2_R signal to the SD card connector DAT2 pin.
16	CH1-OUT	SD3_CD_R	✅	CH1-OUT provides the filtered SD3_CD_R signal to the SD card connector card detect pin.
17	GND_PAD	GND	✅	GND_PAD is correctly connected to the ground plane.

U2 - TPD12S016PW ✅

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📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	CEC_A	HDMI_CEC	✅	CEC_A pin connects to HDMI_CEC net for HDMI controller side CEC signal. Connection is correct.
2	SCL_A	HDMI_DDCCLK	✅	SCL_A pin connects to HDMI_DDCCLK net with external 10kΩ pullup resistor R28. External pullup is not required per datasheet but is acceptable.
3	SDA_A	HDMI_DDCDAT	✅	SDA_A pin connects to HDMI_DDCDAT net with external 10kΩ pullup resistor R30. External pullup is not required per datasheet but is acceptable.
4	HPD_A	HDMI_HPD	✅	HPD_A pin connects to HDMI_HPD net for hot plug detect output to HDMI controller. Connection is correct.
5	LS_OE	LS_OE	✅	LS_OE pin connects to net LS_OE with 2.2kΩ pullup resistor R172 to +V1P8S, enabling level shifters by default. Connection is correct.
6	GND1	GND	✅	GND1 pin is correctly connected to ground net GND.
7	CEC_B	C_HDMI_CEC	✅	CEC_B pin connects to C_HDMI_CEC net and HDMI connector pin 15 for HDMI cable side CEC signal. Connection is correct.
8	SCL_B	C_HDMI_SCL	✅	SCL_B pin connects to C_HDMI_SCL net and HDMI connector pin 17 for HDMI cable side SCL signal. Connection is correct.
9	SDA_B	C_HDMI_SDA	✅	SDA_B pin connects to C_HDMI_SDA net and HDMI connector pin 18 for HDMI cable side SDA signal. Connection is correct.
10	HPD_B	C_HDMI_HPD	✅	HPD_B pin connects to C_HDMI_HPD net and HDMI connector pin 1 for hot plug detect input from HDMI cable. Connection is correct.
11	VCC5V	+5VSB	✅	VCC5V pin connects to +5VSB supply with 0.1µF decoupling capacitor C155. Connection is correct per datasheet recommendations.
12	CT_HPD	HPD_ENB	✅	CT_HPD pin connects to net HPD_ENB with 2.2kΩ pullup resistor R171 to +V1P8S, enabling load switch and HPD by default. Connection is correct.
13	5V_OUT	+HDMI_CRT_VCC	✅	5V_OUT pin connects to +HDMI_CRT_VCC with 4.7µF decoupling capacitor C157 and ferrite bead L7 to HDMI connector +5V pin. Connection is correct.
14	GND2	GND	✅	GND2 pin is correctly connected to ground net GND.
15	CLK-	HDMI_OUT_CLK_DN	✅	CLK- pin connects to HDMI_OUT_CLK_DN through common mode choke L14 and to HDMI connector pin 14. Connection is correct.
16	CLK+	HDMI_OUT_CLK_DP	✅	CLK+ pin connects to HDMI_OUT_CLK_DP through common mode choke L14 and to HDMI connector pin 12. Connection is correct.
17	D0-	HDMI_OUT_TX0_DN	✅	D0- pin connects to HDMI_OUT_TX0_DN through common mode choke L15 and to HDMI connector pin 11. Connection is correct.
18	D0+	HDMI_OUT_TX0_DP	✅	D0+ pin connects to HDMI_OUT_TX0_DP through common mode choke L15 and to HDMI connector pin 9. Connection is correct.
19	GND3	GND	✅	GND3 pin is correctly connected to ground net GND.
20	D1-	HDMI_OUT_TX1_DN	✅	D1- pin connects to HDMI_OUT_TX1_DN through common mode choke L16 and to HDMI connector pin 8. Connection is correct.
21	D1+	HDMI_OUT_TX1_DP	✅	D1+ pin connects to HDMI_OUT_TX1_DP through common mode choke L16 and to HDMI connector pin 6. Connection is correct.
22	D2-	HDMI_OUT_TX2_DN	✅	D2- pin connects to HDMI_OUT_TX2_DN through common mode choke L17 and to HDMI connector pin 5. Connection is correct.
23	D2+	HDMI_OUT_TX2_DP	✅	D2+ pin connects to HDMI_OUT_TX2_DP through common mode choke L17 and to HDMI connector pin 3. Connection is correct.
24	VCCA	+V1P8S	✅	VCCA pin connects to +V1P8S supply with 0.1µF decoupling capacitor C17. Connection is correct per datasheet recommendations.

L16 - CM_CHOKE_4D ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX1_C_DN	✅	IN1 pin connects to HDMI_TX1_C_DN, the negative side of the AC-coupled HDMI data channel 1 differential pair input.
3	IN2	HDMI_TX1_C_DP	✅	IN2 pin connects to HDMI_TX1_C_DP, the positive side of the AC-coupled HDMI data channel 1 differential pair input.
4	OUT2	HDMI_OUT_TX1_DP	✅	OUT2 pin connects to HDMI_OUT_TX1_DP, outputting the filtered positive data channel 1 signal to the ESD protection IC and HDMI connector.
6	OUT1	HDMI_OUT_TX1_DN	✅	OUT1 pin connects to HDMI_OUT_TX1_DN, outputting the filtered negative data channel 1 signal to the ESD protection IC and HDMI connector.

L15 - CM_CHOKE_4D ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX0_C_DN	✅	IN1 pin connects to HDMI_TX0_C_DN, the negative side of the AC-coupled HDMI data channel 0 differential pair input.
3	IN2	HDMI_TX0_C_DP	✅	IN2 pin connects to HDMI_TX0_C_DP, the positive side of the AC-coupled HDMI data channel 0 differential pair input.
4	OUT2	HDMI_OUT_TX0_DP	✅	OUT2 pin connects to HDMI_OUT_TX0_DP, outputting the filtered positive data channel 0 signal to the ESD protection IC and HDMI connector.
6	OUT1	HDMI_OUT_TX0_DN	✅	OUT1 pin connects to HDMI_OUT_TX0_DN, outputting the filtered negative data channel 0 signal to the ESD protection IC and HDMI connector.

L17 - CM_CHOKE_4D ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX2_C_DN	✅	IN1 pin connects to HDMI_TX2_C_DN, the negative side of the AC-coupled HDMI data channel 2 differential pair input.
3	IN2	HDMI_TX2_C_DP	✅	IN2 pin connects to HDMI_TX2_C_DP, the positive side of the AC-coupled HDMI data channel 2 differential pair input.
4	OUT2	HDMI_OUT_TX2_DP	✅	OUT2 pin connects to HDMI_OUT_TX2_DP, outputting the filtered positive data channel 2 signal to the ESD protection IC and HDMI connector.
6	OUT1	HDMI_OUT_TX2_DN	✅	OUT1 pin connects to HDMI_OUT_TX2_DN, outputting the filtered negative data channel 2 signal to the ESD protection IC and HDMI connector.

L14 - CM_CHOKE_4D ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_CLK_C_DN	✅	IN1 pin connects to HDMI_CLK_C_DN, the negative side of the AC-coupled HDMI clock differential pair input.
3	IN2	HDMI_CLK_C_DP	✅	IN2 pin connects to HDMI_CLK_C_DP, the positive side of the AC-coupled HDMI clock differential pair input.
4	OUT2	HDMI_OUT_CLK_DP	✅	OUT2 pin connects to HDMI_OUT_CLK_DP, outputting the filtered positive clock signal to the ESD protection IC and HDMI connector.
6	OUT1	HDMI_OUT_CLK_DN	✅	OUT1 pin connects to HDMI_OUT_CLK_DN, outputting the filtered negative clock signal to the ESD protection IC and HDMI connector.

P1 - microHDMI_TH ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	HPLG	C_HDMI_HPD	✅	Hot plug detect signal correctly connected to U2 HPD_B pin for detecting connector insertion.
2	NC		✅	No connection pin, correctly left unconnected.
3	DAT2+	HDMI_OUT_TX2_DP	✅	Data channel 2 positive signal correctly routed through common mode choke L17 and AC coupling capacitor C406 to U2.
4	DAT2_S	GND	✅	Data channel 2 shield correctly connected to ground.
5	DAT2-	HDMI_OUT_TX2_DN	✅	Data channel 2 negative signal correctly routed through common mode choke L17 and AC coupling capacitor C407 to U2.
6	DAT1+	HDMI_OUT_TX1_DP	✅	Data channel 1 positive signal correctly routed through common mode choke L16 and AC coupling capacitor C404 to U2.
7	DAT1_S	GND	✅	Data channel 1 shield correctly connected to ground.
8	DAT1-	HDMI_OUT_TX1_DN	✅	Data channel 1 negative signal correctly routed through common mode choke L16 and AC coupling capacitor C405 to U2.
9	DAT0+	HDMI_OUT_TX0_DP	✅	Data channel 0 positive signal correctly routed through common mode choke L15 and AC coupling capacitor C402 to U2.
10	DAT0_S	GND	✅	Data channel 0 shield correctly connected to ground.
11	DAT0-	HDMI_OUT_TX0_DN	✅	Data channel 0 negative signal correctly routed through common mode choke L15 and AC coupling capacitor C403 to U2.
12	CLK+	HDMI_OUT_CLK_DP	✅	Clock positive signal correctly routed through common mode choke L14 and AC coupling capacitor C400 to U2.
13	CLK_S	GND	✅	Clock shield correctly connected to ground.
14	CLK-	HDMI_OUT_CLK_DN	✅	Clock negative signal correctly routed through common mode choke L14 and AC coupling capacitor C401 to U2.
15	CEC	C_HDMI_CEC	✅	CEC signal correctly connected to U2 CEC_B pin for consumer electronics control.
16	DDC/CEC_GND	GND	✅	DDC/CEC ground correctly connected to system ground.
17	SCL	C_HDMI_SCL	✅	I2C clock signal correctly connected to U2 SCL_B pin for DDC communication.
18	SDA	C_HDMI_SDA	✅	I2C data signal correctly connected to U2 SDA_B pin for DDC communication.
19	+5V	D5_0V_HDMI	✅	5V power supply correctly provided from U2 charge pump output through ferrite bead L7.
20	MTG1	GND_EARTH	✅	Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection.
21	MTG2	GND_EARTH	✅	Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection.
22	MTG3	GND_EARTH	✅	Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection.
23	MTG4	GND_EARTH	✅	Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection.

Q101 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	HDMI_TERM	✅	Drain is connected to HDMI_TERM net, which connects to eight 619-ohm resistors (R801-R808) that provide DC bias restoration paths for HDMI differential pairs. This configuration is correct for providing a switchable ground reference for the HDMI signal termination network.
G	GATE	$15N747	✅	Gate is connected to +VCC3 power rail through 0-ohm resistor R809, making the MOSFET always ON when powered. This appears intentional for continuous DC bias restoration, though the adequacy depends on the +VCC3 voltage level being sufficient to fully enhance the MOSFET (ideally ≥2.5V).
S	SOURCE	GND	✅	Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch.

L7 - FERRITE_220OHM_2.2A_0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+HDMI_CRT_VCC	✅	Input terminal of ferrite bead connected to +HDMI_CRT_VCC, which is the 5V output from U2 (TPD12S016PW) charge pump. This connection provides EMI filtering for power supplied to the HDMI connector.
2	P2	D5_0V_HDMI	✅	Output terminal of ferrite bead connected to D5_0V_HDMI, which supplies filtered 5V power to the HDMI connector pin 19. The 2200mA current rating is appropriate for HDMI power delivery requirements.

FB13 - 3044-0012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input side of ferrite bead connected to +5VSB supply rail.
2	2	+USBVCC	✅	Output side of ferrite bead connected to +USBVCC, providing filtered power to USB power switch.

C92 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bypass capacitor ground connection.
2	2	+USBVCC	✅	Bypass capacitor power connection to +USBVCC rail.

C93 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bypass capacitor ground connection.
2	2	+USBVCC	✅	Bypass capacitor power connection to +USBVCC rail.

C94 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bypass capacitor ground connection.
2	2	+USBVCC	✅	Bypass capacitor power connection to +USBVCC rail.

U32 - AP2172MPG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	Ground pin correctly connected to GND net.
2	IN	+USBVCC	✅	Input power pin correctly connected to +USBVCC with adequate bypass capacitance.
3	EN1	USB_HOST_EN0	✅	Enable input for switch 1 correctly connected through level translator to SOC control signal.
4	EN2	USB_HOST_EN1	✅	Enable input for switch 2 correctly connected through level translator to SOC control signal.
5	OC2#	SOC_USB_HOST_OC1	✅	Open-drain overcurrent flag outputs correctly connected to SOC. External pull-up resistors are required by datasheet but not visible in this schematic section; they should be verified to exist at the SOC or elsewhere in the design.
8	OC1#	SOC_USB_HOST_OC0	✅	Open-drain overcurrent flag outputs correctly connected to SOC. External pull-up resistors are required by datasheet but not visible in this schematic section; they should be verified to exist at the SOC or elsewhere in the design.
6	OUTB	USBP2	✅	Switch 2 output correctly connected to USB port 2 power rail with appropriate filtering.
7	OUTA	USBP1	✅	Switch 1 output correctly connected to USB port 1 power rail with appropriate filtering.
9	GND_PAD	GND	✅	Exposed pad correctly connected to GND for thermal and electrical grounding.

U4 - NTS0102GT ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
7	VCCB	+USBVCC	❌	VCCB pin incorrectly connected to +USBVCC (approximately 5V), which exceeds the device's maximum voltage rating of 3.6V. This overvoltage condition could damage the device or cause malfunction. Pin 7 (VCCB) is connected to +USBVCC net (from schematic) The device voltage attribute specifies 1.2-3.6V operating range (from schematic) +USBVCC is derived from +5VSB through ferrite bead FB13 (from schematic) FB13 (part 3044-0012) is a ferrite bead inductor, not a voltage regulator, so +USBVCC voltage equals +5VSB voltage minus minimal resistive drop (from schematic) +5VSB is a 5V standby supply based on standard power supply naming conventions (reasoning) +USBVCC supplies U32 (AP2172MPG USB power switch) which has input voltage range 2.7V-5.5V, confirming +USBVCC is intended to be approximately 5V (from schematic) U32 outputs USBP1 and USBP2 connect through ferrite beads L1 and L2 to VBUS1 and VBUS2, which supply USB connector USB1 pins 1 and 10 (from schematic) USB VBUS specification requires 5V ±5% (4.75V-5.25V), therefore +USBVCC must be approximately 5V to provide proper USB power (reasoning) Connecting VCCB to a 5V supply exceeds the 3.6V maximum rating by 1.4V (39% overvoltage) (reasoning) This overvoltage condition violates the device absolute maximum ratings and could cause device damage, latchup, or unreliable operation (reasoning) Recommended fix: Add a 3.3V or 1.8V LDO regulator to power VCCB from +USBVCC or +5VSB, ensuring VCCB stays within the 1.2-3.6V specification (reasoning) Alternative fix: Replace NTS0102GT with a level translator that supports 5V on VCCB, such as TXS0102 or TXB0102 which support VCCB up to 5.5V (reasoning)
1	B2	USB_HOST_EN0	✅	B2 pin correctly connected to USB_HOST_EN0 net, which drives the EN1 input of USB power switch U32.
2	GND	GND	✅	GND pin correctly connected to ground plane.
3	VCCA	+V1P8A	✅	VCCA pin correctly connected to +V1P8A supply, providing 1.8V power for the A-side of the level translator.
4	A2	SOC_USB_HOST_EN0	✅	A2 pin correctly connected to SOC_USB_HOST_EN0, receiving 1.8V enable signal from SOC for USB port 0.
5	A1	SOC_USB_HOST_EN1	✅	A1 pin correctly connected to SOC_USB_HOST_EN1, receiving 1.8V enable signal from SOC for USB port 1.
6	OE	USB_HOST_BUFF_ENB	✅	OE pin correctly connected to USB_HOST_BUFF_ENB with pull-up resistor R116 to +V1P8A, enabling the level translator by default.
8	B1	USB_HOST_EN1	✅	B1 pin correctly connected to USB_HOST_EN1 net, which drives the EN2 input of USB power switch U32.

R116 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB_HOST_BUFF_ENB	✅	10K pull-up resistor correctly connected between USB_HOST_BUFF_ENB (pin 1) and +V1P8A (pin 2), providing default enable state for U4 level translator.
2	2	+V1P8A	✅	10K pull-up resistor correctly connected between USB_HOST_BUFF_ENB (pin 1) and +V1P8A (pin 2), providing default enable state for U4 level translator.

U29 - TPD4USB30 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D1+	USB3_TX0P_C	✅	D1+ provides ESD protection for the USB3 TX positive signal between the common mode choke and the connector.
2	D1-	USB3_TX0N_C	✅	D1- provides ESD protection for the USB3 TX negative signal between the common mode choke and the connector.
3	GND1	GND	✅	GND1 provides ground reference for ESD protection on the first differential pair.
4	D2+	USB3_RX0P_C	✅	D2+ provides ESD protection for the USB3 RX positive signal between the connector and the common mode choke.
5	D2-	USB3_RX0N_C	✅	D2- provides ESD protection for the USB3 RX negative signal between the connector and the common mode choke.
6	NC4	USB3_RX0N_C	✅	NC4 is connected to the USB3 RX negative signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected.
7	NC3	USB3_RX0P_C	✅	NC3 is connected to the USB3 RX positive signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected.
8	GND2	GND	✅	GND2 provides ground reference for ESD protection on the second differential pair.
9	NC2	USB3_TX0N_C	✅	NC2 is connected to the USB3 TX negative signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected.
10	NC1	USB3_TX0P_C	✅	NC1 is connected to the USB3 TX positive signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected.

C192 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_TXP0	✅	AC coupling capacitor for USB3 TX positive signal. The 0.1uF value is correct per USB 3.0 specification requirements.
2	2	USB3_TX0P-R	✅	AC coupling capacitor for USB3 TX positive signal. The 0.1uF value is correct per USB 3.0 specification requirements.

CHOKE1 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_RX0N_C	✅	IN1 receives the USB3 RX negative signal from the USB connector through ESD protection device U29.
3	IN2	USB3_RX0P_C	✅	IN2 receives the USB3 RX positive signal from the USB connector through ESD protection device U29.
4	OUT2	USB3_RXP0	✅	OUT2 outputs the filtered USB3 RX positive signal to the SOC.
6	OUT1	USB3_RXN0	✅	OUT1 outputs the filtered USB3 RX negative signal to the SOC.

C191 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_TXN0	✅	AC coupling capacitor for USB3 TX negative signal. The 0.1uF value is correct per USB 3.0 specification requirements.
2	2	USB3_TX0N-R	✅	AC coupling capacitor for USB3 TX negative signal. The 0.1uF value is correct per USB 3.0 specification requirements.

CHOKE2 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_TX0P-R	✅	IN1 carries the USB3 TX positive signal from the SOC through AC coupling capacitor C192 to the common mode choke input.
3	IN2	USB3_TX0N-R	✅	IN2 carries the USB3 TX negative signal from the SOC through AC coupling capacitor C191 to the common mode choke input.
4	OUT2	USB3_TX0N_C	✅	OUT2 outputs the USB3 TX negative signal to the ESD protection device U29 and ultimately to the USB connector.
6	OUT1	USB3_TX0P_C	✅	OUT1 outputs the USB3 TX positive signal to the ESD protection device U29 and ultimately to the USB connector.

U9 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H0	✅	D+ pin is connected to USB_H0, providing ESD protection for the USB D+ data line between the common mode choke and the USB connector.
2	D-	USB_L0	✅	D- pin is connected to USB_L0, providing ESD protection for the USB D- data line between the common mode choke and the USB connector.
3	ID		✅	ID pin is left unconnected. This is acceptable for USB host-only applications where the ID pin is not used.
4	GND	GND	✅	GND pin is correctly connected to the system ground net.
5	NC		✅	NC pin is not connected, which is correct as this pin is not internally connected per the datasheet.
6	VBUS	VBUS1	✅	VBUS pin is connected to VBUS1, providing ESD protection for the USB power line. The power flows from the power switch through a ferrite bead to this ESD protection device and then to the USB connector.

CHOKE4 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN0	✅	IN1 is connected to USB_DN0, which is the USB D- signal from the SOC side. This pin is the input for the negative differential signal of the common mode choke.
3	IN2	USB_DP0	✅	IN2 is connected to USB_DP0, which is the USB D+ signal from the SOC side. This pin is the input for the positive differential signal of the common mode choke.
4	OUT2	USB_H0	✅	OUT2 is connected to USB_H0, which routes to the ESD protection device U9 and then to the USB connector. This is the output for the positive differential signal.
6	OUT1	USB_L0	✅	OUT1 is connected to USB_L0, which routes to the ESD protection device U9 and then to the USB connector. This is the output for the negative differential signal.

U8 - TPD4S012 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H1	✅	D+ pin is connected to USB_H1, providing ESD protection for the D+ data line of USB Port B.
2	D-	USB_L1	✅	D- pin is connected to USB_L1, providing ESD protection for the D- data line of USB Port B.
3	ID		✅	ID pin is left floating, which is acceptable per the datasheet for applications where the ID pin is not used.
4	GND	GND	✅	GND pin is correctly connected to the ground net.
5	NC		✅	NC pin is correctly left unconnected as it is not internally connected per the datasheet.
6	VBUS	VBUS2	✅	VBUS pin is connected to VBUS2, providing ESD protection for the VBUS line of USB Port B.

CHOKE3 - 3142-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN1	✅	IN1 is connected to USB_DN1, which is the D- input signal for USB Port B. This signal passes through the common mode choke and exits on pin 6 as USB_L1.
3	IN2	USB_DP1	✅	IN2 is connected to USB_DP1, which is the D+ input signal for USB Port B. This signal passes through the common mode choke and exits on pin 4 as USB_H1.
4	OUT2	USB_H1	✅	OUT2 is connected to USB_H1, which is the D+ output signal. This connects to the ESD protection device U8 pin 1 and then to the USB connector.
6	OUT1	USB_L1	✅	OUT1 is connected to USB_L1, which is the D- output signal. This connects to the ESD protection device U8 pin 2 and then to the USB connector.

L1 - 126-0004781 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP1	✅	Connected to USBP1, which is the output of USB power switch U32 pin 7 (OUTA). This is the input side of the ferrite bead filter.
2	2	VBUS1	✅	Connected to VBUS1, which supplies power to USB port A. This is the output side of the ferrite bead, providing filtered power to the USB connector and decoupling capacitors.

C91 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bulk decoupling capacitor (22uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing bulk capacitance for USB port A power supply.
2	2	VBUS1	✅	Bulk decoupling capacitor (22uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing bulk capacitance for USB port A power supply.

C70 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply.
2	2	VBUS2	✅	High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply.

C82 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply.
2	2	VBUS1	✅	High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply.

C234 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply.
2	2	VBUS2	✅	High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply.

C235 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply.
2	2	VBUS1	✅	High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply.

C103 - 123-0001176 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net for bulk decoupling capacitor reference.
2	2	VBUS2	✅	Connected to VBUS2 net, providing bulk capacitance for USB port B power rail.

USB1 - 258-0004503 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUSA	VBUS1	✅	VBUSA provides power to USB port A. Connected to VBUS1 with proper power switching, ESD protection, ferrite bead filtering, and decoupling capacitors.
2	DA-	USB_L0	✅	DA- is the USB 2.0 D- signal for port A. Connected to USB_L0 with proper ESD protection and common mode filtering.
3	DA+	USB_H0	✅	DA+ is the USB 2.0 D+ signal for port A. Connected to USB_H0 with proper ESD protection and common mode filtering.
4	GNDA	GND	✅	GNDA is the ground connection for USB port A, correctly connected to system ground.
5	SSRX-	USB3_RX0N_C	✅	SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected to USB3_RX0N_C with proper ESD protection and common mode filtering.
6	SSRX+	USB3_RX0P_C	✅	SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected to USB3_RX0P_C with proper ESD protection and common mode filtering.
7	GND_DRAIN	GND	✅	GND_DRAIN is the ground drain connection, correctly connected to system ground.
8	SSTX-	USB3_TX0N_C	✅	SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected to USB3_TX0N_C with proper ESD protection, common mode filtering, and AC coupling.
9	SSTX+	USB3_TX0P_C	✅	SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected to USB3_TX0P_C with proper ESD protection, common mode filtering, and AC coupling.
10	VBUSB	VBUS2	✅	VBUSB provides power to USB port B. Connected to VBUS2 with proper power switching, ESD protection, ferrite bead filtering, and decoupling capacitors.
11	DB-	USB_L1	✅	DB- is the USB 2.0 D- signal for port B. Connected to USB_L1 with proper ESD protection and common mode filtering.
12	DB+	USB_H1	✅	DB+ is the USB 2.0 D+ signal for port B. Connected to USB_H1 with proper ESD protection and common mode filtering.
13	GNDB	GND	✅	GNDB is the ground connection for USB port B, correctly connected to system ground.
MH1	SHIELD1	GND_EARTH	✅	Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity.
MH2	SHIELD2	GND_EARTH	✅	Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity.
MH3	SHIELD3	GND_EARTH	✅	Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity.
MH4	SHIELD4	GND_EARTH	✅	Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity.

J10 - 158-0004534 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
2	2	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
13	13	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
14	14	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
25	25	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
26	26	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
37	37	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
38	38	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
49	49	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
50	50	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
59	59	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
60	60	GND	✅	Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors.
3	3	mSATA_TX_P	✅	mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5). Standard differential signaling for SATA interface.
5	5	mSATA_TX_N	✅	mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5). Standard differential signaling for SATA interface.
4	4	mSATA_RX_P	✅	mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6). Standard differential signaling for SATA interface.
6	6	mSATA_RX_N	✅	mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6). Standard differential signaling for SATA interface.
7	7	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
8	8	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
19	19	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
20	20	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
31	31	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
32	32	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
43	43	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
44	44	+5VSB	✅	Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution.
9	9	mPCIE_REFCLK_P	✅	mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11). Provides clock reference for PCIe interface.
11	11	mPCIE_REFCLK_N	✅	mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11). Provides clock reference for PCIe interface.
10	10	USB_HOST_DP	✅	USB host differential pair (DP on pin 10, DN on pin 12). Standard USB 2.0 signaling.
12	12	USB_HOST_DN	✅	USB host differential pair (DP on pin 10, DN on pin 12). Standard USB 2.0 signaling.
15	15	mPCIE_TX_P	✅	mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17). Standard differential signaling for PCIe interface.
17	17	mPCIE_TX_N	✅	mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17). Standard differential signaling for PCIe interface.
16	16	mPCIE_RX_N	✅	mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18). A schematic note explicitly states this inversion is for ease of layout routing.
18	18	mPCIE_RX_P	✅	mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18). A schematic note explicitly states this inversion is for ease of layout routing.
21	21	I2C6_SCL	✅	I2C bus signals (SCL on pin 21, SDA on pin 23) with proper 10K pull-up resistors to +V1P8S. Standard I2C configuration.
23	23	I2C6_SDA	✅	I2C bus signals (SCL on pin 21, SDA on pin 23) with proper 10K pull-up resistors to +V1P8S. Standard I2C configuration.
22	22	mPCIE_WAKEB	✅	mPCIE wake signal (active low). Used to wake the system from low power states.
24	24	mPCIe_CLKREQ3_B	✅	mPCIE clock request signal (active low). Used for PCIe clock power management.
27	27	EXP_GPIO1	✅	Expansion GPIO signals providing general-purpose I/O capability through the connector.
28	28	EXP_GPIO3	✅	Expansion GPIO signals providing general-purpose I/O capability through the connector.
29	29	EXP_GPIO2	✅	Expansion GPIO signals providing general-purpose I/O capability through the connector.
30	30	EXP_GPIO4	✅	Expansion GPIO signals providing general-purpose I/O capability through the connector.
33	33	XDP_H_OBSDATA_A1	✅	XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface.
34	34	XDP_H_OBSDATA_A0	✅	XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface.
35	35	XDP_H_OBSDATA_A2	✅	XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface.
36	36	XDP_H_OBSDATA_A3	✅	XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface.
39	39	XDP_H_PRDYB	✅	XDP probe ready signal (active low). Indicates debug probe is ready.
40	40	XDP_H_PREQB_PB	✅	XDP probe request signal (active low) buffered through U1 with a 200 ohm pull-up. The low pull-up value may be intentional for XDP timing requirements.
41	41	HOOK0	✅	HOOK0 signal connected to PMC_RSMRST through 1K series resistor R15. Provides resume reset signal to expansion connector.
42	42	HOOK1	✅	HOOK1 signal connected to FP_PWRBTN through 0 ohm jumper R5. Optional 4.7K pull-down R4 is DNI.
45	45	HOOK2	✅	HOOK2 signal connected to PMC_CORE_PWROK through 1K series resistor R16. Provides core power good signal to expansion connector.
46	46	PMC_RSTBTN	✅	PMC reset button signal with 1K pull-up to +V1P8S and 0.1uF filter capacitor. Standard reset button configuration.
47	47	HOOK6	✅	HOOK6 signal connected to PMC_PLTRST_R_V1P8 through 1K series resistor R17. Provides platform reset signal to expansion connector.
48	48	ILB_RTC_TESTB	✅	RTC test signal (active low) with 1K pull-up to +RTCVCC and 1uF filter capacitor. Standard test pin configuration.
51	51	HOOK4	✅	HOOK4 signal connected to +3VSB through 0 ohm jumper R18. Provides 3.3V standby power to expansion connector.
52	52	XDP_H_TRSTB	✅	XDP test reset signal (active low). Part of JTAG-like debug interface.
53	53	HOOK5	✅	HOOK5 signal connected to +V1P8S through 0 ohm jumper R20. Provides 1.8V standby power to expansion connector.
54	54	XDP_H_TCK	✅	XDP test clock signal. Part of JTAG-like debug interface.
55	55	+V1P8A	✅	Power supply pin providing +V1P8A (1.8V analog power). This pin supplies power for 1.8V level signals on the expansion connector.
56	56	XDP_H_TMS	✅	XDP test mode select signal. Part of JTAG-like debug interface.
57	57	XDP_H_TDO	✅	XDP test data out signal with 51 ohm pull-up to +V1P8A. The unusually low pull-up value may be a design concern or intentional for specific XDP requirements.
58	58	XDP_H_TDI	✅	XDP test data in signal. Part of JTAG-like debug interface.

R3 - 200 ohm 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XDP_H_PREQB_PB	✅	Pull-up resistor providing 200 ohm resistance between XDP_H_PREQB_PB signal (pin 1) and +V1P8A power rail (pin 2), ensuring defined input state for buffer U1.
2	2	+V1P8A	✅	Pull-up resistor providing 200 ohm resistance between XDP_H_PREQB_PB signal (pin 1) and +V1P8A power rail (pin 2), ensuring defined input state for buffer U1.

R21 - 51 OHM 1% 1/10W 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pull-up resistor providing 51 ohm resistance between +V1P8A power rail (pin 1) and XDP_H_TDO signal (pin 2). The unusually low resistance value appears intentional for signal integrity on the high-speed XDP debug interface.
2	2	XDP_H_TDO	✅	Pull-up resistor providing 51 ohm resistance between +V1P8A power rail (pin 1) and XDP_H_TDO signal (pin 2). The unusually low resistance value appears intentional for signal integrity on the high-speed XDP debug interface.

C5 - 0.1uF 10% 25V 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bypass/decoupling capacitor correctly connected between GND (pin 1) and +V1P8A power rail (pin 2), providing power supply decoupling for U1 as recommended by the datasheet.
2	2	+V1P8A	✅	Bypass/decoupling capacitor correctly connected between GND (pin 1) and +V1P8A power rail (pin 2), providing power supply decoupling for U1 as recommended by the datasheet.

U1 - SN74AUP1G34 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin is correctly left unconnected as specified in the datasheet.
2	A	XDP_H_PREQB_PB	✅	Input A is correctly connected to XDP_H_PREQB_PB signal from connector J10 pin 40, with a 200 ohm pull-up resistor (R3) to +V1P8A providing a defined logic level.
3	GND	GND	✅	Ground pin is correctly connected to the GND net.
4	Y	XDP_H_PREQB	✅	Output Y is correctly connected to net XDP_H_PREQB, providing the buffered version of the input signal.
5	VCC	+V1P8A	✅	VCC pin is correctly connected to +V1P8A (1.8V supply) with proper bypass capacitor C5 (0.1uF) for decoupling.

R13 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SCL	✅	Pin 1 connects to I2C6_SCL signal line, which goes to expansion connector J10 pin 21. This is one side of the I2C pull-up resistor.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C6_SCL line. The 10K ohm value is appropriate for I2C pull-up at 1.8V.

R14 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SDA	✅	Pin 1 connects to I2C6_SDA signal line, which goes to expansion connector J10 pin 23. This is one side of the I2C pull-up resistor.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C6_SDA line. The 10K ohm value is appropriate for I2C pull-up at 1.8V.

U42 - WGI210AT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	LAN_PWR_GOOD	$18N3538	✅	LAN_PWR_GOOD output with 10K pull-up to +3VSB_LAN through R828. This is a power good indicator signal.
2	NC_SI_CLK_IN	$18N3372	✅	NC_SI interface pins (CLK_IN, CRS_DV, TX_EN) pulled to GND through 1K resistors. These unused serial interface pins are terminated to a known state.
3	NC_SI_CRS_DV	$18N3374	✅	NC_SI interface pins (CLK_IN, CRS_DV, TX_EN) pulled to GND through 1K resistors. These unused serial interface pins are terminated to a known state.
7	NC_SI_TX_EN	$18N3376	✅	NC_SI interface pins (CLK_IN, CRS_DV, TX_EN) pulled to GND through 1K resistors. These unused serial interface pins are terminated to a known state.
4	JTAG_TDO		✅	JTAG_TDO is left unconnected. This is acceptable when JTAG debugging is not used.
5	NC_SI_RXD1	$18N3305	✅	NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state.
6	NC_SI_RXD0	$18N3303	✅	NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state.
8	NC_SI_TXD1	$18N3301	✅	NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state.
9	NC_SI_TXD0	$18N3299	✅	NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state.
10	VDD3P3_10	+3VSB_LAN	✅	VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors.
27	VDD3P3_27	+3VSB_LAN	✅	VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors.
41	VDD3P3_41	+3VSB_LAN	✅	VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors.
51	VDD3P3_51	+3VSB_LAN	✅	VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors.
64	VDD3P3_64	+3VSB_LAN	✅	VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors.
11	VDD0P9_11	+0V9_LAN	✅	VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors.
32	VDD0P9_32	+0V9_LAN	✅	VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors.
42	VDD0P9_42	+0V9_LAN	✅	VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors.
59	VDD0P9_59	+0V9_LAN	✅	VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors.
12	NVM_SI	$18N2399	✅	NVM_SI (SPI MOSI) connects to flash memory U43 pin 5 through 33.2 ohm series resistor R832 for signal integrity.
13	NVM_SK	$18N2397	✅	NVM_SK (SPI Clock) connects to flash memory U43 pin 6 through 33.2 ohm series resistor R834 for signal integrity.
14	NVM_SO	$18N3554	✅	NVM_SO (SPI MISO) connects to flash memory U43 pin 2 through 33.2 ohm series resistor R833 for signal integrity.
15	NVM_CS_N	$18N2395	✅	NVM_CS_N (SPI Chip Select) connects to flash memory U43 pin 1 through 33.2 ohm series resistor R835 for signal integrity.
16	PE_WAKE_N	PMC_PCIE_WAKE	✅	PE_WAKE_N connects to PMC_PCIE_WAKE for PCIe wake signaling.
17	PE_RST_N	PMC_PLTRST_L	✅	PE_RST_N connects to PMC_PLTRST_L for PCIe reset signaling.
18	JTAG_TMS	$18N3293	✅	JTAG_TMS with 10K pull-up to +3VSB_LAN through R820. Correct termination for unused JTAG.
19	JTAG_CLK	$18N3295	✅	JTAG_CLK with 10K pull-up to +3VSB_LAN through R821. Correct termination for unused JTAG.
20	PE_TXN	PCIE_C_RXP2	✅	PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification.
21	PE_TXP	PCIE_C_RXN2	✅	PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification.
23	PE_RXN	PCIE_C_TXP2	✅	PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification.
24	PE_RXP	PCIE_C_TXN2	✅	PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification.
22	NC/INTVCC		✅	NC/INTVCC pin is left unconnected. This is likely an internal voltage or no-connect pin.
25	PECLK_N	PCIE_CLK-N2	✅	PECLK_N and PECLK_P are the PCIe reference clock differential pair inputs, connected to PCIE_CLK-N2 and PCIE_CLK-P2 respectively.
26	PECLK_P	PCIE_CLK-P2	✅	PECLK_N and PECLK_P are the PCIe reference clock differential pair inputs, connected to PCIE_CLK-N2 and PCIE_CLK-P2 respectively.
28	DEV_OFF_N	$18N3540	✅	DEV_OFF_N with 10K pull-up to +3VSB_LAN through R827. This keeps the device enabled by default.
29	JTAG_TDI	$18N3297	✅	JTAG_TDI with 10K pull-up to +3VSB_LAN through R822. Correct termination for unused JTAG.
30	LED1	LAN-LED1	✅	LED1 output drives LINK-LED-N through 301 ohm current limiting resistor R843 to control LED in RJ45 connector J11.
31	LED0	LAN-LED0	✅	LED0 output connects to RJ45 connector J11 pin 11 for differential LED drive with LED2.
33	LED2	LAN-LED2	✅	LED2 output drives 1G-LED-N through 301 ohm current limiting resistor R844 to control LED in RJ45 connector J11.
34	SMB_CLK	LAN-SMB-CLK	✅	SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected to system SMBus signals for management interface.
35	SMB_ALRT_N	LAN-SMB-ALERT#	✅	SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected to system SMBus signals for management interface.
36	SMB_DATA	LAN-SMB-DATA	✅	SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected to system SMBus signals for management interface.
37	CBOT	$18N2590	✅	CBOT and CTOP pins connected through 0.039uF capacitor C425 for internal charge pump or regulator.
40	CTOP	$18N2588	✅	CBOT and CTOP pins connected through 0.039uF capacitor C425 for internal charge pump or regulator.
38	VDD0P9_OUT	+0V9_LAN	✅	VDD0P9_OUT is the internal 0.9V regulator output, correctly connected to +0V9_LAN rail.
39	VDD1P5_OUT	+1V5_LAN	✅	VDD1P5_OUT is the internal 1.5V regulator output, correctly connected to +1V5_LAN rail.
43	NC_SI_ARB_IN		✅	NC_SI_ARB_IN and NC_SI_ARB_OUT are left unconnected. These are unused serial interface arbitration pins.
44	NC_SI_ARB_OUT		✅	NC_SI_ARB_IN and NC_SI_ARB_OUT are left unconnected. These are unused serial interface arbitration pins.
45	XTAL2	LAN_XTAL2	✅	XTAL2 and XTAL1 connect to 25MHz crystal X1 with appropriate 27pF load capacitors C252 and C253.
46	XTAL1	LAN_XTAL1	✅	XTAL2 and XTAL1 connect to 25MHz crystal X1 with appropriate 27pF load capacitors C252 and C253.
47	VDD1P5_47	+1V5_LAN	✅	VDD1P5 power supply pins correctly connected to +1V5_LAN with adequate decoupling capacitors.
56	VDD1P5_56	+1V5_LAN	✅	VDD1P5 power supply pins correctly connected to +1V5_LAN with adequate decoupling capacitors.
48	RSET	LAN_RSET	✅	RSET pin connected to GND through 4.99K resistor R836 to set internal reference currents.
49	MDI_MINUS3/SER_N	MDI_N3	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
50	MDI_PLUS3/SER_P	MDI_P3	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
52	MDI_MINUS2/SET_N	MDI_N2	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
53	MDI_PLUS2	MDI_P2	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
54	MDI_MINUS1/SRDS_SIG_DET	MDI_N1	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
55	MDI_PLUS1/SFP_I2C_CLK	MDI_P1	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
57	MDI_MINUS0/SFP_I2C_DATA	MDI_N0	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
58	MDI_PLUS0/NC	MDI_P0	✅	MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface.
60	SDP3		✅	SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs.
61	SDP1/PCIE_DIS		✅	SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs.
62	SDP2		✅	SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs.
63	SDP0		✅	SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs.
65	GND_PAD	GND	✅	GND_PAD correctly connected to GND for thermal and electrical grounding of QFN package.

R832 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2435	✅	Connected to U43 pin 5 (SI) on net $18N2435. This is the flash memory side of the series resistor on the SPI MOSI line.
2	2	$18N2399	✅	Connected to U42 pin 12 (NVM_SI) on net $18N2399. This is the controller side of the series resistor on the SPI MOSI line.

R833 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3554	✅	Connected to U42 pin 14 (NVM_SO) on net $18N3554. This is the controller side of the series resistor on the SPI MISO line.
2	2	$18N3552	✅	Connected to U43 pin 2 (SO) on net $18N3552. This is the flash memory side of the series resistor on the SPI MISO line.

R834 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2437	✅	Connected to U43 pin 6 (SCK) on net $18N2437. This is the flash memory side of the series resistor on the SPI clock line.
2	2	$18N2397	✅	Connected to U42 pin 13 (NVM_SK) on net $18N2397. This is the controller side of the series resistor on the SPI clock line.

R835 - 1120-0003 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2439	✅	Connected to U43 pin 1 (CS#) on net $18N2439. This is the flash memory side of the series resistor on the SPI chip select line.
2	2	$18N2395	✅	Connected to U42 pin 15 (NVM_CS_N) on net $18N2395. This is the controller side of the series resistor on the SPI chip select line.

R829 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3609	✅	Connected to U43 pin 3 (WP#) on net $18N3609. This DNI resistor would pull WP# to ground if installed, enabling hardware write protection.
2	2	GND	✅	Connected to GND. This DNI resistor would pull WP# to ground if installed.

R830 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Connected to +3VSB_LAN. This resistor pulls U43 pin 3 (WP#) high to disable hardware write protection.
2	2	$18N3609	✅	Connected to U43 pin 3 (WP#) on net $18N3609. This pull-up resistor disables hardware write protection as recommended by the datasheet.

R831 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Connected to +3VSB_LAN. This resistor pulls U43 pin 7 (HOLD#) high to disable the hold function.
2	2	$18N3659	✅	Connected to U43 pin 7 (HOLD#) on net $18N3659. This pull-up resistor disables the hold function as recommended by the datasheet.

U43 - AT25DF081A-SSH ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	$18N2439	✅	CS# (Chip Select) is correctly connected to the Ethernet controller U42 through series resistor R835.
2	SO	$18N3552	✅	SO (Serial Output) is correctly connected to the Ethernet controller U42 through series resistor R833.
3	WP#	$18N3609	✅	WP# (Write Protect) is correctly pulled high through R830 (10KΩ) to disable hardware write protection, following datasheet recommendations.
4	GND	GND	✅	GND is correctly connected to the system ground plane.
5	SI	$18N2435	✅	SI (Serial Input) is correctly connected to the Ethernet controller U42 through series resistor R832, with a weak pull-up through R848.
6	SCK	$18N2437	✅	SCK (Serial Clock) is correctly connected to the Ethernet controller U42 through series resistor R834.
7	HOLD#	$18N3659	✅	HOLD# is correctly pulled high through R831 (10KΩ) to disable the hold function, following datasheet recommendations.
8	VCC	+3VSB_LAN	✅	VCC is correctly connected to +3VSB_LAN (3.3V standby power), which is within the specified operating voltage range.

J11 - 3362-0042 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
11	LED2_AC1	LAN-LED0	❌	LED2_AC1 connects directly to U42 LED0 output (pin 31) without a current limiting resistor, unlike the other LED outputs which have 301Ω resistors. This asymmetry indicates a likely missing component in the design. Pin 11 (LED2_AC1) connects to net LAN-LED0 (from schematic) LAN-LED0 connects directly to U42 pin 31 (LED0 output) (from schematic) No current limiting resistor exists between U42 pin 31 and J11 pin 11 (from schematic) U42 pin 30 (LED1) connects through R843 (301Ω) to LINK-LED-N and then to J11 pin 13 (from schematic) U42 pin 33 (LED2) connects through R844 (301Ω) to 1G-LED-N and then to J11 pin 12 (from schematic) C431 (560pF) provides EMI filtering on the LAN-LED0 signal (from schematic) The WGI210AT (U42) is an Intel Ethernet controller whose LED outputs are typically open-drain and require external current limiting resistors (reasoning) The asymmetry in the design (two LED outputs have current limiting resistors, one does not) is inconsistent with standard LED drive practices and indicates a likely missing component (reasoning) Without a current limiting resistor, excessive current could flow through the LED or damage the U42 output driver (reasoning) A resistor similar to R843 and R844 (approximately 301Ω) should be added in series between U42 pin 31 and J11 pin 11 (reasoning)
1	MD1+	MDI_P0	✅	MDI pair 0 (MD1+/MD1-) correctly connected to U42 pins 58/57 for Ethernet differential signaling.
2	MD1-	MDI_N0	✅	MDI pair 0 (MD1+/MD1-) correctly connected to U42 pins 58/57 for Ethernet differential signaling.
3	MD2+	MDI_P1	✅	MDI pair 1 (MD2+/MD2-) correctly connected to U42 pins 55/54 for Ethernet differential signaling.
4	MD2-	MDI_N1	✅	MDI pair 1 (MD2+/MD2-) correctly connected to U42 pins 55/54 for Ethernet differential signaling.
5	CT1	$18N3856	✅	Center tap pins correctly tied together and bypassed to ground through C426, C427, and C428 for common-mode filtering.
6	CT2	$18N3856	✅	Center tap pins correctly tied together and bypassed to ground through C426, C427, and C428 for common-mode filtering.
7	MD3+	MDI_P2	✅	MDI pair 2 (MD3+/MD3-) correctly connected to U42 pins 53/52 for Ethernet differential signaling.
8	MD3-	MDI_N2	✅	MDI pair 2 (MD3+/MD3-) correctly connected to U42 pins 53/52 for Ethernet differential signaling.
9	MD4+	MDI_P3	✅	MDI pair 3 (MD4+/MD4-) correctly connected to U42 pins 50/49 for Ethernet differential signaling.
10	MD4-	MDI_N3	✅	MDI pair 3 (MD4+/MD4-) correctly connected to U42 pins 50/49 for Ethernet differential signaling.
12	LED2_AD1	1G-LED-N	✅	LED2_AD1 connects through R844 (301Ω) to U42 LED2 output, providing proper current limiting for the LED signal.
13	LED1_C	LINK-LED-N	✅	LED1 cathode correctly connected through R843 to U42 LED1 output for active-low LED drive with proper current limiting.
14	LED1_A	+3VSB_LAN	✅	LED1 anode correctly connected to +3VSB_LAN power supply for LED operation.
15	SHLD1	GND_EARTH	✅	Shield pins correctly connected to GND_EARTH for EMI/ESD protection with proper isolation from circuit ground.
16	SHLD2	GND_EARTH	✅	Shield pins correctly connected to GND_EARTH for EMI/ESD protection with proper isolation from circuit ground.

R843 - 1120-0203 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED1	✅	301Ω current-limiting resistor between U42 LED1 output and J11 LED1_C pin for link status LED indication.
2	2	LINK-LED-N	✅	301Ω current-limiting resistor between U42 LED1 output and J11 LED1_C pin for link status LED indication.

R844 - 1120-0203 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED2	✅	301Ω current-limiting resistor between U42 LED2 output and J11 LED2_AD1 pin for speed/activity LED indication.
2	2	1G-LED-N	✅	301Ω current-limiting resistor between U42 LED2 output and J11 LED2_AD1 pin for speed/activity LED indication.

C429 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LINK-LED-N	✅	560pF filter capacitor on LINK-LED-N signal for EMI suppression on the LED1 cathode line.
2	2	GND	✅	560pF filter capacitor on LINK-LED-N signal for EMI suppression on the LED1 cathode line.

C430 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1G-LED-N	✅	560pF filter capacitor on 1G-LED-N signal for EMI suppression on the LED2 cathode line.
2	2	GND	✅	560pF filter capacitor on 1G-LED-N signal for EMI suppression on the LED2 cathode line.

C431 - 2220-0039 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED0	✅	560pF filter capacitor on LAN-LED0 signal for EMI suppression. Note that the LAN-LED0 signal path lacks a current limiting resistor (see J11 pin 11 analysis).
2	2	GND	✅	560pF filter capacitor on LAN-LED0 signal for EMI suppression. Note that the LAN-LED0 signal path lacks a current limiting resistor (see J11 pin 11 analysis).

X1 - 145-0004792 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Crystal terminal connected to XTAL2 pin of U42 through LAN_XTAL2 net, with load capacitor C253 to ground.
2	2	GND	✅	Ground connection for mechanical stability and EMI reduction.
3	3	LAN_XTAL1	✅	Crystal terminal connected to XTAL1 pin of U42 through LAN_XTAL1 net, with load capacitor C252 to ground.
4	4	GND	✅	Ground connection for mechanical stability and EMI reduction.

C253 - 123-0001107 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Load capacitor connected to XTAL2 pin of U42 for crystal oscillator circuit.
2	2	GND	✅	Ground connection for load capacitor.

C252 - 123-0001107 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL1	✅	Load capacitor connected to XTAL1 pin of U42 for crystal oscillator circuit.
2	2	GND	✅	Ground connection for load capacitor.

R836 - 1120-0018 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing ground reference for the RSET resistor.
2	2	LAN_RSET	✅	Connected to LAN_RSET net, which connects to pin 48 (RSET) of U42 (WGI210AT). This sets an internal reference or bias current for the LAN controller.

C425 - 2221-0017 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2588	✅	Connected to net $18N2588, which connects to pin 40 (CTOP) of U42. This is one terminal of an external capacitor required by the LAN controller IC.
2	2	$18N2590	✅	Connected to net $18N2590, which connects to pin 37 (CBOT) of U42. This is the other terminal of the external capacitor, completing the CTOP-CBOT capacitor configuration.

FB12 - 3044-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB	✅	Input pin connected to +3VSB standby power rail, providing the source voltage for filtering.
2	2	+3VSB_LAN	✅	Output pin connected to +3VSB_LAN, providing filtered power to the Ethernet subsystem including U42 and U43.

C426 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Connected to Ethernet magnetics center tap network ($18N3856) along with C427 and C428. Provides AC bypass and common-mode filtering for the center taps.
2	2	GND	✅	Connected to GND, providing the return path for center tap bypass network.

C427 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Connected to Ethernet magnetics center tap network ($18N3856) in parallel with C426 and C428. Provides AC bypass and common-mode filtering.
2	2	GND	✅	Connected to GND, providing the return path for center tap bypass network.

C428 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Connected to Ethernet magnetics center tap network ($18N3856) in parallel with C426 and C427. The larger 1.0uF value provides lower frequency filtering.
2	2	GND	✅	Connected to GND, providing the return path for center tap bypass network.

R828 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connection to +3VSB_LAN power rail. This provides the pull-up voltage for the LAN_PWR_GOOD signal.
2	2	$18N3538	✅	Connected to LAN_PWR_GOOD signal (U42 pin 1). This pull-up resistor is typically used to pull the power good input high, indicating stable power supply conditions to the LAN controller.

R827 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Pull-up resistor connection to +3VSB_LAN power rail. This provides the pull-up voltage for the DEV_OFF_N signal.
2	2	$18N3540	✅	Connected to DEV_OFF_N signal (U42 pin 28). This pull-up resistor keeps the active-low device off signal high (inactive) by default, ensuring the LAN controller remains enabled.

U7 - NTS0102GT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	UART2_RXD	✅	B2 pin connected to UART2_RXD net, which goes to connector JP1 pin 19. This is the 3.3V side receive data line for UART2.
2	GND	GND	✅	GND pin correctly connected to ground net.
3	VCCA	+V1P8S	✅	VCCA pin connected to +V1P8S (1.8V supply) with proper decoupling capacitor C350.
4	A2	SIO_UART2_RXD	✅	A2 pin connected to SIO_UART2_RXD from the SOC. This is the 1.8V side receive data line for UART2.
5	A1	SIO_UART2_TXD	✅	A1 pin connected to SIO_UART2_TXD from the SOC. This is the 1.8V side transmit data line for UART2.
6	OE	PMC_PLTRST_R_V1P8	✅	OE pin connected to PMC_PLTRST_R_V1P8, which controls the translator enable based on platform reset.
7	VCCB	+3VSB	✅	VCCB pin connected to +3VSB (3.3V standby supply) with proper decoupling capacitor C351.
8	B1	UART2_TXD	✅	B1 pin connected to UART2_TXD net, which goes to connector JP1 pin 17. This is the 3.3V side transmit data line for UART2.

U15 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA pin connected to +V1P8S (1.8V supply) with proper decoupling capacitor C356.
2	A1	SIO_UART1_RTSB	✅	A1 pin connected to SIO_UART1_RTSB from the SOC. This is the 1.8V side RTS signal for UART1.
3	A2	SIO_UART1_CTSB	✅	A2 pin connected to SIO_UART1_CTSB from the SOC. This is the 1.8V side CTS signal for UART1.
4	A3	SIO_UART1_RXD	✅	A3 pin connected to SIO_UART1_RXD from the SOC. This is the 1.8V side receive data line for UART1.
5	A4	SIO_UART1_TXD	✅	A4 pin connected to SIO_UART1_TXD from the SOC. This is the 1.8V side transmit data line for UART1.
6	GND	GND	✅	GND pin correctly connected to ground net.
7	B4	UART1_TXD	✅	B4 pin connected to UART1_TXD net, which goes to connector JP1 pin 6. This is the 3.3V side transmit data line for UART1.
8	B3	UART1_RXD	✅	B3 pin connected to UART1_RXD net, which goes to connector JP1 pin 8. This is the 3.3V side receive data line for UART1.
9	B2	UART1_CTSB	✅	B2 pin connected to UART1_CTSB net, which goes to connector JP1 pin 10. This is the 3.3V side CTS signal for UART1.
10	B1	UART1_RTSB	✅	B1 pin connected to UART1_RTSB net, which goes to connector JP1 pin 12. This is the 3.3V side RTS signal for UART1.
11	VCCB	+3VSB	✅	VCCB pin connected to +3VSB (3.3V standby supply) with proper decoupling capacitor C357.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin connected to PMC_PLTRST_R_V1P8, which controls the translator enable based on platform reset.

U14 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S, providing the 1.8V reference voltage for the A-side of the level translator.
2	A1	SOC_SIO_SPI_CLK	✅	A1 is correctly connected to SOC_SIO_SPI_CLK, translating the 1.8V SPI clock signal to 3.3V on B1.
3	A2	SOC_SIO_SPI_MOSI	✅	A2 is correctly connected to SOC_SIO_SPI_MOSI, translating the 1.8V SPI MOSI signal to 3.3V on B2.
4	A3	SOC_SIO_SPI_MISO	✅	A3 is correctly connected to SOC_SIO_SPI_MISO, translating the 1.8V SPI MISO signal to 3.3V on B3.
5	A4	SOC_SIO_SPI_CS1	✅	A4 is correctly connected to SOC_SIO_SPI_CS1, translating the 1.8V SPI chip select signal to 3.3V on B4.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	SIO_SPI_CS1	✅	B4 is correctly connected to SIO_SPI_CS1, providing the 3.3V translated chip select signal.
8	B3	SIO_SPI_MISO	✅	B3 is correctly connected to SIO_SPI_MISO, providing the 3.3V translated MISO signal.
9	B2	SIO_SPI_MOSI	✅	B2 is correctly connected to SIO_SPI_MOSI, providing the 3.3V translated MOSI signal.
10	B1	SIO_SPI_CLK	✅	B1 is correctly connected to SIO_SPI_CLK, providing the 3.3V translated clock signal.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB, providing the 3.3V reference voltage for the B-side of the level translator.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset.

U17 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S, providing the reference voltage for the A-side I/O pins.
2	A1	I2S_MCLK	✅	A1 is correctly connected to I2S_MCLK, translating this 1.8V signal to 3.3V on B1.
3	A2	SOC_PWM1	✅	A2 is correctly connected to SOC_PWM1, translating this 1.8V signal to 3.3V on B2.
4	A3	SOC_PWM0	✅	A3 is correctly connected to SOC_PWM0, translating this 1.8V signal to 3.3V on B3.
5	A4		✅	A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw.
7	B4	GND	✅	A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw.
6	GND	GND	✅	GND is correctly connected to the ground plane.
8	B3	PWM0	✅	B3 is correctly connected to PWM0, translating this 3.3V signal to 1.8V on A3.
9	B2	PWM1	✅	B2 is correctly connected to PWM1, translating this 3.3V signal to 1.8V on A2.
10	B1	I2SMCLK_GPIO	✅	B1 is correctly connected to I2SMCLK_GPIO, translating this 3.3V signal to 1.8V on A1.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB, providing the reference voltage for the B-side I/O pins.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform reset is deasserted.

U10 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the reference voltage for the A-side I/O pins.
2	A1	SOC_GPIO_S5_2	✅	A1 is correctly connected to SOC_GPIO_S5_2, translating this 1.8V signal to 3.3V on B1.
3	A2	SOC_GPIO_S5_1	✅	A2 is correctly connected to SOC_GPIO_S5_1, translating this 1.8V signal to 3.3V on B2.
4	A3	SOC_GPIO_S5_0	✅	A3 is correctly connected to SOC_GPIO_S5_0, translating this 1.8V signal to 3.3V on B3.
5	A4		✅	A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw.
7	B4	GND	✅	A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw.
6	GND	GND	✅	GND is correctly connected to the ground plane.
8	B3	GPIO_S5_0	✅	B3 is correctly connected to GPIO_S5_0, translating this 3.3V signal to 1.8V on A3.
9	B2	GPIO_S5_1	✅	B2 is correctly connected to GPIO_S5_1, translating this 3.3V signal to 1.8V on A2.
10	B1	GPIO_S5_2	✅	B1 is correctly connected to GPIO_S5_2, translating this 3.3V signal to 1.8V on A1.
11	VCCB	+PS_3VSB	✅	VCCB is correctly connected to +PS_3VSB, providing the reference voltage for the B-side I/O pins.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform reset is deasserted.

U16 - NTS0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA is correctly connected to +V1P8S, providing the reference voltage for the A-side I/O pins.
2	A1	I2S_DATIN_R	✅	A1 is correctly connected to I2S_DATIN_R, translating this 1.8V signal to 3.3V on B1.
3	A2	I2S_DATOUT_R	✅	A2 is correctly connected to I2S_DATOUT_R, translating this 1.8V signal to 3.3V on B2.
4	A3	I2S_FRM_R	✅	A3 is correctly connected to I2S_FRM_R, translating this 1.8V signal to 3.3V on B3.
5	A4	I2S_CLK_R	✅	A4 is correctly connected to I2S_CLK_R, translating this 1.8V signal to 3.3V on B4.
6	GND	GND	✅	GND is correctly connected to the ground plane.
7	B4	I2SCLK_GPIO	✅	B4 is correctly connected to I2SCLK_GPIO, translating this 3.3V signal to 1.8V on A4.
8	B3	I2SFRM_GPIO	✅	B3 is correctly connected to I2SFRM_GPIO, translating this 3.3V signal to 1.8V on A3.
9	B2	I2SDO_GPIO	✅	B2 is correctly connected to I2SDO_GPIO, translating this 3.3V signal to 1.8V on A2.
10	B1	I2SDI_GPIO	✅	B1 is correctly connected to I2SDI_GPIO, translating this 3.3V signal to 1.8V on A1.
11	VCCB	+3VSB	✅	VCCB is correctly connected to +3VSB, providing the reference voltage for the B-side I/O pins.
12	OE	PMC_PLTRST_R_V1P8	✅	OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform reset is deasserted.

U3 - W25Q64BVSSIG ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPI_CS0	✅	CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pullup to +V_SPI, translating through U18 to the SOC and available on programming header J1.
2	SO/IO1	SPI_MISO	✅	SO/IO1 (Serial Data Output) is correctly connected to SPI_MISO, translating through U18 to the SOC and available on programming header J1.
3	WP#/IO2	SPI_WP	✅	WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pullup to +V_SPI, disabling hardware write protection and allowing software control.
4	GND	GND	✅	GND is correctly connected to the ground net.
5	SI/IO0	SPI_MOSI	✅	SI/IO0 (Serial Data Input) is correctly connected to SPI_MOSI, translating through U18 to the SOC and available on programming header J1.
6	SCK	SPI_CLK	✅	SCK (Serial Clock) is correctly connected to SPI_CLK, translating through U18 to the SOC and available on programming header J1.
7	HOLD#/IO3	SPI_HOLD	✅	HOLD#/IO3 (Hold Input) is correctly connected to SPI_HOLD with a 10K pullup to +V_SPI, disabling the hold function during normal operation.
8	VCC	+V_SPI	✅	VCC is correctly connected to +V_SPI which is supplied at 3.3V through D8 from +3VSB (via R152) or DDP_VCC, with appropriate decoupling capacitors.

D8 - BAT754C ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	DDP_VCC	✅	Anode A1 is correctly connected to DDP_VCC from the DediProg programming header, providing one of two power sources for the SPI flash.
A2	A2	$20N2079	✅	Anode A2 is correctly connected through R152 to +3VSB, providing board power to the SPI flash when the programmer is not connected.
C	C	+V_SPI	✅	Common cathode C is correctly connected to +V_SPI, OR-ing the two power sources (DDP_VCC and +3VSB) to supply the SPI flash.

R818 - 110-0002124 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N2079	✅	This 0-ohm jumper is correctly marked DNI (Do Not Install) as it would connect +V1P8A (1.8V) to the SPI flash power supply, which is below the minimum voltage specification for the W25Q64BVSSIG.
2	2	+V1P8A	✅	This 0-ohm jumper is correctly marked DNI (Do Not Install) as it would connect +V1P8A (1.8V) to the SPI flash power supply, which is below the minimum voltage specification for the W25Q64BVSSIG.

R152 - 110-0002124 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N2079	✅	This 0-ohm jumper is correctly populated to connect +3VSB (3.3V) to the SPI flash power supply, which is within the voltage specification for the W25Q64BVSSIG.
2	2	+3VSB	✅	This 0-ohm jumper is correctly populated to connect +3VSB (3.3V) to the SPI flash power supply, which is within the voltage specification for the W25Q64BVSSIG.

J1 - 258-0004612 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDP_VCC	✅	Pin 1 (DDP_VCC) correctly provides power from the DediProg programmer to the SPI flash through D8.
2	2	GND	✅	Pin 2 (GND) correctly provides ground reference for the DediProg programmer interface.
3	3	SPI_CS0	✅	Pin 3 (SPI_CS0) correctly provides chip select access for programming the SPI flash.
4	4	SPI_CLK	✅	Pin 4 (SPI_CLK) correctly provides clock access for programming the SPI flash.
5	5	SPI_MISO	✅	Pin 5 (SPI_MISO) correctly provides data output access for reading from the SPI flash during programming.
6	6	SPI_MOSI	✅	Pin 6 (SPI_MOSI) correctly provides data input access for writing to the SPI flash during programming.
7	7		✅	Pin 7 has no connection shown in the schematic, which is acceptable as this pin may be reserved or unused in the DediProg interface.
8	8	DDP_IO3L	✅	Pin 8 (DDP_IO3L) correctly connects to the level translator output enable, allowing the DediProg to control bus isolation during programming.

U40 - PCA9306DCUT ❌

DRCY flagged 1 potential issues in this component.

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Pin Designator	Pin Name	Net	Correct?	Analysis
5	SDA2	GPIO_I2C_SDA	❌	SDA2 and SCL2 pins are connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to connector JP1. No pullup resistors are present on these nets on this board. The PCA9306 datasheet requires pullup resistors on open-drain I/O ports for proper operation. While pullup resistors could theoretically be provided on a remote board, best practice for I2C interfaces is to provide them on the host board to ensure reliable operation. Pullup resistors should be added from these nets to +3VSB. Pin 5 connects to GPIO_I2C_SDA and pin 6 connects to GPIO_I2C_SCL (from schematic) Pins 5 and 6 are SDA2 and SCL2, the serial data and clock on the high-voltage side (from datasheet PCA9306DCUT, page 4) GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 connector pins 15 and 13 respectively (from schematic) Pin 7 (VREF2) connects to net $20N1576, which is pulled to +3VSB through R812 (200K), establishing VDPU as +3VSB (from schematic) Open-drain I/O ports require external pullup resistors to respective supply voltages, with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU (from datasheet PCA9306DCUT, page 10) No pullup resistors are visible on GPIO_I2C_SDA or GPIO_I2C_SCL on this schematic page (from schematic) The low-voltage side I2C signals (I2C5_SCL and I2C5_SDA on pins 3 and 4) have pullup resistors R267 and R266 (both 10K) to +V1P8S (from schematic) Typical application circuits show pullup resistors RPU on both the low-voltage and high-voltage sides (from datasheet PCA9306DCUT, page 17) The asymmetry between the low-voltage side (which has pullups) and high-voltage side (which lacks pullups) suggests a design oversight (reasoning) While it's theoretically possible to provide pullups on a remote board connected to JP1, this creates a dependency and potential failure mode if the remote board doesn't provide them (reasoning) Best practice for I2C interfaces exposed through connectors is to provide pullup resistors on the host board to ensure reliable operation regardless of what's connected (reasoning) Pullup resistors should be added from GPIO_I2C_SCL to +3VSB and from GPIO_I2C_SDA to +3VSB, with values chosen based on bus capacitance and operating frequency per I2C specification (reasoning)
6	SCL2	GPIO_I2C_SCL	❌	SDA2 and SCL2 pins are connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to connector JP1. No pullup resistors are present on these nets on this board. The PCA9306 datasheet requires pullup resistors on open-drain I/O ports for proper operation. While pullup resistors could theoretically be provided on a remote board, best practice for I2C interfaces is to provide them on the host board to ensure reliable operation. Pullup resistors should be added from these nets to +3VSB. Pin 5 connects to GPIO_I2C_SDA and pin 6 connects to GPIO_I2C_SCL (from schematic) Pins 5 and 6 are SDA2 and SCL2, the serial data and clock on the high-voltage side (from datasheet PCA9306DCUT, page 4) GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 connector pins 15 and 13 respectively (from schematic) Pin 7 (VREF2) connects to net $20N1576, which is pulled to +3VSB through R812 (200K), establishing VDPU as +3VSB (from schematic) Open-drain I/O ports require external pullup resistors to respective supply voltages, with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU (from datasheet PCA9306DCUT, page 10) No pullup resistors are visible on GPIO_I2C_SDA or GPIO_I2C_SCL on this schematic page (from schematic) The low-voltage side I2C signals (I2C5_SCL and I2C5_SDA on pins 3 and 4) have pullup resistors R267 and R266 (both 10K) to +V1P8S (from schematic) Typical application circuits show pullup resistors RPU on both the low-voltage and high-voltage sides (from datasheet PCA9306DCUT, page 17) The asymmetry between the low-voltage side (which has pullups) and high-voltage side (which lacks pullups) suggests a design oversight (reasoning) While it's theoretically possible to provide pullups on a remote board connected to JP1, this creates a dependency and potential failure mode if the remote board doesn't provide them (reasoning) Best practice for I2C interfaces exposed through connectors is to provide pullup resistors on the host board to ensure reliable operation regardless of what's connected (reasoning) Pullup resistors should be added from GPIO_I2C_SCL to +3VSB and from GPIO_I2C_SDA to +3VSB, with values chosen based on bus capacitance and operating frequency per I2C specification (reasoning)
1	GND	GND	✅	GND pin is correctly connected to the ground net.
2	VREF1	+V1P8S	✅	VREF1 pin is correctly connected to the 1.8V supply rail (+V1P8S), providing the low-voltage side reference.
3	SCL1	I2C5_SCL	✅	SCL1 pin is correctly connected to the low-voltage I2C clock line (I2C5_SCL) with proper pullup resistor.
4	SDA1	I2C5_SDA	✅	SDA1 pin is correctly connected to the low-voltage I2C data line (I2C5_SDA) with proper pullup resistor.
7	VREF2	$20N1576	✅	VREF2 pin is correctly connected through a 200K resistor (R812) to the 3.3V standby supply (+3VSB), establishing the proper reference voltage for the high-voltage side.
8	EN	$20N1576	✅	EN pin is correctly shorted to VREF2 and pulled up through the 200K resistor (R812) to +3VSB, enabling the level translator.

R147 - 100K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Pin 1 is correctly connected to +V1P8A, providing the pull-up voltage for the OE control signal.
2	2	DDP_IO3L	✅	Pin 2 is correctly connected to DDP_IO3L, pulling it HIGH to enable U18 during normal operation while allowing DediProg override.

U18 - NTB0104GU12 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A (1.8V) with appropriate decoupling capacitor C165 nearby.
2	A1	SOC_SPI_MOSI-R	✅	A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins.
3	A2	SOC_SPI_CLK-R	✅	A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins.
4	A3	SOC_SPI_MISO-R	✅	A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins.
5	A4	SOC_SPI_CS0B-R	✅	A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins.
6	GND	GND	✅	GND pin is correctly connected to the ground net.
7	B4	SPI_CS0	✅	B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins.
8	B3	SPI_MISO	✅	B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins.
9	B2	SPI_CLK	✅	B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins.
10	B1	SPI_MOSI	✅	B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins.
11	VCCB	+V_SPI	✅	VCCB is correctly connected to +V_SPI with appropriate decoupling capacitors C383 and C160 nearby.
12	OE	DDP_IO3L	✅	OE pin is connected to DDP_IO3L with 100K pullup to +V1P8A, enabling DediProg control of the translator. Connection is correct for typical use, though there is a potential concern if DDP_IO3L is driven above VCCA+0.5V.

J5 - HDR_2POS_DUAL_TIN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Pin 1 connects to FP_PWRBTN, allowing a jumper to be installed to simulate a power button press.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the jumper.

SW1 - 3770-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Pin 1 connects to FP_PWRBTN, which is the power button signal line. When the button is pressed, this pin is shorted to pin 2 (GND), pulling the signal low.
2	2	GND	✅	Pin 2 connects to GND, providing the ground return path when the button is pressed.
3	GND1	GND_EARTH	✅	Pins 3 (GND1) and 4 (GND2) connect to GND_EARTH, which is the chassis ground. These are mechanical ground connections for the switch housing.
4	GND2	GND_EARTH	✅	Pins 3 (GND1) and 4 (GND2) connect to GND_EARTH, which is the chassis ground. These are mechanical ground connections for the switch housing.

D9 - DIODE_TVS_5V_84W_XFDFN ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Pin N connects to GND, providing the ground reference for the bidirectional TVS diode.
P	P	FP_PWRBTN	✅	Pin P connects to FP_PWRBTN, providing ESD protection for the power button signal line.

Q105 - FDN327N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	GPIO_LED_CONTROL	✅	Drain is correctly connected to GPIO_LED_CONTROL net, which connects to the LED anode through current-limiting resistor R746 from +VCC. This forms a low-side switch configuration with inverted logic.
G	GATE	GPIO_D2_LED_CTRL	✅	Gate is correctly connected to GPIO_D2_LED_CTRL with a 10kΩ pull-down resistor (R706) to ensure the MOSFET is off when the GPIO is not actively driven.
S	SOURCE	GND	✅	Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET in a low-side switch application.

D2 - 4560-0045 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GPIO_LED_CONTROL	✅	Anode is correctly connected to GPIO_LED_CONTROL net, which is pulled up through R746 (470Ω) from +VCC and can be pulled low by MOSFET Q105.
C	CATHODE	GND	✅	Cathode is correctly connected to GND, providing the return path for LED current and proper forward-bias orientation.

D1 - 4560-0045 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	+PS_5VSB	✅	Anode is connected to +PS_5VSB (5V standby supply), providing power to the LED. This is correct for a power indicator LED.
C	CATHODE	PWR_LEDR	✅	Cathode is connected to PWR_LEDR net, which connects through current limiting resistor R148 (470Ω) to GND. This provides proper current limiting for the LED.

R132 - 110-0004465 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RC_ENB	✅	Connected to RC_ENB, forming an RC filter with C338 to provide a filtered version of the DC input.
2	2	DC_IN_1	✅	Connected to DC_IN_1 to provide the input for the RC filter network.

L12 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$22N1502	✅	Connected to internal net $22N1502 in parallel with L13 for increased current handling.
2	2	DC_IN_1	✅	Connected to DC_IN_1 in parallel with L13 for EMI filtering with higher current capability.

L13 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$22N1502	✅	Connected to internal net $22N1502, which feeds the power distribution and protection circuits.
2	2	DC_IN_1	✅	Connected to DC_IN_1 from the power jack for EMI filtering of the input power.

J9 - RAPC712 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DC_IN_1	✅	Center pin correctly connected to DC_IN_1, the main 5V DC input to the system.
2	2	GND	✅	Sleeve pin correctly connected to GND for ground return path.
3	3	GND	✅	Switch contact connected to GND, which is acceptable if plug detection functionality is not required.

D13 - 4.3V Zener ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Anode connected to GND. The zener operates in reverse breakdown mode to clamp $22N2300 to 4.3V above ground, establishing the voltage reference for the overvoltage protection circuit.
C	CATHODE	$22N2300	✅	Cathode connected to $22N2300, which drives the gate of Q106 (BSS84 P-channel MOSFET). The zener clamps this node to 4.3V above ground, setting the reference voltage for the overvoltage protection threshold.

U36 - IRF9321 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	$22N1502	✅	Source pins connected to $22N1502, which is the filtered DC input through ferrite beads L13 and L12 from DC_IN_1. This is the input side of the overvoltage protection switch.
2	S2	$22N1502	✅	Source pins connected to $22N1502, which is the filtered DC input through ferrite beads L13 and L12 from DC_IN_1. This is the input side of the overvoltage protection switch.
3	S3	$22N1502	✅	Source pins connected to $22N1502, which is the filtered DC input through ferrite beads L13 and L12 from DC_IN_1. This is the input side of the overvoltage protection switch.
4	G	DC_GATE_ENB	✅	Gate pin connected to DC_GATE_ENB, which is controlled by Q106 and pulled down by R309. This controls the on/off state of U36 based on input voltage.
5	D1	+PS_5VSB	✅	Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch.
6	D2	+PS_5VSB	✅	Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch.
7	D3	+PS_5VSB	✅	Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch.
8	D4	+PS_5VSB	✅	Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch.

Q106 - BSS84 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	D	DC_GATE_ENB	✅	Drain pin connected to DC_GATE_ENB, which controls the gate of U36. When Q106 turns on, it pulls DC_GATE_ENB high to turn off U36.
G	G	$22N2300	✅	Gate pin connected to $22N2300, which is the voltage-sensed signal from the R855/D13 divider network. This controls Q106 based on input voltage.
S	S	$22N1502	✅	Source pin connected to $22N1502, which is the same net as the source of U36. This provides the reference voltage for Q106's gate control.

Q14 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	5VSB_LSENB	✅	Drain pin is correctly connected to 5VSB_LSENB, which is pulled up to +10V by R324. Q14 acts as a low-side switch to pull this signal to ground when enabled.
G	GATE	5VSB_GATE	✅	Gate pin is correctly connected to 5VSB_GATE, which is driven by 5VSB_CTRL through R323 (10K) with C340 (1uF) providing filtering.
S	SOURCE	GND	✅	Source pin is correctly connected to GND, which is the proper configuration for a low-side switch.

Q103 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+5VSB	✅	Source pins S1, S2, S3 are correctly connected to the +5VSB output rail. All three source pins are tied together as expected for the PowerPAK 1212-8 package.
2	S2	+5VSB	✅	Source pins S1, S2, S3 are correctly connected to the +5VSB output rail. All three source pins are tied together as expected for the PowerPAK 1212-8 package.
3	S3	+5VSB	✅	Source pins S1, S2, S3 are correctly connected to the +5VSB output rail. All three source pins are tied together as expected for the PowerPAK 1212-8 package.
4	G	5VSB_LSENB	✅	Gate pin is correctly connected to 5VSB_LSENB control signal. This signal is pulled to +10V when Q14 is OFF (enabling Q103) and pulled to GND when Q14 is ON (disabling Q103).
5	D1	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package.
6	D2	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package.
7	D3	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package.
8	D4	+PS_5VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package.

Q4 - MMBT3904 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
B	BASE	S5_ENBL	✅	Base is correctly connected to S5_ENBL control signal through R133 (10K pull-up to +V1P8A). The base current of approximately 110μA when S5_ENBL is high provides adequate drive for the transistor.
C	COLLECTOR	+3VSB_EN_L	✅	Collector is correctly connected to +3VSB_EN_L with pull-up resistor R321 (1K) to +PS_5VSB. This inverts the S5_ENBL signal to control Q11.
E	EMITTER	GND	✅	Emitter is correctly connected to GND, which is the proper configuration for an NPN transistor in common-emitter configuration.

Q104 - SISA18ADN-T1-GE3 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+3VSB	✅	Source pins S1, S2, S3 are correctly connected to +3VSB output rail. Multiple source pins are paralleled for lower resistance and better thermal performance.
2	S2	+3VSB	✅	Source pins S1, S2, S3 are correctly connected to +3VSB output rail. Multiple source pins are paralleled for lower resistance and better thermal performance.
3	S3	+3VSB	✅	Source pins S1, S2, S3 are correctly connected to +3VSB output rail. Multiple source pins are paralleled for lower resistance and better thermal performance.
4	G	+3VSB_EN	✅	Gate pin is correctly connected to +3VSB_EN control signal. The gate drive voltage of approximately 6.7V (10V drive minus 3.3V source) is adequate to fully enhance the MOSFET, though not optimal for minimum RDS(on).
5	D1	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance.
6	D2	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance.
7	D3	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance.
8	D4	+PS_3VSB	✅	Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance.

Q11 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB_EN	✅	Drain is correctly connected to +3VSB_EN, which is the gate control signal for Q104. Q11 acts as a pull-down switch to disable Q104 when activated.
G	GATE	+3VSB_EN_L	✅	Gate is correctly connected to +3VSB_EN_L control signal. This signal is driven by Q4 collector and controls when Q11 pulls down the gate of Q104.
S	SOURCE	GND	✅	Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch.

U13 - NB670 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN	PS5VSB_VIN	✅	VIN pin correctly connected to PS5VSB_VIN input supply with appropriate input capacitors for decoupling.
2	PGND	GND	✅	PGND pin correctly connected to ground plane.
3	N/C		✅	N/C pin correctly left unconnected as specified in datasheet.
4	PG	+PS_3VSB_PG	✅	PG pin correctly configured as open-drain output with 100K pull-up resistor to PS3_VCC.
5	CLK	$22N1411	✅	CLK pin connected to charge pump circuit through capacitors C72 and C283.
6	LDO	PS3_LDO	✅	LDO pin correctly connected with 10uF decoupling capacitor, exceeding minimum 4.7uF requirement.
7	VOUT	+PS_3VSB	✅	VOUT pin correctly connected to output voltage with multiple output capacitors and inductor.
8	SW1	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306.
9	SW2	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306.
15	SW3	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306.
16	SW4	PS3VSB_PHASE	✅	SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306.
10	BST	PS3_BST	✅	BST pin connected to PS3_BST, which connects through series 4.7Ω resistor R291 to bootstrap capacitor C306. The series resistor R291 should not be present in the bootstrap circuit.
11	VCC	PS3_VCC	✅	VCC pin correctly connected with 1uF decoupling capacitor meeting datasheet minimum requirement.
12	ENLDO		✅	ENLDO pin correctly left floating as it is internally pulled high to enable the LDO.
13	EN	PS3_EN	✅	EN pin connected with 499K pull-up resistor to input supply. Missing recommended 10nF noise filtering capacitor (C85 is wrong value and DNI).
14	AGND	GND	✅	AGND pin correctly connected to ground plane.

R291 - 110-0004467 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3_BST	✅	R291 is a 4.7Ω series resistor incorrectly placed in the bootstrap circuit between BST pin and bootstrap capacitor. This resistor should not be present as it limits bootstrap capacitor charging and deviates from datasheet recommendations.
2	2	$22N1498	✅	R291 is a 4.7Ω series resistor incorrectly placed in the bootstrap circuit between BST pin and bootstrap capacitor. This resistor should not be present as it limits bootstrap capacitor charging and deviates from datasheet recommendations.

L3 - 125-0004501 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3VSB_PHASE	✅	Inductor input correctly connected to switch node PS3VSB_PHASE from U13.
2	2	+PS_3VSB	✅	Inductor output correctly connected to +PS_3VSB output rail with multiple output capacitors.

U35 - NCT3012S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DeepS5_Sel	S5_SEL	✅	DeepS5_Sel configuration input connected to S5_SEL with pull-up resistor to +PS_5VSB.
2	VSB	+PS_5VSB	✅	VSB power supply input correctly connected to +PS_5VSB.
3	PS_IN#	PB_RES	✅	PS_IN# power button input connected to PB_RES with series resistor to front panel button.
4	SLP_S5#	SLP_S4_L	✅	SLP_S5# sleep state input connected to SLP_S4_L, which may be a naming inconsistency.
5	SDA	DDR_SMB_DATA	✅	SDA I2C data line correctly connected to DDR_SMB_DATA.
6	SCLK	DDR_SMB_CLK	✅	SCLK I2C clock line correctly connected to DDR_SMB_CLK.
7	PS_OUT#	PS_OUT_L	✅	PS_OUT# power supply output control signal correctly connected to PS_OUT_L.
8	SYS5VSB_OFF	5VSB_CTRL	✅	SYS5VSB_OFF control output correctly connected to 5VSB_CTRL for EuP mode control.
9	GND	GND	✅	GND pin correctly connected to ground.

Q13 - RXR035N03 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+5VSB	✅	Drain is correctly connected to +5VSB input power rail. This MOSFET acts as a high-side switch to generate the +VCC output rail.
G	GATE	SYS_EN	✅	Gate is correctly connected to SYS_EN control signal. The gate is pulled up to +10V through R340 (100K) when enabled, providing adequate Vgs for full turn-on.
S	SOURCE	+VCC	✅	Source is correctly connected to +VCC output rail. This is the switched output that provides power when SYS_EN is high.

Q6 - RXR035N03 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB	✅	Drain is correctly connected to the +3VSB input power rail (3.3V standby supply). This is the input side of the high-side load switch.
G	GATE	SYS_EN	✅	Gate is correctly connected to the SYS_EN control signal with proper pull-up to +10V through R340 (100K). The +10V gate drive provides sufficient VGS (approximately 6.7V when conducting) for full enhancement.
S	SOURCE	+VCC3	✅	Source is correctly connected to the +VCC3 output rail. This is the output side of the high-side load switch, providing switched 3.3V power.

Q7 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN_GATE	✅	Drain is connected to SYS_EN_GATE net, which controls the gate of Q12. This pin pulls the gate of Q12 low when Q7 is turned on.
G	GATE	SLP_S3_L	✅	Gate is connected to SLP_S3_L control signal. This pin controls when Q7 turns on to pull down SYS_EN_GATE.
S	SOURCE	GND	✅	Source is connected to GND. This is the correct connection for an N-channel MOSFET in a low-side switch configuration.

Q12 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN	✅	Drain is connected to SYS_EN net, which controls the gate of Q6. This pin pulls the gate of Q6 low when Q12 is turned on.
G	GATE	SYS_EN_GATE	✅	Gate is connected to SYS_EN_GATE net, which is controlled by Q7. This pin receives the inverted SLP_S3_L signal to control Q12.
S	SOURCE	GND	✅	Source is connected to GND. This is the correct connection for an N-channel MOSFET in a low-side switch configuration.

Q10 - 2N7002K ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	S5_ENBL	✅	Drain is correctly connected to S5_ENBL net, which is pulled up to +V1P8A through R133 (10K). When Q10 turns on, it pulls S5_ENBL low to control downstream circuitry.
G	GATE	5VSB_CTRL	✅	Gate is correctly connected to 5VSB_CTRL control signal from U35 pin 8. The gate voltage of approximately 5V when active provides adequate drive for the MOSFET.
S	SOURCE	GND	✅	Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch.

D6 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB_PG	✅	Part number mismatch: Circuit requires common cathode diode configuration for OR gate function, but BAT54A-S specifies common anode. COMPVALUE attribute shows BAV99-7-F-S-X (common cathode) which would be correct, creating ambiguity about actual part.
2	2	+3VSB_EN	✅	Part number mismatch: Circuit requires common cathode diode configuration for OR gate function, but BAT54A-S specifies common anode. COMPVALUE attribute shows BAV99-7-F-S-X (common cathode) which would be correct, creating ambiguity about actual part.
3	3	PMC_RSMRST	✅	Part number mismatch: Circuit requires common cathode diode configuration for OR gate function, but BAT54A-S specifies common anode. COMPVALUE attribute shows BAV99-7-F-S-X (common cathode) which would be correct, creating ambiguity about actual part.

Q2 - BAV99-7-F-S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	+PS_5VSB	✅	Anode 1 connected to +PS_5VSB, providing high-side clamp reference for AC-coupled CLK signal protection circuit.
2	A2	$22N1417	✅	Anode 2 connected to $22N1417, which is biased to GND through C71, providing low-side clamp reference.
3	C	$22N1419	✅	Common cathode connected to $22N1419, which is AC-coupled to CLK signal from U13 through C72.

Q9 - BAV99-7-F-S-X ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	$22N1417	✅	Anode 1 connected to $22N1417, shared with Q2 pin 2, providing low-side clamp reference.
2	A2	+10V	✅	Anode 2 connected to +10V, providing high-side clamp reference for AC-coupled CLK signal protection circuit.
3	C	$22N1467	✅	Common cathode connected to $22N1467, which is AC-coupled to CLK signal from U13 through C283.

FB11 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_5VSB	✅	Pin 1 connects to +PS_5VSB, the main 5V standby power rail. FB11 is in parallel with FB1 to increase current handling capacity.
2	2	PS5VSB_VIN	✅	Pin 2 connects to PS5VSB_VIN, the filtered input to buck converter U13. This completes the parallel configuration with FB1.

FB1 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_5VSB	✅	Pin 1 connects to +PS_5VSB, the main 5V standby power rail. This is the source side of the ferrite bead providing input filtering to the buck converter.
2	2	PS5VSB_VIN	✅	Pin 2 connects to PS5VSB_VIN, which is the filtered input to buck converter U13. This is the load side of the ferrite bead.

U25 - NCP81109GMNTXG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT pin connected to VR_HOT_L net for thermal alert signaling.
2	SDIO	$23N2429	✅	SDIO pin connected to $23N2429 for I2C/SVID data communication.
3	ALERT	$23N2431	✅	ALERT pin connected to $23N2431 for system alert signaling.
4	SCLK	$23N2430	✅	SCLK pin connected to $23N2430 for I2C/SVID clock communication.
5	GND	AGND-VCORE	✅	Analog ground pins (GND, GND1, GND_PAD) all correctly connected to AGND-VCORE for analog reference.
32	GND1	AGND-VCORE	✅	Analog ground pins (GND, GND1, GND_PAD) all correctly connected to AGND-VCORE for analog reference.
49	GND_PAD	AGND-VCORE	✅	Analog ground pins (GND, GND1, GND_PAD) all correctly connected to AGND-VCORE for analog reference.
6	VR_RDY	$23N3753	✅	VR_RDY pin connected to $23N3753 for power good indication.
7	VIN1	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
11	VIN2	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
12	VIN3	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
13	VIN4	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
14	VIN5	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
15	VIN6	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
16	VIN7	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
17	VIN8	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
50	VIN_PAD	+5VSB_SW	✅	Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling.
8	BST	$23N3711	✅	BST pin connected to bootstrap circuit through R154 and C50 for high-side gate driver supply.
9	GH		✅	GH (high-side gate driver output) appears to have no net connection in the provided data.
10	SW1	$23N3731	✅	SW1 pin connected to $23N3731 as the return path for the bootstrap capacitor.
18	SW2	VCORE-SW	✅	Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output.
25	SW3	VCORE-SW	✅	Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output.
26	SW4	VCORE-SW	✅	Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output.
27	SW5	VCORE-SW	✅	Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output.
28	SW6	VCORE-SW	✅	Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output.
29	SW7	VCORE-SW	✅	Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output.
51	SW_PAD	VCORE-SW	✅	Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output.
19	PGND1	GND	✅	Power ground pins (PGND1-6) all correctly connected to GND for high-current return path.
20	PGND2	GND	✅	Power ground pins (PGND1-6) all correctly connected to GND for high-current return path.
21	PGND3	GND	✅	Power ground pins (PGND1-6) all correctly connected to GND for high-current return path.
22	PGND4	GND	✅	Power ground pins (PGND1-6) all correctly connected to GND for high-current return path.
23	PGND5	GND	✅	Power ground pins (PGND1-6) all correctly connected to GND for high-current return path.
24	PGND6	GND	✅	Power ground pins (PGND1-6) all correctly connected to GND for high-current return path.
30	GL		✅	GL (low-side gate driver output) appears to have no net connection in the provided data.
31	VBOOT	$23N3477	✅	VBOOT pin connected to $23N3477 for boot voltage configuration.
33	VCCP	$23N3625	✅	VCCP pin connected to $23N3625, supplied from +5VSB through R845 (1.00Ω) and decoupled by C48 (4.7uF).
34	TSENSE	$23N3665	✅	TSENSE pin connected to $23N3665 for temperature monitoring through thermistor network.
35	IMAX	$23N3681	✅	IMAX pin connected to $23N3681 with R105 (44.2kΩ) to AGND-VCORE for maximum current limit setting.
36	IOUT	$23N3683	✅	IOUT pin connected to $23N3683 with R146 (16.5kΩ) to AGND-VCORE and C47 (470pF) for output current monitoring.
37	ILIM	VCORE-ILIM	✅	ILIM pin connected to VCORE-ILIM for current limit control.
38	CSCOMP	VCORE-CSCOMP	✅	CSCOMP pin connected to VCORE-CSCOMP for current loop compensation.
39	CSSUM	VCORE-CSSUM	✅	CSSUM pin connected to VCORE-CSSUM for summed current sense signal.
40	CSREF	VCORE-CSREF	✅	CSREF pin connected to VCORE-CSREF for current sense reference voltage.
41	FREQ	$23N2930	✅	FREQ pin connected to $23N2930 with R93 (18.7kΩ) to AGND-VCORE for switching frequency setting.
42	COMP	VCORE-COMP	✅	COMP pin connected to VCORE-COMP for voltage loop compensation.
43	FB	VCORE-FB	✅	FB pin connected to VCORE-FB for output voltage feedback.
44	DIFFOUT	VCORE-DIFFOUT	✅	DIFFOUT pin connected to VCORE-DIFFOUT for differential amplifier output.
45	VSN	VR-VCORE-VSN	✅	VSN pin connected to VR-VCORE-VSN for remote negative sense.
46	VSP	VR-VCORE-VSP	✅	VSP pin connected to VR-VCORE-VSP for remote positive sense.
47	VCC	$23N3860	✅	VCC pin connected to $23N3860, supplied from +5VSB through R166 (2.20Ω) and decoupled by C24 (1.0uF) to AGND-VCORE.
48	EN	$23N5607	✅	EN pin connected to $23N5607 for enable control with pull-up and filtering.

C48 - 2232-0016 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
2	2	GND	❌	Pin 2 connects to GND but should connect to AGND-VCORE for proper analog supply decoupling. This is inconsistent with C24 (VCC decoupling) which correctly connects to AGND-VCORE. Pin 2 is connected to net GND (from schematic) U25 pin 33 (VCCP) is likely an analog power supply pin based on typical power controller architectures (reasoning) U25 analog ground pins (5, 32, 49) all connect to AGND-VCORE (from schematic) C24, which decouples U25 pin 47 (VCC), connects to AGND-VCORE (from schematic) For proper noise isolation, analog supply decoupling capacitors should reference the same ground as the IC's analog ground pins (reasoning) C48 pin 2 should connect to AGND-VCORE instead of GND to maintain consistent ground referencing for analog supplies (reasoning) Connecting to GND instead of AGND-VCORE may introduce switching noise into the analog supply and degrade performance (reasoning) Recommendation: Change C48 pin 2 connection from GND to AGND-VCORE (reasoning)
1	1	$23N3625	✅	Pin 1 correctly connects to VCCP supply net $23N3625.

L18 - 3120-0266 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Pin 1 connects to the switching node VCORE-SW, which is the output of the multiphase buck converter switching stage. This is the correct connection for the input side of the output filter inductor.
2	2	+VCORE	✅	Pin 2 connects to the output voltage rail +VCORE. This is the correct connection for the output side of the buck converter inductor, providing filtered DC output voltage.

L8 - 3120-0183 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of an input filter inductor.
2	2	+5VSB_SW	✅	Pin 2 connects to +5VSB_SW, which feeds the VIN pins of the buck converter IC U25. This is the correct connection for the output side of an input filter inductor.

R88 - 1120-0032 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2824	✅	Connected to intermediate node in compensation network between COMP and FB pins. Part of Type III compensation network for voltage loop.
2	2	VCORE-FB	✅	Connected to VCORE-FB feedback node, which connects to U25 pin 43 (FB). Completes the compensation network path.

R89 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB feedback node. Forms part of differential feedback path to DIFFOUT pin.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT, which connects to U25 pin 44 (DIFFOUT). Completes differential feedback path.

R90 - 1121-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2818	✅	Connected to intermediate node in differential feedback filter network with C36.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT at U25 pin 44. Completes RC filter in differential feedback path.

C35 - 2220-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP at U25 pin 42 (COMP). Part of Type III compensation network.
2	2	VCORE-FB	✅	Connected to VCORE-FB feedback node. Creates high-frequency pole in compensation network.

C36 - 2220-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB feedback node. Part of RC filter in differential feedback path.
2	2	$23N2818	✅	Connected to intermediate node in differential feedback filter with R90.

C37 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP at U25 pin 42. Part of Type III compensation network.
2	2	$23N2824	✅	Connected to intermediate node in compensation network with R88. Creates pole-zero pair.

R63 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_SENSE	✅	Connected to VCC_SENSE remote sense input. Allows remote voltage sensing of the positive output.
2	2	VR-VCORE-VSP	✅	Connected to VR-VCORE-VSP at U25 pin 46. The 0-ohm resistor directly connects remote sense to the positive sense input.

R64 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VSS_SENSE	✅	Connected to VSS_SENSE remote sense input. Allows remote sensing of the negative/ground connection at the load.
2	2	$23N2860	✅	Connected to intermediate node in negative sense path. The 0-ohm resistor connects remote sense to the network feeding VSN.

R65 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2860	✅	Connected to intermediate node in negative sense path. Provides isolation between remote sense network and VSN input.
2	2	VR-VCORE-VSN	✅	Connected to VR-VCORE-VSN at U25 pin 45. Provides isolation and filtering for the negative sense input.

R91 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Provides pull-down path for negative sense network when remote sensing is not used.
2	2	$23N2860	✅	Connected to intermediate node in negative sense path. Pulls the node to ground when remote sensing is not connected.

R92 - 1120-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output. Provides local sensing path from the regulator output to VSP.
2	2	VR-VCORE-VSP	✅	Connected to VR-VCORE-VSP at U25 pin 46. Provides default connection to output voltage for local sensing.

C34 - 2221-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR-VCORE-VSP	✅	DNI capacitor that would filter the differential sense inputs VSP and VSN. Not installed, so electrically absent.
2	2	VR-VCORE-VSN	✅	DNI capacitor that would filter the differential sense inputs VSP and VSN. Not installed, so electrically absent.

C38 - 2221-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2860	✅	DNI capacitor that would filter the negative sense path. Not installed, so electrically absent.
2	2	VR-VCORE-VSN	✅	DNI capacitor that would filter the negative sense path. Not installed, so electrically absent.

SP3 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Connected to VCORE-SW switching node for DCR current sensing.
2	2	$23N3209	✅	Connected to $23N3209, which connects through R107 to VCORE-CSSUM for current sensing.

SP4 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output for DCR current sensing reference.
2	2	$23N3208	✅	Connected to $23N3208, which connects through R108 to VCORE-CSREF for current sensing reference.

TH1 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP for temperature compensation in the current sensing network.
2	2	$23N3115	✅	Connected to junction node $23N3115, which connects through R106 to VCORE-CSSUM.

R78 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	0-ohm jumper connecting U25 TSENSE pin to the thermistor-based temperature sensing network, allowing optional population or circuit modification.
2	2	$23N3662	✅	0-ohm jumper connecting U25 TSENSE pin to the thermistor-based temperature sensing network, allowing optional population or circuit modification.

C46 - 2222-0016 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	0.1uF filter capacitor on the TSENSE pin, providing high-frequency noise filtering for the temperature sensing input to analog ground.
2	2	AGND-VCORE	✅	0.1uF filter capacitor on the TSENSE pin, providing high-frequency noise filtering for the temperature sensing input to analog ground.

TH2 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Thermistor pin connected to the temperature sensing voltage divider node, which connects through R78 to U25 TSENSE pin. This forms the temperature-dependent part of the sensing circuit.
2	2	GND	✅	Thermistor pin connected to ground, providing the reference for the temperature sensing voltage divider.

R131 - 1120-0055 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	14K resistor pin connected to the temperature sensing voltage divider node, in parallel with thermistor TH2.
2	2	GND	✅	14K resistor pin connected to ground, completing the voltage divider for temperature sensing.

R80 - 1120-0329 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Series resistor (16.9Ω) on SVID data line between SVID_DATA-R and U25 SDIO pin. Provides signal integrity and damping for the SVID serial data interface.
2	2	$23N2429	✅	Series resistor (16.9Ω) on SVID data line between SVID_DATA-R and U25 SDIO pin. Provides signal integrity and damping for the SVID serial data interface.

R87 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_CLK-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required.
2	2	SVID_CLK-R	✅	DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_CLK-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required.

R62 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Zero-ohm jumper on SVID alert line between SVID_ALERT-R and U25 ALERT pin. Allows for optional series resistance if needed for signal integrity.
2	2	$23N2431	✅	Zero-ohm jumper on SVID alert line between SVID_ALERT-R and U25 ALERT pin. Allows for optional series resistance if needed for signal integrity.

R85 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_DATA-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required.
2	2	SVID_DATA-R	✅	DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_DATA-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required.

R86 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_ALERT-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required.
2	2	SVID_ALERT-R	✅	DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_ALERT-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required.

R81 - 1120-0099 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Series resistor (20.0Ω) on SVID clock line between SVID_CLK-R and U25 SCLK pin. Provides signal integrity and damping for the SVID serial clock interface.
2	2	$23N2430	✅	Series resistor (20.0Ω) on SVID clock line between SVID_CLK-R and U25 SCLK pin. Provides signal integrity and damping for the SVID serial clock interface.

R849 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	R849 is a 0Ω jumper connecting +VCC to the enable pin (EN) of U25. With R851 (10K) also connected to GND, this creates a continuous current path drawing approximately 0.5mA (assuming +VCC = 5V), which is unnecessary.
2	2	$23N5607	✅	R849 is a 0Ω jumper connecting +VCC to the enable pin (EN) of U25. With R851 (10K) also connected to GND, this creates a continuous current path drawing approximately 0.5mA (assuming +VCC = 5V), which is unnecessary.

R851 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N5607	✅	R851 is a 10K pull-down resistor on the enable pin of U25. With R849 (0Ω) connecting +VCC to the same net, R851 draws unnecessary current without providing functional benefit in the current configuration.
2	2	GND	✅	R851 is a 10K pull-down resistor on the enable pin of U25. With R849 (0Ω) connecting +VCC to the same net, R851 draws unnecessary current without providing functional benefit in the current configuration.

C50 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3733	✅	C50 is a 0.22μF bootstrap capacitor connected between the BST pin of U25 (through series resistor R154) and the SW1 pin. The capacitor value and voltage rating are appropriate for a bootstrap application.
2	2	$23N3731	✅	C50 is a 0.22μF bootstrap capacitor connected between the BST pin of U25 (through series resistor R154) and the SW1 pin. The capacitor value and voltage rating are appropriate for a bootstrap application.

R154 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3711	✅	R154 is a 2.20 ohm resistor in series with bootstrap capacitor C50, connected between the BST pin (pin 8) of U25 and the SW1 pin (pin 10) through C50. This is an unusual bootstrap circuit configuration that may be intentional for current limiting.
2	2	$23N3733	✅	R154 is a 2.20 ohm resistor in series with bootstrap capacitor C50, connected between the BST pin (pin 8) of U25 and the SW1 pin (pin 10) through C50. This is an unusual bootstrap circuit configuration that may be intentional for current limiting.

D4 - BAT54A-S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Cathode 1 of dual Schottky diode, connected to VCORE_PG. Part of AND gate for power good signals.
2	2	VGFX_PG	✅	Cathode 2 of dual Schottky diode, connected to VGFX_PG. Part of AND gate for power good signals.
3	3	VCORE_GFX_PG	✅	Common anode of dual Schottky diode, connected to VCORE_GFX_PG. Output of AND gate for combined power good signal.

C87 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
P			✅	Output bulk capacitor correctly connected between +VCORE and GND. Voltage rating of 2V provides minimal margin for a VCORE rail and should be verified against the maximum VCORE voltage specification.
N			✅	Output bulk capacitor correctly connected between +VCORE and GND. Voltage rating of 2V provides minimal margin for a VCORE rail and should be verified against the maximum VCORE voltage specification.

C88 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output rail as part of parallel ceramic output capacitor bank.
2	2	GND	✅	Connected to ground, completing the output capacitor connection.

C89 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output rail as part of parallel ceramic output capacitor bank.
2	2	GND	✅	Connected to ground, completing the output capacitor connection.

C90 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output rail as part of parallel ceramic output capacitor bank.
2	2	GND	✅	Connected to ground, completing the output capacitor connection.

C101 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output rail as part of parallel ceramic output capacitor bank.
2	2	GND	✅	Connected to ground, completing the output capacitor connection.

C102 - 2242-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output rail as part of parallel ceramic output capacitor bank.
2	2	GND	✅	Connected to ground, completing the output capacitor connection.

R853 - 1130-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCORE	✅	Connected to +VCORE output, forming a permanent load resistor across the DC/DC converter output.
2	2	GND	✅	Connected to ground, completing the load resistor path.

R168 - 1141-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Connected to VCORE-SW switching node, forming the resistor part of an RC snubber network to dampen switching transients.
2	2	$23N3990	✅	Connected to intermediate node of RC snubber network, linking to capacitor C52.

C52 - 2240-0005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3990	✅	Connected to intermediate node of RC snubber network, linking to resistor R168.
2	2	GND	✅	Connected to ground, completing the RC snubber network to dampen switching node ringing.

R37 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	This 0-ohm jumper connects the main power ground (GND) to the analog ground (AGND-VCORE), implementing a single-point star ground connection for the VCORE regulator.
2	2	AGND-VCORE	✅	This 0-ohm jumper connects the main power ground (GND) to the analog ground (AGND-VCORE), implementing a single-point star ground connection for the VCORE regulator.

U26 - NCP81109GMNTXG ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT pin connected to VR_HOT_L net for thermal alert output.
2	SDIO	$24N3490	✅	SDIO pin connected to SVID data interface with 16.9Ω series resistor and 69.8Ω pull-up to +V1P0S.
3	ALERT	$24N3492	✅	ALERT pin connected to SVID alert interface with 0Ω series resistor and DNI pull-up.
4	SCLK	$24N3491	✅	SCLK pin connected to SVID clock interface with 20.0Ω series resistor and 69.8Ω pull-up to +V1P0S.
5	GND	AGND-VGFX	✅	GND pin connected to AGND-VGFX analog ground, which connects to main GND through 0Ω jumper R66.
6	VR_RDY	$24N3598	✅	VR_RDY pin connected to power good output with 0Ω series resistor to VGFX_PG and 1.91kΩ pull-up to +VCC3.
7	VIN1	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
11	VIN2	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
12	VIN3	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
13	VIN4	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
14	VIN5	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
15	VIN6	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
16	VIN7	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
17	VIN8	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors.
8	BST	$24N3593	✅	BST pin connected to bootstrap circuit with 2.20Ω resistor and 0.22µF capacitor to SW1, but associated gate driver outputs GH/GL appear unused.
9	GH		✅	GH pin appears to be unconnected. This may be correct if integrated power stages are used, or an error if external MOSFETs are required.
10	SW1	$24N3595	✅	SW1 pin connected to switch node $24N3595, which connects to bootstrap capacitor.
18	SW2	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output.
25	SW3	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output.
26	SW4	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output.
27	SW5	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output.
28	SW6	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output.
29	SW7	VGFX-SW	✅	SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output.
19	PGND1	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
20	PGND2	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
21	PGND3	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
22	PGND4	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
23	PGND5	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
24	PGND6	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
30	GL		✅	GL pin appears to be unconnected. This may be correct if integrated power stages are used, or an error if external MOSFETs are required.
31	VBOOT	$24N3564	✅	VBOOT pin connected through 100kΩ resistor to AGND-VGFX to set I2C address to 0x1 per text note.
32	GND1	AGND-VGFX	✅	GND1 pin connected to AGND-VGFX analog ground.
33	VCCP	$24N3578	✅	VCCP pin connected to internal LDO output with 1.00Ω resistor to +5VSB and 4.7µF decoupling capacitor.
34	TSENSE	$24N3584	✅	TSENSE pin connected to temperature sensing network with 100kΩ thermistor and 14.0kΩ resistor forming voltage divider.
35	IMAX	$24N3588	✅	IMAX pin connected through 44.2kΩ resistor to AGND-VGFX to set maximum current limit. Text note indicates IMAX = 14A.
36	IOUT	$24N3589	✅	IOUT pin connected through 16.5kΩ resistor and 470pF capacitor to AGND-VGFX for output current monitoring.
37	ILIM	VGFX-ILIM	✅	ILIM pin connected through 15.0kΩ resistor to VGFX-CSCOMP for current limit threshold setting.
38	CSCOMP	VGFX-CSCOMP	✅	CSCOMP pin connected to current sense compensation network with capacitors, resistors, and thermistor for temperature-dependent current limiting.
39	CSSUM	VGFX-CSSUM	✅	CSSUM pin connected to current sense sum network with resistors to sense inductor current through DCR sensing.
40	CSREF	VGFX-CSREF	✅	CSREF pin connected to current sense reference with 1000pF capacitor to GND and 10Ω resistor to output voltage for DCR sensing.
41	FREQ	$24N3542	✅	FREQ pin connected through 18.7kΩ resistor to AGND-VGFX to set switching frequency to 650kHz per text note.
42	COMP	VGFX-COMP	✅	COMP pin connected to voltage loop compensation network with Type III compensator for stable regulation.
43	FB	VGFX-FB	✅	FB pin connected to feedback network with resistor divider from output and compensation components.
44	DIFFOUT	VGFX-DIFFOUT	✅	DIFFOUT pin connected to differential amplifier output with resistors to FB pin and ground.
45	VSN	VR-VGFX-VSN	✅	VSN pin connected to negative remote sense input through 10Ω resistor from a node that connects to GND.
46	VSP	VR-VGFX-VSP	✅	VSP pin connected to positive remote sense input through 100Ω resistor from +VGFX and 0Ω from VCCGT_SENSE.
47	VCC	$24N3610	✅	VCC pin connected to main power supply through 2.20Ω resistor from +5VSB with 1.0µF decoupling capacitor.
48	EN	$24N6011	✅	EN pin connected to enable input with 0Ω pull-up to +VCC and 10kΩ pull-down to GND, enabling converter when +VCC is present.
49	GND_PAD	AGND-VGFX	✅	GND_PAD connected to AGND-VGFX for thermal and electrical grounding of the package.
50	VIN_PAD	+5VSB_SW	✅	VIN_PAD connected to +5VSB_SW input supply for additional current handling.
51	SW_PAD	VGFX-SW	✅	SW_PAD connected to VGFX-SW switch node for additional current handling.

L4 - 3120-0266 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to VGFX-SW switching node from the multiphase buck controller U26. This is the input side of the output filter inductor.
2	2	+VGFX	✅	Connected to +VGFX output rail. The connection topology is correct for a buck converter output inductor. However, there is a significant component rating concern: the inductor is rated for 17.5A, while a schematic text note indicates 'IMAX = 24A' for the output current. This apparent mismatch requires clarification.

SP1 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Solder bridge connecting the output voltage +VGFX to the current sense reference network through R225. This provides DC reference voltage for the current sensing circuit.
2	2	$24N3559	✅	Solder bridge connecting the output voltage +VGFX to the current sense reference network through R225. This provides DC reference voltage for the current sensing circuit.

SP2 - 999-0000005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Solder bridge connecting the switching node VGFX-SW to the current sensing network through R224. This provides AC coupling for current sensing to the CSSUM pin of the controller.
2	2	$24N3558	✅	Solder bridge connecting the switching node VGFX-SW to the current sensing network through R224. This provides AC coupling for current sensing to the CSSUM pin of the controller.

TH3 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	This thermistor provides temperature-dependent current limiting by being part of the current sensing divider network. The connection is correct.
2	2	$24N3557	✅	This thermistor provides temperature-dependent current limiting by being part of the current sensing divider network. The connection is correct.

TH4 - 3880-0004 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	100K@25C thermistor for IC temperature sensing, connected in parallel with R226 (14K) between the TSENSE network and ground.
2	2	GND	✅	100K@25C thermistor for IC temperature sensing, connected in parallel with R226 (14K) between the TSENSE network and ground.

C76 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification.
2	N	GND	✅	330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification.

C77 - 123-0005035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VGFX	✅	330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity, in parallel with C76. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification.
2	N	GND	✅	330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity, in parallel with C76. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification.

C62 - 2220-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-COMP	✅	47pF capacitor providing high-frequency compensation between COMP and FB pins of the voltage regulator. This is part of the Type III compensation network.
2	2	VGFX-FB	✅	47pF capacitor providing high-frequency compensation between COMP and FB pins of the voltage regulator. This is part of the Type III compensation network.

C63 - 2220-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-FB	✅	220pF capacitor in the differential output network, filtering the signal between FB and the intermediate node connected to DIFFOUT through R200.
2	2	$24N3522	✅	220pF capacitor in the differential output network, filtering the signal between FB and the intermediate node connected to DIFFOUT through R200.

C64 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-COMP	✅	2200pF capacitor forming the main compensation network with R198, connecting COMP to an intermediate node that feeds back to FB.
2	2	$24N3524	✅	2200pF capacitor forming the main compensation network with R198, connecting COMP to an intermediate node that feeds back to FB.

R198 - 1120-0032 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3524	✅	3.01K resistor forming part of the Type III compensation network, connecting the intermediate node to FB through C64.
2	2	VGFX-FB	✅	3.01K resistor forming part of the Type III compensation network, connecting the intermediate node to FB through C64.

R199 - 1120-0010 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-FB	✅	1.00K resistor connecting FB to DIFFOUT, providing a feedback path for the differential remote sensing signal.
2	2	VGFX-DIFFOUT	✅	1.00K resistor connecting FB to DIFFOUT, providing a feedback path for the differential remote sensing signal.

R200 - 1121-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3522	✅	47 ohm resistor in the DIFFOUT network, forming a low-pass filter with C63 for damping and filtering the differential sensing signal.
2	2	VGFX-DIFFOUT	✅	47 ohm resistor in the DIFFOUT network, forming a low-pass filter with C63 for damping and filtering the differential sensing signal.

R204 - 1120-0029 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-ILIM	✅	This resistor connects the ILIM pin (pin 37) to the CSCOMP pin (pin 38) of U26, setting the current limit threshold for the voltage regulator.
2	2	VGFX-CSCOMP	✅	This resistor connects the ILIM pin (pin 37) to the CSCOMP pin (pin 38) of U26, setting the current limit threshold for the voltage regulator.

R205 - 1120-0282 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	This resistor connects CSCOMP to an intermediate node (net $24N3557) and is in parallel with thermistor TH3, providing temperature-compensated current sensing.
2	2	$24N3557	✅	This resistor connects CSCOMP to an intermediate node (net $24N3557) and is in parallel with thermistor TH3, providing temperature-compensated current sensing.

R223 - 1120-0037 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3557	✅	This resistor completes the current sensing divider network from the thermistor node to CSSUM (pin 39 of U26).
2	2	VGFX-CSSUM	✅	This resistor completes the current sensing divider network from the thermistor node to CSSUM (pin 39 of U26).

R224 - 1130-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSSUM	✅	This resistor connects CSSUM to the switching node (VGFX-SW through short SP2), implementing DCR current sensing by measuring the voltage across the inductor.
2	2	$24N3558	✅	This resistor connects CSSUM to the switching node (VGFX-SW through short SP2), implementing DCR current sensing by measuring the voltage across the inductor.

R225 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	This resistor connects CSREF to the output voltage (+VGFX through short SP1), providing the reference for DCR current sensing.
2	2	$24N3559	✅	This resistor connects CSREF to the output voltage (+VGFX through short SP1), providing the reference for DCR current sensing.

C113 - 2220-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	This NPO capacitor connects between CSCOMP and CSSUM, providing high-frequency compensation for the current sense loop.
2	2	VGFX-CSSUM	✅	This NPO capacitor connects between CSCOMP and CSSUM, providing high-frequency compensation for the current sense loop.

C166 - 2221-0002 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	This X7R capacitor connects between CSCOMP and CSSUM in parallel with C113, providing additional mid-frequency compensation capacitance for the current sense loop.
2	2	VGFX-CSSUM	✅	This X7R capacitor connects between CSCOMP and CSSUM in parallel with C113, providing additional mid-frequency compensation capacitance for the current sense loop.

C167 - 2220-0035 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	This NPO capacitor connects CSREF to ground, providing high-frequency filtering for the current sense reference voltage.
2	2	GND	✅	This NPO capacitor connects CSREF to ground, providing high-frequency filtering for the current sense reference voltage.

R195 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor for SVID_DATA-R signal with unusually low value of 69.8Ω to 1.0V supply. This value is significantly lower than typical SVID pull-up resistors and could cause excessive current draw, potential VOL specification violations, and reliability concerns.
2	2	SVID_DATA-R	✅	Pull-up resistor for SVID_DATA-R signal with unusually low value of 69.8Ω to 1.0V supply. This value is significantly lower than typical SVID pull-up resistors and could cause excessive current draw, potential VOL specification violations, and reliability concerns.

R197 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor for SVID_CLK-R signal with unusually low value of 69.8Ω to 1.0V supply. This shares the same fundamental issue as R195, with excessive current draw and potential specification violations.
2	2	SVID_CLK-R	✅	Pull-up resistor for SVID_CLK-R signal with unusually low value of 69.8Ω to 1.0V supply. This shares the same fundamental issue as R195, with excessive current draw and potential specification violations.

R193 - 1120-0329 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Series resistor on SVID data line between external SVID_DATA-R signal and U26 SDIO pin. Provides impedance matching, current limiting, and protection for the SVID interface.
2	2	$24N3490	✅	Series resistor on SVID data line between external SVID_DATA-R signal and U26 SDIO pin. Provides impedance matching, current limiting, and protection for the SVID interface.

R194 - 1120-0099 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and U26 SCLK pin. Provides impedance matching, current limiting, and protection for the SVID interface.
2	2	$24N3491	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and U26 SCLK pin. Provides impedance matching, current limiting, and protection for the SVID interface.

R67 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U26 ALERT pin without series resistance.
2	2	$24N3492	✅	Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U26 ALERT pin without series resistance.

R196 - 1120-0330 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Pull-up resistor for SVID alert line, marked DNI (Do Not Install). The alert signal operates without a pull-up in this design, likely because it is driven push-pull or has an external pull-up elsewhere.
2	2	SVID_ALERT-R	✅	Pull-up resistor for SVID alert line, marked DNI (Do Not Install). The alert signal operates without a pull-up in this design, likely because it is driven push-pull or has an external pull-up elsewhere.

C432 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Decoupling capacitor for +V1P0S supply rail used by SVID pull-up resistors. Provides local supply filtering, stability, and energy storage for the pull-up resistor network.
2	2	GND	✅	Decoupling capacitor for +V1P0S supply rail used by SVID pull-up resistors. Provides local supply filtering, stability, and energy storage for the pull-up resistor network.

R203 - 1120-0351 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3542	✅	R203 is an 18.7K resistor connected between the FREQ pin (pin 41) of U26 and analog ground (AGND-VGFX) to set the switching frequency. A nearby text note indicates the target switching frequency is 650kHz.
2	2	AGND-VGFX	✅	R203 is an 18.7K resistor connected between the FREQ pin (pin 41) of U26 and analog ground (AGND-VGFX) to set the switching frequency. A nearby text note indicates the target switching frequency is 650kHz.

R207 - 1120-0115 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3588	✅	Connected to IMAX pin of U26 to set the per-phase current limit. Text note indicates target of 14A.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX, providing the ground reference for current limit setting.

R227 - 1120-0338 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3589	✅	Connected to IOUT pin of U26 for current monitoring. This resistor sets the gain for the current reporting function.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX, providing the ground reference for current monitoring.

C184 - 2220-0025 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3589	✅	Connected to IOUT pin of U26 along with R227 for filtering the current monitoring signal.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX, providing the ground reference for filtering.

C53 - 2222-0014 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3610	✅	Connected to the VCC supply net ($24N3610) which powers U26 through R229. This pin provides the positive terminal for VCC decoupling.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX, providing the ground reference for VCC decoupling. This is the analog ground for the voltage regulator section.

R229 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail, providing the input voltage source for the VCC supply path.
2	2	$24N3610	✅	Connected to net $24N3610 which supplies VCC (pin 47) of U26. The 2.2 ohm resistor provides current limiting and filtering for the controller IC supply.

R846 - 1130-0193 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail, providing the input voltage source for the VCCP supply path.
2	2	$24N3578	✅	Connected to net $24N3578 which supplies VCCP (pin 33) of U26. The 1.0 ohm resistor provides current limiting and filtering for the VCCP supply.

R228 - 1130-0234 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3593	✅	Connected to U26 pin 8 (BST) for bootstrap circuit. This is the input side of the bootstrap charging resistor.
2	2	$24N3596	✅	Connected to bootstrap capacitor C186 pin 1. This is the output side of the bootstrap charging resistor.

C186 - 2222-0008 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3596	✅	Connected through R228 to U26 BST pin. This is the bootstrap capacitor positive terminal.
2	2	$24N3595	✅	Connected to U26 pin 10 (SW1). This is the bootstrap capacitor negative terminal, referenced to the switch node.

R66 - 1121-0001 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	This 0-ohm jumper provides a single-point connection between the main power ground (GND) and the analog ground for the VGFX regulator (AGND-VGFX). This is a standard design practice for switching regulators to minimize noise coupling from power ground into sensitive analog signals.
2	2	AGND-VGFX	✅	This 0-ohm jumper provides a single-point connection between the main power ground (GND) and the analog ground for the VGFX regulator (AGND-VGFX). This is a standard design practice for switching regulators to minimize noise coupling from power ground into sensitive analog signals.

R231 - 1141-0026 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to the switching node VGFX-SW of the buck converter. This is the input to the RC snubber network.
2	2	$24N3623	✅	Connected to the intermediate node $24N3623 of the RC snubber, which connects to snubber capacitor C187.

C187 - 2240-0005 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3623	✅	Connected to the intermediate node $24N3623 of the RC snubber network, between R231 and ground.
2	2	GND	✅	Connected to GND, completing the RC snubber network from the switching node to ground.

U41 - RT8207 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VTTGND	GND	✅	VTTGND is correctly connected to GND as the power ground for the VTT LDO output.
2	VTTSNS	+VDIMM_VTT	✅	VTTSNS is correctly connected to +VDIMM_VTT for remote voltage sensing of the VTT output.
3	GND	GND	✅	GND is correctly connected to the ground plane for analog ground reference.
4	MODE	GND	✅	MODE pin is connected to GND. This pin does not appear in the RT8207P datasheet, suggesting a different package variant.
5	VTTREF	$25N769	✅	VTTREF is connected to a 0.22µF bypass capacitor (C342), which is larger than the datasheet-recommended 33nF but should still function correctly.
6	DEM	$25N1291	✅	DEM pin is connected to a voltage divider network. This pin does not appear in the RT8207P datasheet, suggesting a different package variant.
8	VDDQ	+VDIMM	✅	VDDQ is correctly connected to +VDIMM as the reference input for VTT and VTTREF, and for VDDQ discharge control.
9	FB	$25N987	✅	FB is correctly connected to a resistor divider network (R814/R815) that sets the output voltage to approximately 1.35V for DDR3L.
10	S3	EN_VTT	✅	S3 is correctly connected to EN_VTT signal through R302 for VTT power state control.
11	S5	EN_VDDQ	✅	S5 is correctly connected to EN_VDDQ signal through R300 for overall power enable control.
12	TON	$25N1081	✅	TON is connected to a 464K resistor (R816) to set switching frequency, but the schematic design note specifies 806K for 285kHz operation. The actual 464K resistor will result in approximately 503kHz switching frequency instead of the intended 285kHz, indicating a component value error.
13	PGOOD	DRAM_PWROK	✅	PGOOD is correctly connected as an open-drain output with external pull-up resistor to indicate power good status.
14	VDD	$25N1195	✅	VDD is correctly connected through an RC filter (R813/C380) from VDDP, though the resistor value is 2.2Ω instead of the datasheet-recommended 5.1Ω.
15	VDDP	+5VSB	✅	VDDP is correctly connected to +5VSB with bypass capacitor for the gate driver supply.
16	CS	$25N1238	✅	CS is connected to a 3.83K resistor (R817) for current limit setting. The resulting threshold voltage of 38.3mV is below the datasheet minimum of 50mV, which may affect current limit accuracy.
18	PGND	GND	✅	PGND is correctly connected to GND as the power ground for the low-side MOSFET.
19	LGATE	$25N901	✅	LGATE is correctly connected to the low-side MOSFET gate (Q102 pin 8) for synchronous rectification.
20	PHASE	DDR_PHASE	✅	PHASE is correctly connected to the switch node between the MOSFETs and the output inductor for current sensing and switching.
21	UGATE	$25N897	✅	UGATE is correctly connected to the high-side MOSFET gate (Q102 pin 1) for PWM switching control.
22	BOOT	$25N771	✅	BOOT is correctly connected to the bootstrap circuit with capacitor C309 (0.1µF) between BOOT and PHASE through an optional 4.7-ohm series resistor (R298) for high-side gate drive. The 0.1µF capacitor value matches the typical application circuit in the datasheet.
23	VLDOIN	+VDIMM	✅	VLDOIN is correctly connected to +VDIMM for tracking discharge mode operation of the VTT LDO.
24	VTT	+VDIMM_VTT	✅	VTT is correctly connected to +VDIMM_VTT output with 20µF total capacitance (C361 and C362), meeting the datasheet minimum requirement.
25	GND_PAD	GND	✅	GND_PAD (exposed pad) is correctly connected to GND for thermal dissipation and electrical ground.

Q102 - FDMS3604S ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	Q1G	$25N897	✅	Q1G (G1) gate pin correctly connected to UGATE output from controller U41 for high-side MOSFET drive.
2	VIN_A	DDR3L_VIN	✅	VIN_A/B/C (D1) drain pins correctly connected to DDR3L_VIN input voltage rail with appropriate input capacitance.
3	VIN_B	DDR3L_VIN	✅	VIN_A/B/C (D1) drain pins correctly connected to DDR3L_VIN input voltage rail with appropriate input capacitance.
4	VIN_C	DDR3L_VIN	✅	VIN_A/B/C (D1) drain pins correctly connected to DDR3L_VIN input voltage rail with appropriate input capacitance.
5	PGND_A	GND	✅	PGND_A/B/C (S2) source pins correctly connected to ground for synchronous MOSFET operation.
6	PGND_B	GND	✅	PGND_A/B/C (S2) source pins correctly connected to ground for synchronous MOSFET operation.
7	PGND_C	GND	✅	PGND_A/B/C (S2) source pins correctly connected to ground for synchronous MOSFET operation.
8	Q2G	$25N901	✅	Q2G (G2) gate pin correctly connected to LGATE output from controller U41 for low-side MOSFET drive.
9	PHASE	DDR_PHASE	✅	PHASE pin correctly connected to switching node, output inductor L11, controller feedback, and bootstrap circuit.

L11 - 125-0004454 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_PHASE	✅	Inductor input correctly connected to DDR_PHASE switching node from Q102 for buck converter operation.
2	2	+VDIMM	✅	Inductor output correctly connected to +VDIMM output voltage rail with appropriate output capacitance.

R298 - 110-0004467 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N771	✅	Bootstrap resistor input connected to BOOT pin of RT8207 controller (U41 pin 22). This is the correct connection for a bootstrap circuit in a synchronous buck converter.
2	2	DDR_BST	✅	Bootstrap resistor output connected to intermediate bootstrap node DDR_BST, which connects to bootstrap capacitor C309. This is the correct connection for a bootstrap circuit.

C309 - 123-0001056 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_PHASE	✅	Bootstrap capacitor connection to PHASE switch node (DDR_PHASE). This connects to U41 pin 20 (PHASE), Q102 pin 9 (PHASE), and L11 pin 1, forming the correct bootstrap circuit for the synchronous buck converter.
2	2	DDR_BST	✅	Bootstrap capacitor connection to intermediate bootstrap node DDR_BST, which connects to R298 pin 2. This forms the correct bootstrap circuit topology.

L6 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input pin connected to +5VSB power rail, providing the source voltage for the DDR power stage through the ferrite bead filter.
2	2	DDR3L_VIN	✅	Output pin connected to DDR3L_VIN net, providing filtered input voltage to the DDR switching regulator stage.

L5 - 126-0004457 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input pin connected to +5VSB power rail, providing the source voltage for the DDR power stage through the ferrite bead filter.
2	2	DDR3L_VIN	✅	Output pin connected to DDR3L_VIN net, providing filtered input voltage to the DDR switching regulator stage.

C382 - 2220-0047 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Connected to +VDIMM output rail as part of the feedback compensation network.
2	2	$25N987	✅	Connected to feedback node $25N987 to provide compensation for the feedback loop.

R814 - 1120-0187 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Connected to +VDIMM output rail as the upper resistor in the feedback voltage divider network.
2	2	$25N987	✅	Connected to feedback node $25N987 which feeds into U41 pin 9 (FB).

R815 - 1120-0011 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N987	✅	Connected to feedback node $25N987 as the lower resistor in the feedback voltage divider network.
2	2	GND	✅	Connected to GND to complete the feedback voltage divider.

R816 - 1120-0149 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	R816 sets the switching frequency of the RT8207 DDR memory power controller by connecting +5VSB to the TON pin (U41 pin 12). However, the component value (464K) does not match the design specification documented on the schematic (806K for 285 kHz operation), resulting in a switching frequency of approximately 504 kHz instead of the intended 285 kHz.
2	2	$25N1081	✅	R816 sets the switching frequency of the RT8207 DDR memory power controller by connecting +5VSB to the TON pin (U41 pin 12). However, the component value (464K) does not match the design specification documented on the schematic (806K for 285 kHz operation), resulting in a switching frequency of approximately 504 kHz instead of the intended 285 kHz.

R817 - 1120-0267 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	R817 is part of the current sense circuit for the RT8207 controller, connecting between the VDD and CS pins. Without the RT8207 datasheet, the correct value cannot be verified, but the value of 3.83K appears reasonable and there is no clear evidence of error.
2	2	$25N1238	✅	R817 is part of the current sense circuit for the RT8207 controller, connecting between the VDD and CS pins. Without the RT8207 datasheet, the correct value cannot be verified, but the value of 3.83K appears reasonable and there is no clear evidence of error.

R813 - 110-0004466 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	Connected to net $25N1195, which supplies VDD (pin 14) of U41 (RT8207). Forms an RC filter with C380 to provide filtered power to the controller IC.
2	2	+5VSB	✅	Connected to +5VSB supply rail. Provides the input voltage for the filtered VDD supply to U41.

C379 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Provides the ground reference for the +5VSB decoupling capacitor.
2	2	+5VSB	✅	Connected to +5VSB supply rail. Provides local decoupling for the 5V standby supply near the RT8207 controller.

C380 - 123-0001066 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Provides the ground reference for the VDD decoupling capacitor.
2	2	$25N1195	✅	Connected to net $25N1195 (VDD of U41). Provides local decoupling for the RT8207 controller's VDD pin and completes the RC filter with R813.

R300 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SLP_S4_L	✅	0-ohm resistor connecting SLP_S4_L sleep signal to EN_VDDQ, which controls U41 pin 11 (S5) to enable/disable VDDQ output based on S4 sleep state.
2	2	EN_VDDQ	✅	0-ohm resistor connecting SLP_S4_L sleep signal to EN_VDDQ, which controls U41 pin 11 (S5) to enable/disable VDDQ output based on S4 sleep state.

R810 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1291	✅	10K pull-up resistor connecting U41 pin 6 (DEM) to +5VSB supply, configuring the mode control pin.
2	2	+5VSB	✅	10K pull-up resistor connecting U41 pin 6 (DEM) to +5VSB supply, configuring the mode control pin.

R302 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SLP_S3_L	✅	0-ohm resistor connecting SLP_S3_L sleep signal to EN_VTT, which controls U41 pin 10 (S3) to enable/disable VTT output based on S3 sleep state.
2	2	EN_VTT	✅	0-ohm resistor connecting SLP_S3_L sleep signal to EN_VTT, which controls U41 pin 10 (S3) to enable/disable VTT output based on S3 sleep state.

C342 - 123-0003769 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is correctly connected to GND, providing the ground reference for the VTTREF filtering capacitor.
2	2	$25N769	✅	Pin 2 is correctly connected to net $25N769 (VTTREF pin 5 of U41), providing filtering for the VTT reference voltage input of the RT8207 controller.

R124 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DRAM_S4_PWROK	✅	10K pull-up resistor from DRAM_S4_PWROK to +VDIMM (1.35V output). This pulls up the PGOOD signal from U41 to the output voltage, creating a logical AND function where the signal is high only when both the IC asserts PGOOD and the output voltage is present.
2	2	+VDIMM	✅	10K pull-up resistor from DRAM_S4_PWROK to +VDIMM (1.35V output). This pulls up the PGOOD signal from U41 to the output voltage, creating a logical AND function where the signal is high only when both the IC asserts PGOOD and the output voltage is present.

R293 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DRAM_S4_PWROK	✅	0-ohm jumper resistor connecting DRAM_PWROK from U41 pin 13 (PGOOD) to DRAM_S4_PWROK, which is pulled up to +VDIMM through R124. This allows for easy modification of the power good signal routing.
2	2	DRAM_PWROK	✅	0-ohm jumper resistor connecting DRAM_PWROK from U41 pin 13 (PGOOD) to DRAM_S4_PWROK, which is pulled up to +VDIMM through R124. This allows for easy modification of the power good signal routing.

R24 - 110-0002560 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Upper feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator.
2	2	+V1P8S_FB	✅	Upper feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator.

R25 - 110-0004490 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator.
2	2	+V1P8S_FB	✅	Lower feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator.

R23 - 110-0002058 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Pull-up resistor correctly configured to pull the PGOOD signal to the output voltage level.
2	2	+V1P8S_PGD	✅	Pull-up resistor correctly configured to pull the PGOOD signal to the output voltage level.

R22 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1P8V_EN	✅	Zero-ohm jumper correctly provides direct connection between enable signals for power sequencing.
2	2	+V1P8S_EN	✅	Zero-ohm jumper correctly provides direct connection between enable signals for power sequencing.

U21 - APL5933 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P8S_PGD	✅	PGOOD pin correctly connected to +V1P8S_PGD net with pull-up resistor R23 to output voltage.
2	EN	+V1P8S_EN	✅	EN pin correctly connected to +V1P8S_EN, which is controlled by sequencing circuit through Q3 and R125.
3	VIN	+PS_3VSB	✅	VIN pin correctly connected to +PS_3VSB input supply with bypass capacitor C3.
4	VDD	+PS_3VSB	✅	VDD pin correctly connected to +PS_3VSB, tied together with VIN pin.
5	NC		✅	NC pin correctly left unconnected as specified.
6	VOUT	+V1P8S	✅	VOUT pin correctly connected to +V1P8S output with adequate output capacitance.
7	ADJ	+V1P8S_FB	✅	ADJ pin correctly connected to feedback network that sets output to approximately 1.816V.
8	GND1	GND	✅	GND1 and GND2 pins correctly connected to ground plane.
9	GND2	GND	✅	GND1 and GND2 pins correctly connected to ground plane.

Q5 - RXR035N03 ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
G	GATE	1P35V_EN	❌	Gate is connected to enable signal 1P35V_EN through series resistor R134 (1K). Critical issue: VGS may be insufficient to meet the schematic design constraint 'VGS should > 2V' if +VCC is 3.3V, resulting in VGS ≈ 1.95V and potentially higher RDS(on) and power dissipation. Pin G (GATE) is connected to net 1P35V_EN (from schematic) 1P35V_EN is driven by V1P0S_PG through resistor R134 (1K ohm) (from schematic) V1P0S_PG is the power-good output from LDO U38 pin 7 (POK) (from schematic) V1P0S_PG is pulled up to +VCC through R319 (10K ohm) (from schematic) C105 (0.1uF) provides gate-to-ground filtering (from schematic) Schematic note near Q5 explicitly states 'VGS should > 2V' as a design constraint (from schematic) Pin G is the Gate terminal per the TSMT3 package (pin 3) (from datasheet RXR035N03, page 11) Gate threshold voltage VGS(th) ranges from 1.0V to 2.5V at VDS=10V, ID=1mA (from datasheet RXR035N03, page 2) RDS(on) at VGS=10V is 35mΩ typical, 50mΩ maximum (from datasheet RXR035N03, page 2) RDS(on) at VGS=4.5V is 45mΩ typical, 65mΩ maximum (from datasheet RXR035N03, page 2) RDS(on) at VGS=4.0V is 50mΩ typical, 70mΩ maximum (from datasheet RXR035N03, page 2) When Q5 is fully on, source voltage VS is approximately 1.35V (+V1P35S) (reasoning) Gate voltage VG equals V1P0S_PG, which is pulled up to +VCC when the power good signal is asserted (reasoning) VGS = VG - VS = +VCC - 1.35V (reasoning) If +VCC is 3.3V (common supply voltage), then VGS = 3.3V - 1.35V = 1.95V (reasoning) VGS of 1.95V does NOT meet the schematic design constraint 'VGS should > 2V' (reasoning) For VGS > 2V with VS = 1.35V, the gate voltage must be VG > 3.35V, requiring +VCC to be at least 3.35V (reasoning) If +VCC is 5V, then VGS = 5V - 1.35V = 3.65V, which meets the constraint with adequate margin (reasoning) At marginal VGS levels near threshold, RDS(on) increases significantly, potentially 2-3x higher than specified values (reasoning) Higher RDS(on) at insufficient VGS will increase power dissipation beyond calculated values (reasoning) The schematic notes 'VGS=10V Rds(on)=65m MAX' and 'VGS=5V Rds(on)=90m MAX' appear to be conservative estimates or may reference different conditions than the datasheet specifications (reasoning) Recommend verifying that +VCC is at least 3.35V, preferably 5V, to ensure VGS > 2V and reliable MOSFET operation with specified RDS(on) values (reasoning)
D	DRAIN	+VDIMM	✅	Drain is connected to +VDIMM input power rail. This is the input side of the high-side load switch configuration.
S	SOURCE	+V1P35S	✅	Source is correctly connected to +V1P35S output rail (1.35V). At maximum current of 3.5A, power dissipation (0.8-0.86W) exceeds FR4 board thermal limit (0.76W) but remains within ceramic board limit (1.0W). Thermal management must be verified for FR4 implementations.

R134 - 110-0001923 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	Connected to V1P0S_PG power good signal, which is pulled up to +VCC through R319 (10K) and driven by U38 pin 7 (POK). This signal indicates when the +V1P0S rail is within regulation.
2	2	1P35V_EN	✅	Connected to 1P35V_EN, which drives the gate of Q5 through this 1K resistor. The resistor provides gate current limiting and slew rate control for the MOSFET gate drive.

R120 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Connected to +V1P35S output voltage rail (1.35V). This resistor provides a high-impedance sensing path from the output voltage for power sequencing control.
2	2	1P35V_PWG	✅	Connected to 1P35V_PWG, which drives the base of Q3 (dual NPN transistor) for power sequencing control. When +V1P35S is high, R120 pulls up 1P35V_PWG to turn on Q3 for downstream rail sequencing.

U38 - APL5912KAC-TRGS-X ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
5	VIN-2	+VDIMM	❌	Input pins connected to +VDIMM rail. Critical design issue: upstream MOSFET Q5 is rated for 3.5A maximum, but the required load current is approximately 4.9A (1.3A + 3.6A per schematic notes), creating a current bottleneck. Additionally, there is a circular dependency in the power sequencing that requires careful startup analysis. Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic) Both input pins are paralleled to handle high input current for the 5A LDO (reasoning) Input capacitors C118 (10uF) and C336 (10uF) provide 20uF total input capacitance (from schematic) +VDIMM is sourced from +V1P35S through MOSFET Q5 (RXR035N03) (from schematic) Q5 gate is controlled by 1P35V_EN signal (from schematic) 1P35V_EN is driven by V1P0S_PG (U38 power good output pin 7) through R134 (1K) (from schematic) This creates a circular dependency: U38 requires +VDIMM to operate, but +VDIMM requires Q5 to be enabled, which requires V1P0S_PG from U38 (reasoning) V1P0S_PG is pulled up to +VCC through R319 (10K), which may provide initial gate voltage to Q5 if +VCC is available before +VDIMM (from schematic) Schematic note indicates 'MAX CURRENT = 5A' for U38 (APL5912) (from schematic) Schematic notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic) Schematic note indicates 'Id MAX = 3.5 Amps' for Q5 (RXR035N03) (from schematic) For an LDO regulator, input current approximately equals output current (reasoning) Required input current of approximately 4.9A exceeds Q5's 3.5A maximum rating by 40% (reasoning) This creates a fundamental current bottleneck where Q5 cannot supply sufficient current to U38 for the specified load (reasoning) Q5 will operate beyond its maximum rating, potentially causing overheating, voltage drop, or device failure (reasoning) Recommendation: Replace Q5 with a higher current rated MOSFET (≥5A), or reduce the load current to below 3.5A (reasoning)
9	VIN-1	+VDIMM	❌	Input pins connected to +VDIMM rail. Critical design issue: upstream MOSFET Q5 is rated for 3.5A maximum, but the required load current is approximately 4.9A (1.3A + 3.6A per schematic notes), creating a current bottleneck. Additionally, there is a circular dependency in the power sequencing that requires careful startup analysis. Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic) Both input pins are paralleled to handle high input current for the 5A LDO (reasoning) Input capacitors C118 (10uF) and C336 (10uF) provide 20uF total input capacitance (from schematic) +VDIMM is sourced from +V1P35S through MOSFET Q5 (RXR035N03) (from schematic) Q5 gate is controlled by 1P35V_EN signal (from schematic) 1P35V_EN is driven by V1P0S_PG (U38 power good output pin 7) through R134 (1K) (from schematic) This creates a circular dependency: U38 requires +VDIMM to operate, but +VDIMM requires Q5 to be enabled, which requires V1P0S_PG from U38 (reasoning) V1P0S_PG is pulled up to +VCC through R319 (10K), which may provide initial gate voltage to Q5 if +VCC is available before +VDIMM (from schematic) Schematic note indicates 'MAX CURRENT = 5A' for U38 (APL5912) (from schematic) Schematic notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic) Schematic note indicates 'Id MAX = 3.5 Amps' for Q5 (RXR035N03) (from schematic) For an LDO regulator, input current approximately equals output current (reasoning) Required input current of approximately 4.9A exceeds Q5's 3.5A maximum rating by 40% (reasoning) This creates a fundamental current bottleneck where Q5 cannot supply sufficient current to U38 for the specified load (reasoning) Q5 will operate beyond its maximum rating, potentially causing overheating, voltage drop, or device failure (reasoning) Recommendation: Replace Q5 with a higher current rated MOSFET (≥5A), or reduce the load current to below 3.5A (reasoning)
1	GND	GND	✅	Ground pin correctly connected to GND net.
2	FB	FB_V1P0S	✅	Feedback pin correctly connected to resistor divider network (R136 and R135) with compensation capacitor C119.
3	VOUT-2	+V1P0S	✅	Output pins correctly connected to +V1P0S rail with adequate output capacitance.
4	VOUT-1	+V1P0S	✅	Output pins correctly connected to +V1P0S rail with adequate output capacitance.
6	VCNTL	VCNTL_V1P0S	✅	VCNTL pin connected to +VCC through 10 ohm resistor with 1uF capacitor to ground. Without datasheet, cannot verify if this is the correct configuration.
7	POK	V1P0S_PG	✅	Power good output correctly configured with pull-up resistor to +VCC.
8	EN	1P0V_EN	✅	Enable pin correctly connected to VCORE_GFX_PG through 0 ohm jumper R306.

R136 - 110-0002029 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FB_V1P0S	✅	Upper feedback resistor (40.2K) correctly connected between FB_V1P0S and +V1P0S, setting output voltage to approximately 1.025V.
2	2	+V1P0S	✅	Upper feedback resistor (40.2K) correctly connected between FB_V1P0S and +V1P0S, setting output voltage to approximately 1.025V.

R135 - 110-0004498 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower feedback resistor (143K) correctly connected between GND and FB_V1P0S, completing the feedback divider for 1.0V output.
2	2	FB_V1P0S	✅	Lower feedback resistor (143K) correctly connected between GND and FB_V1P0S, completing the feedback divider for 1.0V output.

R320 - 1120-0022 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCNTL_V1P0S	✅	10Ω resistor connecting VCNTL pin to +VCC. With C117 (1uF), creates 10μs time constant which is unusually fast for typical soft-start applications; function cannot be definitively verified without APL5912KAC-TRGS-X datasheet.
2	2	+VCC	✅	10Ω resistor connecting VCNTL pin to +VCC. With C117 (1uF), creates 10μs time constant which is unusually fast for typical soft-start applications; function cannot be definitively verified without APL5912KAC-TRGS-X datasheet.

R319 - 110-0001875 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	10K pull-up resistor correctly connecting V1P0S_PG to +VCC for power good signal.
2	2	+VCC	✅	10K pull-up resistor correctly connecting V1P0S_PG to +VCC for power good signal.

R306 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_GFX_PG	✅	0Ω jumper correctly connecting VCORE_GFX_PG to 1P0V_EN for power sequencing.
2	2	1P0V_EN	✅	0Ω jumper correctly connecting VCORE_GFX_PG to 1P0V_EN for power sequencing.

R151 - 110-0001853 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	R151 is a 0-ohm jumper correctly implementing power sequencing by connecting the 1.0V rail power good signal to the 1.8V regulator enable input.
2	2	+V1P8A_EN	✅	R151 is a 0-ohm jumper correctly implementing power sequencing by connecting the 1.0V rail power good signal to the 1.8V regulator enable input.

R150 - 110-0002560 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	Pin 1 is correctly connected to +V1P8A_FB as the upper feedback resistor for U20's output voltage adjustment.
2	2	+V1P8A	✅	Pin 2 is correctly connected to +V1P8A output.

R153 - 110-0002726 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	Pin 1 is correctly connected to +V1P8A_FB as the lower feedback resistor for U20's output voltage adjustment.
2	2	GND	✅	Pin 2 is correctly connected to GND.

U20 - NCP606 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN1	+PS_3VSB	✅	VIN1 is correctly connected to +PS_3VSB (3.3V standby rail) to provide input power to the regulator.
2	GND	GND	✅	GND is correctly connected to the ground plane.
3	EN	+V1P8A_EN	✅	EN is correctly connected to +V1P8A_EN, which is driven by +V1P0A_PWRGD through R151 (0Ω) to implement power sequencing.
4	VOUT	+V1P8A	✅	VOUT is correctly connected to +V1P8A output rail with appropriate output capacitance.
5	SENSE/ADJ	+V1P8A_FB	✅	SENSE/ADJ is correctly connected to the feedback divider network (R150 and R153) to set the output voltage to 1.8V.
6	VIN2	+PS_3VSB	✅	VIN2 is correctly connected to +PS_3VSB, tied together with VIN1 as required by the datasheet.
7	GND_PAD	GND	✅	GND_PAD (exposed pad) is correctly connected to ground for thermal management.

R34 - 110-0003781 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Upper feedback resistor correctly configured with 6.04K value to set U24 output voltage to 1.0V in conjunction with R35.
2	2	+V1P0A	✅	Upper feedback resistor correctly configured with 6.04K value to set U24 output voltage to 1.0V in conjunction with R35.

R35 - 110-0004494 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	Lower feedback resistor correctly configured with 23.7K value to set U24 output voltage to 1.0V in conjunction with R34.
2	2	GND	✅	Lower feedback resistor correctly configured with 23.7K value to set U24 output voltage to 1.0V in conjunction with R34.

R32 - 110-0002058 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pull-up resistor for U24 enable pin, correctly configured to pull to +5VSB for power sequencing. The enable voltage exceeds VIN but this is typical and acceptable for most LDO enable pins.
2	2	+V1P0A_ENABLE	✅	Pull-up resistor for U24 enable pin, correctly configured to pull to +5VSB for power sequencing. The enable voltage exceeds VIN but this is typical and acceptable for most LDO enable pins.

R33 - 110-0002058 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB	✅	Pull-up resistor for U24 power good output, correctly configured to pull up to +PS_3VSB for proper open-drain operation.
2	2	+V1P0A_PWRGD	✅	Pull-up resistor for U24 power good output, correctly configured to pull up to +PS_3VSB for proper open-drain operation.

U24 - APL5933 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P0A_PWRGD	✅	PGOOD output is correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB and used for power sequencing through D11.
2	EN	+V1P0A_ENABLE	✅	EN input is pulled up to +5VSB through R32 (4.7K). This may be a concern if the enable pin cannot tolerate 5V when VIN is 3.3V, though it could be intentional for sequencing.
3	VIN	+PS_3VSB	✅	VIN and VDD pins are both correctly connected to +PS_3VSB input supply with appropriate decoupling capacitors.
4	VDD	+PS_3VSB	✅	VIN and VDD pins are both correctly connected to +PS_3VSB input supply with appropriate decoupling capacitors.
5	NC		✅	NC pin is correctly left unconnected.
6	VOUT	+V1P0A	✅	VOUT pin is correctly connected to +V1P0A output with appropriate bulk and decoupling capacitors.
7	ADJ	+V1P0A_FB	✅	ADJ feedback pin is correctly connected to resistor divider R34/R35 that sets output voltage to 1.004V, very close to the target 1.0V.
8	GND1	GND	✅	GND1 and GND2 pins are both correctly connected to ground plane.
9	GND2	GND	✅	GND1 and GND2 pins are both correctly connected to ground plane.

R60 - 110-0001957 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB	✅	Pull-up resistor correctly connected to +PS_3VSB supply.
2	2	PSPUP	✅	Pull-up resistor correctly connected to PSPUP intermediate signal.

R61 - 110-0001957 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Pull-up resistor correctly connected to +VCC3 supply.
2	2	SYS_PWRGD	✅	Pull-up resistor correctly connected to SYS_PWRGD output signal.

R206 - 110-0001951 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PSGOOD	✅	Pull-up resistor correctly connected to PSGOOD signal with appropriate high resistance value for delay circuit.
2	2	+V1P8S	✅	Pull-up resistor correctly connected to +V1P8S supply.

R126 - 110-0002058 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pull-up resistor correctly connected to +5VSB supply.
2	2	1P5V_EN_B	✅	Pull-up resistor correctly connected to 1P5V_EN_B intermediate signal.

R125 - 110-0002058 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Pull-up resistor correctly connected to +VCC supply.
2	2	1P8V_EN	✅	Pull-up resistor correctly connected to 1P8V_EN output signal.

Q1 - MBT3904 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter 1 correctly connected to GND for NPN transistor operation.
2	B1	PSGOOD	✅	Base 1 correctly connected to PSGOOD signal, which is driven by power good AND gate through D11 and pulled up through R206.
3	C2	SYS_PWRGD	✅	Collector 2 correctly connected to SYS_PWRGD output with pull-up resistor R61 to +VCC3.
4	E2	GND	✅	Emitter 2 correctly connected to GND for NPN transistor operation.
5	B2	PSPUP	✅	Base 2 and Collector 1 both connected to PSPUP, forming the intermediate node of a two-stage inverter chain.
6	C1	PSPUP	✅	Base 2 and Collector 1 both connected to PSPUP, forming the intermediate node of a two-stage inverter chain.

Q3 - MBT3904 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter 1 correctly connected to GND for NPN transistor operation.
2	B1	1P35V_PWG	✅	Base 1 correctly connected to 1P35V_PWG power good signal, pulled up to +V1P35S through R120.
3	C2	1P8V_EN	✅	Collector 2 correctly connected to 1P8V_EN output with pull-up resistor R125 to +VCC.
4	E2	GND	✅	Emitter 2 correctly connected to GND for NPN transistor operation.
5	B2	1P5V_EN_B	✅	Base 2 and Collector 1 both connected to 1P5V_EN_B, forming the intermediate node of a two-stage inverter for power sequencing.
6	C1	1P5V_EN_B	✅	Base 2 and Collector 1 both connected to 1P5V_EN_B, forming the intermediate node of a two-stage inverter for power sequencing.

D11 - BAT54A-S ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	Cathode 1 correctly connected to +V1P0A_PWRGD input signal for AND gate function.
2	2	SLP_S3_L	✅	Cathode 2 correctly connected to SLP_S3_L input signal for AND gate function.
3	3	PSGOOD	✅	Common anode correctly connected to PSGOOD output, forming AND gate with pull-up resistor R206.

FB7 - 110-0002124 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Pin 1 is connected to the +VCC3 power rail, serving as the input side of the 0-ohm jumper.
2	2	+VCC3S	✅	Pin 2 is connected to the +VCC3S power rail, serving as the output side of the 0-ohm jumper that supplies power to the CPU.

📤 Upload Missing Datasheets

DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews.

R151, R192, R216, R22, R306, R354, R72, R73, R74 (110-0001853): 📤 Upload a datasheet
R120, R183, R190, R191, R2, R211, R220, R221, R268, R319, R400, R71 (110-0001875): 📤 Upload a datasheet
R134, R208, R234, R259, R94 (110-0001923): 📤 Upload a datasheet
R206 (110-0001951): 📤 Upload a datasheet
R60, R61 (110-0001957): 📤 Upload a datasheet
R179 (110-0001960): 📤 Upload a datasheet
R257 (110-0001984): 📤 Upload a datasheet
R136 (110-0002029): 📤 Upload a datasheet
R125, R126, R23, R32, R33 (110-0002058): 📤 Upload a datasheet
FB7, R222, R265, R275 (110-0002124): 📤 Upload a datasheet
R150, R24 (110-0002560): 📤 Upload a datasheet
R213, R38, R39 (110-0002631): 📤 Upload a datasheet
R153 (110-0002726): 📤 Upload a datasheet
R240, R242, R258 (110-0003059): 📤 Upload a datasheet
R34 (110-0003781): 📤 Upload a datasheet
R132 (110-0004465): 📤 Upload a datasheet
R255 (110-0004474): 📤 Upload a datasheet
R217, R218, R239 (110-0004476): 📤 Upload a datasheet
R25 (110-0004490): 📤 Upload a datasheet
R35 (110-0004494): 📤 Upload a datasheet
R135 (110-0004498): 📤 Upload a datasheet
R40 (110-0004695): 📤 Upload a datasheet
R832, R833, R834, R835 (1120-0003): 📤 Upload a datasheet
R89 (1120-0010): 📤 Upload a datasheet
R827, R828, R829, R830, R831, R851 (1120-0011): 📤 Upload a datasheet
R836 (1120-0018): 📤 Upload a datasheet
R108, R320, R65 (1120-0022): 📤 Upload a datasheet
R91, R92 (1120-0025): 📤 Upload a datasheet
R95 (1120-0029): 📤 Upload a datasheet
R88 (1120-0032): 📤 Upload a datasheet
R106 (1120-0037): 📤 Upload a datasheet
R167 (1120-0052): 📤 Upload a datasheet
R131 (1120-0055): 📤 Upload a datasheet
R81 (1120-0099): 📤 Upload a datasheet
R105 (1120-0115): 📤 Upload a datasheet
R843, R844 (1120-0203): 📤 Upload a datasheet
R96 (1120-0282): 📤 Upload a datasheet
R80 (1120-0329): 📤 Upload a datasheet
R85, R86, R87 (1120-0330): 📤 Upload a datasheet
R146 (1120-0338): 📤 Upload a datasheet
R93 (1120-0351): 📤 Upload a datasheet
R37, R62, R63, R64, R78, R79, R840, R841, R842, R849 (1121-0001): 📤 Upload a datasheet
R90 (1121-0025): 📤 Upload a datasheet
R107 (1130-0002): 📤 Upload a datasheet
R853 (1130-0011): 📤 Upload a datasheet
R845 (1130-0193): 📤 Upload a datasheet
R154, R166 (1130-0234): 📤 Upload a datasheet
R168 (1141-0026): 📤 Upload a datasheet
C10, C11, C12, C13, C177, C178, C179, C180 (123-0001038): 📤 Upload a datasheet
C205, C206, C207, C208, C65 (123-0001056): 📤 Upload a datasheet
C26, C27 (123-0001066): 📤 Upload a datasheet
C252, C253 (123-0001107): 📤 Upload a datasheet
C164, C201, C224, C225 (123-0001176): 📤 Upload a datasheet
C148 (123-0004408): 📤 Upload a datasheet
C129, C76, C77, C87 (123-0005035): 📤 Upload a datasheet
L11 (125-0004454): 📤 Upload a datasheet
L3 (125-0004501): 📤 Upload a datasheet
FB3 (126-0001423): 📤 Upload a datasheet
FB1, FB11, FB4, FB5, L12, L13, L5, L6 (126-0004457): 📤 Upload a datasheet
D3 (130-0004403): 📤 Upload a datasheet
Y1 (145-0004789): 📤 Upload a datasheet
X1, Y2 (145-0004792): 📤 Upload a datasheet
P2 (158-0001269): 📤 Upload a datasheet
P1 (158-0004513): 📤 Upload a datasheet
J10 (158-0004534): 📤 Upload a datasheet
C35 (2220-0002): 📤 Upload a datasheet
C36 (2220-0014): 📤 Upload a datasheet
C39, C47 (2220-0025): 📤 Upload a datasheet
C45 (2220-0035): 📤 Upload a datasheet
C429, C430, C431 (2220-0039): 📤 Upload a datasheet
C34 (2221-0001): 📤 Upload a datasheet
C37, C40 (2221-0002): 📤 Upload a datasheet
C38 (2221-0004): 📤 Upload a datasheet
C425 (2221-0017): 📤 Upload a datasheet
C50 (2222-0008): 📤 Upload a datasheet
C24, C428 (2222-0014): 📤 Upload a datasheet
C25, C426, C427, C433, C46 (2222-0016): 📤 Upload a datasheet
C28 (2232-0012): 📤 Upload a datasheet
C48 (2232-0016): 📤 Upload a datasheet
C52 (2240-0005): 📤 Upload a datasheet
C101, C102, C88, C89, C90 (2242-0014): 📤 Upload a datasheet
J5, J6, J7 (258-0002513): 📤 Upload a datasheet
USB1 (258-0004503): 📤 Upload a datasheet
J1 (258-0004612): 📤 Upload a datasheet
J4 (258-0004869): 📤 Upload a datasheet
JP1 (258-0005019): 📤 Upload a datasheet
FB12 (3044-0010): 📤 Upload a datasheet
FB13 (3044-0012): 📤 Upload a datasheet
L8 (3120-0183): 📤 Upload a datasheet
L18, L4 (3120-0266): 📤 Upload a datasheet
CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17 (3142-0014): 📤 Upload a datasheet
J11 (3362-0042): 📤 Upload a datasheet
J8 (3430-0212): 📤 Upload a datasheet
BH1 (353-0003073): 📤 Upload a datasheet
FL1 (3750-0010): 📤 Upload a datasheet
SW1 (3770-0026): 📤 Upload a datasheet
TH1, TH2, TH3, TH4 (3880-0004): 📤 Upload a datasheet
U42 (4300-0071): 📤 Upload a datasheet
U5, U6 (4327-0009): 📤 Upload a datasheet
U19 (4327-0010): 📤 Upload a datasheet
D10, D5 (4536-0009): 📤 Upload a datasheet
D1, D2 (4560-0045): 📤 Upload a datasheet
D13 (4620-0026): 📤 Upload a datasheet
TP17, TP18 (999-0000003): 📤 Upload a datasheet
SP1, SP2, SP3, SP4 (999-0000005): 📤 Upload a datasheet
U11 (AD42): 📤 Upload a datasheet
U38 (APL5912KAC-TRGS-X): 📤 Upload a datasheet
U21, U24 (APL5933): 📤 Upload a datasheet
D11, D4, D6 (BAT54A-S): 📤 Upload a datasheet
D8 (BAT754C): 📤 Upload a datasheet
Q2, Q9 (BAV99-7-F-S-X): 📤 Upload a datasheet
L1 (BKP2125HS221-T): 📤 Upload a datasheet
U25, U26 (NCP81109GMNTXG): 📤 Upload a datasheet
U35 (NCT3012S-X): 📤 Upload a datasheet
U18 (NTB0104GU12): 📤 Upload a datasheet
U4, U7 (NTS0102GT): 📤 Upload a datasheet
U10, U14, U15, U16, U17 (NTS0104GU12): 📤 Upload a datasheet
U29 (TPD4USB30): 📤 Upload a datasheet

_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 355 component(s) to review, and found 8 potential issue(s) in 9 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary>Component Details</summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AK12 | DDI0_RCOMP_P | DDI_RCOMP_N | ❌ | <details><summary>DDI0_RCOMP pins are swapped. Pin AK13 uses overline notation (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅) indicating negative polarity but connects to DDI_RCOMP_P net, while pin AK12 labeled DDI0_RCOMP_P (positive) connects to DDI_RCOMP_N net.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,31.55,45.57,39.05" aspect-ratio="1.29" } <ul><li>Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in the schematic (from schematic)</li><li>Pin AK12 is labeled DDI0_RCOMP_P in the schematic (from schematic)</li><li>Pin AK13 connects to net DDI_RCOMP_P (from schematic)</li><li>Pin AK12 connects to net DDI_RCOMP_N (from schematic)</li><li>Overline notation in electronics indicates negative, inverted, or complement signals (reasoning)</li><li>The _P suffix in pin names indicates positive polarity (reasoning)</li><li>Pin AK12 is described as DDI0_RCOMP_P (positive) in the datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>Pin AK13 with overline notation should be the negative RCOMP signal (reasoning)</li><li>The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning)</li><li>The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning)</li><li>The connections should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)</li><li>R217 (402 ohm) correctly connects between the two RCOMP nets, but the CPU pin assignments need correction (from schematic)</li></ul></details> | | AK13 | ~DDI0_RCOMP | DDI_RCOMP_P | ❌ | <details><summary>DDI0_RCOMP pins are swapped. Pin AK13 uses overline notation (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅) indicating negative polarity but connects to DDI_RCOMP_P net, while pin AK12 labeled DDI0_RCOMP_P (positive) connects to DDI_RCOMP_N net.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,38.46" aspect-ratio="1.29" } <ul><li>Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in the schematic (from schematic)</li><li>Pin AK12 is labeled DDI0_RCOMP_P in the schematic (from schematic)</li><li>Pin AK13 connects to net DDI_RCOMP_P (from schematic)</li><li>Pin AK12 connects to net DDI_RCOMP_N (from schematic)</li><li>Overline notation in electronics indicates negative, inverted, or complement signals (reasoning)</li><li>The _P suffix in pin names indicates positive polarity (reasoning)</li><li>Pin AK12 is described as DDI0_RCOMP_P (positive) in the datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>Pin AK13 with overline notation should be the negative RCOMP signal (reasoning)</li><li>The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning)</li><li>The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning)</li><li>The connections should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)</li><li>R217 (402 ohm) correctly connects between the two RCOMP nets, but the CPU pin assignments need correction (from schematic)</li></ul></details> | | A29 | RESERVED_A29 | GPIO_NC13 | ✅ | RESERVED_A29 pin connected to GPIO_NC13 with 10K pull-down resistor to ground. This configuration prevents the unused GPIO from floating. | | B26 | DDI0_BKLTCTL | | ✅ | DDI0_BKLTCTL backlight control pin for display port 0, left unconnected. This is acceptable for HDMI which doesn't require backlight control. | | B28 | DDI0_VDDEN | | ✅ | DDI0_VDDEN display power enable pin for display port 0, left unconnected. This is acceptable for HDMI which doesn't require this control signal. | | B30 | GPIO_S0_NC12 | $3N566 | ✅ | GPIO_S0_NC12 pin connected to test point TP15. This provides access to the GPIO signal for testing or debugging. | | C26 | DDI0_DDCDATA | HDMI_DDCDAT | ✅ | DDI0_DDCDATA pin connected to HDMI_DDCDAT for HDMI DDC data communication. | | C27 | DDI0_BKLTEN | | ✅ | DDI0_BKLTEN backlight enable pin for display port 0, left unconnected. This is acceptable for HDMI which doesn't require backlight enable. | | C28 | DDI0_DDCCLK | HDMI_DDCCLK | ✅ | DDI0_DDCCLK pin connected to HDMI_DDCCLK for HDMI DDC clock communication. | | D27 | DDI0_HPD | HDMI_HPD_B | ✅ | DDI0_HPD pin connected to HDMI_HPD_B, which is the inverted output of HDMI_HPD through Schmitt trigger U39. The inversion may be intentional depending on system requirements. | | G30 | DDI1_DDCCLK | GND | ✅ | DDI1_DDCCLK pin connected directly to ground. This disables DDC communication on display port 1 as part of the intentionally disabled DDI1 interface. | | J30 | DDI1_BKLTEN | | ✅ | DDI1_BKLTEN backlight enable pin for display port 1, left unconnected as part of disabled DDI1 interface. | | K30 | DDI1_HPD | GND | ✅ | DDI1_HPD pin connected directly to ground. This prevents hot plug detection on display port 1 as part of the intentionally disabled DDI1 interface. | | M30 | DDI1_BKLTCTL | | ✅ | DDI1_BKLTCTL backlight control pin for display port 1, left unconnected as part of disabled DDI1 interface. | | N30 | DDI1_VDDEN | | ✅ | DDI1_VDDEN display power enable pin for display port 1, left unconnected as part of disabled DDI1 interface. | | P14 | RESERVED_P14 | MCSI_RCOMP | ✅ | RESERVED_P14 pin connected to MCSI_RCOMP with 150-ohm termination resistor to ground, providing compensation for MIPI CSI interface on Bay Trail-I variant. | | P30 | DDI1_DDCDATA | DDI1_DDCDAT | ✅ | DDI1_DDCDATA pin connected to DDI1_DDCDAT with 2.2K pull-down resistor to ground. This provides a weak pull-down for the disabled DDI1 interface. | | BA1 | VGA_GREEN | | ✅ | VGA_GREEN analog output pin left unconnected, indicating VGA interface is not used in this design. | | BA3 | VGA_RED | | ✅ | VGA_RED analog output pin left unconnected, indicating VGA interface is not used in this design. | | AB12 | RESERVED_AB12 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AB13 | RESERVED_AB13 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AB14 | RESERVED_AB14 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AB2 | RESERVED_AB2 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AB3 | RESERVED_AB3 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AB7 | RESERVED_AB7 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AB9 | RESERVED_AB9 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AD4 | RESERVED_AD4 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AD6 | RESERVED_AD6 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AF13 | RESERVED_AF13 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AF14 | RESERVED_AF14 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AH13 | RESERVED_AH13 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AH14 | RESERVED_AH14 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AM13 | RESERVED_AM13 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AM14 | RESERVED_AM14 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | C29 | RESERVED_C29 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | C30 | RESERVED_C30 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | D28 | RESERVED_D28 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | D32 | RESERVED_D32 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | D34 | RESERVED_D34 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | F28 | RESERVED_F28 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | F32 | RESERVED_F32 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | F34 | RESERVED_F34 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | J28 | RESERVED_J28 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | J34 | RESERVED_J34 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | K28 | RESERVED_K28 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | K34 | RESERVED_K34 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | M32 | RESERVED_M32 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | N32 | RESERVED_N32 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | R1 | RESERVED_R1 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | R3 | RESERVED_R3 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T2 | RESERVED_T2 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T3 | RESERVED_T3 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T4 | RESERVED_T4 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T6 | RESERVED_T6 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T7 | RESERVED_T7 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T9 | RESERVED_T9 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T10 | RESERVED_T10 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T12 | RESERVED_T12 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T13 | RESERVED_T13 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | T14 | RESERVED_T14 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V10 | RESERVED_V10 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V13 | RESERVED_V13 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V14 | RESERVED_V14 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V2 | RESERVED_V2 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V3 | RESERVED_V3 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V4 | RESERVED_V4 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V6 | RESERVED_V6 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | V9 | RESERVED_V9 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | W1 | RESERVED_W1 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | W3 | RESERVED_W3 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | Y12 | RESERVED_Y12 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | Y13 | RESERVED_Y13 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | Y2 | RESERVED_Y2 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | Y3 | RESERVED_Y3 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | Y4 | RESERVED_Y4 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | Y6 | RESERVED_Y6 | | ✅ | Multiple RESERVED pins left unconnected. This is acceptable for reserved pins that are not used in this design configuration. | | AC1 | DDI1_TXN_3 | | ✅ | DDI1_TXN_3 and DDI1_TXP_3 differential transmit pair for display port 1 lane 3, left unconnected as part of disabled DDI1 interface. | | AC3 | DDI1_TXP_3 | | ✅ | DDI1_TXN_3 and DDI1_TXP_3 differential transmit pair for display port 1 lane 3, left unconnected as part of disabled DDI1 interface. | | BC1 | VGA_DDCCLK | CRT_CLK | ✅ | VGA_DDCCLK pin connected to CRT_CLK with 150-ohm termination resistor to ground. | | AD2 | DDI1_TXN_2 | | ✅ | DDI1_TXN_2 and DDI1_TXP_2 differential transmit pair for display port 1 lane 2, left unconnected as part of disabled DDI1 interface. | | AD3 | DDI1_TXP_2 | | ✅ | DDI1_TXN_2 and DDI1_TXP_2 differential transmit pair for display port 1 lane 2, left unconnected as part of disabled DDI1 interface. | | BC2 | VGA_DDCDATA | CRT_DAT | ✅ | VGA_DDCDATA pin connected to CRT_DAT with 150-ohm termination resistor to ground. | | BD2 | VGA_HSYNC | | ✅ | VGA_HSYNC horizontal sync output pin left unconnected, indicating VGA interface is not used in this design. | | AF2 | DDI1_TXN_1 | | ✅ | DDI1_TXN_1 and DDI1_TXP_1 differential transmit pair for display port 1 lane 1, left unconnected as part of disabled DDI1 interface. | | AF3 | DDI1_TXP_1 | | ✅ | DDI1_TXN_1 and DDI1_TXP_1 differential transmit pair for display port 1 lane 1, left unconnected as part of disabled DDI1 interface. | | AG1 | DDI1_TXN_0 | | ✅ | DDI1_TXN_0 and DDI1_TXP_0 differential transmit pair for display port 1 lane 0, left unconnected as part of disabled DDI1 interface. | | AG3 | DDI1_TXP_0 | | ✅ | DDI1_TXN_0 and DDI1_TXP_0 differential transmit pair for display port 1 lane 0, left unconnected as part of disabled DDI1 interface. | | BF2 | VGA_VSYNC | | ✅ | VGA_VSYNC vertical sync output pin left unconnected, indicating VGA interface is not used in this design. | | AH2 | RESERVED_VSS3 | $3N554 | ✅ | RESERVED_VSS3 pin connected through 0-ohm resistor R43 to ground, providing optional ground connection. | | AH3 | RESERVED_VSS2 | $3N552 | ✅ | RESERVED_VSS2 pin connected through 0-ohm resistor R46 to ground, providing optional ground connection. | | AK2 | DDI1_AUXN | | ✅ | DDI1_AUXN and DDI1_AUXP auxiliary channel pins for display port 1, left unconnected as part of disabled DDI1 interface. | | AK3 | DDI1_AUXP | | ✅ | DDI1_AUXN and DDI1_AUXP auxiliary channel pins for display port 1, left unconnected as part of disabled DDI1 interface. | | AL1 | DDI0_AUXN | | ✅ | DDI0_AUXN and DDI0_AUXP auxiliary channel pins for display port 0, left unconnected. These are typically used for DisplayPort but not for HDMI. | | AL3 | DDI0_AUXP | | ✅ | DDI0_AUXN and DDI0_AUXP auxiliary channel pins for display port 0, left unconnected. These are typically used for DisplayPort but not for HDMI. | | AM2 | RESERVED_VSS1 | $3N589 | ✅ | RESERVED_VSS1 pin connected through 0-ohm resistor R41 to ground, providing optional ground connection. | | AM3 | RESERVED_VSS0 | $3N579 | ✅ | RESERVED_VSS0 pin connected through 0-ohm resistor R42 to ground, providing optional ground connection. | | AP2 | DDI0_TXN_3 | HDMI_CLK_DN | ✅ | DDI0_TXN_3 and DDI0_TXP_3 differential transmit pair connected to HDMI_CLK_DN and HDMI_CLK_DP for HDMI clock output. | | AP3 | DDI0_TXP_3 | HDMI_CLK_DP | ✅ | DDI0_TXN_3 and DDI0_TXP_3 differential transmit pair connected to HDMI_CLK_DN and HDMI_CLK_DP for HDMI clock output. | | AR1 | DDI0_TXN_2 | HDMI_TX0_DN | ✅ | DDI0_TXN_2 and DDI0_TXP_2 differential transmit pair connected to HDMI_TX0_DN and HDMI_TX0_DP for HDMI data lane 0. | | AR3 | DDI0_TXP_2 | HDMI_TX0_DP | ✅ | DDI0_TXN_2 and DDI0_TXP_2 differential transmit pair connected to HDMI_TX0_DN and HDMI_TX0_DP for HDMI data lane 0. | | AT2 | DDI0_TXP_1 | HDMI_TX1_DP | ✅ | DDI0_TXP_1 and DDI0_TXN_1 differential transmit pair connected to HDMI_TX1_DP and HDMI_TX1_DN for HDMI data lane 1. | | AT3 | DDI0_TXN_1 | HDMI_TX1_DN | ✅ | DDI0_TXP_1 and DDI0_TXN_1 differential transmit pair connected to HDMI_TX1_DP and HDMI_TX1_DN for HDMI data lane 1. | | AV2 | DDI0_TXN_0 | HDMI_TX2_DN | ✅ | DDI0_TXN_0 and DDI0_TXP_0 differential transmit pair connected to HDMI_TX2_DN and HDMI_TX2_DP for HDMI data lane 2. | | AV3 | DDI0_TXP_0 | HDMI_TX2_DP | ✅ | DDI0_TXN_0 and DDI0_TXP_0 differential transmit pair connected to HDMI_TX2_DN and HDMI_TX2_DP for HDMI data lane 2. | | AW1 | VGA_IREF | $3N548 | ✅ | VGA_IREF pin connected through 357-ohm resistor R40 to ground, setting the reference current for VGA DAC. | | AY2 | VGA_BLUE | | ✅ | VGA_BLUE analog output pin left unconnected, indicating VGA interface is not used in this design. | | AY3 | VGA_IRTN | GND | ✅ | VGA_IRTN pin connected directly to ground, providing return path for VGA DAC reference current. | </details> <details> <summary>U39 - SN74LVC1G14DCKR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf?ts=1753365169590&ref_url=https%25253A%25252F%25252Fwww.ti.com%25252Fproduct%25252FSN74LVC1G14) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/SN74LVC1G14DCKR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | No Connect pin is unconnected, which is acceptable per datasheet specifications. | | 2 | A | HDMI_HPD | ✅ | Input pin A is connected to HDMI_HPD signal, which is the hot plug detect from the HDMI connector. This input is inverted and conditioned by the Schmitt-trigger. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to GND. | | 4 | Y | HDMI_HPD_B | ✅ | Output pin Y is connected to HDMI_HPD_B, which feeds the CPU's DDI0_HPD input. The inverted and conditioned hot plug detect signal is correctly routed to the display controller. | | 5 | VCC | +V1P8S | ✅ | VCC pin is correctly connected to +V1P8S (1.8V supply), which is within the device's operating range of 1.65V to 5.5V. Bypass capacitor C375 (0.1µF) is present nearby. | </details> <details> <summary>R38 - 150 ohm 1% 1/16W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_DAT | ✅ | 150Ω resistor connected between VGA_DDCDATA (CRT_DAT) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2. | | 2 | 2 | GND | ✅ | 150Ω resistor connected between VGA_DDCDATA (CRT_DAT) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2. | </details> <details> <summary>R39 - 150 ohm 1% 1/16W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_CLK | ✅ | 150Ω resistor connected between VGA_DDCCLK (CRT_CLK) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2. | | 2 | 2 | GND | ✅ | 150Ω resistor connected between VGA_DDCCLK (CRT_CLK) and ground. This resistor is part of the incorrect DDC interface implementation identified at CPU1 pins BC1, BC2. | </details> <details> <summary>R40 - RES_357R_1/10W_1%_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004695) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N548 | ✅ | R40 is a 357Ω resistor connected between VGA_IREF and ground to set the VGA DAC reference current. | | 2 | 2 | GND | ✅ | R40 is a 357Ω resistor connected between VGA_IREF and ground to set the VGA DAC reference current. | </details> <details> <summary>R257 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI1_DDCDAT | ✅ | Connected to DDI1_DDCDAT signal from CPU1 pin P30. | | 2 | 2 | GND | ✅ | Connected to ground to provide pull-down termination. | </details> <details> <summary>R217 - 402 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI_RCOMP_N | ✅ | R217 correctly provides 402-ohm compensation resistance between DDI_RCOMP_N and DDI_RCOMP_P nets. The resistor specification and connection between the two nets is correct; the issue exists at the CPU pin level where the nets are swapped. | | 2 | 2 | DDI_RCOMP_P | ✅ | R217 correctly provides 402-ohm compensation resistance between DDI_RCOMP_N and DDI_RCOMP_P nets. The resistor specification and connection between the two nets is correct; the issue exists at the CPU pin level where the nets are swapped. | </details> <details> <summary>R213 - 150 ohm 1% 1/16W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCSI_RCOMP | ✅ | R213 correctly connects MCSI_RCOMP to GND with 150-ohm resistance, providing impedance calibration for the MIPI CSI interface. | | 2 | 2 | GND | ✅ | R213 correctly connects MCSI_RCOMP to GND with 150-ohm resistance, providing impedance calibration for the MIPI CSI interface. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C24 | ~PROCHOT | VR_HOT_L | ✅ | Processor hot thermal alert signal, correctly pulled up with 73.2 ohm resistor. | | N34 | RESERVED_N34 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | P34 | RESERVED_P34 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | BA12 | SATA_GP0 | SATA_GP0 | ✅ | SATA general purpose signal 0, correctly pulled down with 10K resistor as it is not used. | | BA16 | SATA_RXN_1 | SATA1_RXN | ✅ | SATA port 1 receive negative, correctly AC-coupled with 0.01uF capacitor to mSATA interface. | | BA18 | SD2_CLK | | ✅ | SD2 clock signal, not connected as SD2 interface is not used. | | BA20 | SD2_D2 | | ✅ | SD2 data bit 2, not connected as SD2 interface is not used. | | BA24 | ~MMC1_RST | | ✅ | MMC1 reset signal, not connected as MMC1 interface is not used. | | BA26 | SD3_D3 | SD3_D3 | ✅ | SD3 data bit 3, connected to SD card interface. | | BA30 | LPE_I2S2_FRM | LPE_I2S_FRM | ✅ | I2S frame sync signal from Low Power Engine, correctly pulled up with 10K resistor. | | BB3 | RESERVED_BB3 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | BB4 | RESERVED_BB4 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | BB5 | RESERVED_VSS6 | RESERVED_VSS6 | ✅ | Reserved VSS pin, correctly connected to ground through 0 ohm resistor. | | BB7 | RESERVED_VSS7 | RESERVED_VSS7 | ✅ | Reserved VSS pin, correctly connected to ground through 0 ohm resistor. | | BB10 | RESERVED_VSS4 | ICLK_SATA_TERMP | ✅ | Reserved VSS pin used for SATA clock termination positive, connected to ground through 0 ohm resistor. | | BC10 | RESERVED_VSS5 | ICLK_SATA_TERMN | ✅ | Reserved VSS pin used for SATA clock termination negative, connected to ground through 0 ohm resistor. | | BC18 | SD2_CMD | | ✅ | SD2 command signal, not connected as SD2 interface is not used. | | BC24 | SD3_CD# | SD3_CD# | ✅ | SD3 card detect signal, connected through 0 ohm resistor to SD3_WP pin in an unusual configuration. | | BC30 | LPE_I2S2_DATAOUT | LPE_I2S_DATOUT | ✅ | I2S data output from Low Power Engine, connected through 1K resistor to GPIO unlock signal. | | BD5 | SD3_WP_BD5 | SD3_WP | ✅ | SD3 write protect signal, connected through 0 ohm resistor to SD3_CD# in an unusual configuration specific to Bay Trail-I. | | BD7 | ~PCIE_CLKREQ_1 | CLKREQ1_B | ✅ | PCIe clock request 1 signal, correctly pulled up with 10K resistor. | | BD10 | SATA_TXP1 | SATA1_TXP | ✅ | SATA port 1 transmit positive, correctly AC-coupled with 0.01uF capacitor to mSATA interface. | | BD18 | ~SD2_D3_CD | | ✅ | SD2 data bit 3 / card detect signal, not connected as SD2 interface is not used. | | BD20 | SD2_D1 | | ✅ | SD2 data bit 1, not connected as SD2 interface is not used. | | BD22 | ~SD3_PWREN | /SD3+PWREN | ✅ | SD3 power enable signal, connected to test point for monitoring. | | BD26 | SD3_D1 | SD3_D1 | ✅ | SD3 data bit 1, connected to SD card interface. | | BD28 | LPE_I2S2_DATAIN | LPE_I2S_DATIN | ✅ | I2S data input to Low Power Engine, connected to audio interface. | | BE3 | ~PCIE_CLKREQ_3 | mPCIe_CLKREQ3_B | ✅ | PCIe clock request 3 signal for mini PCIe, correctly pulled up with 10K resistor. | | BF6 | SATA_TXP_0 | SATA0_TXP | ✅ | SATA port 0 transmit positive, correctly AC-coupled with 0.01uF capacitor to connector. | | BF10 | SATA_TXN_1 | SATA1_TXN | ✅ | SATA port 1 transmit negative, correctly AC-coupled with 0.01uF capacitor to mSATA interface. | | BF20 | HDA_LPE_RCOMP | HDA_RCOMP | ✅ | HD Audio / Low Power Engine compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | BF22 | SD3_1P8EN | SD3_1P8EN | ✅ | SD3 1.8V enable signal, connected to test point for monitoring. | | BF26 | SD3_RCOMP | SD3_RCOMP | ✅ | SD3 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | BF28 | LPE_I2S2_CLK | LPE_I2S_CLK | ✅ | I2S clock signal from Low Power Engine, connected to audio interface. | | BG3 | ~PCIE_CLKREQ_0 | CLKREQ0_B | ✅ | PCIe clock request 0 signal, correctly pulled up with 10K resistor. | | BG5 | ~PCIE_CLKREQ_2 | LAN_CLKREQ2_B | ✅ | PCIe clock request 2 signal for LAN, correctly pulled up with 10K resistor. | | BG7 | SATA_TXN_0 | SATA0_TXN | ✅ | SATA port 0 transmit negative, correctly AC-coupled with 0.01uF capacitor to connector. | | BG18 | GPIO_S0_SC_15 | | ✅ | GPIO pin, not connected as it is not used. | | BG19 | HDA_SDI0 | | ✅ | HD Audio serial data input 0, not connected as HD Audio interface is not used. | | BG20 | HDA_SDO | | ✅ | HD Audio serial data output, not connected as HD Audio interface is not used. | | BG21 | HDA_SDI1 | | ✅ | HD Audio serial data input 1, not connected as HD Audio interface is not used. | | BG22 | ~HDA_RST | | ✅ | HD Audio reset signal, not connected as HD Audio interface is not used. | | BH18 | GPIO_S0_SC_14 | | ✅ | GPIO pin, not connected as it is not used. | | BH20 | HDA_SYNC | | ✅ | HD Audio sync signal, not connected as HD Audio interface is not used. | | AK7 | RESERVED_AK7 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | AK9 | RESERVED_AK9 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | BJ21 | HDA_CLK | | ✅ | HD Audio clock signal, not connected as HD Audio interface is not used. | | AP4 | PCIE_TXN_3 | mPCIE_TX_N | ✅ | PCIe transmit negative for lane 3, connected to mini PCIe slot. | | AP6 | PCIE_TXP_3 | mPCIE_TX_P | ✅ | PCIe transmit positive for lane 3, connected to mini PCIe slot. | | AP7 | PCIE_RXN_3 | mPCIE_RX_N | ✅ | PCIe receive negative for lane 3, connected to mini PCIe slot. | | AP9 | PCIE_RXP_3 | mPCIE_RX_P | ✅ | PCIe receive positive for lane 3, connected to mini PCIe slot. | | AP10 | PCIE_RXN_2 | PCIE_RXN2 | ✅ | PCIe receive negative for lane 2, connected to LAN interface. | | AP12 | PCIE_RXP_2 | PCIE_RXP2 | ✅ | PCIe receive positive for lane 2, connected to LAN interface. | | AP13 | PCIE_RCOMP_N_AP13_AP13 | PCIE_RCOMP_N | ✅ | PCIe compensation resistor negative pin, correctly connected with 402 ohm resistor to positive pin. | | AP14 | PCIE_RCOMP_P_AP14_AP14 | PCIE_RCOMP_P | ✅ | PCIe compensation resistor positive pin, correctly connected with 402 ohm resistor to negative pin. | | AT6 | PCIE_TXN_2 | PCIE_TXN2 | ✅ | PCIe transmit negative for lane 2, connected to LAN interface. | | AT7 | PCIE_TXP_2 | PCIE_TXP2 | ✅ | PCIe transmit positive for lane 2, connected to LAN interface. | | AT9 | PCIE_RXN_1 | | ✅ | PCIe receive negative for lane 1, not connected as PCIe lane 1 is not used. | | AT10 | PCIE_RXP_1 | | ✅ | PCIe receive positive for lane 1, not connected as PCIe lane 1 is not used. | | AT13 | PCIE_RXN_0 | | ✅ | PCIe receive negative for lane 0, not connected as PCIe lane 0 is not used. | | AT14 | PCIE_RXP_0 | | ✅ | PCIe receive positive for lane 0, not connected as PCIe lane 0 is not used. | | AT18 | SATA_RCOMP_N_AT18 | SATA_RCOMP_N | ✅ | SATA compensation resistor negative pin, correctly connected with 402 ohm resistor to positive pin. | | AT20 | MMC1_D3 | | ✅ | MMC1 data bit 3, not connected as MMC1 interface is not used. | | AT22 | MMC1_CLK | | ✅ | MMC1 clock signal, not connected as MMC1 interface is not used. | | AT26 | MMC1_D6 | | ✅ | MMC1 data bit 6, not connected as MMC1 interface is not used. | | AT28 | SD3_D0 | SD3_D0 | ✅ | SD3 data bit 0, connected to SD card interface. | | AU16 | SATA_RXP_0 | SATA0_RXP | ✅ | SATA port 0 receive positive, correctly AC-coupled with 0.01uF capacitor to connector. | | AU18 | SATA_RCOMP_P_AU18 | SATA_RCOMP_P | ✅ | SATA compensation resistor positive pin, correctly connected with 402 ohm resistor to negative pin. | | AU20 | MMC1_D7 | | ✅ | MMC1 data bit 7, not connected as MMC1 interface is not used. | | AU22 | MMC1_D1 | | ✅ | MMC1 data bit 1, not connected as MMC1 interface is not used. | | AU26 | MMC1_D5 | | ✅ | MMC1 data bit 5, not connected as MMC1 interface is not used. | | AU28 | SD3_D2 | SD3_D2 | ✅ | SD3 data bit 2, connected to SD card interface. | | AV4 | PCIE_TXN_1 | | ✅ | PCIe transmit negative for lane 1, not connected as PCIe lane 1 is not used. | | AV6 | PCIE_TXP_1 | | ✅ | PCIe transmit positive for lane 1, not connected as PCIe lane 1 is not used. | | AV9 | RESERVED_AV9 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | AV10 | RESERVED_AV10 | | ✅ | Reserved pin, correctly left unconnected per datasheet requirements. | | AV16 | SATA_RXN_0 | SATA0_RXN | ✅ | SATA port 0 receive negative, correctly AC-coupled with 0.01uF capacitor to connector. | | AV20 | MMC1_D0 | | ✅ | MMC1 data bit 0, not connected as MMC1 interface is not used. | | AV22 | MMC1_D2 | | ✅ | MMC1 data bit 2, not connected as MMC1 interface is not used. | | AV26 | MMC1_CMD | | ✅ | MMC1 command signal, not connected as MMC1 interface is not used. | | AV28 | SD3_CMD | SD3_CMD | ✅ | SD3 command signal, connected to SD card interface. | | AY6 | PCIE_TXN_0 | | ✅ | PCIe transmit negative for lane 0, not connected as PCIe lane 0 is not used. | | AY7 | PCIE_TXP_0 | | ✅ | PCIe transmit positive for lane 0, not connected as PCIe lane 0 is not used. | | AY12 | ~SATA_LED | SATA_LED_B | ✅ | SATA activity LED signal, correctly connected through current-limiting resistor to LED driver circuit. | | AY14 | SATA_GP1 | SATA_GP1 | ✅ | SATA general purpose signal 1, correctly pulled down with 10K resistor as it is not used. | | AY16 | SATA_RXP_1 | SATA1_RXP | ✅ | SATA port 1 receive positive, correctly AC-coupled with 0.01uF capacitor to mSATA interface. | | AY18 | MMC1_RCOMP | MMC1_RCOMP | ✅ | MMC1 compensation resistor pin, correctly connected with 49.9 ohm resistor to ground. | | AY20 | SD2_D0 | | ✅ | SD2 data bit 0, not connected as SD2 interface is not used. | | AY24 | MMC1_D4 | | ✅ | MMC1 data bit 4, not connected as MMC1 interface is not used. | | AY26 | SD3_CLK | SD3_CLK | ✅ | SD3 clock signal, connected to SD card interface. | </details> <details> <summary>J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-67490-001.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0003610) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins for SATA signal connector, correctly connected to circuit ground (GND). | | 4 | 4 | GND | ✅ | Ground pins for SATA signal connector, correctly connected to circuit ground (GND). | | 7 | 7 | GND | ✅ | Ground pins for SATA signal connector, correctly connected to circuit ground (GND). | | 2 | 2 | SATA0_TXP_C | ✅ | TX differential pair (A+/A-) correctly connected through AC coupling capacitors to CPU SATA0 transmit pins. | | 3 | 3 | SATA0_TXN_C | ✅ | TX differential pair (A+/A-) correctly connected through AC coupling capacitors to CPU SATA0 transmit pins. | | 5 | 5 | SATA0_RXN_C | ✅ | RX differential pair (B-/B+) correctly connected through AC coupling capacitors to CPU SATA0 receive pins. | | 6 | 6 | SATA0_RXP_C | ✅ | RX differential pair (B-/B+) correctly connected through AC coupling capacitors to CPU SATA0 receive pins. | | 8 | MH1 | GND_EARTH | ✅ | Mounting holes MH1 and MH2 correctly connected to chassis ground (GND_EARTH) for EMI shielding and ESD protection. | | 9 | MH2 | GND_EARTH | ✅ | Mounting holes MH1 and MH2 correctly connected to chassis ground (GND_EARTH) for EMI shielding and ESD protection. | </details> <details> <summary>C177 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_N | ✅ | AC coupling capacitor connecting mSATA_RX_N to SATA1_RXN. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive negative input. | | 2 | 2 | SATA1_RXN | ✅ | AC coupling capacitor connecting mSATA_RX_N to SATA1_RXN. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive negative input. | </details> <details> <summary>C178 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_P | ✅ | AC coupling capacitor connecting mSATA_RX_P to SATA1_RXP. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive positive input. | | 2 | 2 | SATA1_RXP | ✅ | AC coupling capacitor connecting mSATA_RX_P to SATA1_RXP. This capacitor blocks DC while passing the AC differential signal from the mSATA device to the CPU's SATA1 receive positive input. | </details> <details> <summary>C180 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_N | ✅ | AC coupling capacitor connecting mSATA_TX_N to SATA1_TXN. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit negative output to the mSATA device. | | 2 | 2 | SATA1_TXN | ✅ | AC coupling capacitor connecting mSATA_TX_N to SATA1_TXN. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit negative output to the mSATA device. | </details> <details> <summary>C179 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_P | ✅ | AC coupling capacitor connecting mSATA_TX_P to SATA1_TXP. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit positive output to the mSATA device. | | 2 | 2 | SATA1_TXP | ✅ | AC coupling capacitor connecting mSATA_TX_P to SATA1_TXP. This capacitor blocks DC while passing the AC differential signal from the CPU's SATA1 transmit positive output to the mSATA device. | </details> <details> <summary>R190 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ1_B | ✅ | This 10K ohm resistor provides a pull-up from the active-low CLKREQ1_B signal to +V1P8S power rail. | | 2 | 2 | +V1P8S | ✅ | This 10K ohm resistor provides a pull-up from the active-low CLKREQ1_B signal to +V1P8S power rail. | </details> <details> <summary>R2 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mPCIe_CLKREQ3_B | ✅ | This 10K ohm resistor provides a pull-up from the active-low mPCIe_CLKREQ3_B signal to +V1P8S power rail. | | 2 | 2 | +V1P8S | ✅ | This 10K ohm resistor provides a pull-up from the active-low mPCIe_CLKREQ3_B signal to +V1P8S power rail. | </details> <details> <summary>R191 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ0_B | ✅ | This 10K ohm resistor provides a pull-up from the active-low CLKREQ0_B signal to +V1P8S power rail. | | 2 | 2 | +V1P8S | ✅ | This 10K ohm resistor provides a pull-up from the active-low CLKREQ0_B signal to +V1P8S power rail. | </details> <details> <summary>R71 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_CLKREQ2_B | ✅ | This 10K ohm resistor provides a pull-up from the active-low LAN_CLKREQ2_B signal to +V1P8S power rail. | | 2 | 2 | +V1P8S | ✅ | This 10K ohm resistor provides a pull-up from the active-low LAN_CLKREQ2_B signal to +V1P8S power rail. | </details> <details> <summary>R218 - 402 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PCIE_RCOMP_P | ✅ | This 402 ohm resistor is connected between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on CPU1. | | 2 | 2 | PCIE_RCOMP_N | ✅ | This 402 ohm resistor is connected between PCIE_RCOMP_P and PCIE_RCOMP_N, serving as a compensation resistor for the PCIe interface on CPU1. | </details> <details> <summary>R354 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SD3_WP | ✅ | This 0-ohm resistor connects SD3_WP (write protect) to SD3_CD# (card detect) signals. While this ties together two typically independent SD card interface signals, the connection appears to be an intentional design choice specific to the Bay Trail-I processor implementation, as indicated by schematic notes. | | 2 | 2 | SD3_CD# | ✅ | This 0-ohm resistor connects SD3_WP (write protect) to SD3_CD# (card detect) signals. While this ties together two typically independent SD card interface signals, the connection appears to be an intentional design choice specific to the Bay Trail-I processor implementation, as indicated by schematic notes. | </details> <details> <summary>R258 - 49.9 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to GND as the reference for the RCOMP resistor. | | 2 | 2 | SD3_RCOMP | ✅ | Pin 2 is correctly connected to SD3_RCOMP on the CPU, providing impedance compensation for the SD3 interface. | </details> <details> <summary>R242 - 49.9 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDA_RCOMP | ✅ | Connected to HDA_RCOMP pin (BF20) of the Intel Atom E3825 SOC. This provides impedance compensation for the High Definition Audio interface. | | 2 | 2 | GND | ✅ | Connected to GND. This completes the compensation resistor circuit by providing the ground reference. | </details> <details> <summary>R240 - 49.9 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This provides the ground reference for the RCOMP impedance calibration resistor. | | 2 | 2 | MMC1_RCOMP | ✅ | Connected to MMC1_RCOMP (CPU1 pin AY18). This provides impedance calibration for the MMC1 interface. | </details> <details> <summary>R208 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP2 | ✅ | 1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0. | | 2 | 2 | GND | ✅ | 1K pull-down resistor connecting BOM_OP2 to GND, part of hardware identification scheme. This pulls BOM_OP2 LOW to set bit 1 of the hardware ID to 0. | </details> <details> <summary>R234 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP3 | ✅ | 1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0. | | 2 | 2 | GND | ✅ | 1K pull-down resistor connecting BOM_OP3 to GND, part of hardware identification scheme. This pulls BOM_OP3 LOW to set bit 2 of the hardware ID to 0. | </details> <details> <summary>R211 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1. | | 2 | 2 | BOM_OP1 | ✅ | 10K pull-up resistor connecting BOM_OP1 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP1 HIGH to set bit 0 of the hardware ID to 1. | </details> <details> <summary>R400 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1. | | 2 | 2 | BOM_OP4 | ✅ | 10K pull-up resistor connecting BOM_OP4 to +V1P8A, part of hardware identification scheme. This pulls BOM_OP4 HIGH to set bit 3 of the hardware ID to 1. | </details> <details> <summary>R268 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_FRM | ✅ | Connected to LPE_I2S_FRM, which is the I2S frame sync signal from CPU1 pin BA30 (LPE_I2S2_FRM). This pin provides the pullup connection point for the frame sync signal. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing a 10K pull-up for the I2S frame sync signal. This ensures the signal has a defined state. | </details> <details> <summary>R259 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_10_UNLOCK | ✅ | Connected to GPIO_S5_10_UNLOCK signal. This pin provides one end of a series resistor that appears to interface between a GPIO signal and the I2S data output. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | Connected to LPE_I2S_DATOUT, which is the I2S data output signal from CPU1 pin BC30 (LPE_I2S2_DATAOUT). The 1K series resistor allows GPIO_S5_10_UNLOCK to interface with this signal. | </details> <details> <summary>R179 - 220 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001960) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_LED_B | ✅ | Connected to SATA_LED_B net from CPU1 pin AY12 (active-low SATA LED output). Serves as current limiting resistor for SATA LED driver. | | 2 | 2 | SATA_LED_R | ✅ | Connected to SATA_LED_R net, which connects to jumper J6. Provides connection to +V1P8S power rail when jumper is installed. | </details> <details> <summary>J6 - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S power rail. Provides power source for SATA LED circuit when jumper is installed. | | 2 | 2 | SATA_LED_R | ✅ | Connected to SATA_LED_R net, which connects through R179 to the CPU SATA LED output. Completes the SATA LED driver circuit when jumper is installed. | </details> <details> <summary>R72 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS6 | ✅ | Pin 1 is connected to GND, providing a ground connection for the ICLK_SATA_TERMP net through this 0-ohm resistor. | | 2 | 2 | GND | ✅ | Pin 2 is connected to ICLK_SATA_TERMP, which connects to CPU1 pin BB10 (RESERVED_VSS4). This grounds a reserved VSS pin on the processor. | </details> <details> <summary>R192 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS7 | ✅ | Pin 1 is connected to RESERVED_VSS7, which connects to CPU1 pin BB7. This is one side of a 0-ohm resistor used to ground a reserved VSS pin. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, providing the ground connection for the RESERVED_VSS7 net through this 0-ohm resistor. | </details> <details> <summary>R220 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the pull-down resistor on SATA_GP0. | | 2 | 2 | SATA_GP0 | ✅ | Connected to SATA_GP0, providing a 10K ohm pull-down to ground for the SATA general purpose GPIO pin on the CPU. | </details> <details> <summary>R221 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the pull-down resistor on SATA_GP1. | | 2 | 2 | SATA_GP1 | ✅ | Connected to SATA_GP1, providing a 10K ohm pull-down to ground for the SATA general purpose GPIO pin on the CPU. | </details> <details> <summary>R255 - 73.2 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004474) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR_HOT_L | ✅ | Connected to VR_HOT_L net, which connects to CPU1 pin C24 (P̅R̅O̅C̅H̅O̅T̅). This is the processor hot signal from the Intel Atom E3825 SOC. | | 2 | 2 | +V1P0S | ✅ | Connected to +V1P0S (1.0V supply rail), providing pull-up voltage for the PROCHOT signal. The 73.2 ohm value is lower than typical PROCHOT pull-ups but may be specified by Intel for this processor. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A9 | ILB_RTC_X2 | BRTCX2 | ✅ | ILB_RTC_X2 (RTC crystal pin 2) connects to the 32.768kHz crystal with proper load capacitor and feedback resistor. | | A17 | GPIO_S5_3 | mPCIE_WAKEB | ✅ | GPIO_S5_3 is connected to mPCIE_WAKEB for mini PCIe wake signaling with a DNI pull-up resistor. | | A21 | PCU_SPI_MOSI | SOC_SPI_MOSI | ✅ | PCU_SPI_MOSI (SPI master out slave in) connects through a 0 ohm series resistor to the SPI flash interface. | | A25 | SVID_DATA | SVID_DATA | ✅ | SVID_DATA (Serial VID data) connects through a 16.9 ohm series resistor to the voltage regulator interface for dynamic voltage control. | | B7 | PMC_CORE_PWROK | PMC_CORE_PWROK | ✅ | PMC_CORE_PWROK (core power OK signal) connects through a 0 ohm resistor to SYS_PWRGD with an optional DNI decoupling capacitor. | | B8 | ILB_RTC_EXTPAD | BVCCRTC_EXTPAD | ✅ | ILB_RTC_EXTPAD (RTC external pad for battery backup) has proper decoupling capacitor to ground. | | B10 | ~PMC_RSMRST | PMC_RSMRST | ✅ | PMC_RSMRST# (resume reset, active low) has proper pull-up to +3VSB and pull-down to GND with filtering capacitor. | | B18 | GPIO_S5_0 | SOC_GPIO_S5_0 | ✅ | GPIO_S5 pins 0-2 are connected to platform-specific GPIO signals. | | B16 | GPIO_S5_1 | SOC_GPIO_S5_1 | ✅ | GPIO_S5 pins 0-2 are connected to platform-specific GPIO signals. | | C18 | GPIO_S5_2 | SOC_GPIO_S5_2 | ✅ | GPIO_S5 pins 0-2 are connected to platform-specific GPIO signals. | | B22 | PCU_SPI_MISO | SOC_SPI_MISO | ✅ | PCU_SPI_MISO (SPI master in slave out) connects through a 0 ohm series resistor to the SPI flash interface. | | B24 | ~SVID_ALERT | SVID_ALERT | ✅ | SVID_ALERT# (Serial VID alert, active low) connects through a 20 ohm series resistor with a 69.8 ohm pull-up to +V1P0S for voltage regulator alert signaling. | | C9 | ILB_RTC_X1 | BRTCX1 | ✅ | ILB_RTC_X1 (RTC crystal pin 1) connects to the 32.768kHz crystal with proper load capacitor and feedback resistor. | | C11 | ~ILB_RTC_TEST | ILB_RTC_TESTB | ✅ | ILB_RTC_TEST# (RTC test mode, active low) is left floating, which is acceptable per datasheet guidance. | | C12 | ~ILB_RTC_RST | RTCRST_L | ✅ | ILB_RTC_RST (active low) has a proper pull-up resistor to +RTCVCC and decoupling capacitor, ensuring correct RTC reset operation. | | C13 | GPIO_S5_8 | SOC_USB_HOST_EN0 | ✅ | GPIO_S5 pins 8-9 are connected to USB host enable signals for USB port power control. | | A13 | GPIO_S5_9 | SOC_USB_HOST_EN1 | ✅ | GPIO_S5 pins 8-9 are connected to USB host enable signals for USB port power control. | | C17 | GPIO_S5_4 | BOM_OP4 | ✅ | GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration. | | C16 | GPIO_S5_5 | BOM_OP1 | ✅ | GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration. | | B14 | GPIO_S5_6 | BOM_OP2 | ✅ | GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration. | | C15 | GPIO_S5_7 | BOM_OP3 | ✅ | GPIO_S5 pins 4-7 are connected to BOM option signals for board configuration. | | C19 | GPIO_S5_10 | GPIO_S5_10_UNLOCK | ✅ | GPIO_S5_10 is connected to GPIO_S5_10_UNLOCK signal for platform-specific functionality. | | C21 | ~PCU_SPI_CS_11 | SOC_SPI_CS1B | ✅ | PCU_SPI_CS_11# (SPI chip select 1, active low) connects through a DNI 0 ohm resistor, indicating this chip select is not used. | | C22 | PCU_SPI_CLK | SOC_SPI_CLK | ✅ | PCU_SPI_CLK (SPI clock) connects through a 0 ohm series resistor to the SPI flash interface, with an optional DNI capacitor for filtering. | | C23 | ~PCU_SPI_CS_00 | SOC_SPI_CS0B | ✅ | PCU_SPI_CS_00# (SPI chip select 0, active low) connects through a 0 ohm series resistor to the SPI flash interface. | | C25 | SVID_CLK | SVID_CLK-R | ✅ | SVID_CLK (Serial VID clock) is connected to the voltage regulator interface for dynamic voltage control. | | D14 | TAP_TCK | XDP_H_TCK | ✅ | TAP_TCK (JTAG test clock) has a 51 ohm pull-down resistor to ground, which is appropriate for JTAG interface. | | D18 | ~TAP_PRDY | XDP_H_PRDYB | ✅ | TAP_PRDY# (JTAG probe ready, active low) is connected to the debug header for JTAG communication. | | D20 | PMC_ACPRESENT | PMC_ACPRESENT | ✅ | PMC_ACPRESENT (AC power present indicator) has a 2.2K pull-up to +V1P8A. | | D22 | ~PMC_SLP_S3 | PMC_SLP_S3_L | ✅ | PMC_SLP_S3# (sleep S3 state indicator, active low) connects through a level shifter to translate from 1.8V to 3.3V domain. | | D26 | PMC_SUSPWRDNACK | SUSPWRDNACK | ✅ | PMC_SUSPWRDNACK (suspend power down acknowledge) has a 10K pull-up to +V1P8A and connects to a DNI test point. | | F12 | TAP_TDI | XDP_H_TDI | ✅ | TAP_TDI (JTAG test data in) has a 51 ohm pull-up resistor to +V1P8A, which is appropriate for JTAG interface. | | F14 | TAP_TMS | XDP_H_TMS | ✅ | TAP_TMS (JTAG test mode select) has a 51 ohm pull-up resistor to +V1P8A, which is appropriate for JTAG interface. | | F16 | ~TAP_PREQ | XDP_H_PREQB | ✅ | TAP_PREQ# (JTAG probe request, active low) is connected to the debug header for JTAG communication. | | F18 | ~PMC_SLP_S0IX | PMC_SLP_S0IX | ✅ | PMC_SLP_S0IX# (sleep S0ix state indicator, active low) connects to a DNI test point for monitoring. | | F20 | ~PMC_PLTRST | PMC_PLTRST_R_V1P8 | ✅ | PMC_PLTRST# (platform reset output, active low) connects through a level shifter to translate from 1.8V to 3.3V domain. | | F22 | ~PMC_SLP_S4 | PMC_SLP_S4_L | ✅ | PMC_SLP_S4# (sleep S4 state indicator, active low) connects through a level shifter to translate from 1.8V to 3.3V domain. | | F26 | ~PMC_WAKE_PCIE_0 | PMC_PCIE_WAKE_R | ✅ | PMC_WAKE_PCIE_0# (PCIe wake signal, active low) connects through a diode circuit with 1K pull-up for level translation from 3.3V to 1.8V. | | G12 | ~TAP_TRST | XDP_H_TRSTB | ✅ | TAP_TRST# (JTAG test reset, active low) has a 51 ohm pull-down resistor to ground, which is appropriate for JTAG interface. | | G16 | TAP_TDO | XDP_H_TDO | ✅ | TAP_TDO (JTAG test data out) is connected to the debug header without termination, which is correct for an output signal. | | G18 | ~PMC_SUS_STAT | LPCPD_L | ✅ | PMC_SUS_STAT# (suspend status, active low) connects to a DNI test point for monitoring. | | G24 | PMC_SUSCLK0_G24 | PMC_SUSCLK0 | ✅ | PMC_SUSCLK0 (suspend clock 0) connects through a level shifter to translate from 1.8V to 3.3V domain with a DNI pull-up. | | J20 | GPIO_S5_14 | GPIO_S514_J20 | ✅ | GPIO_S5_14 has a 10K pull-up to +V1P8A for platform-specific functionality. | | J24 | GPIO_S5_17 | GPIO_S5_17 | ✅ | GPIO_S5_17 connects to a jumper and has a 10K pull-up to +V1P8S for configuration purposes. | | J26 | ~PMC_PWRBTN | PMC_PWRBTN | ✅ | PMC_PWRBTN# (power button input, active low) connects to a power button circuit with diode OR logic and has a DNI pull-up resistor. | | K24 | GPIO_S5_22 | GPIO_D2_LED_CTRL | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | N24 | GPIO_S5_23 | XDP_H_OBSDATA_A0 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | M20 | GPIO_S5_24 | XDP_H_OBSDATA_A1 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | J18 | GPIO_S5_25 | XDP_H_OBSDATA_A2 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | M18 | GPIO_S5_26 | XDP_H_OBSDATA_A3 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | K18 | GPIO_S5_27 | EXP_GPIO1 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | K20 | GPIO_S5_28 | EXP_GPIO2 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | M22 | GPIO_S5_29 | EXP_GPIO3 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | M24 | GPIO_S5_30 | EXP_GPIO4 | ✅ | GPIO_S5 pins 22-30 are connected to various platform signals including LED control, debug observation data, and expansion GPIO. | | K26 | ~PMC_BATLOW | PMC_BATLOW | ✅ | PMC_BATLOW# (battery low indicator, active low) has a 20K pull-up to +V1P8A. | | N26 | GPIO_RCOMP | GPIO_RCOMP | ✅ | GPIO_RCOMP connects to a 49.9 ohm compensation resistor to ground, which matches the datasheet requirement for GPIO compensation. | | BA28 | SIO_SPI_MISO | SOC_SIO_SPI_MISO | ✅ | SIO_SPI_MISO (SIO SPI master in slave out) is connected to the Serial I/O SPI interface. | | BA34 | ~SIO_UART1_RTS | SIO_UART1_RTSB | ✅ | SIO_UART1_RTS# (UART1 request to send, active low) is connected to the UART1 interface for hardware flow control. | | AD9 | RESERVED_AD9 | | ✅ | Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins. | | AD10 | RESERVED_AD10 | | ✅ | Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins. | | AD12 | RESERVED_AD12 | | ✅ | Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins. | | AT34 | RESERVED | | ✅ | Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins. | | AM10 | RESERVED_AM10 | | ✅ | Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins. | | AM9 | RESERVED_AM9 | | ✅ | Reserved pins are left unconnected, which is the correct configuration per Intel guidance for unused reserved pins. | | AD13 | ICLK_RCOMP | ICLK_RCOMP | ✅ | ICLK_RCOMP connects to a 47.5 ohm compensation resistor to ground, which matches the datasheet requirement for integrated clock compensation. | | AD14 | ICLK_ICOMP | ICLK_ICOMP | ✅ | ICLK_ICOMP connects to a 4.02K compensation resistor to ground, which matches the datasheet requirement for integrated clock compensation. | | BD34 | SIO_UART2_TXD | SIO_UART2_TXD | ✅ | SIO_UART2_TXD (UART2 transmit data) is connected to the UART2 interface. | | AF6 | PCIE_CLKN_00 | | ✅ | PCIE_CLKN_00 and PCIE_CLKP_00 are unconnected, indicating PCIe port 0 is not used in this design. | | AF4 | PCIE_CLKP_00 | | ✅ | PCIE_CLKN_00 and PCIE_CLKP_00 are unconnected, indicating PCIe port 0 is not used in this design. | | AF9 | PCIE_CLKN_11 | | ✅ | PCIE_CLKN_11 and PCIE_CLKP_11 are unconnected, indicating PCIe port 1 is not used in this design. | | AF7 | PCIE_CLKP_11 | | ✅ | PCIE_CLKN_11 and PCIE_CLKP_11 are unconnected, indicating PCIe port 1 is not used in this design. | | BF32 | ~SIO_UART2_CTS | | ✅ | SIO_UART2_CTS# and SIO_UART2_RTS# (UART2 flow control, active low) are unconnected, indicating hardware flow control is not used for UART2. | | BD32 | ~SIO_UART2_RTS | | ✅ | SIO_UART2_CTS# and SIO_UART2_RTS# (UART2 flow control, active low) are unconnected, indicating hardware flow control is not used for UART2. | | BF34 | SIO_UART2_RXD | SIO_UART2_RXD | ✅ | SIO_UART2_RXD (UART2 receive data) is connected to the UART2 interface. | | BG9 | ~PMC_RSTBTN | PMC_RSTBTN | ✅ | PMC_RSTBTN# (reset button input, active low) is connected to the platform reset button circuit. | | AH10 | ICLK_OSCOUT | XTAL25_OUT | ✅ | ICLK_OSCOUT connects to the output of the 25MHz crystal oscillator with 27pF load capacitors. The load capacitance is slightly higher than the 18pF specified in the datasheet but should be acceptable with PCB stray capacitance. | | AH12 | ICLK_OSCIN | XTAL25_IN | ✅ | ICLK_OSCIN connects to the input of the 25MHz crystal oscillator with proper load capacitors and feedback resistor. | | BH7 | PMC_PLT_CLK_00 | | ✅ | Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design. | | BH4 | PMC_PLT_CLK_22 | | ✅ | Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design. | | BH5 | PMC_PLT_CLK_11 | | ✅ | Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design. | | BH6 | PMC_PLT_CLK_44 | | ✅ | Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design. | | BJ9 | PMC_PLT_CLK_55 | | ✅ | Platform clock outputs PMC_PLT_CLK_00, _22, _11, _44, and _55 are unconnected, indicating they are not used in this design. | | BH8 | PMC_PLT_CLK_33 | I2S_MCLK | ✅ | PMC_PLT_CLK_33 is connected to I2S_MCLK, providing a 25MHz master clock for I2S audio interface. | | AK4 | PCIE_CLKN_22 | PCIE_CLK-N2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 provide differential PCIe reference clock for port 2. | | AK6 | PCIE_CLKP_22 | PCIE_CLK-P2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 provide differential PCIe reference clock for port 2. | | AM4 | PCIE_CLKN_33 | mPCIE_REFCLK_N | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 provide differential PCIe reference clock for port 3, used for mini PCIe interface. | | AM6 | PCIE_CLKP_33 | mPCIE_REFCLK_P | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 provide differential PCIe reference clock for port 3, used for mini PCIe interface. | | AT32 | SIO_PWM_11 | SOC_PWM1 | ✅ | SIO_PWM_11 (PWM output 1) is connected to the PWM interface. | | AU32 | SIO_PWM_00 | SOC_PWM0 | ✅ | SIO_PWM_00 (PWM output 0) is connected to the PWM interface. | | AU34 | SIO_UART1_RXD | SIO_UART1_RXD | ✅ | SIO_UART1_RXD (UART1 receive data) is connected to the UART1 interface. | | AV32 | ~SIO_SPI_CS | SOC_SIO_SPI_CS1 | ✅ | SIO_SPI_CS# (SIO SPI chip select, active low) is connected to the Serial I/O SPI interface. | | AV34 | SIO_UART1_TXD | SIO_UART1_TXD | ✅ | SIO_UART1_TXD (UART1 transmit data) is connected to the UART1 interface. | | AY28 | SIO_SPI_MOSI | SOC_SIO_SPI_MOSI | ✅ | SIO_SPI_MOSI (SIO SPI master out slave in) is connected to the Serial I/O SPI interface. | | AY30 | SIO_SPI_CLK | SOC_SIO_SPI_CLK | ✅ | SIO_SPI_CLK (SIO SPI clock) is connected to the Serial I/O SPI interface. | | AY34 | ~SIO_UART1_CTS | SIO_UART1_CTSB | ✅ | SIO_UART1_CTS# (UART1 clear to send, active low) is connected to the UART1 interface for hardware flow control. | </details> <details> <summary>U19 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4327-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the 1.8V supply for the A-side of the level shifter. | | 2 | A1 | PMC_PLTRST_R_V1P8 | ✅ | A1 is correctly connected to PMC_PLTRST_R_V1P8, the 1.8V side of the platform reset signal from the CPU. | | 3 | A2 | PMC_SUSCLK0 | ✅ | A2 is correctly connected to PMC_SUSCLK0, the 1.8V side of the suspend clock signal from the CPU. | | 4 | A3 | PMC_SLP_S4_L | ✅ | A3 is correctly connected to PMC_SLP_S4_L, the 1.8V side of the S4 sleep state signal from the CPU. | | 5 | A4 | PMC_SLP_S3_L | ✅ | A4 is correctly connected to PMC_SLP_S3_L, the 1.8V side of the S3 sleep state signal from the CPU. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 7 | B4 | SLP_S3_L | ✅ | B4 is correctly connected to SLP_S3_L, the 3.3V side of the S3 sleep state signal. | | 8 | B3 | SLP_S4_L | ✅ | B3 is correctly connected to SLP_S4_L, the 3.3V side of the S4 sleep state signal. | | 9 | B2 | SUSCLK_3P3 | ✅ | B2 is correctly connected to SUSCLK_3P3, the 3.3V side of the suspend clock signal. | | 10 | B1 | PMC_PLTRST_L | ✅ | B1 is correctly connected to PMC_PLTRST_L, the 3.3V side of the platform reset signal. | | 11 | VCCB | PWR_BUF1 | ✅ | VCCB is correctly connected to PWR_BUF1, which is derived from +3VSB through R26 (0 ohm), providing the 3.3V supply for the B-side. | | 12 | OE | PMC_OE | ✅ | OE is correctly connected to PMC_OE with a pull-up resistor R57 (2.2K) to +V1P8A, enabling the level shifter by default. | </details> <details> <summary>Y1 - 32.768KHz, ABRACON ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/145-0004789) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BRTCX2 | ✅ | Crystal pin 1 connected to BRTCX2, which connects to CPU RTC oscillator output pin ILB_RTC_X2. Includes 18pF load capacitor C42 to ground and 10M feedback resistor R76 to pin 2. | | 2 | 2 | BRTCX1 | ✅ | Crystal pin 2 connected to BRTCX1, which connects to CPU RTC oscillator input pin ILB_RTC_X1. Includes 18pF load capacitor C43 to ground and 10M feedback resistor R76 to pin 1. | </details> <details> <summary>BH1 - BATTERY HOLDER VERT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/353-0003073) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +VBAT | ✅ | Both positive terminals of the battery holder connected together to +VBAT net. This net connects through R278 (1K current limiting resistor) to the battery backup OR-ing circuit. | | 2 | P2 | +VBAT | ✅ | Both positive terminals of the battery holder connected together to +VBAT net. This net connects through R278 (1K current limiting resistor) to the battery backup OR-ing circuit. | | 3 | N | GND | ✅ | Negative terminal of battery holder correctly connected to GND. | </details> <details> <summary>Y2 - 25.00MHz crystal ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XTAL25_IN | ✅ | Crystal pin connected to CPU main oscillator input with appropriate load capacitor. | | 2 | 2 | GND | ✅ | Ground pins connected to system ground. | | 4 | 4 | GND | ✅ | Ground pins connected to system ground. | | 3 | 3 | XTAL25_OUT | ✅ | Crystal pin connected to CPU main oscillator output with appropriate load capacitor. | </details> <details> <summary>D3 - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE | ✅ | Both anode pins are connected to PMC_PCIE_WAKE net, which is pulled to +3VSB (3.3V) through R27 (2.2K). This parallel connection is intentional for the BAT54A-S dual Schottky diode configuration. | | 2 | 2 | PMC_PCIE_WAKE | ✅ | Both anode pins are connected to PMC_PCIE_WAKE net, which is pulled to +3VSB (3.3V) through R27 (2.2K). This parallel connection is intentional for the BAT54A-S dual Schottky diode configuration. | | 3 | 3 | PMC_PCIE_WAKE_R | ✅ | Cathode pin connected to PMC_PCIE_WAKE_R net, which connects to CPU pin F26 (PMC_WAKE_PCIE_0) and is pulled to +V1P8A (1.8V) through R253 (1K). This provides the output of the wake signal circuit to the CPU. | </details> <details> <summary>D5 - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | +PS_3VSB | ✅ | Anode pin connected to +PS_3VSB (3.3V standby power), serving as the primary power source for the RTC backup circuit. | | A2 | A2 | +VBAT_R | ✅ | Anode pin connected to +VBAT_R (battery voltage through R278 1K resistor), serving as the backup power source for the RTC when primary power is unavailable. | | C | C | +RTCVCC | ✅ | Common cathode pin connected to +RTCVCC, which powers the RTC circuit. The OR-ing diode configuration automatically selects the higher voltage source between +PS_3VSB and +VBAT_R. | </details> <details> <summary>D10 - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4536-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | 3VSB_OK | ✅ | Anode pin connected to 3VSB_OK signal, which is pulled to +3VSB (3.3V) through R162 (1K). This serves as one input to the power button OR-ing circuit. | | A2 | A2 | PMC_PWRBTN | ✅ | Anode pin connected to PMC_PWRBTN signal from CPU1 pin J26 (active-low power button input). R161 (20K pull-up to +V1P8A) is marked DNI, so the pin relies on CPU internal pull-up. | | C | C | PS_OUT_L | ✅ | Common cathode pin connected to PS_OUT_L output signal. The OR-ing diode configuration combines 3VSB_OK and PMC_PWRBTN signals for power control logic. | </details> <details> <summary>R183 - 10K pull-up ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pin 1 connects to +V1P8S (1.8V standby rail), providing the pull-up voltage source for GPIO_S5_17. | | 2 | 2 | GPIO_S5_17 | ✅ | Pin 2 connects to GPIO_S5_17, which goes to CPU1 pin J24 and J7 pin 1. This provides the pull-up function for the GPIO signal. | </details> <details> <summary>J7 - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_17 | ✅ | Pin 1 connects to GPIO_S5_17, which is pulled high to +V1P8S through R183 (10K) and connects to CPU1 pin J24. This forms the signal side of a jumper configuration. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the jumper. When a jumper is installed, it pulls GPIO_S5_17 to ground. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A7 | USB_HSIC_RCOMP | USB_HSIC0_RCOMP | ✅ | USB_HSIC_RCOMP is correctly connected to ground through a 45.3 ohm resistor for USB HSIC impedance calibration. | | B4 | USB_HSIC0_DATA | | ✅ | USB_HSIC0_DATA is left unconnected, which is acceptable if USB HSIC port 0 is not used in this design. | | B5 | USB_HSIC0_STROBE | | ✅ | USB_HSIC0_STROBE is left unconnected, which is acceptable if USB HSIC port 0 is not used in this design. | | B12 | GPIO_S5_43 | | ✅ | GPIO_S5_43 (USB_ULPI_REFCLK) is left unconnected, which is acceptable if USB ULPI is not used in this design. | | B20 | ~USB_OC_11 | SOC_USB_HOST_OC1 | ✅ | USB_OC[1]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection on port 1. | | C7 | USB_RCOMPI | USB_RCOMP | ✅ | USB_RCOMPI is correctly connected to the same net as USB_RCOMPO with a 45.3 ohm resistor to ground for USB impedance calibration. | | C20 | ~USB_OC_00 | SOC_USB_HOST_OC0 | ✅ | USB_OC[0]# is correctly connected with a 10K pull-up resistor to +V1P8A for USB overcurrent detection on port 0. | | D2 | USB_HSIC1_STROBE | | ✅ | USB_HSIC1_STROBE is left unconnected, which is acceptable if USB HSIC port 1 is not used in this design. | | D4 | USB3_RXP0 | USB3_RXP0 | ✅ | USB3_RXP0 is correctly connected as part of the USB 3.0 differential receive pair for port 0. | | D6 | USB_RCOMPO | USB_RCOMP | ✅ | USB_RCOMPO is correctly connected to the same net as USB_RCOMPI with a 45.3 ohm resistor to ground for USB impedance calibration. | | D10 | ICLK_USB_TERM_1 | ICLK_USB_TERM_0 | ✅ | ICLK_USB_TERM_1 is correctly connected to ground through a 1K resistor for USB termination. | | E2 | USB_HSIC1_DATA | | ✅ | USB_HSIC1_DATA is left unconnected, which is acceptable if USB HSIC port 1 is not used in this design. | | E3 | USB3_RXN0 | USB3_RXN0 | ✅ | USB3_RXN0 is correctly connected as part of the USB 3.0 differential receive pair for port 0. | | F10 | ICLK_USB_TERMN | ICLK_USB_TERM_1 | ✅ | ICLK_USB_TERMN is correctly connected to ground through a 1K resistor for USB termination. | | G2 | GPIO_S5_31 | | ✅ | GPIO_S5_31 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | G14 | USB_DN1 | USB_DN1 | ✅ | USB_DN1 is correctly connected as part of the USB 2.0 differential data pair for port 1. | | H3 | GPIO_S5_42 | | ✅ | GPIO_S5_42 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | H4 | RESERVED_H4 | | ✅ | RESERVED_H4 is correctly left unconnected as it is a reserved pin. | | H5 | RESERVED_H5 | | ✅ | RESERVED_H5 is correctly left unconnected as it is a reserved pin. | | H7 | RESERVED_H7 | | ✅ | RESERVED_H7 is correctly left unconnected as it is a reserved pin. | | H8 | RESERVED_H8 | | ✅ | RESERVED_H8 is correctly left unconnected as it is a reserved pin. | | H10 | USB_DN3 | | ✅ | USB_DN3 is left unconnected, which is acceptable if USB port 3 is not used in this design. | | J3 | GPIO_S5_40 | | ✅ | GPIO_S5_40 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | J12 | USB_DN2 | USB_HOST_DN | ✅ | USB_DN2 is correctly connected as part of the USB 2.0 differential data pair for port 2. | | J14 | USB_DP1 | USB_DP1 | ✅ | USB_DP1 is correctly connected as part of the USB 2.0 differential data pair for port 1. | | K2 | GPIO_S5_34 | | ✅ | GPIO_S5_34 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | K3 | GPIO_S5_35 | | ✅ | GPIO_S5_35 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | K6 | USB3_TXP0 | USB3_TXP0 | ✅ | USB3_TXP0 is correctly connected as part of the USB 3.0 differential transmit pair for port 0. | | K7 | USB3_TXN0 | USB3_TXN0 | ✅ | USB3_TXN0 is correctly connected as part of the USB 3.0 differential transmit pair for port 0. | | K10 | USB_DP3 | | ✅ | USB_DP3 is left unconnected, which is acceptable if USB port 3 is not used in this design. | | K12 | USB_DP2 | USB_HOST_DP | ✅ | USB_DP2 is correctly connected as part of the USB 2.0 differential data pair for port 2. | | K16 | USB_DN0 | USB_DN0 | ✅ | USB_DN0 is correctly connected as part of the USB 2.0 differential data pair for port 0. | | L1 | GPIO_S5_33 | | ✅ | GPIO_S5_33 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | L3 | GPIO_S5_39 | | ✅ | GPIO_S5_39 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | M2 | GPIO_S5_36 | | ✅ | GPIO_S5_36 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | M3 | GPIO_S5_32 | | ✅ | GPIO_S5_32 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | M4 | RESERVED_M4 | | ✅ | RESERVED_M4 is correctly left unconnected as it is a reserved pin. | | M6 | RESERVED_M6 | | ✅ | RESERVED_M6 is correctly left unconnected as it is a reserved pin. | | M7 | RESERVED_M7 | | ✅ | RESERVED_M7 is correctly left unconnected as it is a reserved pin. | | M9 | RESERVED_M9 | | ✅ | RESERVED_M9 is correctly left unconnected as it is a reserved pin. | | M10 | RESERVED_M10 | | ✅ | RESERVED_M10 is correctly left unconnected as it is a reserved pin. | | M12 | USB3_REXT0 | USB3_REXT0 | ✅ | USB3_REXT0 is correctly connected to ground through a 1.24K resistor for USB 3.0 impedance calibration. | | M13 | USB_PLL_MON | USB_PLL_MON | ✅ | USB_PLL_MON is correctly connected to a test point for USB PLL monitoring. | | M16 | USB_DP0 | USB_DP0 | ✅ | USB_DP0 is correctly connected as part of the USB 2.0 differential data pair for port 0. | | N3 | GPIO_S5_37 | | ✅ | GPIO_S5_37 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | P2 | GPIO_S5_38 | | ✅ | GPIO_S5_38 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | P3 | GPIO_S5_41 | | ✅ | GPIO_S5_41 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | P6 | RESERVED_P6 | | ✅ | RESERVED_P6 is correctly left unconnected as it is a reserved pin. | | P7 | RESERVED_P7 | | ✅ | RESERVED_P7 is correctly left unconnected as it is a reserved pin. | | P10 | RESERVED_P10 | | ✅ | RESERVED_P10 is correctly left unconnected as it is a reserved pin. | | P12 | RESERVED_P12 | | ✅ | RESERVED_P12 is correctly left unconnected as it is a reserved pin. | | BC12 | GPIO_S0_SC_56 | GPIO_S0_SC_56 | ✅ | GPIO_S0_SC_56 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | BC14 | GPIO_S0_SC_58 | HDMI_CEC | ✅ | GPIO_S0_SC_58 is configured for HDMI_CEC but left floating, which is acceptable if HDMI CEC is not used. | | BC16 | GPIO_S0_SC_61 | PCU_UART3_RXD | ✅ | GPIO_S0_SC_61 is correctly configured as PCU_UART3_RXD and connected through level shifter U6 to the debug UART connector J4. | | BD12 | GPIO_S0_SC_55 | GPIO_S0_SC_55 | ✅ | GPIO_S0_SC_55 is connected to a test point (DNI) for monitoring purposes. | | BD14 | GPIO_S0_SC_57 | PCU_UART3_TXD | ✅ | GPIO_S0_SC_57 is correctly configured as PCU_UART3_TXD and connected through level shifter U6 to the debug UART connector J4. | | BD16 | GPIO_S0_SC_60 | | ✅ | GPIO_S0_SC_60 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | BF14 | GPIO_S0_SC_59 | | ✅ | GPIO_S0_SC_59 is left unconnected, which is acceptable if this GPIO is not needed in the design. | | BF18 | LPC_RCOMP | LPC_RCOMP | ✅ | LPC_RCOMP is correctly connected to ground through a 49.9 ohm resistor for LPC bus impedance calibration. | | BF27 | SIO_I2C4_DATA | | ✅ | SIO_I2C4_DATA is left unconnected, which is acceptable if I2C port 4 is not used in this design. | | BG11 | ~PCU_SMB_ALERT | PCU_SMB_ALERT | ✅ | PCU_SMB_ALERT# is correctly connected with a 10K pull-up resistor to +V1P8S and routed through a 0 ohm jumper to LAN-SMB-ALERT#. | | BG12 | PCU_SMB_DATA | PCU_SMB_DATA | ✅ | PCU_SMB_DATA is correctly connected with a 2.2K pull-up resistor and routed through level shifter U5 to DDR_SMB_DATA. | | BG13 | ILB_LPC_SERIRQ | | ✅ | ILB_LPC_SERIRQ is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BG14 | ILB_LPC_AD_33 | | ✅ | ILB_LPC_AD_33 is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BG15 | ILB_LPC_CLK_00 | | ✅ | ILB_LPC_CLK_00 is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BG16 | ~ILB_LPC_CLKRUN | | ✅ | ILB_LPC_CLKRUN# is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BG17 | ~ILB_LPC_FRAME | | ✅ | ILB_LPC_FRAME# is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BG23 | SIO_I2C0_CLK | | ✅ | SIO_I2C0_CLK is left unconnected, which is acceptable if I2C port 0 is not used in this design. | | BG24 | SIO_I2C1_DATA | SIO_I2C1_SDA | ✅ | SIO_I2C1_DATA is correctly connected to SIO_I2C1_SDA with a test point for monitoring. | | BG25 | SIO_I2C2_DATA | | ✅ | SIO_I2C2_DATA is left unconnected, which is acceptable if I2C port 2 is not used in this design. | | BG26 | SIO_I2C3_DATA | | ✅ | SIO_I2C3_DATA is left unconnected, which is acceptable if I2C port 3 is not used in this design. | | BG27 | SIO_I2C4_CLK | | ✅ | SIO_I2C4_CLK is left unconnected, which is acceptable if I2C port 4 is not used in this design. | | BG28 | SIO_I2C5_CLK | SI0_I2C5_SCL | ✅ | SIO_I2C5_CLK is correctly connected through a 22 ohm series resistor to I2C5_SCL for signal integrity. | | BG29 | SIO_I2C6_CLK | SI0_I2C6_SCL | ✅ | SIO_I2C6_CLK is correctly connected through a 22 ohm series resistor to I2C6_SCL for signal integrity. | | BG30 | GPIO_S0_SC_093 | TP10_NET | ✅ | GPIO_S0_SC_093 is intentionally grounded through a 0 ohm resistor as indicated by the schematic note. | | BH10 | PCU_SMB_CLK | PCU_SMB_CLK | ✅ | PCU_SMB_CLK is correctly connected with a 2.2K pull-up resistor and routed through level shifter U5 to DDR_SMB_CLK. | | BH12 | ILB_8254_SPKR | ILB_8254_SPKR | ✅ | ILB_8254_SPKR is left floating, which is acceptable if the PC speaker output is not used in this design. | | BH14 | ILB_LPC_CLK_11 | | ✅ | ILB_LPC_CLK_11 is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BH16 | ILB_LPC_AD_00 | | ✅ | ILB_LPC_AD_00 is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BH22 | SIO_I2C0_DATA | | ✅ | SIO_I2C0_DATA is left unconnected, which is acceptable if I2C port 0 is not used in this design. | | BH24 | SIO_I2C1_CLK | SIO_I2C1_SCL | ✅ | SIO_I2C1_CLK is correctly connected to SIO_I2C1_SCL with a test point for monitoring. | | BH26 | SIO_I2C3_CLK | | ✅ | SIO_I2C3_CLK is left unconnected, which is acceptable if I2C port 3 is not used in this design. | | BH28 | SIO_I2C5_DATA | SI0_I2C5_SDA | ✅ | SIO_I2C5_DATA is correctly connected through a 22 ohm series resistor to I2C5_SDA for signal integrity. | | BH30 | GPIO_S0_SC_092 | TP9_NET | ✅ | GPIO_S0_SC_092 is intentionally grounded through a 0 ohm resistor as indicated by the schematic note. | | BJ13 | ILB_LPC_AD_22 | | ✅ | ILB_LPC_AD_22 is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BJ17 | ILB_LPC_AD_11 | | ✅ | ILB_LPC_AD_11 is left unconnected, which is acceptable if the LPC interface is not used in this design. | | BJ25 | SIO_I2C2_CLK | | ✅ | SIO_I2C2_CLK is left unconnected, which is acceptable if I2C port 2 is not used in this design. | | BJ29 | SIO_I2C6_DATA | SI0_I2C6_SDA | ✅ | SIO_I2C6_DATA is correctly connected through a 22 ohm series resistor to I2C6_SDA for signal integrity. | </details> <details> <summary>U5 - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DDR_SMB_CLK | ✅ | B2 pin correctly connected to DDR_SMB_CLK on the 3.3V side of the level translator. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S for the low voltage side supply. | | 4 | A2 | PCU_SMB_CLK | ✅ | A2 pin correctly connected to PCU_SMB_CLK on the 1.8V side of the level translator. | | 5 | A1 | PCU_SMB_DATA | ✅ | A1 pin correctly connected to PCU_SMB_DATA on the 1.8V side of the level translator. | | 6 | OE | PCU_SMB_BUFF_ENB | ✅ | OE pin correctly connected to PCU_SMB_BUFF_ENB with pull-up to enable the translator. | | 7 | VCCB | BUF2_PWR | ✅ | VCCB pin correctly connected to BUF2_PWR for the high voltage side supply. | | 8 | B1 | DDR_SMB_DATA | ✅ | B1 pin correctly connected to DDR_SMB_DATA on the 3.3V side of the level translator. | </details> <details> <summary>R52 - 2.2K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LSENB | ✅ | Pull-up resistor correctly configured to enable U6 level shifter by default while allowing external control. | | 2 | 2 | +V1P8S | ✅ | Pull-up resistor correctly configured to enable U6 level shifter by default while allowing external control. | </details> <details> <summary>R51 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF3_PWR | ✅ | Zero-ohm jumper correctly connects BUF3_PWR to +3VSB, providing the B-side voltage supply for U6 with design flexibility. | | 2 | 2 | +3VSB | ✅ | Zero-ohm jumper correctly connects BUF3_PWR to +3VSB, providing the B-side voltage supply for U6 with design flexibility. | </details> <details> <summary>U6 - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DBG_UART3_TXD | ✅ | B2 pin correctly connected to DBG_UART3_TXD, which routes the CPU's transmit data to the debug connector after level shifting from 1.8V to 3.3V. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V) supply with appropriate decoupling. | | 4 | A2 | PCU_UART3_TXD | ✅ | A2 pin correctly connected to PCU_UART3_TXD from the CPU, forming the A-side of the UART transmit channel. | | 5 | A1 | PCU_UART3_RXD | ✅ | A1 pin correctly connected to PCU_UART3_RXD from the CPU, forming the A-side of the UART receive channel. | | 6 | OE | LSENB | ✅ | OE pin correctly connected to LSENB with a 2.2K pull-up to +V1P8S, enabling the device by default while allowing external control. | | 7 | VCCB | BUF3_PWR | ✅ | VCCB pin correctly connected to BUF3_PWR (+3VSB via R51) with appropriate decoupling. | | 8 | B1 | DBG_UART3_RXD | ✅ | B1 pin correctly connected to DBG_UART3_RXD, which receives data from the debug connector after level shifting from 3.3V to 1.8V. | </details> <details> <summary>J4 - SIP6_RA ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0004869) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | 2 | | ✅ | Pin 2 is not connected, likely intended for CTS (Clear To Send) which is not used in this design. | | 3 | 3 | | ✅ | Pin 3 is unconnected but should be connected to +3VSB to provide 3.3V power for maximum compatibility with standard USB-to-TTL serial cables. | | 4 | 4 | DBG_UART3_RXD | ✅ | UART receive pin correctly connected through level shifter U6 with 100K pull-down resistor R50. | | 5 | 5 | DBG_UART3_TXD_R | ✅ | UART transmit pin correctly connected through 330 ohm series resistor R819 and level shifter U6. | | 6 | 6 | | ✅ | Pin 6 is not connected, likely intended for RTS (Request To Send) which is not used in this design. | </details> <details> <summary>R819 - 330 ohm series on UART3_TXD ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DBG_UART3_TXD | ✅ | Connected to DBG_UART3_TXD from level shifter U6 output (pin 1, B2). | | 2 | 2 | DBG_UART3_TXD_R | ✅ | Connected to DBG_UART3_TXD_R going to connector J4 pin 5 for transmission to the serial cable. | </details> <details> <summary>R50 - 100K pull-down on DBG_UART3_RXD ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND to provide the ground reference for the pull-down function. | | 2 | 2 | DBG_UART3_RXD | ✅ | Connected to DBG_UART3_RXD to pull the receive line low when no cable is connected, preventing floating input conditions. | </details> <details> <summary>R186 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for USB clock termination resistor. Correctly connected to GND. | | 2 | 2 | ICLK_USB_TERM_1 | ✅ | Connected to ICLK_USB_TERM_1 net which connects to CPU1 pin F10 (ICLK_USB_TERMN). There is a naming discrepancy between the CPU pin name (ICLK_USB_TERMN) and the net name (ICLK_USB_TERM_1). | </details> <details> <summary>R187 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground connection for USB clock termination resistor. Correctly connected to GND. | | 2 | 2 | ICLK_USB_TERM_0 | ✅ | Connected to ICLK_USB_TERM_0 net which connects to CPU1 pin D10 (ICLK_USB_TERM_1). There is a naming discrepancy between the CPU pin name (ICLK_USB_TERM_1) and the net name (ICLK_USB_TERM_0). | </details> <details> <summary>R11 - 22 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SDA | ✅ | Series resistor on I2C6 SDA line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity. | | 2 | 2 | I2C6_SDA | ✅ | External side of series resistor on I2C6 SDA line, connected to the I2C bus that routes off-page. | </details> <details> <summary>R12 - 22 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C6_SCL | ✅ | Series resistor on I2C6 SCL line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity. | | 2 | 2 | I2C6_SCL | ✅ | External side of series resistor on I2C6 SCL line, connected to the I2C bus that routes off-page. | </details> <details> <summary>R269 - 22 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SDA | ✅ | Series resistor on I2C5 SDA line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity. | | 2 | 2 | I2C5_SDA | ✅ | External side of series resistor on I2C5 SDA line, connected to the I2C bus that routes off-page. | </details> <details> <summary>R270 - 22 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SI0_I2C5_SCL | ✅ | Series resistor on I2C5 SCL line, connected between CPU pin and external bus. This is a standard configuration for I2C signal integrity. | | 2 | 2 | I2C5_SCL | ✅ | External side of series resistor on I2C5 SCL line, connected to the I2C bus that routes off-page. | </details> <details> <summary>R75 - 10K pull-up on PCU_SMB_ALERT ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S supply to provide pull-up voltage for the SMBus alert signal. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Connected to PCU_SMB_ALERT signal, providing a 10K pull-up for the active-low SMBus alert signal from the CPU. | </details> <details> <summary>R842 - 0 ohm jumper for SMB alert routing ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-SMB-ALERT# | ✅ | Connected to LAN-SMB-ALERT# net, allowing optional connection of LAN SMBus alert to CPU SMBus alert. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Connected to PCU_SMB_ALERT net, allowing the CPU's SMBus alert to be optionally connected to the LAN SMBus alert. | </details> <details> <summary>R841 - 0 ohm jumper DDR_SMB_CLK to LAN-SMB-CLK ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_CLK | ✅ | 0 ohm jumper connecting DDR_SMB_CLK to LAN-SMB-CLK, allowing the SMBus clock line from the level shifter U5 to be shared with a LAN SMBus interface. | | 2 | 2 | LAN-SMB-CLK | ✅ | 0 ohm jumper connecting DDR_SMB_CLK to LAN-SMB-CLK, allowing the SMBus clock line from the level shifter U5 to be shared with a LAN SMBus interface. | </details> <details> <summary>R840 - 0 ohm jumper DDR_SMB_DATA to LAN-SMB-DATA ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_DATA | ✅ | 0 ohm jumper connecting DDR_SMB_DATA to LAN-SMB-DATA, allowing the SMBus data line from the level shifter U5 to be shared with a LAN SMBus interface. | | 2 | 2 | LAN-SMB-DATA | ✅ | 0 ohm jumper connecting DDR_SMB_DATA to LAN-SMB-DATA, allowing the SMBus data line from the level shifter U5 to be shared with a LAN SMBus interface. | </details> <details> <summary>R97 - 10K pull-up on SOC_USB_HOST_OC1 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A power rail to provide pull-up voltage for the USB overcurrent detection signal. | | 2 | 2 | SOC_USB_HOST_OC1 | ✅ | Connected to SOC_USB_HOST_OC1, an active-low USB overcurrent detection signal from the CPU. | </details> <details> <summary>R84 - 10K pull-up on SOC_USB_HOST_OC0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A power rail to provide pull-up voltage for the USB overcurrent detection signal. | | 2 | 2 | SOC_USB_HOST_OC0 | ✅ | Connected to SOC_USB_HOST_OC0, an active-low USB overcurrent detection signal from the CPU. | </details> <details> <summary>R243 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP9_NET | ✅ | 0 ohm resistor connecting GPIO_S0_SC_092 (via TP9_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes. | | 2 | 2 | GND | ✅ | 0 ohm resistor connecting GPIO_S0_SC_092 (via TP9_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes. | </details> <details> <summary>R261 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP10_NET | ✅ | 0 ohm resistor connecting GPIO_S0_SC_093 (via TP10_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes. | | 2 | 2 | GND | ✅ | 0 ohm resistor connecting GPIO_S0_SC_093 (via TP10_NET) to GND. This intentionally grounds the GPIO pin as indicated by nearby text notes. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A48 | DRAM_VDD_S4 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AK38 | DRAM_VDD_S4_AK38 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AM38 | DRAM_VDD_S4_AM38 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AV41 | DRAM_VDD_S4_AV41 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | AV42 | DRAM_VDD_S4_AV42 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BB46 | DRAM_VDD_S4_BB46 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BD49 | DRAM_VDD_S4_BD49 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BD52 | DRAM_VDD_S4_BD52 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BD53 | DRAM_VDD_S4_BD53 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BF44 | DRAM_VDD_S4_BF44 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BG51 | DRAM_VDD_S4_BG51 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | BJ48 | DRAM_VDD_S4_BJ48 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | C51 | DRAM_VDD_S4_C51 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | D44 | DRAM_VDD_S4_D44 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | F49 | DRAM_VDD_S4_F49 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | F52 | DRAM_VDD_S4_F52 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | F53 | DRAM_VDD_S4_F53 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | H46 | DRAM_VDD_S4_H46 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | M41 | DRAM_VDD_S4_M41 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | M42 | DRAM_VDD_S4_M42 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | V38 | DRAM_VDD_S4_V38 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | Y38 | DRAM_VDD_S4_Y38 | +VDIMM | ✅ | DDR3L memory power supply pins connected to +VDIMM rail. These pins provide 1.35V power to the DDR3L memory interface. | | N28 | CORE_VSS_SENSE_N28 | VSS_SENSE | ✅ | Core ground sense pin connected to VSS_SENSE net. This pin provides ground reference feedback for the VCC voltage regulator. | | P28 | CORE_VCC_SENSE_P28 | VCC_SENSE | ✅ | Core voltage sense pin connected to VCC_SENSE net. This pin provides voltage feedback for the VCC voltage regulator. | | AA22 | TP2_CORE_VCC_S0IX | $9N615 | ✅ | Core voltage test point connection. This pin is connected to internal net $9N615 which connects to test point TP2 (marked DNI). | | AA24 | UNCORE_VNN_S3_AA24 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AC22 | UNCORE_VNN_S3_AC22 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AC24 | UNCORE_VNN_S3_AC24 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AD22 | UNCORE_VNN_S3_AD22 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AD24 | UNCORE_VNN_S3_AD24 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AF22 | UNCORE_VNN_S3_AF22 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AF24 | UNCORE_VNN_S3_AF24 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AG22 | UNCORE_VNN_S3_AG22 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AG24 | UNCORE_VNN_S3_AG24 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AJ22 | UNCORE_VNN_S3_AJ22 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AJ24 | UNCORE_VNN_S3_AJ24 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AK22 | UNCORE_VNN_S3_AK22 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AK24 | UNCORE_VNN_S3_AK24 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AK25 | UNCORE_VNN_S3_AK25 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AK27 | UNCORE_VNN_S3_AK27 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AK29 | UNCORE_VNN_S3_AK29 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AK30 | UNCORE_VNN_S3_AK30 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AK32 | UNCORE_VNN_S3_AK32 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AM22 | UNCORE_VNN_S3_AM22 | +VGFX | ✅ | Uncore voltage supply pins connected to +VGFX rail. These pins provide power to the graphics and uncore logic. | | AA27 | CORE_VCC_S0IX_AA27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AA29 | CORE_VCC_S0IX_AA29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AA30 | CORE_VCC_S0IX_AA30 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AC27 | CORE_VCC_S0IX_AC27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AC29 | CORE_VCC_S0IX_AC29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AC30 | CORE_VCC_S0IX_AC30 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AD27 | CORE_VCC_S0IX_AD27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AD29 | CORE_VCC_S0IX_AD29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AD30 | CORE_VCC_S0IX_AD30 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AF27 | CORE_VCC_S0IX_AF27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AF29 | CORE_VCC_S0IX_AF29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AG27 | CORE_VCC_S0IX_AG27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AG29 | CORE_VCC_S0IX_AG29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | AG30 | CORE_VCC_S0IX_AG30 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | P26 | CORE_VCC_S0IX_P26 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | P27 | CORE_VCC_S0IX_P27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | U27 | CORE_VCC_S0IX_U27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | U29 | CORE_VCC_S0IX_U29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | V27 | CORE_VCC_S0IX_V27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | V29 | CORE_VCC_S0IX_V29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | V30 | CORE_VCC_S0IX_V30 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | Y27 | CORE_VCC_S0IX_Y27 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | Y29 | CORE_VCC_S0IX_Y29 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | Y30 | CORE_VCC_S0IX_Y30 | +VCORE | ✅ | Core voltage supply pins connected to +VCORE rail. These pins provide power to the processor cores. | | BB8 | UNCORE_VNN_SENSE | VCCGT_SENSE | ✅ | Uncore voltage sense pin connected to VCCGT_SENSE net. This pin provides voltage feedback for the VNN voltage regulator. | | AD38 | DRAM_VDD_S4_AD38 | DRAM_VDD_CLK | ✅ | DDR3L memory power supply pins connected to DRAM_VDD_CLK rail, which connects to +VDIMM through 0-ohm resistor R275. This separation may be for noise isolation or measurement purposes. | | AF38 | DRAM_VDD_S4_AF38 | DRAM_VDD_CLK | ✅ | DDR3L memory power supply pins connected to DRAM_VDD_CLK rail, which connects to +VDIMM through 0-ohm resistor R275. This separation may be for noise isolation or measurement purposes. | | AF30 | TP_CORE_V1P05_S4 | $9N613 | ✅ | Core voltage test point connection. This pin is connected to internal net $9N613 which connects to test point TP1 (marked DNI). | </details> <details> <summary>R275 - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM, the main DRAM power supply rail. This pin serves as the input side of the 0-ohm jumper. | | 2 | 2 | DRAM_VDD_CLK | ✅ | Connected to DRAM_VDD_CLK, a separate DRAM clock power rail. This pin serves as the output side of the 0-ohm jumper, connecting the clock power pins to the main DRAM supply. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AC32 | CORE_V1P05_S3_AC32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,41.55,44.21,49.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | Y32 | CORE_V1P05_S3_Y32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,42.13,44.21,49.63" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | AA33 | CORE_V1P05_S3_AA33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,33.31,44.21,40.81" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | AF33 | CORE_V1P05_S3_AF33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,28.61,61.48,36.11" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | AG33 | CORE_V1P05_S3_AG33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.20,61.48,36.70" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | AG35 | CORE_V1P05_S3_AG35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.79,61.48,37.29" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | U33 | CORE_V1P05_S3_U33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.37,61.48,37.87" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | U35 | CORE_V1P05_S3_U35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.96,61.48,38.46" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | V33 | CORE_V1P05_S3_V33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,31.55,61.48,39.05" aspect-ratio="1.29" } <ul><li>Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)</li><li>These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213">140-0004628</a>, page 213)</li><li>The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)</li><li>A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)</li><li>Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)</li><li>Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)</li><li>Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)</li><li>These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)</li></ul></details> | | A3 | VSS_A3_A3 | GND | ✅ | VSS ground pins are correctly connected to GND. | | A5 | VSS_A5_A5 | GND | ✅ | VSS ground pins are correctly connected to GND. | | A6 | VSS_A6_A6 | GND | ✅ | VSS ground pins are correctly connected to GND. | | A49 | VSS_A49_A49 | GND | ✅ | VSS ground pins are correctly connected to GND. | | A51 | VSS_A51_A51 | GND | ✅ | VSS ground pins are correctly connected to GND. | | A52 | VSS_A52_A52 | GND | ✅ | VSS ground pins are correctly connected to GND. | | B2 | VSS_B2_B2 | GND | ✅ | VSS ground pins are correctly connected to GND. | | B52 | VSS_B52_B52 | GND | ✅ | VSS ground pins are correctly connected to GND. | | B53 | VSS_B53_B53 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BE1 | VSS_BE1_BE1 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BE53 | VSS_BE53_BE53 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BG1 | VSS_BG1_BG1 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BG53 | VSS_BG53_BG53 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BH1 | VSS_BH1_BH1 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BH2 | VSS_BH2_BH2 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BH52 | VSS_BH52_BH52 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BH53 | VSS_BH53_BH53 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BJ2 | VSS_BJ2_BJ2 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BJ3 | VSS_BJ3_BJ3 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BJ5 | VSS_BJ5_BJ5 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BJ49 | VSS_BJ49_BJ49 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BJ51 | VSS_BJ51_BJ51 | GND | ✅ | VSS ground pins are correctly connected to GND. | | BJ52 | VSS_BJ52_BJ52 | GND | ✅ | VSS ground pins are correctly connected to GND. | | C1 | VSS_C1_C1 | GND | ✅ | VSS ground pins are correctly connected to GND. | | C53 | VSS_C53_C53 | GND | ✅ | VSS ground pins are correctly connected to GND. | | E1 | VSS_E1_E1 | GND | ✅ | VSS ground pins are correctly connected to GND. | | E53 | VSS_E53_E53 | GND | ✅ | VSS ground pins are correctly connected to GND. | | B6 | UNCORE_V1P0_G3_B6 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors. | | C5 | UNCORE_V1P0_G3_C5 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors. | | U22 | UNCORE_V1P0_G3_U22 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors. | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors. | | C3 | USB3_V1P0_G3_C3 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors. | | Y19 | USB3_V1P0_G3_Y19 | +V1P0A | ✅ | UNCORE_V1P0_G3 and USB3_V1P0_G3 power pins are correctly connected to +V1P0A supply with appropriate decoupling capacitors. | | F1 | RESERVED_F1 | $10N1595 | ✅ | RESERVED pin is connected to test point TP4 on net $10N1595. Reserved pins should typically be left unconnected or grounded; connection to a test point may be for factory test purposes but should be verified. | | M14 | USB_V1P0_S3_M14 | +V1P0S | ✅ | USB_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | U18 | USB_V1P0_S3_U18 | +V1P0S | ✅ | USB_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | U19 | USB_V1P0_S3_U19 | +V1P0S | ✅ | USB_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | N18 | USB_V3P3_G3_N18 | +3VSB | ✅ | USB_V3P3_G3 power pins are correctly connected to +3VSB supply with appropriate decoupling capacitors. | | P18 | USB_V3P3_G3_P18 | +3VSB | ✅ | USB_V3P3_G3 power pins are correctly connected to +3VSB supply with appropriate decoupling capacitors. | | N20 | USB_V1P8_G3_N20 | +V1P8A | ✅ | USB_V1P8_G3 power pin is correctly connected to +V1P8A supply. | | N22 | PCU_V3P3_G3_N22 | +3VSB | ✅ | PCU_V3P3_G3 power pin is correctly connected to +3VSB supply with appropriate decoupling capacitors. | | P22 | RTC_VCC_P22 | +RTCVCC | ✅ | RTC_VCC power pin is correctly connected to +RTCVCC supply with 0.1µF decoupling capacitor C212. | | U16 | USB_VSSA_U16 | GND | ✅ | USB_VSSA and VSSA ground pins are correctly connected to GND. | | AN16 | VSSA_AN16 | GND | ✅ | USB_VSSA and VSSA ground pins are correctly connected to GND. | | U24 | UNCORE_V1P8_G3_U24 | +V1P8A | ✅ | UNCORE_V1P8_G3 power pins are correctly connected to +V1P8A supply with appropriate decoupling capacitors. | | AA18 | UNCORE_V1P8_G3_AA18 | +V1P8A | ✅ | UNCORE_V1P8_G3 power pins are correctly connected to +V1P8A supply with appropriate decoupling capacitors. | | U25 | PMU_V1P8_G3_U25 | +V1P8A | ✅ | PMU_V1P8_G3 power pin is correctly connected to +V1P8A supply with decoupling capacitor C236 placed nearby. | | V18 | USB_HSIC_V1P24_G3_V18 | +V1P0A | ✅ | USB_HSIC_V1P24_G3 power pin is connected to +V1P0A (1.0V) instead of the specified 1.24V. This is acceptable per text note indicating USB HSIC is not used and the pin can connect to V1P0A in this configuration. | | V24 | UNCORE_V1P0_S0IX_V24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling. | | Y24 | UNCORE_V1P0_S0IX_Y24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling. | | Y22 | UNCORE_V1P0_S0IX_Y22 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling. | | AN29 | UNCORE_V1P0_S0IX_AN29 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling. | | AN30 | UNCORE_V1P0_S0IX_AN30 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling. | | AF21 | UNCORE_V1P0_S0IX_AF21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling. | | AG21 | UNCORE_V1P0_S0IX_AG21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX power pins are correctly connected to VCC_VIS_V1P0, which derives from +V1P0S through 0-ohm jumper R222 with appropriate decoupling. | | V25 | PCU_V1P8_G3_V25 | +V1P8A | ✅ | PCU_V1P8_G3 power pin is correctly connected to +V1P8A supply with decoupling capacitor C196 placed nearby. | | V32 | SVID_V1P0_S3_V32 | +V1P0S | ✅ | SVID_V1P0_S3 power pin is correctly connected to +V1P0S supply. | | AA25 | UNCORE_V1P35_S0IX_F5_AA25 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling. | | AF19 | UNCORE_V1P35_S0IX_F6 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling. | | V36 | UNCORE_V1P35_S0IX_F3_V36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling. | | U36 | UNCORE_V1P35_S0IX_F4_U36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling. | | AG32 | UNCORE_V1P35_S0IX_F2_AG32 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling. | | AG19 | UNCORE_V1P35_S0IX_F1_AG19 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling. | | AD36 | DRAM_V1P35_S0IX_F1_AD36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX and DRAM_V1P35_S0IX_F1 power pins are correctly connected to VCC_UNCORE_V1P35, which derives from +V1P35S through ferrite bead FB3 with appropriate decoupling. | | AA36 | DRAM_V1P0_S0IX_AA36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | AD35 | DRAM_V1P0_S0IX_AD35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | AF35 | DRAM_V1P0_S0IX_AF35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | AF36 | DRAM_V1P0_S0IX_AF36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | AJ36 | DRAM_V1P0_S0IX_AJ36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | AK35 | DRAM_V1P0_S0IX_AK35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | AK36 | DRAM_V1P0_S0IX_AK36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | Y35 | DRAM_V1P0_S0IX_Y35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | Y36 | DRAM_V1P0_S0IX_Y36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX power pins are correctly connected to VCC_DRAM, which derives from +V1P0S through 0-ohm jumper R265 with appropriate decoupling. | | AD16 | VSS_AD16 | VCC_VSS_V1P2 | ✅ | VSS_AD16 and VSS_AD18 pins are connected to VCC_VSS_V1P2 which connects to GND through 0-ohm resistor R216. This configuration allows grounding when MIPI CSI is not used, as indicated by text notes. | | AD18 | VSS_AD18 | VCC_VSS_V1P2 | ✅ | VSS_AD16 and VSS_AD18 pins are connected to VCC_VSS_V1P2 which connects to GND through 0-ohm resistor R216. This configuration allows grounding when MIPI CSI is not used, as indicated by text notes. | | BD1 | VGA_V1P35_S3_F1_BD1 | VCC_CRT_V1P35 | ✅ | VGA_V1P35_S3_F1 power pin is correctly connected to VCC_CRT_V1P35, which derives from +V1P35S through ferrite bead FB4 with appropriate decoupling. | | AF16 | UNCORE_V1P0_S3_AF16 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AF18 | UNCORE_V1P0_S3_AF18 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | G1 | UNCORE_V1P0_S3_G1 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | Y18 | UNCORE_V1P0_S3_Y18 | +V1P0S | ✅ | UNCORE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AJ18 | DDI_V1P0_S0IX_AJ18 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby. | | AK19 | DDI_V1P0_S0IX_AK19 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby. | | AK21 | DDI_V1P0_S0IX_AK21 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby. | | AM16 | DDI_V1P0_S0IX_AM16 | +V1P0S | ✅ | DDI_V1P0_S0IX power pins are correctly connected to +V1P0S with appropriate decoupling capacitors placed nearby. | | AJ19 | ICLK_V1P35_S3_F1_AJ19 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which derives from +V1P35S through ferrite bead FB5 with appropriate decoupling. | | AG18 | ICLK_V1P35_S3_F2 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 power pins are correctly connected to VCC_ICLK_V1P35, which derives from +V1P35S through ferrite bead FB5 with appropriate decoupling. | | BJ6 | VGA_V1P0_S3_BJ6 | +V1P0S | ✅ | VGA_V1P0_S3 power pin is correctly connected to +V1P0S supply. | | AM27 | LPC_V1P8V3P3_S3_AM27 | +VCC3S | ✅ | LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V), indicating the design uses 3.3V I/O for LPC and SD interfaces. | | AN27 | SD3_V1P8V3P3_S3_AN27 | +VCC3S | ✅ | LPC_V1P8V3P3_S3 and SD3_V1P8V3P3_S3 power pins are correctly connected to +VCC3S (3.3V), indicating the design uses 3.3V I/O for LPC and SD interfaces. | | AM30 | UNCORE_V1P8_S3_AM30 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S supply with appropriate decoupling capacitors. | | AN32 | UNCORE_V1P8_S3_AN32 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S supply with appropriate decoupling capacitors. | | U38 | UNCORE_V1P8_S3_U38 | +V1P8S | ✅ | UNCORE_V1P8_S3 power pins are correctly connected to +V1P8S supply with appropriate decoupling capacitors. | | AM32 | HDA_LPE_V1P5V1P8_S3_AM32 | +V1P8S | ✅ | HDA_LPE_V1P5V1P8_S3 power pin is correctly connected to +V1P8S, indicating the design uses LPE (Low Power Engine) audio at 1.8V rather than HD Audio at 1.5V. | | AN18 | PCIE_SATA_V1P0_S3_AN18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AN19 | SATA_V1P0_S3_AN19 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AN21 | PCIE_V1P0_S3_AN21 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AM21 | PCIE_V1P0_S3_AM21 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AM18 | PCIE_V1P0_S3_AM18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AK18 | PCIE_V1P0_S3_AK18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3, SATA_V1P0_S3, and PCIE_V1P0_S3 power pins are correctly connected to +V1P0S supply. | | AN24 | VGA_V3P3_S3_AN24 | +VCC3S | ✅ | VGA_V3P3_S3 power pin is correctly connected to +VCC3S supply. | | AN25 | GPIO_V1P0_S3_AN25 | +V1P0S | ✅ | GPIO_V1P0_S3 power pin is correctly connected to +V1P0S supply. | </details> <details> <summary>FB3 - FERRITE_600OHM_1.3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0001423) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin correctly connected to +V1P35S source power rail. This is the unfiltered input side of the ferrite bead. | | 2 | 2 | VCC_UNCORE_V1P35 | ✅ | Output pin correctly connected to VCC_UNCORE_V1P35, supplying filtered power to CPU1 UNCORE domain with appropriate decoupling. | </details> <details> <summary>FB4 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to +V1P35S supply rail. This is the unfiltered 1.35V input to the ferrite bead. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Output pin connected to VCC_CRT_V1P35, providing filtered 1.35V power to the VGA/CRT section of CPU1 pin BD1. | </details> <details> <summary>C164 - 22uF 20% 6.3V 0805 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net for decoupling capacitor function. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Power pin connected to VCC_CRT_V1P35, providing bulk decoupling for the VGA 1.35V rail. | </details> <details> <summary>C28 - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net for decoupling capacitor function. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Power pin connected to VCC_CRT_V1P35, providing additional bulk decoupling for the VGA 1.35V rail. | </details> <details> <summary>C26 - 1uF 10% 16V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001066) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin of decoupling capacitor for VCC_ICLK_V1P35 rail. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Power pin connected to VCC_ICLK_V1P35, providing decoupling for the CPU ICLK domain. | </details> <details> <summary>C27 - 1uF 10% 16V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001066) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin of decoupling capacitor for VCC_ICLK_V1P35 rail. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Power pin connected to VCC_ICLK_V1P35, providing decoupling for the CPU ICLK domain. | </details> <details> <summary>FB5 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input pin connected to +V1P35S supply rail. This is the input side of the ferrite bead that filters power for the ICLK domain. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Output pin connected to VCC_ICLK_V1P35 net. This supplies filtered 1.35V power to the CPU ICLK domain. | </details> <details> <summary>R222 - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | 0-ohm jumper connecting +V1P0S supply to VCC_VIS_V1P0 rail, providing power to the VIS/graphics portion of the CPU. Current requirement is 2.1A based on nearby text notes. | | 2 | 2 | VCC_VIS_V1P0 | ✅ | 0-ohm jumper connecting +V1P0S supply to VCC_VIS_V1P0 rail, providing power to the VIS/graphics portion of the CPU. Current requirement is 2.1A based on nearby text notes. | </details> <details> <summary>R265 - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | 0-ohm jumper connecting +V1P0S supply to VCC_DRAM rail, providing power to the DRAM interface of the CPU. Current requirement is 900mA. | | 2 | 2 | VCC_DRAM | ✅ | 0-ohm jumper connecting +V1P0S supply to VCC_DRAM rail, providing power to the DRAM interface of the CPU. Current requirement is 900mA. | </details> <details> <summary>R216 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VSS_V1P2 | ✅ | 0-ohm resistor connecting VCC_VSS_V1P2 net to GND, grounding special VSS pins (AD16, AD18) of the CPU when MIPI/CSI interface is not used. | | 2 | 2 | GND | ✅ | 0-ohm resistor connecting VCC_VSS_V1P2 net to GND, grounding special VSS pins (AD16, AD18) of the CPU when MIPI/CSI interface is not used. | </details> <details> <summary>C153 - 0.1uF ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to +5VSB for decoupling the standby power rail. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND, completing the decoupling capacitor connection. | </details> <details> <summary>D7 - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N is connected to GND, providing the ground reference for the bidirectional TVS diode protecting the +5VSB rail. | | P | P | +5VSB | ✅ | Pin P is connected to +5VSB, the protected power rail for this TVS diode. | </details> <details> <summary>J8 - 3430-0212 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3430-0212) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 provides +5VSB power input to the board. This connector is an alternative to J2 which is marked DNI. | | 2 | 2 | GND | ✅ | Pin 2 provides ground reference for the +5VSB power input. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A11 | VSS1 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A15 | VSS2 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A19 | VSS3 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A23 | VSS4 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A27 | VSS5 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A31 | VSS6 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A35 | VSS7 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A39 | VSS8 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A43 | VSS9 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | A47 | VSS10 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA1 | VSS11 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA3 | VSS15 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA12 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA16 | VSS12 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA19 | VSS13 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA21 | VSS14 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA32 | VSS16 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA35 | VSS17 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA38 | VSS18 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AA53 | VSS19 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB4 | VSS21 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB6 | VSS28 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB10 | VSS20 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB41 | VSS22 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB45 | VSS23 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB47 | VSS24 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB48 | VSS25 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB50 | VSS26 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AB51 | VSS27 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC16 | VSS29 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC18 | VSS30 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC19 | VSS31 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC21 | VSS32 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC25 | VSS33 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC33 | VSS34 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC35 | VSS35 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC36 | VSS36 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AC38 | VSS37 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AD7 | VSS44 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AD19 | VSS38 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AD21 | VSS39 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AD25 | VSS40 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AD32 | VSS41 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AD33 | VSS42 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AD47 | VSS43 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE1 | VSS45 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE3 | VSS49 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE4 | VSS50 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE6 | VSS60 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE8 | VSS61 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE9 | VSS62 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE11 | VSS46 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE12 | VSS47 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE14 | VSS48 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE40 | VSS51 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE42 | VSS52 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE43 | VSS53 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE45 | VSS54 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE46 | VSS55 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE48 | VSS56 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE50 | VSS57 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE51 | VSS58 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AE53 | VSS59 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AF10 | VSS63 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AF12 | VSS64 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AF25 | VSS65 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AF32 | VSS66 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AF47 | VSS67 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AG16 | VSS68 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AG25 | VSS69 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AG36 | VSS70 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AG38 | VSS71 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AG71 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH4 | VSS72 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH6 | VSS110 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH7 | VSS75 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH9 | VSS76 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH41 | VSS73 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH45 | VSS74 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH47 | VSS106 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH48 | VSS107 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH50 | VSS108 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH51 | VSS109 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH74 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH75 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH76 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH106 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH107 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH108 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH109 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AH110 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ1 | VSS77 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ3 | VSS83 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ16 | VSS78 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ21 | VSS79 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ25 | VSS80 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ27 | VSS81 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ29 | VSS82 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ30 | VSS84 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ32 | VSS85 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ33 | VSS86 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ35 | VSS87 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ38 | VSS88 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ53 | VSS89 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ77 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ78 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ79 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ80 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ81 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ82 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ83 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ84 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ85 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ86 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ87 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ88 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AJ89 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK10 | VSS90 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK14 | VSS91 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK16 | VSS92 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK33 | VSS93 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK41 | VSS94 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK44 | VSS95 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK90 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK91 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK92 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK93 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK94 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AK95 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM7 | VSS113 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM12 | VSS96 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM19 | VSS97 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM24 | VSS98 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM25 | VSS99 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM29 | VSS100 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM33 | VSS101 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM35 | VSS102 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM36 | VSS103 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM40 | VSS104 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM44 | VSS111 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM51 | VSS112 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM96 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM97 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM98 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM99 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM100 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM101 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM102 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AM103 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN1 | VSS114 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN3 | VSS119 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN5 | VSS131 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN6 | VSS134 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN8 | VSS135 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN9 | VSS136 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN11 | VSS115 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN12 | VSS116 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN14 | VSS117 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN22 | VSS118 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN33 | VSS120 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN35 | VSS121 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN36 | VSS122 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN38 | VSS123 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN40 | VSS124 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN42 | VSS125 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN43 | VSS126 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN45 | VSS127 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN46 | VSS128 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN48 | VSS129 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN49 | VSS130 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN51 | VSS132 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN53 | VSS133 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN114 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN115 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN116 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN117 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN118 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN119 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN120 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN121 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN122 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN123 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN124 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN125 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN126 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN127 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN128 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN129 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN130 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN131 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN132 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN133 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN134 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN135 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AN136 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AP40 | VSS137 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AP137 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT4 | VSS146 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT12 | VSS138 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT16 | VSS139 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT19 | VSS140 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT24 | VSS141 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT27 | VSS142 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT30 | VSS143 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT35 | VSS144 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT38 | VSS145 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT47 | VSS147 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT52 | VSS148 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT138 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT139 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AT140 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AU1 | VSS149 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AU3 | VSS151 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AU24 | VSS150 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AU30 | VSS152 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AU38 | VSS153 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AU51 | VSS154 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AU52 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV7 | VSS167 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV12 | VSS155 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV13 | VSS156 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV14 | VSS157 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV18 | VSS158 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV19 | VSS159 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV24 | VSS160 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV27 | VSS161 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV30 | VSS162 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV35 | VSS163 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV38 | VSS164 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV47 | VSS165 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AV51 | VSS166 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AW3 | VSS171 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AW13 | VSS168 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AW19 | VSS169 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AW27 | VSS170 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AW35 | VSS172 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AY4 | VSS177 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AY9 | VSS179 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AY10 | VSS173 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AY22 | VSS174 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AY32 | VSS175 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AY36 | VSS176 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | AY50 | VSS178 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA14 | VSS180 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA19 | VSS181 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA22 | VSS182 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA27 | VSS183 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA32 | VSS184 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA35 | VSS185 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA40 | VSS186 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BA53 | VSS187 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BB19 | VSS188 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BB27 | VSS189 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BB35 | VSS190 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BC20 | VSS191 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BC22 | VSS192 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BC26 | VSS193 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BC28 | VSS194 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BC32 | VSS195 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BC34 | VSS196 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BC42 | VSS197 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BD19 | VSS198 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BD24 | VSS199 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BD27 | VSS200 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BD30 | VSS201 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BD35 | VSS202 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BE2 | VSS204 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BE8 | VSS206 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BE19 | VSS203 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BE35 | VSS205 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BF4 | VSS213 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BF12 | VSS207 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BF16 | VSS208 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BF24 | VSS209 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BF30 | VSS211 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BF36 | VSS212 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BF38 | VSS210 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BG31 | VSS214 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BG34 | VSS215 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BG39 | VSS216 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BG42 | VSS217 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BG45 | VSS218 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BG49 | VSS219 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ7 | VSS230 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ11 | VSS220 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ15 | VSS221 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ19 | VSS222 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ23 | VSS223 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ27 | VSS224 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ31 | VSS225 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ35 | VSS226 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ39 | VSS227 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ43 | VSS228 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | BJ47 | VSS229 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C14 | VSS231 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C21 | | | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C31 | VSS232 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C34 | VSS233 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C39 | VSS234 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C42 | VSS235 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C45 | VSS236 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | C49 | VSS237 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | D12 | VSS238 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | D16 | VSS239 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | D24 | VSS240 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | D30 | VSS241 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | D36 | VSS242 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | D38 | VSS243 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | E8 | VSS246 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | E19 | VSS244 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | E35 | VSS245 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F2 | VSS248 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F5 | VSS253 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F7 | VSS254 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F19 | VSS247 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F24 | VSS249 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F27 | VSS250 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F30 | VSS251 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | F35 | VSS252 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G10 | VSS255 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G20 | VSS256 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G22 | VSS257 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G26 | VSS258 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G28 | VSS259 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G32 | VSS260 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G34 | VSS261 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | G42 | VSS262 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | H19 | VSS263 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | H27 | VSS264 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | H35 | VSS265 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J1 | VSS266 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J16 | VSS267 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J19 | VSS268 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J22 | VSS269 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J27 | VSS270 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J32 | VSS271 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J35 | VSS272 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J40 | VSS273 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | J53 | VSS274 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | K4 | VSS279 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | K9 | VSS281 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | K14 | VSS275 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | K22 | VSS276 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | K32 | VSS277 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | K36 | VSS278 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | K50 | VSS280 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | L13 | VSS282 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | L19 | VSS283 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | L27 | VSS284 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | L35 | VSS285 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M19 | VSS286 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M26 | VSS287 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M27 | VSS288 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M28 | VSS105 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M34 | VSS289 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M35 | VSS290 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M38 | VSS291 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M47 | VSS292 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | M51 | VSS293 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | N1 | VSS294 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | N16 | VSS295 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | N38 | VSS296 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | N51 | VSS297 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P4 | VSS306 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P9 | VSS309 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P13 | VSS298 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P16 | VSS299 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P19 | VSS300 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P20 | VSS301 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P24 | VSS302 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P32 | VSS303 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P35 | VSS304 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P38 | VSS305 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P47 | VSS307 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | P52 | VSS308 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | T40 | VSS310 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U1 | VSS311 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U3 | VSS316 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U5 | VSS326 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U6 | VSS329 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U8 | VSS330 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U9 | VSS331 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U11 | VSS312 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U12 | VSS313 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U14 | VSS314 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U21 | VSS315 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U30 | VSS317 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U32 | VSS318 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U40 | VSS319 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U42 | VSS320 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U43 | VSS321 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U45 | VSS322 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U46 | VSS323 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U48 | VSS324 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U49 | VSS325 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U51 | VSS327 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | U53 | VSS328 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V7 | VSS340 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V12 | VSS332 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V16 | VSS333 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V19 | VSS334 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V21 | VSS335 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V35 | VSS336 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V40 | VSS337 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V44 | VSS338 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | V51 | VSS339 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y7 | VSS349 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y9 | VSS350 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y10 | VSS341 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y14 | VSS342 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y16 | VSS343 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y21 | VSS344 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y25 | VSS345 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y33 | VSS346 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y41 | VSS347 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | | Y44 | VSS348 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide essential ground reference for the Intel Atom E3825 processor and must be connected to a solid ground plane for proper operation. | </details> <details> <summary>MEM2 - MT41K256M16HA-125:E ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | C1 | VDDQ2 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | R1 | VDD7 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | B2 | VDD8 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | D2 | VDDQ9 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | H2 | VDDQ4 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | K2 | VDD9 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | G7 | VDD1 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | A8 | VDDQ5 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | K8 | VDD2 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | C9 | VDDQ6 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | N1 | VDD6 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | F1 | VDDQ3 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | D9 | VDD4 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | E9 | VDDQ7 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | H9 | VDDQ8 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | N9 | VDD3 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | R9 | VDD5 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | B1 | VSSQ1 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | D1 | VSSQ2 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | E1 | VSS1 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | G1 | VSSQ3 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | M1 | VSS2 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | P1 | VSS3 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | T1 | VSS4 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | E2 | VSSQ4 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | J2 | VSS5 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | B3 | VSS6 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | D8 | VSSQ5 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | E8 | VSSQ6 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | G8 | VSS7 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | J8 | VSS8 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | A9 | VSS9 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | B9 | VSSQ7 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | F9 | VSSQ8 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | G9 | VSSQ9 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | M9 | VSS10 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | P9 | VSS11 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | T9 | VSS12 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | C7 | DQSU | M_DQS_A_P1 | ✅ | Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P1 and M_DQS_A_N1, providing the strobe signal for the upper byte data. | | B7 | /DQSU | M_DQS_A_N1 | ✅ | Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P1 and M_DQS_A_N1, providing the strobe signal for the upper byte data. | | D3 | DMU | M_DM_A1 | ✅ | Upper byte data mask pin UDM is connected to M_DM_A1, providing write data masking capability for the upper byte. | | D7 | DQU0 | M_DATA_A9 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | C3 | DQU1 | M_DATA_A10 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | C8 | DQU2 | M_DATA_A8 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | C2 | DQU3 | M_DATA_A11 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | A7 | DQU4 | M_DATA_A13 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | A2 | DQU5 | M_DATA_A15 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | B8 | DQU6 | M_DATA_A12 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | A3 | DQU7 | M_DATA_A14 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A8 through M_DATA_A15, forming the upper 8 bits of the 16-bit data bus for this device. | | E3 | DQL0 | M_DATA_A0 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | F7 | DQL1 | M_DATA_A1 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | F2 | DQL2 | M_DATA_A2 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | F8 | DQL3 | M_DATA_A3 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | H3 | DQL4 | M_DATA_A4 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | H8 | DQL5 | M_DATA_A5 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | G2 | DQL6 | M_DATA_A6 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | H7 | DQL7 | M_DATA_A7 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A0 through M_DATA_A7, forming the lower 8 bits of the 16-bit data bus for this device. | | E7 | DML | M_DM_A0 | ✅ | Lower byte data mask pin LDM is connected to M_DM_A0, providing write data masking capability for the lower byte. | | F3 | DQSL | M_DQS_A_P0 | ✅ | Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P0 and M_DQS_A_N0, providing the strobe signal for the lower byte data. | | G3 | /DQSL | M_DQS_A_N0 | ✅ | Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P0 and M_DQS_A_N0, providing the strobe signal for the lower byte data. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | Reference voltage pin VREFDQ is connected to SM_VREF_DQ1_A, which is generated by a resistor divider (R310 and R325) to provide VDD×0.5 reference for data signals. | | J1 | NC1__ODT1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | L1 | NC2__/CS1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | J9 | NC3__CKE1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | L9 | NC4__ZQ1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | M7 | NC5 | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | J3 | /RAS | M_RAS_A_L | ✅ | Row address strobe pin RAS# is connected to M_RAS_A_L, providing the row address strobe command input. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination enable pin ODT is connected to M_ODT_A0, controlling the termination resistance for DQ, DQS, and DM signals. | | K3 | /CAS | M_CAS_A_L | ✅ | Column address strobe pin CAS# is connected to M_CAS_A_L, providing the column address strobe command input. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable pin CKE is connected to M_CKE_A0, controlling the device's clock enable state. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select pin CS# is connected to M_CS_A_L0, enabling/disabling the command decoder for this device. | | L3 | /WE | M_WE_A_L | ✅ | Write enable pin WE# is connected to M_WE_A_L, providing the write enable command input. | | L8 | ZQ | M_ZQ1 | ✅ | ZQ calibration pin is connected to M_ZQ1, which has a 240 ohm resistor (R140) to ground for output driver and ODT calibration. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | Reference voltage pin VREFCA is connected to SM_VREF_CA1_A, which is generated by a resistor divider (R144 and R326) to provide VDD×0.5 reference for control, command, and address signals. | | N3 | A0 | M_MA_A0 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P7 | A1 | M_MA_A1 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P3 | A2 | M_MA_A2 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | N2 | A3 | M_MA_A3 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P8 | A4 | M_MA_A4 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P2 | A5 | M_MA_A5 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R8 | A6 | M_MA_A6 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R2 | A7 | M_MA_A7 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T8 | A8 | M_MA_A8 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R3 | A9 | M_MA_A9 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R7 | A11 | M_MA_A11 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T3 | A13 | M_MA_A13 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T7 | A14 | M_MA_A14 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T2 | /RESET | M_A_RST_L | ✅ | Reset pin RESET# is connected to M_A_RST_L, which is shared with MEM3 and has an optional series resistor (R353) and DNI capacitor (C374) for signal conditioning. | </details> <details> <summary>MEM3 - MT41K256M16HA-125:E ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | C1 | VDDQ2 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | R1 | VDD7 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | B2 | VDD8 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | D2 | VDDQ9 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | H2 | VDDQ4 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | K2 | VDD9 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | G7 | VDD1 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | A8 | VDDQ5 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | K8 | VDD2 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | C9 | VDDQ6 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | N1 | VDD6 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | F1 | VDDQ3 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | D9 | VDD4 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | E9 | VDDQ7 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | H9 | VDDQ8 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | N9 | VDD3 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | R9 | VDD5 | +VDIMM | ✅ | All VDD and VDDQ power supply pins are connected to the +VDIMM rail, providing 1.35V DDR3L power to the device. | | B1 | VSSQ1 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | D1 | VSSQ2 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | E1 | VSS1 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | G1 | VSSQ3 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | M1 | VSS2 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | P1 | VSS3 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | T1 | VSS4 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | E2 | VSSQ4 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | J2 | VSS5 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | B3 | VSS6 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | D8 | VSSQ5 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | E8 | VSSQ6 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | G8 | VSS7 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | J8 | VSS8 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | A9 | VSS9 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | B9 | VSSQ7 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | F9 | VSSQ8 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | G9 | VSSQ9 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | M9 | VSS10 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | P9 | VSS11 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | T9 | VSS12 | GND | ✅ | All VSS and VSSQ ground pins are connected to the GND net, providing proper ground reference for the device. | | C7 | DQSU | M_DQS_A_P3 | ✅ | Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P3 and M_DQS_A_N3, providing the strobe signal for the upper byte data. | | B7 | /DQSU | M_DQS_A_N3 | ✅ | Upper byte differential data strobe pins UDQS and UDQS# are connected to M_DQS_A_P3 and M_DQS_A_N3, providing the strobe signal for the upper byte data. | | D3 | DMU | M_DM_A3 | ✅ | Upper byte data mask pin UDM is connected to M_DM_A3, providing write data masking capability for the upper byte. | | D7 | DQU0 | M_DATA_A29 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | C3 | DQU1 | M_DATA_A26 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | C8 | DQU2 | M_DATA_A28 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | C2 | DQU3 | M_DATA_A27 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | A7 | DQU4 | M_DATA_A25 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | A2 | DQU5 | M_DATA_A30 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | B8 | DQU6 | M_DATA_A24 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | A3 | DQU7 | M_DATA_A31 | ✅ | Upper byte data pins DQU0-DQU7 are connected to M_DATA_A24 through M_DATA_A31, forming bits 24-31 of the 32-bit data bus. | | E3 | DQL0 | M_DATA_A16 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | F7 | DQL1 | M_DATA_A17 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | F2 | DQL2 | M_DATA_A18 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | F8 | DQL3 | M_DATA_A19 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | H3 | DQL4 | M_DATA_A20 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | H8 | DQL5 | M_DATA_A21 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | G2 | DQL6 | M_DATA_A22 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | H7 | DQL7 | M_DATA_A23 | ✅ | Lower byte data pins DQL0-DQL7 are connected to M_DATA_A16 through M_DATA_A23, forming bits 16-23 of the 32-bit data bus. | | E7 | DML | M_DM_A2 | ✅ | Lower byte data mask pin LDM is connected to M_DM_A2, providing write data masking capability for the lower byte. | | F3 | DQSL | M_DQS_A_P2 | ✅ | Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P2 and M_DQS_A_N2, providing the strobe signal for the lower byte data. | | G3 | /DQSL | M_DQS_A_N2 | ✅ | Lower byte differential data strobe pins LDQS and LDQS# are connected to M_DQS_A_P2 and M_DQS_A_N2, providing the strobe signal for the lower byte data. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | Reference voltage pin VREFDQ is connected to SM_VREF_DQ1_A, which is generated by a resistor divider (R310 and R325) to provide VDD×0.5 reference for data signals. | | J1 | NC1__ODT1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | L1 | NC2__/CS1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | J9 | NC3__CKE1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | L9 | NC4__ZQ1_ | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | M7 | NC5 | | ✅ | No connect pins are left unconnected as specified by the datasheet. | | J3 | /RAS | M_RAS_A_L | ✅ | Row address strobe pin RAS# is connected to M_RAS_A_L, providing the row address strobe command input. | | J7 | CK | M_CLK_A_P0 | ✅ | Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device. | | K7 | /CK | M_CLK_A_N0 | ✅ | Differential clock pins CK and CK# are connected to M_CLK_A_P0 and M_CLK_A_N0, providing the system clock to the device. | | K1 | ODT | M_ODT_A0 | ✅ | On-die termination enable pin ODT is connected to M_ODT_A0, controlling the termination resistance for DQ, DQS, and DM signals. | | K3 | /CAS | M_CAS_A_L | ✅ | Column address strobe pin CAS# is connected to M_CAS_A_L, providing the column address strobe command input. | | K9 | CKE | M_CKE_A0 | ✅ | Clock enable pin CKE is connected to M_CKE_A0, controlling the device's clock enable state. | | L2 | /CS | M_CS_A_L0 | ✅ | Chip select pin CS# is connected to M_CS_A_L0, enabling/disabling the command decoder for this device. | | L3 | /WE | M_WE_A_L | ✅ | Write enable pin WE# is connected to M_WE_A_L, providing the write enable command input. | | L8 | ZQ | M_ZQ2 | ✅ | ZQ calibration pin is connected to M_ZQ2, which has a 240 ohm resistor (R327) to ground for output driver and ODT calibration. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address pins BA0-BA2 are connected to M_BS_A0 through M_BS_A2, providing the bank address inputs. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | Reference voltage pin VREFCA is connected to SM_VREF_CA1_A, which is generated by a resistor divider (R144 and R326) to provide VDD×0.5 reference for control, command, and address signals. | | N3 | A0 | M_MA_A0 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P7 | A1 | M_MA_A1 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P3 | A2 | M_MA_A2 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | N2 | A3 | M_MA_A3 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P8 | A4 | M_MA_A4 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | P2 | A5 | M_MA_A5 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R8 | A6 | M_MA_A6 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R2 | A7 | M_MA_A7 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T8 | A8 | M_MA_A8 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R3 | A9 | M_MA_A9 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | R7 | A11 | M_MA_A11 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T3 | A13 | M_MA_A13 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T7 | A14 | M_MA_A14 | ✅ | Address pins A0-A14 are connected to M_MA_A0 through M_MA_A14, providing the row and column address inputs. | | T2 | /RESET | M_A_RST_L | ✅ | Reset pin RESET# is connected to M_A_RST_L, which is shared with MEM2 and has an optional series resistor (R353) and DNI capacitor (C374) for signal conditioning. | </details> <details> <summary>R353 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_A_DRAMRST_L | ✅ | Pin 1 connects to M_A_DRAMRST_L, which is the DRAM reset signal source. Pin 2 connects to M_A_RST_L, which routes to the /RESET pins of DDR3 memory chips MEM2 and MEM3. | | 2 | 2 | M_A_RST_L | ✅ | Pin 2 connects to M_A_RST_L, which routes to the /RESET pins (T2) of DDR3 memory chips MEM2 and MEM3, and to a DNI capacitor C374. | </details> <details> <summary>P2 - 158-0001269 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/158-0001269) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | SD3_D2_R | ✅ | DAT2 is correctly connected to the filtered SD3_D2_R signal from the passive filter. | | 2 | CD/DAT3 | SD3_D3_R | ✅ | CD/DAT3 is correctly connected to the filtered SD3_D3_R signal from the passive filter. | | 3 | CMD | SD3_CMD_R | ✅ | CMD is correctly connected to the filtered SD3_CMD_R signal from the passive filter. | | 4 | VDD | +VCC3 | ✅ | VDD is correctly connected to +VCC3 with appropriate decoupling capacitors. | | 5 | CLOCK | SD3_CLK_R | ✅ | CLOCK is correctly connected to the filtered SD3_CLK_R signal from the passive filter. | | 6 | VSS | GND | ✅ | VSS is correctly connected to ground. | | 7 | DAT0 | SD3_D0_R | ✅ | DAT0 is correctly connected to the filtered SD3_D0_R signal from the passive filter. | | 8 | DAT1 | SD3_D1_R | ✅ | DAT1 is correctly connected to the filtered SD3_D1_R signal from the passive filter. | | 9 | GND | GND | ✅ | GND is correctly connected to ground. | | 10 | CD | SD3_CD_R | ✅ | CD is correctly connected to the filtered SD3_CD_R signal from the passive filter. | | 11 | GND3 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections. | | 12 | GND4 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections. | | 15 | GND7 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections. | | 16 | GND8 | FGND-uSD | ✅ | GND3, GND4, GND7, and GND8 are connected to FGND-uSD for frame ground connections. | | 13 | GND5 | FGND-uSD-Front | ✅ | GND5 and GND6 are connected to FGND-uSD-Front for front frame ground connections. | | 14 | GND6 | FGND-uSD-Front | ✅ | GND5 and GND6 are connected to FGND-uSD-Front for front frame ground connections. | </details> <details> <summary>FL1 - 3750-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3750-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CH1-IN | SD3_CD# | ✅ | CH1-IN receives the card detect signal SD3_CD# with a 100K pull-up to +V1P8S and filters it to the connector. | | 2 | CH2-IN | SD3_D2 | ✅ | CH2-IN receives SD3_D2 with a 100K pull-up to +VCC3 and filters it to the connector. | | 3 | CH3-IN | SD3_D3 | ✅ | CH3-IN receives SD3_D3 with a 100K pull-up to +VCC3 and filters it to the connector. | | 4 | CH4-IN | SD3_CMD | ✅ | CH4-IN receives SD3_CMD with a 100K pull-up to +VCC3 and filters it to the connector. | | 5 | CH5-IN | SD3_CLK | ✅ | CH5-IN receives SD3_CLK with a 100K pull-up to +VCC3 and filters it to the connector. | | 6 | CH6-IN | SD3_D0 | ✅ | CH6-IN receives SD3_D0 with a 100K pull-up to +VCC3 and filters it to the connector. | | 7 | CH7-IN | SD3_D1 | ✅ | CH7-IN receives SD3_D1 with a 100K pull-up to +VCC3 and filters it to the connector. | | 8 | CH8-IN | | ✅ | CH8-IN is not connected, leaving channel 8 unused. | | 9 | CH8-OUT | | ✅ | CH8-OUT is not connected, corresponding to the unused channel 8. | | 10 | CH7-OUT | SD3_D1_R | ✅ | CH7-OUT provides the filtered SD3_D1_R signal to the SD card connector DAT1 pin. | | 11 | CH6-OUT | SD3_D0_R | ✅ | CH6-OUT provides the filtered SD3_D0_R signal to the SD card connector DAT0 pin. | | 12 | CH5-OUT | SD3_CLK_R | ✅ | CH5-OUT provides the filtered SD3_CLK_R signal to the SD card connector CLOCK pin. | | 13 | CH4-OUT | SD3_CMD_R | ✅ | CH4-OUT provides the filtered SD3_CMD_R signal to the SD card connector CMD pin. | | 14 | CH3-OUT | SD3_D3_R | ✅ | CH3-OUT provides the filtered SD3_D3_R signal to the SD card connector CD/DAT3 pin. | | 15 | CH2-OUT | SD3_D2_R | ✅ | CH2-OUT provides the filtered SD3_D2_R signal to the SD card connector DAT2 pin. | | 16 | CH1-OUT | SD3_CD_R | ✅ | CH1-OUT provides the filtered SD3_CD_R signal to the SD card connector card detect pin. | | 17 | GND_PAD | GND | ✅ | GND_PAD is correctly connected to the ground plane. | </details> <details> <summary>U2 - TPD12S016PW ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/TPD12S016PW) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CEC_A | HDMI_CEC | ✅ | CEC_A pin connects to HDMI_CEC net for HDMI controller side CEC signal. Connection is correct. | | 2 | SCL_A | HDMI_DDCCLK | ✅ | SCL_A pin connects to HDMI_DDCCLK net with external 10kΩ pullup resistor R28. External pullup is not required per datasheet but is acceptable. | | 3 | SDA_A | HDMI_DDCDAT | ✅ | SDA_A pin connects to HDMI_DDCDAT net with external 10kΩ pullup resistor R30. External pullup is not required per datasheet but is acceptable. | | 4 | HPD_A | HDMI_HPD | ✅ | HPD_A pin connects to HDMI_HPD net for hot plug detect output to HDMI controller. Connection is correct. | | 5 | LS_OE | LS_OE | ✅ | LS_OE pin connects to net LS_OE with 2.2kΩ pullup resistor R172 to +V1P8S, enabling level shifters by default. Connection is correct. | | 6 | GND1 | GND | ✅ | GND1 pin is correctly connected to ground net GND. | | 7 | CEC_B | C_HDMI_CEC | ✅ | CEC_B pin connects to C_HDMI_CEC net and HDMI connector pin 15 for HDMI cable side CEC signal. Connection is correct. | | 8 | SCL_B | C_HDMI_SCL | ✅ | SCL_B pin connects to C_HDMI_SCL net and HDMI connector pin 17 for HDMI cable side SCL signal. Connection is correct. | | 9 | SDA_B | C_HDMI_SDA | ✅ | SDA_B pin connects to C_HDMI_SDA net and HDMI connector pin 18 for HDMI cable side SDA signal. Connection is correct. | | 10 | HPD_B | C_HDMI_HPD | ✅ | HPD_B pin connects to C_HDMI_HPD net and HDMI connector pin 1 for hot plug detect input from HDMI cable. Connection is correct. | | 11 | VCC5V | +5VSB | ✅ | VCC5V pin connects to +5VSB supply with 0.1µF decoupling capacitor C155. Connection is correct per datasheet recommendations. | | 12 | CT_HPD | HPD_ENB | ✅ | CT_HPD pin connects to net HPD_ENB with 2.2kΩ pullup resistor R171 to +V1P8S, enabling load switch and HPD by default. Connection is correct. | | 13 | 5V_OUT | +HDMI_CRT_VCC | ✅ | 5V_OUT pin connects to +HDMI_CRT_VCC with 4.7µF decoupling capacitor C157 and ferrite bead L7 to HDMI connector +5V pin. Connection is correct. | | 14 | GND2 | GND | ✅ | GND2 pin is correctly connected to ground net GND. | | 15 | CLK- | HDMI_OUT_CLK_DN | ✅ | CLK- pin connects to HDMI_OUT_CLK_DN through common mode choke L14 and to HDMI connector pin 14. Connection is correct. | | 16 | CLK+ | HDMI_OUT_CLK_DP | ✅ | CLK+ pin connects to HDMI_OUT_CLK_DP through common mode choke L14 and to HDMI connector pin 12. Connection is correct. | | 17 | D0- | HDMI_OUT_TX0_DN | ✅ | D0- pin connects to HDMI_OUT_TX0_DN through common mode choke L15 and to HDMI connector pin 11. Connection is correct. | | 18 | D0+ | HDMI_OUT_TX0_DP | ✅ | D0+ pin connects to HDMI_OUT_TX0_DP through common mode choke L15 and to HDMI connector pin 9. Connection is correct. | | 19 | GND3 | GND | ✅ | GND3 pin is correctly connected to ground net GND. | | 20 | D1- | HDMI_OUT_TX1_DN | ✅ | D1- pin connects to HDMI_OUT_TX1_DN through common mode choke L16 and to HDMI connector pin 8. Connection is correct. | | 21 | D1+ | HDMI_OUT_TX1_DP | ✅ | D1+ pin connects to HDMI_OUT_TX1_DP through common mode choke L16 and to HDMI connector pin 6. Connection is correct. | | 22 | D2- | HDMI_OUT_TX2_DN | ✅ | D2- pin connects to HDMI_OUT_TX2_DN through common mode choke L17 and to HDMI connector pin 5. Connection is correct. | | 23 | D2+ | HDMI_OUT_TX2_DP | ✅ | D2+ pin connects to HDMI_OUT_TX2_DP through common mode choke L17 and to HDMI connector pin 3. Connection is correct. | | 24 | VCCA | +V1P8S | ✅ | VCCA pin connects to +V1P8S supply with 0.1µF decoupling capacitor C17. Connection is correct per datasheet recommendations. | </details> <details> <summary>L16 - CM_CHOKE_4D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX1_C_DN | ✅ | IN1 pin connects to HDMI_TX1_C_DN, the negative side of the AC-coupled HDMI data channel 1 differential pair input. | | 3 | IN2 | HDMI_TX1_C_DP | ✅ | IN2 pin connects to HDMI_TX1_C_DP, the positive side of the AC-coupled HDMI data channel 1 differential pair input. | | 4 | OUT2 | HDMI_OUT_TX1_DP | ✅ | OUT2 pin connects to HDMI_OUT_TX1_DP, outputting the filtered positive data channel 1 signal to the ESD protection IC and HDMI connector. | | 6 | OUT1 | HDMI_OUT_TX1_DN | ✅ | OUT1 pin connects to HDMI_OUT_TX1_DN, outputting the filtered negative data channel 1 signal to the ESD protection IC and HDMI connector. | </details> <details> <summary>L15 - CM_CHOKE_4D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX0_C_DN | ✅ | IN1 pin connects to HDMI_TX0_C_DN, the negative side of the AC-coupled HDMI data channel 0 differential pair input. | | 3 | IN2 | HDMI_TX0_C_DP | ✅ | IN2 pin connects to HDMI_TX0_C_DP, the positive side of the AC-coupled HDMI data channel 0 differential pair input. | | 4 | OUT2 | HDMI_OUT_TX0_DP | ✅ | OUT2 pin connects to HDMI_OUT_TX0_DP, outputting the filtered positive data channel 0 signal to the ESD protection IC and HDMI connector. | | 6 | OUT1 | HDMI_OUT_TX0_DN | ✅ | OUT1 pin connects to HDMI_OUT_TX0_DN, outputting the filtered negative data channel 0 signal to the ESD protection IC and HDMI connector. | </details> <details> <summary>L17 - CM_CHOKE_4D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX2_C_DN | ✅ | IN1 pin connects to HDMI_TX2_C_DN, the negative side of the AC-coupled HDMI data channel 2 differential pair input. | | 3 | IN2 | HDMI_TX2_C_DP | ✅ | IN2 pin connects to HDMI_TX2_C_DP, the positive side of the AC-coupled HDMI data channel 2 differential pair input. | | 4 | OUT2 | HDMI_OUT_TX2_DP | ✅ | OUT2 pin connects to HDMI_OUT_TX2_DP, outputting the filtered positive data channel 2 signal to the ESD protection IC and HDMI connector. | | 6 | OUT1 | HDMI_OUT_TX2_DN | ✅ | OUT1 pin connects to HDMI_OUT_TX2_DN, outputting the filtered negative data channel 2 signal to the ESD protection IC and HDMI connector. | </details> <details> <summary>L14 - CM_CHOKE_4D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_CLK_C_DN | ✅ | IN1 pin connects to HDMI_CLK_C_DN, the negative side of the AC-coupled HDMI clock differential pair input. | | 3 | IN2 | HDMI_CLK_C_DP | ✅ | IN2 pin connects to HDMI_CLK_C_DP, the positive side of the AC-coupled HDMI clock differential pair input. | | 4 | OUT2 | HDMI_OUT_CLK_DP | ✅ | OUT2 pin connects to HDMI_OUT_CLK_DP, outputting the filtered positive clock signal to the ESD protection IC and HDMI connector. | | 6 | OUT1 | HDMI_OUT_CLK_DN | ✅ | OUT1 pin connects to HDMI_OUT_CLK_DN, outputting the filtered negative clock signal to the ESD protection IC and HDMI connector. | </details> <details> <summary>P1 - microHDMI_TH ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/158-0004513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | HPLG | C_HDMI_HPD | ✅ | Hot plug detect signal correctly connected to U2 HPD_B pin for detecting connector insertion. | | 2 | NC | | ✅ | No connection pin, correctly left unconnected. | | 3 | DAT2+ | HDMI_OUT_TX2_DP | ✅ | Data channel 2 positive signal correctly routed through common mode choke L17 and AC coupling capacitor C406 to U2. | | 4 | DAT2_S | GND | ✅ | Data channel 2 shield correctly connected to ground. | | 5 | DAT2- | HDMI_OUT_TX2_DN | ✅ | Data channel 2 negative signal correctly routed through common mode choke L17 and AC coupling capacitor C407 to U2. | | 6 | DAT1+ | HDMI_OUT_TX1_DP | ✅ | Data channel 1 positive signal correctly routed through common mode choke L16 and AC coupling capacitor C404 to U2. | | 7 | DAT1_S | GND | ✅ | Data channel 1 shield correctly connected to ground. | | 8 | DAT1- | HDMI_OUT_TX1_DN | ✅ | Data channel 1 negative signal correctly routed through common mode choke L16 and AC coupling capacitor C405 to U2. | | 9 | DAT0+ | HDMI_OUT_TX0_DP | ✅ | Data channel 0 positive signal correctly routed through common mode choke L15 and AC coupling capacitor C402 to U2. | | 10 | DAT0_S | GND | ✅ | Data channel 0 shield correctly connected to ground. | | 11 | DAT0- | HDMI_OUT_TX0_DN | ✅ | Data channel 0 negative signal correctly routed through common mode choke L15 and AC coupling capacitor C403 to U2. | | 12 | CLK+ | HDMI_OUT_CLK_DP | ✅ | Clock positive signal correctly routed through common mode choke L14 and AC coupling capacitor C400 to U2. | | 13 | CLK_S | GND | ✅ | Clock shield correctly connected to ground. | | 14 | CLK- | HDMI_OUT_CLK_DN | ✅ | Clock negative signal correctly routed through common mode choke L14 and AC coupling capacitor C401 to U2. | | 15 | CEC | C_HDMI_CEC | ✅ | CEC signal correctly connected to U2 CEC_B pin for consumer electronics control. | | 16 | DDC/CEC_GND | GND | ✅ | DDC/CEC ground correctly connected to system ground. | | 17 | SCL | C_HDMI_SCL | ✅ | I2C clock signal correctly connected to U2 SCL_B pin for DDC communication. | | 18 | SDA | C_HDMI_SDA | ✅ | I2C data signal correctly connected to U2 SDA_B pin for DDC communication. | | 19 | +5V | D5_0V_HDMI | ✅ | 5V power supply correctly provided from U2 charge pump output through ferrite bead L7. | | 20 | MTG1 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection. | | 21 | MTG2 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection. | | 22 | MTG3 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection. | | 23 | MTG4 | GND_EARTH | ✅ | Mounting pins correctly connected to earth ground through high voltage capacitors for ESD protection. | </details> <details> <summary>Q101 - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | HDMI_TERM | ✅ | Drain is connected to HDMI_TERM net, which connects to eight 619-ohm resistors (R801-R808) that provide DC bias restoration paths for HDMI differential pairs. This configuration is correct for providing a switchable ground reference for the HDMI signal termination network. | | G | GATE | $15N747 | ✅ | Gate is connected to +VCC3 power rail through 0-ohm resistor R809, making the MOSFET always ON when powered. This appears intentional for continuous DC bias restoration, though the adequacy depends on the +VCC3 voltage level being sufficient to fully enhance the MOSFET (ideally ≥2.5V). | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary>L7 - FERRITE_220OHM_2.2A_0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/ferriteBeadInductortypefilter/ENFA0003_PDF_FERRITEBEADINDUCTORTYPEFILTER?lastModifiedDatetime=20250707190934) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BLM18KG221SN1D) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +HDMI_CRT_VCC | ✅ | Input terminal of ferrite bead connected to +HDMI_CRT_VCC, which is the 5V output from U2 (TPD12S016PW) charge pump. This connection provides EMI filtering for power supplied to the HDMI connector. | | 2 | P2 | D5_0V_HDMI | ✅ | Output terminal of ferrite bead connected to D5_0V_HDMI, which supplies filtered 5V power to the HDMI connector pin 19. The 2200mA current rating is appropriate for HDMI power delivery requirements. | </details> <details> <summary>FB13 - 3044-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3044-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input side of ferrite bead connected to +5VSB supply rail. | | 2 | 2 | +USBVCC | ✅ | Output side of ferrite bead connected to +USBVCC, providing filtered power to USB power switch. | </details> <details> <summary>C92 - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bypass capacitor ground connection. | | 2 | 2 | +USBVCC | ✅ | Bypass capacitor power connection to +USBVCC rail. | </details> <details> <summary>C93 - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bypass capacitor ground connection. | | 2 | 2 | +USBVCC | ✅ | Bypass capacitor power connection to +USBVCC rail. | </details> <details> <summary>C94 - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bypass capacitor ground connection. | | 2 | 2 | +USBVCC | ✅ | Bypass capacitor power connection to +USBVCC rail. | </details> <details> <summary>U32 - AP2172MPG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP2162_72.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/AP2172MPG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | IN | +USBVCC | ✅ | Input power pin correctly connected to +USBVCC with adequate bypass capacitance. | | 3 | EN1 | USB_HOST_EN0 | ✅ | Enable input for switch 1 correctly connected through level translator to SOC control signal. | | 4 | EN2 | USB_HOST_EN1 | ✅ | Enable input for switch 2 correctly connected through level translator to SOC control signal. | | 5 | OC2# | SOC_USB_HOST_OC1 | ✅ | Open-drain overcurrent flag outputs correctly connected to SOC. External pull-up resistors are required by datasheet but not visible in this schematic section; they should be verified to exist at the SOC or elsewhere in the design. | | 8 | OC1# | SOC_USB_HOST_OC0 | ✅ | Open-drain overcurrent flag outputs correctly connected to SOC. External pull-up resistors are required by datasheet but not visible in this schematic section; they should be verified to exist at the SOC or elsewhere in the design. | | 6 | OUTB | USBP2 | ✅ | Switch 2 output correctly connected to USB port 2 power rail with appropriate filtering. | | 7 | OUTA | USBP1 | ✅ | Switch 1 output correctly connected to USB port 1 power rail with appropriate filtering. | | 9 | GND_PAD | GND | ✅ | Exposed pad correctly connected to GND for thermal and electrical grounding. | </details> <details> <summary>U4 - NTS0102GT ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 7 | VCCB | +USBVCC | ❌ | <details><summary>VCCB pin incorrectly connected to +USBVCC (approximately 5V), which exceeds the device's maximum voltage rating of 3.6V. This overvoltage condition could damage the device or cause malfunction.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="41.02,68.01,48.52,75.51" aspect-ratio="1.29" } <ul><li>Pin 7 (VCCB) is connected to +USBVCC net (from schematic)</li><li>The device voltage attribute specifies 1.2-3.6V operating range (from schematic)</li><li>+USBVCC is derived from +5VSB through ferrite bead FB13 (from schematic)</li><li>FB13 (part 3044-0012) is a ferrite bead inductor, not a voltage regulator, so +USBVCC voltage equals +5VSB voltage minus minimal resistive drop (from schematic)</li><li>+5VSB is a 5V standby supply based on standard power supply naming conventions (reasoning)</li><li>+USBVCC supplies U32 (AP2172MPG USB power switch) which has input voltage range 2.7V-5.5V, confirming +USBVCC is intended to be approximately 5V (from schematic)</li><li>U32 outputs USBP1 and USBP2 connect through ferrite beads L1 and L2 to VBUS1 and VBUS2, which supply USB connector USB1 pins 1 and 10 (from schematic)</li><li>USB VBUS specification requires 5V ±5% (4.75V-5.25V), therefore +USBVCC must be approximately 5V to provide proper USB power (reasoning)</li><li>Connecting VCCB to a 5V supply exceeds the 3.6V maximum rating by 1.4V (39% overvoltage) (reasoning)</li><li>This overvoltage condition violates the device absolute maximum ratings and could cause device damage, latchup, or unreliable operation (reasoning)</li><li>Recommended fix: Add a 3.3V or 1.8V LDO regulator to power VCCB from +USBVCC or +5VSB, ensuring VCCB stays within the 1.2-3.6V specification (reasoning)</li><li>Alternative fix: Replace NTS0102GT with a level translator that supports 5V on VCCB, such as TXS0102 or TXB0102 which support VCCB up to 5.5V (reasoning)</li></ul></details> | | 1 | B2 | USB_HOST_EN0 | ✅ | B2 pin correctly connected to USB_HOST_EN0 net, which drives the EN1 input of USB power switch U32. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VCCA | +V1P8A | ✅ | VCCA pin correctly connected to +V1P8A supply, providing 1.8V power for the A-side of the level translator. | | 4 | A2 | SOC_USB_HOST_EN0 | ✅ | A2 pin correctly connected to SOC_USB_HOST_EN0, receiving 1.8V enable signal from SOC for USB port 0. | | 5 | A1 | SOC_USB_HOST_EN1 | ✅ | A1 pin correctly connected to SOC_USB_HOST_EN1, receiving 1.8V enable signal from SOC for USB port 1. | | 6 | OE | USB_HOST_BUFF_ENB | ✅ | OE pin correctly connected to USB_HOST_BUFF_ENB with pull-up resistor R116 to +V1P8A, enabling the level translator by default. | | 8 | B1 | USB_HOST_EN1 | ✅ | B1 pin correctly connected to USB_HOST_EN1 net, which drives the EN2 input of USB power switch U32. | </details> <details> <summary>R116 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB_HOST_BUFF_ENB | ✅ | 10K pull-up resistor correctly connected between USB_HOST_BUFF_ENB (pin 1) and +V1P8A (pin 2), providing default enable state for U4 level translator. | | 2 | 2 | +V1P8A | ✅ | 10K pull-up resistor correctly connected between USB_HOST_BUFF_ENB (pin 1) and +V1P8A (pin 2), providing default enable state for U4 level translator. | </details> <details> <summary>U29 - TPD4USB30 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/TPD4USB30) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D1+ | USB3_TX0P_C | ✅ | D1+ provides ESD protection for the USB3 TX positive signal between the common mode choke and the connector. | | 2 | D1- | USB3_TX0N_C | ✅ | D1- provides ESD protection for the USB3 TX negative signal between the common mode choke and the connector. | | 3 | GND1 | GND | ✅ | GND1 provides ground reference for ESD protection on the first differential pair. | | 4 | D2+ | USB3_RX0P_C | ✅ | D2+ provides ESD protection for the USB3 RX positive signal between the connector and the common mode choke. | | 5 | D2- | USB3_RX0N_C | ✅ | D2- provides ESD protection for the USB3 RX negative signal between the connector and the common mode choke. | | 6 | NC4 | USB3_RX0N_C | ✅ | NC4 is connected to the USB3 RX negative signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected. | | 7 | NC3 | USB3_RX0P_C | ✅ | NC3 is connected to the USB3 RX positive signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected. | | 8 | GND2 | GND | ✅ | GND2 provides ground reference for ESD protection on the second differential pair. | | 9 | NC2 | USB3_TX0N_C | ✅ | NC2 is connected to the USB3 TX negative signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected. | | 10 | NC1 | USB3_TX0P_C | ✅ | NC1 is connected to the USB3 TX positive signal. Without datasheet confirmation, this connection should be verified as NC pins may need to be left unconnected. | </details> <details> <summary>C192 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXP0 | ✅ | AC coupling capacitor for USB3 TX positive signal. The 0.1uF value is correct per USB 3.0 specification requirements. | | 2 | 2 | USB3_TX0P-R | ✅ | AC coupling capacitor for USB3 TX positive signal. The 0.1uF value is correct per USB 3.0 specification requirements. | </details> <details> <summary>CHOKE1 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_RX0N_C | ✅ | IN1 receives the USB3 RX negative signal from the USB connector through ESD protection device U29. | | 3 | IN2 | USB3_RX0P_C | ✅ | IN2 receives the USB3 RX positive signal from the USB connector through ESD protection device U29. | | 4 | OUT2 | USB3_RXP0 | ✅ | OUT2 outputs the filtered USB3 RX positive signal to the SOC. | | 6 | OUT1 | USB3_RXN0 | ✅ | OUT1 outputs the filtered USB3 RX negative signal to the SOC. | </details> <details> <summary>C191 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXN0 | ✅ | AC coupling capacitor for USB3 TX negative signal. The 0.1uF value is correct per USB 3.0 specification requirements. | | 2 | 2 | USB3_TX0N-R | ✅ | AC coupling capacitor for USB3 TX negative signal. The 0.1uF value is correct per USB 3.0 specification requirements. | </details> <details> <summary>CHOKE2 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_TX0P-R | ✅ | IN1 carries the USB3 TX positive signal from the SOC through AC coupling capacitor C192 to the common mode choke input. | | 3 | IN2 | USB3_TX0N-R | ✅ | IN2 carries the USB3 TX negative signal from the SOC through AC coupling capacitor C191 to the common mode choke input. | | 4 | OUT2 | USB3_TX0N_C | ✅ | OUT2 outputs the USB3 TX negative signal to the ESD protection device U29 and ultimately to the USB connector. | | 6 | OUT1 | USB3_TX0P_C | ✅ | OUT1 outputs the USB3 TX positive signal to the ESD protection device U29 and ultimately to the USB connector. | </details> <details> <summary>U9 - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H0 | ✅ | D+ pin is connected to USB_H0, providing ESD protection for the USB D+ data line between the common mode choke and the USB connector. | | 2 | D- | USB_L0 | ✅ | D- pin is connected to USB_L0, providing ESD protection for the USB D- data line between the common mode choke and the USB connector. | | 3 | ID | | ✅ | ID pin is left unconnected. This is acceptable for USB host-only applications where the ID pin is not used. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the system ground net. | | 5 | NC | | ✅ | NC pin is not connected, which is correct as this pin is not internally connected per the datasheet. | | 6 | VBUS | VBUS1 | ✅ | VBUS pin is connected to VBUS1, providing ESD protection for the USB power line. The power flows from the power switch through a ferrite bead to this ESD protection device and then to the USB connector. | </details> <details> <summary>CHOKE4 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN0 | ✅ | IN1 is connected to USB_DN0, which is the USB D- signal from the SOC side. This pin is the input for the negative differential signal of the common mode choke. | | 3 | IN2 | USB_DP0 | ✅ | IN2 is connected to USB_DP0, which is the USB D+ signal from the SOC side. This pin is the input for the positive differential signal of the common mode choke. | | 4 | OUT2 | USB_H0 | ✅ | OUT2 is connected to USB_H0, which routes to the ESD protection device U9 and then to the USB connector. This is the output for the positive differential signal. | | 6 | OUT1 | USB_L0 | ✅ | OUT1 is connected to USB_L0, which routes to the ESD protection device U9 and then to the USB connector. This is the output for the negative differential signal. | </details> <details> <summary>U8 - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H1 | ✅ | D+ pin is connected to USB_H1, providing ESD protection for the D+ data line of USB Port B. | | 2 | D- | USB_L1 | ✅ | D- pin is connected to USB_L1, providing ESD protection for the D- data line of USB Port B. | | 3 | ID | | ✅ | ID pin is left floating, which is acceptable per the datasheet for applications where the ID pin is not used. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as it is not internally connected per the datasheet. | | 6 | VBUS | VBUS2 | ✅ | VBUS pin is connected to VBUS2, providing ESD protection for the VBUS line of USB Port B. | </details> <details> <summary>CHOKE3 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN1 | ✅ | IN1 is connected to USB_DN1, which is the D- input signal for USB Port B. This signal passes through the common mode choke and exits on pin 6 as USB_L1. | | 3 | IN2 | USB_DP1 | ✅ | IN2 is connected to USB_DP1, which is the D+ input signal for USB Port B. This signal passes through the common mode choke and exits on pin 4 as USB_H1. | | 4 | OUT2 | USB_H1 | ✅ | OUT2 is connected to USB_H1, which is the D+ output signal. This connects to the ESD protection device U8 pin 1 and then to the USB connector. | | 6 | OUT1 | USB_L1 | ✅ | OUT1 is connected to USB_L1, which is the D- output signal. This connects to the ESD protection device U8 pin 2 and then to the USB connector. | </details> <details> <summary>L1 - 126-0004781 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP1 | ✅ | Connected to USBP1, which is the output of USB power switch U32 pin 7 (OUTA). This is the input side of the ferrite bead filter. | | 2 | 2 | VBUS1 | ✅ | Connected to VBUS1, which supplies power to USB port A. This is the output side of the ferrite bead, providing filtered power to the USB connector and decoupling capacitors. | </details> <details> <summary>C91 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bulk decoupling capacitor (22uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing bulk capacitance for USB port A power supply. | | 2 | 2 | VBUS1 | ✅ | Bulk decoupling capacitor (22uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing bulk capacitance for USB port A power supply. | </details> <details> <summary>C70 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply. | | 2 | 2 | VBUS2 | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply. | </details> <details> <summary>C82 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply. | | 2 | 2 | VBUS1 | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply. | </details> <details> <summary>C234 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply. | | 2 | 2 | VBUS2 | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS2. Pin 1 connects to GND and pin 2 connects to VBUS2, providing high-frequency noise filtering for USB port B power supply. | </details> <details> <summary>C235 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply. | | 2 | 2 | VBUS1 | ✅ | High-frequency decoupling capacitor (0.1uF) for VBUS1. Pin 1 connects to GND and pin 2 connects to VBUS1, providing high-frequency noise filtering for USB port A power supply. | </details> <details> <summary>C103 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net for bulk decoupling capacitor reference. | | 2 | 2 | VBUS2 | ✅ | Connected to VBUS2 net, providing bulk capacitance for USB port B power rail. | </details> <details> <summary>USB1 - 258-0004503 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0004503) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUSA | VBUS1 | ✅ | VBUSA provides power to USB port A. Connected to VBUS1 with proper power switching, ESD protection, ferrite bead filtering, and decoupling capacitors. | | 2 | DA- | USB_L0 | ✅ | DA- is the USB 2.0 D- signal for port A. Connected to USB_L0 with proper ESD protection and common mode filtering. | | 3 | DA+ | USB_H0 | ✅ | DA+ is the USB 2.0 D+ signal for port A. Connected to USB_H0 with proper ESD protection and common mode filtering. | | 4 | GNDA | GND | ✅ | GNDA is the ground connection for USB port A, correctly connected to system ground. | | 5 | SSRX- | USB3_RX0N_C | ✅ | SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected to USB3_RX0N_C with proper ESD protection and common mode filtering. | | 6 | SSRX+ | USB3_RX0P_C | ✅ | SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected to USB3_RX0P_C with proper ESD protection and common mode filtering. | | 7 | GND_DRAIN | GND | ✅ | GND_DRAIN is the ground drain connection, correctly connected to system ground. | | 8 | SSTX- | USB3_TX0N_C | ✅ | SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected to USB3_TX0N_C with proper ESD protection, common mode filtering, and AC coupling. | | 9 | SSTX+ | USB3_TX0P_C | ✅ | SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected to USB3_TX0P_C with proper ESD protection, common mode filtering, and AC coupling. | | 10 | VBUSB | VBUS2 | ✅ | VBUSB provides power to USB port B. Connected to VBUS2 with proper power switching, ESD protection, ferrite bead filtering, and decoupling capacitors. | | 11 | DB- | USB_L1 | ✅ | DB- is the USB 2.0 D- signal for port B. Connected to USB_L1 with proper ESD protection and common mode filtering. | | 12 | DB+ | USB_H1 | ✅ | DB+ is the USB 2.0 D+ signal for port B. Connected to USB_H1 with proper ESD protection and common mode filtering. | | 13 | GNDB | GND | ✅ | GNDB is the ground connection for USB port B, correctly connected to system ground. | | MH1 | SHIELD1 | GND_EARTH | ✅ | Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity. | | MH2 | SHIELD2 | GND_EARTH | ✅ | Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity. | | MH3 | SHIELD3 | GND_EARTH | ✅ | Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity. | | MH4 | SHIELD4 | GND_EARTH | ✅ | Shield connections for EMI and ESD protection. Connected to GND_EARTH with optional high-voltage capacitor C211 (DNI) to system ground for conducted immunity. | </details> <details> <summary>J10 - 158-0004534 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/158-0004534) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 2 | 2 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 13 | 13 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 14 | 14 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 25 | 25 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 26 | 26 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 37 | 37 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 38 | 38 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 49 | 49 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 50 | 50 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 59 | 59 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 60 | 60 | GND | ✅ | Ground pins providing return paths for signals and power. Multiple ground pins are standard practice for signal integrity in high-speed connectors. | | 3 | 3 | mSATA_TX_P | ✅ | mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5). Standard differential signaling for SATA interface. | | 5 | 5 | mSATA_TX_N | ✅ | mSATA transmit differential pair (TX_P on pin 3, TX_N on pin 5). Standard differential signaling for SATA interface. | | 4 | 4 | mSATA_RX_P | ✅ | mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6). Standard differential signaling for SATA interface. | | 6 | 6 | mSATA_RX_N | ✅ | mSATA receive differential pair (RX_P on pin 4, RX_N on pin 6). Standard differential signaling for SATA interface. | | 7 | 7 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 8 | 8 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 19 | 19 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 20 | 20 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 31 | 31 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 32 | 32 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 43 | 43 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 44 | 44 | +5VSB | ✅ | Power supply pins providing +5VSB (5V standby power). Multiple power pins reduce voltage drop and improve power distribution. | | 9 | 9 | mPCIE_REFCLK_P | ✅ | mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11). Provides clock reference for PCIe interface. | | 11 | 11 | mPCIE_REFCLK_N | ✅ | mPCIE reference clock differential pair (REFCLK_P on pin 9, REFCLK_N on pin 11). Provides clock reference for PCIe interface. | | 10 | 10 | USB_HOST_DP | ✅ | USB host differential pair (DP on pin 10, DN on pin 12). Standard USB 2.0 signaling. | | 12 | 12 | USB_HOST_DN | ✅ | USB host differential pair (DP on pin 10, DN on pin 12). Standard USB 2.0 signaling. | | 15 | 15 | mPCIE_TX_P | ✅ | mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17). Standard differential signaling for PCIe interface. | | 17 | 17 | mPCIE_TX_N | ✅ | mPCIE transmit differential pair (TX_P on pin 15, TX_N on pin 17). Standard differential signaling for PCIe interface. | | 16 | 16 | mPCIE_RX_N | ✅ | mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18). A schematic note explicitly states this inversion is for ease of layout routing. | | 18 | 18 | mPCIE_RX_P | ✅ | mPCIE receive differential pair with intentional polarity inversion (RX_N on pin 16, RX_P on pin 18). A schematic note explicitly states this inversion is for ease of layout routing. | | 21 | 21 | I2C6_SCL | ✅ | I2C bus signals (SCL on pin 21, SDA on pin 23) with proper 10K pull-up resistors to +V1P8S. Standard I2C configuration. | | 23 | 23 | I2C6_SDA | ✅ | I2C bus signals (SCL on pin 21, SDA on pin 23) with proper 10K pull-up resistors to +V1P8S. Standard I2C configuration. | | 22 | 22 | mPCIE_WAKEB | ✅ | mPCIE wake signal (active low). Used to wake the system from low power states. | | 24 | 24 | mPCIe_CLKREQ3_B | ✅ | mPCIE clock request signal (active low). Used for PCIe clock power management. | | 27 | 27 | EXP_GPIO1 | ✅ | Expansion GPIO signals providing general-purpose I/O capability through the connector. | | 28 | 28 | EXP_GPIO3 | ✅ | Expansion GPIO signals providing general-purpose I/O capability through the connector. | | 29 | 29 | EXP_GPIO2 | ✅ | Expansion GPIO signals providing general-purpose I/O capability through the connector. | | 30 | 30 | EXP_GPIO4 | ✅ | Expansion GPIO signals providing general-purpose I/O capability through the connector. | | 33 | 33 | XDP_H_OBSDATA_A1 | ✅ | XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface. | | 34 | 34 | XDP_H_OBSDATA_A0 | ✅ | XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface. | | 35 | 35 | XDP_H_OBSDATA_A2 | ✅ | XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface. | | 36 | 36 | XDP_H_OBSDATA_A3 | ✅ | XDP observation data signals (OBSDATA_A0 through A3). Part of Intel eXtensible Debug Port interface. | | 39 | 39 | XDP_H_PRDYB | ✅ | XDP probe ready signal (active low). Indicates debug probe is ready. | | 40 | 40 | XDP_H_PREQB_PB | ✅ | XDP probe request signal (active low) buffered through U1 with a 200 ohm pull-up. The low pull-up value may be intentional for XDP timing requirements. | | 41 | 41 | HOOK0 | ✅ | HOOK0 signal connected to PMC_RSMRST through 1K series resistor R15. Provides resume reset signal to expansion connector. | | 42 | 42 | HOOK1 | ✅ | HOOK1 signal connected to FP_PWRBTN through 0 ohm jumper R5. Optional 4.7K pull-down R4 is DNI. | | 45 | 45 | HOOK2 | ✅ | HOOK2 signal connected to PMC_CORE_PWROK through 1K series resistor R16. Provides core power good signal to expansion connector. | | 46 | 46 | PMC_RSTBTN | ✅ | PMC reset button signal with 1K pull-up to +V1P8S and 0.1uF filter capacitor. Standard reset button configuration. | | 47 | 47 | HOOK6 | ✅ | HOOK6 signal connected to PMC_PLTRST_R_V1P8 through 1K series resistor R17. Provides platform reset signal to expansion connector. | | 48 | 48 | ILB_RTC_TESTB | ✅ | RTC test signal (active low) with 1K pull-up to +RTCVCC and 1uF filter capacitor. Standard test pin configuration. | | 51 | 51 | HOOK4 | ✅ | HOOK4 signal connected to +3VSB through 0 ohm jumper R18. Provides 3.3V standby power to expansion connector. | | 52 | 52 | XDP_H_TRSTB | ✅ | XDP test reset signal (active low). Part of JTAG-like debug interface. | | 53 | 53 | HOOK5 | ✅ | HOOK5 signal connected to +V1P8S through 0 ohm jumper R20. Provides 1.8V standby power to expansion connector. | | 54 | 54 | XDP_H_TCK | ✅ | XDP test clock signal. Part of JTAG-like debug interface. | | 55 | 55 | +V1P8A | ✅ | Power supply pin providing +V1P8A (1.8V analog power). This pin supplies power for 1.8V level signals on the expansion connector. | | 56 | 56 | XDP_H_TMS | ✅ | XDP test mode select signal. Part of JTAG-like debug interface. | | 57 | 57 | XDP_H_TDO | ✅ | XDP test data out signal with 51 ohm pull-up to +V1P8A. The unusually low pull-up value may be a design concern or intentional for specific XDP requirements. | | 58 | 58 | XDP_H_TDI | ✅ | XDP test data in signal. Part of JTAG-like debug interface. | </details> <details> <summary>R3 - 200 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XDP_H_PREQB_PB | ✅ | Pull-up resistor providing 200 ohm resistance between XDP_H_PREQB_PB signal (pin 1) and +V1P8A power rail (pin 2), ensuring defined input state for buffer U1. | | 2 | 2 | +V1P8A | ✅ | Pull-up resistor providing 200 ohm resistance between XDP_H_PREQB_PB signal (pin 1) and +V1P8A power rail (pin 2), ensuring defined input state for buffer U1. | </details> <details> <summary>R21 - 51 OHM 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pull-up resistor providing 51 ohm resistance between +V1P8A power rail (pin 1) and XDP_H_TDO signal (pin 2). The unusually low resistance value appears intentional for signal integrity on the high-speed XDP debug interface. | | 2 | 2 | XDP_H_TDO | ✅ | Pull-up resistor providing 51 ohm resistance between +V1P8A power rail (pin 1) and XDP_H_TDO signal (pin 2). The unusually low resistance value appears intentional for signal integrity on the high-speed XDP debug interface. | </details> <details> <summary>C5 - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bypass/decoupling capacitor correctly connected between GND (pin 1) and +V1P8A power rail (pin 2), providing power supply decoupling for U1 as recommended by the datasheet. | | 2 | 2 | +V1P8A | ✅ | Bypass/decoupling capacitor correctly connected between GND (pin 1) and +V1P8A power rail (pin 2), providing power supply decoupling for U1 as recommended by the datasheet. | </details> <details> <summary>U1 - SN74AUP1G34 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](http://www.ti.com/lit/gpn/SN74AUP1G34) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/sn74aup1g34_dbv_5) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC (No Connect) pin is correctly left unconnected as specified in the datasheet. | | 2 | A | XDP_H_PREQB_PB | ✅ | Input A is correctly connected to XDP_H_PREQB_PB signal from connector J10 pin 40, with a 200 ohm pull-up resistor (R3) to +V1P8A providing a defined logic level. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | XDP_H_PREQB | ✅ | Output Y is correctly connected to net XDP_H_PREQB, providing the buffered version of the input signal. | | 5 | VCC | +V1P8A | ✅ | VCC pin is correctly connected to +V1P8A (1.8V supply) with proper bypass capacitor C5 (0.1uF) for decoupling. | </details> <details> <summary>R13 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SCL | ✅ | Pin 1 connects to I2C6_SCL signal line, which goes to expansion connector J10 pin 21. This is one side of the I2C pull-up resistor. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C6_SCL line. The 10K ohm value is appropriate for I2C pull-up at 1.8V. | </details> <details> <summary>R14 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SDA | ✅ | Pin 1 connects to I2C6_SDA signal line, which goes to expansion connector J10 pin 23. This is one side of the I2C pull-up resistor. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C6_SDA line. The 10K ohm value is appropriate for I2C pull-up at 1.8V. | </details> <details> <summary>U42 - WGI210AT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4300-0071) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | LAN_PWR_GOOD | $18N3538 | ✅ | LAN_PWR_GOOD output with 10K pull-up to +3VSB_LAN through R828. This is a power good indicator signal. | | 2 | NC_SI_CLK_IN | $18N3372 | ✅ | NC_SI interface pins (CLK_IN, CRS_DV, TX_EN) pulled to GND through 1K resistors. These unused serial interface pins are terminated to a known state. | | 3 | NC_SI_CRS_DV | $18N3374 | ✅ | NC_SI interface pins (CLK_IN, CRS_DV, TX_EN) pulled to GND through 1K resistors. These unused serial interface pins are terminated to a known state. | | 7 | NC_SI_TX_EN | $18N3376 | ✅ | NC_SI interface pins (CLK_IN, CRS_DV, TX_EN) pulled to GND through 1K resistors. These unused serial interface pins are terminated to a known state. | | 4 | JTAG_TDO | | ✅ | JTAG_TDO is left unconnected. This is acceptable when JTAG debugging is not used. | | 5 | NC_SI_RXD1 | $18N3305 | ✅ | NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state. | | 6 | NC_SI_RXD0 | $18N3303 | ✅ | NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state. | | 8 | NC_SI_TXD1 | $18N3301 | ✅ | NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state. | | 9 | NC_SI_TXD0 | $18N3299 | ✅ | NC_SI interface pins (RXD1, RXD0, TXD1, TXD0) pulled to +3VSB_LAN through 10K resistors. These unused serial interface pins are terminated to a known state. | | 10 | VDD3P3_10 | +3VSB_LAN | ✅ | VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors. | | 27 | VDD3P3_27 | +3VSB_LAN | ✅ | VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors. | | 41 | VDD3P3_41 | +3VSB_LAN | ✅ | VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors. | | 51 | VDD3P3_51 | +3VSB_LAN | ✅ | VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors. | | 64 | VDD3P3_64 | +3VSB_LAN | ✅ | VDD3P3 power supply pins correctly connected to +3VSB_LAN with adequate decoupling capacitors. | | 11 | VDD0P9_11 | +0V9_LAN | ✅ | VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors. | | 32 | VDD0P9_32 | +0V9_LAN | ✅ | VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors. | | 42 | VDD0P9_42 | +0V9_LAN | ✅ | VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors. | | 59 | VDD0P9_59 | +0V9_LAN | ✅ | VDD0P9 power supply pins correctly connected to +0V9_LAN with adequate decoupling capacitors. | | 12 | NVM_SI | $18N2399 | ✅ | NVM_SI (SPI MOSI) connects to flash memory U43 pin 5 through 33.2 ohm series resistor R832 for signal integrity. | | 13 | NVM_SK | $18N2397 | ✅ | NVM_SK (SPI Clock) connects to flash memory U43 pin 6 through 33.2 ohm series resistor R834 for signal integrity. | | 14 | NVM_SO | $18N3554 | ✅ | NVM_SO (SPI MISO) connects to flash memory U43 pin 2 through 33.2 ohm series resistor R833 for signal integrity. | | 15 | NVM_CS_N | $18N2395 | ✅ | NVM_CS_N (SPI Chip Select) connects to flash memory U43 pin 1 through 33.2 ohm series resistor R835 for signal integrity. | | 16 | PE_WAKE_N | PMC_PCIE_WAKE | ✅ | PE_WAKE_N connects to PMC_PCIE_WAKE for PCIe wake signaling. | | 17 | PE_RST_N | PMC_PLTRST_L | ✅ | PE_RST_N connects to PMC_PLTRST_L for PCIe reset signaling. | | 18 | JTAG_TMS | $18N3293 | ✅ | JTAG_TMS with 10K pull-up to +3VSB_LAN through R820. Correct termination for unused JTAG. | | 19 | JTAG_CLK | $18N3295 | ✅ | JTAG_CLK with 10K pull-up to +3VSB_LAN through R821. Correct termination for unused JTAG. | | 20 | PE_TXN | PCIE_C_RXP2 | ✅ | PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification. | | 21 | PE_TXP | PCIE_C_RXN2 | ✅ | PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification. | | 23 | PE_RXN | PCIE_C_TXP2 | ✅ | PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification. | | 24 | PE_RXP | PCIE_C_TXN2 | ✅ | PCIe TX and RX differential pairs with intentional polarity inversion on both pairs for routing convenience. This is explicitly noted on the schematic and is supported by the PCIe specification. | | 22 | NC/INTVCC | | ✅ | NC/INTVCC pin is left unconnected. This is likely an internal voltage or no-connect pin. | | 25 | PECLK_N | PCIE_CLK-N2 | ✅ | PECLK_N and PECLK_P are the PCIe reference clock differential pair inputs, connected to PCIE_CLK-N2 and PCIE_CLK-P2 respectively. | | 26 | PECLK_P | PCIE_CLK-P2 | ✅ | PECLK_N and PECLK_P are the PCIe reference clock differential pair inputs, connected to PCIE_CLK-N2 and PCIE_CLK-P2 respectively. | | 28 | DEV_OFF_N | $18N3540 | ✅ | DEV_OFF_N with 10K pull-up to +3VSB_LAN through R827. This keeps the device enabled by default. | | 29 | JTAG_TDI | $18N3297 | ✅ | JTAG_TDI with 10K pull-up to +3VSB_LAN through R822. Correct termination for unused JTAG. | | 30 | LED1 | LAN-LED1 | ✅ | LED1 output drives LINK-LED-N through 301 ohm current limiting resistor R843 to control LED in RJ45 connector J11. | | 31 | LED0 | LAN-LED0 | ✅ | LED0 output connects to RJ45 connector J11 pin 11 for differential LED drive with LED2. | | 33 | LED2 | LAN-LED2 | ✅ | LED2 output drives 1G-LED-N through 301 ohm current limiting resistor R844 to control LED in RJ45 connector J11. | | 34 | SMB_CLK | LAN-SMB-CLK | ✅ | SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected to system SMBus signals for management interface. | | 35 | SMB_ALRT_N | LAN-SMB-ALERT# | ✅ | SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected to system SMBus signals for management interface. | | 36 | SMB_DATA | LAN-SMB-DATA | ✅ | SMBus interface pins (SMB_CLK, SMB_ALRT_N, SMB_DATA) connected to system SMBus signals for management interface. | | 37 | CBOT | $18N2590 | ✅ | CBOT and CTOP pins connected through 0.039uF capacitor C425 for internal charge pump or regulator. | | 40 | CTOP | $18N2588 | ✅ | CBOT and CTOP pins connected through 0.039uF capacitor C425 for internal charge pump or regulator. | | 38 | VDD0P9_OUT | +0V9_LAN | ✅ | VDD0P9_OUT is the internal 0.9V regulator output, correctly connected to +0V9_LAN rail. | | 39 | VDD1P5_OUT | +1V5_LAN | ✅ | VDD1P5_OUT is the internal 1.5V regulator output, correctly connected to +1V5_LAN rail. | | 43 | NC_SI_ARB_IN | | ✅ | NC_SI_ARB_IN and NC_SI_ARB_OUT are left unconnected. These are unused serial interface arbitration pins. | | 44 | NC_SI_ARB_OUT | | ✅ | NC_SI_ARB_IN and NC_SI_ARB_OUT are left unconnected. These are unused serial interface arbitration pins. | | 45 | XTAL2 | LAN_XTAL2 | ✅ | XTAL2 and XTAL1 connect to 25MHz crystal X1 with appropriate 27pF load capacitors C252 and C253. | | 46 | XTAL1 | LAN_XTAL1 | ✅ | XTAL2 and XTAL1 connect to 25MHz crystal X1 with appropriate 27pF load capacitors C252 and C253. | | 47 | VDD1P5_47 | +1V5_LAN | ✅ | VDD1P5 power supply pins correctly connected to +1V5_LAN with adequate decoupling capacitors. | | 56 | VDD1P5_56 | +1V5_LAN | ✅ | VDD1P5 power supply pins correctly connected to +1V5_LAN with adequate decoupling capacitors. | | 48 | RSET | LAN_RSET | ✅ | RSET pin connected to GND through 4.99K resistor R836 to set internal reference currents. | | 49 | MDI_MINUS3/SER_N | MDI_N3 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 50 | MDI_PLUS3/SER_P | MDI_P3 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 52 | MDI_MINUS2/SET_N | MDI_N2 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 53 | MDI_PLUS2 | MDI_P2 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 54 | MDI_MINUS1/SRDS_SIG_DET | MDI_N1 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 55 | MDI_PLUS1/SFP_I2C_CLK | MDI_P1 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 57 | MDI_MINUS0/SFP_I2C_DATA | MDI_N0 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 58 | MDI_PLUS0/NC | MDI_P0 | ✅ | MDI differential pairs correctly connected to RJ45 connector J11 for Gigabit Ethernet interface. | | 60 | SDP3 | | ✅ | SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs. | | 61 | SDP1/PCIE_DIS | | ✅ | SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs. | | 62 | SDP2 | | ✅ | SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs. | | 63 | SDP0 | | ✅ | SDP configuration pins left unconnected. Without datasheet, cannot verify if these require external termination or have internal pull-ups/downs. | | 65 | GND_PAD | GND | ✅ | GND_PAD correctly connected to GND for thermal and electrical grounding of QFN package. | </details> <details> <summary>R832 - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2435 | ✅ | Connected to U43 pin 5 (SI) on net $18N2435. This is the flash memory side of the series resistor on the SPI MOSI line. | | 2 | 2 | $18N2399 | ✅ | Connected to U42 pin 12 (NVM_SI) on net $18N2399. This is the controller side of the series resistor on the SPI MOSI line. | </details> <details> <summary>R833 - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3554 | ✅ | Connected to U42 pin 14 (NVM_SO) on net $18N3554. This is the controller side of the series resistor on the SPI MISO line. | | 2 | 2 | $18N3552 | ✅ | Connected to U43 pin 2 (SO) on net $18N3552. This is the flash memory side of the series resistor on the SPI MISO line. | </details> <details> <summary>R834 - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2437 | ✅ | Connected to U43 pin 6 (SCK) on net $18N2437. This is the flash memory side of the series resistor on the SPI clock line. | | 2 | 2 | $18N2397 | ✅ | Connected to U42 pin 13 (NVM_SK) on net $18N2397. This is the controller side of the series resistor on the SPI clock line. | </details> <details> <summary>R835 - 1120-0003 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2439 | ✅ | Connected to U43 pin 1 (CS#) on net $18N2439. This is the flash memory side of the series resistor on the SPI chip select line. | | 2 | 2 | $18N2395 | ✅ | Connected to U42 pin 15 (NVM_CS_N) on net $18N2395. This is the controller side of the series resistor on the SPI chip select line. | </details> <details> <summary>R829 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3609 | ✅ | Connected to U43 pin 3 (WP#) on net $18N3609. This DNI resistor would pull WP# to ground if installed, enabling hardware write protection. | | 2 | 2 | GND | ✅ | Connected to GND. This DNI resistor would pull WP# to ground if installed. | </details> <details> <summary>R830 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Connected to +3VSB_LAN. This resistor pulls U43 pin 3 (WP#) high to disable hardware write protection. | | 2 | 2 | $18N3609 | ✅ | Connected to U43 pin 3 (WP#) on net $18N3609. This pull-up resistor disables hardware write protection as recommended by the datasheet. | </details> <details> <summary>R831 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Connected to +3VSB_LAN. This resistor pulls U43 pin 7 (HOLD#) high to disable the hold function. | | 2 | 2 | $18N3659 | ✅ | Connected to U43 pin 7 (HOLD#) on net $18N3659. This pull-up resistor disables the hold function as recommended by the datasheet. | </details> <details> <summary>U43 - AT25DF081A-SSH ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25df081a-datasheet?language=en) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4356-0082) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | $18N2439 | ✅ | CS# (Chip Select) is correctly connected to the Ethernet controller U42 through series resistor R835. | | 2 | SO | $18N3552 | ✅ | SO (Serial Output) is correctly connected to the Ethernet controller U42 through series resistor R833. | | 3 | WP# | $18N3609 | ✅ | WP# (Write Protect) is correctly pulled high through R830 (10KΩ) to disable hardware write protection, following datasheet recommendations. | | 4 | GND | GND | ✅ | GND is correctly connected to the system ground plane. | | 5 | SI | $18N2435 | ✅ | SI (Serial Input) is correctly connected to the Ethernet controller U42 through series resistor R832, with a weak pull-up through R848. | | 6 | SCK | $18N2437 | ✅ | SCK (Serial Clock) is correctly connected to the Ethernet controller U42 through series resistor R834. | | 7 | HOLD# | $18N3659 | ✅ | HOLD# is correctly pulled high through R831 (10KΩ) to disable the hold function, following datasheet recommendations. | | 8 | VCC | +3VSB_LAN | ✅ | VCC is correctly connected to +3VSB_LAN (3.3V standby power), which is within the specified operating voltage range. | </details> <details> <summary>J11 - 3362-0042 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3362-0042) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 11 | LED2_AC1 | LAN-LED0 | ❌ | <details><summary>LED2_AC1 connects directly to U42 LED0 output (pin 31) without a current limiting resistor, unlike the other LED outputs which have 301Ω resistors. This asymmetry indicates a likely missing component in the design.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="116841b2cce1b13c9d52" diff-visibility="full" variant="default" view-coords="79.20,65.65,86.70,73.15" aspect-ratio="1.29" } <ul><li>Pin 11 (LED2_AC1) connects to net LAN-LED0 (from schematic)</li><li>LAN-LED0 connects directly to U42 pin 31 (LED0 output) (from schematic)</li><li>No current limiting resistor exists between U42 pin 31 and J11 pin 11 (from schematic)</li><li>U42 pin 30 (LED1) connects through R843 (301Ω) to LINK-LED-N and then to J11 pin 13 (from schematic)</li><li>U42 pin 33 (LED2) connects through R844 (301Ω) to 1G-LED-N and then to J11 pin 12 (from schematic)</li><li>C431 (560pF) provides EMI filtering on the LAN-LED0 signal (from schematic)</li><li>The WGI210AT (U42) is an Intel Ethernet controller whose LED outputs are typically open-drain and require external current limiting resistors (reasoning)</li><li>The asymmetry in the design (two LED outputs have current limiting resistors, one does not) is inconsistent with standard LED drive practices and indicates a likely missing component (reasoning)</li><li>Without a current limiting resistor, excessive current could flow through the LED or damage the U42 output driver (reasoning)</li><li>A resistor similar to R843 and R844 (approximately 301Ω) should be added in series between U42 pin 31 and J11 pin 11 (reasoning)</li></ul></details> | | 1 | MD1+ | MDI_P0 | ✅ | MDI pair 0 (MD1+/MD1-) correctly connected to U42 pins 58/57 for Ethernet differential signaling. | | 2 | MD1- | MDI_N0 | ✅ | MDI pair 0 (MD1+/MD1-) correctly connected to U42 pins 58/57 for Ethernet differential signaling. | | 3 | MD2+ | MDI_P1 | ✅ | MDI pair 1 (MD2+/MD2-) correctly connected to U42 pins 55/54 for Ethernet differential signaling. | | 4 | MD2- | MDI_N1 | ✅ | MDI pair 1 (MD2+/MD2-) correctly connected to U42 pins 55/54 for Ethernet differential signaling. | | 5 | CT1 | $18N3856 | ✅ | Center tap pins correctly tied together and bypassed to ground through C426, C427, and C428 for common-mode filtering. | | 6 | CT2 | $18N3856 | ✅ | Center tap pins correctly tied together and bypassed to ground through C426, C427, and C428 for common-mode filtering. | | 7 | MD3+ | MDI_P2 | ✅ | MDI pair 2 (MD3+/MD3-) correctly connected to U42 pins 53/52 for Ethernet differential signaling. | | 8 | MD3- | MDI_N2 | ✅ | MDI pair 2 (MD3+/MD3-) correctly connected to U42 pins 53/52 for Ethernet differential signaling. | | 9 | MD4+ | MDI_P3 | ✅ | MDI pair 3 (MD4+/MD4-) correctly connected to U42 pins 50/49 for Ethernet differential signaling. | | 10 | MD4- | MDI_N3 | ✅ | MDI pair 3 (MD4+/MD4-) correctly connected to U42 pins 50/49 for Ethernet differential signaling. | | 12 | LED2_AD1 | 1G-LED-N | ✅ | LED2_AD1 connects through R844 (301Ω) to U42 LED2 output, providing proper current limiting for the LED signal. | | 13 | LED1_C | LINK-LED-N | ✅ | LED1 cathode correctly connected through R843 to U42 LED1 output for active-low LED drive with proper current limiting. | | 14 | LED1_A | +3VSB_LAN | ✅ | LED1 anode correctly connected to +3VSB_LAN power supply for LED operation. | | 15 | SHLD1 | GND_EARTH | ✅ | Shield pins correctly connected to GND_EARTH for EMI/ESD protection with proper isolation from circuit ground. | | 16 | SHLD2 | GND_EARTH | ✅ | Shield pins correctly connected to GND_EARTH for EMI/ESD protection with proper isolation from circuit ground. | </details> <details> <summary>R843 - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED1 | ✅ | 301Ω current-limiting resistor between U42 LED1 output and J11 LED1_C pin for link status LED indication. | | 2 | 2 | LINK-LED-N | ✅ | 301Ω current-limiting resistor between U42 LED1 output and J11 LED1_C pin for link status LED indication. | </details> <details> <summary>R844 - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED2 | ✅ | 301Ω current-limiting resistor between U42 LED2 output and J11 LED2_AD1 pin for speed/activity LED indication. | | 2 | 2 | 1G-LED-N | ✅ | 301Ω current-limiting resistor between U42 LED2 output and J11 LED2_AD1 pin for speed/activity LED indication. | </details> <details> <summary>C429 - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LINK-LED-N | ✅ | 560pF filter capacitor on LINK-LED-N signal for EMI suppression on the LED1 cathode line. | | 2 | 2 | GND | ✅ | 560pF filter capacitor on LINK-LED-N signal for EMI suppression on the LED1 cathode line. | </details> <details> <summary>C430 - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1G-LED-N | ✅ | 560pF filter capacitor on 1G-LED-N signal for EMI suppression on the LED2 cathode line. | | 2 | 2 | GND | ✅ | 560pF filter capacitor on 1G-LED-N signal for EMI suppression on the LED2 cathode line. | </details> <details> <summary>C431 - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED0 | ✅ | 560pF filter capacitor on LAN-LED0 signal for EMI suppression. Note that the LAN-LED0 signal path lacks a current limiting resistor (see J11 pin 11 analysis). | | 2 | 2 | GND | ✅ | 560pF filter capacitor on LAN-LED0 signal for EMI suppression. Note that the LAN-LED0 signal path lacks a current limiting resistor (see J11 pin 11 analysis). | </details> <details> <summary>X1 - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Crystal terminal connected to XTAL2 pin of U42 through LAN_XTAL2 net, with load capacitor C253 to ground. | | 2 | 2 | GND | ✅ | Ground connection for mechanical stability and EMI reduction. | | 3 | 3 | LAN_XTAL1 | ✅ | Crystal terminal connected to XTAL1 pin of U42 through LAN_XTAL1 net, with load capacitor C252 to ground. | | 4 | 4 | GND | ✅ | Ground connection for mechanical stability and EMI reduction. | </details> <details> <summary>C253 - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Load capacitor connected to XTAL2 pin of U42 for crystal oscillator circuit. | | 2 | 2 | GND | ✅ | Ground connection for load capacitor. | </details> <details> <summary>C252 - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL1 | ✅ | Load capacitor connected to XTAL1 pin of U42 for crystal oscillator circuit. | | 2 | 2 | GND | ✅ | Ground connection for load capacitor. | </details> <details> <summary>R836 - 1120-0018 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0018) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing ground reference for the RSET resistor. | | 2 | 2 | LAN_RSET | ✅ | Connected to LAN_RSET net, which connects to pin 48 (RSET) of U42 (WGI210AT). This sets an internal reference or bias current for the LAN controller. | </details> <details> <summary>C425 - 2221-0017 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0017) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2588 | ✅ | Connected to net $18N2588, which connects to pin 40 (CTOP) of U42. This is one terminal of an external capacitor required by the LAN controller IC. | | 2 | 2 | $18N2590 | ✅ | Connected to net $18N2590, which connects to pin 37 (CBOT) of U42. This is the other terminal of the external capacitor, completing the CTOP-CBOT capacitor configuration. | </details> <details> <summary>FB12 - 3044-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3044-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB | ✅ | Input pin connected to +3VSB standby power rail, providing the source voltage for filtering. | | 2 | 2 | +3VSB_LAN | ✅ | Output pin connected to +3VSB_LAN, providing filtered power to the Ethernet subsystem including U42 and U43. | </details> <details> <summary>C426 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Connected to Ethernet magnetics center tap network ($18N3856) along with C427 and C428. Provides AC bypass and common-mode filtering for the center taps. | | 2 | 2 | GND | ✅ | Connected to GND, providing the return path for center tap bypass network. | </details> <details> <summary>C427 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Connected to Ethernet magnetics center tap network ($18N3856) in parallel with C426 and C428. Provides AC bypass and common-mode filtering. | | 2 | 2 | GND | ✅ | Connected to GND, providing the return path for center tap bypass network. | </details> <details> <summary>C428 - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Connected to Ethernet magnetics center tap network ($18N3856) in parallel with C426 and C427. The larger 1.0uF value provides lower frequency filtering. | | 2 | 2 | GND | ✅ | Connected to GND, providing the return path for center tap bypass network. | </details> <details> <summary>R828 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connection to +3VSB_LAN power rail. This provides the pull-up voltage for the LAN_PWR_GOOD signal. | | 2 | 2 | $18N3538 | ✅ | Connected to LAN_PWR_GOOD signal (U42 pin 1). This pull-up resistor is typically used to pull the power good input high, indicating stable power supply conditions to the LAN controller. | </details> <details> <summary>R827 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Pull-up resistor connection to +3VSB_LAN power rail. This provides the pull-up voltage for the DEV_OFF_N signal. | | 2 | 2 | $18N3540 | ✅ | Connected to DEV_OFF_N signal (U42 pin 28). This pull-up resistor keeps the active-low device off signal high (inactive) by default, ensuring the LAN controller remains enabled. | </details> <details> <summary>U7 - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | UART2_RXD | ✅ | B2 pin connected to UART2_RXD net, which goes to connector JP1 pin 19. This is the 3.3V side receive data line for UART2. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground net. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin connected to +V1P8S (1.8V supply) with proper decoupling capacitor C350. | | 4 | A2 | SIO_UART2_RXD | ✅ | A2 pin connected to SIO_UART2_RXD from the SOC. This is the 1.8V side receive data line for UART2. | | 5 | A1 | SIO_UART2_TXD | ✅ | A1 pin connected to SIO_UART2_TXD from the SOC. This is the 1.8V side transmit data line for UART2. | | 6 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin connected to PMC_PLTRST_R_V1P8, which controls the translator enable based on platform reset. | | 7 | VCCB | +3VSB | ✅ | VCCB pin connected to +3VSB (3.3V standby supply) with proper decoupling capacitor C351. | | 8 | B1 | UART2_TXD | ✅ | B1 pin connected to UART2_TXD net, which goes to connector JP1 pin 17. This is the 3.3V side transmit data line for UART2. | </details> <details> <summary>U15 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin connected to +V1P8S (1.8V supply) with proper decoupling capacitor C356. | | 2 | A1 | SIO_UART1_RTSB | ✅ | A1 pin connected to SIO_UART1_RTSB from the SOC. This is the 1.8V side RTS signal for UART1. | | 3 | A2 | SIO_UART1_CTSB | ✅ | A2 pin connected to SIO_UART1_CTSB from the SOC. This is the 1.8V side CTS signal for UART1. | | 4 | A3 | SIO_UART1_RXD | ✅ | A3 pin connected to SIO_UART1_RXD from the SOC. This is the 1.8V side receive data line for UART1. | | 5 | A4 | SIO_UART1_TXD | ✅ | A4 pin connected to SIO_UART1_TXD from the SOC. This is the 1.8V side transmit data line for UART1. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground net. | | 7 | B4 | UART1_TXD | ✅ | B4 pin connected to UART1_TXD net, which goes to connector JP1 pin 6. This is the 3.3V side transmit data line for UART1. | | 8 | B3 | UART1_RXD | ✅ | B3 pin connected to UART1_RXD net, which goes to connector JP1 pin 8. This is the 3.3V side receive data line for UART1. | | 9 | B2 | UART1_CTSB | ✅ | B2 pin connected to UART1_CTSB net, which goes to connector JP1 pin 10. This is the 3.3V side CTS signal for UART1. | | 10 | B1 | UART1_RTSB | ✅ | B1 pin connected to UART1_RTSB net, which goes to connector JP1 pin 12. This is the 3.3V side RTS signal for UART1. | | 11 | VCCB | +3VSB | ✅ | VCCB pin connected to +3VSB (3.3V standby supply) with proper decoupling capacitor C357. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin connected to PMC_PLTRST_R_V1P8, which controls the translator enable based on platform reset. | </details> <details> <summary>U14 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing the 1.8V reference voltage for the A-side of the level translator. | | 2 | A1 | SOC_SIO_SPI_CLK | ✅ | A1 is correctly connected to SOC_SIO_SPI_CLK, translating the 1.8V SPI clock signal to 3.3V on B1. | | 3 | A2 | SOC_SIO_SPI_MOSI | ✅ | A2 is correctly connected to SOC_SIO_SPI_MOSI, translating the 1.8V SPI MOSI signal to 3.3V on B2. | | 4 | A3 | SOC_SIO_SPI_MISO | ✅ | A3 is correctly connected to SOC_SIO_SPI_MISO, translating the 1.8V SPI MISO signal to 3.3V on B3. | | 5 | A4 | SOC_SIO_SPI_CS1 | ✅ | A4 is correctly connected to SOC_SIO_SPI_CS1, translating the 1.8V SPI chip select signal to 3.3V on B4. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SIO_SPI_CS1 | ✅ | B4 is correctly connected to SIO_SPI_CS1, providing the 3.3V translated chip select signal. | | 8 | B3 | SIO_SPI_MISO | ✅ | B3 is correctly connected to SIO_SPI_MISO, providing the 3.3V translated MISO signal. | | 9 | B2 | SIO_SPI_MOSI | ✅ | B2 is correctly connected to SIO_SPI_MOSI, providing the 3.3V translated MOSI signal. | | 10 | B1 | SIO_SPI_CLK | ✅ | B1 is correctly connected to SIO_SPI_CLK, providing the 3.3V translated clock signal. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing the 3.3V reference voltage for the B-side of the level translator. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform is out of reset. | </details> <details> <summary>U17 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing the reference voltage for the A-side I/O pins. | | 2 | A1 | I2S_MCLK | ✅ | A1 is correctly connected to I2S_MCLK, translating this 1.8V signal to 3.3V on B1. | | 3 | A2 | SOC_PWM1 | ✅ | A2 is correctly connected to SOC_PWM1, translating this 1.8V signal to 3.3V on B2. | | 4 | A3 | SOC_PWM0 | ✅ | A3 is correctly connected to SOC_PWM0, translating this 1.8V signal to 3.3V on B3. | | 5 | A4 | | ✅ | A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw. | | 7 | B4 | GND | ✅ | A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 8 | B3 | PWM0 | ✅ | B3 is correctly connected to PWM0, translating this 3.3V signal to 1.8V on A3. | | 9 | B2 | PWM1 | ✅ | B2 is correctly connected to PWM1, translating this 3.3V signal to 1.8V on A2. | | 10 | B1 | I2SMCLK_GPIO | ✅ | B1 is correctly connected to I2SMCLK_GPIO, translating this 3.3V signal to 1.8V on A1. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing the reference voltage for the B-side I/O pins. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform reset is deasserted. | </details> <details> <summary>U10 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the reference voltage for the A-side I/O pins. | | 2 | A1 | SOC_GPIO_S5_2 | ✅ | A1 is correctly connected to SOC_GPIO_S5_2, translating this 1.8V signal to 3.3V on B1. | | 3 | A2 | SOC_GPIO_S5_1 | ✅ | A2 is correctly connected to SOC_GPIO_S5_1, translating this 1.8V signal to 3.3V on B2. | | 4 | A3 | SOC_GPIO_S5_0 | ✅ | A3 is correctly connected to SOC_GPIO_S5_0, translating this 1.8V signal to 3.3V on B3. | | 5 | A4 | | ✅ | A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw. | | 7 | B4 | GND | ✅ | A4 is floating while B4 is connected to GND. This is not the recommended configuration for an unused channel in a bidirectional level translator and may cause unpredictable behavior or increased current draw. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 8 | B3 | GPIO_S5_0 | ✅ | B3 is correctly connected to GPIO_S5_0, translating this 3.3V signal to 1.8V on A3. | | 9 | B2 | GPIO_S5_1 | ✅ | B2 is correctly connected to GPIO_S5_1, translating this 3.3V signal to 1.8V on A2. | | 10 | B1 | GPIO_S5_2 | ✅ | B1 is correctly connected to GPIO_S5_2, translating this 3.3V signal to 1.8V on A1. | | 11 | VCCB | +PS_3VSB | ✅ | VCCB is correctly connected to +PS_3VSB, providing the reference voltage for the B-side I/O pins. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform reset is deasserted. | </details> <details> <summary>U16 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA is correctly connected to +V1P8S, providing the reference voltage for the A-side I/O pins. | | 2 | A1 | I2S_DATIN_R | ✅ | A1 is correctly connected to I2S_DATIN_R, translating this 1.8V signal to 3.3V on B1. | | 3 | A2 | I2S_DATOUT_R | ✅ | A2 is correctly connected to I2S_DATOUT_R, translating this 1.8V signal to 3.3V on B2. | | 4 | A3 | I2S_FRM_R | ✅ | A3 is correctly connected to I2S_FRM_R, translating this 1.8V signal to 3.3V on B3. | | 5 | A4 | I2S_CLK_R | ✅ | A4 is correctly connected to I2S_CLK_R, translating this 1.8V signal to 3.3V on B4. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 7 | B4 | I2SCLK_GPIO | ✅ | B4 is correctly connected to I2SCLK_GPIO, translating this 3.3V signal to 1.8V on A4. | | 8 | B3 | I2SFRM_GPIO | ✅ | B3 is correctly connected to I2SFRM_GPIO, translating this 3.3V signal to 1.8V on A3. | | 9 | B2 | I2SDO_GPIO | ✅ | B2 is correctly connected to I2SDO_GPIO, translating this 3.3V signal to 1.8V on A2. | | 10 | B1 | I2SDI_GPIO | ✅ | B1 is correctly connected to I2SDI_GPIO, translating this 3.3V signal to 1.8V on A1. | | 11 | VCCB | +3VSB | ✅ | VCCB is correctly connected to +3VSB, providing the reference voltage for the B-side I/O pins. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE is correctly connected to PMC_PLTRST_R_V1P8, enabling the level translator when the platform reset is deasserted. | </details> <details> <summary>U3 - W25Q64BVSSIG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/653/W25Q64BV.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/W25Q64BVSSIG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPI_CS0 | ✅ | CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pullup to +V_SPI, translating through U18 to the SOC and available on programming header J1. | | 2 | SO/IO1 | SPI_MISO | ✅ | SO/IO1 (Serial Data Output) is correctly connected to SPI_MISO, translating through U18 to the SOC and available on programming header J1. | | 3 | WP#/IO2 | SPI_WP | ✅ | WP#/IO2 (Write Protect) is correctly connected to SPI_WP with a 10K pullup to +V_SPI, disabling hardware write protection and allowing software control. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 5 | SI/IO0 | SPI_MOSI | ✅ | SI/IO0 (Serial Data Input) is correctly connected to SPI_MOSI, translating through U18 to the SOC and available on programming header J1. | | 6 | SCK | SPI_CLK | ✅ | SCK (Serial Clock) is correctly connected to SPI_CLK, translating through U18 to the SOC and available on programming header J1. | | 7 | HOLD#/IO3 | SPI_HOLD | ✅ | HOLD#/IO3 (Hold Input) is correctly connected to SPI_HOLD with a 10K pullup to +V_SPI, disabling the hold function during normal operation. | | 8 | VCC | +V_SPI | ✅ | VCC is correctly connected to +V_SPI which is supplied at 3.3V through D8 from +3VSB (via R152) or DDP_VCC, with appropriate decoupling capacitors. | </details> <details> <summary>D8 - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | DDP_VCC | ✅ | Anode A1 is correctly connected to DDP_VCC from the DediProg programming header, providing one of two power sources for the SPI flash. | | A2 | A2 | $20N2079 | ✅ | Anode A2 is correctly connected through R152 to +3VSB, providing board power to the SPI flash when the programmer is not connected. | | C | C | +V_SPI | ✅ | Common cathode C is correctly connected to +V_SPI, OR-ing the two power sources (DDP_VCC and +3VSB) to supply the SPI flash. | </details> <details> <summary>R818 - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | This 0-ohm jumper is correctly marked DNI (Do Not Install) as it would connect +V1P8A (1.8V) to the SPI flash power supply, which is below the minimum voltage specification for the W25Q64BVSSIG. | | 2 | 2 | +V1P8A | ✅ | This 0-ohm jumper is correctly marked DNI (Do Not Install) as it would connect +V1P8A (1.8V) to the SPI flash power supply, which is below the minimum voltage specification for the W25Q64BVSSIG. | </details> <details> <summary>R152 - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | This 0-ohm jumper is correctly populated to connect +3VSB (3.3V) to the SPI flash power supply, which is within the voltage specification for the W25Q64BVSSIG. | | 2 | 2 | +3VSB | ✅ | This 0-ohm jumper is correctly populated to connect +3VSB (3.3V) to the SPI flash power supply, which is within the voltage specification for the W25Q64BVSSIG. | </details> <details> <summary>J1 - 258-0004612 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0004612) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDP_VCC | ✅ | Pin 1 (DDP_VCC) correctly provides power from the DediProg programmer to the SPI flash through D8. | | 2 | 2 | GND | ✅ | Pin 2 (GND) correctly provides ground reference for the DediProg programmer interface. | | 3 | 3 | SPI_CS0 | ✅ | Pin 3 (SPI_CS0) correctly provides chip select access for programming the SPI flash. | | 4 | 4 | SPI_CLK | ✅ | Pin 4 (SPI_CLK) correctly provides clock access for programming the SPI flash. | | 5 | 5 | SPI_MISO | ✅ | Pin 5 (SPI_MISO) correctly provides data output access for reading from the SPI flash during programming. | | 6 | 6 | SPI_MOSI | ✅ | Pin 6 (SPI_MOSI) correctly provides data input access for writing to the SPI flash during programming. | | 7 | 7 | | ✅ | Pin 7 has no connection shown in the schematic, which is acceptable as this pin may be reserved or unused in the DediProg interface. | | 8 | 8 | DDP_IO3L | ✅ | Pin 8 (DDP_IO3L) correctly connects to the level translator output enable, allowing the DediProg to control bus isolation during programming. | </details> <details> <summary>U40 - PCA9306DCUT ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fpca9306) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/PCA9306DCUT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | SDA2 | GPIO_I2C_SDA | ❌ | <details><summary>SDA2 and SCL2 pins are connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to connector JP1. No pullup resistors are present on these nets on this board. The PCA9306 datasheet requires pullup resistors on open-drain I/O ports for proper operation. While pullup resistors could theoretically be provided on a remote board, best practice for I2C interfaces is to provide them on the host board to ensure reliable operation. Pullup resistors should be added from these nets to +3VSB.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,77.42,31.26,84.92" aspect-ratio="1.29" } <ul><li>Pin 5 connects to GPIO_I2C_SDA and pin 6 connects to GPIO_I2C_SCL (from schematic)</li><li>Pins 5 and 6 are SDA2 and SCL2, the serial data and clock on the high-voltage side (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</li><li>GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 connector pins 15 and 13 respectively (from schematic)</li><li>Pin 7 (VREF2) connects to net $20N1576, which is pulled to +3VSB through R812 (200K), establishing VDPU as +3VSB (from schematic)</li><li>Open-drain I/O ports require external pullup resistors to respective supply voltages, with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</li><li>No pullup resistors are visible on GPIO_I2C_SDA or GPIO_I2C_SCL on this schematic page (from schematic)</li><li>The low-voltage side I2C signals (I2C5_SCL and I2C5_SDA on pins 3 and 4) have pullup resistors R267 and R266 (both 10K) to +V1P8S (from schematic)</li><li>Typical application circuits show pullup resistors RPU on both the low-voltage and high-voltage sides (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17">PCA9306DCUT</a>, page 17)</li><li>The asymmetry between the low-voltage side (which has pullups) and high-voltage side (which lacks pullups) suggests a design oversight (reasoning)</li><li>While it's theoretically possible to provide pullups on a remote board connected to JP1, this creates a dependency and potential failure mode if the remote board doesn't provide them (reasoning)</li><li>Best practice for I2C interfaces exposed through connectors is to provide pullup resistors on the host board to ensure reliable operation regardless of what's connected (reasoning)</li><li>Pullup resistors should be added from GPIO_I2C_SCL to +3VSB and from GPIO_I2C_SDA to +3VSB, with values chosen based on bus capacitance and operating frequency per I2C specification (reasoning)</li></ul></details> | | 6 | SCL2 | GPIO_I2C_SCL | ❌ | <details><summary>SDA2 and SCL2 pins are connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to connector JP1. No pullup resistors are present on these nets on this board. The PCA9306 datasheet requires pullup resistors on open-drain I/O ports for proper operation. While pullup resistors could theoretically be provided on a remote board, best practice for I2C interfaces is to provide them on the host board to ensure reliable operation. Pullup resistors should be added from these nets to +3VSB.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.33" aspect-ratio="1.29" } <ul><li>Pin 5 connects to GPIO_I2C_SDA and pin 6 connects to GPIO_I2C_SCL (from schematic)</li><li>Pins 5 and 6 are SDA2 and SCL2, the serial data and clock on the high-voltage side (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4">PCA9306DCUT</a>, page 4)</li><li>GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 connector pins 15 and 13 respectively (from schematic)</li><li>Pin 7 (VREF2) connects to net $20N1576, which is pulled to +3VSB through R812 (200K), establishing VDPU as +3VSB (from schematic)</li><li>Open-drain I/O ports require external pullup resistors to respective supply voltages, with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10">PCA9306DCUT</a>, page 10)</li><li>No pullup resistors are visible on GPIO_I2C_SDA or GPIO_I2C_SCL on this schematic page (from schematic)</li><li>The low-voltage side I2C signals (I2C5_SCL and I2C5_SDA on pins 3 and 4) have pullup resistors R267 and R266 (both 10K) to +V1P8S (from schematic)</li><li>Typical application circuits show pullup resistors RPU on both the low-voltage and high-voltage sides (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17">PCA9306DCUT</a>, page 17)</li><li>The asymmetry between the low-voltage side (which has pullups) and high-voltage side (which lacks pullups) suggests a design oversight (reasoning)</li><li>While it's theoretically possible to provide pullups on a remote board connected to JP1, this creates a dependency and potential failure mode if the remote board doesn't provide them (reasoning)</li><li>Best practice for I2C interfaces exposed through connectors is to provide pullup resistors on the host board to ensure reliable operation regardless of what's connected (reasoning)</li><li>Pullup resistors should be added from GPIO_I2C_SCL to +3VSB and from GPIO_I2C_SDA to +3VSB, with values chosen based on bus capacitance and operating frequency per I2C specification (reasoning)</li></ul></details> | | 1 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 2 | VREF1 | +V1P8S | ✅ | VREF1 pin is correctly connected to the 1.8V supply rail (+V1P8S), providing the low-voltage side reference. | | 3 | SCL1 | I2C5_SCL | ✅ | SCL1 pin is correctly connected to the low-voltage I2C clock line (I2C5_SCL) with proper pullup resistor. | | 4 | SDA1 | I2C5_SDA | ✅ | SDA1 pin is correctly connected to the low-voltage I2C data line (I2C5_SDA) with proper pullup resistor. | | 7 | VREF2 | $20N1576 | ✅ | VREF2 pin is correctly connected through a 200K resistor (R812) to the 3.3V standby supply (+3VSB), establishing the proper reference voltage for the high-voltage side. | | 8 | EN | $20N1576 | ✅ | EN pin is correctly shorted to VREF2 and pulled up through the 200K resistor (R812) to +3VSB, enabling the level translator. | </details> <details> <summary>R147 - 100K ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Pin 1 is correctly connected to +V1P8A, providing the pull-up voltage for the OE control signal. | | 2 | 2 | DDP_IO3L | ✅ | Pin 2 is correctly connected to DDP_IO3L, pulling it HIGH to enable U18 during normal operation while allowing DediProg override. | </details> <details> <summary>U18 - NTB0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTB0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A (1.8V) with appropriate decoupling capacitor C165 nearby. | | 2 | A1 | SOC_SPI_MOSI-R | ✅ | A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins. | | 3 | A2 | SOC_SPI_CLK-R | ✅ | A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins. | | 4 | A3 | SOC_SPI_MISO-R | ✅ | A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins. | | 5 | A4 | SOC_SPI_CS0B-R | ✅ | A-side pins (A1-A4) are correctly connected to SOC SPI signals with proper channel mapping to corresponding B-side pins. | | 6 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 7 | B4 | SPI_CS0 | ✅ | B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins. | | 8 | B3 | SPI_MISO | ✅ | B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins. | | 9 | B2 | SPI_CLK | ✅ | B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins. | | 10 | B1 | SPI_MOSI | ✅ | B-side pins (B1-B4) are correctly connected to SPI flash signals with proper channel mapping to corresponding A-side pins. | | 11 | VCCB | +V_SPI | ✅ | VCCB is correctly connected to +V_SPI with appropriate decoupling capacitors C383 and C160 nearby. | | 12 | OE | DDP_IO3L | ✅ | OE pin is connected to DDP_IO3L with 100K pullup to +V1P8A, enabling DediProg control of the translator. Connection is correct for typical use, though there is a potential concern if DDP_IO3L is driven above VCCA+0.5V. | </details> <details> <summary>J5 - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Pin 1 connects to FP_PWRBTN, allowing a jumper to be installed to simulate a power button press. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the jumper. | </details> <details> <summary>SW1 - 3770-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3770-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Pin 1 connects to FP_PWRBTN, which is the power button signal line. When the button is pressed, this pin is shorted to pin 2 (GND), pulling the signal low. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground return path when the button is pressed. | | 3 | GND1 | GND_EARTH | ✅ | Pins 3 (GND1) and 4 (GND2) connect to GND_EARTH, which is the chassis ground. These are mechanical ground connections for the switch housing. | | 4 | GND2 | GND_EARTH | ✅ | Pins 3 (GND1) and 4 (GND2) connect to GND_EARTH, which is the chassis ground. These are mechanical ground connections for the switch housing. | </details> <details> <summary>D9 - DIODE_TVS_5V_84W_XFDFN ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N connects to GND, providing the ground reference for the bidirectional TVS diode. | | P | P | FP_PWRBTN | ✅ | Pin P connects to FP_PWRBTN, providing ESD protection for the power button signal line. | </details> <details> <summary>Q105 - FDN327N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/FDN327N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | GPIO_LED_CONTROL | ✅ | Drain is correctly connected to GPIO_LED_CONTROL net, which connects to the LED anode through current-limiting resistor R746 from +VCC. This forms a low-side switch configuration with inverted logic. | | G | GATE | GPIO_D2_LED_CTRL | ✅ | Gate is correctly connected to GPIO_D2_LED_CTRL with a 10kΩ pull-down resistor (R706) to ensure the MOSFET is off when the GPIO is not actively driven. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET in a low-side switch application. | </details> <details> <summary>D2 - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GPIO_LED_CONTROL | ✅ | Anode is correctly connected to GPIO_LED_CONTROL net, which is pulled up through R746 (470Ω) from +VCC and can be pulled low by MOSFET Q105. | | C | CATHODE | GND | ✅ | Cathode is correctly connected to GND, providing the return path for LED current and proper forward-bias orientation. | </details> <details> <summary>D1 - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | +PS_5VSB | ✅ | Anode is connected to +PS_5VSB (5V standby supply), providing power to the LED. This is correct for a power indicator LED. | | C | CATHODE | PWR_LEDR | ✅ | Cathode is connected to PWR_LEDR net, which connects through current limiting resistor R148 (470Ω) to GND. This provides proper current limiting for the LED. | </details> <details> <summary>R132 - 110-0004465 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004465) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RC_ENB | ✅ | Connected to RC_ENB, forming an RC filter with C338 to provide a filtered version of the DC input. | | 2 | 2 | DC_IN_1 | ✅ | Connected to DC_IN_1 to provide the input for the RC filter network. | </details> <details> <summary>L12 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Connected to internal net $22N1502 in parallel with L13 for increased current handling. | | 2 | 2 | DC_IN_1 | ✅ | Connected to DC_IN_1 in parallel with L13 for EMI filtering with higher current capability. | </details> <details> <summary>L13 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Connected to internal net $22N1502, which feeds the power distribution and protection circuits. | | 2 | 2 | DC_IN_1 | ✅ | Connected to DC_IN_1 from the power jack for EMI filtering of the input power. | </details> <details> <summary>J9 - RAPC712 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/414/RAPC712_cd.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/RAPC712) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DC_IN_1 | ✅ | Center pin correctly connected to DC_IN_1, the main 5V DC input to the system. | | 2 | 2 | GND | ✅ | Sleeve pin correctly connected to GND for ground return path. | | 3 | 3 | GND | ✅ | Switch contact connected to GND, which is acceptable if plug detection functionality is not required. | </details> <details> <summary>D13 - 4.3V Zener ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4620-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode connected to GND. The zener operates in reverse breakdown mode to clamp $22N2300 to 4.3V above ground, establishing the voltage reference for the overvoltage protection circuit. | | C | CATHODE | $22N2300 | ✅ | Cathode connected to $22N2300, which drives the gate of Q106 (BSS84 P-channel MOSFET). The zener clamps this node to 4.3V above ground, setting the reference voltage for the overvoltage protection threshold. | </details> <details> <summary>U36 - IRF9321 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.umw-ic.com/static/pdf/b379d167af492bcd72ba51c793d83236.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/IRF9321) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | $22N1502 | ✅ | Source pins connected to $22N1502, which is the filtered DC input through ferrite beads L13 and L12 from DC_IN_1. This is the input side of the overvoltage protection switch. | | 2 | S2 | $22N1502 | ✅ | Source pins connected to $22N1502, which is the filtered DC input through ferrite beads L13 and L12 from DC_IN_1. This is the input side of the overvoltage protection switch. | | 3 | S3 | $22N1502 | ✅ | Source pins connected to $22N1502, which is the filtered DC input through ferrite beads L13 and L12 from DC_IN_1. This is the input side of the overvoltage protection switch. | | 4 | G | DC_GATE_ENB | ✅ | Gate pin connected to DC_GATE_ENB, which is controlled by Q106 and pulled down by R309. This controls the on/off state of U36 based on input voltage. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins connected to +PS_5VSB, which is the 5V standby output rail. This is the output side of the overvoltage protection switch. | </details> <details> <summary>Q106 - BSS84 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/bss84-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BSS84) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | D | DC_GATE_ENB | ✅ | Drain pin connected to DC_GATE_ENB, which controls the gate of U36. When Q106 turns on, it pulls DC_GATE_ENB high to turn off U36. | | G | G | $22N2300 | ✅ | Gate pin connected to $22N2300, which is the voltage-sensed signal from the R855/D13 divider network. This controls Q106 based on input voltage. | | S | S | $22N1502 | ✅ | Source pin connected to $22N1502, which is the same net as the source of U36. This provides the reference voltage for Q106's gate control. | </details> <details> <summary>Q14 - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | 5VSB_LSENB | ✅ | Drain pin is correctly connected to 5VSB_LSENB, which is pulled up to +10V by R324. Q14 acts as a low-side switch to pull this signal to ground when enabled. | | G | GATE | 5VSB_GATE | ✅ | Gate pin is correctly connected to 5VSB_GATE, which is driven by 5VSB_CTRL through R323 (10K) with C340 (1uF) providing filtering. | | S | SOURCE | GND | ✅ | Source pin is correctly connected to GND, which is the proper configuration for a low-side switch. | </details> <details> <summary>Q103 - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +5VSB | ✅ | Source pins S1, S2, S3 are correctly connected to the +5VSB output rail. All three source pins are tied together as expected for the PowerPAK 1212-8 package. | | 2 | S2 | +5VSB | ✅ | Source pins S1, S2, S3 are correctly connected to the +5VSB output rail. All three source pins are tied together as expected for the PowerPAK 1212-8 package. | | 3 | S3 | +5VSB | ✅ | Source pins S1, S2, S3 are correctly connected to the +5VSB output rail. All three source pins are tied together as expected for the PowerPAK 1212-8 package. | | 4 | G | 5VSB_LSENB | ✅ | Gate pin is correctly connected to 5VSB_LSENB control signal. This signal is pulled to +10V when Q14 is OFF (enabling Q103) and pulled to GND when Q14 is ON (disabling Q103). | | 5 | D1 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to the +PS_5VSB input power rail. All four drain pins are tied together as expected for the PowerPAK 1212-8 package. | </details> <details> <summary>Q4 - MMBT3904 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/MMBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B | BASE | S5_ENBL | ✅ | Base is correctly connected to S5_ENBL control signal through R133 (10K pull-up to +V1P8A). The base current of approximately 110μA when S5_ENBL is high provides adequate drive for the transistor. | | C | COLLECTOR | +3VSB_EN_L | ✅ | Collector is correctly connected to +3VSB_EN_L with pull-up resistor R321 (1K) to +PS_5VSB. This inverts the S5_ENBL signal to control Q11. | | E | EMITTER | GND | ✅ | Emitter is correctly connected to GND, which is the proper configuration for an NPN transistor in common-emitter configuration. | </details> <details> <summary>Q104 - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +3VSB | ✅ | Source pins S1, S2, S3 are correctly connected to +3VSB output rail. Multiple source pins are paralleled for lower resistance and better thermal performance. | | 2 | S2 | +3VSB | ✅ | Source pins S1, S2, S3 are correctly connected to +3VSB output rail. Multiple source pins are paralleled for lower resistance and better thermal performance. | | 3 | S3 | +3VSB | ✅ | Source pins S1, S2, S3 are correctly connected to +3VSB output rail. Multiple source pins are paralleled for lower resistance and better thermal performance. | | 4 | G | +3VSB_EN | ✅ | Gate pin is correctly connected to +3VSB_EN control signal. The gate drive voltage of approximately 6.7V (10V drive minus 3.3V source) is adequate to fully enhance the MOSFET, though not optimal for minimum RDS(on). | | 5 | D1 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance. | | 6 | D2 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance. | | 7 | D3 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance. | | 8 | D4 | +PS_3VSB | ✅ | Drain pins D1, D2, D3, D4 are correctly connected to +PS_3VSB input power rail. Multiple drain pins are paralleled for lower resistance and better thermal performance. | </details> <details> <summary>Q11 - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB_EN | ✅ | Drain is correctly connected to +3VSB_EN, which is the gate control signal for Q104. Q11 acts as a pull-down switch to disable Q104 when activated. | | G | GATE | +3VSB_EN_L | ✅ | Gate is correctly connected to +3VSB_EN_L control signal. This signal is driven by Q4 collector and controls when Q11 pulls down the gate of Q104. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary>U13 - NB670 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NB670) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN | PS5VSB_VIN | ✅ | VIN pin correctly connected to PS5VSB_VIN input supply with appropriate input capacitors for decoupling. | | 2 | PGND | GND | ✅ | PGND pin correctly connected to ground plane. | | 3 | N/C | | ✅ | N/C pin correctly left unconnected as specified in datasheet. | | 4 | PG | +PS_3VSB_PG | ✅ | PG pin correctly configured as open-drain output with 100K pull-up resistor to PS3_VCC. | | 5 | CLK | $22N1411 | ✅ | CLK pin connected to charge pump circuit through capacitors C72 and C283. | | 6 | LDO | PS3_LDO | ✅ | LDO pin correctly connected with 10uF decoupling capacitor, exceeding minimum 4.7uF requirement. | | 7 | VOUT | +PS_3VSB | ✅ | VOUT pin correctly connected to output voltage with multiple output capacitors and inductor. | | 8 | SW1 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306. | | 9 | SW2 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306. | | 15 | SW3 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306. | | 16 | SW4 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to PS3VSB_PHASE switching node, which connects to inductor L3 and bootstrap capacitor C306. | | 10 | BST | PS3_BST | ✅ | BST pin connected to PS3_BST, which connects through series 4.7Ω resistor R291 to bootstrap capacitor C306. The series resistor R291 should not be present in the bootstrap circuit. | | 11 | VCC | PS3_VCC | ✅ | VCC pin correctly connected with 1uF decoupling capacitor meeting datasheet minimum requirement. | | 12 | ENLDO | | ✅ | ENLDO pin correctly left floating as it is internally pulled high to enable the LDO. | | 13 | EN | PS3_EN | ✅ | EN pin connected with 499K pull-up resistor to input supply. Missing recommended 10nF noise filtering capacitor (C85 is wrong value and DNI). | | 14 | AGND | GND | ✅ | AGND pin correctly connected to ground plane. | </details> <details> <summary>R291 - 110-0004467 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3_BST | ✅ | R291 is a 4.7Ω series resistor incorrectly placed in the bootstrap circuit between BST pin and bootstrap capacitor. This resistor should not be present as it limits bootstrap capacitor charging and deviates from datasheet recommendations. | | 2 | 2 | $22N1498 | ✅ | R291 is a 4.7Ω series resistor incorrectly placed in the bootstrap circuit between BST pin and bootstrap capacitor. This resistor should not be present as it limits bootstrap capacitor charging and deviates from datasheet recommendations. | </details> <details> <summary>L3 - 125-0004501 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/125-0004501) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | Inductor input correctly connected to switch node PS3VSB_PHASE from U13. | | 2 | 2 | +PS_3VSB | ✅ | Inductor output correctly connected to +PS_3VSB output rail with multiple output capacitors. | </details> <details> <summary>U35 - NCT3012S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NCT3012S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DeepS5_Sel | S5_SEL | ✅ | DeepS5_Sel configuration input connected to S5_SEL with pull-up resistor to +PS_5VSB. | | 2 | VSB | +PS_5VSB | ✅ | VSB power supply input correctly connected to +PS_5VSB. | | 3 | PS_IN# | PB_RES | ✅ | PS_IN# power button input connected to PB_RES with series resistor to front panel button. | | 4 | SLP_S5# | SLP_S4_L | ✅ | SLP_S5# sleep state input connected to SLP_S4_L, which may be a naming inconsistency. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA I2C data line correctly connected to DDR_SMB_DATA. | | 6 | SCLK | DDR_SMB_CLK | ✅ | SCLK I2C clock line correctly connected to DDR_SMB_CLK. | | 7 | PS_OUT# | PS_OUT_L | ✅ | PS_OUT# power supply output control signal correctly connected to PS_OUT_L. | | 8 | SYS5VSB_OFF | 5VSB_CTRL | ✅ | SYS5VSB_OFF control output correctly connected to 5VSB_CTRL for EuP mode control. | | 9 | GND | GND | ✅ | GND pin correctly connected to ground. | </details> <details> <summary>Q13 - RXR035N03 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +5VSB | ✅ | Drain is correctly connected to +5VSB input power rail. This MOSFET acts as a high-side switch to generate the +VCC output rail. | | G | GATE | SYS_EN | ✅ | Gate is correctly connected to SYS_EN control signal. The gate is pulled up to +10V through R340 (100K) when enabled, providing adequate Vgs for full turn-on. | | S | SOURCE | +VCC | ✅ | Source is correctly connected to +VCC output rail. This is the switched output that provides power when SYS_EN is high. | </details> <details> <summary>Q6 - RXR035N03 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB | ✅ | Drain is correctly connected to the +3VSB input power rail (3.3V standby supply). This is the input side of the high-side load switch. | | G | GATE | SYS_EN | ✅ | Gate is correctly connected to the SYS_EN control signal with proper pull-up to +10V through R340 (100K). The +10V gate drive provides sufficient VGS (approximately 6.7V when conducting) for full enhancement. | | S | SOURCE | +VCC3 | ✅ | Source is correctly connected to the +VCC3 output rail. This is the output side of the high-side load switch, providing switched 3.3V power. | </details> <details> <summary>Q7 - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN_GATE | ✅ | Drain is connected to SYS_EN_GATE net, which controls the gate of Q12. This pin pulls the gate of Q12 low when Q7 is turned on. | | G | GATE | SLP_S3_L | ✅ | Gate is connected to SLP_S3_L control signal. This pin controls when Q7 turns on to pull down SYS_EN_GATE. | | S | SOURCE | GND | ✅ | Source is connected to GND. This is the correct connection for an N-channel MOSFET in a low-side switch configuration. | </details> <details> <summary>Q12 - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN | ✅ | Drain is connected to SYS_EN net, which controls the gate of Q6. This pin pulls the gate of Q6 low when Q12 is turned on. | | G | GATE | SYS_EN_GATE | ✅ | Gate is connected to SYS_EN_GATE net, which is controlled by Q7. This pin receives the inverted SLP_S3_L signal to control Q12. | | S | SOURCE | GND | ✅ | Source is connected to GND. This is the correct connection for an N-channel MOSFET in a low-side switch configuration. | </details> <details> <summary>Q10 - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | S5_ENBL | ✅ | Drain is correctly connected to S5_ENBL net, which is pulled up to +V1P8A through R133 (10K). When Q10 turns on, it pulls S5_ENBL low to control downstream circuitry. | | G | GATE | 5VSB_CTRL | ✅ | Gate is correctly connected to 5VSB_CTRL control signal from U35 pin 8. The gate voltage of approximately 5V when active provides adequate drive for the MOSFET. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary>D6 - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB_PG | ✅ | Part number mismatch: Circuit requires common cathode diode configuration for OR gate function, but BAT54A-S specifies common anode. COMPVALUE attribute shows BAV99-7-F-S-X (common cathode) which would be correct, creating ambiguity about actual part. | | 2 | 2 | +3VSB_EN | ✅ | Part number mismatch: Circuit requires common cathode diode configuration for OR gate function, but BAT54A-S specifies common anode. COMPVALUE attribute shows BAV99-7-F-S-X (common cathode) which would be correct, creating ambiguity about actual part. | | 3 | 3 | PMC_RSMRST | ✅ | Part number mismatch: Circuit requires common cathode diode configuration for OR gate function, but BAT54A-S specifies common anode. COMPVALUE attribute shows BAV99-7-F-S-X (common cathode) which would be correct, creating ambiguity about actual part. | </details> <details> <summary>Q2 - BAV99-7-F-S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | +PS_5VSB | ✅ | Anode 1 connected to +PS_5VSB, providing high-side clamp reference for AC-coupled CLK signal protection circuit. | | 2 | A2 | $22N1417 | ✅ | Anode 2 connected to $22N1417, which is biased to GND through C71, providing low-side clamp reference. | | 3 | C | $22N1419 | ✅ | Common cathode connected to $22N1419, which is AC-coupled to CLK signal from U13 through C72. | </details> <details> <summary>Q9 - BAV99-7-F-S-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | $22N1417 | ✅ | Anode 1 connected to $22N1417, shared with Q2 pin 2, providing low-side clamp reference. | | 2 | A2 | +10V | ✅ | Anode 2 connected to +10V, providing high-side clamp reference for AC-coupled CLK signal protection circuit. | | 3 | C | $22N1467 | ✅ | Common cathode connected to $22N1467, which is AC-coupled to CLK signal from U13 through C283. | </details> <details> <summary>FB11 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB, the main 5V standby power rail. FB11 is in parallel with FB1 to increase current handling capacity. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, the filtered input to buck converter U13. This completes the parallel configuration with FB1. | </details> <details> <summary>FB1 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB, the main 5V standby power rail. This is the source side of the ferrite bead providing input filtering to the buck converter. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, which is the filtered input to buck converter U13. This is the load side of the ferrite bead. | </details> <details> <summary>U25 - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin connected to VR_HOT_L net for thermal alert signaling. | | 2 | SDIO | $23N2429 | ✅ | SDIO pin connected to $23N2429 for I2C/SVID data communication. | | 3 | ALERT | $23N2431 | ✅ | ALERT pin connected to $23N2431 for system alert signaling. | | 4 | SCLK | $23N2430 | ✅ | SCLK pin connected to $23N2430 for I2C/SVID clock communication. | | 5 | GND | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) all correctly connected to AGND-VCORE for analog reference. | | 32 | GND1 | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) all correctly connected to AGND-VCORE for analog reference. | | 49 | GND_PAD | AGND-VCORE | ✅ | Analog ground pins (GND, GND1, GND_PAD) all correctly connected to AGND-VCORE for analog reference. | | 6 | VR_RDY | $23N3753 | ✅ | VR_RDY pin connected to $23N3753 for power good indication. | | 7 | VIN1 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 11 | VIN2 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 12 | VIN3 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 13 | VIN4 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 14 | VIN5 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 15 | VIN6 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 16 | VIN7 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 17 | VIN8 | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 50 | VIN_PAD | +5VSB_SW | ✅ | Input power supply pins (VIN1-8, VIN_PAD) all correctly connected to +5VSB_SW with adequate decoupling. | | 8 | BST | $23N3711 | ✅ | BST pin connected to bootstrap circuit through R154 and C50 for high-side gate driver supply. | | 9 | GH | | ✅ | GH (high-side gate driver output) appears to have no net connection in the provided data. | | 10 | SW1 | $23N3731 | ✅ | SW1 pin connected to $23N3731 as the return path for the bootstrap capacitor. | | 18 | SW2 | VCORE-SW | ✅ | Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output. | | 25 | SW3 | VCORE-SW | ✅ | Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output. | | 26 | SW4 | VCORE-SW | ✅ | Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output. | | 27 | SW5 | VCORE-SW | ✅ | Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output. | | 28 | SW6 | VCORE-SW | ✅ | Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output. | | 29 | SW7 | VCORE-SW | ✅ | Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output. | | 51 | SW_PAD | VCORE-SW | ✅ | Main switch node pins (SW2-7, SW_PAD) all correctly connected to VCORE-SW output. | | 19 | PGND1 | GND | ✅ | Power ground pins (PGND1-6) all correctly connected to GND for high-current return path. | | 20 | PGND2 | GND | ✅ | Power ground pins (PGND1-6) all correctly connected to GND for high-current return path. | | 21 | PGND3 | GND | ✅ | Power ground pins (PGND1-6) all correctly connected to GND for high-current return path. | | 22 | PGND4 | GND | ✅ | Power ground pins (PGND1-6) all correctly connected to GND for high-current return path. | | 23 | PGND5 | GND | ✅ | Power ground pins (PGND1-6) all correctly connected to GND for high-current return path. | | 24 | PGND6 | GND | ✅ | Power ground pins (PGND1-6) all correctly connected to GND for high-current return path. | | 30 | GL | | ✅ | GL (low-side gate driver output) appears to have no net connection in the provided data. | | 31 | VBOOT | $23N3477 | ✅ | VBOOT pin connected to $23N3477 for boot voltage configuration. | | 33 | VCCP | $23N3625 | ✅ | VCCP pin connected to $23N3625, supplied from +5VSB through R845 (1.00Ω) and decoupled by C48 (4.7uF). | | 34 | TSENSE | $23N3665 | ✅ | TSENSE pin connected to $23N3665 for temperature monitoring through thermistor network. | | 35 | IMAX | $23N3681 | ✅ | IMAX pin connected to $23N3681 with R105 (44.2kΩ) to AGND-VCORE for maximum current limit setting. | | 36 | IOUT | $23N3683 | ✅ | IOUT pin connected to $23N3683 with R146 (16.5kΩ) to AGND-VCORE and C47 (470pF) for output current monitoring. | | 37 | ILIM | VCORE-ILIM | ✅ | ILIM pin connected to VCORE-ILIM for current limit control. | | 38 | CSCOMP | VCORE-CSCOMP | ✅ | CSCOMP pin connected to VCORE-CSCOMP for current loop compensation. | | 39 | CSSUM | VCORE-CSSUM | ✅ | CSSUM pin connected to VCORE-CSSUM for summed current sense signal. | | 40 | CSREF | VCORE-CSREF | ✅ | CSREF pin connected to VCORE-CSREF for current sense reference voltage. | | 41 | FREQ | $23N2930 | ✅ | FREQ pin connected to $23N2930 with R93 (18.7kΩ) to AGND-VCORE for switching frequency setting. | | 42 | COMP | VCORE-COMP | ✅ | COMP pin connected to VCORE-COMP for voltage loop compensation. | | 43 | FB | VCORE-FB | ✅ | FB pin connected to VCORE-FB for output voltage feedback. | | 44 | DIFFOUT | VCORE-DIFFOUT | ✅ | DIFFOUT pin connected to VCORE-DIFFOUT for differential amplifier output. | | 45 | VSN | VR-VCORE-VSN | ✅ | VSN pin connected to VR-VCORE-VSN for remote negative sense. | | 46 | VSP | VR-VCORE-VSP | ✅ | VSP pin connected to VR-VCORE-VSP for remote positive sense. | | 47 | VCC | $23N3860 | ✅ | VCC pin connected to $23N3860, supplied from +5VSB through R166 (2.20Ω) and decoupled by C24 (1.0uF) to AGND-VCORE. | | 48 | EN | $23N5607 | ✅ | EN pin connected to $23N5607 for enable control with pull-up and filtering. | </details> <details> <summary>C48 - 2232-0016 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2232-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | 2 | GND | ❌ | <details><summary>Pin 2 connects to GND but should connect to AGND-VCORE for proper analog supply decoupling. This is inconsistent with C24 (VCC decoupling) which correctly connects to AGND-VCORE.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="60.11,54.19,67.61,61.69" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to net GND (from schematic)</li><li>U25 pin 33 (VCCP) is likely an analog power supply pin based on typical power controller architectures (reasoning)</li><li>U25 analog ground pins (5, 32, 49) all connect to AGND-VCORE (from schematic)</li><li>C24, which decouples U25 pin 47 (VCC), connects to AGND-VCORE (from schematic)</li><li>For proper noise isolation, analog supply decoupling capacitors should reference the same ground as the IC's analog ground pins (reasoning)</li><li>C48 pin 2 should connect to AGND-VCORE instead of GND to maintain consistent ground referencing for analog supplies (reasoning)</li><li>Connecting to GND instead of AGND-VCORE may introduce switching noise into the analog supply and degrade performance (reasoning)</li><li>Recommendation: Change C48 pin 2 connection from GND to AGND-VCORE (reasoning)</li></ul></details> | | 1 | 1 | $23N3625 | ✅ | Pin 1 correctly connects to VCCP supply net $23N3625. | </details> <details> <summary>L18 - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Pin 1 connects to the switching node VCORE-SW, which is the output of the multiphase buck converter switching stage. This is the correct connection for the input side of the output filter inductor. | | 2 | 2 | +VCORE | ✅ | Pin 2 connects to the output voltage rail +VCORE. This is the correct connection for the output side of the buck converter inductor, providing filtered DC output voltage. | </details> <details> <summary>L8 - 3120-0183 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3120-0183) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of an input filter inductor. | | 2 | 2 | +5VSB_SW | ✅ | Pin 2 connects to +5VSB_SW, which feeds the VIN pins of the buck converter IC U25. This is the correct connection for the output side of an input filter inductor. | </details> <details> <summary>R88 - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0032) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2824 | ✅ | Connected to intermediate node in compensation network between COMP and FB pins. Part of Type III compensation network for voltage loop. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node, which connects to U25 pin 43 (FB). Completes the compensation network path. | </details> <details> <summary>R89 - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node. Forms part of differential feedback path to DIFFOUT pin. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT, which connects to U25 pin 44 (DIFFOUT). Completes differential feedback path. | </details> <details> <summary>R90 - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2818 | ✅ | Connected to intermediate node in differential feedback filter network with C36. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT at U25 pin 44. Completes RC filter in differential feedback path. | </details> <details> <summary>C35 - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP at U25 pin 42 (COMP). Part of Type III compensation network. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node. Creates high-frequency pole in compensation network. | </details> <details> <summary>C36 - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB feedback node. Part of RC filter in differential feedback path. | | 2 | 2 | $23N2818 | ✅ | Connected to intermediate node in differential feedback filter with R90. | </details> <details> <summary>C37 - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP at U25 pin 42. Part of Type III compensation network. | | 2 | 2 | $23N2824 | ✅ | Connected to intermediate node in compensation network with R88. Creates pole-zero pair. | </details> <details> <summary>R63 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_SENSE | ✅ | Connected to VCC_SENSE remote sense input. Allows remote voltage sensing of the positive output. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP at U25 pin 46. The 0-ohm resistor directly connects remote sense to the positive sense input. | </details> <details> <summary>R64 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VSS_SENSE | ✅ | Connected to VSS_SENSE remote sense input. Allows remote sensing of the negative/ground connection at the load. | | 2 | 2 | $23N2860 | ✅ | Connected to intermediate node in negative sense path. The 0-ohm resistor connects remote sense to the network feeding VSN. | </details> <details> <summary>R65 - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | Connected to intermediate node in negative sense path. Provides isolation between remote sense network and VSN input. | | 2 | 2 | VR-VCORE-VSN | ✅ | Connected to VR-VCORE-VSN at U25 pin 45. Provides isolation and filtering for the negative sense input. | </details> <details> <summary>R91 - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Provides pull-down path for negative sense network when remote sensing is not used. | | 2 | 2 | $23N2860 | ✅ | Connected to intermediate node in negative sense path. Pulls the node to ground when remote sensing is not connected. | </details> <details> <summary>R92 - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0025) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output. Provides local sensing path from the regulator output to VSP. | | 2 | 2 | VR-VCORE-VSP | ✅ | Connected to VR-VCORE-VSP at U25 pin 46. Provides default connection to output voltage for local sensing. | </details> <details> <summary>C34 - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VCORE-VSP | ✅ | DNI capacitor that would filter the differential sense inputs VSP and VSN. Not installed, so electrically absent. | | 2 | 2 | VR-VCORE-VSN | ✅ | DNI capacitor that would filter the differential sense inputs VSP and VSN. Not installed, so electrically absent. | </details> <details> <summary>C38 - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2860 | ✅ | DNI capacitor that would filter the negative sense path. Not installed, so electrically absent. | | 2 | 2 | VR-VCORE-VSN | ✅ | DNI capacitor that would filter the negative sense path. Not installed, so electrically absent. | </details> <details> <summary>SP3 - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Connected to VCORE-SW switching node for DCR current sensing. | | 2 | 2 | $23N3209 | ✅ | Connected to $23N3209, which connects through R107 to VCORE-CSSUM for current sensing. | </details> <details> <summary>SP4 - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output for DCR current sensing reference. | | 2 | 2 | $23N3208 | ✅ | Connected to $23N3208, which connects through R108 to VCORE-CSREF for current sensing reference. | </details> <details> <summary>TH1 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP for temperature compensation in the current sensing network. | | 2 | 2 | $23N3115 | ✅ | Connected to junction node $23N3115, which connects through R106 to VCORE-CSSUM. | </details> <details> <summary>R78 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | 0-ohm jumper connecting U25 TSENSE pin to the thermistor-based temperature sensing network, allowing optional population or circuit modification. | | 2 | 2 | $23N3662 | ✅ | 0-ohm jumper connecting U25 TSENSE pin to the thermistor-based temperature sensing network, allowing optional population or circuit modification. | </details> <details> <summary>C46 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | 0.1uF filter capacitor on the TSENSE pin, providing high-frequency noise filtering for the temperature sensing input to analog ground. | | 2 | 2 | AGND-VCORE | ✅ | 0.1uF filter capacitor on the TSENSE pin, providing high-frequency noise filtering for the temperature sensing input to analog ground. | </details> <details> <summary>TH2 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Thermistor pin connected to the temperature sensing voltage divider node, which connects through R78 to U25 TSENSE pin. This forms the temperature-dependent part of the sensing circuit. | | 2 | 2 | GND | ✅ | Thermistor pin connected to ground, providing the reference for the temperature sensing voltage divider. | </details> <details> <summary>R131 - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0055) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | 14K resistor pin connected to the temperature sensing voltage divider node, in parallel with thermistor TH2. | | 2 | 2 | GND | ✅ | 14K resistor pin connected to ground, completing the voltage divider for temperature sensing. | </details> <details> <summary>R80 - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0329) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Series resistor (16.9Ω) on SVID data line between SVID_DATA-R and U25 SDIO pin. Provides signal integrity and damping for the SVID serial data interface. | | 2 | 2 | $23N2429 | ✅ | Series resistor (16.9Ω) on SVID data line between SVID_DATA-R and U25 SDIO pin. Provides signal integrity and damping for the SVID serial data interface. | </details> <details> <summary>R87 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0330) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_CLK-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required. | | 2 | 2 | SVID_CLK-R | ✅ | DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_CLK-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required. | </details> <details> <summary>R62 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Zero-ohm jumper on SVID alert line between SVID_ALERT-R and U25 ALERT pin. Allows for optional series resistance if needed for signal integrity. | | 2 | 2 | $23N2431 | ✅ | Zero-ohm jumper on SVID alert line between SVID_ALERT-R and U25 ALERT pin. Allows for optional series resistance if needed for signal integrity. | </details> <details> <summary>R85 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0330) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_DATA-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required. | | 2 | 2 | SVID_DATA-R | ✅ | DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_DATA-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required. | </details> <details> <summary>R86 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0330) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_ALERT-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required. | | 2 | 2 | SVID_ALERT-R | ✅ | DNI pull-up resistor (69.8Ω) that would connect +V1P0S to SVID_ALERT-R if installed. Not populated, indicating pull-ups are provided elsewhere or not required. | </details> <details> <summary>R81 - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0099) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Series resistor (20.0Ω) on SVID clock line between SVID_CLK-R and U25 SCLK pin. Provides signal integrity and damping for the SVID serial clock interface. | | 2 | 2 | $23N2430 | ✅ | Series resistor (20.0Ω) on SVID clock line between SVID_CLK-R and U25 SCLK pin. Provides signal integrity and damping for the SVID serial clock interface. | </details> <details> <summary>R849 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | R849 is a 0Ω jumper connecting +VCC to the enable pin (EN) of U25. With R851 (10K) also connected to GND, this creates a continuous current path drawing approximately 0.5mA (assuming +VCC = 5V), which is unnecessary. | | 2 | 2 | $23N5607 | ✅ | R849 is a 0Ω jumper connecting +VCC to the enable pin (EN) of U25. With R851 (10K) also connected to GND, this creates a continuous current path drawing approximately 0.5mA (assuming +VCC = 5V), which is unnecessary. | </details> <details> <summary>R851 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ✅ | R851 is a 10K pull-down resistor on the enable pin of U25. With R849 (0Ω) connecting +VCC to the same net, R851 draws unnecessary current without providing functional benefit in the current configuration. | | 2 | 2 | GND | ✅ | R851 is a 10K pull-down resistor on the enable pin of U25. With R849 (0Ω) connecting +VCC to the same net, R851 draws unnecessary current without providing functional benefit in the current configuration. | </details> <details> <summary>C50 - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0008) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3733 | ✅ | C50 is a 0.22μF bootstrap capacitor connected between the BST pin of U25 (through series resistor R154) and the SW1 pin. The capacitor value and voltage rating are appropriate for a bootstrap application. | | 2 | 2 | $23N3731 | ✅ | C50 is a 0.22μF bootstrap capacitor connected between the BST pin of U25 (through series resistor R154) and the SW1 pin. The capacitor value and voltage rating are appropriate for a bootstrap application. | </details> <details> <summary>R154 - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1130-0234) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3711 | ✅ | R154 is a 2.20 ohm resistor in series with bootstrap capacitor C50, connected between the BST pin (pin 8) of U25 and the SW1 pin (pin 10) through C50. This is an unusual bootstrap circuit configuration that may be intentional for current limiting. | | 2 | 2 | $23N3733 | ✅ | R154 is a 2.20 ohm resistor in series with bootstrap capacitor C50, connected between the BST pin (pin 8) of U25 and the SW1 pin (pin 10) through C50. This is an unusual bootstrap circuit configuration that may be intentional for current limiting. | </details> <details> <summary>D4 - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Cathode 1 of dual Schottky diode, connected to VCORE_PG. Part of AND gate for power good signals. | | 2 | 2 | VGFX_PG | ✅ | Cathode 2 of dual Schottky diode, connected to VGFX_PG. Part of AND gate for power good signals. | | 3 | 3 | VCORE_GFX_PG | ✅ | Common anode of dual Schottky diode, connected to VCORE_GFX_PG. Output of AND gate for combined power good signal. | </details> <details> <summary>C87 - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | P | | | ✅ | Output bulk capacitor correctly connected between +VCORE and GND. Voltage rating of 2V provides minimal margin for a VCORE rail and should be verified against the maximum VCORE voltage specification. | | N | | | ✅ | Output bulk capacitor correctly connected between +VCORE and GND. Voltage rating of 2V provides minimal margin for a VCORE rail and should be verified against the maximum VCORE voltage specification. | </details> <details> <summary>C88 - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2242-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output rail as part of parallel ceramic output capacitor bank. | | 2 | 2 | GND | ✅ | Connected to ground, completing the output capacitor connection. | </details> <details> <summary>C89 - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2242-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output rail as part of parallel ceramic output capacitor bank. | | 2 | 2 | GND | ✅ | Connected to ground, completing the output capacitor connection. | </details> <details> <summary>C90 - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2242-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output rail as part of parallel ceramic output capacitor bank. | | 2 | 2 | GND | ✅ | Connected to ground, completing the output capacitor connection. | </details> <details> <summary>C101 - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2242-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output rail as part of parallel ceramic output capacitor bank. | | 2 | 2 | GND | ✅ | Connected to ground, completing the output capacitor connection. | </details> <details> <summary>C102 - 2242-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2242-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output rail as part of parallel ceramic output capacitor bank. | | 2 | 2 | GND | ✅ | Connected to ground, completing the output capacitor connection. | </details> <details> <summary>R853 - 1130-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1130-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCORE | ✅ | Connected to +VCORE output, forming a permanent load resistor across the DC/DC converter output. | | 2 | 2 | GND | ✅ | Connected to ground, completing the load resistor path. | </details> <details> <summary>R168 - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1141-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Connected to VCORE-SW switching node, forming the resistor part of an RC snubber network to dampen switching transients. | | 2 | 2 | $23N3990 | ✅ | Connected to intermediate node of RC snubber network, linking to capacitor C52. | </details> <details> <summary>C52 - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2240-0005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3990 | ✅ | Connected to intermediate node of RC snubber network, linking to resistor R168. | | 2 | 2 | GND | ✅ | Connected to ground, completing the RC snubber network to dampen switching node ringing. | </details> <details> <summary>R37 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | This 0-ohm jumper connects the main power ground (GND) to the analog ground (AGND-VCORE), implementing a single-point star ground connection for the VCORE regulator. | | 2 | 2 | AGND-VCORE | ✅ | This 0-ohm jumper connects the main power ground (GND) to the analog ground (AGND-VCORE), implementing a single-point star ground connection for the VCORE regulator. | </details> <details> <summary>U26 - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin connected to VR_HOT_L net for thermal alert output. | | 2 | SDIO | $24N3490 | ✅ | SDIO pin connected to SVID data interface with 16.9Ω series resistor and 69.8Ω pull-up to +V1P0S. | | 3 | ALERT | $24N3492 | ✅ | ALERT pin connected to SVID alert interface with 0Ω series resistor and DNI pull-up. | | 4 | SCLK | $24N3491 | ✅ | SCLK pin connected to SVID clock interface with 20.0Ω series resistor and 69.8Ω pull-up to +V1P0S. | | 5 | GND | AGND-VGFX | ✅ | GND pin connected to AGND-VGFX analog ground, which connects to main GND through 0Ω jumper R66. | | 6 | VR_RDY | $24N3598 | ✅ | VR_RDY pin connected to power good output with 0Ω series resistor to VGFX_PG and 1.91kΩ pull-up to +VCC3. | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with multiple 22µF and 0.1µF decoupling capacitors. | | 8 | BST | $24N3593 | ✅ | BST pin connected to bootstrap circuit with 2.20Ω resistor and 0.22µF capacitor to SW1, but associated gate driver outputs GH/GL appear unused. | | 9 | GH | | ✅ | GH pin appears to be unconnected. This may be correct if integrated power stages are used, or an error if external MOSFETs are required. | | 10 | SW1 | $24N3595 | ✅ | SW1 pin connected to switch node $24N3595, which connects to bootstrap capacitor. | | 18 | SW2 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output. | | 25 | SW3 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output. | | 26 | SW4 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output. | | 27 | SW5 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output. | | 28 | SW6 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output. | | 29 | SW7 | VGFX-SW | ✅ | SW2-SW7 pins all connected to common VGFX-SW net, which connects through inductor L4 to +VGFX output. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 30 | GL | | ✅ | GL pin appears to be unconnected. This may be correct if integrated power stages are used, or an error if external MOSFETs are required. | | 31 | VBOOT | $24N3564 | ✅ | VBOOT pin connected through 100kΩ resistor to AGND-VGFX to set I2C address to 0x1 per text note. | | 32 | GND1 | AGND-VGFX | ✅ | GND1 pin connected to AGND-VGFX analog ground. | | 33 | VCCP | $24N3578 | ✅ | VCCP pin connected to internal LDO output with 1.00Ω resistor to +5VSB and 4.7µF decoupling capacitor. | | 34 | TSENSE | $24N3584 | ✅ | TSENSE pin connected to temperature sensing network with 100kΩ thermistor and 14.0kΩ resistor forming voltage divider. | | 35 | IMAX | $24N3588 | ✅ | IMAX pin connected through 44.2kΩ resistor to AGND-VGFX to set maximum current limit. Text note indicates IMAX = 14A. | | 36 | IOUT | $24N3589 | ✅ | IOUT pin connected through 16.5kΩ resistor and 470pF capacitor to AGND-VGFX for output current monitoring. | | 37 | ILIM | VGFX-ILIM | ✅ | ILIM pin connected through 15.0kΩ resistor to VGFX-CSCOMP for current limit threshold setting. | | 38 | CSCOMP | VGFX-CSCOMP | ✅ | CSCOMP pin connected to current sense compensation network with capacitors, resistors, and thermistor for temperature-dependent current limiting. | | 39 | CSSUM | VGFX-CSSUM | ✅ | CSSUM pin connected to current sense sum network with resistors to sense inductor current through DCR sensing. | | 40 | CSREF | VGFX-CSREF | ✅ | CSREF pin connected to current sense reference with 1000pF capacitor to GND and 10Ω resistor to output voltage for DCR sensing. | | 41 | FREQ | $24N3542 | ✅ | FREQ pin connected through 18.7kΩ resistor to AGND-VGFX to set switching frequency to 650kHz per text note. | | 42 | COMP | VGFX-COMP | ✅ | COMP pin connected to voltage loop compensation network with Type III compensator for stable regulation. | | 43 | FB | VGFX-FB | ✅ | FB pin connected to feedback network with resistor divider from output and compensation components. | | 44 | DIFFOUT | VGFX-DIFFOUT | ✅ | DIFFOUT pin connected to differential amplifier output with resistors to FB pin and ground. | | 45 | VSN | VR-VGFX-VSN | ✅ | VSN pin connected to negative remote sense input through 10Ω resistor from a node that connects to GND. | | 46 | VSP | VR-VGFX-VSP | ✅ | VSP pin connected to positive remote sense input through 100Ω resistor from +VGFX and 0Ω from VCCGT_SENSE. | | 47 | VCC | $24N3610 | ✅ | VCC pin connected to main power supply through 2.20Ω resistor from +5VSB with 1.0µF decoupling capacitor. | | 48 | EN | $24N6011 | ✅ | EN pin connected to enable input with 0Ω pull-up to +VCC and 10kΩ pull-down to GND, enabling converter when +VCC is present. | | 49 | GND_PAD | AGND-VGFX | ✅ | GND_PAD connected to AGND-VGFX for thermal and electrical grounding of the package. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN_PAD connected to +5VSB_SW input supply for additional current handling. | | 51 | SW_PAD | VGFX-SW | ✅ | SW_PAD connected to VGFX-SW switch node for additional current handling. | </details> <details> <summary>L4 - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to VGFX-SW switching node from the multiphase buck controller U26. This is the input side of the output filter inductor. | | 2 | 2 | +VGFX | ✅ | Connected to +VGFX output rail. The connection topology is correct for a buck converter output inductor. However, there is a significant component rating concern: the inductor is rated for 17.5A, while a schematic text note indicates 'IMAX = 24A' for the output current. This apparent mismatch requires clarification. | </details> <details> <summary>SP1 - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Solder bridge connecting the output voltage +VGFX to the current sense reference network through R225. This provides DC reference voltage for the current sensing circuit. | | 2 | 2 | $24N3559 | ✅ | Solder bridge connecting the output voltage +VGFX to the current sense reference network through R225. This provides DC reference voltage for the current sensing circuit. | </details> <details> <summary>SP2 - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Solder bridge connecting the switching node VGFX-SW to the current sensing network through R224. This provides AC coupling for current sensing to the CSSUM pin of the controller. | | 2 | 2 | $24N3558 | ✅ | Solder bridge connecting the switching node VGFX-SW to the current sensing network through R224. This provides AC coupling for current sensing to the CSSUM pin of the controller. | </details> <details> <summary>TH3 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | This thermistor provides temperature-dependent current limiting by being part of the current sensing divider network. The connection is correct. | | 2 | 2 | $24N3557 | ✅ | This thermistor provides temperature-dependent current limiting by being part of the current sensing divider network. The connection is correct. | </details> <details> <summary>TH4 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | 100K@25C thermistor for IC temperature sensing, connected in parallel with R226 (14K) between the TSENSE network and ground. | | 2 | 2 | GND | ✅ | 100K@25C thermistor for IC temperature sensing, connected in parallel with R226 (14K) between the TSENSE network and ground. | </details> <details> <summary>C76 - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | 330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification. | | 2 | N | GND | ✅ | 330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification. | </details> <details> <summary>C77 - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VGFX | ✅ | 330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity, in parallel with C76. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification. | | 2 | N | GND | ✅ | 330µF tantalum capacitor correctly connected between +VGFX output rail and GND with proper polarity, in parallel with C76. The 2V voltage rating is adequate for typical GPU core voltage applications (≤1.0V) but should be verified against the actual VGFX specification. | </details> <details> <summary>C62 - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | 47pF capacitor providing high-frequency compensation between COMP and FB pins of the voltage regulator. This is part of the Type III compensation network. | | 2 | 2 | VGFX-FB | ✅ | 47pF capacitor providing high-frequency compensation between COMP and FB pins of the voltage regulator. This is part of the Type III compensation network. | </details> <details> <summary>C63 - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | 220pF capacitor in the differential output network, filtering the signal between FB and the intermediate node connected to DIFFOUT through R200. | | 2 | 2 | $24N3522 | ✅ | 220pF capacitor in the differential output network, filtering the signal between FB and the intermediate node connected to DIFFOUT through R200. | </details> <details> <summary>C64 - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | 2200pF capacitor forming the main compensation network with R198, connecting COMP to an intermediate node that feeds back to FB. | | 2 | 2 | $24N3524 | ✅ | 2200pF capacitor forming the main compensation network with R198, connecting COMP to an intermediate node that feeds back to FB. | </details> <details> <summary>R198 - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3524 | ✅ | 3.01K resistor forming part of the Type III compensation network, connecting the intermediate node to FB through C64. | | 2 | 2 | VGFX-FB | ✅ | 3.01K resistor forming part of the Type III compensation network, connecting the intermediate node to FB through C64. | </details> <details> <summary>R199 - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | 1.00K resistor connecting FB to DIFFOUT, providing a feedback path for the differential remote sensing signal. | | 2 | 2 | VGFX-DIFFOUT | ✅ | 1.00K resistor connecting FB to DIFFOUT, providing a feedback path for the differential remote sensing signal. | </details> <details> <summary>R200 - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3522 | ✅ | 47 ohm resistor in the DIFFOUT network, forming a low-pass filter with C63 for damping and filtering the differential sensing signal. | | 2 | 2 | VGFX-DIFFOUT | ✅ | 47 ohm resistor in the DIFFOUT network, forming a low-pass filter with C63 for damping and filtering the differential sensing signal. | </details> <details> <summary>R204 - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-ILIM | ✅ | This resistor connects the ILIM pin (pin 37) to the CSCOMP pin (pin 38) of U26, setting the current limit threshold for the voltage regulator. | | 2 | 2 | VGFX-CSCOMP | ✅ | This resistor connects the ILIM pin (pin 37) to the CSCOMP pin (pin 38) of U26, setting the current limit threshold for the voltage regulator. | </details> <details> <summary>R205 - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | This resistor connects CSCOMP to an intermediate node (net $24N3557) and is in parallel with thermistor TH3, providing temperature-compensated current sensing. | | 2 | 2 | $24N3557 | ✅ | This resistor connects CSCOMP to an intermediate node (net $24N3557) and is in parallel with thermistor TH3, providing temperature-compensated current sensing. | </details> <details> <summary>R223 - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3557 | ✅ | This resistor completes the current sensing divider network from the thermistor node to CSSUM (pin 39 of U26). | | 2 | 2 | VGFX-CSSUM | ✅ | This resistor completes the current sensing divider network from the thermistor node to CSSUM (pin 39 of U26). | </details> <details> <summary>R224 - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSSUM | ✅ | This resistor connects CSSUM to the switching node (VGFX-SW through short SP2), implementing DCR current sensing by measuring the voltage across the inductor. | | 2 | 2 | $24N3558 | ✅ | This resistor connects CSSUM to the switching node (VGFX-SW through short SP2), implementing DCR current sensing by measuring the voltage across the inductor. | </details> <details> <summary>R225 - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | This resistor connects CSREF to the output voltage (+VGFX through short SP1), providing the reference for DCR current sensing. | | 2 | 2 | $24N3559 | ✅ | This resistor connects CSREF to the output voltage (+VGFX through short SP1), providing the reference for DCR current sensing. | </details> <details> <summary>C113 - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | This NPO capacitor connects between CSCOMP and CSSUM, providing high-frequency compensation for the current sense loop. | | 2 | 2 | VGFX-CSSUM | ✅ | This NPO capacitor connects between CSCOMP and CSSUM, providing high-frequency compensation for the current sense loop. | </details> <details> <summary>C166 - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | This X7R capacitor connects between CSCOMP and CSSUM in parallel with C113, providing additional mid-frequency compensation capacitance for the current sense loop. | | 2 | 2 | VGFX-CSSUM | ✅ | This X7R capacitor connects between CSCOMP and CSSUM in parallel with C113, providing additional mid-frequency compensation capacitance for the current sense loop. | </details> <details> <summary>C167 - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | This NPO capacitor connects CSREF to ground, providing high-frequency filtering for the current sense reference voltage. | | 2 | 2 | GND | ✅ | This NPO capacitor connects CSREF to ground, providing high-frequency filtering for the current sense reference voltage. | </details> <details> <summary>R195 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor for SVID_DATA-R signal with unusually low value of 69.8Ω to 1.0V supply. This value is significantly lower than typical SVID pull-up resistors and could cause excessive current draw, potential VOL specification violations, and reliability concerns. | | 2 | 2 | SVID_DATA-R | ✅ | Pull-up resistor for SVID_DATA-R signal with unusually low value of 69.8Ω to 1.0V supply. This value is significantly lower than typical SVID pull-up resistors and could cause excessive current draw, potential VOL specification violations, and reliability concerns. | </details> <details> <summary>R197 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor for SVID_CLK-R signal with unusually low value of 69.8Ω to 1.0V supply. This shares the same fundamental issue as R195, with excessive current draw and potential specification violations. | | 2 | 2 | SVID_CLK-R | ✅ | Pull-up resistor for SVID_CLK-R signal with unusually low value of 69.8Ω to 1.0V supply. This shares the same fundamental issue as R195, with excessive current draw and potential specification violations. | </details> <details> <summary>R193 - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and U26 SDIO pin. Provides impedance matching, current limiting, and protection for the SVID interface. | | 2 | 2 | $24N3490 | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and U26 SDIO pin. Provides impedance matching, current limiting, and protection for the SVID interface. | </details> <details> <summary>R194 - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and U26 SCLK pin. Provides impedance matching, current limiting, and protection for the SVID interface. | | 2 | 2 | $24N3491 | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and U26 SCLK pin. Provides impedance matching, current limiting, and protection for the SVID interface. | </details> <details> <summary>R67 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U26 ALERT pin without series resistance. | | 2 | 2 | $24N3492 | ✅ | Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U26 ALERT pin without series resistance. | </details> <details> <summary>R196 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Pull-up resistor for SVID alert line, marked DNI (Do Not Install). The alert signal operates without a pull-up in this design, likely because it is driven push-pull or has an external pull-up elsewhere. | | 2 | 2 | SVID_ALERT-R | ✅ | Pull-up resistor for SVID alert line, marked DNI (Do Not Install). The alert signal operates without a pull-up in this design, likely because it is driven push-pull or has an external pull-up elsewhere. | </details> <details> <summary>C432 - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Decoupling capacitor for +V1P0S supply rail used by SVID pull-up resistors. Provides local supply filtering, stability, and energy storage for the pull-up resistor network. | | 2 | 2 | GND | ✅ | Decoupling capacitor for +V1P0S supply rail used by SVID pull-up resistors. Provides local supply filtering, stability, and energy storage for the pull-up resistor network. | </details> <details> <summary>R203 - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3542 | ✅ | R203 is an 18.7K resistor connected between the FREQ pin (pin 41) of U26 and analog ground (AGND-VGFX) to set the switching frequency. A nearby text note indicates the target switching frequency is 650kHz. | | 2 | 2 | AGND-VGFX | ✅ | R203 is an 18.7K resistor connected between the FREQ pin (pin 41) of U26 and analog ground (AGND-VGFX) to set the switching frequency. A nearby text note indicates the target switching frequency is 650kHz. | </details> <details> <summary>R207 - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3588 | ✅ | Connected to IMAX pin of U26 to set the per-phase current limit. Text note indicates target of 14A. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, providing the ground reference for current limit setting. | </details> <details> <summary>R227 - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | Connected to IOUT pin of U26 for current monitoring. This resistor sets the gain for the current reporting function. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, providing the ground reference for current monitoring. | </details> <details> <summary>C184 - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | Connected to IOUT pin of U26 along with R227 for filtering the current monitoring signal. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, providing the ground reference for filtering. | </details> <details> <summary>C53 - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3610 | ✅ | Connected to the VCC supply net ($24N3610) which powers U26 through R229. This pin provides the positive terminal for VCC decoupling. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX, providing the ground reference for VCC decoupling. This is the analog ground for the voltage regulator section. | </details> <details> <summary>R229 - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail, providing the input voltage source for the VCC supply path. | | 2 | 2 | $24N3610 | ✅ | Connected to net $24N3610 which supplies VCC (pin 47) of U26. The 2.2 ohm resistor provides current limiting and filtering for the controller IC supply. | </details> <details> <summary>R846 - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail, providing the input voltage source for the VCCP supply path. | | 2 | 2 | $24N3578 | ✅ | Connected to net $24N3578 which supplies VCCP (pin 33) of U26. The 1.0 ohm resistor provides current limiting and filtering for the VCCP supply. | </details> <details> <summary>R228 - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3593 | ✅ | Connected to U26 pin 8 (BST) for bootstrap circuit. This is the input side of the bootstrap charging resistor. | | 2 | 2 | $24N3596 | ✅ | Connected to bootstrap capacitor C186 pin 1. This is the output side of the bootstrap charging resistor. | </details> <details> <summary>C186 - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3596 | ✅ | Connected through R228 to U26 BST pin. This is the bootstrap capacitor positive terminal. | | 2 | 2 | $24N3595 | ✅ | Connected to U26 pin 10 (SW1). This is the bootstrap capacitor negative terminal, referenced to the switch node. | </details> <details> <summary>R66 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | This 0-ohm jumper provides a single-point connection between the main power ground (GND) and the analog ground for the VGFX regulator (AGND-VGFX). This is a standard design practice for switching regulators to minimize noise coupling from power ground into sensitive analog signals. | | 2 | 2 | AGND-VGFX | ✅ | This 0-ohm jumper provides a single-point connection between the main power ground (GND) and the analog ground for the VGFX regulator (AGND-VGFX). This is a standard design practice for switching regulators to minimize noise coupling from power ground into sensitive analog signals. | </details> <details> <summary>R231 - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to the switching node VGFX-SW of the buck converter. This is the input to the RC snubber network. | | 2 | 2 | $24N3623 | ✅ | Connected to the intermediate node $24N3623 of the RC snubber, which connects to snubber capacitor C187. | </details> <details> <summary>C187 - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3623 | ✅ | Connected to the intermediate node $24N3623 of the RC snubber network, between R231 and ground. | | 2 | 2 | GND | ✅ | Connected to GND, completing the RC snubber network from the switching node to ground. | </details> <details> <summary>U41 - RT8207 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.richtek.com/SaveDownload.aspx?specid=RT8207P) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/RT8207) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VTTGND | GND | ✅ | VTTGND is correctly connected to GND as the power ground for the VTT LDO output. | | 2 | VTTSNS | +VDIMM_VTT | ✅ | VTTSNS is correctly connected to +VDIMM_VTT for remote voltage sensing of the VTT output. | | 3 | GND | GND | ✅ | GND is correctly connected to the ground plane for analog ground reference. | | 4 | MODE | GND | ✅ | MODE pin is connected to GND. This pin does not appear in the RT8207P datasheet, suggesting a different package variant. | | 5 | VTTREF | $25N769 | ✅ | VTTREF is connected to a 0.22µF bypass capacitor (C342), which is larger than the datasheet-recommended 33nF but should still function correctly. | | 6 | DEM | $25N1291 | ✅ | DEM pin is connected to a voltage divider network. This pin does not appear in the RT8207P datasheet, suggesting a different package variant. | | 8 | VDDQ | +VDIMM | ✅ | VDDQ is correctly connected to +VDIMM as the reference input for VTT and VTTREF, and for VDDQ discharge control. | | 9 | FB | $25N987 | ✅ | FB is correctly connected to a resistor divider network (R814/R815) that sets the output voltage to approximately 1.35V for DDR3L. | | 10 | S3 | EN_VTT | ✅ | S3 is correctly connected to EN_VTT signal through R302 for VTT power state control. | | 11 | S5 | EN_VDDQ | ✅ | S5 is correctly connected to EN_VDDQ signal through R300 for overall power enable control. | | 12 | TON | $25N1081 | ✅ | TON is connected to a 464K resistor (R816) to set switching frequency, but the schematic design note specifies 806K for 285kHz operation. The actual 464K resistor will result in approximately 503kHz switching frequency instead of the intended 285kHz, indicating a component value error. | | 13 | PGOOD | DRAM_PWROK | ✅ | PGOOD is correctly connected as an open-drain output with external pull-up resistor to indicate power good status. | | 14 | VDD | $25N1195 | ✅ | VDD is correctly connected through an RC filter (R813/C380) from VDDP, though the resistor value is 2.2Ω instead of the datasheet-recommended 5.1Ω. | | 15 | VDDP | +5VSB | ✅ | VDDP is correctly connected to +5VSB with bypass capacitor for the gate driver supply. | | 16 | CS | $25N1238 | ✅ | CS is connected to a 3.83K resistor (R817) for current limit setting. The resulting threshold voltage of 38.3mV is below the datasheet minimum of 50mV, which may affect current limit accuracy. | | 18 | PGND | GND | ✅ | PGND is correctly connected to GND as the power ground for the low-side MOSFET. | | 19 | LGATE | $25N901 | ✅ | LGATE is correctly connected to the low-side MOSFET gate (Q102 pin 8) for synchronous rectification. | | 20 | PHASE | DDR_PHASE | ✅ | PHASE is correctly connected to the switch node between the MOSFETs and the output inductor for current sensing and switching. | | 21 | UGATE | $25N897 | ✅ | UGATE is correctly connected to the high-side MOSFET gate (Q102 pin 1) for PWM switching control. | | 22 | BOOT | $25N771 | ✅ | BOOT is correctly connected to the bootstrap circuit with capacitor C309 (0.1µF) between BOOT and PHASE through an optional 4.7-ohm series resistor (R298) for high-side gate drive. The 0.1µF capacitor value matches the typical application circuit in the datasheet. | | 23 | VLDOIN | +VDIMM | ✅ | VLDOIN is correctly connected to +VDIMM for tracking discharge mode operation of the VTT LDO. | | 24 | VTT | +VDIMM_VTT | ✅ | VTT is correctly connected to +VDIMM_VTT output with 20µF total capacitance (C361 and C362), meeting the datasheet minimum requirement. | | 25 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) is correctly connected to GND for thermal dissipation and electrical ground. | </details> <details> <summary>Q102 - FDMS3604S ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pub/Collateral/FDMS3604S-D.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/FDMS3604S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Q1G | $25N897 | ✅ | Q1G (G1) gate pin correctly connected to UGATE output from controller U41 for high-side MOSFET drive. | | 2 | VIN_A | DDR3L_VIN | ✅ | VIN_A/B/C (D1) drain pins correctly connected to DDR3L_VIN input voltage rail with appropriate input capacitance. | | 3 | VIN_B | DDR3L_VIN | ✅ | VIN_A/B/C (D1) drain pins correctly connected to DDR3L_VIN input voltage rail with appropriate input capacitance. | | 4 | VIN_C | DDR3L_VIN | ✅ | VIN_A/B/C (D1) drain pins correctly connected to DDR3L_VIN input voltage rail with appropriate input capacitance. | | 5 | PGND_A | GND | ✅ | PGND_A/B/C (S2) source pins correctly connected to ground for synchronous MOSFET operation. | | 6 | PGND_B | GND | ✅ | PGND_A/B/C (S2) source pins correctly connected to ground for synchronous MOSFET operation. | | 7 | PGND_C | GND | ✅ | PGND_A/B/C (S2) source pins correctly connected to ground for synchronous MOSFET operation. | | 8 | Q2G | $25N901 | ✅ | Q2G (G2) gate pin correctly connected to LGATE output from controller U41 for low-side MOSFET drive. | | 9 | PHASE | DDR_PHASE | ✅ | PHASE pin correctly connected to switching node, output inductor L11, controller feedback, and bootstrap circuit. | </details> <details> <summary>L11 - 125-0004454 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/125-0004454) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | Inductor input correctly connected to DDR_PHASE switching node from Q102 for buck converter operation. | | 2 | 2 | +VDIMM | ✅ | Inductor output correctly connected to +VDIMM output voltage rail with appropriate output capacitance. | </details> <details> <summary>R298 - 110-0004467 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N771 | ✅ | Bootstrap resistor input connected to BOOT pin of RT8207 controller (U41 pin 22). This is the correct connection for a bootstrap circuit in a synchronous buck converter. | | 2 | 2 | DDR_BST | ✅ | Bootstrap resistor output connected to intermediate bootstrap node DDR_BST, which connects to bootstrap capacitor C309. This is the correct connection for a bootstrap circuit. | </details> <details> <summary>C309 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | Bootstrap capacitor connection to PHASE switch node (DDR_PHASE). This connects to U41 pin 20 (PHASE), Q102 pin 9 (PHASE), and L11 pin 1, forming the correct bootstrap circuit for the synchronous buck converter. | | 2 | 2 | DDR_BST | ✅ | Bootstrap capacitor connection to intermediate bootstrap node DDR_BST, which connects to R298 pin 2. This forms the correct bootstrap circuit topology. | </details> <details> <summary>L6 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input pin connected to +5VSB power rail, providing the source voltage for the DDR power stage through the ferrite bead filter. | | 2 | 2 | DDR3L_VIN | ✅ | Output pin connected to DDR3L_VIN net, providing filtered input voltage to the DDR switching regulator stage. | </details> <details> <summary>L5 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input pin connected to +5VSB power rail, providing the source voltage for the DDR power stage through the ferrite bead filter. | | 2 | 2 | DDR3L_VIN | ✅ | Output pin connected to DDR3L_VIN net, providing filtered input voltage to the DDR switching regulator stage. | </details> <details> <summary>C382 - 2220-0047 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM output rail as part of the feedback compensation network. | | 2 | 2 | $25N987 | ✅ | Connected to feedback node $25N987 to provide compensation for the feedback loop. | </details> <details> <summary>R814 - 1120-0187 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM output rail as the upper resistor in the feedback voltage divider network. | | 2 | 2 | $25N987 | ✅ | Connected to feedback node $25N987 which feeds into U41 pin 9 (FB). | </details> <details> <summary>R815 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N987 | ✅ | Connected to feedback node $25N987 as the lower resistor in the feedback voltage divider network. | | 2 | 2 | GND | ✅ | Connected to GND to complete the feedback voltage divider. | </details> <details> <summary>R816 - 1120-0149 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | R816 sets the switching frequency of the RT8207 DDR memory power controller by connecting +5VSB to the TON pin (U41 pin 12). However, the component value (464K) does not match the design specification documented on the schematic (806K for 285 kHz operation), resulting in a switching frequency of approximately 504 kHz instead of the intended 285 kHz. | | 2 | 2 | $25N1081 | ✅ | R816 sets the switching frequency of the RT8207 DDR memory power controller by connecting +5VSB to the TON pin (U41 pin 12). However, the component value (464K) does not match the design specification documented on the schematic (806K for 285 kHz operation), resulting in a switching frequency of approximately 504 kHz instead of the intended 285 kHz. | </details> <details> <summary>R817 - 1120-0267 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | R817 is part of the current sense circuit for the RT8207 controller, connecting between the VDD and CS pins. Without the RT8207 datasheet, the correct value cannot be verified, but the value of 3.83K appears reasonable and there is no clear evidence of error. | | 2 | 2 | $25N1238 | ✅ | R817 is part of the current sense circuit for the RT8207 controller, connecting between the VDD and CS pins. Without the RT8207 datasheet, the correct value cannot be verified, but the value of 3.83K appears reasonable and there is no clear evidence of error. | </details> <details> <summary>R813 - 110-0004466 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | Connected to net $25N1195, which supplies VDD (pin 14) of U41 (RT8207). Forms an RC filter with C380 to provide filtered power to the controller IC. | | 2 | 2 | +5VSB | ✅ | Connected to +5VSB supply rail. Provides the input voltage for the filtered VDD supply to U41. | </details> <details> <summary>C379 - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Provides the ground reference for the +5VSB decoupling capacitor. | | 2 | 2 | +5VSB | ✅ | Connected to +5VSB supply rail. Provides local decoupling for the 5V standby supply near the RT8207 controller. | </details> <details> <summary>C380 - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Provides the ground reference for the VDD decoupling capacitor. | | 2 | 2 | $25N1195 | ✅ | Connected to net $25N1195 (VDD of U41). Provides local decoupling for the RT8207 controller's VDD pin and completes the RC filter with R813. | </details> <details> <summary>R300 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SLP_S4_L | ✅ | 0-ohm resistor connecting SLP_S4_L sleep signal to EN_VDDQ, which controls U41 pin 11 (S5) to enable/disable VDDQ output based on S4 sleep state. | | 2 | 2 | EN_VDDQ | ✅ | 0-ohm resistor connecting SLP_S4_L sleep signal to EN_VDDQ, which controls U41 pin 11 (S5) to enable/disable VDDQ output based on S4 sleep state. | </details> <details> <summary>R810 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1291 | ✅ | 10K pull-up resistor connecting U41 pin 6 (DEM) to +5VSB supply, configuring the mode control pin. | | 2 | 2 | +5VSB | ✅ | 10K pull-up resistor connecting U41 pin 6 (DEM) to +5VSB supply, configuring the mode control pin. | </details> <details> <summary>R302 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SLP_S3_L | ✅ | 0-ohm resistor connecting SLP_S3_L sleep signal to EN_VTT, which controls U41 pin 10 (S3) to enable/disable VTT output based on S3 sleep state. | | 2 | 2 | EN_VTT | ✅ | 0-ohm resistor connecting SLP_S3_L sleep signal to EN_VTT, which controls U41 pin 10 (S3) to enable/disable VTT output based on S3 sleep state. | </details> <details> <summary>C342 - 123-0003769 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is correctly connected to GND, providing the ground reference for the VTTREF filtering capacitor. | | 2 | 2 | $25N769 | ✅ | Pin 2 is correctly connected to net $25N769 (VTTREF pin 5 of U41), providing filtering for the VTT reference voltage input of the RT8207 controller. | </details> <details> <summary>R124 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DRAM_S4_PWROK | ✅ | 10K pull-up resistor from DRAM_S4_PWROK to +VDIMM (1.35V output). This pulls up the PGOOD signal from U41 to the output voltage, creating a logical AND function where the signal is high only when both the IC asserts PGOOD and the output voltage is present. | | 2 | 2 | +VDIMM | ✅ | 10K pull-up resistor from DRAM_S4_PWROK to +VDIMM (1.35V output). This pulls up the PGOOD signal from U41 to the output voltage, creating a logical AND function where the signal is high only when both the IC asserts PGOOD and the output voltage is present. | </details> <details> <summary>R293 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DRAM_S4_PWROK | ✅ | 0-ohm jumper resistor connecting DRAM_PWROK from U41 pin 13 (PGOOD) to DRAM_S4_PWROK, which is pulled up to +VDIMM through R124. This allows for easy modification of the power good signal routing. | | 2 | 2 | DRAM_PWROK | ✅ | 0-ohm jumper resistor connecting DRAM_PWROK from U41 pin 13 (PGOOD) to DRAM_S4_PWROK, which is pulled up to +VDIMM through R124. This allows for easy modification of the power good signal routing. | </details> <details> <summary>R24 - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Upper feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator. | | 2 | 2 | +V1P8S_FB | ✅ | Upper feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator. | </details> <details> <summary>R25 - 110-0004490 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004490) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator. | | 2 | 2 | +V1P8S_FB | ✅ | Lower feedback resistor correctly configured to set 1.8V output voltage for the APL5933 LDO regulator. | </details> <details> <summary>R23 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Pull-up resistor correctly configured to pull the PGOOD signal to the output voltage level. | | 2 | 2 | +V1P8S_PGD | ✅ | Pull-up resistor correctly configured to pull the PGOOD signal to the output voltage level. | </details> <details> <summary>R22 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V_EN | ✅ | Zero-ohm jumper correctly provides direct connection between enable signals for power sequencing. | | 2 | 2 | +V1P8S_EN | ✅ | Zero-ohm jumper correctly provides direct connection between enable signals for power sequencing. | </details> <details> <summary>U21 - APL5933 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/APL5933) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P8S_PGD | ✅ | PGOOD pin correctly connected to +V1P8S_PGD net with pull-up resistor R23 to output voltage. | | 2 | EN | +V1P8S_EN | ✅ | EN pin correctly connected to +V1P8S_EN, which is controlled by sequencing circuit through Q3 and R125. | | 3 | VIN | +PS_3VSB | ✅ | VIN pin correctly connected to +PS_3VSB input supply with bypass capacitor C3. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin correctly connected to +PS_3VSB, tied together with VIN pin. | | 5 | NC | | ✅ | NC pin correctly left unconnected as specified. | | 6 | VOUT | +V1P8S | ✅ | VOUT pin correctly connected to +V1P8S output with adequate output capacitance. | | 7 | ADJ | +V1P8S_FB | ✅ | ADJ pin correctly connected to feedback network that sets output to approximately 1.816V. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins correctly connected to ground plane. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins correctly connected to ground plane. | </details> <details> <summary>Q5 - RXR035N03 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | G | GATE | 1P35V_EN | ❌ | <details><summary>Gate is connected to enable signal 1P35V_EN through series resistor R134 (1K). Critical issue: VGS may be insufficient to meet the schematic design constraint 'VGS should > 2V' if +VCC is 3.3V, resulting in VGS ≈ 1.95V and potentially higher RDS(on) and power dissipation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="17.17,54.48,24.67,61.98" aspect-ratio="1.29" } <ul><li>Pin G (GATE) is connected to net 1P35V_EN (from schematic)</li><li>1P35V_EN is driven by V1P0S_PG through resistor R134 (1K ohm) (from schematic)</li><li>V1P0S_PG is the power-good output from LDO U38 pin 7 (POK) (from schematic)</li><li>V1P0S_PG is pulled up to +VCC through R319 (10K ohm) (from schematic)</li><li>C105 (0.1uF) provides gate-to-ground filtering (from schematic)</li><li>Schematic note near Q5 explicitly states 'VGS should > 2V' as a design constraint (from schematic)</li><li>Pin G is the Gate terminal per the TSMT3 package (pin 3) (from datasheet <a href="https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=11">RXR035N03</a>, page 11)</li><li>Gate threshold voltage VGS(th) ranges from 1.0V to 2.5V at VDS=10V, ID=1mA (from datasheet <a href="https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2">RXR035N03</a>, page 2)</li><li>RDS(on) at VGS=10V is 35mΩ typical, 50mΩ maximum (from datasheet <a href="https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2">RXR035N03</a>, page 2)</li><li>RDS(on) at VGS=4.5V is 45mΩ typical, 65mΩ maximum (from datasheet <a href="https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2">RXR035N03</a>, page 2)</li><li>RDS(on) at VGS=4.0V is 50mΩ typical, 70mΩ maximum (from datasheet <a href="https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2">RXR035N03</a>, page 2)</li><li>When Q5 is fully on, source voltage VS is approximately 1.35V (+V1P35S) (reasoning)</li><li>Gate voltage VG equals V1P0S_PG, which is pulled up to +VCC when the power good signal is asserted (reasoning)</li><li>VGS = VG - VS = +VCC - 1.35V (reasoning)</li><li>If +VCC is 3.3V (common supply voltage), then VGS = 3.3V - 1.35V = 1.95V (reasoning)</li><li>VGS of 1.95V does NOT meet the schematic design constraint 'VGS should > 2V' (reasoning)</li><li>For VGS > 2V with VS = 1.35V, the gate voltage must be VG > 3.35V, requiring +VCC to be at least 3.35V (reasoning)</li><li>If +VCC is 5V, then VGS = 5V - 1.35V = 3.65V, which meets the constraint with adequate margin (reasoning)</li><li>At marginal VGS levels near threshold, RDS(on) increases significantly, potentially 2-3x higher than specified values (reasoning)</li><li>Higher RDS(on) at insufficient VGS will increase power dissipation beyond calculated values (reasoning)</li><li>The schematic notes 'VGS=10V Rds(on)=65m MAX' and 'VGS=5V Rds(on)=90m MAX' appear to be conservative estimates or may reference different conditions than the datasheet specifications (reasoning)</li><li>Recommend verifying that +VCC is at least 3.35V, preferably 5V, to ensure VGS > 2V and reliable MOSFET operation with specified RDS(on) values (reasoning)</li></ul></details> | | D | DRAIN | +VDIMM | ✅ | Drain is connected to +VDIMM input power rail. This is the input side of the high-side load switch configuration. | | S | SOURCE | +V1P35S | ✅ | Source is correctly connected to +V1P35S output rail (1.35V). At maximum current of 3.5A, power dissipation (0.8-0.86W) exceeds FR4 board thermal limit (0.76W) but remains within ceramic board limit (1.0W). Thermal management must be verified for FR4 implementations. | </details> <details> <summary>R134 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | Connected to V1P0S_PG power good signal, which is pulled up to +VCC through R319 (10K) and driven by U38 pin 7 (POK). This signal indicates when the +V1P0S rail is within regulation. | | 2 | 2 | 1P35V_EN | ✅ | Connected to 1P35V_EN, which drives the gate of Q5 through this 1K resistor. The resistor provides gate current limiting and slew rate control for the MOSFET gate drive. | </details> <details> <summary>R120 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Connected to +V1P35S output voltage rail (1.35V). This resistor provides a high-impedance sensing path from the output voltage for power sequencing control. | | 2 | 2 | 1P35V_PWG | ✅ | Connected to 1P35V_PWG, which drives the base of Q3 (dual NPN transistor) for power sequencing control. When +V1P35S is high, R120 pulls up 1P35V_PWG to turn on Q3 for downstream rail sequencing. | </details> <details> <summary>U38 - APL5912KAC-TRGS-X ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/APL5912KAC-TRGS-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | VIN-2 | +VDIMM | ❌ | <details><summary>Input pins connected to +VDIMM rail. Critical design issue: upstream MOSFET Q5 is rated for 3.5A maximum, but the required load current is approximately 4.9A (1.3A + 3.6A per schematic notes), creating a current bottleneck. Additionally, there is a circular dependency in the power sequencing that requires careful startup analysis.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="20.80,18.61,28.30,26.11" aspect-ratio="1.29" } <ul><li>Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic)</li><li>Both input pins are paralleled to handle high input current for the 5A LDO (reasoning)</li><li>Input capacitors C118 (10uF) and C336 (10uF) provide 20uF total input capacitance (from schematic)</li><li>+VDIMM is sourced from +V1P35S through MOSFET Q5 (RXR035N03) (from schematic)</li><li>Q5 gate is controlled by 1P35V_EN signal (from schematic)</li><li>1P35V_EN is driven by V1P0S_PG (U38 power good output pin 7) through R134 (1K) (from schematic)</li><li>This creates a circular dependency: U38 requires +VDIMM to operate, but +VDIMM requires Q5 to be enabled, which requires V1P0S_PG from U38 (reasoning)</li><li>V1P0S_PG is pulled up to +VCC through R319 (10K), which may provide initial gate voltage to Q5 if +VCC is available before +VDIMM (from schematic)</li><li>Schematic note indicates 'MAX CURRENT = 5A' for U38 (APL5912) (from schematic)</li><li>Schematic notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic)</li><li>Schematic note indicates 'Id MAX = 3.5 Amps' for Q5 (RXR035N03) (from schematic)</li><li>For an LDO regulator, input current approximately equals output current (reasoning)</li><li>Required input current of approximately 4.9A exceeds Q5's 3.5A maximum rating by 40% (reasoning)</li><li>This creates a fundamental current bottleneck where Q5 cannot supply sufficient current to U38 for the specified load (reasoning)</li><li>Q5 will operate beyond its maximum rating, potentially causing overheating, voltage drop, or device failure (reasoning)</li><li>Recommendation: Replace Q5 with a higher current rated MOSFET (≥5A), or reduce the load current to below 3.5A (reasoning)</li></ul></details> | | 9 | VIN-1 | +VDIMM | ❌ | <details><summary>Input pins connected to +VDIMM rail. Critical design issue: upstream MOSFET Q5 is rated for 3.5A maximum, but the required load current is approximately 4.9A (1.3A + 3.6A per schematic notes), creating a current bottleneck. Additionally, there is a circular dependency in the power sequencing that requires careful startup analysis.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="18.53,23.32,26.03,30.82" aspect-ratio="1.29" } <ul><li>Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic)</li><li>Both input pins are paralleled to handle high input current for the 5A LDO (reasoning)</li><li>Input capacitors C118 (10uF) and C336 (10uF) provide 20uF total input capacitance (from schematic)</li><li>+VDIMM is sourced from +V1P35S through MOSFET Q5 (RXR035N03) (from schematic)</li><li>Q5 gate is controlled by 1P35V_EN signal (from schematic)</li><li>1P35V_EN is driven by V1P0S_PG (U38 power good output pin 7) through R134 (1K) (from schematic)</li><li>This creates a circular dependency: U38 requires +VDIMM to operate, but +VDIMM requires Q5 to be enabled, which requires V1P0S_PG from U38 (reasoning)</li><li>V1P0S_PG is pulled up to +VCC through R319 (10K), which may provide initial gate voltage to Q5 if +VCC is available before +VDIMM (from schematic)</li><li>Schematic note indicates 'MAX CURRENT = 5A' for U38 (APL5912) (from schematic)</li><li>Schematic notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic)</li><li>Schematic note indicates 'Id MAX = 3.5 Amps' for Q5 (RXR035N03) (from schematic)</li><li>For an LDO regulator, input current approximately equals output current (reasoning)</li><li>Required input current of approximately 4.9A exceeds Q5's 3.5A maximum rating by 40% (reasoning)</li><li>This creates a fundamental current bottleneck where Q5 cannot supply sufficient current to U38 for the specified load (reasoning)</li><li>Q5 will operate beyond its maximum rating, potentially causing overheating, voltage drop, or device failure (reasoning)</li><li>Recommendation: Replace Q5 with a higher current rated MOSFET (≥5A), or reduce the load current to below 3.5A (reasoning)</li></ul></details> | | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | FB | FB_V1P0S | ✅ | Feedback pin correctly connected to resistor divider network (R136 and R135) with compensation capacitor C119. | | 3 | VOUT-2 | +V1P0S | ✅ | Output pins correctly connected to +V1P0S rail with adequate output capacitance. | | 4 | VOUT-1 | +V1P0S | ✅ | Output pins correctly connected to +V1P0S rail with adequate output capacitance. | | 6 | VCNTL | VCNTL_V1P0S | ✅ | VCNTL pin connected to +VCC through 10 ohm resistor with 1uF capacitor to ground. Without datasheet, cannot verify if this is the correct configuration. | | 7 | POK | V1P0S_PG | ✅ | Power good output correctly configured with pull-up resistor to +VCC. | | 8 | EN | 1P0V_EN | ✅ | Enable pin correctly connected to VCORE_GFX_PG through 0 ohm jumper R306. | </details> <details> <summary>R136 - 110-0002029 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002029) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FB_V1P0S | ✅ | Upper feedback resistor (40.2K) correctly connected between FB_V1P0S and +V1P0S, setting output voltage to approximately 1.025V. | | 2 | 2 | +V1P0S | ✅ | Upper feedback resistor (40.2K) correctly connected between FB_V1P0S and +V1P0S, setting output voltage to approximately 1.025V. | </details> <details> <summary>R135 - 110-0004498 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004498) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor (143K) correctly connected between GND and FB_V1P0S, completing the feedback divider for 1.0V output. | | 2 | 2 | FB_V1P0S | ✅ | Lower feedback resistor (143K) correctly connected between GND and FB_V1P0S, completing the feedback divider for 1.0V output. | </details> <details> <summary>R320 - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCNTL_V1P0S | ✅ | 10Ω resistor connecting VCNTL pin to +VCC. With C117 (1uF), creates 10μs time constant which is unusually fast for typical soft-start applications; function cannot be definitively verified without APL5912KAC-TRGS-X datasheet. | | 2 | 2 | +VCC | ✅ | 10Ω resistor connecting VCNTL pin to +VCC. With C117 (1uF), creates 10μs time constant which is unusually fast for typical soft-start applications; function cannot be definitively verified without APL5912KAC-TRGS-X datasheet. | </details> <details> <summary>R319 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | 10K pull-up resistor correctly connecting V1P0S_PG to +VCC for power good signal. | | 2 | 2 | +VCC | ✅ | 10K pull-up resistor correctly connecting V1P0S_PG to +VCC for power good signal. | </details> <details> <summary>R306 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | 0Ω jumper correctly connecting VCORE_GFX_PG to 1P0V_EN for power sequencing. | | 2 | 2 | 1P0V_EN | ✅ | 0Ω jumper correctly connecting VCORE_GFX_PG to 1P0V_EN for power sequencing. | </details> <details> <summary>R151 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | R151 is a 0-ohm jumper correctly implementing power sequencing by connecting the 1.0V rail power good signal to the 1.8V regulator enable input. | | 2 | 2 | +V1P8A_EN | ✅ | R151 is a 0-ohm jumper correctly implementing power sequencing by connecting the 1.0V rail power good signal to the 1.8V regulator enable input. | </details> <details> <summary>R150 - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | Pin 1 is correctly connected to +V1P8A_FB as the upper feedback resistor for U20's output voltage adjustment. | | 2 | 2 | +V1P8A | ✅ | Pin 2 is correctly connected to +V1P8A output. | </details> <details> <summary>R153 - 110-0002726 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002726) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | Pin 1 is correctly connected to +V1P8A_FB as the lower feedback resistor for U20's output voltage adjustment. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND. | </details> <details> <summary>U20 - NCP606 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncp605-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NCP606) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN1 | +PS_3VSB | ✅ | VIN1 is correctly connected to +PS_3VSB (3.3V standby rail) to provide input power to the regulator. | | 2 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 3 | EN | +V1P8A_EN | ✅ | EN is correctly connected to +V1P8A_EN, which is driven by +V1P0A_PWRGD through R151 (0Ω) to implement power sequencing. | | 4 | VOUT | +V1P8A | ✅ | VOUT is correctly connected to +V1P8A output rail with appropriate output capacitance. | | 5 | SENSE/ADJ | +V1P8A_FB | ✅ | SENSE/ADJ is correctly connected to the feedback divider network (R150 and R153) to set the output voltage to 1.8V. | | 6 | VIN2 | +PS_3VSB | ✅ | VIN2 is correctly connected to +PS_3VSB, tied together with VIN1 as required by the datasheet. | | 7 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) is correctly connected to ground for thermal management. | </details> <details> <summary>R34 - 110-0003781 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0003781) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Upper feedback resistor correctly configured with 6.04K value to set U24 output voltage to 1.0V in conjunction with R35. | | 2 | 2 | +V1P0A | ✅ | Upper feedback resistor correctly configured with 6.04K value to set U24 output voltage to 1.0V in conjunction with R35. | </details> <details> <summary>R35 - 110-0004494 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004494) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | Lower feedback resistor correctly configured with 23.7K value to set U24 output voltage to 1.0V in conjunction with R34. | | 2 | 2 | GND | ✅ | Lower feedback resistor correctly configured with 23.7K value to set U24 output voltage to 1.0V in conjunction with R34. | </details> <details> <summary>R32 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pull-up resistor for U24 enable pin, correctly configured to pull to +5VSB for power sequencing. The enable voltage exceeds VIN but this is typical and acceptable for most LDO enable pins. | | 2 | 2 | +V1P0A_ENABLE | ✅ | Pull-up resistor for U24 enable pin, correctly configured to pull to +5VSB for power sequencing. The enable voltage exceeds VIN but this is typical and acceptable for most LDO enable pins. | </details> <details> <summary>R33 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | Pull-up resistor for U24 power good output, correctly configured to pull up to +PS_3VSB for proper open-drain operation. | | 2 | 2 | +V1P0A_PWRGD | ✅ | Pull-up resistor for U24 power good output, correctly configured to pull up to +PS_3VSB for proper open-drain operation. | </details> <details> <summary>U24 - APL5933 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/APL5933) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P0A_PWRGD | ✅ | PGOOD output is correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB and used for power sequencing through D11. | | 2 | EN | +V1P0A_ENABLE | ✅ | EN input is pulled up to +5VSB through R32 (4.7K). This may be a concern if the enable pin cannot tolerate 5V when VIN is 3.3V, though it could be intentional for sequencing. | | 3 | VIN | +PS_3VSB | ✅ | VIN and VDD pins are both correctly connected to +PS_3VSB input supply with appropriate decoupling capacitors. | | 4 | VDD | +PS_3VSB | ✅ | VIN and VDD pins are both correctly connected to +PS_3VSB input supply with appropriate decoupling capacitors. | | 5 | NC | | ✅ | NC pin is correctly left unconnected. | | 6 | VOUT | +V1P0A | ✅ | VOUT pin is correctly connected to +V1P0A output with appropriate bulk and decoupling capacitors. | | 7 | ADJ | +V1P0A_FB | ✅ | ADJ feedback pin is correctly connected to resistor divider R34/R35 that sets output voltage to 1.004V, very close to the target 1.0V. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins are both correctly connected to ground plane. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins are both correctly connected to ground plane. | </details> <details> <summary>R60 - 110-0001957 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001957) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | Pull-up resistor correctly connected to +PS_3VSB supply. | | 2 | 2 | PSPUP | ✅ | Pull-up resistor correctly connected to PSPUP intermediate signal. | </details> <details> <summary>R61 - 110-0001957 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001957) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Pull-up resistor correctly connected to +VCC3 supply. | | 2 | 2 | SYS_PWRGD | ✅ | Pull-up resistor correctly connected to SYS_PWRGD output signal. | </details> <details> <summary>R206 - 110-0001951 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001951) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PSGOOD | ✅ | Pull-up resistor correctly connected to PSGOOD signal with appropriate high resistance value for delay circuit. | | 2 | 2 | +V1P8S | ✅ | Pull-up resistor correctly connected to +V1P8S supply. | </details> <details> <summary>R126 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pull-up resistor correctly connected to +5VSB supply. | | 2 | 2 | 1P5V_EN_B | ✅ | Pull-up resistor correctly connected to 1P5V_EN_B intermediate signal. | </details> <details> <summary>R125 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002058) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Pull-up resistor correctly connected to +VCC supply. | | 2 | 2 | 1P8V_EN | ✅ | Pull-up resistor correctly connected to 1P8V_EN output signal. | </details> <details> <summary>Q1 - MBT3904 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/MBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter 1 correctly connected to GND for NPN transistor operation. | | 2 | B1 | PSGOOD | ✅ | Base 1 correctly connected to PSGOOD signal, which is driven by power good AND gate through D11 and pulled up through R206. | | 3 | C2 | SYS_PWRGD | ✅ | Collector 2 correctly connected to SYS_PWRGD output with pull-up resistor R61 to +VCC3. | | 4 | E2 | GND | ✅ | Emitter 2 correctly connected to GND for NPN transistor operation. | | 5 | B2 | PSPUP | ✅ | Base 2 and Collector 1 both connected to PSPUP, forming the intermediate node of a two-stage inverter chain. | | 6 | C1 | PSPUP | ✅ | Base 2 and Collector 1 both connected to PSPUP, forming the intermediate node of a two-stage inverter chain. | </details> <details> <summary>Q3 - MBT3904 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/MBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter 1 correctly connected to GND for NPN transistor operation. | | 2 | B1 | 1P35V_PWG | ✅ | Base 1 correctly connected to 1P35V_PWG power good signal, pulled up to +V1P35S through R120. | | 3 | C2 | 1P8V_EN | ✅ | Collector 2 correctly connected to 1P8V_EN output with pull-up resistor R125 to +VCC. | | 4 | E2 | GND | ✅ | Emitter 2 correctly connected to GND for NPN transistor operation. | | 5 | B2 | 1P5V_EN_B | ✅ | Base 2 and Collector 1 both connected to 1P5V_EN_B, forming the intermediate node of a two-stage inverter for power sequencing. | | 6 | C1 | 1P5V_EN_B | ✅ | Base 2 and Collector 1 both connected to 1P5V_EN_B, forming the intermediate node of a two-stage inverter for power sequencing. | </details> <details> <summary>D11 - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | Cathode 1 correctly connected to +V1P0A_PWRGD input signal for AND gate function. | | 2 | 2 | SLP_S3_L | ✅ | Cathode 2 correctly connected to SLP_S3_L input signal for AND gate function. | | 3 | 3 | PSGOOD | ✅ | Common anode correctly connected to PSGOOD output, forming AND gate with pull-up resistor R206. | </details> <details> <summary>FB7 - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Pin 1 is connected to the +VCC3 power rail, serving as the input side of the 0-ohm jumper. | | 2 | 2 | +VCC3S | ✅ | Pin 2 is connected to the +VCC3S power rail, serving as the output side of the 0-ohm jumper that supplies power to the CPU. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **R151, R192, R216, R22, R306, R354, R72, R73, R74** (110-0001853): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001853) - **R120, R183, R190, R191, R2, R211, R220, R221, R268, R319, R400, R71** (110-0001875): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001875) - **R134, R208, R234, R259, R94** (110-0001923): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001923) - **R206** (110-0001951): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001951) - **R60, R61** (110-0001957): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001957) - **R179** (110-0001960): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001960) - **R257** (110-0001984): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0001984) - **R136** (110-0002029): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002029) - **R125, R126, R23, R32, R33** (110-0002058): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002058) - **FB7, R222, R265, R275** (110-0002124): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002124) - **R150, R24** (110-0002560): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002560) - **R213, R38, R39** (110-0002631): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002631) - **R153** (110-0002726): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0002726) - **R240, R242, R258** (110-0003059): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0003059) - **R34** (110-0003781): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0003781) - **R132** (110-0004465): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004465) - **R255** (110-0004474): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004474) - **R217, R218, R239** (110-0004476): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004476) - **R25** (110-0004490): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004490) - **R35** (110-0004494): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004494) - **R135** (110-0004498): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004498) - **R40** (110-0004695): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/110-0004695) - **R832, R833, R834, R835** (1120-0003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0003) - **R89** (1120-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0010) - **R827, R828, R829, R830, R831, R851** (1120-0011): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0011) - **R836** (1120-0018): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0018) - **R108, R320, R65** (1120-0022): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0022) - **R91, R92** (1120-0025): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0025) - **R95** (1120-0029): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0029) - **R88** (1120-0032): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0032) - **R106** (1120-0037): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0037) - **R167** (1120-0052): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0052) - **R131** (1120-0055): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0055) - **R81** (1120-0099): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0099) - **R105** (1120-0115): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0115) - **R843, R844** (1120-0203): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0203) - **R96** (1120-0282): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0282) - **R80** (1120-0329): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0329) - **R85, R86, R87** (1120-0330): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0330) - **R146** (1120-0338): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0338) - **R93** (1120-0351): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1120-0351) - **R37, R62, R63, R64, R78, R79, R840, R841, R842, R849** (1121-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0001) - **R90** (1121-0025): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1121-0025) - **R107** (1130-0002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1130-0002) - **R853** (1130-0011): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1130-0011) - **R845** (1130-0193): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1130-0193) - **R154, R166** (1130-0234): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1130-0234) - **R168** (1141-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/1141-0026) - **C10, C11, C12, C13, C177, C178, C179, C180** (123-0001038): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001038) - **C205, C206, C207, C208, C65** (123-0001056): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001056) - **C26, C27** (123-0001066): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001066) - **C252, C253** (123-0001107): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001107) - **C164, C201, C224, C225** (123-0001176): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0001176) - **C148** (123-0004408): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0004408) - **C129, C76, C77, C87** (123-0005035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/123-0005035) - **L11** (125-0004454): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/125-0004454) - **L3** (125-0004501): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/125-0004501) - **FB3** (126-0001423): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0001423) - **FB1, FB11, FB4, FB5, L12, L13, L5, L6** (126-0004457): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/126-0004457) - **D3** (130-0004403): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/130-0004403) - **Y1** (145-0004789): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/145-0004789) - **X1, Y2** (145-0004792): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/145-0004792) - **P2** (158-0001269): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/158-0001269) - **P1** (158-0004513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/158-0004513) - **J10** (158-0004534): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/158-0004534) - **C35** (2220-0002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0002) - **C36** (2220-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0014) - **C39, C47** (2220-0025): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0025) - **C45** (2220-0035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0035) - **C429, C430, C431** (2220-0039): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2220-0039) - **C34** (2221-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0001) - **C37, C40** (2221-0002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0002) - **C38** (2221-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0004) - **C425** (2221-0017): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2221-0017) - **C50** (2222-0008): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0008) - **C24, C428** (2222-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0014) - **C25, C426, C427, C433, C46** (2222-0016): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2222-0016) - **C28** (2232-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2232-0012) - **C48** (2232-0016): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2232-0016) - **C52** (2240-0005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2240-0005) - **C101, C102, C88, C89, C90** (2242-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2242-0014) - **J5, J6, J7** (258-0002513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0002513) - **USB1** (258-0004503): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0004503) - **J1** (258-0004612): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0004612) - **J4** (258-0004869): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0004869) - **JP1** (258-0005019): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/258-0005019) - **FB12** (3044-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3044-0010) - **FB13** (3044-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3044-0012) - **L8** (3120-0183): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3120-0183) - **L18, L4** (3120-0266): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3120-0266) - **CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17** (3142-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3142-0014) - **J11** (3362-0042): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3362-0042) - **J8** (3430-0212): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3430-0212) - **BH1** (353-0003073): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/353-0003073) - **FL1** (3750-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3750-0010) - **SW1** (3770-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3770-0026) - **TH1, TH2, TH3, TH4** (3880-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3880-0004) - **U42** (4300-0071): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4300-0071) - **U5, U6** (4327-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4327-0009) - **U19** (4327-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4327-0010) - **D10, D5** (4536-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4536-0009) - **D1, D2** (4560-0045): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4560-0045) - **D13** (4620-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/4620-0026) - **TP17, TP18** (999-0000003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/999-0000003) - **SP1, SP2, SP3, SP4** (999-0000005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/999-0000005) - **U11** (AD42): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/AD42) - **U38** (APL5912KAC-TRGS-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/APL5912KAC-TRGS-X) - **U21, U24** (APL5933): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/APL5933) - **D11, D4, D6** (BAT54A-S): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAT54A-S) - **D8** (BAT754C): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAT754C) - **Q2, Q9** (BAV99-7-F-S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BAV99-7-F-S-X) - **L1** (BKP2125HS221-T): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/BKP2125HS221-T) - **U25, U26** (NCP81109GMNTXG): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NCP81109GMNTXG) - **U35** (NCT3012S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NCT3012S-X) - **U18** (NTB0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTB0104GU12) - **U4, U7** (NTS0102GT): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0102GT) - **U10, U14, U15, U16, U17** (NTS0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0104GU12) - **U29** (TPD4USB30): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/TPD4USB30) </details> Note: DRCY uses AI. Please verify the outputs.

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[🚨 Error] Component CPU1, pins AK12, AK13: DDI0_RCOMP pins are swapped. Pin AK13 uses overline notation (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅) indicating negative polarity but connects to DDI_RCOMP_P net, while pin AK12 labeled DDI0_RCOMP_P (positive) connects to DDI_RCOMP_N net.

Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in the schematic (from schematic)
Pin AK12 is labeled DDI0_RCOMP_P in the schematic (from schematic)
Pin AK13 connects to net DDI_RCOMP_P (from schematic)
Pin AK12 connects to net DDI_RCOMP_N (from schematic)
Overline notation in electronics indicates negative, inverted, or complement signals (reasoning)
The _P suffix in pin names indicates positive polarity (reasoning)
Pin AK12 is described as DDI0_RCOMP_P (positive) in the datasheet (from datasheet 140-0004628)
Pin AK13 with overline notation should be the negative RCOMP signal (reasoning)
The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) (reasoning)
The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) (reasoning)
The connections should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P (reasoning)
R217 (402 ohm) correctly connects between the two RCOMP nets, but the CPU pin assignments need correction (from schematic)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AK12, AK13`: DDI0_RCOMP pins are swapped. Pin AK13 uses overline notation (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅) indicating negative polarity but connects to DDI_RCOMP_P net, while pin AK12 labeled DDI0_RCOMP_P (positive) connects to DDI_RCOMP_N net.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,39.05" aspect-ratio="1.29" } - Pin AK13 is labeled D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation in the schematic *(from schematic)* - Pin AK12 is labeled DDI0_RCOMP_P in the schematic *(from schematic)* - Pin AK13 connects to net DDI_RCOMP_P *(from schematic)* - Pin AK12 connects to net DDI_RCOMP_N *(from schematic)* - Overline notation in electronics indicates negative, inverted, or complement signals *(reasoning)* - The _P suffix in pin names indicates positive polarity *(reasoning)* - Pin AK12 is described as DDI0_RCOMP_P (positive) in the datasheet *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - Pin AK13 with overline notation should be the negative RCOMP signal *(reasoning)* - The negative pin (AK13) is incorrectly connected to the positive net (DDI_RCOMP_P) *(reasoning)* - The positive pin (AK12) is incorrectly connected to the negative net (DDI_RCOMP_N) *(reasoning)* - The connections should be swapped: AK13 should connect to DDI_RCOMP_N and AK12 should connect to DDI_RCOMP_P *(reasoning)* - R217 (402 ohm) correctly connects between the two RCOMP nets, but the CPU pin assignments need correction *(from schematic)* Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[🚨 Error] Component CPU1, pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33: CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.

Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S (from schematic)
These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply (from datasheet 140-0004628, page 213)
The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail (from datasheet 140-0004628, page 120)
The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% (from datasheet 140-0004628, page 119)
The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails (reasoning)
A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification (from schematic)
Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail (from schematic)
Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins (from schematic)
Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures (reasoning)
These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33`: CORE_V1P05_S3 power pins are connected to +V1P0S (1.0V) instead of the specified 1.05V supply. This is 50mV (approximately 5%) below the nominal voltage specification.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,28.61,61.48,49.63" aspect-ratio="1.29" } - Pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33 are all connected to net +V1P0S *(from schematic)* - These pins are labeled CORE_V1P05_S3 in the datasheet, indicating they require a 1.05V supply *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=213>), page 213)* - The datasheet specifies V1P05S Supply Voltage as typ 1.05V with DC tolerance ±2% and AC tolerance ±3%, maximum current 1.3A for CORE_V1P05_S3 rail *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120>), page 120)* - The datasheet specifies V1P0S Supply Voltage as typ 1.0V with DC tolerance ±2% and AC tolerance ±3% *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/03a16c08268a6769be4b354bc17b1024595b904d/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119>), page 119)* - The voltage ranges for V1P05S (1.029V to 1.071V) and V1P0S (0.98V to 1.02V) do not overlap, confirming these are distinct power rails *(reasoning)* - A text note indicates 1.1A current draw for these pins, which is within the 1.3A maximum specification *(from schematic)* - Text notes reference +V1P05S supply existing elsewhere in the design, suggesting these pins should connect to that rail *(from schematic)* - Multiple decoupling capacitors (C182, C183, C193, C194, C195, C198, C199, C200, C220, C222, C223, C245, C246, C254, C255, C263, C274, C181, C171) connect +V1P0S to GND near these pins *(from schematic)* - Connecting 1.05V-specified pins to a 1.0V rail results in 50mV undervoltage, which could cause reliability issues or functional failures *(reasoning)* - These pins should be connected to a +V1P05S rail (1.05V) instead of +V1P0S (1.0V) to meet datasheet specifications *(reasoning)* Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/140-0004628)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[🚨 Error] Component U4, pin 7: VCCB pin incorrectly connected to +USBVCC (approximately 5V), which exceeds the device's maximum voltage rating of 3.6V. This overvoltage condition could damage the device or cause malfunction.

Pin 7 (VCCB) is connected to +USBVCC net (from schematic)
The device voltage attribute specifies 1.2-3.6V operating range (from schematic)
+USBVCC is derived from +5VSB through ferrite bead FB13 (from schematic)
FB13 (part 3044-0012) is a ferrite bead inductor, not a voltage regulator, so +USBVCC voltage equals +5VSB voltage minus minimal resistive drop (from schematic)
+5VSB is a 5V standby supply based on standard power supply naming conventions (reasoning)
+USBVCC supplies U32 (AP2172MPG USB power switch) which has input voltage range 2.7V-5.5V, confirming +USBVCC is intended to be approximately 5V (from schematic)
U32 outputs USBP1 and USBP2 connect through ferrite beads L1 and L2 to VBUS1 and VBUS2, which supply USB connector USB1 pins 1 and 10 (from schematic)
USB VBUS specification requires 5V ±5% (4.75V-5.25V), therefore +USBVCC must be approximately 5V to provide proper USB power (reasoning)
Connecting VCCB to a 5V supply exceeds the 3.6V maximum rating by 1.4V (39% overvoltage) (reasoning)
This overvoltage condition violates the device absolute maximum ratings and could cause device damage, latchup, or unreliable operation (reasoning)
Recommended fix: Add a 3.3V or 1.8V LDO regulator to power VCCB from +USBVCC or +5VSB, ensuring VCCB stays within the 1.2-3.6V specification (reasoning)
Alternative fix: Replace NTS0102GT with a level translator that supports 5V on VCCB, such as TXS0102 or TXB0102 which support VCCB up to 5.5V (reasoning)

_{Upload a datasheet: 📤 U4}

[🚨 Error] **Component `U4`, pin `7`: VCCB pin incorrectly connected to +USBVCC (approximately 5V), which exceeds the device's maximum voltage rating of 3.6V. This overvoltage condition could damage the device or cause malfunction.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="41.02,68.01,48.52,75.51" aspect-ratio="1.29" } - Pin 7 (VCCB) is connected to +USBVCC net *(from schematic)* - The device voltage attribute specifies 1.2-3.6V operating range *(from schematic)* - +USBVCC is derived from +5VSB through ferrite bead FB13 *(from schematic)* - FB13 (part 3044-0012) is a ferrite bead inductor, not a voltage regulator, so +USBVCC voltage equals +5VSB voltage minus minimal resistive drop *(from schematic)* - +5VSB is a 5V standby supply based on standard power supply naming conventions *(reasoning)* - +USBVCC supplies U32 (AP2172MPG USB power switch) which has input voltage range 2.7V-5.5V, confirming +USBVCC is intended to be approximately 5V *(from schematic)* - U32 outputs USBP1 and USBP2 connect through ferrite beads L1 and L2 to VBUS1 and VBUS2, which supply USB connector USB1 pins 1 and 10 *(from schematic)* - USB VBUS specification requires 5V ±5% (4.75V-5.25V), therefore +USBVCC must be approximately 5V to provide proper USB power *(reasoning)* - Connecting VCCB to a 5V supply exceeds the 3.6V maximum rating by 1.4V (39% overvoltage) *(reasoning)* - This overvoltage condition violates the device absolute maximum ratings and could cause device damage, latchup, or unreliable operation *(reasoning)* - Recommended fix: Add a 3.3V or 1.8V LDO regulator to power VCCB from +USBVCC or +5VSB, ensuring VCCB stays within the 1.2-3.6V specification *(reasoning)* - Alternative fix: Replace NTS0102GT with a level translator that supports 5V on VCCB, such as TXS0102 or TXB0102 which support VCCB up to 5.5V *(reasoning)* Upload a datasheet: [📤 U4](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/NTS0102GT)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[🚨 Error] Component J11, pin 11: LED2_AC1 connects directly to U42 LED0 output (pin 31) without a current limiting resistor, unlike the other LED outputs which have 301Ω resistors. This asymmetry indicates a likely missing component in the design.

Pin 11 (LED2_AC1) connects to net LAN-LED0 (from schematic)
LAN-LED0 connects directly to U42 pin 31 (LED0 output) (from schematic)
No current limiting resistor exists between U42 pin 31 and J11 pin 11 (from schematic)
U42 pin 30 (LED1) connects through R843 (301Ω) to LINK-LED-N and then to J11 pin 13 (from schematic)
U42 pin 33 (LED2) connects through R844 (301Ω) to 1G-LED-N and then to J11 pin 12 (from schematic)
C431 (560pF) provides EMI filtering on the LAN-LED0 signal (from schematic)
The WGI210AT (U42) is an Intel Ethernet controller whose LED outputs are typically open-drain and require external current limiting resistors (reasoning)
The asymmetry in the design (two LED outputs have current limiting resistors, one does not) is inconsistent with standard LED drive practices and indicates a likely missing component (reasoning)
Without a current limiting resistor, excessive current could flow through the LED or damage the U42 output driver (reasoning)
A resistor similar to R843 and R844 (approximately 301Ω) should be added in series between U42 pin 31 and J11 pin 11 (reasoning)

_{Upload a datasheet: 📤 J11}

[🚨 Error] **Component `J11`, pin `11`: LED2_AC1 connects directly to U42 LED0 output (pin 31) without a current limiting resistor, unlike the other LED outputs which have 301Ω resistors. This asymmetry indicates a likely missing component in the design.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="116841b2cce1b13c9d52" diff-visibility="full" variant="default" view-coords="79.20,65.65,86.70,73.15" aspect-ratio="1.29" } - Pin 11 (LED2_AC1) connects to net LAN-LED0 *(from schematic)* - LAN-LED0 connects directly to U42 pin 31 (LED0 output) *(from schematic)* - No current limiting resistor exists between U42 pin 31 and J11 pin 11 *(from schematic)* - U42 pin 30 (LED1) connects through R843 (301Ω) to LINK-LED-N and then to J11 pin 13 *(from schematic)* - U42 pin 33 (LED2) connects through R844 (301Ω) to 1G-LED-N and then to J11 pin 12 *(from schematic)* - C431 (560pF) provides EMI filtering on the LAN-LED0 signal *(from schematic)* - The WGI210AT (U42) is an Intel Ethernet controller whose LED outputs are typically open-drain and require external current limiting resistors *(reasoning)* - The asymmetry in the design (two LED outputs have current limiting resistors, one does not) is inconsistent with standard LED drive practices and indicates a likely missing component *(reasoning)* - Without a current limiting resistor, excessive current could flow through the LED or damage the U42 output driver *(reasoning)* - A resistor similar to R843 and R844 (approximately 301Ω) should be added in series between U42 pin 31 and J11 pin 11 *(reasoning)* Upload a datasheet: [📤 J11](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/3362-0042)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[🚨 Error] Component U40, pins 5, 6: SDA2 and SCL2 pins are connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to connector JP1. No pullup resistors are present on these nets on this board. The PCA9306 datasheet requires pullup resistors on open-drain I/O ports for proper operation. While pullup resistors could theoretically be provided on a remote board, best practice for I2C interfaces is to provide them on the host board to ensure reliable operation. Pullup resistors should be added from these nets to +3VSB.

Pin 5 connects to GPIO_I2C_SDA and pin 6 connects to GPIO_I2C_SCL (from schematic)
Pins 5 and 6 are SDA2 and SCL2, the serial data and clock on the high-voltage side (from datasheet PCA9306DCUT, page 4)
GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 connector pins 15 and 13 respectively (from schematic)
Pin 7 (VREF2) connects to net $20N1576, which is pulled to +3VSB through R812 (200K), establishing VDPU as +3VSB (from schematic)
Open-drain I/O ports require external pullup resistors to respective supply voltages, with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU (from datasheet PCA9306DCUT, page 10)
No pullup resistors are visible on GPIO_I2C_SDA or GPIO_I2C_SCL on this schematic page (from schematic)
The low-voltage side I2C signals (I2C5_SCL and I2C5_SDA on pins 3 and 4) have pullup resistors R267 and R266 (both 10K) to +V1P8S (from schematic)
Typical application circuits show pullup resistors RPU on both the low-voltage and high-voltage sides (from datasheet PCA9306DCUT, page 17)
The asymmetry between the low-voltage side (which has pullups) and high-voltage side (which lacks pullups) suggests a design oversight (reasoning)
While it's theoretically possible to provide pullups on a remote board connected to JP1, this creates a dependency and potential failure mode if the remote board doesn't provide them (reasoning)
Best practice for I2C interfaces exposed through connectors is to provide pullup resistors on the host board to ensure reliable operation regardless of what's connected (reasoning)
Pullup resistors should be added from GPIO_I2C_SCL to +3VSB and from GPIO_I2C_SDA to +3VSB, with values chosen based on bus capacitance and operating frequency per I2C specification (reasoning)

_{Replace a datasheet: 📤 U40}

[🚨 Error] **Component `U40`, pins `5, 6`: SDA2 and SCL2 pins are connected to GPIO_I2C_SDA and GPIO_I2C_SCL respectively, which route to connector JP1. No pullup resistors are present on these nets on this board. The PCA9306 datasheet requires pullup resistors on open-drain I/O ports for proper operation. While pullup resistors could theoretically be provided on a remote board, best practice for I2C interfaces is to provide them on the host board to ensure reliable operation. Pullup resistors should be added from these nets to +3VSB.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="9dc15be70220da2ee936" diff-visibility="full" variant="default" view-coords="23.76,76.83,31.26,84.92" aspect-ratio="1.29" } - Pin 5 connects to GPIO_I2C_SDA and pin 6 connects to GPIO_I2C_SCL *(from schematic)* - Pins 5 and 6 are SDA2 and SCL2, the serial data and clock on the high-voltage side *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=4>), page 4)* - GPIO_I2C_SDA and GPIO_I2C_SCL connect to JP1 connector pins 15 and 13 respectively *(from schematic)* - Pin 7 (VREF2) connects to net $20N1576, which is pulled to +3VSB through R812 (200K), establishing VDPU as +3VSB *(from schematic)* - Open-drain I/O ports require external pullup resistors to respective supply voltages, with pullup resistors required to pull SCL2 and SDA2 outputs to VDPU *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=10>), page 10)* - No pullup resistors are visible on GPIO_I2C_SDA or GPIO_I2C_SCL on this schematic page *(from schematic)* - The low-voltage side I2C signals (I2C5_SCL and I2C5_SDA on pins 3 and 4) have pullup resistors R267 and R266 (both 10K) to +V1P8S *(from schematic)* - Typical application circuits show pullup resistors RPU on both the low-voltage and high-voltage sides *(from datasheet [PCA9306DCUT](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fpca9306#page=17>), page 17)* - The asymmetry between the low-voltage side (which has pullups) and high-voltage side (which lacks pullups) suggests a design oversight *(reasoning)* - While it's theoretically possible to provide pullups on a remote board connected to JP1, this creates a dependency and potential failure mode if the remote board doesn't provide them *(reasoning)* - Best practice for I2C interfaces exposed through connectors is to provide pullup resistors on the host board to ensure reliable operation regardless of what's connected *(reasoning)* - Pullup resistors should be added from GPIO_I2C_SCL to +3VSB and from GPIO_I2C_SDA to +3VSB, with values chosen based on bus capacitance and operating frequency per I2C specification *(reasoning)* Replace a datasheet: [📤 U40](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/PCA9306DCUT)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[⚠️ Warning] Component C48, pin 2: Pin 2 connects to GND but should connect to AGND-VCORE for proper analog supply decoupling. This is inconsistent with C24 (VCC decoupling) which correctly connects to AGND-VCORE.

Pin 2 is connected to net GND (from schematic)
U25 pin 33 (VCCP) is likely an analog power supply pin based on typical power controller architectures (reasoning)
U25 analog ground pins (5, 32, 49) all connect to AGND-VCORE (from schematic)
C24, which decouples U25 pin 47 (VCC), connects to AGND-VCORE (from schematic)
For proper noise isolation, analog supply decoupling capacitors should reference the same ground as the IC's analog ground pins (reasoning)
C48 pin 2 should connect to AGND-VCORE instead of GND to maintain consistent ground referencing for analog supplies (reasoning)
Connecting to GND instead of AGND-VCORE may introduce switching noise into the analog supply and degrade performance (reasoning)
Recommendation: Change C48 pin 2 connection from GND to AGND-VCORE (reasoning)

_{Upload a datasheet: 📤 C48}

[⚠️ Warning] **Component `C48`, pin `2`: Pin 2 connects to GND but should connect to AGND-VCORE for proper analog supply decoupling. This is inconsistent with C24 (VCC decoupling) which correctly connects to AGND-VCORE.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="60.11,54.19,67.61,61.69" aspect-ratio="1.29" } - Pin 2 is connected to net GND *(from schematic)* - U25 pin 33 (VCCP) is likely an analog power supply pin based on typical power controller architectures *(reasoning)* - U25 analog ground pins (5, 32, 49) all connect to AGND-VCORE *(from schematic)* - C24, which decouples U25 pin 47 (VCC), connects to AGND-VCORE *(from schematic)* - For proper noise isolation, analog supply decoupling capacitors should reference the same ground as the IC's analog ground pins *(reasoning)* - C48 pin 2 should connect to AGND-VCORE instead of GND to maintain consistent ground referencing for analog supplies *(reasoning)* - Connecting to GND instead of AGND-VCORE may introduce switching noise into the analog supply and degrade performance *(reasoning)* - Recommendation: Change C48 pin 2 connection from GND to AGND-VCORE *(reasoning)* Upload a datasheet: [📤 C48](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/2232-0016)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[🚨 Error] Component Q5, pin G: Gate is connected to enable signal 1P35V_EN through series resistor R134 (1K). Critical issue: VGS may be insufficient to meet the schematic design constraint 'VGS should > 2V' if +VCC is 3.3V, resulting in VGS ≈ 1.95V and potentially higher RDS(on) and power dissipation.

Pin G (GATE) is connected to net 1P35V_EN (from schematic)
1P35V_EN is driven by V1P0S_PG through resistor R134 (1K ohm) (from schematic)
V1P0S_PG is the power-good output from LDO U38 pin 7 (POK) (from schematic)
V1P0S_PG is pulled up to +VCC through R319 (10K ohm) (from schematic)
C105 (0.1uF) provides gate-to-ground filtering (from schematic)
Schematic note near Q5 explicitly states 'VGS should > 2V' as a design constraint (from schematic)
Pin G is the Gate terminal per the TSMT3 package (pin 3) (from datasheet RXR035N03, page 11)
Gate threshold voltage VGS(th) ranges from 1.0V to 2.5V at VDS=10V, ID=1mA (from datasheet RXR035N03, page 2)
RDS(on) at VGS=10V is 35mΩ typical, 50mΩ maximum (from datasheet RXR035N03, page 2)
RDS(on) at VGS=4.5V is 45mΩ typical, 65mΩ maximum (from datasheet RXR035N03, page 2)
RDS(on) at VGS=4.0V is 50mΩ typical, 70mΩ maximum (from datasheet RXR035N03, page 2)
When Q5 is fully on, source voltage VS is approximately 1.35V (+V1P35S) (reasoning)
Gate voltage VG equals V1P0S_PG, which is pulled up to +VCC when the power good signal is asserted (reasoning)
VGS = VG - VS = +VCC - 1.35V (reasoning)
If +VCC is 3.3V (common supply voltage), then VGS = 3.3V - 1.35V = 1.95V (reasoning)
VGS of 1.95V does NOT meet the schematic design constraint 'VGS should > 2V' (reasoning)
For VGS > 2V with VS = 1.35V, the gate voltage must be VG > 3.35V, requiring +VCC to be at least 3.35V (reasoning)
If +VCC is 5V, then VGS = 5V - 1.35V = 3.65V, which meets the constraint with adequate margin (reasoning)
At marginal VGS levels near threshold, RDS(on) increases significantly, potentially 2-3x higher than specified values (reasoning)
Higher RDS(on) at insufficient VGS will increase power dissipation beyond calculated values (reasoning)
The schematic notes 'VGS=10V Rds(on)=65m MAX' and 'VGS=5V Rds(on)=90m MAX' appear to be conservative estimates or may reference different conditions than the datasheet specifications (reasoning)
Recommend verifying that +VCC is at least 3.35V, preferably 5V, to ensure VGS > 2V and reliable MOSFET operation with specified RDS(on) values (reasoning)

_{Replace a datasheet: 📤 Q5}

[🚨 Error] **Component `Q5`, pin `G`: Gate is connected to enable signal 1P35V_EN through series resistor R134 (1K). Critical issue: VGS may be insufficient to meet the schematic design constraint 'VGS should > 2V' if +VCC is 3.3V, resulting in VGS ≈ 1.95V and potentially higher RDS(on) and power dissipation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="17.17,54.48,24.67,61.98" aspect-ratio="1.29" } - Pin G (GATE) is connected to net 1P35V_EN *(from schematic)* - 1P35V_EN is driven by V1P0S_PG through resistor R134 (1K ohm) *(from schematic)* - V1P0S_PG is the power-good output from LDO U38 pin 7 (POK) *(from schematic)* - V1P0S_PG is pulled up to +VCC through R319 (10K ohm) *(from schematic)* - C105 (0.1uF) provides gate-to-ground filtering *(from schematic)* - Schematic note near Q5 explicitly states 'VGS should > 2V' as a design constraint *(from schematic)* - Pin G is the Gate terminal per the TSMT3 package (pin 3) *(from datasheet [RXR035N03](<https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=11>), page 11)* - Gate threshold voltage VGS(th) ranges from 1.0V to 2.5V at VDS=10V, ID=1mA *(from datasheet [RXR035N03](<https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2>), page 2)* - RDS(on) at VGS=10V is 35mΩ typical, 50mΩ maximum *(from datasheet [RXR035N03](<https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2>), page 2)* - RDS(on) at VGS=4.5V is 45mΩ typical, 65mΩ maximum *(from datasheet [RXR035N03](<https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2>), page 2)* - RDS(on) at VGS=4.0V is 50mΩ typical, 70mΩ maximum *(from datasheet [RXR035N03](<https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf#page=2>), page 2)* - When Q5 is fully on, source voltage VS is approximately 1.35V (+V1P35S) *(reasoning)* - Gate voltage VG equals V1P0S_PG, which is pulled up to +VCC when the power good signal is asserted *(reasoning)* - VGS = VG - VS = +VCC - 1.35V *(reasoning)* - If +VCC is 3.3V (common supply voltage), then VGS = 3.3V - 1.35V = 1.95V *(reasoning)* - VGS of 1.95V does NOT meet the schematic design constraint 'VGS should > 2V' *(reasoning)* - For VGS > 2V with VS = 1.35V, the gate voltage must be VG > 3.35V, requiring +VCC to be at least 3.35V *(reasoning)* - If +VCC is 5V, then VGS = 5V - 1.35V = 3.65V, which meets the constraint with adequate margin *(reasoning)* - At marginal VGS levels near threshold, RDS(on) increases significantly, potentially 2-3x higher than specified values *(reasoning)* - Higher RDS(on) at insufficient VGS will increase power dissipation beyond calculated values *(reasoning)* - The schematic notes 'VGS=10V Rds(on)=65m MAX' and 'VGS=5V Rds(on)=90m MAX' appear to be conservative estimates or may reference different conditions than the datasheet specifications *(reasoning)* - Recommend verifying that +VCC is at least 3.35V, preferably 5V, to ensure VGS > 2V and reliable MOSFET operation with specified RDS(on) values *(reasoning)* Replace a datasheet: [📤 Q5](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/RXR035N03)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-28 00:08:45 +00:00

[🚨 Error] Component U38, pins 5, 9: Input pins connected to +VDIMM rail. Critical design issue: upstream MOSFET Q5 is rated for 3.5A maximum, but the required load current is approximately 4.9A (1.3A + 3.6A per schematic notes), creating a current bottleneck. Additionally, there is a circular dependency in the power sequencing that requires careful startup analysis.

Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net (from schematic)
Both input pins are paralleled to handle high input current for the 5A LDO (reasoning)
Input capacitors C118 (10uF) and C336 (10uF) provide 20uF total input capacitance (from schematic)
+VDIMM is sourced from +V1P35S through MOSFET Q5 (RXR035N03) (from schematic)
Q5 gate is controlled by 1P35V_EN signal (from schematic)
1P35V_EN is driven by V1P0S_PG (U38 power good output pin 7) through R134 (1K) (from schematic)
This creates a circular dependency: U38 requires +VDIMM to operate, but +VDIMM requires Q5 to be enabled, which requires V1P0S_PG from U38 (reasoning)
V1P0S_PG is pulled up to +VCC through R319 (10K), which may provide initial gate voltage to Q5 if +VCC is available before +VDIMM (from schematic)
Schematic note indicates 'MAX CURRENT = 5A' for U38 (APL5912) (from schematic)
Schematic notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A (from schematic)
Schematic note indicates 'Id MAX = 3.5 Amps' for Q5 (RXR035N03) (from schematic)
For an LDO regulator, input current approximately equals output current (reasoning)
Required input current of approximately 4.9A exceeds Q5's 3.5A maximum rating by 40% (reasoning)
This creates a fundamental current bottleneck where Q5 cannot supply sufficient current to U38 for the specified load (reasoning)
Q5 will operate beyond its maximum rating, potentially causing overheating, voltage drop, or device failure (reasoning)
Recommendation: Replace Q5 with a higher current rated MOSFET (≥5A), or reduce the load current to below 3.5A (reasoning)

_{Upload a datasheet: 📤 U38}

[🚨 Error] **Component `U38`, pins `5, 9`: Input pins connected to +VDIMM rail. Critical design issue: upstream MOSFET Q5 is rated for 3.5A maximum, but the required load current is approximately 4.9A (1.3A + 3.6A per schematic notes), creating a current bottleneck. Additionally, there is a circular dependency in the power sequencing that requires careful startup analysis.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...03a16c08268a6769be4b354bc17b1024595b904d" pr="196" doc-id="20f8daf5c727683e4b9d" diff-visibility="full" variant="default" view-coords="18.53,18.61,28.30,30.82" aspect-ratio="1.29" } - Pins 5 (VIN-2) and 9 (VIN-1) are both connected to the +VDIMM net *(from schematic)* - Both input pins are paralleled to handle high input current for the 5A LDO *(reasoning)* - Input capacitors C118 (10uF) and C336 (10uF) provide 20uF total input capacitance *(from schematic)* - +VDIMM is sourced from +V1P35S through MOSFET Q5 (RXR035N03) *(from schematic)* - Q5 gate is controlled by 1P35V_EN signal *(from schematic)* - 1P35V_EN is driven by V1P0S_PG (U38 power good output pin 7) through R134 (1K) *(from schematic)* - This creates a circular dependency: U38 requires +VDIMM to operate, but +VDIMM requires Q5 to be enabled, which requires V1P0S_PG from U38 *(reasoning)* - V1P0S_PG is pulled up to +VCC through R319 (10K), which may provide initial gate voltage to Q5 if +VCC is available before +VDIMM *(from schematic)* - Schematic note indicates 'MAX CURRENT = 5A' for U38 (APL5912) *(from schematic)* - Schematic notes indicate load currents of 'V1.05 : 1.3A' and 'V1.0 : 3.6A', totaling 4.9A *(from schematic)* - Schematic note indicates 'Id MAX = 3.5 Amps' for Q5 (RXR035N03) *(from schematic)* - For an LDO regulator, input current approximately equals output current *(reasoning)* - Required input current of approximately 4.9A exceeds Q5's 3.5A maximum rating by 40% *(reasoning)* - This creates a fundamental current bottleneck where Q5 cannot supply sufficient current to U38 for the specified load *(reasoning)* - Q5 will operate beyond its maximum rating, potentially causing overheating, voltage drop, or device failure *(reasoning)* - Recommendation: Replace Q5 with a higher current rated MOSFET (≥5A), or reduce the load current to below 3.5A *(reasoning)* Upload a datasheet: [📤 U38](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/58364de5/.allspice/datasheets/APL5912KAC-TRGS-X)