vincentb.nikhef.nl e992dc0464 Added artifact and FPGA constraint check to build

2020-08-05 07:37:57 +00:00

..

doc

TDC register for Minimum ToT

2020-06-02 16:43:24 +00:00

ip_cores

First steps towards integration with David and the TDCs + StMachine.

2014-02-06 08:39:23 +00:00

ipsar_tests/IPSAR_V3

2013-12-09 14:03:29 +00:00

modules

kc705_without_softpll added.

2013-12-06 13:06:15 +00:00

sim

Added IRQ on illegal (ROM) write access of LM32_2nd DPRAM

2019-05-11 10:32:05 +00:00

syn

Added artifact and FPGA constraint check to build

2020-08-05 07:37:57 +00:00

top

FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.

2019-07-19 07:26:59 +00:00

clb.ews.zip

FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.

2019-07-19 07:26:59 +00:00