vincentb.nikhef.nl e992dc0464 Added artifact and FPGA constraint check to build

2020-08-05 07:37:57 +00:00

..

kc705

Removed use of std_logic_arith and cleaned up the design. Design now works using either XST or Precision Synthesis.

2014-08-11 18:42:32 +00:00

kc705_without_softpll

Removed use of std_logic_arith and cleaned up the design. Design now works using either XST or Precision Synthesis.

2014-08-11 18:42:32 +00:00

preserie1

Removed use of std_logic_arith and cleaned up the design. Design now works using either XST or Precision Synthesis.

2014-08-11 18:42:32 +00:00

proto

Rebuild Proto, V2_2 and V2_2_1 (latter including .bin and .mcs)

2014-11-10 13:54:29 +00:00

specials/v2_2_1_lvds

ability to do 'specials'

2019-06-17 13:19:46 +00:00

syn_lm32

First step towards intergration. Connectec clb_wrpc and ipmux. A packet generator generates 5 packets that are received by clb_wrpc and forwarded to ipmux. The frames are received by ipmux which distributes the frames to stream UDP_RX(0 to 3). The last frame has a different destination port number and is forwarded to the "others" stream UDP_RX(4).

2013-09-30 14:33:29 +00:00

v2_2

2015-06-15 13:46:40 +00:00

v2_2_1

Added artifact and FPGA constraint check to build

2020-08-05 07:37:57 +00:00

HowToCreateBinFile.docx

2014-10-30 11:49:00 +00:00