peterj.nikhef.nl 496ca2faac Removed use of std_logic_arith and cleaned up the design. Design now works using either XST or Precision Synthesis. ...

LM32_2nd GPIO now 16 bits wide; used GPIO(8) to enable (or default disable to reduce interference) the test pad drivers (PPS and REF_CLK).

2014-08-11 18:42:32 +00:00

..

bash

Removed use of std_logic_arith and cleaned up the design. Design now works using either XST or Precision Synthesis.

2014-08-11 18:42:32 +00:00

CLBv2_2_top.vhd

added ucf and top file for CLBv2.2

2014-04-04 14:45:37 +00:00

CLBv2_2.ucf

Piezo signals needs lvds_25, now

2014-05-06 15:05:35 +00:00

do_input_file_list.cmd

Removed use of std_logic_arith and cleaned up the design. Design now works using either XST or Precision Synthesis.

2014-08-11 18:42:32 +00:00

do_xilinx.cmd

aes fifo is now a built-in fifo

2014-08-01 10:30:14 +00:00

fpga_bd.bmm

aes fifo is now a built-in fifo

2014-08-01 10:30:14 +00:00

fpga_xst.bmm

ucf modified for the first 22 clb preseries (reset pin swap)

2014-07-30 13:59:22 +00:00

fpga.bit

aes fifo is now a built-in fifo

2014-08-01 10:30:14 +00:00

fpga.ucf

aes fifo is now a built-in fifo

2014-08-01 10:30:14 +00:00

fpga.ut

ucf modified for the first 22 clb preseries (reset pin swap)

2014-07-30 13:59:22 +00:00

fpga.xst

ucf modified for the first 22 clb preseries (reset pin swap)

2014-07-30 13:59:22 +00:00

lm32_empty_memory.ldr

ucf modified for the first 22 clb preseries (reset pin swap)

2014-07-30 13:59:22 +00:00

revisiondate.tcl

ucf modified for the first 22 clb preseries (reset pin swap)

2014-07-30 13:59:22 +00:00