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New Design Review gitified_old_clb_svn/fw/CLBv2_Design/clb/doc/ThermalPictures
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peterj.nikhef.nl 47f6691be8 IPMUX TxFifos (and RxFifo for LM32_2nd) size increased from 512 16bitwords bits to 8192 16bitwords. Changed Fifos and packet buffer into WR inferred fifo and dpram types (no longer using Generic "Vendor" and ipcores directory with coregen wizzard files).
Created Proto, V2_2 and V2_2_1 Tested V2_2_1 in real hardware.
2014-09-15 08:00:29 +00:00
..
CLBv2_2_1_Plus_PBv2_3_Plus_Mushroom
IPMUX TxFifos (and RxFifo for LM32_2nd) size increased from 512 16bitwords bits to 8192 16bitwords. Changed Fifos and packet buffer into WR inferred fifo and dpram types (no longer using Generic "Vendor" and ipcores directory with coregen wizzard files).
2014-09-15 08:00:29 +00:00
CLBv2_Proto
This design implements a packet generator (bunches of 16 UDP packets Ethernet-frame size 170 bytes each @ 25.8 KHz) if dip-5 is set to 'on'.
2014-03-06 09:01:07 +00:00
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