You've already forked gitified_old_clb_svn
431 lines
63 KiB
Tcl
431 lines
63 KiB
Tcl
onerror {resume}
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quietly virtual signal -install /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter { /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/ir(28 downto 13)} insn_cmp_value
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quietly virtual signal -install /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter { /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/ir(12 downto 7)} insn_offset
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quietly virtual signal -install /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0 {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram } aap
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quietly virtual function -install /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0 -env /clb_top_tb { &{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[31], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[30], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[29], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[28], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[27], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[26], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[25], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[24], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[23], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[22], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[21], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[20], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[19], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[18], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[17], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[16], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[15], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[14], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[13], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[12], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[11], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[10], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[9], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[8], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[7], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[6], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[5], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[4], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[3], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[2], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[1], /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram[0] }} aap001
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quietly virtual signal -install /clb_top_tb/u5/u13/wrap_aes/U_Wrapped_aes/Wrapped_aes/U_aes/aes_f/FIFO18E1_inst { /clb_top_tb/u5/u13/wrap_aes/U_Wrapped_aes/Wrapped_aes/U_aes/aes_f/FIFO18E1_inst/DO(15 downto 0)} AES_FIFO_Dout
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quietly virtual signal -install /clb_top_tb/u5/u13/wrap_aes/U_Wrapped_aes/Wrapped_aes/U_aes/aes_f/FIFO18E1_inst { /clb_top_tb/u5/u13/wrap_aes/U_Wrapped_aes/Wrapped_aes/U_aes/aes_f/FIFO18E1_inst/DI(15 downto 0)} AES_FIFO_Din
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider {Config and Reset}
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add wave -noupdate /clb_top_tb/u5/u12/g_simulation
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add wave -noupdate /clb_top_tb/u5/u15/EOS
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add wave -noupdate /clb_top_tb/u5/u15/FLASH_SPI_CCLK
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add wave -noupdate /clb_top_tb/u5/u12/Clk
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add wave -noupdate /clb_top_tb/u5/u12/EOS
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add wave -noupdate /clb_top_tb/u5/u12/O
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add wave -noupdate /clb_top_tb/u5/u12/RESET
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add wave -noupdate /clb_top_tb/u5/u0/U_GTP/clk_gtx_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/mdio_mcr_pdown
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/serdes_rst_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_RX_PCS/phy_rx_clk_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/pcs_reset_n
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/synced
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/sync_lost
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/link_ok
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/link_ok_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/lstat_read_notify
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/mdio_msr_lstatus
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_fromwb.ecr_rx_en_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/rst_n_rx
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/rst_n_rx_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/rst_n_sys
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/rst_n_rx
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/rst_n_ref
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/rst_n_i
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add wave -noupdate -divider {Test PADs}
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add wave -noupdate /clb_top_tb/u5/u17/refclk_driver
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add wave -noupdate /clb_top_tb/u5/u17/pps_p_o
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add wave -noupdate /clb_top_tb/u5/u17/pps_n_o
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add wave -noupdate /clb_top_tb/u5/u17/refclk_p_o
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add wave -noupdate /clb_top_tb/u5/u17/refclk_n_o
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add wave -noupdate -divider General
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add wave -noupdate /clb_top_tb/MGTCLK_P
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add wave -noupdate /clb_top_tb/button1_i
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add wave -noupdate /clb_top_tb/u5/clk_20m_vcxo_n_i
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add wave -noupdate /clb_top_tb/u5/clk_20m_vcxo_p_i
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add wave -noupdate /clb_top_tb/u5/u4/clk20_vcxo_o
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add wave -noupdate /clb_top_tb/u5/u17/ref_clk_locked_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/phy_rst_o
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add wave -noupdate /clb_top_tb/u5/ref_clk_lock
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add wave -noupdate /clb_top_tb/u5/ref_clk_62_5
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add wave -noupdate /clb_top_tb/u5/ref_clk_125
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add wave -noupdate /clb_top_tb/u5/ref_clk_250
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add wave -noupdate /clb_top_tb/u5/ref_clk_250_90
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add wave -noupdate /clb_top_tb/u5/pps
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/tm_cycles
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/tm_tai
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add wave -noupdate /clb_top_tb/u5/tm_time_valid
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add wave -noupdate /clb_top_tb/u5/u14/u6/Tx_Fire
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add wave -noupdate /clb_top_tb/u5/u14/u6/UDP_Tx
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add wave -noupdate /clb_top_tb/u5/u14/u6/WrReq
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add wave -noupdate /clb_top_tb/u5/u14/div_ratio
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add wave -noupdate /clb_top_tb/u5/u14/numpackets
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add wave -noupdate /clb_top_tb/u5/u14/numwords
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add wave -noupdate /clb_top_tb/u5/u14/u6/state_decoding/Cnt
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add wave -noupdate /clb_top_tb/u5/u14/u6/state_decoding/Frame
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add wave -noupdate /clb_top_tb/u5/u0/wrf_snk_i
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add wave -noupdate /clb_top_tb/u5/u0/wrf_snk_o
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add wave -noupdate /clb_top_tb/u5/u0/wrf_src_i
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/state
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add wave -noupdate /clb_top_tb/u5/u0/wrf_src_o
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add wave -noupdate -divider UART-IRQ-Test
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add wave -noupdate /clb_top_tb/u5/USB_RX2
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add wave -noupdate /clb_top_tb/u5/u11/u12/U_Wrapped_UART/wb_int_o
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add wave -noupdate -divider LM32_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/clk_sys_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/rst_n_i
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add wave -noupdate /clb_top_tb/u5/u11/irq_i
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add wave -noupdate -divider Instructions_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/irq_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.cyc
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.stb
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.adr
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.ack
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.we
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(31) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(30) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(29) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(28) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(27) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(26) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(25) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(24) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(23) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(22) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(21) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(20) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(19) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(18) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(17) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(16) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(15) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(14) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(13) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(12) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(11) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(10) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(9) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(8) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(7) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(6) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(5) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(4) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(3) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(2) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(1) -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(0) -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(31) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(30) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(29) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(28) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(27) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(26) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(25) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(24) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(23) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(22) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(21) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(20) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(19) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(18) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(17) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(16) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(15) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(14) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(13) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(12) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(11) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(10) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(9) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(8) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(7) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(6) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(5) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(4) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(3) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(2) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(1) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat(0) {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/lstat_read_notify
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/dwb_o
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/iwb_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_1/ram
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add wave -noupdate -divider Instructions_WRPC
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add wave -noupdate -radix hexadecimal -childformat {{{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[31]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[30]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[29]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[28]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[27]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[26]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[25]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[24]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[23]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[22]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[21]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[20]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[19]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[18]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[17]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[16]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[15]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[14]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[13]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[12]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[11]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[10]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[9]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[8]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[7]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[6]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[5]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[4]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[3]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[2]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[1]} -radix hexadecimal} {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[0]} -radix hexadecimal}} -subitemconfig {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[31]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[30]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[29]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[28]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[27]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[26]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[25]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[24]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[23]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[22]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[21]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[20]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[19]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[18]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[17]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[16]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[15]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[14]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[13]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[12]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[11]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[10]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[9]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[8]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[7]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[6]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[5]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[4]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[3]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[2]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[1]} {-height 15 -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction[0]} {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/valid_d
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/pc_d
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add wave -noupdate -divider MemoryMonitor
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add wave -noupdate -expand /clb_top_tb/u5/u11/MEM_MON/slave_i
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add wave -noupdate /clb_top_tb/u5/u11/MEM_MON/c_lm32_2nd_addr_range
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add wave -noupdate /clb_top_tb/u5/u11/irq_i(9)
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add wave -noupdate -divider WB_CON_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/crossbar/c_address
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/slave_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/slave_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_i_1
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_CON/master_o_1
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add wave -noupdate -divider WB_SECONDARY_CON_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/WB_SECONDARY_CON/crossbar/c_address
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add wave -noupdate -divider DPRAM_WRPC
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add wave -noupdate -expand /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave1_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave1_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave2_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/slave2_o
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add wave -noupdate -divider UART_WRPC
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/clk_sys_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.cyc -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.stb -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.adr -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.sel -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.we -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/uart_rxd_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/slave_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/uart_txd_o
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/rst_n_i
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add wave -noupdate -childformat {{/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_tx_busy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_rx_rdy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.rdr_rx_data_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_tdr_rdy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_data_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_rdy_i -radix hexadecimal} {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_count_i -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_tx_busy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.sr_rx_rdy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.rdr_rx_data_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_tdr_rdy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_data_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_rdy_i {-height 15 -radix hexadecimal} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in.host_rdr_count_i {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u0/U_WR_CORE/WRPC/PERIPH/UART/U_Wrapped_UART/regs_in
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add wave -noupdate -divider LM32_2nd
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/clk_sys_i
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/rst_n_i
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add wave -noupdate -divider Instructions_2nd
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/irq_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.cyc
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.stb
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.adr
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_i.ack
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/iwb_o.we
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(31) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(30) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(29) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(28) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(27) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(26) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(25) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(24) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(23) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(22) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(21) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(20) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(19) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(18) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(17) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(16) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(15) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(14) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(13) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(12) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(11) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(10) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(9) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(8) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(7) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(6) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(5) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(4) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(3) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(2) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(1) -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(0) -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(31) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(30) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(29) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(28) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(27) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(26) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(25) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(24) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(23) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(22) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(21) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(20) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(19) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(18) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(17) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(16) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(15) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(14) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(13) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(12) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(11) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(10) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(9) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(8) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(7) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(6) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(5) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(4) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(3) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(2) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(1) {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat(0) {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/dwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/dwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/dwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/dwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/dwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/dwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/dwb_o
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/iwb_i.ack -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.err -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.rty -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.stall -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.int -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/iwb_i.ack {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.err {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.rty {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.stall {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.int {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/iwb_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/LM32_CORE/iwb_o.cyc -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.stb -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.adr -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.sel -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.we -radix hexadecimal} {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/LM32_CORE/iwb_o.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/LM32_CORE/iwb_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/LM32_CORE/iwb_o
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_0/ram
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/reg_1/ram
|
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add wave -noupdate -divider Instructions_2nd
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/decoder/instruction
|
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add wave -noupdate /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/valid_d
|
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/LM32_CORE/gen_profile_medium_icache_debug/U_Wrapped_LM32/cpu/instruction_unit/pc_d
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add wave -noupdate -divider WB_CON_2nd
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/crossbar/c_address
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/slave_i
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/slave_o
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/master_i
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/master_o
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/master_i_1
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add wave -noupdate /clb_top_tb/u5/u11/WB_CON/master_o_1
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add wave -noupdate -divider WB_SECONDARY_CON_2nd
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add wave -noupdate /clb_top_tb/u5/u11/WB_SECONDARY_CON/crossbar/c_address
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add wave -noupdate -divider DPRAM_2nd
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave1_i
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave1_o
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave2_i
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add wave -noupdate /clb_top_tb/u5/u11/DPRAM/slave2_o
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add wave -noupdate -divider UART_2nd
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add wave -noupdate /clb_top_tb/u5/u11/u12/clk_sys_i
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add wave -noupdate -radix hexadecimal -childformat {{/clb_top_tb/u5/u11/u12/slave_i.cyc -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.stb -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.adr -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.sel -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.we -radix hexadecimal} {/clb_top_tb/u5/u11/u12/slave_i.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u11/u12/slave_i.cyc {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.stb {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.sel {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.we {-height 15 -radix hexadecimal} /clb_top_tb/u5/u11/u12/slave_i.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u11/u12/slave_i
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add wave -noupdate /clb_top_tb/u5/u11/u12/uart_rxd_i
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add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u11/u12/slave_o
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add wave -noupdate /clb_top_tb/u5/u11/u12/uart_txd_o
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add wave -noupdate /clb_top_tb/u5/u11/u12/rst_n_i
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add wave -noupdate /clb_top_tb/u5/u11/u12/U_Wrapped_UART/regs_in
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add wave -noupdate -divider {TransmitFrame 16 Bit}
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add wave -noupdate /clb_top_tb/u2/Clk
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add wave -noupdate /clb_top_tb/u2/tx_data_swap
|
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add wave -noupdate /clb_top_tb/u2/Rx_Fire
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add wave -noupdate /clb_top_tb/u2/Rx_CRC_Err
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add wave -noupdate /clb_top_tb/u2/TxCharIsK
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add wave -noupdate /clb_top_tb/u2/TxData
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add wave -noupdate /clb_top_tb/u2/state
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add wave -noupdate /clb_top_tb/u2/CRCOut
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add wave -noupdate -divider {IPMUX PauseReqLogic}
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add wave -noupdate /clb_top_tb/u5/u5/u6/u2/PauseAck
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u2/PauseReq
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u6/u2/PauseVal
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u2/WaterMarkHigh
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u2/WaterMarkLow
|
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add wave -noupdate -divider FirePackets
|
|
add wave -noupdate /clb_top_tb/u5/u14/udp_tstgen_cont
|
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add wave -noupdate /clb_top_tb/u5/u14/u6/Tx_Fire
|
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add wave -noupdate /clb_top_tb/u5/u14/u1/div_ratio
|
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add wave -noupdate -divider wrf_mux_input
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_snk_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_snk_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_src_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/ep_src_o
|
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add wave -noupdate -divider wrf_mux_output
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_class_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_snk_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_snk_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_WBP_MUX/mux_src_o
|
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add wave -noupdate -divider WRF
|
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add wave -noupdate /clb_top_tb/u5/u0/wrf_snk_i
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add wave -noupdate /clb_top_tb/u5/u0/wrf_snk_o
|
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add wave -noupdate /clb_top_tb/u5/u0/wrf_src_i
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add wave -noupdate /clb_top_tb/u5/u0/wrf_src_o
|
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add wave -noupdate -divider WOL
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add wave -noupdate /clb_top_tb/u5/u0/U_GTP/rx_rbclk_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_GTP/rx_data_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_GTP/rx_k16_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_GTP/rx_k_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WOL/mac
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WOL/Rst
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WOL/rx_data_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WOL/rx_k16_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WOL/rx_k_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WOL/rx_rbclk_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WOL/state
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WOL/wol_n_o
|
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add wave -noupdate /clb_top_tb/u5/SUICIDE_FPGA
|
|
add wave -noupdate -divider ipmux_wrf_src
|
|
add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Clk
|
|
add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Din
|
|
add wave -noupdate /clb_top_tb/u5/u5/u0/u3/EOP
|
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Empty
|
|
add wave -noupdate /clb_top_tb/u5/u5/u0/u3/Offset
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u0/u3/PktPtr
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u0/u3/PktRdPtr
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u0/u3/RdAddr
|
|
add wave -noupdate /clb_top_tb/u5/u5/u0/u3/state
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u0/u3/src_o.adr -radix hexadecimal} {/clb_top_tb/u5/u5/u0/u3/src_o.dat -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u5/u0/u3/src_o.adr {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u0/u3/src_o.dat {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u0/u3/src_o
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add wave -noupdate /clb_top_tb/u5/u5/u0/u3/src_i
|
|
add wave -noupdate -divider ReceivedInTestbench_PHY
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u1/rx_k_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u1/rx_data_o
|
|
add wave -noupdate /clb_top_tb/u1/rx_rbclk_o
|
|
add wave -noupdate -divider Debug
|
|
add wave -noupdate /clb_top_tb/u2/Rx_Fire
|
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add wave -noupdate /clb_top_tb/u2/TxCharIsK
|
|
add wave -noupdate /clb_top_tb/u2/TxData
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/link_ok
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/synced
|
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add wave -noupdate -divider ep_rx_path
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/g_rx_buffer_size
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/g_with_dpi_classifier
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/g_with_rtu
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/g_with_rx_buffer
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/g_with_vlans
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/regs_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/clk_sys_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/clk_rx_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/rst_n_sys_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/rst_n_rx_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pcs_fab_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_hp
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/ematch_is_pause
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/done_int
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/ematch_done
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/done_int
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
|
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add wave -noupdate -divider MicroCodeRAM
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/rst_n_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/clka_i
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/aa_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/wea_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/bwea_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/da_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/qa_o
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/clkb_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/ab_i
|
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add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/web_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/bweb_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/db_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter/U_packet_filter/U_microcode_ram/qb_o
|
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add wave -noupdate -divider EndPoint
|
|
add wave -noupdate -expand /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_fromwb
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/phy_rx_data_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/phy_rx_clk_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/phy_rx_k_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/phy_rx_enc_err_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/phy_rx_bitslide_i
|
|
add wave -noupdate -divider ipmux_wrf_snk
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Clk
|
|
add wave -noupdate -expand /clb_top_tb/u5/u5/u6/u1/snk_i
|
|
add wave -noupdate /clb_top_tb/u5/u5/u6/u1/We_Int
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/snk_o
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/rd_req
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/stall_int
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/q_adr_p1
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/q_data_p1
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/q_valid_p1
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/snk_valid
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/adr_change
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/eocycle
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/shift_pipeline
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/good_frame
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/bad_frame
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Dout
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/EOF
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Full
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/Offset
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/OverFlow
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/PktPtr
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/PktWrPtr
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/We
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/WrAddr
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/abits
|
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add wave -noupdate /clb_top_tb/u5/u5/u6/u1/snk_cyc_d0
|
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add wave -noupdate -divider IPMUX
|
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add wave -noupdate /clb_top_tb/u5/u5/Rst
|
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add wave -noupdate /clb_top_tb/u5/u5/WrClk
|
|
add wave -noupdate -expand /clb_top_tb/u5/u5/WrReq
|
|
add wave -noupdate /clb_top_tb/u5/u5/Full
|
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add wave -noupdate -expand -subitemconfig {/clb_top_tb/u5/u5/Tx(3) -expand /clb_top_tb/u5/u5/Tx(1) -expand} /clb_top_tb/u5/u5/Tx
|
|
add wave -noupdate /clb_top_tb/u5/u5/RdClk
|
|
add wave -noupdate /clb_top_tb/u5/u5/RdReq
|
|
add wave -noupdate /clb_top_tb/u5/u5/Empty
|
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add wave -noupdate /clb_top_tb/u5/u5/Rx
|
|
add wave -noupdate /clb_top_tb/u5/u5/u1/RdReqin
|
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add wave -noupdate /clb_top_tb/u5/u5/u1/Dout
|
|
add wave -noupdate /clb_top_tb/u5/u5/u1/Validout
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/Flush
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/RdClk
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/RdReq
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/TXi
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/WrClk
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/WrReq
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/Full
|
|
add wave -noupdate -expand -subitemconfig {/clb_top_tb/u5/u5/u8/TXo(3) -expand} /clb_top_tb/u5/u5/u8/TXo
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/Valid
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/Packet_RdReq
|
|
add wave -noupdate /clb_top_tb/u5/u5/u1/Stream
|
|
add wave -noupdate /clb_top_tb/u5/u5/u1/ConnectReq
|
|
add wave -noupdate /clb_top_tb/u5/u5/u1/Connected
|
|
add wave -noupdate /clb_top_tb/u5/u5/u1/Packet
|
|
add wave -noupdate /clb_top_tb/u5/u5/u8/PacketsDone
|
|
add wave -noupdate /clb_top_tb/u5/u5/u1/TxStreamDebug
|
|
add wave -noupdate -divider ep_tx_framer
|
|
add wave -noupdate -expand /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/pcs_fab_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/pcs_dreq_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/pcs_busy_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/pcs_error_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_cyc_d0
|
|
add wave -noupdate -expand /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/sof_p1
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/sof_p1_latch
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/eof_p1
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/eof_p1_latch
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ack_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ack_latch
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/state
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/counter
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/q_valid
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/write_mask
|
|
add wave -noupdate -divider PHY
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/mdio_mcr_pdown
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/pcs_reset_n
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/serdes_rst_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_GTP/rx_k_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_GTP/rx_data_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_RX_PCS/an_rx_val_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_RX_PCS/an_rx_valid_o
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_GTP/tx_k_i
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_GTP/tx_data_i
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_val_i
|
|
add wave -noupdate /clb_top_tb/u5/u0/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit/U_TX_PCS/an_tx_en_i
|
|
add wave -noupdate -divider ipmux_Registers
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/Clk
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/Rst
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/wb_ipmux_reg_i
|
|
add wave -noupdate /clb_top_tb/u5/u5/u4/wb_ipmux_reg_o
|
|
add wave -noupdate -childformat {{/clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Mod -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Srv -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.IP_Mod -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.IP_Srv -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.UDP_SrvPrt -radix hexadecimal} {/clb_top_tb/u5/u5/u4/eth_regs_o.UDP_ModPrt -radix hexadecimal}} -subitemconfig {/clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Mod {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.MAC_Srv {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.IP_Mod {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.IP_Srv {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.UDP_SrvPrt {-height 15 -radix hexadecimal} /clb_top_tb/u5/u5/u4/eth_regs_o.UDP_ModPrt {-height 15 -radix hexadecimal}} /clb_top_tb/u5/u5/u4/eth_regs_o
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/IP_Mod
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/IP_Srv
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/MAC_Mod
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/MAC_Srv
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/UDP_ModPrt
|
|
add wave -noupdate -radix hexadecimal /clb_top_tb/u5/u5/u4/UDP_SrvPrt
|
|
add wave -noupdate -divider EOS
|
|
add wave -noupdate /clb_top_tb/u5/u12/Clk
|
|
add wave -noupdate /clb_top_tb/u5/u12/EOS
|
|
add wave -noupdate /clb_top_tb/u5/u12/O
|
|
add wave -noupdate /clb_top_tb/u5/u12/O_n
|
|
add wave -noupdate /clb_top_tb/u5/u12/RESET
|
|
add wave -noupdate /clb_top_tb/u5/u12/g_simulation
|
|
add wave -noupdate /clb_top_tb/u5/u12/tc
|
|
add wave -noupdate -divider TDC
|
|
add wave -noupdate /clb_top_tb/u5/u8/Rst
|
|
add wave -noupdate /clb_top_tb/u5/u8/rst_n_i
|
|
add wave -noupdate /clb_top_tb/u5/u8/ref_clk_lock
|
|
add wave -noupdate /clb_top_tb/u5/u8/ref_clk_62_5
|
|
add wave -noupdate /clb_top_tb/u5/u8/ref_clk_250
|
|
add wave -noupdate /clb_top_tb/u5/u8/ref_clk_250_90
|
|
add wave -noupdate /clb_top_tb/u5/u8/clk_sys_i
|
|
add wave -noupdate /clb_top_tb/u5/u8/download
|
|
add wave -noupdate /clb_top_tb/u5/u8/enable
|
|
add wave -noupdate /clb_top_tb/u5/u8/flush
|
|
add wave -noupdate /clb_top_tb/u5/u8/internal_tdc_in
|
|
add wave -noupdate /clb_top_tb/u5/u8/r_enable_tdc_ch
|
|
add wave -noupdate /clb_top_tb/u5/u8/r_veto_value
|
|
add wave -noupdate /clb_top_tb/u5/u8/s
|
|
add wave -noupdate /clb_top_tb/u5/u8/s_hits
|
|
add wave -noupdate /clb_top_tb/u5/u8/s_n
|
|
add wave -noupdate /clb_top_tb/u5/u8/ss_test
|
|
add wave -noupdate /clb_top_tb/u5/u8/tdc_o
|
|
add wave -noupdate /clb_top_tb/u5/u8/time_offset
|
|
add wave -noupdate /clb_top_tb/u5/u8/timeslice_start
|
|
add wave -noupdate /clb_top_tb/u5/u8/wb_tdc_i
|
|
add wave -noupdate /clb_top_tb/u5/u8/wb_tdc_o
|
|
TreeUpdate [SetDefaultTree]
|
|
WaveRestoreCursors {{Cursor 8} {10431943 ps} 0} {{Cursor 3} {208972100 ps} 1} {{Cursor 4} {403532100 ps} 1}
|
|
quietly wave cursor active 1
|
|
configure wave -namecolwidth 505
|
|
configure wave -valuecolwidth 141
|
|
configure wave -justifyvalue left
|
|
configure wave -signalnamewidth 0
|
|
configure wave -snapdistance 10
|
|
configure wave -datasetprefix 0
|
|
configure wave -rowmargin 4
|
|
configure wave -childrowmargin 2
|
|
configure wave -gridoffset 0
|
|
configure wave -gridperiod 1
|
|
configure wave -griddelta 40
|
|
configure wave -timeline 0
|
|
configure wave -timelineunits ns
|
|
update
|
|
WaveRestoreZoom {0 ps} {194822650 ps}
|