gitified_old_clb_svn

Files

New Design Review

peterj.nikhef.nl 2c7ebd9a93 FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.

2019-07-19 07:26:59 +00:00

clb_top_tb.vhd

FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.

2019-07-19 07:26:59 +00:00

fpga.vhd

FPGA Corruption NRB (a.k.a LM32_2nd ROM bitflip issue); added (static) DPRAM buserr monitor IRQ; added ref_clk_lock synchronization FF's; re-ordered MCH states (VETO Status); added LVDS pullup/down.

2019-07-19 07:26:59 +00:00

README.txt

Added aes and tdc files to the CLBv2 project. State machine is still empty so aes and tdc are largely optimized away!

2014-02-17 10:15:11 +00:00

README.txt

File description:

clb_top_tb.vhd	the testbench of clb_top. To be used for simulation.
fpga.vhd		the file to used for synthesis in the CLBv2-Proto FPGA for test purposes


modules:
	

Lower level modules:


Note that these files are generated by EASE.