peterj.nikhef.nl 5619bfd538 IPMUX TX input fifos are now split into a data fifo and an End Of Data fifo. The latter shows the availability of a complete packet in the data fifo. w This solves blocking of other input streams (due to a connect to a stream for which the header is initiated but the tail is kept until the next time slice). Added some extra bits "packet available" in the Tx Stream Select register and added CPU_Req and CPU_Gnt pins on the FMC Test Connector.

2014-09-17 13:44:36 +00:00

..

ipmux.lib

IPMUX TX input fifos are now split into a data fifo and an End Of Data fifo. The latter shows the availability of a complete packet in the data fifo. w This solves blocking of other input streams (due to a connect to a stream for which the header is initiated but the tail is kept until the next time slice). Added some extra bits "packet available" in the Tx Stream Select register and added CPU_Req and CPU_Gnt pins on the FMC Test Connector.

2014-09-17 13:44:36 +00:00

test_scripts

removed superfluous Start Of Packet / Start Of Data wherever it was still used in ipmux.ews.zip

2013-11-22 17:12:49 +00:00

modelsim.ini

Used the p:\RnD_Projecten\SPIDR\MPX3\Designs\mpx3_mpx3rx\ design as a starting point.

2013-08-05 09:08:33 +00:00

Questa Sim_10.2a.lnk

Used the p:\RnD_Projecten\SPIDR\MPX3\Designs\mpx3_mpx3rx\ design as a starting point.

2013-08-05 09:08:33 +00:00

VCom_Functional.tcl

IPMUX TxFifos (and RxFifo for LM32_2nd) size increased from 512 16bitwords bits to 8192 16bitwords. Changed Fifos and packet buffer into WR inferred fifo and dpram types (no longer using Generic "Vendor" and ipcores directory with coregen wizzard files).

2014-09-15 08:00:29 +00:00

VSim_Current_Revision.tcl

Used the p:\RnD_Projecten\SPIDR\MPX3\Designs\mpx3_mpx3rx\ design as a starting point.

2013-08-05 09:08:33 +00:00

VSim_Functional.tcl

IPMUX TxFifos (and RxFifo for LM32_2nd) size increased from 512 16bitwords bits to 8192 16bitwords. Changed Fifos and packet buffer into WR inferred fifo and dpram types (no longer using Generic "Vendor" and ipcores directory with coregen wizzard files).

2014-09-15 08:00:29 +00:00

wave.tcl

IPMUX TX input fifos are now split into a data fifo and an End Of Data fifo. The latter shows the availability of a complete packet in the data fifo. w This solves blocking of other input streams (due to a connect to a stream for which the header is initiated but the tail is kept until the next time slice). Added some extra bits "packet available" in the Tx Stream Select register and added CPU_Req and CPU_Gnt pins on the FMC Test Connector.

2014-09-17 13:44:36 +00:00