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New Design Review gitified_old_clb_svn/fw/TestDesigns/KC705_ReFClkAndPPS
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peterj.nikhef.nl 0bb580be08 added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)
2014-02-26 14:11:22 +00:00
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sim
added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)
2014-02-26 14:11:22 +00:00
syn
added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)
2014-02-26 14:11:22 +00:00
top
added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)
2014-02-26 14:11:22 +00:00
kc705_refclk_and_pps.ews.zip
added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)
2014-02-26 14:11:22 +00:00
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