peterj.nikhef.nl 0bb580be08 added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

..

_.imp

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

do_impact.cmd

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

do_syn.cmd

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

do_xilinx.cmd

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

FPGA_impact.log

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

fpga_syn.log

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

fpga-syn.tcl

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

fpga-xilinx.log

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

fpga.bit

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

fpga.ucf

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00

fpga.ut

added simple KC705+SoftPLL design to generate a 10 MHz (SoftPLL-FMC Lemo J6) and PPS (SoftPLL-FMC Lemo J5) signal from a 10 MHz reference (Input on J6 of the KC705)

2014-02-26 14:11:22 +00:00