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30 lines
713 B
Tcl
30 lines
713 B
Tcl
# fpga-synt.tcl 7-Jun-2013
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new_project -name refclk_and_pps -folder . -force
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#source revisiondate.tcl
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new_impl -name impl -force
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add_input_file ../top/fpga.vhd
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# KC705
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setup_design -manufacturer Xilinx -family KINTEX-7 -part 7K325TFFG900 -speed -2
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# CLBv2 Proto equipped with 7K160 (speed grade -1 has lowest performance)
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#setup_design -manufacturer Xilinx -family KINTEX-7 -part 7K160TFBG676 -speed -1
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# CLBv2 Proto equipped with 7K325 (speed grade -1 has lowest performance)
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#setup_design -manufacturer Xilinx -family KINTEX-7 -part 7K325TFBG676 -speed -2
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setup_design -max_fanout=10000
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setup_design -design fpga
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compile
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synthesize
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report_area
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save_impl
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close_project
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