gitified_old_clb_svn/fw/TestDesigns/KC705_ReFClkAndPPS/top/fpga.vhd

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--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
--
-- Ease library  : design
-- HDL library   : work
-- Host name     : SERING
-- User name     : peterj
-- Time stamp    : Tue Jan 21 15:22:41 2014
--
-- Designed by   : 
-- Company       : HDL Works
-- Project info  : 
--
--------------------------------------------------------------------------------

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-- Object        : Entity design.DiffIn
-- Last modified : Tue Jan 21 15:20:01 2014.
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library ieee, UNISIM;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use UNISIM.VCOMPONENTS.all;

entity DiffIn is
  port(
    REFCLK           : out    std_logic;
    SMA_MGT_REFCLK_N : in     std_logic;
    SMA_MGT_REFCLK_P : in     std_logic);
end entity DiffIn;

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-- Object        : Architecture design.DiffIn.rtl
-- Last modified : Tue Jan 21 15:20:01 2014.
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architecture rtl of DiffIn is
  Signal RefClk_GTE2: std_logic;
begin
   ibufds_gte2_ref_clk: IBUFDS_GTE2
   generic map(
     CLKCM_CFG      => True,
	 CLKRCV_TRST    => True,
	 CLKSWING_CFG   => "11")
   port map(
     CEB   => '0',
	 I     => SMA_MGT_REFCLK_P,
     IB    => SMA_MGT_REFCLK_N,
     O     => RefClk_GTE2,
	 ODIV2 => open);

   -- ibufds_ref_clk: IBUFGDS
   -- generic map(
     -- CAPACITANCE      => "DONT_CARE",
	 -- DIFF_TERM        => False,
	 -- IBUF_DELAY_VALUE => "0",
	 -- IBUF_LOW_PWR     => True,
	 -- IOSTANDARD       => "DEFAULT")
   -- port map(
	 -- I     => SMA_MGT_REFCLK_P,
     -- IB    => SMA_MGT_REFCLK_N,
     -- O     => RefClk_GTE2);

   bufg_ref_clk: BUFG
   port map(
	 I     => RefClk_GTE2,
     O     => REFCLK);

	 
end architecture rtl ; -- of DiffIn

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-- Object        : Entity design.DiffOut
-- Last modified : Tue Jan 21 14:13:32 2014.
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library ieee, UNISIM;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use UNISIM.VCOMPONENTS.all;

entity DiffOut is
  port(
    PPS      : in     std_logic;
    PPS_N    : out    std_logic;
    PPS_P    : out    std_logic;
    REFCLK   : in     std_logic;
    REFCLK_N : out    std_logic;
    REFCLK_P : out    std_logic);
end entity DiffOut;

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-- Object        : Architecture design.DiffOut.rtl
-- Last modified : Tue Jan 21 14:13:32 2014.
--------------------------------------------------------------------------------


architecture rtl of DiffOut is

begin
   obuf_ref_clk: OBUFDS
   generic map(
     CAPACITANCE => "DONT_CARE",
     IOSTANDARD  => "DEFAULT",
     SLEW        => "SLOW")
   port map(
     O  => REFCLK_P,
     OB => REFCLK_N,
     I  => REFCLK);

   obuf_pps: OBUFDS
   generic map(
     CAPACITANCE => "DONT_CARE",
     IOSTANDARD  => "DEFAULT",
     SLEW        => "SLOW")
   port map(
     O  => PPS_P,
     OB => PPS_N,
     I  => PPS);

end architecture rtl ; -- of DiffOut

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-- Object        : Entity design.PPS_Divider
-- Last modified : Tue Jan 21 15:22:40 2014.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity PPS_Divider is
  port(
    Clk : in     std_logic;
    PPS : out    std_logic);
end entity PPS_Divider;

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-- Object        : Architecture design.PPS_Divider.rtl
-- Last modified : Tue Jan 21 15:22:40 2014.
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architecture rtl of PPS_Divider is

begin
   Process (Clk)
      Variable Count: Unsigned(31 downto 0) := (Others => '0');
   Begin       
      If Rising_Edge(Clk) Then
		 If count = 9999999 then
            Count := (others => '0');
		 else
		    Count := Count + 1;
         end if;
      End If;

     If count > 0 and Count <= 1000 then
            PPS <= '1';
		 else
            PPS <= '0';
         end if;
   End Process;

end architecture rtl ; -- of PPS_Divider

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-- Object        : Entity design.fpga
-- Last modified : Tue Jan 21 15:11:19 2014.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fpga is
  port(
    OE0_N            : out    std_logic;
    PPS_N            : out    std_logic;
    PPS_P            : out    std_logic;
    REFCLK_N         : out    std_logic;
    REFCLK_P         : out    std_logic;
    SMA_MGT_REFCLK_N : in     std_logic;
    SMA_MGT_REFCLK_P : in     std_logic);
end entity fpga;

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-- Object        : Architecture design.fpga.a0
-- Last modified : Tue Jan 21 15:11:19 2014.
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architecture a0 of fpga is

  signal PPS    : std_logic;
  signal REFCLK : std_logic;

  component PPS_Divider
    port(
      Clk : in     std_logic;
      PPS : out    std_logic);
  end component PPS_Divider;

  component DiffOut
    port(
      PPS      : in     std_logic;
      PPS_N    : out    std_logic;
      PPS_P    : out    std_logic;
      REFCLK   : in     std_logic;
      REFCLK_N : out    std_logic;
      REFCLK_P : out    std_logic);
  end component DiffOut;

  component DiffIn
    port(
      REFCLK           : out    std_logic;
      SMA_MGT_REFCLK_N : in     std_logic;
      SMA_MGT_REFCLK_P : in     std_logic);
  end component DiffIn;

begin
  --Kintex-7 evaluation board KC705
  --J16 SMA_MGT_REFCLK_P (FPGA pin J8)
  --J15 SMA_MGT_REFCLK_N (FPGA pin J7)
  OE0_N <= '0';
  u1: PPS_Divider
    port map(
      Clk => REFCLK,
      PPS => PPS);

  u0: DiffOut
    port map(
      PPS      => PPS,
      PPS_N    => PPS_N,
      PPS_P    => PPS_P,
      REFCLK   => REFCLK,
      REFCLK_N => REFCLK_N,
      REFCLK_P => REFCLK_P);

  u2: DiffIn
    port map(
      REFCLK           => REFCLK,
      SMA_MGT_REFCLK_N => SMA_MGT_REFCLK_N,
      SMA_MGT_REFCLK_P => SMA_MGT_REFCLK_P);

end architecture a0 ; -- of fpga