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New Design Review gitified_old_clb_svn/fw/TestDesigns/KC705_ReFClkAndPPS/top/system.vhd

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--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
--
-- Ease library : design
-- HDL library : work
-- Host name : SERING
-- User name : peterj
-- Time stamp : Tue Jan 21 14:38:39 2014
--
-- Designed by :
-- Company : HDL Works
-- Project info :
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Object : Entity design.ClkRstGen
-- Last modified : Tue Jan 21 11:55:18 2014.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ClkRstGen is
port(
Rst : out std_logic;
USER_CLK_N : buffer std_logic;
USER_CLK_P : buffer std_logic);
end entity ClkRstGen;
--------------------------------------------------------------------------------
-- Object : Architecture design.ClkRstGen.rtl
-- Last modified : Tue Jan 21 11:55:18 2014.
--------------------------------------------------------------------------------
architecture rtl of ClkRstGen is
-- 100 ns equals 10.0 MHz
Constant ClockPeriod: Time := 100 ns;
begin
Process
Begin
If now = 0 ns Then
Rst <= '1', '0' After 1 us;
USER_CLK_P <= '0';
USER_CLK_N <= '1';
Else
USER_CLK_P <= not USER_CLK_P;
USER_CLK_N <= not USER_CLK_N;
End If;
Wait for ClockPeriod / 2;
End Process;
end architecture rtl ; -- of ClkRstGen
--------------------------------------------------------------------------------
-- Object : Entity design.DiffIn
-- Last modified : Tue Jan 21 14:35:53 2014.
--------------------------------------------------------------------------------
library ieee, UNISIM;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use UNISIM.VCOMPONENTS.all;
entity DiffIn is
port(
REFCLK : out std_logic;
SMA_MGT_REFCLK_N : in std_logic;
SMA_MGT_REFCLK_P : in std_logic);
end entity DiffIn;
--------------------------------------------------------------------------------
-- Object : Architecture design.DiffIn.rtl
-- Last modified : Tue Jan 21 14:35:53 2014.
--------------------------------------------------------------------------------
architecture rtl of DiffIn is
Signal RefClk_GTE2: std_logic;
begin
ibufds_gte2_ref_clk: IBUFDS_GTE2
generic map(
CLKCM_CFG => True,
CLKRCV_TRST => True,
CLKSWING_CFG => "11")
port map(
CEB => '0',
I => SMA_MGT_REFCLK_P,
IB => SMA_MGT_REFCLK_N,
O => RefClk_GTE2,
ODIV2 => open);
bufg_ref_clk: BUFG
port map(
I => RefClk_GTE2,
O => REFCLK);
end architecture rtl ; -- of DiffIn
--------------------------------------------------------------------------------
-- Object : Entity design.DiffOut
-- Last modified : Tue Jan 21 14:13:32 2014.
--------------------------------------------------------------------------------
library ieee, UNISIM;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use UNISIM.VCOMPONENTS.all;
entity DiffOut is
port(
PPS : in std_logic;
PPS_N : out std_logic;
PPS_P : out std_logic;
REFCLK : in std_logic;
REFCLK_N : out std_logic;
REFCLK_P : out std_logic);
end entity DiffOut;
--------------------------------------------------------------------------------
-- Object : Architecture design.DiffOut.rtl
-- Last modified : Tue Jan 21 14:13:32 2014.
--------------------------------------------------------------------------------
architecture rtl of DiffOut is
begin
obuf_ref_clk: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => REFCLK_P,
OB => REFCLK_N,
I => REFCLK);
obuf_pps: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => PPS_P,
OB => PPS_N,
I => PPS);
end architecture rtl ; -- of DiffOut
--------------------------------------------------------------------------------
-- Object : Entity design.PPS_Divider
-- Last modified : Tue Jan 21 13:32:56 2014.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PPS_Divider is
port(
Clk : in std_logic;
PPS : out std_logic);
end entity PPS_Divider;
--------------------------------------------------------------------------------
-- Object : Architecture design.PPS_Divider.rtl
-- Last modified : Tue Jan 21 13:32:56 2014.
--------------------------------------------------------------------------------
architecture rtl of PPS_Divider is
begin
Process (Clk)
Variable Count: Unsigned(31 downto 0) := (Others => '0');
Begin
If Rising_Edge(Clk) Then
If count = 9999999 then
Count := (others => '0');
else
Count := Count + 1;
end if;
End If;
If count > 0 and Count <= 100 then
PPS <= '1';
else
PPS <= '0';
end if;
End Process;
end architecture rtl ; -- of PPS_Divider
--------------------------------------------------------------------------------
-- Object : Entity design.fpga
-- Last modified : Tue Jan 21 14:35:52 2014.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpga is
port(
PPS_N : out std_logic;
PPS_P : out std_logic;
REFCLK_N : out std_logic;
REFCLK_P : out std_logic;
SMA_MGT_REFCLK_N : in std_logic;
SMA_MGT_REFCLK_P : in std_logic);
end entity fpga;
--------------------------------------------------------------------------------
-- Object : Architecture design.fpga.a0
-- Last modified : Tue Jan 21 14:35:52 2014.
--------------------------------------------------------------------------------
architecture a0 of fpga is
signal PPS : std_logic;
signal REFCLK : std_logic;
component PPS_Divider
port(
Clk : in std_logic;
PPS : out std_logic);
end component PPS_Divider;
component DiffOut
port(
PPS : in std_logic;
PPS_N : out std_logic;
PPS_P : out std_logic;
REFCLK : in std_logic;
REFCLK_N : out std_logic;
REFCLK_P : out std_logic);
end component DiffOut;
component DiffIn
port(
REFCLK : out std_logic;
SMA_MGT_REFCLK_N : in std_logic;
SMA_MGT_REFCLK_P : in std_logic);
end component DiffIn;
begin
--Kintex-7 evaluation board KC705
--J16 SMA_MGT_REFCLK_P (FPGA pin J8)
--J15 SMA_MGT_REFCLK_N (FPGA pin J7)
u1: PPS_Divider
port map(
Clk => REFCLK,
PPS => PPS);
u0: DiffOut
port map(
PPS => PPS,
PPS_N => PPS_N,
PPS_P => PPS_P,
REFCLK => REFCLK,
REFCLK_N => REFCLK_N,
REFCLK_P => REFCLK_P);
u2: DiffIn
port map(
REFCLK => REFCLK,
SMA_MGT_REFCLK_N => SMA_MGT_REFCLK_N,
SMA_MGT_REFCLK_P => SMA_MGT_REFCLK_P);
end architecture a0 ; -- of fpga
--------------------------------------------------------------------------------
-- Object : Entity design.System
-- Last modified : Tue Jan 21 14:30:17 2014.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity System is
end entity System;
--------------------------------------------------------------------------------
-- Object : Architecture design.System.a0
-- Last modified : Tue Jan 21 14:30:17 2014.
--------------------------------------------------------------------------------
architecture a0 of System is
signal Rst : std_logic;
signal USER_CLK_P : std_logic;
signal USER_CLK_N : std_logic;
component fpga
port(
PPS_N : out std_logic;
PPS_P : out std_logic;
REFCLK_N : out std_logic;
REFCLK_P : out std_logic;
SMA_MGT_REFCLK_N : in std_logic;
SMA_MGT_REFCLK_P : in std_logic);
end component fpga;
component ClkRstGen
port(
Rst : out std_logic;
USER_CLK_N : buffer std_logic;
USER_CLK_P : buffer std_logic);
end component ClkRstGen;
begin
u0: fpga
port map(
PPS_N => open,
PPS_P => open,
REFCLK_N => open,
REFCLK_P => open,
SMA_MGT_REFCLK_N => USER_CLK_N,
SMA_MGT_REFCLK_P => USER_CLK_P);
u2: ClkRstGen
port map(
Rst => Rst,
USER_CLK_N => USER_CLK_N,
USER_CLK_P => USER_CLK_P);
end architecture a0 ; -- of System
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