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NoIndexTests/gitified_old_clb_svn

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New Design Review

History

aorzelli.ge.infn.it 962b81d264 added v2_2 folder

2014-12-03 10:16:10 +00:00

..

copy of Uart_output_genova in Uart_ethernet_dataout

2013-12-10 15:00:10 +00:00

Changed aes module and susm module, to support new data format

2014-04-16 09:32:55 +00:00

Changed aes module and susm module, to support new data format

2014-04-16 09:32:55 +00:00

added v2_2 folder

2014-12-03 10:16:10 +00:00

adapted to clbv2.2

2014-05-23 12:10:35 +00:00

README

copy of Uart_output_genova in Uart_ethernet_dataout

2013-12-10 15:00:10 +00:00

README

V. Kulikovskiy
20/09/2013 changes:
After Peter updated *cmd scripts and fpga.vhd file some additional changes were done in order to make it compile under linux:
1) softpll modules were added to do_input_files.sh 
2) UNISIM and GTE2 libraries input were commented in fpga.vhd