21 lines
1.2 KiB
Markdown
Executable File
21 lines
1.2 KiB
Markdown
Executable File
# uob-hep-pc072
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DUNE Timing System MicroTCA Interface Board(MIB).
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Schematic capture in Cadence DE-HDL. PCB Layout in Cadence Allegro.
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Design files for the current (v3) board at https://github.com/uob-hep-cad/uob-hep-pc072/tree/main/hardware/Cadence/top/mtca_interface_board_reocc/top_mib_v3 (project file https://github.com/uob-hep-cad/uob-hep-pc072/blob/main/hardware/Cadence/top/top_mib_v3.cpm)
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Design files for the tongue-2 board at https://github.com/uob-hep-cad/uob-hep-pc072/tree/main/hardware/Cadence/top/mtca_interface_board_reocc/mib_tongue2 (project file https://github.com/uob-hep-cad/uob-hep-pc072/blob/main/hardware/Cadence/top/top_mib_v3.cpm)
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Schematic capture and PCB layout of the original (v1) version done at University of Pensylvania by Godwin Meyers in Cadence Orcad/Allegro
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The v1 design translated to Cadence Allegro Design Entry HDL by Elgris Technologies
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Changes to v1 design done by Magnus Loutit and David Cussans to produce the v2 and then v3 design
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PCB layout of the v3 design done at the University of Oxford by Pete Hastings
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The MIB v2 onwards has no ADN2814 CDR - recovery of clock done directly by Si5395 PLL
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List of changes w.r.t. v0.1 MIB at https://webapps-pp.bris.ac.uk/elog/DUNE/34
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