Prototype-to-Pilot DFM changes #1
Assignees
allspice-admin-daniel
allspice-alex
AllSpiceAlice
allspice-carah
allspice-eli
allspice-hermes
allspice-ian
allspice-kyle
allspice-nick
allspice-thomas
brendan
coleblaeser
daniel-allspice
emmy
john-allspice
MikaChanical
nick
PavelInPurchasing
RevaReviewa
rowan
sam
sherry
shrikanth-allspice
shrikanthup
Tayawiggins
valentina
Clear assignees
allspice-admin-daniel
allspice-alex
AllSpiceAlice
allspice-carah
allspice-eli
allspice-hermes
allspice-ian
allspice-kyle
allspice-nick
allspice-thomas
brendan
coleblaeser
daniel-allspice
emmy
john-allspice
MikaChanical
nick
PavelInPurchasing
RevaReviewa
rowan
sam
sherry
shrikanth-allspice
shrikanthup
Tayawiggins
valentina
No Assignees
Notifications
Due Date
No due date set.
Dependencies
No dependencies set.
Reference: AllSpice-Demos/AI-DRCY-Review#1
Loading…
x
Reference in New Issue
Block a user
No description provided.
Delete Branch "develop"
Deleting a branch is permanent. Although the deleted branch may continue to exist for a short time before it actually gets removed, it CANNOT be undone in most cases. Continue?
Description
V0.4 Fixes design errors from V0.3
Design Review Checklist
Process
System
Components
Schematics
PCB
Manufacturing
fablayer info presentFootprints
Placement
Clearance
Mechanical
Electrical
Signal Integrity
Copper Pour
Traces
Thermal
Testing
Silk screen
DRCY has reviewed this Design Review, and there should be a review posted below.
DRCY Connections Checker Review
DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 67 component(s) to review, and found 9 potential issue(s) in 8 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.
Component Details
DRCY selected and reviewed all connections from the following components of the schematic:
U1 - TPS54531 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
BOOT pin correctly connected to bootstrap capacitor C1 along with PH pin.
Pin 1 (BOOT) connects to net NetC1_1, which connects to one side of C1 (100nF capacitor). The other side of C1 connects to NetC1_2, which is the PH pin (pin 8). The datasheet (page 3) states 'A 0.1-μF bootstrap capacitor is required between the BOOT and PH pins' and specifies 'The bootstrap capacitor value must be 0.1 μF' (page 13). C1 is 100nF which equals 0.1μF, meeting the requirement exactly. This bootstrap capacitor is essential for proper operation of the high-side MOSFET.VIN pin correctly connected to VPWR input supply rail.
Pin 2 (VIN) connects to net VPWR, which is the main input power rail. The datasheet (page 3) states 'This pin is the 3.5- to 28-V input supply voltage.' The VPWR net connects to input capacitors and power sources throughout the circuit, which is appropriate for the input supply connection. This follows standard buck converter topology.EN pin correctly connected to UVLO voltage divider network.
Pin 3 (EN) connects to net NetR2_2, which forms a voltage divider with R11 (10K to VPWR) and R2 (1.4K to GND). The datasheet (page 3) states 'Programming the input undervoltage lockout with two resistors is recommended' and (page 13) describes 'The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1 is connected between the VIN and EN pins of the TPS54531 device and R2 is connected between the EN and GND pins.' While the datasheet refers to VIN, R11 connects to VPWR which is the same net as VIN (pin 2), making this functionally equivalent and correct.SS pin correctly connected to slow-start capacitor C171.
Pin 4 (SS) connects to net NetC171_2, which connects to C171 (10nF capacitor) with the other side grounded. The datasheet (page 3) states 'This pin is slow-start pin. An external capacitor connected to this pin sets the output rise time.' The 10nF capacitor to ground provides the slow-start timing function as specified. This is a standard configuration for controlling the output voltage rise time during startup.VSNS pin correctly connected to output voltage feedback divider network.
Pin 5 (VSNS) connects to net NetC3_1, which is the center point of a voltage divider formed by R1 (10.2k) and R5 (1.96k). The datasheet (page 3) states 'This pin is the inverting node of the transconductance (gm) error amplifier' and (page 13) explains 'The output voltage of the TPS54531 device is externally adjustable using a resistor divider network' with VREF = 0.8V. The voltage divider ratio calculates to Vout = 0.8V × (1 + 10.2k/1.96k) = 0.8V × 6.204 = 4.96V ≈ 5V, which is correct for a 5V output regulator. R1 connects to the output through NetC3_2.COMP pin correctly connected to frequency compensation network.
Pin 6 (COMP) connects to net NetC150_2, which forms a compensation network with R10 (37.4K to GND), C150 (2.2nF), and C151 (22pF to GND). The datasheet (page 3) states 'This pin is the error-amplifier output and the input to the PWM comparator. Connect frequency compensation components to this pin.' The typical application (page 13) shows similar compensation components including a 37.4kΩ resistor and 2200pF capacitor. This Type II compensation network provides proper loop stability for the buck converter.GND pin correctly connected to circuit ground.
Pin 7 (GND) connects to the GND net, which is the circuit ground reference. The datasheet (page 3) identifies this as the 'Ground pin.' This is a straightforward and correct connection for the ground reference of the IC.PH pin correctly connected to switching node with bootstrap capacitor, inductor, and catch diode.
Pin 8 (PH) connects to net NetC1_2, which connects to: the bootstrap capacitor C1 (forming the required BOOT-PH capacitor), inductor L1 pin 1 (switching node to output filter), and catch diode D2 cathode. The datasheet (page 3) states 'The PH pin is the source of the internal high-side power MOSFET.' The typical application (page 13) shows the PH pin connected to the inductor and catch diode cathode, exactly as implemented here. This is the correct switching node configuration for a buck converter.PAD pin correctly connected to ground for thermal and electrical performance.
Pin 9 (PAD) connects to the GND net. The datasheet (page 3) states 'For proper operation, the GND pin must be connected to the exposed pad.' This connection is essential for both thermal dissipation and proper electrical operation of the device. The layout guidelines (page 13) emphasize that 'For operation at full rated load, the exposed thermal pad must be soldered directly to the top-side ground area under the device.'D2 - SK54B ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode correctly connected to ground for catch diode operation.
Pin A (Anode) connects to GND. This is the correct connection for a catch diode in a buck converter. The TPS54531 datasheet (page 13) states 'The TPS54531 device is designed to operate using an external catch diode between the PH and GND pins.' The SK54B datasheet (page 1) shows this is a 5 Amp Schottky Rectifier with appropriate ratings for this application. The anode-to-ground connection allows the diode to conduct the inductor current when the high-side MOSFET is off.Cathode correctly connected to switching node PH for catch diode operation.
Pin K (Cathode) connects to net NetC1_2, which is the PH switching node of U1. This completes the catch diode connection between PH and GND as required by the TPS54531 datasheet (page 13). The SK54B has a forward voltage VF of 0.55V at IF=5A (datasheet page 1), which is appropriate for this 5A buck converter application. The cathode connection to the switching node allows proper freewheeling current flow during the off-time of the switching cycle.L1 - 4.7uH 10A ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Terminal 1 correctly connected to switching node PH of the buck converter.
Pin 1 connects to net NetC1_2, which is the PH switching node from U1 pin 8. This is the correct connection for the input side of the output filter inductor in a buck converter topology. The switching node provides the pulsed DC voltage that the LC filter converts to a smooth DC output.Terminal 2 correctly connected to output node for buck converter filtering.
Pin 2 connects to net NetC3_2, which is the output node of the buck converter. This connects to the output capacitors and feedback network. The 4.7μH inductance value is appropriate as the TPS54531 datasheet (page 13) states 'inductor values for use with the TPS54531 device are in the range of 1 μH to 47 μH' and the typical application shows a 4.7μH inductor. The SRP1038A datasheet shows this inductor can handle the required current with Irms=10A and Isat=17A ratings, suitable for the 5A output application.U8 - MIC5353-3.3YMT-TR ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
EN pin is connected to +5VCC to enable the 3.3V regulator when 5V power is available.
The EN pin is the enable input according to the datasheet (page 1). It is connected to the +5VCC net, which means the 3.3V regulator will be enabled when the 5V rail is active. This is a logical design choice as it ensures the 3.3V regulator only operates when there is a stable 5V supply available. The datasheet does not specify voltage levels for the enable pin, but connecting it to the input supply voltage is a standard configuration.GND pin is correctly connected to the system ground reference.
The GND pin is described as 'Ground reference' in the datasheet (page 1) and is properly connected to the system GND net. This provides the necessary ground reference for the regulator's operation.VIN pin is connected to +5VCC as the input voltage supply for the 3.3V regulator.
The VIN pin is the 'Input voltage supply, 2.6V to 6V' according to the datasheet (page 1). It is connected to the +5VCC net, which should provide approximately 5V. This voltage level is well within the specified input range of 2.6V to 6V, making this connection appropriate for the regulator's operation.VOUT pin provides the regulated 3.3V output to the 3.3VCC net.
The VOUT pin is the 'Regulated output voltage' according to the datasheet (page 1). It is connected to the 3.3VCC net, which is consistent with the part number MIC5353-3.3YMT-TR indicating a fixed 3.3V output version. This connection properly distributes the regulated 3.3V power throughout the system.ADJ pin is left unconnected, which is appropriate for the fixed voltage version of this regulator.
The ADJ pin is connected to 'unconnected-(NetU8_5)' net. According to the datasheet (page 1), this pin is 'Not connected in fixed voltage version' but serves as an 'Adjustment pin for adjustable voltage version'. Since the part number MIC5353-3.3YMT-TR indicates this is a fixed 3.3V version, leaving this pin unconnected is the correct configuration.BYP pin is connected to a 100nF bypass capacitor (C26) for noise reduction.
The BYP pin is the 'Bypass pin for noise reduction' according to the datasheet (page 1). It is connected to NetC26_1, which connects to capacitor C26 (100nF) that has its other terminal connected to ground. This matches the typical application circuit shown in the datasheet (page 2) which uses a 0.1μF bypass capacitor. The 100nF capacitor provides the necessary noise filtering for improved regulator performance.PAD pin is connected to ground for proper thermal management.
The PAD pin represents the thermal pad of the package and is connected to the GND net. This connection provides a thermal path for heat dissipation from the regulator to the ground plane, which is essential for proper thermal management in the compact 6-pin UDFN package. This is standard practice for thermal pad connections in LDO regulators.U20 - 78L05 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
OUT pin provides the regulated 5V output to the 5V0_AUX auxiliary power rail.
The OUT pin is the 'Regulated output voltage' according to the datasheet (page 3). It is connected to the 5V0_AUX net, which indicates this regulator is providing auxiliary 5V power separate from the main 5V rail. The L78L05 is designed to provide a fixed 5V output, making this connection appropriate for supplying auxiliary 5V power to specific circuits that need isolation from the main 5V supply.GND pin is correctly connected to the system ground reference.
The GND pin is described as 'Ground reference' in the datasheet (page 3) and is properly connected to the system GND net. This provides the necessary ground reference for the regulator's operation and completes the current return path.IN pin receives input power from the VPWR main power rail.
The IN pin is the 'DC input voltage' according to the datasheet (page 3). It is connected to the VPWR net, which based on schematic annotations appears to be the main power input (12-24VDC). The L78L05 datasheet features (page 1) indicate it can handle input voltages well above this range, making VPWR an appropriate input source. This configuration allows the auxiliary 5V regulator to operate directly from the main power input.U19 - INA381_ALT ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
IN+ pin correctly connected to the supply side of current sense resistor R148 via NetC3_2.
Pin 1 (IN+) connects to NetC3_2, which is one terminal of the 0.01R current sense resistor R148. According to the datasheet (page 3), IN+ should 'Connect this pin to the supply side of the shunt resistor'. Tracing the circuit, NetC3_2 connects to the output of buck regulator U1 and represents the supply side, while +5VCC (connected to IN-) represents the load side after the voltage drop across R148. Current flows from NetC3_2 through R148 to +5VCC, making NetC3_2 the higher potential supply side. This connection is correct for current sensing in the +5V rail.Vs pin correctly connected to 5V0_AUX auxiliary power supply.
Pin 2 (Vs) connects to 5V0_AUX, which is the output of the 78L05 auxiliary regulator U20. According to the datasheet (page 3), VS+ is the 'Power supply: 2.7 V to 5.5 V'. The 5V0_AUX rail provides 5V, which is within the specified operating range. This auxiliary supply is separate from the main +5VCC rail being monitored, which is appropriate to avoid supply dependency issues during overcurrent conditions.nALERT pin correctly connected to enable control of main buck regulator for overcurrent protection.
Pin 3 (nALERT) connects to NetR2_2, which connects to the EN pin of the TPS54531 buck regulator U1. According to the datasheet (page 3), ALERT is an 'Overlimit alert, active low, open-drain output'. When overcurrent is detected, this pin will pull low, disabling the main regulator through its enable pin. The net also has pull-up resistor R11 (10k) to VPWR and is connected to outputs of comparators U21 and U6, creating a comprehensive protection scheme. This configuration provides proper overcurrent protection functionality.RESET pin correctly pulled high to 5V0_AUX through R102 for mode selection.
Pin 4 (RESET) connects to NetR102_1, which is pulled up to 5V0_AUX through R102 (1k resistor). According to the datasheet (page 3), RESET is a 'Transparent or latch mode selection input'. The schematic notes indicate 'RESET=1=LATCHING' and 'RESET=0=TRANSPARENT'. By pulling this pin high, the circuit selects latching mode, meaning once an overcurrent condition triggers the alert, it will remain latched until manually reset. This is appropriate for a protection circuit where you want the fault condition to persist until acknowledged.CMPREF pin correctly connected to voltage divider setting the overcurrent threshold reference.
Pin 5 (CMPREF) connects to NetR115_1, which is the junction of voltage divider formed by R115 (15k) to 5V0_AUX and R119 (4.7k) to GND. According to the datasheet (page 3), CMPREF is the 'Input reference to the comparator'. The voltage divider creates a reference of approximately 5V × 4.7k/(15k+4.7k) ≈ 1.19V. This sets the threshold voltage that the amplified current signal must exceed to trigger an alert. The reference level appears reasonable for the INA381A2's 50V/V gain and the 0.01R sense resistor.CMPIN and VOUT pins are directly connected together, creating direct feedback from amplifier output to comparator input.
Pins 6 (CMPIN) and 7 (VOUT) are both connected to NetU19_6, creating a direct connection between the current-sense amplifier output and the comparator input. According to the datasheet (page 3), CMPIN is the 'Signal input to the comparator' and VOUT is the 'Current-sense amplifier output voltage'. This configuration means the comparator directly compares the amplified current signal (VOUT) against the reference voltage (CMPREF). While the datasheet (page 19) mentions connecting VOUT to CMPIN through a resistor for hysteresis adjustment, the direct connection is valid for basic overcurrent detection where the amplified voltage represents current level and triggers alert when exceeding the reference threshold.CMPIN and VOUT pins are directly connected together, creating direct feedback from amplifier output to comparator input.
Pins 6 (CMPIN) and 7 (VOUT) are both connected to NetU19_6, creating a direct connection between the current-sense amplifier output and the comparator input. According to the datasheet (page 3), CMPIN is the 'Signal input to the comparator' and VOUT is the 'Current-sense amplifier output voltage'. This configuration means the comparator directly compares the amplified current signal (VOUT) against the reference voltage (CMPREF). While the datasheet (page 19) mentions connecting VOUT to CMPIN through a resistor for hysteresis adjustment, the direct connection is valid for basic overcurrent detection where the amplified voltage represents current level and triggers alert when exceeding the reference threshold.IN- pin correctly connected to the load side of current sense resistor R148 via +5VCC.
Pin 8 (IN-) connects to +5VCC, which is the load side terminal of current sense resistor R148. According to the datasheet (page 3), IN- should 'Connect this pin to the load side of the shunt resistor'. The circuit topology shows current flowing from NetC3_2 (supply side) through R148 to +5VCC (load side), with +5VCC being at lower potential due to the resistive drop. This creates the proper differential voltage across the INA381's inputs proportional to the load current, enabling accurate current measurement and protection.GND pin correctly connected to system ground.
Pin 9 (GND) connects to the system GND net. According to the datasheet (page 3), this is the 'Device ground' and should be 'Connect the thermal pad to the system ground'. This provides the proper ground reference for the device operation and is correctly implemented.U21 - AP331A ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
IN- pin connected to a reference voltage divider providing ~2.17V from 5V0_AUX rail. This serves as the threshold reference for undervoltage detection.
Pin 1 is the inverting input (IN-) according to the datasheet (page 2). It connects to NetR157_1, which is the junction of a voltage divider formed by R157 (130k) from 5V0_AUX and R158 (100k) to GND. This creates a reference voltage of approximately 5V * 100k/(130k+100k) = 2.17V. This reference voltage sets the threshold for the undervoltage lockout function. The connection is correct as it provides a stable reference voltage derived from the auxiliary 5V supply.GND pin correctly connected to system ground reference.
Pin 2 is the ground reference according to the datasheet (page 2). It is properly connected to the system GND net, providing the ground reference for the comparator. This connection is correct and follows standard practice for comparator ground connections.IN+ pin connected to a scaled version of VMOTA voltage through voltage divider, providing ~0.29 * VMOTA for undervoltage monitoring.
Pin 3 is the non-inverting input (IN+) according to the datasheet (page 2). It connects to NetR154_2, which receives a scaled version of the VMOTA voltage through R154 (24k). The voltage divider is completed by the parallel combination of R155 (10k to GND) and R156 (1M to NetR2_2). Since R155 is much smaller than R156, the effective bottom resistance is approximately 10k, giving a scaling factor of 10k/(24k+10k) ≈ 0.29. This means the comparator will trigger when VMOTA drops below approximately 2.17V/0.29 ≈ 7.5V, providing undervoltage protection for the motor supply. The connection is correct for this monitoring function.Output pin connected to shared enable/alert signal that controls main 5V regulator and current monitor alert.
Pin 4 is the comparator output according to the datasheet (page 2), described as 'uncommitted collector of grounded-emitter NPN transistor'. It connects to NetR2_2, which is a shared signal connecting to U1 pin 3 (EN), U19 pin 3 (nALERT), U6 pin 4 (OUT), and pull-up/pull-down resistors. This creates a wired-OR configuration where either comparator can pull the signal low to disable the main 5V regulator (TPS54531) and alert the current monitor (INA381) when an undervoltage condition is detected. The open-collector output configuration from the datasheet (page 2) supports this wired-OR topology. The connection is correct for implementing undervoltage lockout protection.VCC pin correctly powered from VPWR supply rail.
Pin 5 is the power supply input (Vcc) according to the datasheet (page 2). It is connected to VPWR, which appears to be the main power rail. The datasheet (page 1) specifies a wide supply voltage range of 2.0V to 36V, and VPWR appears to be within this range based on the circuit context with 12-24VDC inputs. The connection provides proper power to the comparator and is correct.U6 - AP331A ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
IN- pin connected to identical reference voltage divider as U21, providing ~2.17V threshold for undervoltage detection.
Pin 1 is the inverting input (IN-) according to the datasheet (page 2). It connects to NetR57_1, which is the junction of a voltage divider formed by R57 (130k) from 5V0_AUX and R58 (100k) to GND. This creates the same reference voltage as U21: approximately 5V * 100k/(130k+100k) = 2.17V. This consistent reference voltage ensures both motor voltage monitors have the same threshold. The connection is correct and matches the design intent for parallel voltage monitoring.GND pin correctly connected to system ground reference.
Pin 2 is the ground reference according to the datasheet (page 2). It is properly connected to the system GND net, providing the ground reference for the comparator. This connection is correct and follows standard practice for comparator ground connections.IN+ pin connected to scaled version of VMOTE voltage through voltage divider, providing ~0.29 * VMOTE for undervoltage monitoring.
Pin 3 is the non-inverting input (IN+) according to the datasheet (page 2). It connects to NetR26_2, which receives a scaled version of the VMOTE voltage through R26 (24k). The voltage divider is completed by the parallel combination of R56 (10k to GND) and R28 (1M to NetR2_2). Similar to U21, the effective bottom resistance is approximately 10k, giving the same scaling factor of 10k/(24k+10k) ≈ 0.29. This means the comparator will trigger when VMOTE drops below approximately 2.17V/0.29 ≈ 7.5V, providing undervoltage protection for the second motor supply. The connection is correct and consistent with U21's monitoring function.Output pin connected to same shared enable/alert signal as U21, creating wired-OR undervoltage protection.
Pin 4 is the comparator output according to the datasheet (page 2), described as 'uncommitted collector of grounded-emitter NPN transistor'. It connects to the same NetR2_2 as U21, creating a wired-OR configuration where either comparator can pull the signal low. This shared output controls U1 pin 3 (EN) to disable the main 5V regulator and U19 pin 3 (nALERT) to alert the current monitor when either VMOTA or VMOTE experiences an undervoltage condition. The open-collector output configuration from the datasheet (page 2) properly supports this wired-OR topology. The connection is correct for implementing comprehensive motor supply undervoltage protection.VCC pin correctly powered from VPWR supply rail.
Pin 5 is the power supply input (Vcc) according to the datasheet (page 2). It is connected to VPWR, the same supply as U21. The datasheet (page 1) specifies a wide supply voltage range of 2.0V to 36V, and VPWR appears to be within this range based on the circuit context with 12-24VDC inputs. The connection provides proper power to the comparator and is correct.P1 - Header 4X2 ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
VFAN power pins connected to fan power rail. VFAN is connected to VPWR through 0R jumper R103.
Pins 1 and 3 are both connected to the VFAN net. Tracing this net, I find that R103 (0R jumper resistor) connects VPWR to VFAN, making VFAN equivalent to VPWR when the jumper is populated. This arrangement allows for optional separation of fan power from main power by removing the jumper if needed. The dual pins provide redundancy and better current distribution for fan loads. Without the datasheet, I cannot verify the current rating, but the connection logic is sound for a power distribution header.VFAN power pins connected to fan power rail. VFAN is connected to VPWR through 0R jumper R103.
Pins 1 and 3 are both connected to the VFAN net. Tracing this net, I find that R103 (0R jumper resistor) connects VPWR to VFAN, making VFAN equivalent to VPWR when the jumper is populated. This arrangement allows for optional separation of fan power from main power by removing the jumper if needed. The dual pins provide redundancy and better current distribution for fan loads. Without the datasheet, I cannot verify the current rating, but the connection logic is sound for a power distribution header.Ground pins properly connected to main ground net. Multiple ground connections provide good current distribution.
Pins 2, 4, 6, and 8 are all connected to the GND net, which serves as the main ground reference throughout the circuit. Having multiple ground pins in a power connector is good practice as it reduces ground impedance, improves current distribution, and provides redundancy. The alternating power/ground pattern (power on odd pins, ground on even pins) is typical for power connectors as it minimizes inductance and provides good electrical performance. Without the datasheet, I cannot verify current ratings, but the connection approach is correct.Ground pins properly connected to main ground net. Multiple ground connections provide good current distribution.
Pins 2, 4, 6, and 8 are all connected to the GND net, which serves as the main ground reference throughout the circuit. Having multiple ground pins in a power connector is good practice as it reduces ground impedance, improves current distribution, and provides redundancy. The alternating power/ground pattern (power on odd pins, ground on even pins) is typical for power connectors as it minimizes inductance and provides good electrical performance. Without the datasheet, I cannot verify current ratings, but the connection approach is correct.Ground pins properly connected to main ground net. Multiple ground connections provide good current distribution.
Pins 2, 4, 6, and 8 are all connected to the GND net, which serves as the main ground reference throughout the circuit. Having multiple ground pins in a power connector is good practice as it reduces ground impedance, improves current distribution, and provides redundancy. The alternating power/ground pattern (power on odd pins, ground on even pins) is typical for power connectors as it minimizes inductance and provides good electrical performance. Without the datasheet, I cannot verify current ratings, but the connection approach is correct.Ground pins properly connected to main ground net. Multiple ground connections provide good current distribution.
Pins 2, 4, 6, and 8 are all connected to the GND net, which serves as the main ground reference throughout the circuit. Having multiple ground pins in a power connector is good practice as it reduces ground impedance, improves current distribution, and provides redundancy. The alternating power/ground pattern (power on odd pins, ground on even pins) is typical for power connectors as it minimizes inductance and provides good electrical performance. Without the datasheet, I cannot verify current ratings, but the connection approach is correct.VPWR power pins connected to main power rail. Dual pins provide redundancy and current distribution.
Pins 5 and 7 are both connected to the VPWR net, which is the main power rail feeding multiple components including U1 (TPS54531 buck regulator), U20 (78L05 linear regulator), and comparators U21 and U6. The dual pins provide redundancy and better current distribution capability. VPWR originates from VPWR_IN through fuse F2, providing overcurrent protection. The connection is logically correct for distributing main power, though without the datasheet I cannot verify if the connector can handle the expected current loads.VPWR power pins connected to main power rail. Dual pins provide redundancy and current distribution.
Pins 5 and 7 are both connected to the VPWR net, which is the main power rail feeding multiple components including U1 (TPS54531 buck regulator), U20 (78L05 linear regulator), and comparators U21 and U6. The dual pins provide redundancy and better current distribution capability. VPWR originates from VPWR_IN through fuse F2, providing overcurrent protection. The connection is logically correct for distributing main power, though without the datasheet I cannot verify if the connector can handle the expected current loads.J3 - 10 Pos barrier ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
VMOTE motor power input connected to motor power rail with proper filtering and protection components.
Pin 1 is connected to the VMOTE net, which feeds various components including bypass capacitors C18 (100nF), C17 (1nF), bulk capacitor C14 (10uF), TVS diode D21 (SMAJ24A) for overvoltage protection, and voltage divider R26/R56 for monitoring via comparator U6. This appears to be a motor power input with appropriate filtering and protection. The TVS diode provides transient protection, while the capacitors provide filtering. The connection is logically sound for a motor power input, though without the datasheet I cannot verify current handling capability.Ground pins properly connected to main ground net. Multiple ground connections provide excellent current distribution for high-power application.
Pins 2, 4, 6, and 8 are all connected to the GND net. Having four ground pins out of ten total pins (40%) is appropriate for a high-power application where significant return currents are expected from motor drives, heated bed, and other power loads. This provides low impedance ground return paths and good current distribution. The spacing between ground pins helps minimize ground bounce and provides multiple low-inductance return paths. Without the datasheet, I cannot verify current ratings, but the approach is correct for high-power applications.Ground pins properly connected to main ground net. Multiple ground connections provide excellent current distribution for high-power application.
Pins 2, 4, 6, and 8 are all connected to the GND net. Having four ground pins out of ten total pins (40%) is appropriate for a high-power application where significant return currents are expected from motor drives, heated bed, and other power loads. This provides low impedance ground return paths and good current distribution. The spacing between ground pins helps minimize ground bounce and provides multiple low-inductance return paths. Without the datasheet, I cannot verify current ratings, but the approach is correct for high-power applications.Ground pins properly connected to main ground net. Multiple ground connections provide excellent current distribution for high-power application.
Pins 2, 4, 6, and 8 are all connected to the GND net. Having four ground pins out of ten total pins (40%) is appropriate for a high-power application where significant return currents are expected from motor drives, heated bed, and other power loads. This provides low impedance ground return paths and good current distribution. The spacing between ground pins helps minimize ground bounce and provides multiple low-inductance return paths. Without the datasheet, I cannot verify current ratings, but the approach is correct for high-power applications.Ground pins properly connected to main ground net. Multiple ground connections provide excellent current distribution for high-power application.
Pins 2, 4, 6, and 8 are all connected to the GND net. Having four ground pins out of ten total pins (40%) is appropriate for a high-power application where significant return currents are expected from motor drives, heated bed, and other power loads. This provides low impedance ground return paths and good current distribution. The spacing between ground pins helps minimize ground bounce and provides multiple low-inductance return paths. Without the datasheet, I cannot verify current ratings, but the approach is correct for high-power applications.VMOTA motor power input connected to motor power rail with filtering, protection, and monitoring components.
Pin 3 is connected to the VMOTA net, which feeds bypass capacitors C95 (100nF) and C94 (1nF), bulk capacitor C93 (10uF), TVS diode D43 (SMAJ24A) for overvoltage protection, and voltage divider R154/R155 for monitoring. This appears to be another motor power input (possibly for a different set of motors) with similar protection and filtering as VMOTE. The circuit topology matches the VMOTE rail, providing consistent protection and monitoring across motor power inputs. The connection is appropriate for motor power distribution.VPWR_IN main power input that feeds through fuse F2 to create the VPWR rail for logic and control circuits.
Pin 5 is connected to VPWR_IN net, which connects to fuse F2 pin 1 and test point TP48. Fuse F2 (3557-2, rated for 30A 500V) connects VPWR_IN to VPWR, providing overcurrent protection for the main power rail. VPWR then feeds the TPS54531 buck regulator (U1), 78L05 linear regulator (U20), and various comparators. This fused input arrangement provides safety protection for the main logic power, which is good design practice. The connection is correct for a protected main power input.VBED_IN heated bed power input that feeds through fuse F1 to create the VBED rail for heated bed power.
Pin 7 is connected to VBED_IN net, which connects to fuse F1 pin 1 and test point TP44. Fuse F1 (3557-20, rated for 30A 500V) connects VBED_IN to VBED, providing overcurrent protection for the heated bed power rail. VBED feeds filtering capacitors C15 (100nF), C13 (1nF), C16 (10uF), bulk capacitor C210 (100uF), and TVS diode D78 for protection. This fused input arrangement is essential for heated bed safety, as heated beds can draw significant current. The connection is correct for protected heated bed power input.VBED heated bed power output with filtering and protection components. Provides direct access to fused heated bed power.
Pin 9 is connected to the VBED net, which is the output of fuse F1 from VBED_IN. This provides direct access to the filtered and fused heated bed power rail. VBED connects to filtering capacitors C15, C13, C16, bulk capacitor C210, TVS diode D78, and test point TP43. This allows external heated bed connections while maintaining the protection and filtering provided by the onboard components. The connection is appropriate for heated bed power distribution.HTBD-OUT appears to be a heated bed control output signal that doesn't connect to other components on this page.
Pin 10 is connected to the HTBD-OUT net, which doesn't appear to connect to any other components on this schematic page. Based on the name, this appears to be a heated bed control output signal, likely a switched or PWM signal for controlling heated bed power. Since this is a multi-page schematic (indicated by 'Sheet: * of 11'), this signal likely connects to heated bed control circuitry on another page. Without seeing the complete schematic or datasheet, I cannot verify the specific function, but the naming suggests it's an output control signal rather than a power connection.F1 - 3557-2 ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Input terminal connected to VBED_IN for overcurrent protection of heated bed power rail.
Pin 1 is connected to VBED_IN and pin 2 to VBED, placing the fuse block in series with the heated bed power supply. This is the correct configuration for overcurrent protection - the fuse will interrupt current flow if it exceeds the fuse rating, protecting downstream circuits from overcurrent conditions. The fuse acts as a sacrificial element that will blow before damage occurs to more expensive components. Without the datasheet, I cannot verify the specific current rating, but the series connection is electrically correct for this protection function.Output terminal connected to VBED for overcurrent protection of heated bed power rail.
Pin 2 is connected to VBED and pin 1 to VBED_IN, placing the fuse block in series with the heated bed power supply. This is the correct configuration for overcurrent protection - the fuse will interrupt current flow if it exceeds the fuse rating, protecting downstream circuits from overcurrent conditions. The fuse acts as a sacrificial element that will blow before damage occurs to more expensive components. Without the datasheet, I cannot verify the specific current rating, but the series connection is electrically correct for this protection function.F2 - 3557-2 ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Input terminal connected to VPWR_IN for overcurrent protection of main power rail.
Pin 1 is connected to VPWR_IN and pin 2 to VPWR, placing the fuse block in series with the main power supply. This is the correct configuration for overcurrent protection - the fuse will interrupt current flow if it exceeds the fuse rating, protecting downstream circuits from overcurrent conditions. The fuse acts as a sacrificial element that will blow before damage occurs to more expensive components. Without the datasheet, I cannot verify the specific current rating, but the series connection is electrically correct for this protection function.Output terminal connected to VPWR for overcurrent protection of main power rail.
Pin 2 is connected to VPWR and pin 1 to VPWR_IN, placing the fuse block in series with the main power supply. This is the correct configuration for overcurrent protection - the fuse will interrupt current flow if it exceeds the fuse rating, protecting downstream circuits from overcurrent conditions. The fuse acts as a sacrificial element that will blow before damage occurs to more expensive components. Without the datasheet, I cannot verify the specific current rating, but the series connection is electrically correct for this protection function.D43 - SMAJ24A ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Anode correctly connected to GND for overvoltage protection of VMOTA rail.
The anode is connected to GND while the cathode is connected to VMOTA. This is the correct polarity for a unidirectional TVS diode protecting a positive voltage rail. During normal operation, the diode is reverse-biased and does not conduct. When an overvoltage transient occurs on VMOTA that exceeds the breakdown voltage (24V based on the SMAJ24A designation), the diode will avalanche and clamp the voltage to protect downstream circuits. The current path during clamping is from VMOTA through the diode to GND, which is the intended protection mechanism.Cathode correctly connected to VMOTA rail for overvoltage protection.
The cathode is connected to VMOTA while the anode is connected to GND. This is the correct polarity for a unidirectional TVS diode protecting a positive voltage rail. During normal operation, the diode is reverse-biased and does not conduct. When an overvoltage transient occurs on VMOTA that exceeds the breakdown voltage (24V based on the SMAJ24A designation), the diode will avalanche and clamp the voltage to protect downstream circuits. The current path during clamping is from VMOTA through the diode to GND, which is the intended protection mechanism.D22 - SMAJ24A ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Anode correctly connected to GND for overvoltage protection of VPWR rail.
The anode is connected to GND while the cathode is connected to VPWR. This is the correct polarity for a unidirectional TVS diode protecting a positive voltage rail. During normal operation, the diode is reverse-biased and does not conduct. When an overvoltage transient occurs on VPWR that exceeds the breakdown voltage (24V based on the SMAJ24A designation), the diode will avalanche and clamp the voltage to protect downstream circuits. The current path during clamping is from VPWR through the diode to GND, which is the intended protection mechanism.Cathode correctly connected to VPWR rail for overvoltage protection.
The cathode is connected to VPWR while the anode is connected to GND. This is the correct polarity for a unidirectional TVS diode protecting a positive voltage rail. During normal operation, the diode is reverse-biased and does not conduct. When an overvoltage transient occurs on VPWR that exceeds the breakdown voltage (24V based on the SMAJ24A designation), the diode will avalanche and clamp the voltage to protect downstream circuits. The current path during clamping is from VPWR through the diode to GND, which is the intended protection mechanism.D21 - SMAJ24A ❌
DRCY flagged 1 potential issues in this component.
⚠️ DRCY couldn't retrieve a Datasheet for this component.
TVS diode is connected with incorrect polarity - anode to VMOTE and cathode to GND will create a short circuit.
TVS diode is connected with incorrect polarity - anode to VMOTE and cathode to GND will create a short circuit.
D78 - SMAJ24A ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Anode correctly connected to GND for overvoltage protection of VBED rail.
The anode is connected to GND while the cathode is connected to VBED. This is the correct polarity for a unidirectional TVS diode protecting a positive voltage rail. During normal operation, the diode is reverse-biased and does not conduct. When an overvoltage transient occurs on VBED that exceeds the breakdown voltage (24V based on the SMAJ24A designation), the diode will avalanche and clamp the voltage to protect downstream circuits. The current path during clamping is from VBED through the diode to GND, which is the intended protection mechanism.Cathode correctly connected to VBED rail for overvoltage protection.
The cathode is connected to VBED while the anode is connected to GND. This is the correct polarity for a unidirectional TVS diode protecting a positive voltage rail. During normal operation, the diode is reverse-biased and does not conduct. When an overvoltage transient occurs on VBED that exceeds the breakdown voltage (24V based on the SMAJ24A designation), the diode will avalanche and clamp the voltage to protect downstream circuits. The current path during clamping is from VBED through the diode to GND, which is the intended protection mechanism.D23 - 5988170107F ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
LED anode is correctly connected through current limiting resistor R33 (1k) to 3.3VCC supply rail.
The anode pin connects to net NetD23_A, which traces to pin 1 of resistor R33. Pin 2 of R33 connects to the 3.3VCC supply rail. This creates a proper current limiting circuit for the LED. With a 3.3V supply and the LED's 2V forward voltage drop (from part description '2V 0805'), the current through the 1k resistor would be approximately (3.3V - 2V) / 1000Ω = 1.3mA, which is appropriate for an indicator LED. The datasheet (page 4-5) confirms this is the anode connection for 0805 package LEDs. This connection is correct for forward bias operation.LED cathode is correctly connected to ground for proper forward bias operation.
The cathode pin connects directly to the GND net. This provides the return path for current flow through the LED. When the anode is at a higher potential than the cathode (through the 3.3V supply and current limiting resistor), the LED will conduct and illuminate. The datasheet (page 4-5) confirms this is the cathode connection for 0805 package LEDs and includes Zener diode protection. This connection is correct and follows standard LED circuit topology.J8 - USB-B ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
VBUS pin correctly connected to power supply filtering and TVS diode VCC input.
Pin 1 (VBUS) carries the USB power supply voltage and is connected to net NetC43_2, which connects to D27 pin 5 (VCC according to datasheet page 3) and C43 pin 2. This creates a filtered power connection where C43 provides power supply filtering (C43 pin 1 connects to USB_GND) and D27 pin 5 receives the supply voltage for proper TVS diode operation. This is the correct connection for USB power input with appropriate filtering and protection.DM pin correctly connected to TVS diode I/O1 for ESD protection of USB D- data line.
Pin 2 (DM) is the USB D- data line connected to net DM, which connects to D27 pin 1. According to the PRTR5V0U2F datasheet (page 3), pin 1 is I/O1 (input/output 1), providing ESD protection for this data line. This is the standard and correct connection for protecting the USB D- signal from ESD events.DP pin correctly connected to TVS diode I/O2 for ESD protection of USB D+ data line.
Pin 3 (DP) is the USB D+ data line connected to net DP, which connects to D27 pin 3. According to the PRTR5V0U2F datasheet (page 3), pin 3 is I/O2 (input/output 2), providing ESD protection for this data line. This is the standard and correct connection for protecting the USB D+ signal from ESD events.GND pin correctly connected to USB ground network providing proper grounding for protection circuit.
Pin 4 (GND) is connected to net USB_GND, which also connects to D27 pin 2 (GND according to datasheet page 3) and C43 pin 1. This provides the proper ground reference for both the TVS diode protection circuit and the power supply filter capacitor. This is the correct connection for USB ground.Shield pins correctly connected to USB ground for EMI shielding.
Both shield pins (5 and 6) are connected to net USB_GND. This is standard practice for USB connectors where the metallic shield is connected to ground to provide electromagnetic interference (EMI) shielding and proper grounding of the connector housing. This connection is correct for EMI protection.Shield pins correctly connected to USB ground for EMI shielding.
Both shield pins (5 and 6) are connected to net USB_GND. This is standard practice for USB connectors where the metallic shield is connected to ground to provide electromagnetic interference (EMI) shielding and proper grounding of the connector housing. This connection is correct for EMI protection.D27 - PRTR5V0U2F ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
I/O1 pin correctly connected to USB DM data line for ESD protection.
Pin 1 is connected to net DM (USB D- data line from J8 pin 2). According to the datasheet (page 3), pin 1 is I/O1 (input/output 1). This provides ESD protection for the USB D- signal line, which is the correct application for this TVS diode pin.GND pin correctly connected to USB ground network.
Pin 2 is connected to net USB_GND. According to the datasheet (page 3), pin 2 is GND (ground). This provides the ground reference for the TVS diode protection circuit and is correctly connected to the USB ground network that includes J8 pin 4 and C43 pin 1.I/O2 pin correctly connected to USB DP data line for ESD protection.
Pin 3 is connected to net DP (USB D+ data line from J8 pin 3). According to the datasheet (page 3), pin 3 is I/O2 (input/output 2). This provides ESD protection for the USB D+ signal line, which is the correct application for this TVS diode pin.I/O2 pin correctly connected to provide additional ESD protection after common mode choke filtering.
Pin 4 is connected to net NetD27_4, which connects to L5 pin 2 (common mode choke). According to the datasheet (page 3), pin 4 is I/O2 (input/output 2), same as pin 3. The PRTR5V0U2F datasheet (page 1) describes this device as having 'two ultra low capacitance rail-to-rail ESD protection channels' where pins 3 and 4 both provide I/O2 protection. This configuration provides ESD protection at multiple points along the USB D+ signal path - pin 3 protects at the connector side while pin 4 protects after the common mode choke L5. This is a valid dual-point protection scheme.VCC pin correctly connected to filtered USB power supply.
Pin 5 is connected to net NetC43_2, which carries the USB VBUS power through filter capacitor C43. According to the datasheet (page 3), pin 5 is VCC (supply voltage). This provides the necessary supply voltage for the TVS diode to operate properly. The connection through the filter capacitor C43 ensures clean power supply to the protection device.I/O1 pin correctly connected to provide additional ESD protection after common mode choke filtering.
Pin 6 is connected to net NetD27_6, which connects to L5 pin 3 (common mode choke). According to the datasheet (page 3), pin 6 is I/O1 (input/output 1), same as pin 1. The PRTR5V0U2F datasheet (page 1) describes this device as having 'two ultra low capacitance rail-to-rail ESD protection channels' where pins 1 and 6 both provide I/O1 protection. This configuration provides ESD protection at multiple points along the USB D- signal path - pin 1 protects at the connector side while pin 6 protects after the common mode choke L5. This is a valid dual-point protection scheme.C43 - GRM155R71H103JA88D ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Capacitor terminal correctly connected to USB ground for power supply filtering.
Pin 1 is connected to net USB_GND. According to the datasheet (page 1), this is a capacitor terminal. With pin 2 connected to the USB power supply (NetC43_2), this creates a power supply filter capacitor configuration. The 10nF capacitance value and 50V rating (datasheet page 1) are appropriate for USB power supply filtering applications.Capacitor terminal correctly connected to USB power supply for filtering.
Pin 2 is connected to net NetC43_2, which carries the USB VBUS power from J8 pin 1. According to the datasheet (page 1), this is a capacitor terminal. This creates a power supply filter capacitor where C43 filters the USB power supply between VBUS and ground. The 10nF value is appropriate for high-frequency noise filtering on the USB power line.U9 - ADuM4160 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
VBUS1 is correctly connected to the USB bus voltage through filtering components.
Pin 1 (VBUS1) is connected to the VUSB net, which traces back through ferrite bead FB29 to NetC43_2, ultimately connecting to the USB-B connector's VBUS pin (J8 pin 1). According to the datasheet (page 9): 'When the isolator is powered by the USB bus voltage (4.5 V to 5.5 V), connect the VBUS1 pin to the USB power bus.' The connection includes appropriate filtering through FB29 (120Ω ferrite bead) and bypass capacitors C28 and C32. A solder bridge JP1 allows optional connection to +5VCC. This configuration correctly provides the USB bus voltage to power the upstream side of the isolator.GND1 pins are correctly connected to USB_GND as the ground reference for the upstream side.
Both pins 2 and 8 (GND1) are connected to the USB_GND net, which serves as the ground reference for the USB side of the isolation barrier. The datasheet (page 9) states: 'Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground.' The USB_GND net is properly isolated from the main system GND through the isolation barrier, with ESD protection provided by D26 between the two ground domains. This connection is correct for maintaining proper isolation.GND1 pins are correctly connected to USB_GND as the ground reference for the upstream side.
Both pins 2 and 8 (GND1) are connected to the USB_GND net, which serves as the ground reference for the USB side of the isolation barrier. The datasheet (page 9) states: 'Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground.' The USB_GND net is properly isolated from the main system GND through the isolation barrier, with ESD protection provided by D26 between the two ground domains. This connection is correct for maintaining proper isolation.VDD1 is correctly connected to provide regulated 3.3V for the upstream side with proper bypass capacitance.
Pin 3 (VDD1) is connected to the VDD1 net, which has bypass capacitor C39 (100nF) to USB_GND and also connects to pins 4 and 5 for configuration. According to the datasheet (page 9): 'When the isolator is powered by the USB bus voltage (4.5 V to 5.5 V), the VDD1 pin should be used for a bypass capacitor to GND1. Signal lines that may require pull-up, such as PDEN and SPU, should be tied to this pin.' The connection includes the required bypass capacitor and properly supplies the configuration pins, which is correct.PDEN is correctly tied to VDD1 for standard operation enabling downstream pull-down resistors.
Pin 4 (PDEN) is connected to the VDD1 net. The datasheet (page 9) explicitly states: 'This pin must be connected to VDD1 for standard operation.' When tied high, this enables the downstream pull-down resistors for proper USB operation. The connection is correct for standard USB peripheral operation.SPU is correctly tied high to VDD1 for full-speed operation, matching the downstream SPD configuration.
Pin 5 (SPU) is connected to VDD1, setting it high for full-speed operation. The datasheet (page 9) states: 'When SPU is tied high, the full speed slew rate, timing, and logic conventions are selected... This input must be set high via connection to VDD1 or set low via connection to GND1 and must match Pin 13 (both pins tied high or both pins tied low).' Pin 13 (SPD) is also tied high to 3.3VCC, so both speed select pins match for full-speed operation. This configuration is correct.UD- 1 is correctly connected to the upstream USB D- line with proper 24Ω series termination for full-speed operation.
Pin 6 (UD- 1) connects to UD_N, which goes through R43 (24Ω series resistor) to NetL5_4, then through common mode choke L5 to the TVS protection and ultimately to the USB connector's D- pin. The datasheet application info (page 11) states: 'For full speed operation, the D+ and D− lines on each side of the device require a 24 Ω ± 1% series termination resistor.' The 24Ω termination and common mode filtering are correctly implemented for full-speed USB operation.UD+ 1 is correctly connected to the upstream USB D+ line with proper 24Ω series termination for full-speed operation.
Pin 7 (UD+ 1) connects to UD_P, which goes through R46 (24Ω series resistor) to NetL5_1, then through common mode choke L5 to the TVS protection and ultimately to the USB connector's D+ pin. This matches the datasheet requirement (page 11) for 24Ω series termination on full-speed D+ and D- lines. The implementation with common mode filtering and ESD protection is correct.GND2 pins are correctly connected to the isolated system ground for the downstream side.
Both pins 9 and 15 (GND2) are connected to the main system GND net, providing the ground reference for the isolated downstream side. The datasheet (page 9) states: 'Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground.' This connection properly maintains the isolation barrier between USB_GND and system GND while providing the required ground reference for the downstream side.GND2 pins are correctly connected to the isolated system ground for the downstream side.
Both pins 9 and 15 (GND2) are connected to the main system GND net, providing the ground reference for the isolated downstream side. The datasheet (page 9) states: 'Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground.' This connection properly maintains the isolation barrier between USB_GND and system GND while providing the required ground reference for the downstream side.UD+ 2 is correctly connected to the downstream USB D+ line with proper 24Ω series termination to the microcontroller.
Pin 10 (UD+ 2) connects to UI_P, which goes through R47 (24Ω series resistor) to UMCU_P, ultimately connecting to the microcontroller's USB D+ pin (U11B pin 37, DHSDP). The datasheet (page 11) requires 24Ω series termination for full-speed operation on both sides of the isolator. The connection to the microcontroller's high-speed USB D+ pin is appropriate, and the series termination is correctly implemented.UD- 2 is correctly connected to the downstream USB D- line with proper 24Ω series termination to the microcontroller.
Pin 11 (UD- 2) connects to UI_N, which goes through R45 (24Ω series resistor) to UMCU_N, ultimately connecting to the microcontroller's USB D- pin (U11B pin 38, DHSDM). This matches the required 24Ω series termination for full-speed operation as specified in the datasheet (page 11). The connection to the microcontroller's high-speed USB D- pin is correct.PIN is correctly tied to 3.3VCC to enable upstream pull-up resistors on power-up for immediate enumeration.
Pin 12 (PIN) is connected to 3.3VCC, which enables the upstream pull-up resistors immediately on power-up. The datasheet (page 9) states: 'It can be tied to VDD2 for operation on power-up, or it can be tied to an external control signal for an application that requires delayed enumeration.' Since it's tied to the 3.3V supply (equivalent to VDD2), this allows immediate USB enumeration when power is applied, which is appropriate for most USB peripheral applications.SPD is correctly tied high to 3.3VCC for full-speed operation, matching the upstream SPU configuration.
Pin 13 (SPD) is connected to 3.3VCC, setting it high for full-speed operation on the downstream side. The datasheet (page 9) requires: 'This input must be set high via connection to VDD2 or set low via connection to GND2 and must match Pin 5 (both pins tied high or both pins tied low).' Since pin 5 (SPU) is also tied high to VDD1, both speed select pins are correctly configured for full-speed operation with matching settings.VDD2 is correctly connected to +3.3VCC as the power supply for the downstream side with proper bypass capacitance.
Pin 14 (VDD2) is connected to +3.3VCC, providing the 3.3V power supply for the downstream side of the isolator. The datasheet (page 9) states: 'When the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2 and to the external 3.3 V power supply. A bypass capacitor to GND2 is required.' Bypass capacitors C29 and C33 (both 100nF) are connected between +3.3VCC and GND, providing the required bypass capacitance. This configuration is correct for 3.3V operation.VBUS2 is correctly connected to +3.3VCC for 3.3V power supply operation on the downstream side.
Pin 16 (VBUS2) is connected to +3.3VCC, matching the VDD2 connection for 3.3V operation. The datasheet (page 9) specifies: 'When the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2 and to the external 3.3 V power supply.' Both VBUS2 and VDD2 are connected to the same +3.3VCC supply with appropriate bypass capacitance, which is the correct configuration for 3.3V powered operation.L5 - DLW21HN900SQ2L ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Common mode choke correctly inserted in the USB differential pair between the isolator and TVS protection.
Pins 1 and 4 form one winding of the common mode choke, with pin 1 connected to NetL5_1 (from UD_P through R46) and pin 4 connected to NetL5_4 (from UD_N through R43). This places the common mode choke in series with the USB differential pair between the isolator's upstream ports and the TVS protection diode D27. According to the datasheet, this component provides common mode noise suppression while allowing differential signals to pass with minimal attenuation. The placement is correct for filtering common mode noise on the USB lines while preserving signal integrity.Common mode choke correctly inserted in the USB differential pair between the isolator and TVS protection.
Pins 1 and 4 form one winding of the common mode choke, with pin 1 connected to NetL5_1 (from UD_P through R46) and pin 4 connected to NetL5_4 (from UD_N through R43). This places the common mode choke in series with the USB differential pair between the isolator's upstream ports and the TVS protection diode D27. According to the datasheet, this component provides common mode noise suppression while allowing differential signals to pass with minimal attenuation. The placement is correct for filtering common mode noise on the USB lines while preserving signal integrity.Common mode choke output correctly connected to TVS protection diode for ESD protection of USB lines.
Pins 2 and 3 form the second winding of the common mode choke, with pin 2 connected to NetD27_4 and pin 3 connected to NetD27_6, both connecting to the TVS protection diode D27. This configuration allows the common mode choke to filter the USB differential signals before they reach the TVS protection and ultimately the USB connector. The datasheet indicates this component is suitable for communication equipment applications. The connection provides proper common mode filtering while maintaining the differential signal path to the ESD protection elements.Common mode choke output correctly connected to TVS protection diode for ESD protection of USB lines.
Pins 2 and 3 form the second winding of the common mode choke, with pin 2 connected to NetD27_4 and pin 3 connected to NetD27_6, both connecting to the TVS protection diode D27. This configuration allows the common mode choke to filter the USB differential signals before they reach the TVS protection and ultimately the USB connector. The datasheet indicates this component is suitable for communication equipment applications. The connection provides proper common mode filtering while maintaining the differential signal path to the ESD protection elements.D26 - RSB39VTE-17 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Bi-directional ESD protection diode correctly placed between isolated USB ground and system ground domains.
The anode (A) is connected to GND (system ground) and cathode (C) is connected to USB_GND (isolated USB ground). This creates bi-directional ESD protection between the two ground domains. The datasheet indicates this is a 39V bi-directional ESD protection diode with 30pF maximum capacitance. The 39V breakdown voltage is appropriate for protecting against ESD events between the isolated and non-isolated ground domains while remaining well above normal operating voltages. This placement provides essential ESD protection for the isolation barrier while maintaining the galvanic isolation between USB and system grounds.Bi-directional ESD protection diode correctly placed between isolated USB ground and system ground domains.
The anode (A) is connected to GND (system ground) and cathode (C) is connected to USB_GND (isolated USB ground). This creates bi-directional ESD protection between the two ground domains. The datasheet indicates this is a 39V bi-directional ESD protection diode with 30pF maximum capacitance. The 39V breakdown voltage is appropriate for protecting against ESD events between the isolated and non-isolated ground domains while remaining well above normal operating voltages. This placement provides essential ESD protection for the isolation barrier while maintaining the galvanic isolation between USB and system grounds.U11B - ATML-ATSAM3X-LQFP-144 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
XOUT pin correctly connected to crystal output through 3pF load capacitor.
Pin 35 (XOUT) is connected to net NetC41_2, which connects to X1 pin 3 (crystal terminal) and C41 pin 2 (3pF load capacitor to ground). According to the datasheet (page 4-7), XOUT is the 'Main oscillator crystal output'. This connection is correct for a crystal oscillator circuit. The 3pF load capacitor value appears appropriate for the crystal configuration, though the specific load capacitance requirement for part 405C35B12M00000 should be verified against the crystal's specification.XIN pin correctly connected to crystal input through 3pF load capacitor.
Pin 36 (XIN) is connected to net NetC42_2, which connects to X1 pin 1 (crystal terminal) and C42 pin 2 (3pF load capacitor to ground). According to the datasheet (page 4-7), XIN is the 'Main oscillator crystal input'. This connection is correct for a crystal oscillator circuit, with the crystal terminals properly connected between XIN and XOUT pins with appropriate load capacitors.DHSDP pin correctly connected to USB D+ high-speed line through series resistor.
Pin 37 (DHSDP) is connected to net UMCU_P, which connects through R48 (24Ω series resistor) to pin 42 (DFSDP). According to the datasheet (page 4-7), DHSDP is 'USB D+ high speed data plus'. The 24Ω series resistor provides proper impedance matching and signal integrity for USB high-speed differential signaling. This connection is correct for USB interface design.DHSDM pin correctly connected to USB D- high-speed line through series resistor.
Pin 38 (DHSDM) is connected to net UMCU_N, which connects through R42 (24Ω series resistor) to pin 43 (DFSDM). According to the datasheet (page 4-7), DHSDM is 'USB D- high speed data minus'. The 24Ω series resistor provides proper impedance matching and signal integrity for USB high-speed differential signaling. This connection is correct for USB interface design.VBUS pin correctly connected to isolated VBUS detection circuit.
Pin 39 (VBUS) is connected to net VBUS_UC, which connects to Q8 collector (NPN transistor), R150 (6.8kΩ pull-up to +5VCC), and test point TP30. The transistor Q8 is controlled by optoisolator U18, providing galvanic isolation between USB VBUS and the microcontroller's VBUS input. According to the datasheet (page 4-7), VBUS is 'USB VBUS input'. This isolated detection circuit is a good design practice for USB VBUS sensing, providing protection and isolation.VBG pin correctly connected to bandgap reference circuit with appropriate filtering.
Pin 40 (VBG) is connected to net NetC49_1, which connects to C49 pin 1 (10pF capacitor to ground), R49 pin 2 (6.8kΩ resistor to ground), and test point TP32. While the datasheet doesn't explicitly define VBG in the pin functions section, this appears to be a bandgap voltage reference based on the pin name and circuit configuration. The 10pF capacitor provides high-frequency filtering, and the 6.8kΩ resistor provides a discharge path. This is a typical configuration for voltage reference pins.DFSDP pin correctly connected to USB D+ full-speed line through series resistor.
Pin 42 (DFSDP) is connected to net NetR48_1, which connects to R48 pin 1 (24Ω series resistor). The other side of R48 connects to the DHSDP pin (37). According to the datasheet (page 4-7), DFSDP is 'USB D+ full speed data plus'. This connection allows the microcontroller to use either full-speed or high-speed USB modes, with the series resistor providing proper signal conditioning between the full-speed and high-speed USB pins.DFSDM pin correctly connected to USB D- full-speed line through series resistor.
Pin 43 (DFSDM) is connected to net NetR42_1, which connects to R42 pin 1 (24Ω series resistor). The other side of R42 connects to the DHSDM pin (38). According to the datasheet (page 4-7), DFSDM is 'USB D- full speed data minus'. This connection allows the microcontroller to use either full-speed or high-speed USB modes, with the series resistor providing proper signal conditioning between the full-speed and high-speed USB pins.JTAGSEL pin correctly tied to ground for normal operation.
Pin 46 (JTAGSEL) is connected to net GND (ground). According to the datasheet (page 4-7), JTAGSEL is 'JTAG selection'. Tying this pin to ground is the standard configuration for normal operation when JTAG debugging is not required. This connection is correct.NRSTB pin correctly connected to reset signal.
Pin 47 (NRSTB) is connected to net RESET. According to the datasheet (page 4-7), NRSTB is 'Reset input, active low'. This connection to the reset signal is correct for providing external reset capability to the microcontroller.XIN32 pin correctly connected to 32kHz crystal input.
Pin 48 (XIN32) is connected to net XIN32. According to the datasheet (page 4-7), XIN32 is '32.768 kHz crystal oscillator input'. This connection is correct for connecting to a 32.768kHz crystal for real-time clock functionality.XOUT32 pin correctly connected to 32kHz crystal output.
Pin 49 (XOUT32) is connected to net XOUT32. According to the datasheet (page 4-7), XOUT32 is '32.768 kHz crystal oscillator output'. This connection is correct for connecting to a 32.768kHz crystal for real-time clock functionality.SHDN pin correctly connected to shutdown control signal.
Pin 50 (SHDN) is connected to net SHDN. According to the datasheet (page 4-7), SHDN is 'Shutdown input (SAM3X8E/4E only)'. This connection is correct for providing shutdown control functionality to the microcontroller.TST pin correctly tied to ground for normal operation.
Pin 51 (TST) is connected to net GND (ground). According to the datasheet (page 4-7), TST is 'Test mode input'. Tying this pin to ground is the standard configuration for normal operation when test mode is not required. This connection is correct.FWUP pin correctly connected with pull-up resistor for force wake-up functionality.
Pin 53 (FWUP) is connected to net NetR51_1, which connects to R51 pin 1 (100kΩ resistor). The other side of R51 connects to +3.3VCC, providing a pull-up. According to the datasheet (page 4-7), FWUP is 'Force wake-up input'. The pull-up resistor configuration is correct for this input, ensuring a defined logic level when not actively driven.NRST pin correctly connected to reset circuit with filtering capacitor and series resistor.
Pin 69 (NRST) is connected to net NetC169_1, which connects to C169 pin 1 (100nF capacitor to ground) and R149 pin 2 (100Ω series resistor). R149 pin 1 connects to the NRST net. According to the datasheet (page 4-7), NRST is 'Reset input, active low'. This configuration with a filtering capacitor and series resistor is correct for reset signal conditioning and noise immunity.ADVREF pin correctly connected to analog power supply for ADC voltage reference.
Pin 75 (ADVREF) is connected to net VDDANA, which is the analog power supply rail with appropriate filtering components (C76, C77). According to the datasheet (page 4-7), ADVREF is 'ADC voltage reference'. Connecting the ADC voltage reference to the clean analog power supply is correct and provides a stable reference for ADC conversions.X1 - 405C35B12M00000 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Crystal terminal correctly connected to microcontroller XIN pin.
Pin 1 (C1) is connected to net NetC42_2, which connects to U11B pin 36 (XIN) and load capacitor C42. According to the datasheet (page 3), pin 1 is a 'Crystal connection'. This connection is correct for a crystal oscillator circuit, with one crystal terminal connected to the microcontroller's crystal input pin.Ground pin correctly connected to system ground.
Pin 2 (GND) is connected to net GND (system ground). According to the datasheet (page 3), pin 2 is 'Ground connection, internally connected to pins 4 and metal lid'. This connection is correct for providing proper grounding of the crystal package.Crystal terminal correctly connected to microcontroller XOUT pin.
Pin 3 (C2) is connected to net NetC41_2, which connects to U11B pin 35 (XOUT) and load capacitor C41. According to the datasheet (page 3), pin 3 is a 'Crystal connection'. This connection is correct for a crystal oscillator circuit, with the second crystal terminal connected to the microcontroller's crystal output pin.Ground pin correctly connected to system ground.
Pin 4 (GND) is connected to net GND (system ground). According to the datasheet (page 3), pin 4 is 'Ground connection, internally connected to pins 2 and metal lid'. This connection is correct for providing proper grounding of the crystal package.U18 - OPTO SO-4 OPNDRN OUT ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode of LED connected to VUSB through R152 (1k) for USB power detection. This connection correctly provides current to the LED when USB power is present.
Pin 1 is the anode of the internal LED according to the TLP293 datasheet (page 1). It connects to net NetR152_2, which traces to R152 pin 2. R152 pin 1 connects to VUSB net. This creates a current path from VUSB through the 1k resistor R152 to the LED anode when USB power is present. The 1k resistance provides appropriate current limiting for the LED. This configuration correctly implements USB power detection by energizing the optoisolator LED when USB power is available.Cathode of LED connected to USB_GND, completing the LED current path in the isolated USB domain. This connection is correct for proper optoisolator operation.
Pin 2 is the cathode of the internal LED according to the TLP293 datasheet (page 1). It connects to USB_GND net, which is the isolated ground domain on the USB side of the circuit. This completes the current path for the LED (anode to cathode) within the isolated USB power domain. The connection is correct as it maintains proper isolation between the USB side (USB_GND) and system side (GND) while allowing the LED to function when VUSB is present.Emitter of phototransistor connected to system GND, providing the low-side connection for the switching transistor. This connection is correct.
Pin 3 is the emitter of the internal phototransistor according to the TLP293 datasheet (page 1). It connects to the main system GND net. When the LED is energized (USB power present), the phototransistor conducts between collector (pin 4) and emitter (pin 3), effectively connecting NetQ8_1 to GND. This pulls the base of Q8 low, turning off the NPN transistor. The connection to system GND is correct as it provides the reference for the output side of the optoisolator while maintaining isolation from the input side.Collector of phototransistor connected to Q8 base through NetQ8_1, controlling the power detection transistor. This connection correctly implements the optoisolated switching function.
Pin 4 is the collector of the internal phototransistor according to the TLP293 datasheet (page 1). It connects to net NetQ8_1, which connects to Q8 pin 1 (base) and R151 pin 1. When the LED is off (no USB power), the phototransistor is off, allowing R151 to pull Q8's base high through +5VCC, turning Q8 on. When the LED is on (USB power present), the phototransistor conducts, pulling Q8's base low and turning Q8 off. This creates an inverted logic signal where USB power presence turns off Q8, allowing VBUS_UC to be pulled high through R150. The connection correctly implements isolated USB power detection.Q8 - MMBT3904_SOT523 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Base terminal connected to optoisolator output and pull-up resistor for USB power detection switching. This connection correctly implements the transistor control logic.
Pin 1 is the base terminal according to the MMBT3904 datasheet (page 1). It connects to net NetQ8_1, which connects to U18 pin 4 (optoisolator collector) and R151 pin 1. R151 pin 2 connects to +5VCC, providing a pull-up. When USB power is absent, U18's phototransistor is off, so R151 pulls the base high, turning Q8 on and pulling VBUS_UC to ground. When USB power is present, U18's phototransistor conducts, pulling the base low and turning Q8 off, allowing VBUS_UC to be pulled high through R150. This configuration correctly implements inverted logic for USB power detection.Emitter terminal connected to system ground, providing the low-side reference for the NPN transistor. This connection is correct for proper transistor operation.
Pin 2 is the emitter terminal according to the MMBT3904 datasheet (page 1). It connects to the main system GND net. For an NPN transistor in a switching configuration, the emitter should be connected to the low-side reference (ground). When Q8 is turned on (base high), current flows from collector to emitter, pulling VBUS_UC low. When Q8 is turned off (base low), no current flows and VBUS_UC can be pulled high through R150. The connection to system ground is correct for this switching application.Collector terminal connected to VBUS_UC for USB power detection signaling to the microcontroller. This connection correctly implements the switching output.
Pin 3 is the collector terminal according to the MMBT3904 datasheet (page 1). It connects to net VBUS_UC, which connects to U11B pin 39 (VBUS) and R150 pin 1. R150 pin 2 connects to +5VCC. When Q8 is on (no USB power), the collector-emitter path conducts, pulling VBUS_UC to ground. When Q8 is off (USB power present), VBUS_UC is pulled high through R150, signaling to the microcontroller that USB power is available. The connection correctly implements the output switching function for USB power detection.FB29 - FERRITE 120R 3A 0603 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Input side of ferrite bead connected to VUSB for EMI filtering of USB power. This connection correctly positions the filter in the power path.
Pin 1 connects to the VUSB net, which is the isolated USB power domain from the USB isolator U9. According to the CIS10P121AC datasheet (page 1), this is a chip bead for EMI suppression used for noise suppression in power lines. Placing the ferrite bead between the isolated USB power (VUSB) and the USB connector power provides appropriate EMI filtering. The bead is rated for high current applications up to 6A, which is suitable for USB power applications. The connection is correct for power line noise suppression.Output side of ferrite bead connected to USB connector power through NetC43_2 for EMI filtering. This connection correctly completes the EMI filter in the USB power path.
Pin 2 connects to net NetC43_2, which connects to J8 pin 1 (VBUS), D27 pin 5, C43 pin 2, and TP61 pin 1. This represents the USB connector power after EMI filtering. The ferrite bead filters high-frequency noise between the isolated USB power domain and the actual USB connector power. According to the CIS10P121AC datasheet (page 1), this component is specifically designed for noise suppression in power lines. The placement and connection are correct for EMI suppression in the USB power path.U11A - ATML-ATSAM3X-LQFP-144 ❌
DRCY flagged 1 potential issues in this component.
📄 DRCY referred to this Datasheet for this component.
JTAG TDI and TDO signals are swapped between pins 29 and 30.
JTAG TDI and TDO signals are swapped between pins 29 and 30.
PB26 pin configured as STEP6 signal for stepper motor control.
Pin 1 (PB26/CTS0/TCLK0/WKUP15) is connected to STEP6 net. According to the datasheet (page 4-7), PB26 has alternate functions including CTS0 (USART0 clear to send), TCLK0 (Timer Counter external clock), and WKUP15 (wake-up input). The pin is being used as a general purpose I/O for stepper motor step signal, which is a valid use of this pin when USART0 flow control is not needed.PA9 correctly configured as UART transmit data (UTXD).
Pin 2 (PA9/UTXD/PWMH3) is connected to PA9_UTXD net. According to the datasheet (page 4-7), PA9 has UTXD function which is UART transmit data. This connection is correct for UART communication functionality.PA10 repurposed from USART0 RXD0 to DIAG7 diagnostic signal.
Pin 3 (PA10/RXD0/DATRG/WKUP5) is connected to DIAG7 net. According to the datasheet (page 4-7), PA10 has RXD0 function (USART0 receive data), DATRG (DAC trigger), and WKUP5 (wake-up input). The pin is being used as a general purpose I/O for diagnostic purposes instead of USART0, which is acceptable when USART0 is not needed.PA11 repurposed from USART0 TXD0 to DIAG8 diagnostic signal.
Pin 4 (PA11/TXD0/ADTRG/WKUP6) is connected to DIAG8 net. According to the datasheet (page 4-7), PA11 has TXD0 function (USART0 transmit data), ADTRG (ADC trigger), and WKUP6 (wake-up input). The pin is being used as a general purpose I/O for diagnostic purposes instead of USART0, which is acceptable when USART0 is not needed.PA12 correctly configured as USART1 receive data (RXD1).
Pin 5 (PA12/RXD1/PWML1/WKUP7) is connected to PA12_RXD1 net. According to the datasheet (page 4-7), PA12 has RXD1 function which is USART1 receive data. This connection is correct for USART1 communication functionality.PA13 correctly configured as USART1 transmit data (TXD1).
Pin 6 (PA13/TXD1/PWMH2) is connected to PA13_TXD1 net. According to the datasheet (page 4-7), PA13 has TXD1 function which is USART1 transmit data. This connection is correct for USART1 communication functionality.PA14 correctly configured as USART1 request to send (RTS1).
Pin 7 (PA14/RTS1/TK) is connected to PA14_RTS1 net. According to the datasheet (page 4-7), PA14 has RTS1 function which is USART1 request to send for flow control. This connection is correct for USART1 with hardware flow control.PA15 correctly configured as USART1 clear to send (CTS1).
Pin 8 (PA15/CTS1/TF/WKUP8) is connected to PA15_CTS1 net. According to the datasheet (page 4-7), PA15 has CTS1 function which is USART1 clear to send for flow control. This connection is correct for USART1 with hardware flow control.PA17 correctly configured as TWI0 data line (SDA).
Pin 9 (PA17/TWD0/SPCK0) is connected to PA17_SDA net. According to the datasheet (page 4-7), PA17 has TWD0 function which is TWI0 (I2C) data line. The net name PA17_SDA correctly indicates this is the I2C SDA signal. This connection is correct for I2C communication.PD0 repurposed from external memory interface to M_nCS7 chip select.
Pin 13 (PD0/A10/MCDA4) is connected to M_nCS7 net. According to the datasheet (page 4-7), PD0 has A10 function (external bus interface address bit 10) and MCDA4 (HSMCI data 4). The pin is being used as a chip select signal for external devices instead of the external memory interface, which is acceptable when external memory is not used.PD1 repurposed from external memory interface to DIR8 direction signal.
Pin 14 (PD1/A11/MCDA5) is connected to DIR8 net. According to the datasheet (page 4-7), PD1 has A11 function (external bus interface address bit 11) and MCDA5 (HSMCI data 5). The pin is being used as a direction signal for stepper motor control instead of the external memory interface, which is acceptable when external memory is not used.PD2 repurposed from external memory interface to M_nCS8 chip select.
Pin 15 (PD2/A12/MCDA6) is connected to M_nCS8 net. According to the datasheet (page 4-7), PD2 has A12 function (external bus interface address bit 12) and MCDA6 (HSMCI data 6). The pin is being used as a chip select signal for external devices instead of the external memory interface, which is acceptable when external memory is not used.PD3 repurposed from external memory interface to STEP8 stepper signal.
Pin 16 (PD3/A13/MCDA7) is connected to STEP8 net. According to the datasheet (page 4-7), PD3 has A13 function (external bus interface address bit 13) and MCDA7 (HSMCI data 7). The pin is being used as a step signal for stepper motor control instead of the external memory interface, which is acceptable when external memory is not used.PD4 repurposed from USART3 TXD3 to MIN_ES1 endstop signal.
Pin 17 (PD4/A14/TXD3) is connected to MIN_ES1 net. According to the datasheet (page 4-7), PD4 has A14 function (external bus interface address bit 14) and TXD3 (USART3 transmit data). The pin is being used as an endstop input signal instead of USART3, which is acceptable when USART3 is not needed.PD5 repurposed from USART3 RXD3 to MAX_ES2 endstop signal.
Pin 18 (PD5/A15/RXD3) is connected to MAX_ES2 net. According to the datasheet (page 4-7), PD5 has A15 function (external bus interface address bit 15) and RXD3 (USART3 receive data). The pin is being used as an endstop input signal instead of USART3, which is acceptable when USART3 is not needed.PD6 repurposed from external memory interface to MIN_ES2 endstop signal.
Pin 19 (PD6/A16/BA0/PWMFI2) is connected to MIN_ES2 net. According to the datasheet (page 4-7), PD6 has A16 function (external bus interface address bit 16), BA0 (bank address 0), and PWMFI2 (PWM fault input 2). The pin is being used as an endstop input signal instead of the external memory interface, which is acceptable when external memory is not used.PD7 repurposed from external memory interface to TACH_3 tachometer signal.
Pin 20 (PD7/A17/BA1/TIOA8) is connected to TACH_3 net. According to the datasheet (page 4-7), PD7 has A17 function (external bus interface address bit 17), BA1 (bank address 1), and TIOA8 (Timer Counter I/O A channel 8). The pin is being used as a tachometer input signal, potentially utilizing the TIOA8 timer function for frequency measurement, which is a good use of this pin's capabilities.PD8 repurposed from external memory interface to TACH_2 tachometer signal.
Pin 21 (PD8/A21/NANDALE/TIOB8) is connected to TACH_2 net. According to the datasheet (page 4-7), PD8 has A21 function (external bus interface address bit 21), NANDALE (NAND flash address latch enable), and TIOB8 (Timer Counter I/O B channel 8). The pin is being used as a tachometer input signal, potentially utilizing the TIOB8 timer function for frequency measurement, which is a good use of this pin's capabilities.PD9 repurposed from external memory interface to MAX_ES3 endstop signal.
Pin 22 (PD9/A22/NANDCLE/TCLK8) is connected to MAX_ES3 net. According to the datasheet (page 4-7), PD9 has A22 function (external bus interface address bit 22), NANDCLE (NAND flash command latch enable), and TCLK8 (Timer Counter external clock 8). The pin is being used as an endstop input signal instead of the external memory interface, which is acceptable when external memory is not used.PA0 correctly configured as CAN0 transmit (CANTX0).
Pin 23 (PA0/CANTX0/PWML3) is connected to PA0_CANTX0 net. According to the datasheet (page 4-7), PA0 has CANTX0 function which is CAN0 transmit. This connection is correct for CAN bus communication functionality.PA1 correctly configured as CAN0 receive (CANRX0).
Pin 24 (PA1/CANRX0/PCK0/WKUP0) is connected to PA1_CANRX0 net. According to the datasheet (page 4-7), PA1 has CANRX0 function which is CAN0 receive. This connection is correct for CAN bus communication functionality.PA5 repurposed from timer function to PA5_PWM signal.
Pin 25 (PA5/TIOA2/PWMFI0/WKUP2) is connected to PA5_PWM net. According to the datasheet (page 4-7), PA5 has TIOA2 function (Timer Counter I/O A channel 2) and PWMFI0 (PWM fault input 0). The pin is being used for PWM generation, which could utilize the TIOA2 timer function. This is a correct use of this pin's capabilities.PA7 repurposed from external memory interface to MIN_ES3 endstop signal.
Pin 26 (PA7/TCLK2/NCS1/WKUP3) is connected to MIN_ES3 net. According to the datasheet (page 4-7), PA7 has TCLK2 function (Timer Counter external clock 2), NCS1 (chip select 1), and WKUP3 (wake-up input 3). The pin is being used as an endstop input signal instead of the external memory interface, which is acceptable when external memory is not used.PA8 correctly configured as UART receive data (URXD).
Pin 27 (PA8/URXD/PWMH0/WKUP4) is connected to PA8_URXD net. According to the datasheet (page 4-7), PA8 has URXD function which is UART receive data. This connection is correct for UART communication functionality.PB28 correctly configured as JTAG/SWD clock (TCK/SWCLK).
Pin 28 (PB28/TCK/SWCLK) is connected to TCK/SWDCLK net. According to the datasheet (page 4-7), PB28 has TCK function (JTAG test clock) and SWCLK (Serial Wire Debug clock). This connection is correct for JTAG/SWD debugging interface.PB31 correctly configured as JTAG/SWD mode select (TMS/SWDIO).
Pin 31 (PB31/TMS/SWDIO) is connected to TMS/SWDIO net. According to the datasheet (page 4-7), PB31 has TMS function (JTAG test mode select) and SWDIO (Serial Wire Debug data I/O). This connection is correct for JTAG/SWD debugging interface.PD10 repurposed from external memory interface to MAX_ES1 endstop signal.
Pin 32 (PD10/NWR1/NBS1) is connected to MAX_ES1 net. According to the datasheet (page 4-7), PD10 has NWR1 function (external bus interface write strobe 1) and NBS1 (byte select 1). The pin is being used as an endstop input signal instead of the external memory interface, which is acceptable when external memory is not used.PC1 configured as LED_Y signal for yellow LED control.
Pin 55 (PC1) is connected to LED_Y net. According to the datasheet (page 4-7), PC1 is a general purpose I/O pin. The pin is being used to control a yellow LED, which is a standard use for a GPIO pin.PC2 configured as PWM output (PWML0).
Pin 59 (PC2/D0/PWML0) is connected to PC2_PWML0 net. According to the datasheet (page 4-7), PC2 has D0 function (external bus interface data bit 0) and PWML0 (PWM low output 0). The pin is being used for PWM generation instead of the external memory interface, which is acceptable when external memory is not used.PC3 configured as LED_R signal for red LED control.
Pin 60 (PC3/D1/PWMH0) is connected to LED_R net. According to the datasheet (page 4-7), PC3 has D1 function (external bus interface data bit 1) and PWMH0 (PWM high output 0). The pin is being used to control a red LED instead of the external memory interface or PWM, which is acceptable when these functions are not needed.PC5 repurposed from external memory interface to DIAG1 diagnostic signal.
Pin 63 (PC5/D3/PWMH1) is connected to DIAG1 net. According to the datasheet (page 4-7), PC5 has D3 function (external bus interface data bit 3) and PWMH1 (PWM high output 1). The pin is being used as a diagnostic signal instead of the external memory interface, which is acceptable when external memory is not used.PC6 repurposed from external memory interface to DIR1 direction signal.
Pin 64 (PC6/D4/PWML2) is connected to DIR1 net. According to the datasheet (page 4-7), PC6 has D4 function (external bus interface data bit 4) and PWML2 (PWM low output 2). The pin is being used as a direction signal for stepper motor control instead of the external memory interface, which is acceptable when external memory is not used.PC7 repurposed from external memory interface to STEP1 stepper signal.
Pin 65 (PC7/D5/PWMH2) is connected to STEP1 net. According to the datasheet (page 4-7), PC7 has D5 function (external bus interface data bit 5) and PWMH2 (PWM high output 2). The pin is being used as a step signal for stepper motor control instead of the external memory interface, which is acceptable when external memory is not used.PC8 configured as PWM output (PWML3).
Pin 66 (PC8/D6/PWML3) is connected to PC8_PWML3 net. According to the datasheet (page 4-7), PC8 has D6 function (external bus interface data bit 6) and PWML3 (PWM low output 3). The pin is being used for PWM generation instead of the external memory interface, which is acceptable when external memory is not used.PC9 repurposed from external memory interface to DRV_EN driver enable signal.
Pin 67 (PC9/D7/PWMH3) is connected to DRV_EN net. According to the datasheet (page 4-7), PC9 has D7 function (external bus interface data bit 7) and PWMH3 (PWM high output 3). The pin is being used as a driver enable signal instead of the external memory interface, which is acceptable when external memory is not used.PB27 configured as timer I/O (TIOB0).
Pin 68 (PB27/NCS3/TIOB0) is connected to PB27_TIOB0 net. According to the datasheet (page 4-7), PB27 has NCS3 function (chip select 3) and TIOB0 (Timer Counter I/O B channel 0). The pin is being used for timer functionality instead of the external memory interface, which is acceptable when external memory is not used.PA18 correctly configured as TWI0 clock line (SCL).
Pin 70 (PA18/TWCK0/A20/WKUP9) is connected to PA18_SCL net. According to the datasheet (page 4-7), PA18 has TWCK0 function which is TWI0 (I2C) clock line. The net name PA18_SCL correctly indicates this is the I2C SCL signal. This connection is correct for I2C communication.PA19 correctly configured as HSMCI clock (MCCK).
Pin 71 (PA19/MCCK/PWMH1) is connected to MCCK net. According to the datasheet (page 4-7), PA19 has MCCK function which is HSMCI (SD/MMC) clock. This connection is correct for SD card interface functionality.PA20 correctly configured as HSMCI command/data (MCCDA).
Pin 72 (PA20/MCCDA/PWML2) is connected to MCCDA net. According to the datasheet (page 4-7), PA20 has MCCDA function which is HSMCI command/data A. This connection is correct for SD card interface functionality.PB15 repurposed from CAN1 receive and DAC0 to Fan3 control signal.
Pin 76 (PB15/CANRX1/PWMH3/DAC0/WKUP12) is connected to Fan3 net. According to the datasheet (page 4-7), PB15 has CANRX1 function (CAN1 receive), PWMH3 (PWM high output 3), and DAC0 (DAC channel 0 output). The pin is being used for fan control instead of CAN1 or DAC functionality, which is acceptable when these functions are not needed. However, note that this repurposes the DAC0 output.PB16 repurposed from DAC1 to Fan4 control signal.
Pin 77 (PB16/TCLK5/PWML0/DAC1) is connected to Fan4 net. According to the datasheet (page 4-7), PB16 has TCLK5 function (Timer Counter external clock 5), PWML0 (PWM low output 0), and DAC1 (DAC channel 1 output). The pin is being used for fan control instead of DAC functionality, which is acceptable when DAC is not needed. However, note that this repurposes the DAC1 output.PA16 configured as general purpose I/O.
Pin 78 (PA16/SPCK1/TD/AD7) is connected to PA16 net. According to the datasheet (page 4-7), PA16 has SPCK1 function (SPI1 serial clock), TD (SSC transmit data), and AD7 (ADC input 7). The pin is being used as a general purpose I/O instead of these specific functions, which is acceptable when they are not needed.PA24 correctly configured as HSMCI data 3 (MCDA3).
Pin 79 (PA24/MCDA3/PCK1/AD6) is connected to MCDA3 net. According to the datasheet (page 4-7), PA24 has MCDA3 function which is HSMCI data A bit 3. This connection is correct for SD card interface functionality.PA23 correctly configured as HSMCI data 2 (MCDA2).
Pin 80 (PA23/MCDA2/TCLK4/AD5) is connected to MCDA2 net. According to the datasheet (page 4-7), PA23 has MCDA2 function which is HSMCI data A bit 2. This connection is correct for SD card interface functionality.PA22 correctly configured as HSMCI data 1 (MCDA1).
Pin 81 (PA22/MCDA1/TCLK3/AD4) is connected to MCDA1 net. According to the datasheet (page 4-7), PA22 has MCDA1 function which is HSMCI data A bit 1. This connection is correct for SD card interface functionality.PA6 repurposed from external memory interface to TC_nCS3 chip select.
Pin 82 (PA6/TIOB2/NCS0/AD3) is connected to TC_nCS3 net. According to the datasheet (page 4-7), PA6 has TIOB2 function (Timer Counter I/O B channel 2), NCS0 (chip select 0), and AD3 (ADC input 3). The pin is being used as a chip select signal for thermocouple interface, which is acceptable when the external memory interface is not used.PA4 repurposed from external memory interface to M_nCS1 chip select.
Pin 83 (PA4/TCLK1/NWAIT/AD2) is connected to M_nCS1 net. According to the datasheet (page 4-7), PA4 has TCLK1 function (Timer Counter external clock 1), NWAIT (external bus interface wait), and AD2 (ADC input 2). The pin is being used as a chip select signal instead of the external memory interface, which is acceptable when external memory is not used.PA3 configured as ADC input (AD1) but net name suggests AD2.
Pin 84 (PA3/TIOB1/PWMFI1/AD1/WKUP1) is connected to PA3_AD2 net. According to the datasheet (page 4-7), PA3 has AD1 function (ADC input 1), but the net name suggests AD2. This appears to be a naming inconsistency where the net name doesn't match the actual ADC channel. The connection is functionally correct for ADC usage, but the naming could be confusing.PA2 repurposed from timer and ADC functions to TC_nCS4 chip select.
Pin 85 (PA2/TIOA1/NANDRDY/AD0) is connected to TC_nCS4 net. According to the datasheet (page 4-7), PA2 has TIOA1 function (Timer Counter I/O A channel 1), NANDRDY (NAND flash ready), and AD0 (ADC input 0). The pin is being used as a chip select signal for thermocouple interface instead of timer or ADC functionality, which is acceptable when these functions are not needed.PB12 repurposed from TWI1 data line to ADC input (AD8).
Pin 86 (PB12/TWD1/PWMH0/AD8) is connected to PB12_AD8 net. According to the datasheet (page 4-7), PB12 has TWD1 function (TWI1 data line), PWMH0 (PWM high output 0), and AD8 (ADC input 8). The pin is being used for ADC functionality instead of TWI1, which is acceptable when TWI1 is not needed.PB13 repurposed from TWI1 clock line to ADC input (AD9).
Pin 87 (PB13/TWCK1/PWMH1/AD9) is connected to PB13_AD9 net. According to the datasheet (page 4-7), PB13 has TWCK1 function (TWI1 clock line), PWMH1 (PWM high output 1), and AD9 (ADC input 9). The pin is being used for ADC functionality instead of TWI1, which is acceptable when TWI1 is not needed.PB17 repurposed from SSC receive frame sync to TC_nCS5 chip select.
Pin 88 (PB17/RF/PWML1/AD10) is connected to TC_nCS5 net. According to the datasheet (page 4-7), PB17 has RF function (SSC receive frame sync), PWML1 (PWM low output 1), and AD10 (ADC input 10). The pin is being used as a chip select signal for thermocouple interface instead of SSC functionality, which is acceptable when SSC is not needed.PB18 repurposed from SSC receive data to THERM_AN2 thermistor input.
Pin 89 (PB18/RD/PWML2/AD11) is connected to THERM_AN2 net. According to the datasheet (page 4-7), PB18 has RD function (SSC receive data), PWML2 (PWM low output 2), and AD11 (ADC input 11). The pin is being used for thermistor analog input, likely utilizing the AD11 ADC function, which is a good use of this pin's capabilities.PB19 repurposed from SSC receive clock to THERM_AN1 thermistor input.
Pin 90 (PB19/RK/PWML3/AD12) is connected to THERM_AN1 net. According to the datasheet (page 4-7), PB19 has RK function (SSC receive clock), PWML3 (PWM low output 3), and AD12 (ADC input 12). The pin is being used for thermistor analog input, likely utilizing the AD12 ADC function, which is a good use of this pin's capabilities.PB20 repurposed from USART2 transmit to THERM_AN3 thermistor input.
Pin 91 (PB20/TXD2/SPI0_NPCS1/AD13) is connected to THERM_AN3 net. According to the datasheet (page 4-7), PB20 has TXD2 function (USART2 transmit data), SPI0_NPCS1 (SPI0 chip select 1), and AD13 (ADC input 13). The pin is being used for thermistor analog input, likely utilizing the AD13 ADC function, which is a good use of this pin's capabilities when USART2 is not needed.PB21 repurposed from USART2 receive to SPIFLASH_CS chip select.
Pin 92 (PB21/RXD2/SPI0_NPCS2/AD14/WKUP13) is connected to SPIFLASH_CS net. According to the datasheet (page 4-7), PB21 has RXD2 function (USART2 receive data), SPI0_NPCS2 (SPI0 chip select 2), and AD14 (ADC input 14). The pin is being used as a chip select for SPI flash, potentially utilizing the SPI0_NPCS2 function, which is a good use of this pin's capabilities when USART2 is not needed.PC11 repurposed from external memory interface to DIAG2 diagnostic signal.
Pin 93 (PC11/D9/ERX2) is connected to DIAG2 net. According to the datasheet (page 4-7), PC11 has D9 function (external bus interface data bit 9) and ERX2 (Ethernet receive data 2). The pin is being used as a diagnostic signal instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PC12 repurposed from external memory interface to DIR2 direction signal.
Pin 94 (PC12/D10/ERX3) is connected to DIR2 net. According to the datasheet (page 4-7), PC12 has D10 function (external bus interface data bit 10) and ERX3 (Ethernet receive data 3). The pin is being used as a direction signal for stepper motor control instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PC13 repurposed from external memory interface to STEP2 stepper signal.
Pin 95 (PC13/D11/ECOL) is connected to STEP2 net. According to the datasheet (page 4-7), PC13 has D11 function (external bus interface data bit 11) and ECOL (Ethernet collision). The pin is being used as a step signal for stepper motor control instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PC14 repurposed from external memory interface to M_nCS2 chip select.
Pin 96 (PC14/D12/ERXCK) is connected to M_nCS2 net. According to the datasheet (page 4-7), PC14 has D12 function (external bus interface data bit 12) and ERXCK (Ethernet receive clock). The pin is being used as a chip select signal instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PC15 repurposed from external memory interface to DIAG3 diagnostic signal.
Pin 97 (PC15/D13/ETX2) is connected to DIAG3 net. According to the datasheet (page 4-7), PC15 has D13 function (external bus interface data bit 13) and ETX2 (Ethernet transmit data 2). The pin is being used as a diagnostic signal instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PC16 repurposed from external memory interface to DIR3 direction signal.
Pin 98 (PC16/D14/ETX3) is connected to DIR3 net. According to the datasheet (page 4-7), PC16 has D14 function (external bus interface data bit 14) and ETX3 (Ethernet transmit data 3). The pin is being used as a direction signal for stepper motor control instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PC17 repurposed from external memory interface to STEP3 stepper signal.
Pin 99 (PC17/D15/ETXER) is connected to STEP3 net. According to the datasheet (page 4-7), PC17 has D15 function (external bus interface data bit 15) and ETXER (Ethernet transmit error). The pin is being used as a step signal for stepper motor control instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PC18 repurposed from external memory interface to M_nCS3 chip select.
Pin 100 (PC18/NWR0/NWE/PWMH6) is connected to M_nCS3 net. According to the datasheet (page 4-7), PC18 has NWR0 function (external bus interface write strobe 0), NWE (write enable), and PWMH6 (PWM high output 6). The pin is being used as a chip select signal instead of the external memory interface, which is acceptable when external memory is not used.PC19 repurposed from NAND flash interface to DIAG4 diagnostic signal.
Pin 101 (PC19/NANDOE/PWMH5) is connected to DIAG4 net. According to the datasheet (page 4-7), PC19 has NANDOE function (NAND flash output enable) and PWMH5 (PWM high output 5). The pin is being used as a diagnostic signal instead of NAND flash interface, which is acceptable when NAND flash is not used.PC29 repurposed from external memory interface to TACH_4 tachometer signal.
Pin 102 (PC29/A8/TIOB7) is connected to TACH_4 net. According to the datasheet (page 4-7), PC29 has A8 function (external bus interface address bit 8) and TIOB7 (Timer Counter I/O B channel 7). The pin is being used as a tachometer input signal, potentially utilizing the TIOB7 timer function for frequency measurement, which is a good use of this pin's capabilities.PC30 repurposed from external memory interface to HOLD# SPI flash signal.
Pin 103 (PC30/A9/TCLK7) is connected to HOLD# net. According to the datasheet (page 4-7), PC30 has A9 function (external bus interface address bit 9) and TCLK7 (Timer Counter external clock 7). The pin is being used as a hold signal for SPI flash interface instead of the external memory interface, which is acceptable when external memory is not used.PA21 correctly configured as HSMCI data 0 (MCDA0).
Pin 107 (PA21/MCDA0/PWML0) is connected to MCDA0 net. According to the datasheet (page 4-7), PA21 has MCDA0 function which is HSMCI data A bit 0. This connection is correct for SD card interface functionality.PA25 correctly configured as SPI0 MISO with series resistor buffering.
Pin 108 (PA25/SPI0_MISO/A18) is connected to NetR83_2 net, which connects through resistor R83 to PA25_MISO. According to the datasheet (page 4-7), PA25 has SPI0_MISO function (SPI0 master in slave out). The series resistor provides signal integrity and protection, which is a good design practice for SPI interfaces.PA26 correctly configured as SPI0 MOSI with series resistor buffering.
Pin 109 (PA26/SPI0_MOSI/A19) is connected to NetR77_2 net, which connects through resistor R77 to PA26_MOSI_D. According to the datasheet (page 4-7), PA26 has SPI0_MOSI function (SPI0 master out slave in). The series resistor provides signal integrity and protection, which is a good design practice for SPI interfaces.PA27 correctly configured as SPI0 clock with series resistor buffering.
Pin 110 (PA27/SPI0_SPCK/A20/WKUP10) is connected to NetR82_2 net, which connects through resistor R82 to NetC64_2. According to the datasheet (page 4-7), PA27 has SPI0_SPCK function (SPI0 serial clock). The series resistor provides signal integrity and protection, which is a good design practice for SPI interfaces.PA28 correctly configured as SPI0 chip select 0 (NPCS0).
Pin 111 (PA28/SPI0_NPCS0/PCK2/WKUP11) is connected to PA28_CS0 net. According to the datasheet (page 4-7), PA28 has SPI0_NPCS0 function (SPI0 chip select 0). This connection is correct for SPI interface functionality.PA29 correctly configured as SPI0 chip select 1 (NPCS1).
Pin 112 (PA29/SPI0_NPCS1/NRD) is connected to PA29_CS net. According to the datasheet (page 4-7), PA29 has SPI0_NPCS1 function (SPI0 chip select 1). This connection is correct for SPI interface functionality.PB0 repurposed from Ethernet transmit clock to PB0_ETXCK signal.
Pin 113 (PB0/ETXCK/EREFCK) is connected to PB0_ETXCK net. According to the datasheet (page 4-7), PB0 has ETXCK function (Ethernet transmit clock) and EREFCK (Ethernet reference clock). The pin is being used for a signal that maintains the Ethernet naming but may not be used for actual Ethernet functionality, which is acceptable when Ethernet is not used.PB1 repurposed from Ethernet transmit enable to PB1_ETXEN signal.
Pin 114 (PB1/ETXEN) is connected to PB1_ETXEN net. According to the datasheet (page 4-7), PB1 has ETXEN function (Ethernet transmit enable). The pin is being used for a signal that maintains the Ethernet naming but may not be used for actual Ethernet functionality, which is acceptable when Ethernet is not used.PB2 repurposed from Ethernet transmit data to PB2_ETX0 signal.
Pin 115 (PB2/ETX0) is connected to PB2_ETX0 net. According to the datasheet (page 4-7), PB2 has ETX0 function (Ethernet transmit data 0). The pin is being used for a signal that maintains the Ethernet naming but may not be used for actual Ethernet functionality, which is acceptable when Ethernet is not used.PC4 repurposed from external memory interface to DIR4 direction signal.
Pin 116 (PC4/D2/PWML1) is connected to DIR4 net. According to the datasheet (page 4-7), PC4 has D2 function (external bus interface data bit 2) and PWML1 (PWM low output 1). The pin is being used as a direction signal for stepper motor control instead of the external memory interface, which is acceptable when external memory is not used.PC10 repurposed from external memory interface to STEP4 stepper signal.
Pin 117 (PC10/D8/ECRS) is connected to STEP4 net. According to the datasheet (page 4-7), PC10 has D8 function (external bus interface data bit 8) and ECRS (Ethernet carrier sense). The pin is being used as a step signal for stepper motor control instead of the external memory interface or Ethernet, which is acceptable when these functions are not used.PB3 repurposed from Ethernet transmit data to STEP5 stepper signal.
Pin 118 (PB3/ETX1) is connected to STEP5 net. According to the datasheet (page 4-7), PB3 has ETX1 function (Ethernet transmit data 1). The pin is being used as a step signal for stepper motor control instead of Ethernet functionality, which is acceptable when Ethernet is not used.PB4 repurposed from Ethernet carrier sense to M_nCS6 chip select.
Pin 119 (PB4/ECRSDV/ERXDV) is connected to M_nCS6 net. According to the datasheet (page 4-7), PB4 has ECRSDV function (Ethernet carrier sense/data valid) and ERXDV (Ethernet receive data valid). The pin is being used as a chip select signal instead of Ethernet functionality, which is acceptable when Ethernet is not used.PB5 repurposed from Ethernet receive data to M_nCS5 chip select.
Pin 120 (PB5/ERX0) is connected to M_nCS5 net. According to the datasheet (page 4-7), PB5 has ERX0 function (Ethernet receive data 0). The pin is being used as a chip select signal instead of Ethernet functionality, which is acceptable when Ethernet is not used.PB6 repurposed from Ethernet receive data to DIR7 direction signal.
Pin 121 (PB6/ERX1) is connected to DIR7 net. According to the datasheet (page 4-7), PB6 has ERX1 function (Ethernet receive data 1). The pin is being used as a direction signal for stepper motor control instead of Ethernet functionality, which is acceptable when Ethernet is not used.PB7 repurposed from Ethernet receive error to MAX_ES4 endstop signal.
Pin 122 (PB7/ERXER) is connected to MAX_ES4 net. According to the datasheet (page 4-7), PB7 has ERXER function (Ethernet receive error). The pin is being used as an endstop input signal instead of Ethernet functionality, which is acceptable when Ethernet is not used.PB8 repurposed from Ethernet management data clock to STEP7 stepper signal.
Pin 123 (PB8/EMDC) is connected to STEP7 net. According to the datasheet (page 4-7), PB8 has EMDC function (Ethernet management data clock). The pin is being used as a step signal for stepper motor control instead of Ethernet functionality, which is acceptable when Ethernet is not used.PB9 repurposed from Ethernet management data I/O to TC_nCS2 chip select.
Pin 127 (PB9/EMDIO) is connected to TC_nCS2 net. According to the datasheet (page 4-7), PB9 has EMDIO function (Ethernet management data I/O). The pin is being used as a chip select signal for thermocouple interface instead of Ethernet functionality, which is acceptable when Ethernet is not used.PB10 repurposed from USB OTG VBUS output to M_nCS4 chip select.
Pin 128 (PB10/UOTGVBOF/A18) is connected to M_nCS4 net. According to the datasheet (page 4-7), PB10 has UOTGVBOF function (USB OTG VBUS output) and A18 (external bus interface address bit 18). The pin is being used as a chip select signal instead of USB OTG functionality, which is acceptable when USB OTG is not used.PB11 repurposed from USB OTG ID to SDCD SD card detect signal.
Pin 129 (PB11/UOTGID/A19) is connected to SDCD net. According to the datasheet (page 4-7), PB11 has UOTGID function (USB OTG ID input) and A19 (external bus interface address bit 19). The pin is being used as SD card detect signal instead of USB OTG functionality, which is acceptable when USB OTG is not used.PC0 correctly configured as ERASE input.
Pin 130 (PC0/ERASE) is connected to ERASE net. According to the datasheet (page 4-7), PC0 has ERASE function which is the flash erase input. This connection is correct for flash programming and debugging functionality.PC20 repurposed from NAND flash interface to DIAG5 diagnostic signal.
Pin 131 (PC20/NANDWE/PWMH4) is connected to DIAG5 net. According to the datasheet (page 4-7), PC20 has NANDWE function (NAND flash write enable) and PWMH4 (PWM high output 4). The pin is being used as a diagnostic signal instead of NAND flash interface, which is acceptable when NAND flash is not used.PC21 repurposed from external memory interface to HEAT1 heater control.
Pin 132 (PC21/A0/NBS0/PWML4) is connected to HEAT1 net. According to the datasheet (page 4-7), PC21 has A0 function (external bus interface address bit 0), NBS0 (byte select 0), and PWML4 (PWM low output 4). The pin is being used for heater control, potentially utilizing the PWML4 PWM function, which is a good use of this pin's capabilities when external memory is not used.PC22 repurposed from external memory interface to HEAT2 heater control.
Pin 133 (PC22/A1/PWML5) is connected to HEAT2 net. According to the datasheet (page 4-7), PC22 has A1 function (external bus interface address bit 1) and PWML5 (PWM low output 5). The pin is being used for heater control, potentially utilizing the PWML5 PWM function, which is a good use of this pin's capabilities when external memory is not used.PC23 repurposed from external memory interface to HEATBED heater control.
Pin 134 (PC23/A2/PWML6) is connected to HEATBED net. According to the datasheet (page 4-7), PC23 has A2 function (external bus interface address bit 2) and PWML6 (PWM low output 6). The pin is being used for heated bed control, potentially utilizing the PWML6 PWM function, which is a good use of this pin's capabilities when external memory is not used.PC24 repurposed from external memory interface to HEAT3 heater control.
Pin 135 (PC24/A3/PWML7) is connected to HEAT3 net. According to the datasheet (page 4-7), PC24 has A3 function (external bus interface address bit 3) and PWML7 (PWM low output 7). The pin is being used for heater control, potentially utilizing the PWML7 PWM function, which is a good use of this pin's capabilities when external memory is not used.PC25 repurposed from external memory interface to FAN2 fan control.
Pin 136 (PC25/A4/TIOA6) is connected to FAN2 net. According to the datasheet (page 4-7), PC25 has A4 function (external bus interface address bit 4) and TIOA6 (Timer Counter I/O A channel 6). The pin is being used for fan control, potentially utilizing the TIOA6 timer function for PWM generation, which is a good use of this pin's capabilities when external memory is not used.PC26 repurposed from external memory interface to FAN1 fan control.
Pin 137 (PC26/A5/TIOB6) is connected to FAN1 net. According to the datasheet (page 4-7), PC26 has A5 function (external bus interface address bit 5) and TIOB6 (Timer Counter I/O B channel 6). The pin is being used for fan control, potentially utilizing the TIOB6 timer function for PWM generation, which is a good use of this pin's capabilities when external memory is not used.PC27 repurposed from external memory interface to TC_nCS1 chip select.
Pin 138 (PC27/A6/TCLK6) is connected to TC_nCS1 net. According to the datasheet (page 4-7), PC27 has A6 function (external bus interface address bit 6) and TCLK6 (Timer Counter external clock 6). The pin is being used as a chip select signal for thermocouple interface instead of the external memory interface, which is acceptable when external memory is not used.PC28 repurposed from external memory interface to TACH_1 tachometer signal.
Pin 139 (PC28/A7/TIOA7) is connected to TACH_1 net. According to the datasheet (page 4-7), PC28 has A7 function (external bus interface address bit 7) and TIOA7 (Timer Counter I/O A channel 7). The pin is being used as a tachometer input signal, potentially utilizing the TIOA7 timer function for frequency measurement, which is a good use of this pin's capabilities.PB14 repurposed from CAN1 transmit to MIN_ES4 endstop signal.
Pin 140 (PB14/CANTX1/PWMH2) is connected to MIN_ES4 net. According to the datasheet (page 4-7), PB14 has CANTX1 function (CAN1 transmit) and PWMH2 (PWM high output 2). The pin is being used as an endstop input signal instead of CAN1 functionality, which is acceptable when CAN1 is not needed.PB22 repurposed from USART2 request to send to DIR5 direction signal.
Pin 141 (PB22/RTS2/PCK0) is connected to DIR5 net. According to the datasheet (page 4-7), PB22 has RTS2 function (USART2 request to send) and PCK0 (programmable clock output 0). The pin is being used as a direction signal for stepper motor control instead of USART2 functionality, which is acceptable when USART2 is not needed.PB23 repurposed from USART2 clear to send to DIAG6 diagnostic signal.
Pin 142 (PB23/CTS2/SPI0_NPCS3/WKUP14) is connected to DIAG6 net. According to the datasheet (page 4-7), PB23 has CTS2 function (USART2 clear to send), SPI0_NPCS3 (SPI0 chip select 3), and WKUP14 (wake-up input 14). The pin is being used as a diagnostic signal instead of USART2 or SPI functionality, which is acceptable when these functions are not needed.PB24 repurposed from USART2 serial clock to DIR6 direction signal.
Pin 143 (PB24/SCK2/NCS2) is connected to DIR6 net. According to the datasheet (page 4-7), PB24 has SCK2 function (USART2 serial clock) and NCS2 (chip select 2). The pin is being used as a direction signal for stepper motor control instead of USART2 or external memory interface functionality, which is acceptable when these functions are not needed.PB25 configured as timer I/O (TIOA0).
Pin 144 (PB25/RTS0/TIOA0) is connected to PB25_TIOA0 net. According to the datasheet (page 4-7), PB25 has RTS0 function (USART0 request to send) and TIOA0 (Timer Counter I/O A channel 0). The pin is being used for timer functionality instead of USART0, which is acceptable when USART0 flow control is not needed.U11C - ATML-ATSAM3X-LQFP-144 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
VDDCORE pins correctly connected to internal voltage regulator output (VDDOUT).
Pins 10, 45, 61, 104, and 124 are all VDDCORE pins connected to VDDOUT net. According to the datasheet (page 4-7), VDDCORE pins are the core power supply inputs that should be connected to the voltage regulator output. The VDDOUT net comes from pin 56 (VDDOUT) which is the internal voltage regulator output. This connection is correct for proper core power supply distribution.VDDCORE pins correctly connected to internal voltage regulator output (VDDOUT).
Pins 10, 45, 61, 104, and 124 are all VDDCORE pins connected to VDDOUT net. According to the datasheet (page 4-7), VDDCORE pins are the core power supply inputs that should be connected to the voltage regulator output. The VDDOUT net comes from pin 56 (VDDOUT) which is the internal voltage regulator output. This connection is correct for proper core power supply distribution.VDDCORE pins correctly connected to internal voltage regulator output (VDDOUT).
Pins 10, 45, 61, 104, and 124 are all VDDCORE pins connected to VDDOUT net. According to the datasheet (page 4-7), VDDCORE pins are the core power supply inputs that should be connected to the voltage regulator output. The VDDOUT net comes from pin 56 (VDDOUT) which is the internal voltage regulator output. This connection is correct for proper core power supply distribution.VDDCORE pins correctly connected to internal voltage regulator output (VDDOUT).
Pins 10, 45, 61, 104, and 124 are all VDDCORE pins connected to VDDOUT net. According to the datasheet (page 4-7), VDDCORE pins are the core power supply inputs that should be connected to the voltage regulator output. The VDDOUT net comes from pin 56 (VDDOUT) which is the internal voltage regulator output. This connection is correct for proper core power supply distribution.VDDCORE pins correctly connected to internal voltage regulator output (VDDOUT).
Pins 10, 45, 61, 104, and 124 are all VDDCORE pins connected to VDDOUT net. According to the datasheet (page 4-7), VDDCORE pins are the core power supply inputs that should be connected to the voltage regulator output. The VDDOUT net comes from pin 56 (VDDOUT) which is the internal voltage regulator output. This connection is correct for proper core power supply distribution.VDDIO pins correctly connected to I/O voltage supply (3.3VIO).
Pins 11, 62, 105, and 125 are all VDDIO pins connected to 3.3VIO net. According to the datasheet (page 4-7), VDDIO pins are the I/O power supply inputs. The 3.3VIO net is derived from 3.3VCC through ferrite bead FB28, providing clean power for I/O operations. This connection is correct for proper I/O power supply distribution.VDDIO pins correctly connected to I/O voltage supply (3.3VIO).
Pins 11, 62, 105, and 125 are all VDDIO pins connected to 3.3VIO net. According to the datasheet (page 4-7), VDDIO pins are the I/O power supply inputs. The 3.3VIO net is derived from 3.3VCC through ferrite bead FB28, providing clean power for I/O operations. This connection is correct for proper I/O power supply distribution.VDDIO pins correctly connected to I/O voltage supply (3.3VIO).
Pins 11, 62, 105, and 125 are all VDDIO pins connected to 3.3VIO net. According to the datasheet (page 4-7), VDDIO pins are the I/O power supply inputs. The 3.3VIO net is derived from 3.3VCC through ferrite bead FB28, providing clean power for I/O operations. This connection is correct for proper I/O power supply distribution.VDDIO pins correctly connected to I/O voltage supply (3.3VIO).
Pins 11, 62, 105, and 125 are all VDDIO pins connected to 3.3VIO net. According to the datasheet (page 4-7), VDDIO pins are the I/O power supply inputs. The 3.3VIO net is derived from 3.3VCC through ferrite bead FB28, providing clean power for I/O operations. This connection is correct for proper I/O power supply distribution.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.All ground pins correctly connected to system ground (GND).
Pins 12, 33, 44, 54, 58, 74, 106, and 126 are various ground pins (GND, GNDPLL, GNDUTMI, GNDBU, GNDANA) all connected to GND net. According to the datasheet (page 4-7), all ground pins should be connected to the system ground plane. This connection is correct for proper grounding.VDDPLL pin correctly connected to PLL power supply (VDDPLL).
Pin 34 (VDDPLL) is connected to VDDPLL net. According to the datasheet (page 4-7), VDDPLL is the PLL power supply input. The VDDPLL net is derived from VDDOUT through ferrite bead FB26, providing clean power for the PLL circuitry. This connection is correct for proper PLL power supply.VDDUTMI pin correctly connected to USB transceiver power supply (VDDUTMI).
Pin 41 (VDDUTMI) is connected to VDDUTMI net. According to the datasheet (page 4-7), VDDUTMI is the USB transceiver power supply input. The VDDUTMI net is derived from 3.3VCC through ferrite bead FB30, providing clean power for the USB transceiver. This connection is correct for proper USB power supply, even if USB functionality is not used.VDDBU pin correctly connected to backup power supply (3.3VCC).
Pin 52 (VDDBU) is connected to 3.3VCC net. According to the datasheet (page 4-7), VDDBU is the backup power supply input for RTC and backup registers. Connecting it to the main 3.3VCC supply is correct when a separate backup battery is not used.VDDOUT pin correctly configured as voltage regulator output.
Pin 56 (VDDOUT) is connected to VDDOUT net. According to the datasheet (page 4-7), VDDOUT is the internal voltage regulator output that provides power to the core. This pin should be connected to decoupling capacitors and used to supply the VDDCORE pins, which is correctly implemented in this design.VDDIN pin correctly connected to voltage regulator input (3.3VCC).
Pin 57 (VDDIN) is connected to 3.3VCC net. According to the datasheet (page 4-7), VDDIN is the voltage regulator input that should be connected to the main power supply. This connection is correct for powering the internal voltage regulator.VDDANA pin correctly connected to analog power supply (VDDANA).
Pin 73 (VDDANA) is connected to VDDANA net. According to the datasheet (page 4-7), VDDANA is the analog power supply input for ADC and DAC circuits. The VDDANA net is derived from 3.3VCC through ferrite bead FB27, providing clean power for analog circuits. This connection is correct for proper analog power supply.U12 - AT25SF161-SSHD-T ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
CS# pin is correctly connected to microcontroller SPI chip select with proper bus isolation.
Pin 1 (CS#) is connected to net SPIFLASH_CS, which connects to U11A pin 92 (PB21/RXD2/SPI0_NPCS2/AD14/WKUP13). The microcontroller pin PB21 can function as SPI0_NPCS2, which is the appropriate SPI chip select function. The connection also includes diode D77 (BAT54WX) with cathode on SPIFLASH_CS and anode on CS_M1BUS, providing isolation to prevent bus conflicts when other SPI devices are selected. According to the datasheet (page 7-8), 'Asserting the CS pin selects the device. When the CS pin is deasserted, the device is deselected and normally be placed in standby mode.' This connection is correct and follows good design practices for multi-device SPI buses.SO pin is correctly connected through a buffer to microcontroller MISO with proper bus conflict prevention.
Pin 2 (SO) is connected to net MISO_M1BUS, which connects to U16 pin 5 (SN74LVC125A buffer input). The buffer output (pin 6) connects through NetR94_2 and resistor R94 to PA25_MISO, which connects to U11A pin 108 (PA25/SPI0_MISO/A18). The buffer enable (pin 4) is controlled by CS_M1BUS, ensuring the flash memory's output is only active when this device is selected, preventing bus conflicts with other SPI devices sharing the MISO line. According to the datasheet (page 7-8), 'Data on the SO pin is clocked out on the falling edge of SCK' and 'The SO pin is in a high-impedance state whenever the device is deselected (CS is deasserted).' The buffering scheme properly manages multiple devices on the shared MISO line. Capacitor C75 provides signal integrity. This connection is correct.WP# pin is correctly pulled high through a 10K resistor to disable write protection.
Pin 3 (WP#) is connected to net WP#, which connects to resistor R85 pin 1. R85 pin 2 connects to 3.3VCC, creating a 10K pull-up resistor. According to the datasheet (page 7-8), 'When the Quad Enable (QE) bit of Status Register 2 is 0, and the SRP1 and SRP0 bits are 0 and 1, respectively, the pin can be used for write-protection' and 'The WP pin is internally pulled-high and can be left floating if not used.' While the internal pull-up would be sufficient, using an external 10K pull-up provides better noise immunity and ensures reliable operation. This connection correctly disables write protection functionality.GND pin is correctly connected to system ground.
Pin 4 (GND) is connected to the system ground net (GND). According to the datasheet (page 7-8), 'The ground reference for the power supply. Connect GND to the system ground.' This connection is straightforward and correct.SI/IO0 pin is correctly connected through buffering to microcontroller MOSI pin.
Pin 5 (SI/IO0) is connected to net MOSI_M1BUS, which connects to resistor R59 pin 2. R59 pin 1 connects to PA26_MOSI_D, which traces through buffer U17 back to the microcontroller's PA26/SPI0_MOSI pin (U11A pin 109). The signal path includes proper buffering for drive strength and signal integrity. According to the datasheet (page 7-8), 'The SI pin is used for all data input, including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK.' Capacitor C88 provides signal integrity. This connection is correct.SCK pin is correctly connected through a clock buffer to microcontroller SPI clock pin.
Pin 6 (SCK) is connected to net SCLK_M1BUS, which connects to resistor R13 pin 2. The signal originates from clock buffer U14 (74AVC9112) pin 7, which receives input from the microcontroller's PA27/SPI0_SPCK pin (U11A pin 110) through the buffering network. According to the datasheet (page 7-8), 'This pin provides a clock to the device. Command, address, and input data present on the SI pin is latched in on the rising edge of SCK, while output data on the SO pin is clocked out on the falling edge of SCK.' The clock buffering provides proper drive strength and signal integrity for the SPI clock. Capacitor C104 provides additional signal integrity. This connection is correct.HOLD# pin is connected to microcontroller GPIO for software control of hold functionality.
Pin 7 (HOLD#) is connected to net HOLD#, which connects to U11A pin 103 (PC30/A9/TCLK7) and test point TP78. According to the datasheet (page 7-8), 'The HOLD/IO3 pin is internally pulled-high and can be left floating if not used' and 'The HOLD pin is used to pause a SPI sequence without resetting the clocking sequence.' While the pin could be left floating, connecting it to a microcontroller GPIO allows software control of the HOLD functionality, which can be useful for advanced SPI operations or debugging. The internal pull-up ensures proper operation when the GPIO is configured as input or high-impedance. This connection is correct and provides additional functionality.VCC pin is correctly connected to 3.3V power supply within specified voltage range.
Pin 8 (VCC) is connected to net 3.3VCC, which is the 3.3V power supply rail. According to the datasheet (page 1), the device supports 'Two supply voltage options: 2.7V-3.6V and 2.5V-3.6V' and (page 7-8) 'The VCC pin supplies the source voltage to the device.' The 3.3V supply is well within the specified operating range. The power supply includes proper decoupling capacitors throughout the design. This connection is correct.J18 - 0475710001 ❌
DRCY flagged 1 potential issues in this component.
📄 DRCY referred to this Datasheet for this component.
DAT1 and DAT0 data lines are swapped - DAT1 connects to MCDA0 and DAT0 connects to MCDA1, which is incorrect.
DAT1 and DAT0 data lines are swapped - DAT1 connects to MCDA0 and DAT0 connects to MCDA1, which is incorrect.
DAT2 data line correctly connected to microcontroller MCDA2 pin with proper pullup resistor and ESD protection.
Pin 1 (DAT2) connects to net MCDA2, which routes to microcontroller pin 80 (PA23/MCDA2/TCLK4/AD5), test point TP16, 10K pullup resistor R68 to 3.3VCC, and ESD protection diode D69 to ground. This follows the standard SD card protocol where DAT2 is one of the four data lines. The pullup resistor ensures proper logic levels and the ESD protection prevents damage from electrostatic discharge. The connection to the microcontroller's dedicated MCDA2 function is correct according to the ATSAM3X datasheet.CD/DAT3 data line correctly connected to microcontroller MCDA3 pin with proper pullup resistor and ESD protection.
Pin 2 (CD/DAT3) connects to net MCDA3, which routes to microcontroller pin 79 (PA24/MCDA3/PCK1/AD6), test point TP22, 10K pullup resistor R67 to 3.3VCC, and ESD protection diode D68 to ground. This pin serves dual purpose as both card detect and data line 3 in SD protocol. The pullup resistor and ESD protection are appropriate. The connection to the microcontroller's MCDA3 function is correct.CMD command line correctly connected to microcontroller MCCDA pin with proper pullup resistor and ESD protection.
Pin 3 (CMD) connects to net MCCDA, which routes to microcontroller pin 72 (PA20/MCCDA/PWML2), test point TP15, 10K pullup resistor R65 to 3.3VCC, and ESD protection diode D66 to ground. The CMD line is used for sending commands to the SD card. The pullup resistor ensures proper logic levels during idle state and the ESD protection is appropriate. The connection to the microcontroller's dedicated MCCDA (MultiMedia Card Command/Data) function is correct.VDD power supply correctly connected to 3.3VCC rail.
Pin 4 (VDD) connects to the 3.3VCC power rail, providing power to the SD card. According to the datasheet (page 1), the connector supports '5 VDC maximum rated voltage per contact', so 3.3V operation is within specification. This is the standard operating voltage for modern SD cards and matches the microcontroller's I/O voltage levels.CLK clock line correctly connected to microcontroller MCCK pin with ESD protection.
Pin 5 (CLK) connects to net MCCK, which routes to microcontroller pin 71 (PA19/MCCK/PWMH1), test point TP21, and ESD protection diode D67 to ground. The clock line is used to synchronize data transfers with the SD card. The connection to the microcontroller's dedicated MCCK (MultiMedia Card Clock) function is correct. Note that clock lines typically don't require pullup resistors as they are actively driven.VSS ground correctly connected to system ground.
Pin 6 (VSS) connects to the GND net, providing the ground reference for the SD card. This is the standard ground connection and is correctly implemented.Shield connections correctly tied to ground for EMI protection.
Pins 9, 10, and 11 (SH) are all connected to the GND net. These are shield connections that provide electromagnetic interference (EMI) protection and mechanical grounding for the metal shell of the connector. According to the datasheet (page 1), this connector has 'Metal shell construction', and grounding the shield is the correct implementation for EMI suppression and safety.Shield connections correctly tied to ground for EMI protection.
Pins 9, 10, and 11 (SH) are all connected to the GND net. These are shield connections that provide electromagnetic interference (EMI) protection and mechanical grounding for the metal shell of the connector. According to the datasheet (page 1), this connector has 'Metal shell construction', and grounding the shield is the correct implementation for EMI suppression and safety.Shield connections correctly tied to ground for EMI protection.
Pins 9, 10, and 11 (SH) are all connected to the GND net. These are shield connections that provide electromagnetic interference (EMI) protection and mechanical grounding for the metal shell of the connector. According to the datasheet (page 1), this connector has 'Metal shell construction', and grounding the shield is the correct implementation for EMI suppression and safety.Card detect pin correctly connected to microcontroller with pullup resistor and ESD protection.
Pin 12 (CD) connects to net SDCD, which routes to microcontroller pin 129 (PB11/UOTGID/A19), test point TP13, 10K pullup resistor R64 to 3.3VCC, and ESD protection diode D42 to ground. This is one of the '2 detect pins for card presence detection' mentioned in the datasheet (page 1). The pullup resistor ensures the signal reads high when no card is present, and the card grounds this pin when inserted. The connection to a general-purpose I/O pin on the microcontroller is appropriate for card detection functionality.Card detect polarity pin correctly tied to ground.
Pin 13 (CD/POL) is connected to GND. This pin is used to set the polarity of the card detect function. By tying it to ground, the card detect signal (pin 12) will be pulled low when a card is inserted and high when no card is present. This is a standard configuration for card detect polarity and is correctly implemented.J4 - ARM Cortex JTAG-DEBUG Header ❌
DRCY flagged 1 potential issues in this component.
📄 DRCY referred to this Datasheet for this component.
TDO/SWO and TDI signals are swapped between JTAG connector and microcontroller pins.
TDO/SWO and TDI signals are swapped between JTAG connector and microcontroller pins.
VTref pin correctly connected to 3.3VCC power supply for target voltage reference.
Pin 1 connects to the 3.3VCC net which provides the target voltage reference for the JTAG interface. According to standard ARM 10-pin JTAG connector pinout, pin 1 should be VTref (target voltage reference). The connection to 3.3VCC is correct as this provides the reference voltage that the debug probe uses to determine the logic levels of the target device.TMS/SWDIO pin correctly connected to microcontroller PB31/TMS/SWDIO.
Pin 2 connects to net TMS/SWDIO which goes to microcontroller U11A pin 31 (PB31/TMS/SWDIO). According to standard ARM JTAG pinout, pin 2 should be TMS/SWDIO (Test Mode Select/Serial Wire Debug Data I/O). The microcontroller pin PB31 is correctly identified as TMS/SWDIO in the pin name, making this connection correct.Ground pin correctly connected to GND.
Pin 3 connects to the GND net. According to standard ARM JTAG pinout, pin 3 should be ground. This connection is correct.TCK/SWDCLK pin correctly connected to microcontroller PB28/TCK/SWCLK.
Pin 4 connects to net TCK/SWDCLK which goes to microcontroller U11A pin 28 (PB28/TCK/SWCLK). According to standard ARM JTAG pinout, pin 4 should be TCK/SWDCLK (Test Clock/Serial Wire Debug Clock). The microcontroller pin PB28 is correctly identified as TCK/SWCLK in the pin name, making this connection correct.Ground pin correctly connected to GND.
Pin 5 connects to the GND net. According to standard ARM JTAG pinout, pin 5 should be ground. This connection is correct.Key pin correctly left unconnected.
Pin 7 connects to net 'unconnected-(NetJ4_7)' indicating it is intentionally left unconnected. According to standard ARM JTAG pinout, pin 7 is the key pin which should not be connected. This is correct.Ground pin correctly connected to GND.
Pin 9 connects to the GND net. According to standard ARM JTAG pinout, pin 9 should be ground. This connection is correct.Reset pin correctly connected to RESET signal.
Pin 10 connects to the RESET net which is part of the reset circuitry including switch S1 and connects to the microcontroller's reset functionality. According to standard ARM JTAG pinout, pin 10 should be nRESET. This connection is correct for providing debug probe control over the target reset.U14 - 74AVC9112 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
VCC supply pin correctly connected to 3.3VCC power rail.
Pin 1 is the VCC supply voltage input according to the datasheet (page 3). It is connected to 3.3VCC which provides 3.3V power. The datasheet specifies a wide supply voltage range of 0.8V to 3.6V (page 2), so 3.3V is well within the acceptable range. This connection is correct and provides proper power to the device.Data input A connected to NetC64_2, which appears to be a clock signal input through a capacitive coupling network.
Pin 2 is the data input (A) according to the datasheet (page 3). It connects to NetC64_2, which is connected to capacitor C64 pin 2 (C64 pin 1 connects to GND). This forms a capacitive coupling network. The signal also connects through R82 to NetR82_2. Based on the circuit topology and the fact that this is a 1-to-4 fan-out buffer suitable for clock distribution (datasheet page 1), this appears to be receiving a clock signal that will be distributed to multiple SPI buses. The capacitive coupling may be used for AC coupling or signal conditioning. This connection is appropriate for the intended clock distribution function.Output enable (nOE) correctly tied to GND to permanently enable all outputs.
Pin 3 is the output enable input (OE) which is active LOW according to the datasheet (page 3). The function table shows that when OE is LOW, outputs follow input A, and when OE is HIGH, all outputs are LOW (datasheet page 1). By connecting nOE to GND (LOW), all four outputs are permanently enabled and will follow the input signal on pin 2. This is the correct configuration for a clock distribution buffer where you want all outputs active simultaneously.Ground pin correctly connected to system ground.
Pin 4 is the ground (GND) connection according to the datasheet (page 3). It is properly connected to the system ground rail (GND net). This provides the reference voltage and return path for the device. The connection is correct.Output Y1 drives SCLK_TCBUS through series resistor R3 for thermocouple bus clock distribution.
Pin 5 is data output Y1 according to the datasheet (page 3). It connects to NetR3_2, which connects to R3 pin 2. R3 pin 1 connects to SCLK_TCBUS. R3 is a 47Ω series resistor that provides signal integrity and current limiting for the clock signal going to the thermocouple bus. This is a proper clock distribution connection where the buffered clock signal is sent to one of the SPI buses through a series resistor for signal conditioning.Output Y2 drives PA27_SCLK through series resistor R4, providing buffered clock back to microcontroller pin.
Pin 6 is data output Y2 according to the datasheet (page 3). It connects to NetR4_2, which connects to R4 pin 2. R4 pin 1 connects to PA27_SCLK. R4 is a 47Ω series resistor. PA27_SCLK connects to various external connectors (J20 pin 2, test points). This output provides a buffered and conditioned version of the clock signal for external use, separate from the direct microcontroller output. The series resistor provides signal integrity. This connection is correct for clock distribution.Output Y3 drives SCLK_M1BUS through series resistor R13 for motor bus 1 clock distribution.
Pin 7 is data output Y3 according to the datasheet (page 3). It connects to NetR13_2, which connects to R13 pin 2. R13 pin 1 connects to SCLK_M1BUS. R13 is a 47Ω series resistor that provides signal integrity for the clock signal going to motor bus 1. This follows the same pattern as the other clock distribution outputs and is correctly implemented for distributing the buffered clock signal to one of the motor control SPI buses.Output Y4 drives SCLK_M2BUS through series resistor R32 for motor bus 2 clock distribution.
Pin 8 is data output Y4 according to the datasheet (page 3). It connects to NetR32_2, which connects to R32 pin 2. R32 pin 1 connects to SCLK_M2BUS. R32 is a 47Ω series resistor that provides signal integrity for the clock signal going to motor bus 2. This completes the 1-to-4 clock distribution, sending the buffered clock signal to the second motor control SPI bus through appropriate series resistance for signal conditioning.No Connect pin correctly left unconnected.
Pin 23 is marked as NC (No Connect) in the schematic and has no electrical connection. This is correct as NC pins should not be connected to anything. The pin designation matches the component's intended usage.U16 - SN74LVC125A ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Output enable nOE1 connected to CS_TCBUS to enable buffer 1 when thermocouple bus is selected.
Pin 1 is the output enable for buffer 1 (1OE) which is active LOW according to the datasheet (page 3). It is connected to CS_TCBUS. When CS_TCBUS is LOW (active), this buffer is enabled, allowing MISO_TCBUS to pass through to the shared MISO line. When CS_TCBUS is HIGH (inactive), the output is in high-impedance state, preventing bus conflicts. This implements proper SPI bus multiplexing where only one MISO source can drive the shared line at a time.Input A1 receives MISO_TCBUS signal from thermocouple bus.
Pin 2 is input A1 for buffer 1 according to the datasheet (page 3). It is connected to MISO_TCBUS, which is the MISO (Master In, Slave Out) signal from the thermocouple bus. When buffer 1 is enabled (nOE1 LOW), this signal will be passed to output Y1. This is the correct connection for multiplexing the thermocouple bus MISO signal onto the shared MISO line back to the microcontroller.Output Y1 drives shared MISO line through NetR94_2 when thermocouple bus is selected.
Pin 3 is output Y1 for buffer 1 according to the datasheet (page 3). It connects to NetR94_2, which connects to R94 pin 2. R94 pin 1 connects to PA25_MISO, which goes back to the microcontroller's MISO input. When CS_TCBUS is active (LOW), this output will drive the thermocouple MISO signal to the microcontroller through the series resistor R94 (47Ω) which provides signal integrity. This is correct for the MISO multiplexing scheme.Output enable nOE2 connected to CS_M1BUS to enable buffer 2 when motor bus 1 is selected.
Pin 4 is the output enable for buffer 2 (2OE) which is active LOW according to the datasheet (page 3). It is connected to CS_M1BUS. When CS_M1BUS is LOW (active), this buffer is enabled, allowing MISO_M1BUS to pass through to the shared MISO line. When CS_M1BUS is HIGH (inactive), the output is in high-impedance state. This correctly implements the multiplexing control for motor bus 1 MISO signal.Input A2 receives MISO_M1BUS signal from motor bus 1.
Pin 5 is input A2 for buffer 2 according to the datasheet (page 3). It is connected to MISO_M1BUS, which is the MISO signal from motor bus 1. When buffer 2 is enabled (nOE2 LOW), this signal will be passed to output Y2. This is the correct connection for multiplexing the motor bus 1 MISO signal onto the shared MISO line.Output Y2 drives shared MISO line through NetR94_2 when motor bus 1 is selected.
Pin 6 is output Y2 for buffer 2 according to the datasheet (page 3). It connects to NetR94_2, the same net as Y1 (pin 3). This creates a wired-OR configuration where multiple outputs connect to the same line, but only one should be enabled at a time through the nOE controls. When CS_M1BUS is active, this output drives the motor bus 1 MISO signal to the shared line going back to the microcontroller. The connection is correct for the multiplexing implementation.Ground pin correctly connected to system ground.
Pin 7 is the ground connection according to the datasheet (page 3). It is properly connected to the system ground rail (GND net). This provides the reference voltage and return path for the device. The connection is correct.Output Y3 drives shared MISO line through NetR94_2 when motor bus 2 is selected.
Pin 8 is output Y3 for buffer 3 according to the datasheet (page 3). It connects to NetR94_2, the same shared MISO net as the other outputs. When CS_M2BUS is active (enabling buffer 3 through nOE3), this output will drive the motor bus 2 MISO signal to the shared line. This continues the proper wired-OR multiplexing implementation where only one buffer should be active at a time.Input A3 receives MISO_M2BUS signal from motor bus 2.
Pin 9 is input A3 for buffer 3 according to the datasheet (page 3). It is connected to MISO_M2BUS, which is the MISO signal from motor bus 2. When buffer 3 is enabled (nOE3 LOW), this signal will be passed to output Y3. This is the correct connection for multiplexing the motor bus 2 MISO signal onto the shared MISO line.Output enable nOE3 connected to CS_M2BUS to enable buffer 3 when motor bus 2 is selected.
Pin 10 is the output enable for buffer 3 (3OE) which is active LOW according to the datasheet (page 3). It is connected to CS_M2BUS. When CS_M2BUS is LOW (active), this buffer is enabled, allowing MISO_M2BUS to pass through to the shared MISO line. This correctly implements the multiplexing control for motor bus 2 MISO signal, completing the three-way MISO multiplexing scheme.Output Y4 is unused and connected to an unconnected net, which is acceptable for an unused buffer.
Pin 11 is output Y4 for buffer 4 according to the datasheet (page 3). It is connected to 'unconnected-(NetU16_11)', indicating this output is not used in the design. Since buffer 4 is not needed for the three-way MISO multiplexing (thermocouple, motor bus 1, motor bus 2), leaving this output unconnected is acceptable. The output will be in a defined state based on the input A4 and enable nOE4 conditions.Input A4 tied to GND since buffer 4 is unused.
Pin 12 is input A4 for buffer 4 according to the datasheet (page 3). It is connected to GND. Since buffer 4 is not used in this design, tying the input to a defined logic level (GND = LOW) is good practice to prevent floating inputs. This ensures the unused buffer has a predictable input state. The datasheet layout guidelines (section on mixed voltage operation) recommend that unused inputs should be tied to appropriate logic levels.Output enable nOE4 tied to GND, permanently enabling unused buffer 4.
Pin 13 is the output enable for buffer 4 (4OE) which is active LOW according to the datasheet (page 3). It is connected to GND (LOW), which permanently enables buffer 4. Since A4 is tied to GND, Y4 will be driven LOW when enabled. While this seems unusual to enable an unused buffer, it ensures Y4 has a defined output state (LOW) rather than being in high-impedance. Since Y4 is not connected to anything critical, this does not cause problems and may be intentional to avoid floating outputs.VCC supply pin correctly connected to 3.3VCC power rail.
Pin 14 is the VCC positive supply according to the datasheet (page 3). It is connected to 3.3VCC which provides 3.3V power. The datasheet specifies the device operates from 1.65V to 3.6V (page 1), so 3.3V is within the acceptable range. This connection provides proper power to the device.Thermal pad correctly connected to ground for heat dissipation.
Pin 15 is the PAD (thermal pad) connection. It is connected to GND, which is the standard practice for thermal pads to provide a heat dissipation path to the ground plane. The datasheet power supply recommendations (section 8.1.2) indicate proper grounding is important for device operation. Connecting the thermal pad to ground is correct for both thermal and electrical performance.No Connect pin correctly left unconnected.
Pin 23 is marked as NC (No Connect) in the schematic and has no electrical connection. This is correct as NC pins should not be connected to anything. The pin designation matches the component's intended usage.U17 - SN74LVC125A ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Output enable nOE1 tied to GND to permanently enable buffer 1 for MOSI distribution.
Pin 1 is the output enable for buffer 1 (1OE) which is active LOW according to the datasheet (page 3). It is connected to GND (LOW), which permanently enables buffer 1. This allows the MOSI signal on A1 to always pass through to Y1. Since MOSI is a broadcast signal that needs to go to all SPI devices simultaneously (unlike MISO which is multiplexed), permanently enabling this buffer is correct for MOSI distribution to the thermocouple bus.Input A1 receives PA26_MOSI_D signal from microcontroller for distribution to thermocouple bus.
Pin 2 is input A1 for buffer 1 according to the datasheet (page 3). It is connected to PA26_MOSI_D, which comes from the microcontroller's MOSI output through resistor R77. This signal will be buffered and sent to the thermocouple bus. The connection is correct for distributing the MOSI signal from the microcontroller to one of the SPI buses.Output Y1 drives MOSI_TCBUS through series resistor R84 for thermocouple bus.
Pin 3 is output Y1 for buffer 1 according to the datasheet (page 3). It connects to NetR84_2, which connects to R84 pin 2. R84 pin 1 connects to MOSI_TCBUS. R84 is a 47Ω series resistor that provides signal integrity for the MOSI signal going to the thermocouple bus. This is the correct implementation for buffered MOSI distribution with proper signal conditioning.Output enable nOE2 tied to GND to permanently enable buffer 2 for MOSI distribution.
Pin 4 is the output enable for buffer 2 (2OE) which is active LOW according to the datasheet (page 3). It is connected to GND (LOW), permanently enabling buffer 2. This allows the MOSI signal to pass through to motor bus 1. Like buffer 1, this is correct since MOSI needs to be broadcast to all SPI devices simultaneously.Input A2 receives PA26_MOSI_D signal from microcontroller for distribution to motor bus 1.
Pin 5 is input A2 for buffer 2 according to the datasheet (page 3). It is connected to PA26_MOSI_D, the same signal as A1. This allows the same MOSI signal to be distributed to multiple buses simultaneously, which is the correct behavior for SPI MOSI distribution where all slave devices receive the same data.Output Y2 drives MOSI_M1BUS through series resistor R59 for motor bus 1.
Pin 6 is output Y2 for buffer 2 according to the datasheet (page 3). It connects to NetR59_2, which connects to R59 pin 2. R59 pin 1 connects to MOSI_M1BUS. R59 is a 47Ω series resistor providing signal integrity for the MOSI signal going to motor bus 1. This follows the same correct pattern as the thermocouple bus output.Ground pin correctly connected to system ground.
Pin 7 is the ground connection according to the datasheet (page 3). It is properly connected to the system ground rail (GND net). This provides the reference voltage and return path for the device. The connection is correct.Output Y3 drives MOSI_M2BUS through series resistor R89 for motor bus 2.
Pin 8 is output Y3 for buffer 3 according to the datasheet (page 3). It connects to NetR89_2, which connects to R89 pin 2. R89 pin 1 connects to MOSI_M2BUS. R89 is a 47Ω series resistor providing signal integrity for the MOSI signal going to motor bus 2. This continues the correct MOSI distribution pattern to the third SPI bus.Input A3 receives PA26_MOSI_D signal from microcontroller for distribution to motor bus 2.
Pin 9 is input A3 for buffer 3 according to the datasheet (page 3). It is connected to PA26_MOSI_D, the same signal as the other inputs. This ensures all SPI buses receive the same MOSI data simultaneously, which is the correct behavior for SPI MOSI distribution.Output enable nOE3 tied to GND to permanently enable buffer 3 for MOSI distribution.
Pin 10 is the output enable for buffer 3 (3OE) which is active LOW according to the datasheet (page 3). It is connected to GND (LOW), permanently enabling buffer 3. This allows the MOSI signal to pass through to motor bus 2, maintaining the correct broadcast behavior for MOSI distribution.Output Y4 provides buffered PA26_MOSI signal through series resistor R93 for external use.
Pin 11 is output Y4 for buffer 4 according to the datasheet (page 3). It connects to NetR93_2, which connects to R93 pin 2. R93 pin 1 connects to PA26_MOSI. This creates a buffered version of the MOSI signal that is separate from PA26_MOSI_D (the direct microcontroller output). PA26_MOSI connects to external connectors (J20 pin 3) and test points, providing a buffered MOSI signal for external use. This is not a feedback loop but rather a separate buffered output for external access.Input A4 receives PA26_MOSI_D signal from microcontroller for creating buffered external MOSI signal.
Pin 12 is input A4 for buffer 4 according to the datasheet (page 3). It is connected to PA26_MOSI_D, the same as the other buffer inputs. This input feeds buffer 4 which creates the buffered PA26_MOSI signal for external use through Y4. The connection is correct for providing a buffered copy of the MOSI signal.Output enable nOE4 tied to GND to permanently enable buffer 4 for external MOSI buffering.
Pin 13 is the output enable for buffer 4 (4OE) which is active LOW according to the datasheet (page 3). It is connected to GND (LOW), permanently enabling buffer 4. This allows the creation of the buffered PA26_MOSI signal for external use. The permanent enable is correct since this buffered signal should always be available for external connections.VCC supply pin correctly connected to 3.3VCC power rail.
Pin 14 is the VCC positive supply according to the datasheet (page 3). It is connected to 3.3VCC which provides 3.3V power. The datasheet specifies the device operates from 1.65V to 3.6V (page 1), so 3.3V is within the acceptable range. This connection provides proper power to the device.Thermal pad correctly connected to ground for heat dissipation.
Pin 15 is the PAD (thermal pad) connection. It is connected to GND, which is the standard practice for thermal pads to provide a heat dissipation path to the ground plane. The datasheet power supply recommendations (section 8.1.2) indicate proper grounding is important for device operation. Connecting the thermal pad to ground is correct for both thermal and electrical performance.No Connect pin correctly left unconnected.
Pin 23 is marked as NC (No Connect) in the schematic and has no electrical connection. This is correct as NC pins should not be connected to anything. The pin designation matches the component's intended usage.S1 - 1571610-2 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Switch contact connected to RESET net for reset functionality. Connection appears correct for reset switch operation.
Pin 1 (labeled 'P') is connected to the RESET net, which connects to the microcontroller reset pin (via J28 pin 6), a test point (TP56), and a 10nF filter capacitor (C40) to 3.3VIO. According to the datasheet (page1-2), this is a 'Single pole - single throw configuration' with 'Normally open (NO) operation'. When the switch is pressed, pin 1 connects to pin 2 (which is connected to GND), pulling the RESET line low to create a reset condition. The 10nF capacitor provides debouncing/filtering. This is a standard reset button configuration.Switch contact connected to GND for reset functionality. Connection is correct for reset switch operation.
Pin 2 (labeled 'S') is connected to GND. According to the datasheet (page1-2), this switch has 'Terminal 1' and 'Terminal 2' as 'Switch contact terminal'. When the switch is pressed, it connects pin 1 (RESET) to pin 2 (GND), creating the reset condition. This is the correct configuration for a reset switch.Additional pins connected to GND, likely for mechanical mounting and EMI shielding. Connection appears correct.
Pins 3 and 4 are both connected to GND. The datasheet (page1-2) describes this as having 'Terminal 1' and 'Terminal 2' as switch contacts, but the schematic shows 4 pins. This discrepancy is likely because the physical part has additional mechanical mounting pins or shield connections that are not the primary switch contacts. Connecting these to GND is appropriate for EMI shielding and mechanical stability. The datasheet mentions 'Through hole PCB mounting' with 'kinked legs for secure mounting', which supports the presence of additional mechanical pins.Additional pins connected to GND, likely for mechanical mounting and EMI shielding. Connection appears correct.
Pins 3 and 4 are both connected to GND. The datasheet (page1-2) describes this as having 'Terminal 1' and 'Terminal 2' as switch contacts, but the schematic shows 4 pins. This discrepancy is likely because the physical part has additional mechanical mounting pins or shield connections that are not the primary switch contacts. Connecting these to GND is appropriate for EMI shielding and mechanical stability. The datasheet mentions 'Through hole PCB mounting' with 'kinked legs for secure mounting', which supports the presence of additional mechanical pins.S2 - KMR741NG ULC LFS ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Switch contact connected to 3.3VCC for erase button functionality. Connection appears correct assuming proper switch pin pairing.
Pin 1 is connected to 3.3VCC. According to the datasheet (page1), this is a 'Momentary action SPST normally open contact' with 4 pins that are all 'Switch contact terminal'. For a 4-pin tactile switch, pins are typically arranged in pairs that connect when actuated. If pins 1&2 form one pair and pins 3&4 form another pair, then when pressed, pin 1 (3.3VCC) would connect through the switch mechanism to create the erase function. The connection to 3.3VCC is appropriate for providing the logic high signal needed for the erase function.Switch contact left unconnected. Connection is acceptable if switch has internal pin pairing with pin 1.
Pin 2 is unconnected (net 'unconnected-(NetS2_2)'). In a typical 4-pin tactile switch configuration, pins are internally paired. If pins 1&2 are internally connected, then leaving pin 2 unconnected is acceptable since pin 1 already provides the 3.3VCC connection. The datasheet (page1) shows all pins as 'Switch contact terminal' but doesn't specify the internal connection pattern. This configuration is common in tactile switch designs where redundant pins are left unconnected.Switch contact connected to ERASE net for microcontroller erase functionality. Connection appears correct.
Pin 3 is connected to the ERASE net, which connects to the microcontroller's PC0/ERASE pin (U11A pin 130), a test point (TP54), header connector (J28 pin 7), and ESD protection diode D1. When the switch is pressed, this pin should connect to pin 1 (3.3VCC) to assert the erase signal. The presence of ESD protection diode D1 (cathode on ERASE, anode to GND) indicates this is a functional erase button circuit. This connection is appropriate for the erase functionality.Switch contact left unconnected. Connection is acceptable if switch has internal pin pairing with pin 3.
Pin 4 is unconnected (net 'unconnected-(NetS2_4)'). Similar to pin 2, if the switch has internal pin pairing where pins 3&4 are connected together, then leaving pin 4 unconnected is acceptable since pin 3 already provides the ERASE connection. The datasheet (page1) indicates all pins are 'Switch contact terminal' but the specific internal connection pattern isn't detailed. This is a common practice in 4-pin tactile switch implementations.J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Pin 1 is connected to +5VCC power supply rail. This provides 5V power to external circuits connected to this header.
Pin 1 connects directly to the +5VCC net, which is the main 5V power supply rail in the system. According to the datasheet (page 1), this connector has a current rating of 3.0A AC/DC and voltage rating of 250V AC/DC, which is more than adequate for 5V power distribution. The connection is straightforward and appropriate for providing power to external expansion circuits.Pin 2 is connected to GND providing ground reference to external circuits. This is correctly paired with the power pin.
Pin 2 connects to the GND net, providing the ground reference for the power supplied on pin 1. This is a standard and correct arrangement for power distribution in expansion headers. The datasheet (page 1) confirms this pin can handle the required current levels.Pin 3 connects to PC2_PWML0 through a 100R series resistor R137. This provides a PWM output signal with current limiting protection.
Pin 3 connects to NetJ12_3, which goes to R137 pin 1. R137 pin 2 connects to PC2_PWML0, which is a PWM output from the microcontroller (U11A pin 59). The 100R series resistor (R137) provides current limiting and signal conditioning, which is good practice for protecting both the microcontroller and external circuits. This connection allows external circuits to access a PWM signal from the microcontroller.Pin 4 connects to PA1_CANRX0 through a 100R series resistor R136. This provides access to the CAN receive signal with protection.
Pin 4 connects to NetJ12_4, which goes to R136 pin 1. R136 pin 2 connects to PA1_CANRX0, which is the CAN receive signal from microcontroller pin 24. The 100R series resistor provides signal conditioning and protection. This allows external circuits to access the CAN bus receive functionality.Pin 5 connects to PA16 through a 100R series resistor R135. This provides access to a general purpose I/O pin with protection.
Pin 5 connects to NetJ12_5, which goes to R135 pin 1. R135 pin 2 connects to PA16, which is a general purpose I/O pin from microcontroller pin 78. The 100R series resistor provides the same protection as other signal pins. This gives external circuits access to a configurable GPIO pin.Pin 6 connects to PA0_CANTX0 through a 100R series resistor R134. This provides access to the CAN transmit signal with protection.
Pin 6 connects to NetJ12_6, which goes to R134 pin 1. R134 pin 2 connects to PA0_CANTX0, which is the CAN transmit signal from microcontroller pin 23. The 100R series resistor provides signal conditioning and protection. This complements pin 4 to provide complete CAN bus interface access to external circuits.Pin 7 connects to PA12_RXD1 through a 100R series resistor R133. This provides access to UART1 receive signal with protection.
Pin 7 connects to NetJ12_7, which goes to R133 pin 1. R133 pin 2 connects to PA12_RXD1, which is UART1 receive from microcontroller pin 5. The 100R series resistor provides signal conditioning and protection. This allows external circuits to interface with the secondary UART port.Pin 8 connects to PA15_CTS1 through a 100R series resistor R120. This provides access to UART1 clear-to-send signal with protection.
Pin 8 connects to NetJ12_8, which goes to R120 pin 1. R120 pin 2 connects to PA15_CTS1, which is the UART1 clear-to-send signal from microcontroller pin 8. The 100R series resistor provides signal conditioning and protection. This provides hardware flow control capability for the UART1 interface.Pin 9 connects to PA13_TXD1 through a 100R series resistor R114. This provides access to UART1 transmit signal with protection.
Pin 9 connects to NetJ12_9, which goes to R114 pin 1. R114 pin 2 connects to PA13_TXD1, which is UART1 transmit from microcontroller pin 6. The 100R series resistor provides signal conditioning and protection. This complements pin 7 to provide complete UART1 interface access to external circuits.Pin 10 connects to PA14_RTS1 through a 100R series resistor R109. This provides access to UART1 request-to-send signal with protection.
Pin 10 connects to NetJ12_10, which goes to R109 pin 1. R109 pin 2 connects to PA14_RTS1, which is the UART1 request-to-send signal from microcontroller pin 7. The 100R series resistor provides signal conditioning and protection. This complements pin 8 to provide complete hardware flow control for the UART1 interface.J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Pin 1 is connected to +5VCC power supply rail. This provides 5V power to external circuits connected to this header.
Pin 1 connects directly to the +5VCC net, which is the main 5V power supply rail in the system. According to the datasheet (page 1), this connector has a current rating of 3.0A AC/DC and voltage rating of 250V AC/DC, which is more than adequate for 5V power distribution. The connection is identical to J12 pin 1 and appropriate for providing power to external expansion circuits.Pin 2 is connected to GND providing ground reference to external circuits. This is correctly paired with the power pin.
Pin 2 connects to the GND net, providing the ground reference for the power supplied on pin 1. This is a standard and correct arrangement for power distribution in expansion headers. The datasheet (page 1) confirms this pin can handle the required current levels.Pin 3 connects to NRST through a 100R series resistor R145. This provides access to the system reset signal with protection.
Pin 3 connects to NetJ13_3, which goes to R145 pin 1. R145 pin 2 connects to NRST, which is the system reset signal. The 100R series resistor provides signal conditioning and protection. This allows external circuits to monitor or control the system reset functionality, which is useful for expansion boards that need reset coordination.Pin 4 connects to PB25_TIOA0 through a 100R series resistor R144. This provides access to timer/counter output signal with protection.
Pin 4 connects to NetJ13_4, which goes to R144 pin 1. R144 pin 2 connects to PB25_TIOA0, which is timer/counter channel 0 output A from microcontroller pin 144. The 100R series resistor provides signal conditioning and protection. This gives external circuits access to timer/counter functionality for timing or PWM applications.Pin 5 connects to PA26_MOSI through a 100R series resistor R143. This provides access to SPI master-out-slave-in signal with protection.
Pin 5 connects to NetJ13_5, which goes to R143 pin 1. R143 pin 2 connects to PA26_MOSI, which is the SPI MOSI signal from microcontroller pin 109. The 100R series resistor provides signal conditioning and protection. This allows external SPI slave devices to receive data from the microcontroller.Pin 6 connects to PA3_AD2 through a 100R series resistor R142. This provides access to analog input/GPIO signal with protection.
Pin 6 connects to NetJ13_6, which goes to R142 pin 1. R142 pin 2 connects to PA3_AD2, which is an analog input/GPIO from microcontroller pin 84. The 100R series resistor provides signal conditioning and protection. This gives external circuits access to analog measurement capability or additional GPIO functionality.Pin 7 connects to PA29_CS through a 100R series resistor R141. This provides access to SPI chip select signal with protection.
Pin 7 connects to NetJ13_7, which goes to R141 pin 1. R141 pin 2 connects to PA29_CS, which is a chip select signal from microcontroller pin 112. The 100R series resistor provides signal conditioning and protection. This allows external SPI devices to be controlled by the microcontroller's chip select functionality.Pin 8 connects to PB27_TIOB0 through a 100R series resistor R140. This provides access to timer/counter input signal with protection.
Pin 8 connects to NetJ13_8, which goes to R140 pin 1. R140 pin 2 connects to PB27_TIOB0, which is timer/counter channel 0 input/output B from microcontroller pin 68. The 100R series resistor provides signal conditioning and protection. This gives external circuits access to timer/counter functionality for input capture or output compare applications.Pin 9 connects to PA27_SCLK through a 100R series resistor R139. This provides access to SPI clock signal with protection.
Pin 9 connects to NetJ13_9, which goes to R139 pin 1. R139 pin 2 connects to PA27_SCLK, which is the SPI clock signal from microcontroller pin 110. The 100R series resistor provides signal conditioning and protection. This provides the clock signal needed for SPI communication with external devices.Pin 10 connects to PA25_MISO through a 100R series resistor R138. This provides access to SPI master-in-slave-out signal with protection.
Pin 10 connects to NetJ13_10, which goes to R138 pin 1. R138 pin 2 connects to PA25_MISO, which is the SPI MISO signal from microcontroller pin 108. The 100R series resistor provides signal conditioning and protection. This completes the SPI interface along with pins 5 and 9, allowing full SPI communication with external devices.J20 - Header 12X2 ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Pin 1 connects to PA28_CS0 providing SPI chip select functionality. This allows external SPI device selection.
Pin 1 connects directly to PA28_CS0, which is a chip select signal from microcontroller pin 111. This provides direct access to SPI chip select functionality for external devices. The connection is straightforward without series resistance, which is appropriate for chip select signals that typically don't require current limiting.Pin 2 connects to PA27_SCLK providing SPI clock signal. This provides the clock for SPI communication.
Pin 2 connects directly to PA27_SCLK, which is the SPI clock signal from microcontroller pin 110. This provides direct access to the SPI clock for external devices. The direct connection is appropriate as this signal is also buffered through other paths in the design when needed.Pin 3 connects to PA26_MOSI providing SPI master-out-slave-in signal. This allows data transmission to external SPI devices.
Pin 3 connects directly to PA26_MOSI, which is the SPI MOSI signal from microcontroller pin 109. This provides direct access for sending data to external SPI slave devices. The direct connection is consistent with the other SPI signals on this header.Pin 4 connects to PA25_MISO providing SPI master-in-slave-out signal. This allows data reception from external SPI devices.
Pin 4 connects directly to PA25_MISO, which is the SPI MISO signal from microcontroller pin 108. This provides direct access for receiving data from external SPI slave devices. The direct connection completes the SPI interface along with pins 1-3.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.These pins are unconnected and available for future expansion. They provide flexibility for additional signals if needed.
Pins 5, 6, 7, 9, 10, 11, 12, 13, 14, and 17 are all marked as unconnected with nets like 'unconnected-(NetJ20_5)'. This is a common design practice to provide spare pins in expansion headers for future functionality or customization. The unconnected status is intentional and correct for a flexible expansion interface.Pin 8 connects to PB12_AD8 providing analog input functionality. This allows external analog signal measurement.
Pin 8 connects directly to PB12_AD8, which is an analog input from microcontroller pin 86. This provides direct access to analog measurement capability for external circuits. The direct connection is appropriate for analog signals, though some designs might include filtering.Pin 15 connects to PB2_ETX0 through a 100R series resistor and has ESD protection. This provides Ethernet transmit functionality with protection.
Pin 15 connects to NetJ20_15, which connects to both RV3 pin 1 (6.8V varistor to GND for ESD protection) and R161 pin 1 (100R series resistor). R161 pin 2 connects to PB2_ETX0, which is Ethernet transmit data 0 from microcontroller pin 115. The combination of series resistance and ESD protection is excellent design practice for signals that may be exposed to external environments.Pin 16 connects to PB1_ETXEN through a 100R series resistor and has ESD protection. This provides Ethernet transmit enable functionality with protection.
Pin 16 connects to NetJ20_16, which connects to both RV4 pin 1 (6.8V varistor to GND for ESD protection) and R160 pin 1 (100R series resistor). R160 pin 2 connects to PB1_ETXEN, which is Ethernet transmit enable from microcontroller pin 114. The protection scheme matches pin 15 and is appropriate for Ethernet signals.Pin 18 connects to NRST providing system reset functionality. This allows external reset control or monitoring.
Pin 18 connects directly to NRST, which is the system reset signal. This provides external circuits with access to the system reset functionality, allowing them to either monitor reset status or initiate system resets. The direct connection is appropriate as reset signals typically have their own protection elsewhere in the circuit.Pin 19 connects to PB13_AD9 through a 100R series resistor and has ESD protection. This provides analog input functionality with protection.
Pin 19 connects to NetJ20_19, which connects to both RV2 pin 1 (6.8V varistor to GND for ESD protection) and R159 pin 1 (100R series resistor). R159 pin 2 connects to PB13_AD9, which is an analog input from microcontroller pin 87. The protection scheme is consistent with other protected signals and appropriate for analog inputs that may be exposed externally.Pin 20 connects to PB0_ETXCK through a 100R series resistor and has ESD protection. This provides Ethernet transmit clock functionality with protection.
Pin 20 connects to NetJ20_20, which connects to both RV1 pin 1 (6.8V varistor to GND for ESD protection) and R153 pin 1 (100R series resistor). R153 pin 2 connects to PB0_ETXCK, which is Ethernet transmit clock from microcontroller pin 113. The protection scheme matches the other Ethernet signals and is appropriate for clock signals that may be exposed externally.Pin 21 connects to PA18_SCL providing I2C clock functionality. This allows I2C communication with external devices.
Pin 21 connects directly to PA18_SCL, which is the I2C clock signal from microcontroller pin 70. This provides direct access to I2C clock functionality for external devices. The direct connection is typical for I2C signals, which usually have pull-up resistors elsewhere in the circuit (R71 provides pull-up to 3.3VIO).Pin 22 connects to PA17_SDA providing I2C data functionality. This allows I2C communication with external devices.
Pin 22 connects directly to PA17_SDA, which is the I2C data signal from microcontroller pin 9. This provides direct access to I2C data functionality for external devices. The direct connection complements pin 21 to provide complete I2C interface access. Like the clock signal, this has pull-up resistor R40 to 3.3VIO elsewhere in the circuit.Pin 23 is connected to GND providing ground reference. This is essential for proper signal referencing.
Pin 23 connects to the GND net, providing ground reference for the signals on this header. This is essential for proper operation of the interface signals and is correctly placed to provide a good ground reference for external circuits.Pin 24 is connected to 3.3VCC providing 3.3V power. This supplies power for 3.3V logic external circuits.
Pin 24 connects to the 3.3VCC net, which is the main 3.3V power supply rail. This provides power for external 3.3V logic circuits that interface with the signals on this header. The placement at the end of the header along with ground on pin 23 is a good design practice for power distribution.J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Pin 1 is connected to GND providing ground reference. This provides ground for the programming/debug interface.
Pin 1 connects to the GND net, providing ground reference for this programming/debug header. According to the datasheet (page 1), this connector can handle the required current levels. The ground placement at pin 1 is appropriate for a debug interface.Pin 2 connects to PA9_UTXD providing UART transmit functionality. This allows serial communication for debugging or programming.
Pin 2 connects directly to PA9_UTXD, which is the UART transmit signal from microcontroller pin 2. This provides serial transmit capability for debugging, programming, or communication with external tools. The direct connection is appropriate for a dedicated debug/programming interface.Pin 3 is connected to +5VCC providing 5V power. This supplies power for external programming/debug tools.
Pin 3 connects to the +5VCC net, providing 5V power for external programming or debug tools that may require 5V operation. The datasheet (page 1) confirms this connector can handle the required current and voltage levels. This is appropriate for powering external debug hardware.Pin 4 connects to PA8_URXD providing UART receive functionality. This allows serial communication for debugging or programming.
Pin 4 connects directly to PA8_URXD, which is the UART receive signal from microcontroller pin 27. This complements pin 2 to provide complete UART communication capability for debugging, programming, or communication with external tools. The direct connection is appropriate for a dedicated debug interface.Pin 5 is connected to 3.3VCC providing 3.3V power. This supplies power for 3.3V logic external circuits.
Pin 5 connects to the 3.3VCC net, providing 3.3V power for external circuits that operate at 3.3V logic levels. This is useful for debug tools or programming adapters that need to match the microcontroller's logic levels.Pin 6 connects to NRST providing system reset functionality. This allows external reset control for programming or debugging.
Pin 6 connects directly to NRST, which is the system reset signal. This allows external programming or debug tools to control the system reset, which is essential for programming operations and debug control. The direct connection is appropriate for debug interfaces.Pin 7 connects to ERASE providing erase functionality. This allows external tools to trigger chip erase operations.
Pin 7 connects directly to ERASE, which is connected to microcontroller pin 130 (PC0/ERASE). This provides external tools with the ability to trigger erase operations, which is important for programming and recovery operations. The direct connection is appropriate for this control signal.Pin 8 is connected to +5VCC providing additional 5V power. This provides extra power capacity for external tools.
Pin 8 connects to the +5VCC net, providing additional 5V power capacity. Having multiple power pins is good practice for headers that may need to supply significant current to external tools or when redundant power connections are desired for reliability.Pin 9 connects to PC8_PWML3 providing PWM functionality. This allows access to PWM signals for testing or control.
Pin 9 connects directly to PC8_PWML3, which is a PWM output from microcontroller pin 66. This provides access to PWM functionality, which could be useful for testing, control applications, or providing timing signals to external debug equipment. The direct connection is appropriate for this application.Pin 10 is connected to GND providing additional ground reference. This provides good grounding for the interface.
Pin 10 connects to the GND net, providing additional ground reference for the debug interface. Having ground connections at both ends of the header (pins 1 and 10) is good practice for maintaining signal integrity and providing stable ground reference for all the interface signals.Q12A - NCV8402AD ✅
DRCY found no issues in this component 🎉
ℹ️ DRCY didn't use a Datasheet for this component.
Source pin correctly connected to ground for low-side switching operation.
Pin 1 (S) is connected to GND net. For a low-side MOSFET driver like the NCV8402AD, the source should be connected to ground to provide the return path for current when the MOSFET is conducting. This connection is correct for low-side switching applications where the load is connected between the positive supply and the MOSFET drain.Gate pin correctly connected to buffer output through current limiting resistor.
Pin 2 (G) is connected to NetQ12_2, which connects to R98 pin 2. R98 is a 100 ohm resistor with its other end (pin 1) connected to NetR98_1, which connects to U2D pin 11 (4Y output). This forms a proper gate drive circuit where the buffer output drives the MOSFET gate through a 100 ohm current limiting resistor. The 100 ohm value is appropriate for limiting gate current and reducing switching noise/ringing.Drain pin correctly connected to LED cathode and fan connector for load switching.
Pin 7 (D) is connected to NetC154_2, which connects to LED1 cathode (C), test point TP8, connector J29 pin 1, and capacitor C154 pin 2. This is the correct configuration for a low-side switch where the drain connects to the cathode of the LED load. The LED anode connects through current limiting resistor R96 to VFAN supply. When the MOSFET turns on, it provides a path to ground for the LED current.Q12B - NCV8402AD ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Source pin correctly connected to ground for low-side switching operation.
Pin 3 (S) is connected to GND net. This is the correct connection for the source of the second channel in the dual NCV8402AD low-side driver. The source provides the return path to ground when the MOSFET conducts.Gate pin correctly connected to buffer output through current limiting resistor.
Pin 4 (G) is connected to NetQ12_4, which connects to R99 pin 2. R99 is a 100 ohm resistor with its other end connected to U2C pin 8 (3Y output). This provides proper gate drive from the buffer through an appropriate current limiting resistor.Drain pin correctly connected to LED cathode and fan connector for load switching.
Pin 5 (D) is connected to NetC153_2, which connects to LED2 cathode (C), test point TP2, connector J22 pin 1, and capacitor C153 pin 2. This follows the same correct low-side switching pattern as Q12A, where the drain switches the LED load to ground.Q13A - NCV8402AD ✅
DRCY found no issues in this component 🎉
ℹ️ DRCY didn't use a Datasheet for this component.
Source pin correctly connected to ground for low-side switching operation.
Pin 1 (S) is connected to GND net. This is the correct connection for the source of the first channel in the second dual NCV8402AD package, providing the ground return path.Gate pin correctly connected to buffer output through current limiting resistor.
Pin 2 (G) is connected to NetQ13_2, which connects to R180 pin 2. R180 is a 100 ohm resistor connected to U2B pin 6 (2Y output). This provides proper gate drive with appropriate current limiting.Drain pin correctly connected to LED cathode and fan connector for load switching.
Pin 7 (D) is connected to NetC211_2, which connects to LED3 cathode (C), test point TP18, connector J31 pin 1, and capacitor C211 pin 2. This maintains the correct low-side switching configuration for LED3.Q13B - NCV8402AD ❌
DRCY flagged 1 potential issues in this component.
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Drain pin incorrectly connected directly to positive supply rail instead of load. This creates a short circuit when MOSFET turns on.
Source pin correctly connected to ground for low-side switching operation.
Pin 3 (S) is connected to GND net. This is the correct source connection for the second channel of the Q13 NCV8402AD package.Gate pin correctly connected to buffer output through current limiting resistor.
Pin 4 (G) is connected to NetQ13_4, which connects to R181 pin 2. R181 is a 100 ohm resistor connected to U2A pin 3 (1Y output). This provides proper gate drive with current limiting.D50 - BAT54WX ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode connected to NetD50_A for positive voltage clamping of TACH_1 signal conditioning circuit.
The anode connects to NetD50_A, which is part of the TACH_1 signal conditioning network. NetD50_A connects to R174 (from TACH_1), R175 (to NetJ29_3), and D52 cathode. This forms a voltage divider with clamping protection. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. When NetD50_A voltage exceeds 3.3V + Vf, this diode will conduct and clamp the voltage. With maximum forward voltage of 0.80V at 100mA per datasheet (page 1), the clamp level will be approximately 4.1V maximum. This is correct for protecting downstream circuitry from overvoltage on the tachometer input.Cathode correctly connected to 3.3VCC to establish positive clamp reference level.
The cathode connects to 3.3VCC rail. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode, marked with cathode mark on package'. This connection establishes the positive clamp reference level at 3.3V + Vf. The diode will conduct when NetD50_A exceeds this level, providing overvoltage protection. The 30V maximum recurrent peak reverse voltage rating from datasheet (page 1) is more than adequate for this 3.3V application. This connection is correct for the intended clamping function.D51 - BAT54WX ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode connected to NetD51_A for positive voltage clamping of TACH_2 signal conditioning circuit.
The anode connects to NetD51_A, which is part of the TACH_2 signal conditioning network. NetD51_A connects to R176 (from TACH_2), R177 (to NetJ22_3), and D53 cathode. This forms a voltage divider with clamping protection similar to the TACH_1 circuit. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. When NetD51_A voltage exceeds 3.3V + Vf, this diode will conduct and clamp the voltage. This provides the same overvoltage protection as D50 for the TACH_2 input signal conditioning.Cathode correctly connected to 3.3VCC to establish positive clamp reference level.
The cathode connects to 3.3VCC rail, establishing the positive clamp reference level at 3.3V + Vf for the TACH_2 signal conditioning circuit. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode'. This connection is identical to D50 and provides the same overvoltage protection function. The connection is correct for the intended positive clamping application.D52 - BAT54WX ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode correctly connected to GND for negative voltage clamping of TACH_1 signal.
The anode connects to GND. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. This connection allows D52 to function as a negative clamp for NetD50_A. When NetD50_A tries to go below GND - Vf, the diode will conduct and clamp the voltage. With maximum forward voltage of 0.80V at 100mA per datasheet (page 1), this provides protection against negative voltage excursions down to approximately -0.8V. This is correct for protecting downstream circuitry from undervoltage conditions on the TACH_1 input.Cathode correctly connected to NetD50_A to complete negative clamp function.
The cathode connects to NetD50_A, completing the negative clamp circuit for the TACH_1 signal conditioning network. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode'. This connection works with the anode-to-GND connection to prevent NetD50_A from going significantly below ground potential. The diode will conduct when NetD50_A drops below GND - Vf, providing undervoltage protection. This connection is correct and complements the positive clamp provided by D50.D53 - BAT54WX ❌
DRCY flagged 2 potential issues in this component.
📄 DRCY referred to this Datasheet for this component.
Anode is unconnected, preventing this diode from functioning as intended negative clamp. Should be connected to GND.
Cathode correctly connected to NetD51_A but diode is non-functional due to unconnected anode.
D54 - BAT54WX ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode connected to NetD54_A for positive voltage clamping of TACH_3 signal conditioning circuit.
The anode connects to NetD54_A, which is part of the TACH_3 signal conditioning network. NetD54_A connects to R186 (from TACH_3), R187 (to NetJ31_3), and D56 cathode. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. This configuration matches the other positive clamp diodes (D50, D51, D55) and will clamp NetD54_A when it exceeds 3.3V + Vf. The connection is correct for providing overvoltage protection to the TACH_3 signal conditioning circuit.Cathode correctly connected to 3.3VCC to establish positive clamp reference level.
The cathode connects to 3.3VCC rail, establishing the positive clamp reference level for the TACH_3 signal conditioning circuit. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode'. This connection is identical to the other positive clamp diodes and provides the same overvoltage protection function. The connection is correct for the intended positive clamping application.D55 - BAT54WX ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode connected to NetD55_A for positive voltage clamping of TACH_4 signal conditioning circuit.
The anode connects to NetD55_A, which is part of the TACH_4 signal conditioning network. NetD55_A connects to R188 (from TACH_4), R189 (to NetJ30_3), and D57 cathode. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. This configuration matches the other positive clamp diodes and will clamp NetD55_A when it exceeds 3.3V + Vf. The connection is correct for providing overvoltage protection to the TACH_4 signal conditioning circuit.Cathode correctly connected to 3.3VCC to establish positive clamp reference level.
The cathode connects to 3.3VCC rail, establishing the positive clamp reference level for the TACH_4 signal conditioning circuit. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode'. This connection is identical to the other positive clamp diodes and provides the same overvoltage protection function. The connection is correct for the intended positive clamping application.D56 - BAT54WX ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode correctly connected to GND for negative voltage clamping of TACH_3 signal.
The anode connects to GND. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. This connection allows D56 to function as a negative clamp for NetD54_A, identical to D52 and D57. When NetD54_A tries to go below GND - Vf, the diode will conduct and clamp the voltage. This provides protection against negative voltage excursions on the TACH_3 input. The connection is correct for the intended negative clamping function.Cathode correctly connected to NetD54_A to complete negative clamp function.
The cathode connects to NetD54_A, completing the negative clamp circuit for the TACH_3 signal conditioning network. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode'. This connection works with the anode-to-GND connection to prevent NetD54_A from going significantly below ground potential. The connection is correct and complements the positive clamp provided by D54.D57 - BAT54WX ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode correctly connected to GND for negative voltage clamping of TACH_4 signal.
The anode connects to GND. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. This connection allows D57 to function as a negative clamp for NetD55_A, identical to D52 and D56. When NetD55_A tries to go below GND - Vf, the diode will conduct and clamp the voltage. This provides protection against negative voltage excursions on the TACH_4 input. The connection is correct for the intended negative clamping function.Cathode correctly connected to NetD55_A to complete negative clamp function.
The cathode connects to NetD55_A, completing the negative clamp circuit for the TACH_4 signal conditioning network. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode'. This connection works with the anode-to-GND connection to prevent NetD55_A from going significantly below ground potential. The connection is correct and complements the positive clamp provided by D55.J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Pin 1 connects to NetC153_2, providing a switched ground path through Q12B MOSFET for fan control.
Pin 1 connects to NetC153_2, which is connected to Q12B drain (pin 5). Q12B is part of the NCV8402AD low-side driver with its source connected to GND and gate controlled by NetQ12_4 through R99. When Q12B turns on, pin 1 is pulled to ground, completing the circuit for the fan connected between pins 1 and 2. This is a standard low-side switching configuration for fan control. The connection also drives LED2 cathode, providing visual indication of fan operation.Pin 2 connects to VFAN, providing the positive supply voltage for the fan.
Pin 2 connects to VFAN, which serves as the positive supply voltage for the fan. This is the standard configuration for the positive terminal of a fan connector in a low-side switching arrangement. The fan operates when current flows from VFAN (pin 2) through the fan to the switched ground (pin 1).Pin 3 connects to NetJ22_3, providing the tachometer signal input with proper pull-up and protection circuitry.
Pin 3 connects to NetJ22_3, which has a 1.8K pull-up resistor (R173) to 3.3VCC and connects through a 1K resistor (R175) to NetD50_A. The signal path includes Schottky diode protection (D50, D52) and eventually connects to TACH_1 through R174. The tachometer signal is filtered by C155 (100nF to GND). This provides proper signal conditioning for the fan tachometer output with pull-up, protection, and filtering.J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Pin 1 connects to NetC154_2, providing a switched ground path through Q12A MOSFET for fan control.
Pin 1 connects to NetC154_2, which is connected to Q12A drain (pin 7). Q12A is part of the NCV8402AD low-side driver with its source connected to GND and gate controlled by NetQ12_2 through R98. When Q12A turns on, pin 1 is pulled to ground, completing the circuit for the fan connected between pins 1 and 2. This matches the same low-side switching configuration as J22. The connection also drives LED1 cathode, providing visual indication of fan operation.Pin 2 connects to VFAN, providing the positive supply voltage for the fan.
Pin 2 connects to VFAN, which serves as the positive supply voltage for the fan. This is consistent with the other fan connectors and provides the standard positive terminal connection for a fan in a low-side switching arrangement.Pin 3 connects to NetJ29_3, providing the tachometer signal input with proper pull-up and protection circuitry.
Pin 3 connects to NetJ29_3, which has a 1.8K pull-up resistor (R172) to 3.3VCC and connects through a 1K resistor (R175) to NetD50_A. This shares the same protection and signal conditioning path as J22 pin 3, eventually connecting to TACH_1 through the same diode network and filtering. The circuit provides proper tachometer signal conditioning.J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ❌
DRCY flagged 1 potential issues in this component.
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Both pins 1 and 2 connect to VFAN, which is incorrect as pin 1 should provide switched ground for fan control. This breaks the switching functionality for this fan connector.
Both pins 1 and 2 connect to VFAN, which is incorrect as pin 1 should provide switched ground for fan control. This breaks the switching functionality for this fan connector.
Pin 3 connects to NetJ30_3, providing the tachometer signal input with proper pull-up and protection circuitry.
Pin 3 connects to NetJ30_3, which has a 1.8K pull-up resistor (R185) to 3.3VCC and connects through a 1K resistor (R189) to NetD55_A. The signal path includes Schottky diode protection (D55, D57) and eventually connects to TACH_4 through R188. The tachometer signal is filtered by C213 (100nF to GND). This provides the same proper signal conditioning as the other fan connectors.J31 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅
DRCY found no issues in this component 🎉
⚠️ DRCY couldn't retrieve a Datasheet for this component.
Pin 1 connects to NetC211_2, providing a switched ground path through Q13A MOSFET for fan control.
Pin 1 connects to NetC211_2, which is connected to Q13A drain (pin 7). Q13A is part of the NCV8402AD low-side driver with its source connected to GND and gate controlled by NetQ13_2 through R180. When Q13A turns on, pin 1 is pulled to ground, completing the circuit for the fan connected between pins 1 and 2. This follows the same low-side switching configuration as J22 and J29. The connection also drives LED3 cathode, providing visual indication of fan operation.Pin 2 connects to VFAN, providing the positive supply voltage for the fan.
Pin 2 connects to VFAN, which serves as the positive supply voltage for the fan. This is consistent with the other fan connectors and provides the standard positive terminal connection for a fan in a low-side switching arrangement.Pin 3 connects to NetJ31_3, providing the tachometer signal input with proper pull-up and protection circuitry.
Pin 3 connects to NetJ31_3, which has a 1.8K pull-up resistor (R184) to 3.3VCC and connects through a 1K resistor (R187) to NetD54_A. The signal path includes Schottky diode protection (D54, D56) and eventually connects to TACH_3 through R186. The tachometer signal is filtered by C212 (100nF to GND). This provides proper signal conditioning for the fan tachometer output with pull-up, protection, and filtering.LED1 - 5988110107F ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode connected through current limiting resistor R96 (4.7K) to VFAN power supply. This provides the high-side connection for the LED.
The anode pin A is connected to net NetLED1_A, which connects to R96 pin 1. R96 pin 2 connects to VFAN. This creates a current limiting path from the VFAN power supply through the 4.7K resistor to the LED anode. According to the datasheet (page 4-27), pin 2 is the anode connection for the 0805 package. The schematic uses descriptive pin names (A for anode) which correctly corresponds to the datasheet specification. The 4.7K resistor provides appropriate current limiting for the LED's 20mA specification.Cathode connected to MOSFET drain Q12A pin 7, allowing the LED to be switched on/off by the MOSFET. This is a standard LED driver configuration.
The cathode pin C is connected to net NetC154_2, which connects to Q12A pin 7 (drain), C154 pin 2, J29 pin 1, and TP8. When MOSFET Q12A turns on, it provides a low-resistance path from the LED cathode to ground through the MOSFET's source pin (Q12A pin 1 connects to GND). This allows current to flow from VFAN through R96, through the LED from anode to cathode, and to ground via the MOSFET. According to the datasheet (page 4-27), pin 1 is the cathode connection for the 0805 package. The schematic pin name C correctly corresponds to cathode in the datasheet.LED2 - 5988110107F ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode connected through current limiting resistor R12 (4.7K) to VFAN power supply. This provides the high-side connection for the LED.
The anode pin A is connected to net NetLED2_A, which connects to R12 pin 1. R12 pin 2 connects to VFAN. This creates a current limiting path from the VFAN power supply through the 4.7K resistor to the LED anode. According to the datasheet (page 4-27), pin 2 is the anode connection for the 0805 package. The schematic uses descriptive pin names (A for anode) which correctly corresponds to the datasheet specification. The 4.7K resistor provides appropriate current limiting for the LED's 20mA specification.Cathode connected to MOSFET drain Q12B pin 5, allowing the LED to be switched on/off by the MOSFET. This is a standard LED driver configuration.
The cathode pin C is connected to net NetC153_2, which connects to Q12B pin 5 (drain), C153 pin 2, J22 pin 1, and TP2. When MOSFET Q12B turns on, it provides a low-resistance path from the LED cathode to ground through the MOSFET's source pin (Q12B pin 3 connects to GND). This allows current to flow from VFAN through R12, through the LED from anode to cathode, and to ground via the MOSFET. According to the datasheet (page 4-27), pin 1 is the cathode connection for the 0805 package. The schematic pin name C correctly corresponds to cathode in the datasheet.LED3 - 5988110107F ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Anode connected through current limiting resistor R15 (4.7K) to VFAN power supply. This provides the high-side connection for the LED.
The anode pin A is connected to net NetLED3_A, which connects to R15 pin 1. R15 pin 2 connects to VFAN. This creates a current limiting path from the VFAN power supply through the 4.7K resistor to the LED anode. According to the datasheet (page 4-27), pin 2 is the anode connection for the 0805 package. The schematic uses descriptive pin names (A for anode) which correctly corresponds to the datasheet specification. The 4.7K resistor provides appropriate current limiting for the LED's 20mA specification.Cathode connected to MOSFET drain Q13A pin 7, allowing the LED to be switched on/off by the MOSFET. This is a standard LED driver configuration.
The cathode pin C is connected to net NetC211_2, which connects to Q13A pin 7 (drain), C211 pin 2, J31 pin 1, and TP18. When MOSFET Q13A turns on, it provides a low-resistance path from the LED cathode to ground through the MOSFET's source pin (Q13A pin 1 connects to GND). This allows current to flow from VFAN through R15, through the LED from anode to cathode, and to ground via the MOSFET. According to the datasheet (page 4-27), pin 1 is the cathode connection for the 0805 package. The schematic pin name C correctly corresponds to cathode in the datasheet.LED4 - 5988110107F ❌
DRCY flagged 1 potential issues in this component.
📄 DRCY referred to this Datasheet for this component.
Both anode and cathode are effectively connected to the same potential (VFAN), preventing current flow through the LED. The LED will not illuminate.
Both anode and cathode are effectively connected to the same potential (VFAN), preventing current flow through the LED. The LED will not illuminate.
U2A - SN74AHCT125 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Output enable pin for gate 1 is correctly tied to GND to permanently enable the buffer.
Pin 1 (1OE) is the output enable for gate 1. According to the datasheet (page 4), 'Each output is disabled when the associated output-enable (OE) input is high' and 'When OE is low, the respective gate passes the data from the A input to its Y output'. This pin is connected to GND, which keeps the output permanently enabled (active low). This is the correct configuration for a buffer application where the gate should always be enabled.Gate 1 input correctly receives Fan4 control signal from system controller.
Pin 2 (1A) is gate 1 input according to the datasheet (page 4). It is connected to the Fan4 net, which appears to be a control signal from the system controller. This is the correct connection for receiving the input signal that needs to be buffered and conditioned before driving the MOSFET gate driver.Gate 1 output correctly drives MOSFET gate driver through current limiting resistor.
Pin 3 (1Y) is gate 1 output according to the datasheet (page 4). It is connected to NetR181_1, which connects through R181 (100R resistor) to NetQ13_4, ultimately driving the gate of Q13B (NCV8402AD MOSFET driver). The 100R resistor provides appropriate current limiting for the gate drive signal. This is a proper buffer output configuration for driving MOSFET gate drivers.U2B - SN74AHCT125 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Output enable pin for gate 2 is correctly tied to GND to permanently enable the buffer.
Pin 4 (2OE) is the output enable for gate 2. According to the datasheet (page 4), this pin controls whether the output is enabled or disabled. Connected to GND, it keeps gate 2 permanently enabled (active low), which is the correct configuration for this buffer application.Gate 2 input correctly receives Fan3 control signal from system controller.
Pin 5 (2A) is gate 2 input according to the datasheet (page 4). It is connected to the Fan3 net, which is a control signal from the system controller. This is the proper connection for the input signal that will be buffered and sent to the MOSFET gate driver.Gate 2 output correctly drives MOSFET gate driver through current limiting resistor.
Pin 6 (2Y) is gate 2 output according to the datasheet (page 4). It connects to NetR180_1, which goes through R180 (100R resistor) to NetQ13_2, driving the gate of Q13A (NCV8402AD MOSFET driver). The 100R resistor provides proper current limiting for the gate drive signal. This is a correct buffer output configuration.U2C - SN74AHCT125 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Gate 3 output correctly drives MOSFET gate driver through current limiting resistor.
Pin 8 (3Y) is gate 3 output according to the datasheet (page 4). It connects to NetR99_1, which goes through R99 (100R resistor) to NetQ12_4, driving the gate of Q12B (NCV8402AD MOSFET driver). The 100R current limiting resistor is appropriate for gate drive applications. This is a proper buffer output configuration.Gate 3 input correctly receives FAN2 control signal from system controller.
Pin 9 (3A) is gate 3 input according to the datasheet (page 4). It is connected to the FAN2 net, which is a control signal from the system controller. This is the correct connection for receiving the input signal that needs to be buffered before driving the MOSFET gate driver.Output enable pin for gate 3 is correctly tied to GND to permanently enable the buffer.
Pin 10 (3OE) is the output enable for gate 3. According to the datasheet (page 4), this pin controls the output state. Connected to GND, it keeps gate 3 permanently enabled (active low), which is the correct configuration for this buffer application where the gate should always be active.U2D - SN74AHCT125 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Gate 4 output correctly drives MOSFET gate driver through current limiting resistor.
Pin 11 (4Y) is gate 4 output according to the datasheet (page 4). It connects to NetR98_1, which goes through R98 (100R resistor) to NetQ12_2, driving the gate of Q12A (NCV8402AD MOSFET driver). The 100R resistor provides appropriate current limiting for the gate drive signal. This is a correct buffer output configuration.Gate 4 input correctly receives FAN1 control signal from system controller.
Pin 12 (4A) is gate 4 input according to the datasheet (page 4). It is connected to the FAN1 net, which is a control signal from the system controller. This is the proper connection for the input signal that will be buffered and conditioned before driving the MOSFET gate driver.Output enable pin for gate 4 is correctly tied to GND to permanently enable the buffer.
Pin 13 (4OE) is the output enable for gate 4. According to the datasheet (page 4), this pin controls whether the output is enabled or disabled. Connected to GND, it keeps gate 4 permanently enabled (active low), which is the correct configuration for this buffer application.U2E - SN74AHCT125 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Ground pin is correctly connected to system ground.
Pin 7 (GND) is the ground pin according to the datasheet (page 4). It is properly connected to the GND net, providing the necessary ground reference for the IC. This is the correct power connection.Power pin is correctly connected to +5VCC supply.
Pin 14 (VCC) is the power pin according to the datasheet (page 4). It is connected to +5VCC, which is within the operating voltage range for the SN74AHCT125. The datasheet (section 8) recommends proper bypass capacitoring, and C92 (100nF) is present on the +5VCC rail for this purpose. This is the correct power supply connection.Thermal pad is connected to test point for thermal management.
Pin 15 (PAD) is the thermal pad for the VQFN package. It is connected to SNTP1, which appears to be a test point. This connection provides thermal management and electrical connection to the die paddle, which is appropriate for proper thermal performance of the IC in the VQFN package.📤 Upload Missing Datasheets
DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews.
Note: DRCY uses AI. Please verify the outputs.
Component
Q13B, pin5: Drain pin incorrectly connected directly to positive supply rail instead of load. This creates a short circuit when MOSFET turns on.Pin 5 (D) is connected to VFAN, which is the positive supply rail that feeds LED anodes and connector positive terminals. This is incorrect for a low-side MOSFET driver. When the MOSFET turns on, this would create a direct short from VFAN to ground through the MOSFET. The drain should connect to a load (like LED4 cathode) instead. Looking at the pattern, LED4 cathode is connected to VFAN, which is also incorrect - it should connect to this MOSFET drain. The correct connection would be Q13B pin 5 to LED4 cathode, and LED4 cathode should not connect to VFAN.
Component
D53, pinA: Anode is unconnected, preventing this diode from functioning as intended negative clamp. Should be connected to GND.The anode shows 'unconnected-(NetD53_A)' indicating it is not connected to any net. According to the datasheet (page 1), the anode is the 'Positive terminal of the Schottky diode'. For D53 to function as a negative clamp like D52, D56, and D57, the anode should be connected to GND. The circuit topology shows D53 is intended to provide negative clamping for NetD51_A (TACH_2 signal), but with an unconnected anode, this diode cannot conduct and provides no protection. This appears to be a connection error. The anode should be connected to GND to match the other negative clamp diodes in the circuit.
Component
D53, pinK: Cathode correctly connected to NetD51_A but diode is non-functional due to unconnected anode.The cathode connects to NetD51_A as intended for negative clamping of the TACH_2 signal conditioning circuit. According to the datasheet (page 1), the cathode is the 'Negative terminal of the Schottky diode'. However, since the anode is unconnected, this diode cannot conduct and provides no clamping function. The connection to NetD51_A is correct in principle, but the diode is rendered non-functional by the missing anode connection. This leaves the TACH_2 circuit without negative voltage protection, unlike the other three tachometer circuits which have proper negative clamps.
Component
J30, pins1, 2: Both pins 1 and 2 connect to VFAN, which is incorrect as pin 1 should provide switched ground for fan control. This breaks the switching functionality for this fan connector.Pins 1 and 2 both connect to VFAN, which is inconsistent with the other fan connectors (J22, J29, J31) where pin 1 provides switched ground through MOSFET control and pin 2 provides positive supply. In a proper low-side switching fan control circuit, pin 1 should connect to a switched ground output from a MOSFET drain. Looking at the pattern: J22 pin 1 connects to Q12B drain (NetC153_2), J29 pin 1 connects to Q12A drain (NetC154_2), and J31 pin 1 connects to Q13A drain (NetC211_2). J30 pin 1 should connect to Q13B drain, but Q13B drain (pin 5) incorrectly connects directly to VFAN instead of providing a switched output. This means J30 cannot be controlled - the fan would either be always on (if connected) or the circuit would not function properly. Pin 1 should be connected to a switched ground output, likely requiring a correction to the Q13B drain connection or addition of another switching MOSFET.
Component
LED4, pinsA, C: Both anode and cathode are effectively connected to the same potential (VFAN), preventing current flow through the LED. The LED will not illuminate.The anode pin A connects to net NetLED4_A, which connects to R14 pin 1. R14 pin 2 connects to VFAN. The cathode pin C connects directly to net VFAN. This means both terminals of the LED are at the same potential (VFAN) with only the 4.7K resistor R14 in between. Since there is no voltage difference across the LED, no current will flow and the LED will not illuminate. According to the datasheet (page 4-27), pin 2 is the anode and pin 1 is the cathode for the 0805 package. For proper operation, the LED needs a voltage difference between anode and cathode, with the anode at higher potential. The cathode should be connected to a switching element (like a MOSFET drain) that can provide a path to ground, similar to LED1, LED2, and LED3. To fix this, the cathode should be connected to a MOSFET drain instead of directly to VFAN.
Component
U11A, pins29, 30: JTAG TDI and TDO signals are swapped between pins 29 and 30.Pin 29 (PB29/TDI) is connected to TDO/SWO net, and Pin 30 (PB30/TDO/TRACESWO) is connected to TDI net. According to the datasheet (page 4-7), PB29 has TDI function (JTAG test data input) and should connect to TDI, while PB30 has TDO function (JTAG test data output) and should connect to TDO/SWO. These connections are swapped and will prevent proper JTAG debugging functionality. The connections should be: Pin 29 → TDI and Pin 30 → TDO/SWO.
Component
J18, pins7, 8: DAT1 and DAT0 data lines are swapped - DAT1 connects to MCDA0 and DAT0 connects to MCDA1, which is incorrect.Pin 7 (DAT1) connects to net MCDA0 and pin 8 (DAT0) connects to net MCDA1. However, according to SD card protocol standards, DAT0 should connect to MCDA0 and DAT1 should connect to MCDA1. The current connections are: MCDA0 -> Pin 7 (DAT1) and MCDA1 -> Pin 8 (DAT0). This is a pin swap error. The correct connections should be: MCDA0 -> Pin 8 (DAT0) and MCDA1 -> Pin 7 (DAT1). Both pins have proper pullup resistors (R70 and R69) and ESD protection (D65 and D64), but the fundamental pin assignments are incorrect. This will prevent proper SD card communication as the data lines will be misaligned.
📄 DRCY referred to this Datasheet for this component.
Component
J4, pins6, 8: TDO/SWO and TDI signals are swapped between JTAG connector and microcontroller pins.Pin 6 (TDO/SWO) connects to net 'TDO/SWO' which goes to microcontroller pin 29 (PB29/TDI), while pin 8 (TDI) connects to net 'TDI' which goes to microcontroller pin 30 (PB30/TDO/TRACESWO). According to standard ARM JTAG pinout, pin 6 should be TDO/SWO and pin 8 should be TDI. However, the signals are swapped: TDO/SWO is connected to the microcontroller's TDI pin, and TDI is connected to the microcontroller's TDO pin. The correct connections should be: JTAG pin 6 (TDO/SWO) to microcontroller pin 30 (PB30/TDO/TRACESWO), and JTAG pin 8 (TDI) to microcontroller pin 29 (PB29/TDI). This swap will prevent proper JTAG debugging functionality.
📄 DRCY referred to this Datasheet for this component.
Component
D21, pinsA, K: TVS diode is connected with incorrect polarity - anode to VMOTE and cathode to GND will create a short circuit.The anode is connected to VMOTE and the cathode is connected to GND, which is the incorrect polarity for protecting a positive voltage rail. In this configuration, the diode is forward-biased during normal operation and will conduct current from VMOTE to GND, creating a short circuit path. This will prevent the VMOTE rail from functioning properly and will not provide overvoltage protection. For proper TVS protection of a positive rail, the anode should be connected to GND and the cathode should be connected to VMOTE. This would keep the diode reverse-biased during normal operation and allow it to clamp overvoltages by avalanching when the voltage exceeds the breakdown threshold. The current connection needs to be corrected by swapping the anode and cathode connections.
@allspice-carah please fix this issue and update any other channels.
Checkout
From your project repository, check out a new branch and test the changes.