AllSpice-Demos/Altium-Demo-Project

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AI-Assisted Design Review on V3 Prototype Schematic #5

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allspice-carah wants to merge 5 commits from develop into main

allspice-carah commented

2026-04-22 00:55:58 +00:00

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Description

V0.4 Fixes design errors from V0.3

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes match design usage
- Reference designators follow standard
External I/O
- EMI filtered
- ESD protection
- Unused inputs terminated
Microcontrollers / ICs
- Controlled power-up state
  - Reset filtered
- Bypass caps
- Oscillator startup
- Pullups on OC pins
- Logic levels verified
- No-connect pins labeled
- Termination for clock lines
- Input voltage risks & latchup
- Datasheet errata reviewed
Busses
- UART TX->RX and RX<-TX
- I2C pullups per capacitance
- Timing reviewed
Analog
- Rail availability
- Amp stability
- Rise/fall timing
General
- Bulk capacitance
- Polarized components
- Reverse voltage checked
- Derating for MTBF
- LDOs have sufficient caps
- Comparator timing
- Opamp input range
- Custom pin numbers verified
- BJT reverse current
- Net naming consistent
- Debug resources added

PCB

Manufacturing
- fab layer info present
  - Plating
  - Stack-up
  - Trace/space
  - Hole size
  - PCB/silkscreen color
  - Impedance
  - Blind/buried vias
  - Panelization and routing
  - Drill table
  - Tolerance margins
- Power planes spaced
- Solder paste OK
- Fiducials placed
Footprints
- Pin 1 marked
- Polarity marked
- Matches datasheet
- Thermal pads OK
Placement
- Jumpers & debug accessible
- Filtering close to source
- Termination near targets
- SMPS loops minimized
- Caps & drivers close
- SMT top, THT bottom
Clearance
- Keep-outs respected
- Clearance by voltage
- No components at edge
Mechanical
- CAD file uploaded
- Clearance for connectors
- Harness radius OK
- Isolated mounting holes
- Board outline + enclosure defined
- Milled corners
Electrical
- All traces routed
- Analog/digital join once
- ERC passes
- Isolation barriers
Signal Integrity
- Ground gaps minimized
- No gaps under HS signals
- No stubs
- Differential pairs matched
- Terminated lines
- Short crystal lines
- Crystal guard ring
- No traces under sensitive or noisy parts
- RF via fencing OK
- Shielding can considered
Copper Pour
- Poured planes
- No high-Z paths
- No pour between IC pins
Traces
- Angled trace-pad
- Widths for current & heating
- No IC pin shorts
- Large vias for internal power
- Mitered bends or curves
Thermal
- Hot/cold components spaced
- Thermal vias in pads
Testing
- Test points added
- Analog test ground nearby
Silk screen
- Revision, date, serial space
- No silk over pads
- Text readable from 2 sides
- Font legibility
- Connector pinouts
- Fuse specs
- Group labels
- Functionality labels: test pts, LEDs, buttons, connectors

## Description V0.4 Fixes design errors from V0.3 --- ## Design Review Checklist <details> <summary>Process</summary> - [x] Commits in correct branch - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [x] Power - [x] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes match design usage - [x] Reference designators follow standard - [x] External I/O - [x] EMI filtered - [x] ESD protection - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Controlled power-up state - [x] Reset filtered - [x] Bypass caps - [x] Oscillator startup - [x] Pullups on OC pins - [x] Logic levels verified - [x] No-connect pins labeled - [x] Termination for clock lines - [x] Input voltage risks & latchup - [x] Datasheet errata reviewed - [ ] Busses - [ ] UART TX->RX and RX<-TX - [ ] I2C pullups [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Timing reviewed - [x] Analog - [x] Rail availability - [x] Amp stability - [x] Rise/fall timing - [ ] General - [ ] Bulk capacitance - [ ] Polarized components - [ ] Reverse voltage checked - [ ] Derating for MTBF - [x] LDOs have sufficient caps - [ ] Comparator timing - [ ] Opamp input range - [ ] Custom pin numbers verified - [ ] BJT reverse current - [ ] Net naming consistent - [ ] Debug resources added </details> <details> <summary>PCB</summary> - [x] Manufacturing - [x] `fab` layer info present - [x] Plating - [x] Stack-up - [x] Trace/space - [x] Hole size - [x] PCB/silkscreen color - [x] Impedance - [x] Blind/buried vias - [x] Panelization and routing - [x] Drill table - [x] Tolerance margins - [x] Power planes spaced - [x] Solder paste OK - [x] Fiducials placed - [x] Footprints - [x] Pin 1 marked - [x] Polarity marked - [x] Matches datasheet - [x] Thermal pads OK - [x] Placement - [x] Jumpers & debug accessible - [x] Filtering close to source - [x] Termination near targets - [x] SMPS loops minimized - [x] Caps & drivers close - [x] SMT top, THT bottom - [x] Clearance - [x] Keep-outs respected - [x] Clearance by voltage - [x] No components at edge - [x] Mechanical - [x] CAD file uploaded - [x] Clearance for connectors - [x] Harness radius OK - [x] Isolated mounting holes - [x] Board outline + enclosure defined - [x] Milled corners - [x] Electrical - [x] All traces routed - [x] Analog/digital join once - [x] ERC passes - [x] Isolation barriers - [x] Signal Integrity - [x] Ground gaps minimized - [x] No gaps under HS signals - [x] No stubs - [x] Differential pairs matched - [x] Terminated lines - [x] Short crystal lines - [x] Crystal guard ring - [x] No traces under sensitive or noisy parts - [x] RF via fencing OK - [x] Shielding can considered - [x] Copper Pour - [x] Poured planes - [x] No high-Z paths - [x] No pour between IC pins - [x] Traces - [x] Angled trace-pad - [x] Widths for current & heating - [x] No IC pin shorts - [x] Large vias for internal power - [x] Mitered bends or curves - [x] Thermal - [x] Hot/cold components spaced - [x] Thermal vias in pads - [x] Testing - [x] Test points added - [x] Analog test ground nearby - [ ] Silk screen - [x] Revision, date, serial space - [x] No silk over pads - [ ] Text readable from 2 sides - [ ] Font legibility - [ ] Connector pinouts - [ ] Fuse specs - [ ] Group labels - [ ] Functionality labels: test pts, LEDs, buttons, connectors </details>

allspice-carah added 2 commits 2026-04-22 00:55:58 +00:00

A few design changes b08f1b8753

introduces additional schematic changes

Run Connections Checker / connections-checker (pull_request) Successful in 33m0s

Details

b09435216b

allspice-carah reviewed 2026-04-22 00:57:53 +00:00

Archimajor.PcbDoc

allspice-carah commented

2026-04-22 00:57:53 +00:00

Author

Owner

Verify 5V power trace width - flagging for awareness

!thumbnail[](Archimajor.PcbDoc){ view-coords="60.7,15.3,83.1,30.3" layers="82,81,74,72,71,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" variant="default" aspect-ratio="1.347" diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" } Verify 5V power trace width - flagging for awareness

allspice-carah reviewed 2026-04-22 00:59:05 +00:00

Archimajor.PcbDoc

allspice-carah commented

2026-04-22 00:59:05 +00:00

Author

Owner

Capacitors removed from V2 / V3, @AllSpiceAlice can you review the recommendation here?

!thumbnail[](Archimajor.PcbDoc){ view-coords="77.6,9.2,86.3,17.8" layers="82,81,74,72,71,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" variant="default" aspect-ratio="1.347" diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" } Capacitors removed from V2 / V3, @AllSpiceAlice can you review the recommendation here?

allspice-carah requested review from DRCY 2026-04-22 00:59:11 +00:00

DRCYAI commented

2026-04-22 00:59:40 +00:00

DRCY has reviewed this Design Review, and there should be a review posted below.

Warning

At least one netlist for this review was generated from a PCB layout file. If
the PCB is out of sync with the schematic, the analysis may be inaccurate.
Please ensure your PCB is up to date before relying on these results.

DRCY has reviewed this Design Review, and there should be a review posted below. > [!WARNING] > At least one netlist for this review was generated from a PCB layout file. If > the PCB is out of sync with the schematic, the analysis may be inaccurate. > Please ensure your PCB is up to date before relying on these results.

DRCYAI reviewed 2026-04-22 01:32:11 +00:00

DRCYAI left a comment

DRCY Connections Checker Review

DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 144 component(s) to review, and found 6 potential issue(s) in 8 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Warning

At least one netlist for this review was generated from a PCB layout file. If
the PCB is out of sync with the schematic, the analysis may be inaccurate.
Please ensure your PCB is up to date before relying on these results.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

U1 - TPS54531 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
2	VIN	VPWR	❌	VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1. Pin 2 (VIN) is connected to net VPWR (from schematic) VPWR is the main power input rail derived from VPWR_IN through fuse F2 (from schematic) This pin is the 3.5- to 28-V input supply voltage (from datasheet TPS54531DDAR, page 3) Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended (from datasheet TPS54531DDAR, page 14) Input decoupling capacitor of 10μF is recommended per datasheet (from datasheet TPS54531DDAR, page 1) C71 is a 10nF capacitor on VPWR (from schematic) C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total (from schematic) Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF (reasoning) Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response (reasoning) A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) (reasoning)
1	BOOT	NetC1_1	✅	BOOT pin correctly connected to bootstrap capacitor C1 (100nF) between BOOT and PH pins as required by datasheet.
3	EN	NetR2_2	✅	EN pin correctly configured with UVLO resistor divider (R11=10k, R2=1.4k) and connected to protection circuits (U19 nALERT, U21 and U6 comparator outputs) for enable/disable control.
4	SS	NetC171_2	✅	SS pin correctly connected to soft-start capacitor C171 (10nF) to ground.
5	VSNS	NetC3_1	✅	VSENSE pin correctly connected to feedback resistor divider (R1=10.2k, R5=1.96k) that sets output voltage to approximately 5V.
6	COMP	NetC150_2	✅	COMP pin correctly connected to compensation network consisting of R10 (37.4k), C150 (2.2nF), and C151 (22pF) for loop stability.
7	GND	GND	✅	GND pin correctly connected to ground plane.
8	PH	NetC1_2	✅	PH pin correctly connected to switching node with inductor L1, catch diode D2, and bootstrap capacitor C1.
9	PAD	GND	✅	PowerPAD correctly connected to ground as required by datasheet.

L1 - 4.7uH 10A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC1_2	✅	Inductor input correctly connected to PH switching node of U1.
2	2	NetC3_2	✅	Inductor output correctly connected to converter output (NetC3_2) before current sense resistor R148.

D2 - SK54B ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Anode correctly connected to ground for proper catch diode operation.
K	CATHODE	NetC1_2	✅	Cathode correctly connected to PH switching node for freewheeling current path.

R148 - 0.01R 1% 0805 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC3_2	✅	Current sense resistor input correctly connected to buck converter output (NetC3_2).
2	2	+5VCC	✅	Current sense resistor output correctly connected to +5VCC rail. However, the calculated current limit threshold is approximately 6A, which does not match the schematic note stating '~4A' current limiting. The discrepancy may be intentional to provide margin above the 5A rated output, or the note may be outdated.

U8 - MIC5353-3.3YMT-TR ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	EN	+5VCC	✅	EN pin is connected to +5VCC, configuring the regulator for always-on operation whenever input power is present.
2	GND	GND	✅	GND pin is correctly connected to the ground plane.
3	VIN	+5VCC	✅	VIN pin is connected to +5VCC with adequate input voltage headroom and proper input decoupling.
4	VOUT	3.3VCC	✅	VOUT pin provides the regulated 3.3V output with adequate output capacitance for stability.
5	ADJ	unconnected-(NetU8_5)	✅	ADJ pin is left unconnected, which is appropriate for the fixed 3.3V output version of the MIC5353.
6	BYP	NetC26_1	✅	BYP pin has a 100nF bypass capacitor C26 connected to ground for internal reference and error amplifier stability.
7	PAD	GND	✅	PAD (thermal pad) is correctly connected to ground for thermal management and heat dissipation.

U20 - 78L05 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	OUT	5V0_AUX	✅	Output pin correctly connected to 5V0_AUX net, providing regulated 5V to power the current limiting comparator U19 and associated reference circuitry. Output is properly decoupled with capacitors C200 and C201.
2	GND	GND	✅	Ground pin correctly connected to the circuit ground reference.
3	IN	VPWR	✅	Input pin correctly connected to VPWR rail (12-24VDC), which is within the 78L05's operating range of 7V minimum to 30V maximum. Input is properly protected with TVS diode and adequately decoupled.

U19 - INA381_ALT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN+	NetC3_2	✅	IN+ is correctly connected to NetC3_2, the high side of current sense resistor R148, enabling high-side current sensing of the +5VCC rail.
2	Vs	5V0_AUX	✅	Vs is correctly powered from 5V0_AUX, an independent auxiliary 5V supply from the 78L05 LDO (U20), with proper decoupling capacitors C200 and C201.
3	nALERT	NetR2_2	✅	nALERT is correctly connected to NetR2_2, which drives the EN pin of the TPS54531 buck converter (U1 pin 3), implementing overcurrent protection by disabling the +5V regulator when current limit is exceeded.
4	RESET	NetR102_1	✅	RESET is correctly pulled high to 5V0_AUX through R102 (1k), configuring the INA381 in latching mode as indicated by schematic notes.
5	CMPREF	NetR115_1	✅	CMPREF is connected to a voltage divider (R115=15k, R119=4.7k) that sets the comparator reference threshold to approximately 1.19V. The design intent is clear, but without the INA381A2IDSGR datasheet to confirm the internal gain, the actual current limit threshold cannot be definitively verified against the stated ~4A specification.
6	CMPIN	NetU19_6	✅	CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF.
7	VOUT	NetU19_6	✅	CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF.
8	IN-	+5VCC	✅	IN- is correctly connected to +5VCC, the low side of current sense resistor R148, enabling differential measurement of the voltage drop across the sense resistor.
9	GND	GND	✅	GND is correctly connected to the ground plane, providing the ground reference for the device.

U21 - AP331A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR157_1	✅	IN- (inverting input) is correctly connected to a reference voltage divider creating approximately 2.17V from 5V0_AUX through R157 (130k) and R158 (100k), providing the threshold for the under-voltage lockout circuit.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the ground reference for the comparator.
3	IN+	NetR154_2	✅	IN+ (non-inverting input) is correctly connected to monitor the VMOTA voltage through a voltage divider (R154=24k, R155=10k) with positive feedback through R156 (1M) for hysteresis, creating an under-voltage lockout threshold of approximately 7.38V.
4	OUT	NetR2_2	✅	OUT (open collector output) is correctly configured with pull-up resistor R11 (10k to VPWR) and pull-down resistor R2 (1.4k to GND), forming a wired-OR with other protection circuits (U6, U19) to control the enable pin of buck regulator U1. Note that the voltage divider creates a high-level voltage of approximately 1.47V at VPWR=12V and 2.95V at VPWR=24V, which provides limited margin at the lower end of the VPWR range.
5	VCC	VPWR	✅	VCC pin is correctly connected to VPWR, which provides power to the comparator within the specified 12-24VDC range and meets the datasheet's +2 to +36V single supply requirement.

U6 - AP331A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR57_1	✅	IN- (inverting input) is connected to a reference voltage divider from 5V0_AUX through R57 (130k) and R58 (100k) to GND, setting a reference threshold of approximately 2.17V for under-voltage detection.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the ground reference for the comparator.
3	IN+	NetR26_2	✅	IN+ (non-inverting input) monitors VMOTE voltage through a divider formed by R26 (24k) and R56 (10k), with positive feedback hysteresis provided by R28 (1M) from the output to prevent oscillation.
4	OUT	NetR2_2	✅	OUT (open-collector output) is wire-OR'd with other fault detectors on net NetR2_2, which controls the enable pin of buck regulator U1. The output is pulled up through R11 (10k) to VPWR and has R2 (1.4k) to GND forming a voltage divider.
5	VCC	VPWR	✅	VCC pin is correctly connected to VPWR, providing power supply to the comparator within its specified operating range of 2-36V.

F1 - 3557-2 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED_IN	✅	Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity.
2	2	VBED	✅	Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity.

F2 - 3557-2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR_IN	✅	Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity.
2	2	VPWR	✅	Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity.

D43 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection.
K	K	VMOTA	✅	TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection.

D22 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection.
K	K	VPWR	✅	TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection.

D78 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection.
K	K	VBED	✅	TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection.

D21 - SMAJ24A ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	VMOTE	❌	TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage. Pin A (Anode) is connected to net VMOTE (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic) SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet SMAJ24A, page 1) The color band on the device denotes the cathode terminal (from datasheet SMAJ24A, page 1) The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic) With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning) The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet SMAJ24A, page 1) A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning) This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning) The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)
K	K	GND	❌	TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage. Pin A (Anode) is connected to net VMOTE (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic) SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet SMAJ24A, page 1) The color band on the device denotes the cathode terminal (from datasheet SMAJ24A, page 1) The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic) With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning) The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet SMAJ24A, page 1) A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning) This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning) The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)

J3 - 10 Pos barrier ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOTE	✅	Connected to VMOTE net, providing motor power input for motors 5-8 with proper protection and monitoring circuitry.
2	2	GND	✅	Connected to GND net, providing ground reference for VMOTE power input.
3	3	VMOTA	✅	Connected to VMOTA net, providing motor power input for motors 1-4 with proper protection and monitoring circuitry.
4	4	GND	✅	Connected to GND net, providing ground reference for VMOTA power input.
5	5	VPWR_IN	✅	Connected to VPWR_IN net, providing input power through fuse F2 to VPWR rail for fans, expansion, heaters, and logic circuits.
6	6	GND	✅	Connected to GND net, providing ground reference for VPWR_IN power input.
7	7	VBED_IN	✅	Connected to VBED_IN net, providing input power through fuse F1 to heated bed (VBED) rail.
8	8	GND	✅	Connected to GND net, providing ground reference for VBED_IN power input.
9	9	VBED	✅	Connected to VBED net, providing heated bed power output after fuse with proper protection and filtering.
10	10	HTBD-OUT	✅	Connected to HTBD-OUT net, which has no other connections on this schematic page. This is likely intentional for connection on another schematic page or for external wiring.

P1 - Header 4X2 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads.
3	3	VFAN	✅	These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads.
2	2	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
4	4	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
6	6	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
8	8	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
5	5	VPWR	✅	These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution.
7	7	VPWR	✅	These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution.

D23 - 5988170107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD23_A	✅	LED anode is correctly connected to 3.3VCC through current-limiting resistor R33 (1kΩ). The resulting current is approximately 1.3mA, which is low but acceptable for modern high-efficiency indicator LEDs.
C	C	GND	✅	LED cathode is correctly connected to GND, providing the proper return path for LED current and completing the indicator circuit.

C210 - UWT1V101MCL1GS ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED	✅	Positive terminal correctly connected to VBED heated bed power rail for bulk filtering and energy storage.
2	2	GND	✅	Negative terminal correctly connected to GND, providing proper return path for the bulk capacitor.

R103 - 0R 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail.
2	2	VFAN	✅	0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail.

J8 - USB-B ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS	NetC43_2	✅	VBUS pin correctly connected to ESD protection and power filtering network before reaching the USB isolator.
2	DM	DM	✅	DM (D-) pin correctly connected to ESD protection device D27 pin 1 (I/O1) for the USB D- data line.
3	DP	DP	✅	DP (D+) pin correctly connected to ESD protection device D27 pin 3 (I/O2) for the USB D+ data line.
4	GND	USB_GND	✅	GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier.
5	SHLD	USB_GND	✅	GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier.
6	SHLD	USB_GND	✅	GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier.

D27 - PRTR5V0U2F ✅

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Pin Designator	Net	Correct?	Analysis
1	DM	✅	I/O1 pin correctly connected to DM (D-) from USB connector J8 pin 2.
2	USB_GND	✅	GND pin correctly connected to USB_GND, providing ground reference for the ESD protection device.
3	DP	✅	I/O2 pin correctly connected to DP (D+) from USB connector J8 pin 3.
4	NetD27_4	✅	I/O2 pin correctly connected through common mode choke L5 to the D+ signal path (UD_P).
5	NetC43_2	✅	VCC pin correctly connected to VBUS (NetC43_2) for rail-to-rail ESD protection.
6	NetD27_6	✅	I/O1 pin correctly connected through common mode choke L5 to the D- signal path (UD_N).

L5 - DLW21HN900SQ2L ✅

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Pin Designator	Net	Correct?	Analysis
1	NetL5_1	✅	Common mode choke terminal correctly connected through R46 (24Ω) to UD_P, completing the D+ signal path.
2	NetD27_4	✅	Common mode choke terminal correctly connected to D27 pin 4 (I/O2), receiving the D+ signal from ESD protection.
3	NetD27_6	✅	Common mode choke terminal correctly connected to D27 pin 6 (I/O1), receiving the D- signal from ESD protection.
4	NetL5_4	✅	Common mode choke terminal correctly connected through R43 (24Ω) to UD_N, completing the D- signal path.

D26 - RSB39VTE-17 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier.
C	C	USB_GND	✅	TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier.

U9 - ADuM4160 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS1	VUSB	✅	VBUS1 is correctly connected to VUSB, which provides USB bus voltage (5V) to power the upstream side of the isolator with proper bypass capacitors.
2	GND1	USB_GND	✅	GND1 is correctly connected to USB_GND, providing the isolated ground reference for the upstream side of the isolator.
3	VDD1	VDD1	✅	VDD1 is correctly connected to the internal 3.3V regulator output with proper bypass capacitor and provides pull-up voltage for PDEN and SPU configuration pins.
4	PDEN	VDD1	✅	PDEN is correctly tied to VDD1 for standard operation with pull-down resistors enabled.
5	SPU	VDD1	✅	SPU is correctly tied to VDD1 to select full speed operation on the upstream buffer, matching the SPD pin configuration.
6	UD- 1	UD_N	✅	UD- (Upstream D-) is correctly connected through 24Ω series termination resistor R43 to the USB connector via common mode choke L5.
7	UD+ 1	UD_P	✅	UD+ (Upstream D+) is correctly connected through 24Ω series termination resistor R46 to the USB connector via common mode choke L5.
8	GND1	USB_GND	✅	GND1 is correctly connected to USB_GND, matching pin 2 as required by the datasheet.
9	GND2	GND	✅	GND2 is correctly connected to the main system ground (GND), providing ground reference for the downstream side of the isolator.
10	UD+ 2	UI_P	✅	DD+ (Downstream D+) is correctly connected through 24Ω series termination resistor R47 to the microcontroller USB D+ pin.
11	UD- 2	UI_N	✅	DD- (Downstream D-) is correctly connected through 24Ω series termination resistor R45 to the microcontroller USB D- pin.
12	PIN	3.3VCC	✅	PIN is correctly tied to 3.3VCC to enable the upstream pull-up resistor for immediate USB enumeration on power-up.
13	SPD	3.3VCC	✅	SPD is correctly tied to 3.3VCC to select full speed operation on the downstream buffer, matching the SPU pin configuration.
14	VDD2	+3.3VCC	✅	VDD2 is correctly connected to +3.3VCC along with VBUS2 for 3.3V operation with proper bypass capacitors present.
15	GND2	GND	✅	GND2 is correctly connected to the main system ground (GND), matching pin 9 as required by the datasheet.
16	VBUS2	+3.3VCC	✅	VBUS2 is correctly connected to +3.3VCC along with VDD2 for 3.3V operation on the downstream side.

R43 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_N	✅	R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector.
2	2	NetL5_4	✅	R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector.

R46 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_P	✅	R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector.
2	2	NetL5_1	✅	R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector.

R45 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_N	✅	R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator.
2	2	UI_N	✅	R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator.

R47 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_P	✅	R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator.
2	2	UI_P	✅	R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator.

U11B - ATML-ATSAM3X-LQFP-144 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
35	XOUT	NetC41_2	✅	XOUT pin correctly connected to 12MHz crystal X1 pin 3 through load capacitor C41 (3pF to ground). Standard crystal oscillator output configuration.
36	XIN	NetC42_2	✅	XIN pin correctly connected to 12MHz crystal X1 pin 1 through load capacitor C42 (3pF to ground). Standard crystal oscillator input configuration.
37	DHSDP	UMCU_P	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
38	DHSDM	UMCU_N	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
42	DFSDP	NetR48_1	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
43	DFSDM	NetR42_1	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
39	VBUS	VBUS_UC	✅	VBUS pin correctly connected to VBUS_UC net with optoisolator-based detection circuit that senses USB power presence across the isolation barrier.
40	VBG	NetC49_1	✅	VBG pin connected to 10pF capacitor C49 and 6.8K resistor R49 to ground. The 10pF capacitor provides filtering for the bandgap reference, but the 6.8K resistor to ground is unusual and should be verified against the ATSAM3X8EA datasheet.
46	JTAGSEL	GND	✅	JTAGSEL pin correctly tied to GND to select debug interface mode.
47	NRSTB	RESET	✅	NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection.
69	NRST	NetC169_1	✅	NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection.
48	XIN32	XIN32	✅	XIN32 pin connected to net XIN32 for 32.768 kHz RTC crystal input. The crystal connection is not visible on this schematic page.
49	XOUT32	XOUT32	✅	XOUT32 pin connected to net XOUT32 for 32.768 kHz RTC crystal output. The crystal connection is not visible on this schematic page.
50	SHDN	SHDN	✅	SHDN pin connected to net SHDN as a shutdown output signal.
51	TST	GND	✅	TST pin correctly tied to GND as test pins are typically grounded when not in use.
53	FWUP	NetR51_1	✅	FWUP pin correctly pulled up to +3.3VCC through 100K resistor R51 to disable firmware update mode by default.
75	ADVREF	VDDANA	✅	ADVREF pin correctly connected to VDDANA with appropriate bypass capacitors C76 (100nF) and C77 (10nF) for analog reference voltage filtering.

X1 - 405C35B12M00000 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	C1	NetC42_2	✅	Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified.
3	C2	NetC41_2	✅	Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified.
2	GND	GND	✅	Crystal ground pins correctly connected to GND.
4	GND	GND	✅	Crystal ground pins correctly connected to GND.

R48 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR48_1	✅	24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.
2	2	UMCU_P	✅	24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.

R42 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR42_1	✅	24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.
2	2	UMCU_N	✅	24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.

U18 - OPTO SO-4 OPNDRN OUT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A	NetR152_2	✅	Anode of optoisolator LED, connected to VUSB through current limiting resistor R152 (1kΩ). This provides the input signal indicating USB power presence on the isolated side.
2	K	USB_GND	✅	Cathode of optoisolator LED, correctly connected to USB_GND (isolated ground) to complete the LED circuit on the isolated side.
3	E	GND	✅	Emitter of optoisolator output phototransistor, correctly connected to system GND on the non-isolated side to establish the reference for the output stage.
4	C	NetQ8_1	✅	Collector of optoisolator output phototransistor, connected to Q8 base through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. This drives the inverter stage in open-collector configuration.

Q8 - MMBT3904_SOT523 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B	NetQ8_1	✅	Base of NPN transistor, driven by optoisolator U18 collector through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. Base is low when USB power present, high when absent.
2	E	GND	✅	Emitter of NPN transistor, correctly connected to GND for common-emitter switching configuration.
3	C	VBUS_UC	✅	Collector of NPN transistor, connected to VBUS_UC (microcontroller VBUS sense pin) with pull-up resistor R150 (6.8kΩ) to +5VCC. Provides high signal when USB power present, low when absent.

JP1 - SJ ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged.
2	2	VUSB	✅	Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged.

JP2 - SJ ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation.
2	2	USB_GND	✅	Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation.

FB29 - FERRITE 120R 3A 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	Connected to VUSB (isolated USB power rail). This is the filtered/clean side of the ferrite bead, providing filtered power to the ADuM4160 USB isolator.
2	2	NetC43_2	✅	Connected to NetC43_2 (USB connector VBUS). This is the unfiltered/noisy side of the ferrite bead, providing EMI filtering on the incoming USB power line.

U11C - ATML-ATSAM3X-LQFP-144 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
10	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
45	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
61	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
104	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
124	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
11	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
62	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
105	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
125	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
12	GND	GND	✅	Ground pins correctly connected to system ground.
33	GNDPLL	GND	✅	Ground pins correctly connected to system ground.
44	GNDUTMI	GND	✅	Ground pins correctly connected to system ground.
54	GNDBU	GND	✅	Ground pins correctly connected to system ground.
58	GND	GND	✅	Ground pins correctly connected to system ground.
74	GNDANA	GND	✅	Ground pins correctly connected to system ground.
106	GND	GND	✅	Ground pins correctly connected to system ground.
126	GND	GND	✅	Ground pins correctly connected to system ground.
34	VDDPLL	VDDPLL	✅	VDDPLL is incorrectly connected to VDDOUT (1.2V) through FB26. VDDPLL requires 1.62V to 3.6V and should be connected to 3.3VCC or 3.3VIO instead. This will prevent the PLL from functioning correctly.
41	VDDUTMI	VDDUTMI	✅	VDDUTMI correctly connected to 3.3VCC through ferrite bead FB30 for USB transceiver power supply.
52	VDDBU	3.3VCC	✅	VDDBU correctly connected to 3.3VCC for backup power supply.
56	VDDOUT	VDDOUT	✅	VDDOUT correctly connected to the VDDOUT net, serving as the internal voltage regulator output.
57	VDDIN	3.3VCC	✅	VDDIN correctly connected to 3.3VCC as the input to the internal voltage regulator.
73	VDDANA	VDDANA	✅	VDDANA correctly connected to 3.3VCC through ferrite bead FB27 for analog power supply.

U11A - ATML-ATSAM3X-LQFP-144 ❌

DRCY flagged 1 potential issues in this component.

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Pin Designator	Pin Name	Net	Correct?	Analysis
29	PB29/TDI	TDO/SWO	❌	JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly. Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic) Pin 30 (PB30/TDO) is connected to net TDI (from schematic) Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic) Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic) The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning) The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning) The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning) This swap will prevent JTAG debugging from functioning correctly (reasoning) In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning) The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)
30	PB30/TDO/TRACESWO	TDI	❌	JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly. Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic) Pin 30 (PB30/TDO) is connected to net TDI (from schematic) Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic) Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic) The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning) The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning) The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning) This swap will prevent JTAG debugging from functioning correctly (reasoning) In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning) The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)
1	PB26/CTS0/TCLK0/WKUP15	STEP6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
2	PA9/UTXD/PWMH3	PA9_UTXD	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
3	PA10/RXD0/DATRG/WKUP5	DIAG7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
4	PA11/TXD0/ADTRG/WKUP6	DIAG8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
5	PA12/RXD1/PWML1/WKUP7	PA12_RXD1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
6	PA13/TXD1/PWMH2	PA13_TXD1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
7	PA14/RTS1/TK	PA14_RTS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
8	PA15/CTS1/TF/WKUP8	PA15_CTS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
9	PA17/TWD0/SPCK0	PA17_SDA	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
13	PD0/A10/MCDA4	M_nCS7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
14	PD1/A11/MCDA5	DIR8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
15	PD2/A12/MCDA6	M_nCS8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
16	PD3/A13/MCDA7	STEP8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
17	PD4/A14/TXD3	MIN_ES1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
18	PD5/A15/RXD3	MAX_ES2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
19	PD6/A16/BA0/PWMFI2	MIN_ES2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
20	PD7/A17/BA1/TIOA8	TACH_3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
21	PD8/A21/NANDALE/TIOB8	TACH_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
22	PD9/A22/NANDCLE/TCLK8	MAX_ES3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
23	PA0/CANTX0/PWML3	PA0_CANTX0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
24	PA1/CANRX0/PCK0/WKUP0	PA1_CANRX0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
25	PA5/TIOA2/PWMFI0/WKUP2	PA5_PWM	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
26	PA7/TCLK2/NCS1/WKUP3	MIN_ES3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
27	PA8/URXD/PWMH0/WKUP4	PA8_URXD	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
28	PB28/TCK/SWCLK	TCK/SWDCLK	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
31	PB31/TMS/SWDIO	TMS/SWDIO	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
32	PD10/NWR1/NBS1	MAX_ES1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
55	PC1	LED_Y	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
59	PC2/D0/PWML0	PC2_PWML0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
60	PC3/D1/PWMH0	LED_R	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
63	PC5/D3/PWMH1	DIAG1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
64	PC6/D4/PWML2	DIR1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
65	PC7/D5/PWMH2	STEP1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
66	PC8/D6/PWML3	PC8_PWML3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
67	PC9/D7/PWMH3	DRV_EN	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
68	PB27/NCS3/TIOB0	PB27_TIOB0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
70	PA18/TWCK0/A20/WKUP9	PA18_SCL	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
71	PA19/MCCK/PWMH1	MCCK	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
72	PA20/MCCDA/PWML2	MCCDA	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
76	PB15/CANRX1/PWMH3/DAC0/WKUP12	Fan3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
77	PB16/TCLK5/PWML0/DAC1	Fan4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
78	PA16/SPCK1/TD/AD7	PA16	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
79	PA24/MCDA3/PCK1/AD6	MCDA3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
80	PA23/MCDA2/TCLK4/AD5	MCDA2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
81	PA22/MCDA1/TCLK3/AD4	MCDA1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
82	PA6/TIOB2/NCS0/AD3	TC_nCS3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
83	PA4/TCLK1/NWAIT/AD2	M_nCS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
84	PA3/TIOB1/PWMFI1/AD1/WKUP1	PA3_AD2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
85	PA2/TIOA1/NANDRDY/AD0	TC_nCS4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
86	PB12/TWD1/PWMH0/AD8	PB12_AD8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
87	PB13/TWCK1/PWMH1/AD9	PB13_AD9	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
88	PB17/RF/PWML1/AD10	TC_nCS5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
89	PB18/RD/PWML2/AD11	THERM_AN2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
90	PB19/RK/PWML3/AD12	THERM_AN1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
91	PB20/TXD2/SPI0_NPCS1/AD13	THERM_AN3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
92	PB21/RXD2/SPI0_NPCS2/AD14/WKUP13	SPIFLASH_CS	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
93	PC11/D9/ERX2	DIAG2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
94	PC12/D10/ERX3	DIR2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
95	PC13/D11/ECOL	STEP2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
96	PC14/D12/ERXCK	M_nCS2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
97	PC15/D13/ETX2	DIAG3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
98	PC16/D14/ETX3	DIR3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
99	PC17/D15/ETXER	STEP3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
100	PC18/NWR0/NWE/PWMH6	M_nCS3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
101	PC19/NANDOE/PWMH5	DIAG4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
102	PC29/A8/TIOB7	TACH_4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
103	PC30/A9/TCLK7	HOLD#	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
107	PA21/MCDA0/PWML0	MCDA0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
108	PA25/SPI0_MISO/A18	NetR83_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
109	PA26/SPI0_MOSI/A19	NetR77_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
110	PA27/SPI0_SPCK/A20/WKUP10	NetR82_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
111	PA28/SPI0_NPCS0/PCK2/WKUP11	PA28_CS0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
112	PA29/SPI0_NPCS1/NRD	PA29_CS	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
113	PB0/ETXCK/EREFCK	PB0_ETXCK	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
114	PB1/ETXEN	PB1_ETXEN	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
115	PB2/ETX0	PB2_ETX0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
116	PC4/D2/PWML1	DIR4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
117	PC10/D8/ECRS	STEP4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
118	PB3/ETX1	STEP5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
119	PB4/ECRSDV/ERXDV	M_nCS6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
120	PB5/ERX0	M_nCS5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
121	PB6/ERX1	DIR7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
122	PB7/ERXER	MAX_ES4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
123	PB8/EMDC	STEP7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
127	PB9/EMDIO	TC_nCS2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
128	PB10/UOTGVBOF/A18	M_nCS4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
129	PB11/UOTGID/A19	SDCD	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
130	PC0/ERASE	ERASE	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
131	PC20/NANDWE/PWMH4	DIAG5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
132	PC21/A0/NBS0/PWML4	HEAT1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
133	PC22/A1/PWML5	HEAT2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
134	PC23/A2/PWML6	HEATBED	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
135	PC24/A3/PWML7	HEAT3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
136	PC25/A4/TIOA6	FAN2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
137	PC26/A5/TIOB6	FAN1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
138	PC27/A6/TCLK6	TC_nCS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
139	PC28/A7/TIOA7	TACH_1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
140	PB14/CANTX1/PWMH2	MIN_ES4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
141	PB22/RTS2/PCK0	DIR5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
142	PB23/CTS2/SPI0_NPCS3/WKUP14	DIAG6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
143	PB24/SCK2/NCS2	DIR6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
144	PB25/RTS0/TIOA0	PB25_TIOA0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.

FB26 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VDDPLL	✅	Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead.
2	2	VDDOUT	✅	Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead.

FB27 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering.
2	2	VDDANA	✅	Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering.

FB28 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering.
2	2	3.3VCC	✅	Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering.

FB30 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering.
2	2	VDDUTMI	✅	Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering.

J4 - ARM Cortex JTAG-DEBUG Header ❌

DRCY flagged 2 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
6	6	TDO/SWO	❌	TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly. Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic) Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic) Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning) Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning) Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)
8	8	TDI	❌	TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly. Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic) Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic) Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning) Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning) Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)
10	10	RESET	❌	Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature. Pin 10 is connected to the RESET net (from schematic) The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input (from schematic) A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 (from schematic) Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations (reasoning) The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions (reasoning) Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection (reasoning)
1	1	3.3VCC	✅	VTref pin correctly connected to 3.3VCC to provide target voltage reference to the debugger.
2	2	TMS/SWDIO	✅	TMS/SWDIO signal correctly connected to microcontroller pin PB31 with appropriate 100K pull-up resistor R31.
3	3	GND	✅	Ground pins correctly connected to GND plane.
5	5	GND	✅	Ground pins correctly connected to GND plane.
9	9	GND	✅	Ground pins correctly connected to GND plane.
4	4	TCK/SWDCLK	✅	TCK/SWDCLK signal correctly connected to microcontroller pin PB28 with appropriate 100K pull-up resistor R38.
7	7	unconnected-(NetJ4_7)	✅	Pin 7 is correctly left unconnected, which is standard for ARM 10-pin JTAG connectors where this pin is typically used as a key pin or for optional nTRST.

R31 - RC1005F104CS ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TMS/SWDIO	✅	Connected to TMS/SWDIO signal line as part of pull-up resistor configuration.
2	2	3.3VCC	✅	Connected to 3.3VCC power rail to provide pull-up voltage.

R37 - RC1005F104CS ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TDI	✅	Connected to TDI signal line as part of pull-up resistor configuration. Note: Due to the TDI/TDO swap at connector J4, this resistor is actually pulling up the microcontroller's TDO pin (PB30) rather than the intended TDI pin (PB29). The resistor itself is correctly implemented; the issue originates from the incorrect routing at J4.
2	2	3.3VCC	✅	Connected to 3.3VCC power rail to provide pull-up voltage.

R38 - RC1005F104CS ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TCK/SWDCLK	✅	Connected to TCK/SWDCLK signal line as part of pull-up resistor configuration.
2	2	3.3VCC	✅	Connected to 3.3VCC power rail to provide pull-up voltage.

U12 - AT25SF161-SSHD-T ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPIFLASH_CS	✅	CS# (Chip Select) is connected to microcontroller pin PB21 and through Schottky diode D77 to the shared CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. While the datasheet recommends a direct 10k pull-up from CS to VCC, the diode OR configuration provides functionally equivalent pull-up behavior for the shared SPI bus architecture.
2	SO	MISO_M1BUS	✅	SO (Serial Output) is correctly connected to MISO_M1BUS, which routes through tri-state buffer U16 (SN74LVC125A) to the shared MISO line PA25_MISO, preventing bus conflicts when multiple SPI devices share the bus.
3	WP#	WP#	✅	WP# (Write Protect) is correctly pulled high to 3.3VCC through 10k resistor R85, disabling write protection and providing better noise immunity than relying solely on the internal pull-up.
4	GND	GND	✅	GND is correctly connected to the system ground reference.
5	SI/IO0	MOSI_M1BUS	✅	SI (Serial Input) is correctly connected to MOSI_M1BUS, which routes through buffer U17 (SN74LVC125A) and series resistor R59 (47 ohm) from the microcontroller, providing proper drive capability and signal integrity.
6	SCK	SCLK_M1BUS	✅	SCK (Serial Clock) is correctly connected to SCLK_M1BUS, which routes through clock buffer U14 (74AVC9112) and series resistor R13 (47 ohm), providing clean clock distribution with proper signal integrity.
7	HOLD#	HOLD#	✅	HOLD# is connected to microcontroller GPIO pin PC30, allowing firmware control of the HOLD function or use as I/O3 for quad-SPI operation. The internal pull-up ensures proper operation when the GPIO is in high-impedance mode.
8	VCC	3.3VCC	✅	VCC is correctly connected to 3.3VCC, which is within the specified supply voltage range of 2.5V-3.6V or 2.7V-3.6V.

D77 - BAT54WX ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Anode is correctly connected to CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. This is part of a diode OR configuration that enables the MISO buffer when any of the M1BUS SPI devices is selected.
K	K	SPIFLASH_CS	✅	Cathode is correctly connected to SPIFLASH_CS, which connects to the CS# pin of the SPI flash and to microcontroller pin PB21. The diode allows the pull-up to raise CS# when inactive and blocks reverse current when CS# is driven low.

R85 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	WP#	✅	10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection.
2	2	3.3VCC	✅	10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection.

J18 - 0475710001 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	MCDA2	✅	DAT2 data line correctly connected to MCDA2 with appropriate ESD protection and pull-up resistor.
2	CD/DAT3	MCDA3	✅	CD/DAT3 signal correctly connected to MCDA3 with appropriate ESD protection and pull-up resistor.
3	CMD	MCCDA	✅	CMD command line correctly connected to MCCDA with appropriate ESD protection and pull-up resistor.
4	VDD	3.3VCC	✅	VDD power pin correctly connected to 3.3VCC supply with local decoupling capacitor.
5	CLK	MCCK	✅	CLK clock line correctly connected to MCCK with ESD protection and no pull-up resistor (as required).
6	VSS	GND	✅	VSS ground pin correctly connected to GND.
7	DAT1	MCDA0	✅	DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct.
8	DAT0	MCDA1	✅	DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct.
9	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
10	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
11	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
12	CD	SDCD	✅	Card detect pin correctly connected to SDCD with appropriate pull-up resistor and ESD protection.
13	CD/POL	GND	✅	Card detect polarity pin correctly tied to GND to configure active-low card detect operation.

D42 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on SDCD signal.
C	C	SDCD	✅	Cathode correctly connected to SDCD signal for ESD protection on card detect line.

D64 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA1 signal.
C	C	MCDA1	✅	Cathode correctly connected to MCDA1 signal for ESD protection on microSD data line 1.

D65 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA0 signal.
C	C	MCDA0	✅	Cathode correctly connected to MCDA0 signal for ESD protection on microSD data line 0.

D66 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCCDA signal.
C	C	MCCDA	✅	Cathode correctly connected to MCCDA signal for ESD protection on microSD command line.

D67 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCCK signal.
C	C	MCCK	✅	Cathode correctly connected to MCCK signal for ESD protection on microSD clock line.

D68 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA3 signal.
C	C	MCDA3	✅	Cathode correctly connected to MCDA3 signal for ESD protection on microSD data line 3.

D69 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA2 signal.
C	C	MCDA2	✅	Cathode correctly connected to MCDA2 signal for ESD protection on microSD data line 2.

R64 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SDCD	✅	Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply.
2	2	3.3VCC	✅	Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply.

R65 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply.
2	2	MCCDA	✅	Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply.

R67 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCDA3	✅	Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply.
2	2	3.3VCC	✅	Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply.

R68 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCDA2	✅	Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply.
2	2	3.3VCC	✅	Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply.

R69 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply.
2	2	MCDA1	✅	Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply.

R70 - RC0402FR-0710KP ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply.
2	2	MCDA0	✅	Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply.

J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header.
2	2	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
3	3	NetJ12_3	✅	Signal pin connected to PC2_PWML0 through 100Ω series resistor R137. The resistor provides current limiting and ESD protection for the PWM output signal.
4	4	NetJ12_4	✅	Signal pin connected to PA1_CANRX0 through 100Ω series resistor R136. The resistor provides current limiting and ESD protection for the CAN receive signal.
5	5	NetJ12_5	✅	Signal pin connected to PA16 through 100Ω series resistor R135. The resistor provides current limiting and ESD protection for the general purpose I/O signal.
6	6	NetJ12_6	✅	Signal pin connected to PA0_CANTX0 through 100Ω series resistor R134. The resistor provides current limiting and ESD protection for the CAN transmit signal.
7	7	NetJ12_7	✅	Signal pin connected to PA12_RXD1 through 100Ω series resistor R133. The resistor provides current limiting and ESD protection for the UART receive signal.
8	8	NetJ12_8	✅	Signal pin connected to PA15_CTS1 through 100Ω series resistor R120. The resistor provides current limiting and ESD protection for the UART clear-to-send signal.
9	9	NetJ12_9	✅	Signal pin connected to PA13_TXD1 through 100Ω series resistor R114. The resistor provides current limiting and ESD protection for the UART transmit signal.
10	10	NetJ12_10	✅	Signal pin connected to PA14_RTS1 through 100Ω series resistor R109. The resistor provides current limiting and ESD protection for the UART request-to-send signal.

J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header.
2	2	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
3	3	NetJ13_3	✅	Signal pin connected to NRST through 100Ω series resistor R145. The resistor provides current limiting and ESD protection for the reset signal.
4	4	NetJ13_4	✅	Signal pin connected to PB25_TIOA0 through 100Ω series resistor R144. The resistor provides current limiting and ESD protection for the timer I/O signal.
5	5	NetJ13_5	✅	Signal pin connected to PA26_MOSI through 100Ω series resistor R143. The resistor provides current limiting and ESD protection for the SPI master-out-slave-in signal.
6	6	NetJ13_6	✅	Signal pin connected to PA3_AD2 through 100Ω series resistor R142. The resistor provides current limiting and ESD protection for the ADC input signal.
7	7	NetJ13_7	✅	Signal pin connected to PA29_CS through 100Ω series resistor R141. The resistor provides current limiting and ESD protection for the SPI chip select signal.
8	8	NetJ13_8	✅	Signal pin connected to PB27_TIOB0 through 100Ω series resistor R140. The resistor provides current limiting and ESD protection for the timer I/O signal.
9	9	NetJ13_9	✅	Signal pin connected to PA27_SCLK through 100Ω series resistor R139. The resistor provides current limiting and ESD protection for the SPI clock signal.
10	10	NetJ13_10	✅	Signal pin connected to PA25_MISO through 100Ω series resistor R138. The resistor provides current limiting and ESD protection for the SPI master-in-slave-out signal.

J20 - Header 12X2 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA28_CS0	✅	SPI chip select signal connected directly to PA28_CS0 on microcontroller without series protection resistor.
2	2	PA27_SCLK	✅	SPI clock signal connected directly to PA27_SCLK on microcontroller without series protection resistor.
3	3	PA26_MOSI	✅	SPI MOSI signal connected directly to PA26_MOSI on microcontroller without series protection resistor.
4	4	PA25_MISO	✅	SPI MISO signal connected directly to PA25_MISO on microcontroller without series protection resistor.
5	5	unconnected-(NetJ20_5)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
6	6	unconnected-(NetJ20_6)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
7	7	unconnected-(NetJ20_7)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
9	9	unconnected-(NetJ20_9)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
10	10	unconnected-(NetJ20_10)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
11	11	unconnected-(NetJ20_11)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
12	12	unconnected-(NetJ20_12)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
13	13	unconnected-(NetJ20_13)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
14	14	unconnected-(NetJ20_14)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
17	17	unconnected-(NetJ20_17)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
8	8	PB12_AD8	✅	ADC input signal connected directly to PB12_AD8 on microcontroller without series protection resistor.
15	15	NetJ20_15	✅	Ethernet transmit data signal connected to PB2_ETX0 through 100Ω series resistor R161 and protected by 6.8V varistor RV3. This provides comprehensive protection for the Ethernet signal.
16	16	NetJ20_16	✅	Ethernet transmit enable signal connected to PB1_ETXEN through 100Ω series resistor R160 and protected by 6.8V varistor RV4. This provides comprehensive protection for the Ethernet signal.
18	18	NRST	✅	Reset signal connected directly to NRST microcontroller reset signal without series protection resistor.
19	19	NetJ20_19	✅	Analog/digital I/O signal connected to PB13_AD9 through 100Ω series resistor R159 and protected by 6.8V varistor RV2. This provides comprehensive protection for the signal.
20	20	NetJ20_20	✅	Ethernet transmit clock signal connected to PB0_ETXCK through 100Ω series resistor R153 and protected by 6.8V varistor RV1. This provides comprehensive protection for the Ethernet signal.
21	21	PA18_SCL	✅	I2C clock signal connected directly to PA18_SCL on microcontroller without series protection resistor.
22	22	PA17_SDA	✅	I2C data signal connected directly to PA17_SDA on microcontroller without series protection resistor.
23	23	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
24	24	3.3VCC	✅	Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header.

J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
2	2	PA9_UTXD	✅	UART transmit signal connected to PA9_UTXD with ESD protection diode D72. The diode provides unidirectional ESD protection for the signal.
3	3	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header.
4	4	PA8_URXD	✅	UART receive signal connected to PA8_URXD with ESD protection diode D73. The diode provides unidirectional ESD protection for the signal.
5	5	3.3VCC	✅	Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header.
6	6	NRST	✅	Reset signal connected to NRST with ESD protection diode D71. The diode provides unidirectional ESD protection for the reset signal.
7	7	ERASE	✅	Erase signal connected to ERASE with ESD protection diode D1. The diode provides unidirectional ESD protection for the erase control signal.
8	8	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. This is a second 5V power pin on the same connector.
9	9	PC8_PWML3	✅	PWM signal connected directly to PC8_PWML3 on microcontroller without series protection resistor or ESD diode. This lacks the protection provided to other signals on this connector.
10	10	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device. This is a second ground pin on the same connector.

D71 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	NRST	✅	Cathode connected to NRST signal for ESD protection. This is correct for protecting the reset pin exposed on external connectors.

D72 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	PA9_UTXD	✅	Cathode connected to PA9_UTXD signal for ESD protection. This is correct for protecting the UART transmit pin exposed on external connector J28.

D73 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	PA8_URXD	✅	Cathode connected to PA8_URXD signal for ESD protection. This is correct for protecting the UART receive pin exposed on external connector J28.

D1 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	ERASE	✅	Cathode connected to ERASE signal for ESD protection. This is correct for protecting the erase pin exposed on external connector J28.

RV1 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_20	✅	Connected to NetJ20_20 which connects to PB0_ETXCK via series resistor R153. This provides bidirectional ESD protection for the Ethernet transmit clock signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

RV2 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_19	✅	Connected to NetJ20_19 which connects to PB13_AD9 via series resistor R159. This provides bidirectional ESD protection for the ADC input signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

RV3 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_15	✅	Connected to NetJ20_15 which connects to PB2_ETX0 via series resistor R161. This provides bidirectional ESD protection for the Ethernet transmit data signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

RV4 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_16	✅	Connected to NetJ20_16 which connects to PB1_ETXEN via series resistor R160. This provides bidirectional ESD protection for the Ethernet transmit enable signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

U14 - 74AVC9112 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	Vcc	3.3VCC	✅	Vcc pin correctly connected to 3.3VCC power supply. The 3.3V supply voltage is within the device's specified operating range of 0.8V to 3.6V, and proper decoupling is provided by C67 (100nF).
2	A	NetC64_2	✅	Data input A correctly connected to microcontroller SPI clock output PA27/SPI0_SPCK through source termination resistor R82 (24Ω) and filter capacitor C64. The input accepts voltages up to 3.6V and features Schmitt trigger action for noise immunity.
3	nOE	GND	✅	Output enable nOE correctly tied to GND to permanently enable all outputs. This is appropriate for a clock distribution buffer that should always be active.
4	GND	GND	✅	Ground pin correctly connected to GND.
5	Y1	NetR3_2	✅	Output Y1 correctly connected through series termination resistor R3 (47Ω) to SCLK_TCBUS. The series resistor provides impedance matching and improves signal integrity for the thermocouple bus clock signal.
6	Y2	NetR4_2	✅	Output Y2 correctly connected through series termination resistor R4 (47Ω) to PA27_SCLK, which routes to external connector J20. This provides a buffered clock output to off-board devices with proper signal termination.
7	Y3	NetR13_2	✅	Output Y3 correctly connected through series termination resistor R13 (47Ω) to SCLK_M1BUS. The series resistor provides impedance matching and improves signal integrity for the motor 1 bus clock signal.
8	Y4	NetR32_2	✅	Output Y4 correctly connected through series termination resistor R32 (47Ω) to SCLK_M2BUS. The series resistor provides impedance matching and improves signal integrity for the motor 2 bus clock signal.
23	NC		✅	NC (no connect) pin correctly left unconnected.

R3 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_TCBUS	✅	Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution.
2	2	NetR3_2	✅	Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution.

R4 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA27_SCLK	✅	Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal.
2	2	NetR4_2	✅	Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal.

R13 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_M1BUS	✅	Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution.
2	2	NetR13_2	✅	Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution.

R32 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_M2BUS	✅	Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution.
2	2	NetR32_2	✅	Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution.

U16 - SN74LVC125A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	nOE1	CS_TCBUS	✅	Output enable for buffer 1, connected to CS_TCBUS which is derived from thermocouple chip selects through diode OR gate with 10k pullup (R95).
2	A1	MISO_TCBUS	✅	Input to buffer 1, connected to MISO_TCBUS from the thermocouple SPI bus.
3	Y1	NetR94_2	✅	Output of buffer 1, connected through R94 (47R) to PA25_MISO along with outputs from buffers 2 and 3 in a wire-OR configuration.
4	nOE2	CS_M1BUS	✅	Output enable for buffer 2, connected to CS_M1BUS which is derived from motor bus 1 chip selects through diode OR gate with 10k pullup (R100).
5	A2	MISO_M1BUS	✅	Input to buffer 2, connected to MISO_M1BUS from motor bus 1 and SPI flash.
6	Y2	NetR94_2	✅	Output of buffer 2, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 3 in a wire-OR configuration.
7	GND	GND	✅	Ground pin, correctly connected to GND net.
8	Y3	NetR94_2	✅	Output of buffer 3, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 2 in a wire-OR configuration.
9	A3	MISO_M2BUS	✅	Input to buffer 3, connected to MISO_M2BUS from motor bus 2.
10	nOE3	CS_M2BUS	✅	Output enable for buffer 3, connected to CS_M2BUS which is derived from motor bus 2 chip selects through diode OR gate with 10k pullup (R97).
11	Y4	unconnected-(NetU16_11)	✅	Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality.
12	A4	GND	✅	Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality.
13	nOE4	GND	✅	Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality.
14	Vcc	3.3VCC	✅	Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor.
15	PAD	GND	✅	Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance.
23	NC		✅	No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN.

U17 - SN74LVC125A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	nOE1	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
4	nOE2	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
10	nOE3	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
13	nOE4	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
2	A1	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
5	A2	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
9	A3	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
12	A4	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
3	Y1	NetR84_2	✅	Output of buffer 1, connected through R84 (47R) to MOSI_TCBUS to distribute the MOSI signal to the thermocouple bus.
6	Y2	NetR59_2	✅	Output of buffer 2, connected through R59 (47R) to MOSI_M1BUS to distribute the MOSI signal to motor bus 1.
7	GND	GND	✅	Ground pin, correctly connected to GND net.
8	Y3	NetR89_2	✅	Output of buffer 3, connected through R89 (47R) to MOSI_M2BUS to distribute the MOSI signal to motor bus 2.
11	Y4	NetR93_2	✅	Output of buffer 4, connected through R93 (47R) to PA26_MOSI to distribute the MOSI signal to an additional SPI device or connector.
14	Vcc	3.3VCC	✅	Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor.
15	PAD	GND	✅	Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance.
23	NC		✅	No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN.

R59 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M1BUS	✅	Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting.
2	2	NetR59_2	✅	Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting.

R84 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_TCBUS	✅	Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting.
2	2	NetR84_2	✅	Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting.

R89 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M2BUS	✅	Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting.
2	2	NetR89_2	✅	Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting.

R93 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA26_MOSI	✅	Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting.
2	2	NetR93_2	✅	Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting.

R94 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA25_MISO	✅	Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals.
2	2	NetR94_2	✅	Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals.

R77 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA26_MOSI_D	✅	Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side.
2	2	NetR77_2	✅	Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side.

R82 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC64_2	✅	Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination.
2	2	NetR82_2	✅	Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination.

R83 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA25_MISO	✅	Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side.
2	2	NetR83_2	✅	Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side.

D5 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS4	✅	Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing.

D30 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS2	✅	Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing.

D31 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS3	✅	Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing.

D40 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS6	✅	Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing.

D41 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS7	✅	Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing.

D60 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS5	✅	Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing.

D61 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS1	✅	Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing.

D62 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS5	✅	Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing.

D63 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS8	✅	Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing.

D70 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS1	✅	Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing.

D74 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS2	✅	Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing.

D75 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS3	✅	Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing.

D76 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS4	✅	Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing.

R95 - 10k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active.
2	2	CS_TCBUS	✅	Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active.

R97 - 10k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active.
2	2	CS_M2BUS	✅	Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active.

R100 - 10k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active.
2	2	CS_M1BUS	✅	Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active.

S1 - 1571610-2 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	RESET	✅	Pin 1 connects to the RESET net, which is the JTAG reset signal. When the button is pressed, it pulls RESET to ground. The RESET net lacks a pull-up resistor on the target board, but this is acceptable for JTAG applications where the external programmer typically provides the pull-up.
2	S	GND	✅	Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability.
3	3	GND	✅	Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability.
4	4	GND	✅	Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability.

S2 - KMR741NG ULC LFS ✅

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Pin Designator	Net	Correct?	Analysis
1	3.3VCC	✅	Pin 1 is correctly connected to 3.3VCC, providing the high voltage source for the ERASE signal when the button is pressed.
2	unconnected-(NetS2_2)	✅	Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability.
4	unconnected-(NetS2_4)	✅	Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability.
3	ERASE	✅	Pin 3 is correctly connected to the ERASE net. When the button is pressed, ERASE is pulled high to 3.3VCC through pin 1.

C40 - GRM155R71H103JA88D ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESET	✅	Pin 1 is correctly connected to the RESET net to provide filtering and debouncing for the JTAG reset signal.
2	2	3.3VIO	✅	Pin 2 is correctly connected to 3.3VIO. This provides filtering referenced to the I/O voltage rail, which is an acceptable design choice though less common than connecting to ground.

D24 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD24_A	✅	LED anode correctly connected to current limiting resistor R34. The LED is driven by microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0) through a 1kΩ resistor, providing approximately 1.1mA forward current.
C	C	GND	✅	LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high.

D25 - 5988140107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD25_A	✅	LED anode correctly connected to current limiting resistor R36. The LED is driven by microcontroller GPIO LED_Y (U11A pin 55, PC1) through a 1kΩ resistor, providing approximately 1.3mA forward current.
C	C	GND	✅	LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high.

R34 - RK73H1ETTP1001F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LED_R	✅	Resistor connected to microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0). This is the input side of the current limiting resistor for the red LED.
2	2	NetD24_A	✅	Resistor connected to red LED anode (D24 pin A). This is the output side of the current limiting resistor, providing approximately 1.1mA to the LED.

R36 - RK73H1ETTP1001F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LED_Y	✅	Resistor connected to microcontroller GPIO LED_Y (U11A pin 55, PC1). This is the input side of the current limiting resistor for the yellow LED.
2	2	NetD25_A	✅	Resistor connected to yellow LED anode (D25 pin A). This is the output side of the current limiting resistor, providing approximately 1.3mA to the LED.

D44 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD protection of the 3.3VCC power rail. This is the correct connection for an ESD protection diode.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail for ESD protection. This is the correct connection for protecting the 3.3V power supply from ESD events.

D45 - DF2S6.8FS,L3M ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD protection of the +5VCC power rail. This is the correct connection for an ESD protection diode.
K	K	+5VCC	✅	Cathode connected to +5VCC rail for ESD protection. This is the correct connection for protecting the 5V power supply from bidirectional ESD events.

R40 - 1k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Connected to 3.3VIO power rail to provide pull-up voltage for I2C SDA line.
2	2	PA17_SDA	✅	Connected to PA17_SDA (I2C data line) from microcontroller pin 9 and external header J20 pin 22.

R71 - 1k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Connected to 3.3VIO power rail to provide pull-up voltage for I2C SCL line.
2	2	PA18_SCL	✅	Connected to PA18_SCL (I2C clock line) from microcontroller pin 70 and external header J20 pin 21.

Q12A - NCV8402AD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Source 1 is correctly connected to GND for low-side switching operation.
2	G	NetQ12_2	✅	Gate 1 is correctly driven through a 100Ω series resistor from buffer U2D output, controlling Fan 1 switching.
7	D	NetC154_2	✅	Drain 1 is correctly connected to switch the Fan 1 load and LED1 indicator.

Q12B - NCV8402AD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
3	S	GND	✅	Source 2 is correctly connected to GND for low-side switching operation.
4	G	NetQ12_4	✅	Gate 2 is correctly driven through a 100Ω series resistor from buffer U2C output, controlling Fan 2 switching.
5	D	NetC153_2	✅	Drain 2 is correctly connected to switch the Fan 2 load and LED2 indicator.

Q13A - NCV8402AD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Source 1 is correctly connected to GND for low-side switching operation.
2	G	NetQ13_2	✅	Gate 1 is correctly driven through a 100Ω series resistor from buffer U2B output, controlling Fan 3 switching.
7	D	NetC211_2	✅	Drain 1 is correctly connected to switch the Fan 3 load and LED3 indicator.

Q13B - NCV8402AD ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
5	D	VFAN	❌	Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on. Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet NCV8402ADDR2G, page 1) Pin 5 is connected to the VFAN net (from schematic) VFAN is the positive power supply rail for the fans (from schematic) In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning) The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic) Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic) Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic) Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic) J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic) J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic) With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning) LED4 cathode is connected to VFAN (from schematic) LED4 anode connects through R14 to VFAN (from schematic) With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning) C209 has both pins connected to VFAN, providing no filtering function (from schematic) When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet NCV8402ADDR2G, page 3) This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet NCV8402ADDR2G, page 3) The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet NCV8402ADDR2G, page 3) This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning) The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet NCV8402ADDR2G, page 1) Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning) This connection error makes the Fan 4 control circuit completely non-functional (reasoning)
3	S	GND	✅	Source 2 is correctly connected to GND for low-side switching operation.
4	G	NetQ13_4	✅	Gate 2 is correctly driven through a 100Ω series resistor from buffer U2A output, controlling Fan 4 switching.

U2A - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1OE	GND	✅	Output enable (1OE) is tied directly to GND, permanently enabling gate 1. This is functionally correct for this always-on fan control application, though it differs from the datasheet recommendation to use a pullup resistor to VCC for high-impedance state during power transitions.
2	1A	Fan4	✅	Input (1A) is connected to Fan4 control signal with a 10K pulldown resistor (R101) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
3	1Y	NetR181_1	✅	Output (1Y) drives a 100R gate resistor (R181) which controls the gate of MOSFET driver Q13B. This is standard practice for MOSFET gate drive circuits to limit inrush current and reduce ringing.

U2B - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
4	2OE	GND	✅	Output enable (2OE) is tied directly to GND, permanently enabling gate 2. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers.
5	2A	Fan3	✅	Input (2A) is connected to Fan3 control signal with a 10K pulldown resistor (R171) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
6	2Y	NetR180_1	✅	Output (2Y) drives a 100R gate resistor (R180) which controls the gate of MOSFET driver Q13A. This is standard practice for MOSFET gate drive circuits.

U2C - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
8	3Y	NetR99_1	✅	Output (3Y) drives a 100R gate resistor (R99) which controls the gate of MOSFET driver Q12B. This is standard practice for MOSFET gate drive circuits.
9	3A	FAN2	✅	Input (3A) is connected to FAN2 control signal with a 10K pulldown resistor (R182) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
10	3OE	GND	✅	Output enable (3OE) is tied directly to GND, permanently enabling gate 3. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers.

U2D - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
11	4Y	NetR98_1	✅	Output (4Y) drives a 100R gate resistor (R98) which controls the gate of MOSFET driver Q12A. This is standard practice for MOSFET gate drive circuits.
12	4A	FAN1	✅	Input (4A) is connected to FAN1 control signal with a 10K pulldown resistor (R183) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
13	4OE	GND	✅	Output enable (4OE) is tied directly to GND, permanently enabling gate 4. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers.

U2E - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
7	GND	GND	✅	Ground pin is correctly connected to the GND net.
14	VCC	+5VCC	✅	Power supply pin is correctly connected to +5VCC with a 100nF bypass capacitor (C92) nearby, meeting datasheet recommendations for decoupling.
15	PAD	SNTP1	✅	Exposed thermal pad (PAD) is connected to net SNTP1. The text label 'SNTP1' near the component suggests this connection is intentional. For optimal thermal performance, this pad should be connected to ground. Verify that SNTP1 is properly connected to ground elsewhere in the design for adequate thermal dissipation.

D50 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD50_A	✅	Anode connected to NetD50_A, forming the upper clamp for the TACH_1 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D51 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD51_A	✅	Anode connected to NetD51_A, forming the upper clamp for the TACH_2 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D52 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct.
K	K	NetD50_A	✅	Cathode connected to NetD50_A, completing the lower clamping path for TACH_1 signal protection. This connection is correct.

D53 - BAT54WX ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	unconnected-(NetD53_A)	❌	Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels. Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected (from schematic) D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp (reasoning) All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND (from schematic) The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) (reasoning) Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients (reasoning) The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits (reasoning) D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 (reasoning)
K	K	NetD51_A	✅	Cathode connected to NetD51_A, which is the correct connection for a lower clamp diode. However, the diode is non-functional because pin A is unconnected.

D54 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD54_A	✅	Anode connected to NetD54_A, forming the upper clamp for the TACH_3 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D55 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD55_A	✅	Anode connected to NetD55_A, forming the upper clamp for the TACH_4 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D56 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct.
K	K	NetD54_A	✅	Cathode connected to NetD54_A, completing the lower clamping path for TACH_3 signal protection. This connection is correct.

D57 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct.
K	K	NetD55_A	✅	Cathode connected to NetD55_A, completing the lower clamping path for TACH_4 signal protection. This connection is correct.

LED1 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED1_A	✅	Anode is correctly connected through current limiting resistor R96 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit.
C	C	NetC154_2	✅	Cathode is correctly connected to the drain of low-side MOSFET driver Q12A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated.

LED2 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED2_A	✅	Anode is correctly connected through current limiting resistor R12 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit.
C	C	NetC153_2	✅	Cathode is correctly connected to the drain of low-side MOSFET driver Q12B (pin 5), which switches the LED on/off by pulling the cathode to ground when activated.

LED3 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED3_A	✅	Anode is correctly connected through current limiting resistor R15 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit.
C	C	NetC211_2	✅	Cathode is correctly connected to the drain of low-side MOSFET driver Q13A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated.

LED4 - 5988110107F ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
C	C	VFAN	❌	Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3. Pin C (Cathode) is connected directly to net VFAN (from schematic) Pin C is the Cathode connection per the datasheet (from datasheet 5988110107F) The anode is connected to VFAN through R14, making both terminals at the same potential (from schematic) For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop (from datasheet 5988110107F) With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow (reasoning) LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) (from schematic) Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern (from schematic) J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets (from schematic) The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated (reasoning) This error prevents LED4 from functioning as a fan status indicator (reasoning)
A	A	NetLED4_A	✅	Anode is connected through current limiting resistor R14 (4.7K) to VFAN power rail. While this connection topology is correct, the LED cannot function because the cathode is also connected to VFAN, creating zero voltage difference across the LED.

J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC154_2	✅	Pin 1 is correctly connected to the switched ground output (NetC154_2) for Fan 1, implementing low-side PWM control where the MOSFET switches the ground return path.
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan.
3	S	NetJ29_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ29_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor.

J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC153_2	✅	Pin 1 is correctly connected to the switched ground output (NetC153_2) for Fan 2, implementing low-side PWM control where the MOSFET switches the ground return path.
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan.
3	S	NetJ22_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ22_3) with proper signal conditioning including pull-up resistor, series resistors, upper clamp diode, and filtering capacitor. Note that the lower clamp diode D53 has an unconnected anode, which reduces protection against negative transients but should not prevent normal operation.

J31 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC211_2	✅	Pin 1 is correctly connected to the switched ground output (NetC211_2) for Fan 3, implementing low-side PWM control where the MOSFET switches the ground return path.
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan.
3	S	NetJ31_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ31_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor.

J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	VFAN	❌	Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor. Pin 1 is connected to net VFAN (from schematic) Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net (from schematic) Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 (from schematic) For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) (from schematic) Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 (from schematic) Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively (from schematic) LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 (from schematic) Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output (from schematic) The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference (from schematic) In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path (reasoning) Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate (reasoning) With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation (reasoning) Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits (reasoning)
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing the power supply voltage. However, the fan cannot operate due to the error on pin 1 which prevents the ground return path.
3	S	NetJ30_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ30_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. The tachometer circuit is correctly implemented, though the fan may not operate due to the error on pin 1.

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_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 144 component(s) to review, and found 6 potential issue(s) in 8 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. > [!WARNING] > At least one netlist for this review was generated from a PCB layout file. If > the PCB is out of sync with the schematic, the analysis may be inaccurate. > Please ensure your PCB is up to date before relying on these results. <details> <summary>Component Details</summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary>U1 - TPS54531 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftps54531) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TPS54531DDAR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | VIN | VPWR | ❌ | <details><summary>VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="50.79,50.95,58.29,58.45" aspect-ratio="1.29" } <ul><li>Pin 2 (VIN) is connected to net VPWR (from schematic)</li><li>VPWR is the main power input rail derived from VPWR_IN through fuse F2 (from schematic)</li><li>This pin is the 3.5- to 28-V input supply voltage (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=3">TPS54531DDAR</a>, page 3)</li><li>Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14">TPS54531DDAR</a>, page 14)</li><li>Input decoupling capacitor of 10μF is recommended per datasheet (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=1">TPS54531DDAR</a>, page 1)</li><li>C71 is a 10nF capacitor on VPWR (from schematic)</li><li>C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total (from schematic)</li><li>Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF (reasoning)</li><li>Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response (reasoning)</li><li>A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) (reasoning)</li></ul></details> | | 1 | BOOT | NetC1_1 | ✅ | BOOT pin correctly connected to bootstrap capacitor C1 (100nF) between BOOT and PH pins as required by datasheet. | | 3 | EN | NetR2_2 | ✅ | EN pin correctly configured with UVLO resistor divider (R11=10k, R2=1.4k) and connected to protection circuits (U19 nALERT, U21 and U6 comparator outputs) for enable/disable control. | | 4 | SS | NetC171_2 | ✅ | SS pin correctly connected to soft-start capacitor C171 (10nF) to ground. | | 5 | VSNS | NetC3_1 | ✅ | VSENSE pin correctly connected to feedback resistor divider (R1=10.2k, R5=1.96k) that sets output voltage to approximately 5V. | | 6 | COMP | NetC150_2 | ✅ | COMP pin correctly connected to compensation network consisting of R10 (37.4k), C150 (2.2nF), and C151 (22pF) for loop stability. | | 7 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 8 | PH | NetC1_2 | ✅ | PH pin correctly connected to switching node with inductor L1, catch diode D2, and bootstrap capacitor C1. | | 9 | PAD | GND | ✅ | PowerPAD correctly connected to ground as required by datasheet. | </details> <details> <summary>L1 - 4.7uH 10A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.bourns.com/docs/Product-Datasheets/SRP1038A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SRP1038A-4R7M) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC1_2 | ✅ | Inductor input correctly connected to PH switching node of U1. | | 2 | 2 | NetC3_2 | ✅ | Inductor output correctly connected to converter output (NetC3_2) before current sense resistor R148. | </details> <details> <summary>D2 - SK54B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/SK52B-L_SK520B-L%28SMB%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SK54B-LTP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode correctly connected to ground for proper catch diode operation. | | K | CATHODE | NetC1_2 | ✅ | Cathode correctly connected to PH switching node for freewheeling current path. | </details> <details> <summary>R148 - 0.01R 1% 0805 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.susumu.co.jp/common/pdf/n_catalog_partition09_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/KRL1220E-M-R010-F-T5) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC3_2 | ✅ | Current sense resistor input correctly connected to buck converter output (NetC3_2). | | 2 | 2 | +5VCC | ✅ | Current sense resistor output correctly connected to +5VCC rail. However, the calculated current limit threshold is approximately 6A, which does not match the schematic note stating '~4A' current limiting. The discrepancy may be intentional to provide margin above the 5A rated output, or the note may be outdated. | </details> <details> <summary>U8 - MIC5353-3.3YMT-TR ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MIC5353-3.3YMT-TR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | EN | +5VCC | ✅ | EN pin is connected to +5VCC, configuring the regulator for always-on operation whenever input power is present. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground plane. | | 3 | VIN | +5VCC | ✅ | VIN pin is connected to +5VCC with adequate input voltage headroom and proper input decoupling. | | 4 | VOUT | 3.3VCC | ✅ | VOUT pin provides the regulated 3.3V output with adequate output capacitance for stability. | | 5 | ADJ | unconnected-(NetU8_5) | ✅ | ADJ pin is left unconnected, which is appropriate for the fixed 3.3V output version of the MIC5353. | | 6 | BYP | NetC26_1 | ✅ | BYP pin has a 100nF bypass capacitor C26 connected to ground for internal reference and error amplifier stability. | | 7 | PAD | GND | ✅ | PAD (thermal pad) is correctly connected to ground for thermal management and heat dissipation. | </details> <details> <summary>U20 - 78L05 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/L78L05ABUTR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | OUT | 5V0_AUX | ✅ | Output pin correctly connected to 5V0_AUX net, providing regulated 5V to power the current limiting comparator U19 and associated reference circuitry. Output is properly decoupled with capacitors C200 and C201. | | 2 | GND | GND | ✅ | Ground pin correctly connected to the circuit ground reference. | | 3 | IN | VPWR | ✅ | Input pin correctly connected to VPWR rail (12-24VDC), which is within the 78L05's operating range of 7V minimum to 30V maximum. Input is properly protected with TVS diode and adequately decoupled. | </details> <details> <summary>U19 - INA381_ALT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/INA381A2IDSGR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN+ | NetC3_2 | ✅ | IN+ is correctly connected to NetC3_2, the high side of current sense resistor R148, enabling high-side current sensing of the +5VCC rail. | | 2 | Vs | 5V0_AUX | ✅ | Vs is correctly powered from 5V0_AUX, an independent auxiliary 5V supply from the 78L05 LDO (U20), with proper decoupling capacitors C200 and C201. | | 3 | nALERT | NetR2_2 | ✅ | nALERT is correctly connected to NetR2_2, which drives the EN pin of the TPS54531 buck converter (U1 pin 3), implementing overcurrent protection by disabling the +5V regulator when current limit is exceeded. | | 4 | RESET | NetR102_1 | ✅ | RESET is correctly pulled high to 5V0_AUX through R102 (1k), configuring the INA381 in latching mode as indicated by schematic notes. | | 5 | CMPREF | NetR115_1 | ✅ | CMPREF is connected to a voltage divider (R115=15k, R119=4.7k) that sets the comparator reference threshold to approximately 1.19V. The design intent is clear, but without the INA381A2IDSGR datasheet to confirm the internal gain, the actual current limit threshold cannot be definitively verified against the stated ~4A specification. | | 6 | CMPIN | NetU19_6 | ✅ | CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF. | | 7 | VOUT | NetU19_6 | ✅ | CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF. | | 8 | IN- | +5VCC | ✅ | IN- is correctly connected to +5VCC, the low side of current sense resistor R148, enabling differential measurement of the voltage drop across the sense resistor. | | 9 | GND | GND | ✅ | GND is correctly connected to the ground plane, providing the ground reference for the device. | </details> <details> <summary>U21 - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP331A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AP331AWG-7) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR157_1 | ✅ | IN- (inverting input) is correctly connected to a reference voltage divider creating approximately 2.17V from 5V0_AUX through R157 (130k) and R158 (100k), providing the threshold for the under-voltage lockout circuit. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the comparator. | | 3 | IN+ | NetR154_2 | ✅ | IN+ (non-inverting input) is correctly connected to monitor the VMOTA voltage through a voltage divider (R154=24k, R155=10k) with positive feedback through R156 (1M) for hysteresis, creating an under-voltage lockout threshold of approximately 7.38V. | | 4 | OUT | NetR2_2 | ✅ | OUT (open collector output) is correctly configured with pull-up resistor R11 (10k to VPWR) and pull-down resistor R2 (1.4k to GND), forming a wired-OR with other protection circuits (U6, U19) to control the enable pin of buck regulator U1. Note that the voltage divider creates a high-level voltage of approximately 1.47V at VPWR=12V and 2.95V at VPWR=24V, which provides limited margin at the lower end of the VPWR range. | | 5 | VCC | VPWR | ✅ | VCC pin is correctly connected to VPWR, which provides power to the comparator within the specified 12-24VDC range and meets the datasheet's +2 to +36V single supply requirement. | </details> <details> <summary>U6 - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP331A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AP331AWG-7) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR57_1 | ✅ | IN- (inverting input) is connected to a reference voltage divider from 5V0_AUX through R57 (130k) and R58 (100k) to GND, setting a reference threshold of approximately 2.17V for under-voltage detection. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the comparator. | | 3 | IN+ | NetR26_2 | ✅ | IN+ (non-inverting input) monitors VMOTE voltage through a divider formed by R26 (24k) and R56 (10k), with positive feedback hysteresis provided by R28 (1M) from the output to prevent oscillation. | | 4 | OUT | NetR2_2 | ✅ | OUT (open-collector output) is wire-OR'd with other fault detectors on net NetR2_2, which controls the enable pin of buck regulator U1. The output is pulled up through R11 (10k) to VPWR and has R2 (1.4k) to GND forming a voltage divider. | | 5 | VCC | VPWR | ✅ | VCC pin is correctly connected to VPWR, providing power supply to the comparator within its specified operating range of 2-36V. | </details> <details> <summary>F1 - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.keyelco.com/userAssets/file/K75p47.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-20) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED_IN | ✅ | Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity. | | 2 | 2 | VBED | ✅ | Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity. | </details> <details> <summary>F2 - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-2) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR_IN | ✅ | Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity. | | 2 | 2 | VPWR | ✅ | Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity. | </details> <details> <summary>D43 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection. | | K | K | VMOTA | ✅ | TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection. | </details> <details> <summary>D22 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection. | | K | K | VPWR | ✅ | TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection. | </details> <details> <summary>D78 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection. | | K | K | VBED | ✅ | TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection. | </details> <details> <summary>D21 - SMAJ24A ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | VMOTE | ❌ | <details><summary>TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="2.64,54.95,10.14,62.45" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOTE (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic)</li><li>SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The color band on the device denotes the cathode terminal (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic)</li><li>With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning)</li><li>The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning)</li><li>This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning)</li><li>The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)</li></ul></details> | | K | K | GND | ❌ | <details><summary>TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="2.64,56.13,10.14,63.63" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOTE (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic)</li><li>SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The color band on the device denotes the cathode terminal (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic)</li><li>With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning)</li><li>The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning)</li><li>This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning)</li><li>The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)</li></ul></details> | </details> <details> <summary>J3 - 10 Pos barrier ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/4DB-P108-10) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOTE | ✅ | Connected to VMOTE net, providing motor power input for motors 5-8 with proper protection and monitoring circuitry. | | 2 | 2 | GND | ✅ | Connected to GND net, providing ground reference for VMOTE power input. | | 3 | 3 | VMOTA | ✅ | Connected to VMOTA net, providing motor power input for motors 1-4 with proper protection and monitoring circuitry. | | 4 | 4 | GND | ✅ | Connected to GND net, providing ground reference for VMOTA power input. | | 5 | 5 | VPWR_IN | ✅ | Connected to VPWR_IN net, providing input power through fuse F2 to VPWR rail for fans, expansion, heaters, and logic circuits. | | 6 | 6 | GND | ✅ | Connected to GND net, providing ground reference for VPWR_IN power input. | | 7 | 7 | VBED_IN | ✅ | Connected to VBED_IN net, providing input power through fuse F1 to heated bed (VBED) rail. | | 8 | 8 | GND | ✅ | Connected to GND net, providing ground reference for VBED_IN power input. | | 9 | 9 | VBED | ✅ | Connected to VBED net, providing heated bed power output after fuse with proper protection and filtering. | | 10 | 10 | HTBD-OUT | ✅ | Connected to HTBD-OUT net, which has no other connections on this schematic page. This is likely intentional for connection on another schematic page or for external wiring. | </details> <details> <summary>P1 - Header 4X2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-08G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads. | | 3 | 3 | VFAN | ✅ | These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads. | | 2 | 2 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 4 | 4 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 6 | 6 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 8 | 8 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 5 | 5 | VPWR | ✅ | These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution. | | 7 | 7 | VPWR | ✅ | These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution. | </details> <details> <summary>D23 - 5988170107F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988170107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD23_A | ✅ | LED anode is correctly connected to 3.3VCC through current-limiting resistor R33 (1kΩ). The resulting current is approximately 1.3mA, which is low but acceptable for modern high-efficiency indicator LEDs. | | C | C | GND | ✅ | LED cathode is correctly connected to GND, providing the proper return path for LED current and completing the indicator circuit. | </details> <details> <summary>C210 - UWT1V101MCL1GS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.nichicon.co.jp/english/series_items/catalog_pdf/e-uwt.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/UWT1V101MCL1GS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED | ✅ | Positive terminal correctly connected to VBED heated bed power rail for bulk filtering and energy storage. | | 2 | 2 | GND | ✅ | Negative terminal correctly connected to GND, providing proper return path for the bulk capacitor. | </details> <details> <summary>R103 - 0R 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://bourns.com/docs/product-datasheets/cr.pdf?sfvrsn=574d41f6_14) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CR0603-J_-000ELF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | 0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail. | | 2 | 2 | VFAN | ✅ | 0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail. | </details> <details> <summary>J8 - USB-B ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/61729-0010BLF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS | NetC43_2 | ✅ | VBUS pin correctly connected to ESD protection and power filtering network before reaching the USB isolator. | | 2 | DM | DM | ✅ | DM (D-) pin correctly connected to ESD protection device D27 pin 1 (I/O1) for the USB D- data line. | | 3 | DP | DP | ✅ | DP (D+) pin correctly connected to ESD protection device D27 pin 3 (I/O2) for the USB D+ data line. | | 4 | GND | USB_GND | ✅ | GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier. | | 5 | SHLD | USB_GND | ✅ | GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier. | | 6 | SHLD | USB_GND | ✅ | GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier. | </details> <details> <summary>D27 - PRTR5V0U2F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2F_PRTR5V0U2K.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/PRTR5V0U2F,115) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | DM | ✅ | I/O1 pin correctly connected to DM (D-) from USB connector J8 pin 2. | | 2 | | USB_GND | ✅ | GND pin correctly connected to USB_GND, providing ground reference for the ESD protection device. | | 3 | | DP | ✅ | I/O2 pin correctly connected to DP (D+) from USB connector J8 pin 3. | | 4 | | NetD27_4 | ✅ | I/O2 pin correctly connected through common mode choke L5 to the D+ signal path (UD_P). | | 5 | | NetC43_2 | ✅ | VCC pin correctly connected to VBUS (NetC43_2) for rail-to-rail ESD protection. | | 6 | | NetD27_6 | ✅ | I/O1 pin correctly connected through common mode choke L5 to the D- signal path (UD_N). | </details> <details> <summary>L5 - DLW21HN900SQ2L ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/commonModeChokeCoilCommonModeNoiseFilter/EFLC0005_PDF_COMMONMODECHOKECOILCOMMONMODENOISEFILTER?lastModifiedDatetime=20250707191631) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DLW21HN900SQ2L) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | NetL5_1 | ✅ | Common mode choke terminal correctly connected through R46 (24Ω) to UD_P, completing the D+ signal path. | | 2 | | NetD27_4 | ✅ | Common mode choke terminal correctly connected to D27 pin 4 (I/O2), receiving the D+ signal from ESD protection. | | 3 | | NetD27_6 | ✅ | Common mode choke terminal correctly connected to D27 pin 6 (I/O1), receiving the D- signal from ESD protection. | | 4 | | NetL5_4 | ✅ | Common mode choke terminal correctly connected through R43 (24Ω) to UD_N, completing the D- signal path. | </details> <details> <summary>D26 - RSB39VTE-17 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RSB39VTE-17) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier. | | C | C | USB_GND | ✅ | TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier. | </details> <details> <summary>U9 - ADuM4160 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM3160.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ADUM3160BRWZ-RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS1 | VUSB | ✅ | VBUS1 is correctly connected to VUSB, which provides USB bus voltage (5V) to power the upstream side of the isolator with proper bypass capacitors. | | 2 | GND1 | USB_GND | ✅ | GND1 is correctly connected to USB_GND, providing the isolated ground reference for the upstream side of the isolator. | | 3 | VDD1 | VDD1 | ✅ | VDD1 is correctly connected to the internal 3.3V regulator output with proper bypass capacitor and provides pull-up voltage for PDEN and SPU configuration pins. | | 4 | PDEN | VDD1 | ✅ | PDEN is correctly tied to VDD1 for standard operation with pull-down resistors enabled. | | 5 | SPU | VDD1 | ✅ | SPU is correctly tied to VDD1 to select full speed operation on the upstream buffer, matching the SPD pin configuration. | | 6 | UD- 1 | UD_N | ✅ | UD- (Upstream D-) is correctly connected through 24Ω series termination resistor R43 to the USB connector via common mode choke L5. | | 7 | UD+ 1 | UD_P | ✅ | UD+ (Upstream D+) is correctly connected through 24Ω series termination resistor R46 to the USB connector via common mode choke L5. | | 8 | GND1 | USB_GND | ✅ | GND1 is correctly connected to USB_GND, matching pin 2 as required by the datasheet. | | 9 | GND2 | GND | ✅ | GND2 is correctly connected to the main system ground (GND), providing ground reference for the downstream side of the isolator. | | 10 | UD+ 2 | UI_P | ✅ | DD+ (Downstream D+) is correctly connected through 24Ω series termination resistor R47 to the microcontroller USB D+ pin. | | 11 | UD- 2 | UI_N | ✅ | DD- (Downstream D-) is correctly connected through 24Ω series termination resistor R45 to the microcontroller USB D- pin. | | 12 | PIN | 3.3VCC | ✅ | PIN is correctly tied to 3.3VCC to enable the upstream pull-up resistor for immediate USB enumeration on power-up. | | 13 | SPD | 3.3VCC | ✅ | SPD is correctly tied to 3.3VCC to select full speed operation on the downstream buffer, matching the SPU pin configuration. | | 14 | VDD2 | +3.3VCC | ✅ | VDD2 is correctly connected to +3.3VCC along with VBUS2 for 3.3V operation with proper bypass capacitors present. | | 15 | GND2 | GND | ✅ | GND2 is correctly connected to the main system ground (GND), matching pin 9 as required by the datasheet. | | 16 | VBUS2 | +3.3VCC | ✅ | VBUS2 is correctly connected to +3.3VCC along with VDD2 for 3.3V operation on the downstream side. | </details> <details> <summary>R43 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_N | ✅ | R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector. | | 2 | 2 | NetL5_4 | ✅ | R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector. | </details> <details> <summary>R46 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_P | ✅ | R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector. | | 2 | 2 | NetL5_1 | ✅ | R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector. | </details> <details> <summary>R45 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_N | ✅ | R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator. | | 2 | 2 | UI_N | ✅ | R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator. | </details> <details> <summary>R47 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_P | ✅ | R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator. | | 2 | 2 | UI_P | ✅ | R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator. | </details> <details> <summary>U11B - ATML-ATSAM3X-LQFP-144 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 35 | XOUT | NetC41_2 | ✅ | XOUT pin correctly connected to 12MHz crystal X1 pin 3 through load capacitor C41 (3pF to ground). Standard crystal oscillator output configuration. | | 36 | XIN | NetC42_2 | ✅ | XIN pin correctly connected to 12MHz crystal X1 pin 1 through load capacitor C42 (3pF to ground). Standard crystal oscillator input configuration. | | 37 | DHSDP | UMCU_P | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 38 | DHSDM | UMCU_N | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 42 | DFSDP | NetR48_1 | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 43 | DFSDM | NetR42_1 | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 39 | VBUS | VBUS_UC | ✅ | VBUS pin correctly connected to VBUS_UC net with optoisolator-based detection circuit that senses USB power presence across the isolation barrier. | | 40 | VBG | NetC49_1 | ✅ | VBG pin connected to 10pF capacitor C49 and 6.8K resistor R49 to ground. The 10pF capacitor provides filtering for the bandgap reference, but the 6.8K resistor to ground is unusual and should be verified against the ATSAM3X8EA datasheet. | | 46 | JTAGSEL | GND | ✅ | JTAGSEL pin correctly tied to GND to select debug interface mode. | | 47 | NRSTB | RESET | ✅ | NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection. | | 69 | NRST | NetC169_1 | ✅ | NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection. | | 48 | XIN32 | XIN32 | ✅ | XIN32 pin connected to net XIN32 for 32.768 kHz RTC crystal input. The crystal connection is not visible on this schematic page. | | 49 | XOUT32 | XOUT32 | ✅ | XOUT32 pin connected to net XOUT32 for 32.768 kHz RTC crystal output. The crystal connection is not visible on this schematic page. | | 50 | SHDN | SHDN | ✅ | SHDN pin connected to net SHDN as a shutdown output signal. | | 51 | TST | GND | ✅ | TST pin correctly tied to GND as test pins are typically grounded when not in use. | | 53 | FWUP | NetR51_1 | ✅ | FWUP pin correctly pulled up to +3.3VCC through 100K resistor R51 to disable firmware update mode by default. | | 75 | ADVREF | VDDANA | ✅ | ADVREF pin correctly connected to VDDANA with appropriate bypass capacitors C76 (100nF) and C77 (10nF) for analog reference voltage filtering. | </details> <details> <summary>X1 - 405C35B12M00000 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/405C35B12M00000) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | C1 | NetC42_2 | ✅ | Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified. | | 3 | C2 | NetC41_2 | ✅ | Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified. | | 2 | GND | GND | ✅ | Crystal ground pins correctly connected to GND. | | 4 | GND | GND | ✅ | Crystal ground pins correctly connected to GND. | </details> <details> <summary>R48 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR48_1 | ✅ | 24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | | 2 | 2 | UMCU_P | ✅ | 24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | </details> <details> <summary>R42 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR42_1 | ✅ | 24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | | 2 | 2 | UMCU_N | ✅ | 24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | </details> <details> <summary>U18 - OPTO SO-4 OPNDRN OUT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TLP293%28TPL,E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A | NetR152_2 | ✅ | Anode of optoisolator LED, connected to VUSB through current limiting resistor R152 (1kΩ). This provides the input signal indicating USB power presence on the isolated side. | | 2 | K | USB_GND | ✅ | Cathode of optoisolator LED, correctly connected to USB_GND (isolated ground) to complete the LED circuit on the isolated side. | | 3 | E | GND | ✅ | Emitter of optoisolator output phototransistor, correctly connected to system GND on the non-isolated side to establish the reference for the output stage. | | 4 | C | NetQ8_1 | ✅ | Collector of optoisolator output phototransistor, connected to Q8 base through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. This drives the inverter stage in open-collector configuration. | </details> <details> <summary>Q8 - MMBT3904_SOT523 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MMBT3904T-7-F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B | NetQ8_1 | ✅ | Base of NPN transistor, driven by optoisolator U18 collector through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. Base is low when USB power present, high when absent. | | 2 | E | GND | ✅ | Emitter of NPN transistor, correctly connected to GND for common-emitter switching configuration. | | 3 | C | VBUS_UC | ✅ | Collector of NPN transistor, connected to VBUS_UC (microcontroller VBUS sense pin) with pull-up resistor R150 (6.8kΩ) to +5VCC. Provides high signal when USB power present, low when absent. | </details> <details> <summary>JP1 - SJ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged. | | 2 | 2 | VUSB | ✅ | Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged. | </details> <details> <summary>JP2 - SJ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation. | | 2 | 2 | USB_GND | ✅ | Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation. | </details> <details> <summary>FB29 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | Connected to VUSB (isolated USB power rail). This is the filtered/clean side of the ferrite bead, providing filtered power to the ADuM4160 USB isolator. | | 2 | 2 | NetC43_2 | ✅ | Connected to NetC43_2 (USB connector VBUS). This is the unfiltered/noisy side of the ferrite bead, providing EMI filtering on the incoming USB power line. | </details> <details> <summary>U11C - ATML-ATSAM3X-LQFP-144 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 45 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 61 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 104 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 124 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 11 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 62 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 105 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 125 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 12 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 33 | GNDPLL | GND | ✅ | Ground pins correctly connected to system ground. | | 44 | GNDUTMI | GND | ✅ | Ground pins correctly connected to system ground. | | 54 | GNDBU | GND | ✅ | Ground pins correctly connected to system ground. | | 58 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 74 | GNDANA | GND | ✅ | Ground pins correctly connected to system ground. | | 106 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 126 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 34 | VDDPLL | VDDPLL | ✅ | VDDPLL is incorrectly connected to VDDOUT (1.2V) through FB26. VDDPLL requires 1.62V to 3.6V and should be connected to 3.3VCC or 3.3VIO instead. This will prevent the PLL from functioning correctly. | | 41 | VDDUTMI | VDDUTMI | ✅ | VDDUTMI correctly connected to 3.3VCC through ferrite bead FB30 for USB transceiver power supply. | | 52 | VDDBU | 3.3VCC | ✅ | VDDBU correctly connected to 3.3VCC for backup power supply. | | 56 | VDDOUT | VDDOUT | ✅ | VDDOUT correctly connected to the VDDOUT net, serving as the internal voltage regulator output. | | 57 | VDDIN | 3.3VCC | ✅ | VDDIN correctly connected to 3.3VCC as the input to the internal voltage regulator. | | 73 | VDDANA | VDDANA | ✅ | VDDANA correctly connected to 3.3VCC through ferrite bead FB27 for analog power supply. | </details> <details> <summary>U11A - ATML-ATSAM3X-LQFP-144 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 29 | PB29/TDI | TDO/SWO | ❌ | <details><summary>JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.08,54.04,35.58" aspect-ratio="1.55" } <ul><li>Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)</li><li>Pin 30 (PB30/TDO) is connected to net TDI (from schematic)</li><li>Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)</li><li>Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)</li><li>The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)</li><li>The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)</li><li>The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)</li><li>This swap will prevent JTAG debugging from functioning correctly (reasoning)</li><li>In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)</li><li>The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)</li></ul></details> | | 30 | PB30/TDO/TRACESWO | TDI | ❌ | <details><summary>JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.99,54.04,36.49" aspect-ratio="1.55" } <ul><li>Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)</li><li>Pin 30 (PB30/TDO) is connected to net TDI (from schematic)</li><li>Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)</li><li>Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)</li><li>The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)</li><li>The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)</li><li>The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)</li><li>This swap will prevent JTAG debugging from functioning correctly (reasoning)</li><li>In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)</li><li>The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)</li></ul></details> | | 1 | PB26/CTS0/TCLK0/WKUP15 | STEP6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 2 | PA9/UTXD/PWMH3 | PA9_UTXD | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 3 | PA10/RXD0/DATRG/WKUP5 | DIAG7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 4 | PA11/TXD0/ADTRG/WKUP6 | DIAG8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 5 | PA12/RXD1/PWML1/WKUP7 | PA12_RXD1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 6 | PA13/TXD1/PWMH2 | PA13_TXD1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 7 | PA14/RTS1/TK | PA14_RTS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 8 | PA15/CTS1/TF/WKUP8 | PA15_CTS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 9 | PA17/TWD0/SPCK0 | PA17_SDA | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 13 | PD0/A10/MCDA4 | M_nCS7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 14 | PD1/A11/MCDA5 | DIR8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 15 | PD2/A12/MCDA6 | M_nCS8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 16 | PD3/A13/MCDA7 | STEP8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 17 | PD4/A14/TXD3 | MIN_ES1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 18 | PD5/A15/RXD3 | MAX_ES2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 19 | PD6/A16/BA0/PWMFI2 | MIN_ES2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 20 | PD7/A17/BA1/TIOA8 | TACH_3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 21 | PD8/A21/NANDALE/TIOB8 | TACH_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 22 | PD9/A22/NANDCLE/TCLK8 | MAX_ES3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 23 | PA0/CANTX0/PWML3 | PA0_CANTX0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 24 | PA1/CANRX0/PCK0/WKUP0 | PA1_CANRX0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 25 | PA5/TIOA2/PWMFI0/WKUP2 | PA5_PWM | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 26 | PA7/TCLK2/NCS1/WKUP3 | MIN_ES3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 27 | PA8/URXD/PWMH0/WKUP4 | PA8_URXD | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 28 | PB28/TCK/SWCLK | TCK/SWDCLK | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 31 | PB31/TMS/SWDIO | TMS/SWDIO | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 32 | PD10/NWR1/NBS1 | MAX_ES1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 55 | PC1 | LED_Y | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 59 | PC2/D0/PWML0 | PC2_PWML0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 60 | PC3/D1/PWMH0 | LED_R | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 63 | PC5/D3/PWMH1 | DIAG1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 64 | PC6/D4/PWML2 | DIR1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 65 | PC7/D5/PWMH2 | STEP1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 66 | PC8/D6/PWML3 | PC8_PWML3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 67 | PC9/D7/PWMH3 | DRV_EN | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 68 | PB27/NCS3/TIOB0 | PB27_TIOB0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 70 | PA18/TWCK0/A20/WKUP9 | PA18_SCL | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 71 | PA19/MCCK/PWMH1 | MCCK | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 72 | PA20/MCCDA/PWML2 | MCCDA | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 76 | PB15/CANRX1/PWMH3/DAC0/WKUP12 | Fan3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 77 | PB16/TCLK5/PWML0/DAC1 | Fan4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 78 | PA16/SPCK1/TD/AD7 | PA16 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 79 | PA24/MCDA3/PCK1/AD6 | MCDA3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 80 | PA23/MCDA2/TCLK4/AD5 | MCDA2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 81 | PA22/MCDA1/TCLK3/AD4 | MCDA1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 82 | PA6/TIOB2/NCS0/AD3 | TC_nCS3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 83 | PA4/TCLK1/NWAIT/AD2 | M_nCS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 84 | PA3/TIOB1/PWMFI1/AD1/WKUP1 | PA3_AD2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 85 | PA2/TIOA1/NANDRDY/AD0 | TC_nCS4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 86 | PB12/TWD1/PWMH0/AD8 | PB12_AD8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 87 | PB13/TWCK1/PWMH1/AD9 | PB13_AD9 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 88 | PB17/RF/PWML1/AD10 | TC_nCS5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 89 | PB18/RD/PWML2/AD11 | THERM_AN2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 90 | PB19/RK/PWML3/AD12 | THERM_AN1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 91 | PB20/TXD2/SPI0_NPCS1/AD13 | THERM_AN3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 92 | PB21/RXD2/SPI0_NPCS2/AD14/WKUP13 | SPIFLASH_CS | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 93 | PC11/D9/ERX2 | DIAG2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 94 | PC12/D10/ERX3 | DIR2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 95 | PC13/D11/ECOL | STEP2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 96 | PC14/D12/ERXCK | M_nCS2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 97 | PC15/D13/ETX2 | DIAG3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 98 | PC16/D14/ETX3 | DIR3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 99 | PC17/D15/ETXER | STEP3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 100 | PC18/NWR0/NWE/PWMH6 | M_nCS3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 101 | PC19/NANDOE/PWMH5 | DIAG4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 102 | PC29/A8/TIOB7 | TACH_4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 103 | PC30/A9/TCLK7 | HOLD# | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 107 | PA21/MCDA0/PWML0 | MCDA0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 108 | PA25/SPI0_MISO/A18 | NetR83_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 109 | PA26/SPI0_MOSI/A19 | NetR77_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 110 | PA27/SPI0_SPCK/A20/WKUP10 | NetR82_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 111 | PA28/SPI0_NPCS0/PCK2/WKUP11 | PA28_CS0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 112 | PA29/SPI0_NPCS1/NRD | PA29_CS | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 113 | PB0/ETXCK/EREFCK | PB0_ETXCK | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 114 | PB1/ETXEN | PB1_ETXEN | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 115 | PB2/ETX0 | PB2_ETX0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 116 | PC4/D2/PWML1 | DIR4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 117 | PC10/D8/ECRS | STEP4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 118 | PB3/ETX1 | STEP5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 119 | PB4/ECRSDV/ERXDV | M_nCS6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 120 | PB5/ERX0 | M_nCS5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 121 | PB6/ERX1 | DIR7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 122 | PB7/ERXER | MAX_ES4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 123 | PB8/EMDC | STEP7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 127 | PB9/EMDIO | TC_nCS2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 128 | PB10/UOTGVBOF/A18 | M_nCS4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 129 | PB11/UOTGID/A19 | SDCD | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 130 | PC0/ERASE | ERASE | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 131 | PC20/NANDWE/PWMH4 | DIAG5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 132 | PC21/A0/NBS0/PWML4 | HEAT1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 133 | PC22/A1/PWML5 | HEAT2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 134 | PC23/A2/PWML6 | HEATBED | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 135 | PC24/A3/PWML7 | HEAT3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 136 | PC25/A4/TIOA6 | FAN2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 137 | PC26/A5/TIOB6 | FAN1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 138 | PC27/A6/TCLK6 | TC_nCS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 139 | PC28/A7/TIOA7 | TACH_1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 140 | PB14/CANTX1/PWMH2 | MIN_ES4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 141 | PB22/RTS2/PCK0 | DIR5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 142 | PB23/CTS2/SPI0_NPCS3/WKUP14 | DIAG6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 143 | PB24/SCK2/NCS2 | DIR6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 144 | PB25/RTS0/TIOA0 | PB25_TIOA0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | </details> <details> <summary>FB26 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDDPLL | ✅ | Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead. | | 2 | 2 | VDDOUT | ✅ | Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead. | </details> <details> <summary>FB27 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering. | | 2 | 2 | VDDANA | ✅ | Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering. | </details> <details> <summary>FB28 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering. | | 2 | 2 | 3.3VCC | ✅ | Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering. | </details> <details> <summary>FB30 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering. | | 2 | 2 | VDDUTMI | ✅ | Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering. | </details> <details> <summary>J4 - ARM Cortex JTAG-DEBUG Header ❌</summary> DRCY flagged 2 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://cdn.amphenol-cs.com/media/wysiwyg/files/documentation/datasheet/boardwiretoboard/bwb_minitek127_btb.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 6 | 6 | TDO/SWO | ❌ | <details><summary>TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,71.24,46.69,78.74" aspect-ratio="1.55" } <ul><li>Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic)</li><li>Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic)</li><li>Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning)</li><li>Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning)</li><li>Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)</li></ul></details> | | 8 | 8 | TDI | ❌ | <details><summary>TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,70.33,46.69,77.83" aspect-ratio="1.55" } <ul><li>Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic)</li><li>Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic)</li><li>Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning)</li><li>Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning)</li><li>Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)</li></ul></details> | | 10 | 10 | RESET | ❌ | <details><summary>Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,69.42,46.69,76.92" aspect-ratio="1.55" } <ul><li>Pin 10 is connected to the RESET net (from schematic)</li><li>The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input (from schematic)</li><li>A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 (from schematic)</li><li>Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations (reasoning)</li><li>The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions (reasoning)</li><li>Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection (reasoning)</li></ul></details> | | 1 | 1 | 3.3VCC | ✅ | VTref pin correctly connected to 3.3VCC to provide target voltage reference to the debugger. | | 2 | 2 | TMS/SWDIO | ✅ | TMS/SWDIO signal correctly connected to microcontroller pin PB31 with appropriate 100K pull-up resistor R31. | | 3 | 3 | GND | ✅ | Ground pins correctly connected to GND plane. | | 5 | 5 | GND | ✅ | Ground pins correctly connected to GND plane. | | 9 | 9 | GND | ✅ | Ground pins correctly connected to GND plane. | | 4 | 4 | TCK/SWDCLK | ✅ | TCK/SWDCLK signal correctly connected to microcontroller pin PB28 with appropriate 100K pull-up resistor R38. | | 7 | 7 | unconnected-(NetJ4_7) | ✅ | Pin 7 is correctly left unconnected, which is standard for ARM 10-pin JTAG connectors where this pin is typically used as a key pin or for optional nTRST. | </details> <details> <summary>R31 - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TMS/SWDIO | ✅ | Connected to TMS/SWDIO signal line as part of pull-up resistor configuration. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC power rail to provide pull-up voltage. | </details> <details> <summary>R37 - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TDI | ✅ | Connected to TDI signal line as part of pull-up resistor configuration. Note: Due to the TDI/TDO swap at connector J4, this resistor is actually pulling up the microcontroller's TDO pin (PB30) rather than the intended TDI pin (PB29). The resistor itself is correctly implemented; the issue originates from the incorrect routing at J4. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC power rail to provide pull-up voltage. | </details> <details> <summary>R38 - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TCK/SWDCLK | ✅ | Connected to TCK/SWDCLK signal line as part of pull-up resistor configuration. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC power rail to provide pull-up voltage. | </details> <details> <summary>U12 - AT25SF161-SSHD-T ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25sf161b-datasheet?language=en) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AT25SF161-SSHD-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPIFLASH_CS | ✅ | CS# (Chip Select) is connected to microcontroller pin PB21 and through Schottky diode D77 to the shared CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. While the datasheet recommends a direct 10k pull-up from CS to VCC, the diode OR configuration provides functionally equivalent pull-up behavior for the shared SPI bus architecture. | | 2 | SO | MISO_M1BUS | ✅ | SO (Serial Output) is correctly connected to MISO_M1BUS, which routes through tri-state buffer U16 (SN74LVC125A) to the shared MISO line PA25_MISO, preventing bus conflicts when multiple SPI devices share the bus. | | 3 | WP# | WP# | ✅ | WP# (Write Protect) is correctly pulled high to 3.3VCC through 10k resistor R85, disabling write protection and providing better noise immunity than relying solely on the internal pull-up. | | 4 | GND | GND | ✅ | GND is correctly connected to the system ground reference. | | 5 | SI/IO0 | MOSI_M1BUS | ✅ | SI (Serial Input) is correctly connected to MOSI_M1BUS, which routes through buffer U17 (SN74LVC125A) and series resistor R59 (47 ohm) from the microcontroller, providing proper drive capability and signal integrity. | | 6 | SCK | SCLK_M1BUS | ✅ | SCK (Serial Clock) is correctly connected to SCLK_M1BUS, which routes through clock buffer U14 (74AVC9112) and series resistor R13 (47 ohm), providing clean clock distribution with proper signal integrity. | | 7 | HOLD# | HOLD# | ✅ | HOLD# is connected to microcontroller GPIO pin PC30, allowing firmware control of the HOLD function or use as I/O3 for quad-SPI operation. The internal pull-up ensures proper operation when the GPIO is in high-impedance mode. | | 8 | VCC | 3.3VCC | ✅ | VCC is correctly connected to 3.3VCC, which is within the specified supply voltage range of 2.5V-3.6V or 2.7V-3.6V. | </details> <details> <summary>D77 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Anode is correctly connected to CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. This is part of a diode OR configuration that enables the MISO buffer when any of the M1BUS SPI devices is selected. | | K | K | SPIFLASH_CS | ✅ | Cathode is correctly connected to SPIFLASH_CS, which connects to the CS# pin of the SPI flash and to microcontroller pin PB21. The diode allows the pull-up to raise CS# when inactive and blocks reverse current when CS# is driven low. | </details> <details> <summary>R85 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | WP# | ✅ | 10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection. | | 2 | 2 | 3.3VCC | ✅ | 10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection. | </details> <details> <summary>J18 - 0475710001 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-47309-001.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0475710001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | MCDA2 | ✅ | DAT2 data line correctly connected to MCDA2 with appropriate ESD protection and pull-up resistor. | | 2 | CD/DAT3 | MCDA3 | ✅ | CD/DAT3 signal correctly connected to MCDA3 with appropriate ESD protection and pull-up resistor. | | 3 | CMD | MCCDA | ✅ | CMD command line correctly connected to MCCDA with appropriate ESD protection and pull-up resistor. | | 4 | VDD | 3.3VCC | ✅ | VDD power pin correctly connected to 3.3VCC supply with local decoupling capacitor. | | 5 | CLK | MCCK | ✅ | CLK clock line correctly connected to MCCK with ESD protection and no pull-up resistor (as required). | | 6 | VSS | GND | ✅ | VSS ground pin correctly connected to GND. | | 7 | DAT1 | MCDA0 | ✅ | DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct. | | 8 | DAT0 | MCDA1 | ✅ | DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct. | | 9 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 10 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 11 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 12 | CD | SDCD | ✅ | Card detect pin correctly connected to SDCD with appropriate pull-up resistor and ESD protection. | | 13 | CD/POL | GND | ✅ | Card detect polarity pin correctly tied to GND to configure active-low card detect operation. | </details> <details> <summary>D42 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on SDCD signal. | | C | C | SDCD | ✅ | Cathode correctly connected to SDCD signal for ESD protection on card detect line. | </details> <details> <summary>D64 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA1 signal. | | C | C | MCDA1 | ✅ | Cathode correctly connected to MCDA1 signal for ESD protection on microSD data line 1. | </details> <details> <summary>D65 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA0 signal. | | C | C | MCDA0 | ✅ | Cathode correctly connected to MCDA0 signal for ESD protection on microSD data line 0. | </details> <details> <summary>D66 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCCDA signal. | | C | C | MCCDA | ✅ | Cathode correctly connected to MCCDA signal for ESD protection on microSD command line. | </details> <details> <summary>D67 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCCK signal. | | C | C | MCCK | ✅ | Cathode correctly connected to MCCK signal for ESD protection on microSD clock line. | </details> <details> <summary>D68 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA3 signal. | | C | C | MCDA3 | ✅ | Cathode correctly connected to MCDA3 signal for ESD protection on microSD data line 3. | </details> <details> <summary>D69 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA2 signal. | | C | C | MCDA2 | ✅ | Cathode correctly connected to MCDA2 signal for ESD protection on microSD data line 2. | </details> <details> <summary>R64 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SDCD | ✅ | Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply. | </details> <details> <summary>R65 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply. | | 2 | 2 | MCCDA | ✅ | Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply. | </details> <details> <summary>R67 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCDA3 | ✅ | Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply. | </details> <details> <summary>R68 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCDA2 | ✅ | Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply. | </details> <details> <summary>R69 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply. | | 2 | 2 | MCDA1 | ✅ | Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply. | </details> <details> <summary>R70 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply. | | 2 | 2 | MCDA0 | ✅ | Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply. | </details> <details> <summary>J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. | | 2 | 2 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 3 | 3 | NetJ12_3 | ✅ | Signal pin connected to PC2_PWML0 through 100Ω series resistor R137. The resistor provides current limiting and ESD protection for the PWM output signal. | | 4 | 4 | NetJ12_4 | ✅ | Signal pin connected to PA1_CANRX0 through 100Ω series resistor R136. The resistor provides current limiting and ESD protection for the CAN receive signal. | | 5 | 5 | NetJ12_5 | ✅ | Signal pin connected to PA16 through 100Ω series resistor R135. The resistor provides current limiting and ESD protection for the general purpose I/O signal. | | 6 | 6 | NetJ12_6 | ✅ | Signal pin connected to PA0_CANTX0 through 100Ω series resistor R134. The resistor provides current limiting and ESD protection for the CAN transmit signal. | | 7 | 7 | NetJ12_7 | ✅ | Signal pin connected to PA12_RXD1 through 100Ω series resistor R133. The resistor provides current limiting and ESD protection for the UART receive signal. | | 8 | 8 | NetJ12_8 | ✅ | Signal pin connected to PA15_CTS1 through 100Ω series resistor R120. The resistor provides current limiting and ESD protection for the UART clear-to-send signal. | | 9 | 9 | NetJ12_9 | ✅ | Signal pin connected to PA13_TXD1 through 100Ω series resistor R114. The resistor provides current limiting and ESD protection for the UART transmit signal. | | 10 | 10 | NetJ12_10 | ✅ | Signal pin connected to PA14_RTS1 through 100Ω series resistor R109. The resistor provides current limiting and ESD protection for the UART request-to-send signal. | </details> <details> <summary>J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. | | 2 | 2 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 3 | 3 | NetJ13_3 | ✅ | Signal pin connected to NRST through 100Ω series resistor R145. The resistor provides current limiting and ESD protection for the reset signal. | | 4 | 4 | NetJ13_4 | ✅ | Signal pin connected to PB25_TIOA0 through 100Ω series resistor R144. The resistor provides current limiting and ESD protection for the timer I/O signal. | | 5 | 5 | NetJ13_5 | ✅ | Signal pin connected to PA26_MOSI through 100Ω series resistor R143. The resistor provides current limiting and ESD protection for the SPI master-out-slave-in signal. | | 6 | 6 | NetJ13_6 | ✅ | Signal pin connected to PA3_AD2 through 100Ω series resistor R142. The resistor provides current limiting and ESD protection for the ADC input signal. | | 7 | 7 | NetJ13_7 | ✅ | Signal pin connected to PA29_CS through 100Ω series resistor R141. The resistor provides current limiting and ESD protection for the SPI chip select signal. | | 8 | 8 | NetJ13_8 | ✅ | Signal pin connected to PB27_TIOB0 through 100Ω series resistor R140. The resistor provides current limiting and ESD protection for the timer I/O signal. | | 9 | 9 | NetJ13_9 | ✅ | Signal pin connected to PA27_SCLK through 100Ω series resistor R139. The resistor provides current limiting and ESD protection for the SPI clock signal. | | 10 | 10 | NetJ13_10 | ✅ | Signal pin connected to PA25_MISO through 100Ω series resistor R138. The resistor provides current limiting and ESD protection for the SPI master-in-slave-out signal. | </details> <details> <summary>J20 - Header 12X2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-24G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA28_CS0 | ✅ | SPI chip select signal connected directly to PA28_CS0 on microcontroller without series protection resistor. | | 2 | 2 | PA27_SCLK | ✅ | SPI clock signal connected directly to PA27_SCLK on microcontroller without series protection resistor. | | 3 | 3 | PA26_MOSI | ✅ | SPI MOSI signal connected directly to PA26_MOSI on microcontroller without series protection resistor. | | 4 | 4 | PA25_MISO | ✅ | SPI MISO signal connected directly to PA25_MISO on microcontroller without series protection resistor. | | 5 | 5 | unconnected-(NetJ20_5) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 6 | 6 | unconnected-(NetJ20_6) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 7 | 7 | unconnected-(NetJ20_7) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 9 | 9 | unconnected-(NetJ20_9) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 10 | 10 | unconnected-(NetJ20_10) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 11 | 11 | unconnected-(NetJ20_11) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 12 | 12 | unconnected-(NetJ20_12) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 13 | 13 | unconnected-(NetJ20_13) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 14 | 14 | unconnected-(NetJ20_14) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 17 | 17 | unconnected-(NetJ20_17) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 8 | 8 | PB12_AD8 | ✅ | ADC input signal connected directly to PB12_AD8 on microcontroller without series protection resistor. | | 15 | 15 | NetJ20_15 | ✅ | Ethernet transmit data signal connected to PB2_ETX0 through 100Ω series resistor R161 and protected by 6.8V varistor RV3. This provides comprehensive protection for the Ethernet signal. | | 16 | 16 | NetJ20_16 | ✅ | Ethernet transmit enable signal connected to PB1_ETXEN through 100Ω series resistor R160 and protected by 6.8V varistor RV4. This provides comprehensive protection for the Ethernet signal. | | 18 | 18 | NRST | ✅ | Reset signal connected directly to NRST microcontroller reset signal without series protection resistor. | | 19 | 19 | NetJ20_19 | ✅ | Analog/digital I/O signal connected to PB13_AD9 through 100Ω series resistor R159 and protected by 6.8V varistor RV2. This provides comprehensive protection for the signal. | | 20 | 20 | NetJ20_20 | ✅ | Ethernet transmit clock signal connected to PB0_ETXCK through 100Ω series resistor R153 and protected by 6.8V varistor RV1. This provides comprehensive protection for the Ethernet signal. | | 21 | 21 | PA18_SCL | ✅ | I2C clock signal connected directly to PA18_SCL on microcontroller without series protection resistor. | | 22 | 22 | PA17_SDA | ✅ | I2C data signal connected directly to PA17_SDA on microcontroller without series protection resistor. | | 23 | 23 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 24 | 24 | 3.3VCC | ✅ | Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header. | </details> <details> <summary>J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 2 | 2 | PA9_UTXD | ✅ | UART transmit signal connected to PA9_UTXD with ESD protection diode D72. The diode provides unidirectional ESD protection for the signal. | | 3 | 3 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. | | 4 | 4 | PA8_URXD | ✅ | UART receive signal connected to PA8_URXD with ESD protection diode D73. The diode provides unidirectional ESD protection for the signal. | | 5 | 5 | 3.3VCC | ✅ | Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header. | | 6 | 6 | NRST | ✅ | Reset signal connected to NRST with ESD protection diode D71. The diode provides unidirectional ESD protection for the reset signal. | | 7 | 7 | ERASE | ✅ | Erase signal connected to ERASE with ESD protection diode D1. The diode provides unidirectional ESD protection for the erase control signal. | | 8 | 8 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. This is a second 5V power pin on the same connector. | | 9 | 9 | PC8_PWML3 | ✅ | PWM signal connected directly to PC8_PWML3 on microcontroller without series protection resistor or ESD diode. This lacks the protection provided to other signals on this connector. | | 10 | 10 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. This is a second ground pin on the same connector. | </details> <details> <summary>D71 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | NRST | ✅ | Cathode connected to NRST signal for ESD protection. This is correct for protecting the reset pin exposed on external connectors. | </details> <details> <summary>D72 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | PA9_UTXD | ✅ | Cathode connected to PA9_UTXD signal for ESD protection. This is correct for protecting the UART transmit pin exposed on external connector J28. | </details> <details> <summary>D73 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | PA8_URXD | ✅ | Cathode connected to PA8_URXD signal for ESD protection. This is correct for protecting the UART receive pin exposed on external connector J28. | </details> <details> <summary>D1 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | ERASE | ✅ | Cathode connected to ERASE signal for ESD protection. This is correct for protecting the erase pin exposed on external connector J28. | </details> <details> <summary>RV1 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_20 | ✅ | Connected to NetJ20_20 which connects to PB0_ETXCK via series resistor R153. This provides bidirectional ESD protection for the Ethernet transmit clock signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>RV2 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_19 | ✅ | Connected to NetJ20_19 which connects to PB13_AD9 via series resistor R159. This provides bidirectional ESD protection for the ADC input signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>RV3 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_15 | ✅ | Connected to NetJ20_15 which connects to PB2_ETX0 via series resistor R161. This provides bidirectional ESD protection for the Ethernet transmit data signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>RV4 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_16 | ✅ | Connected to NetJ20_16 which connects to PB1_ETXEN via series resistor R160. This provides bidirectional ESD protection for the Ethernet transmit enable signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>U14 - 74AVC9112 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://assets.nexperia.com/documents/data-sheet/74AVC9112.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/74AVC9112GTX) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Vcc | 3.3VCC | ✅ | Vcc pin correctly connected to 3.3VCC power supply. The 3.3V supply voltage is within the device's specified operating range of 0.8V to 3.6V, and proper decoupling is provided by C67 (100nF). | | 2 | A | NetC64_2 | ✅ | Data input A correctly connected to microcontroller SPI clock output PA27/SPI0_SPCK through source termination resistor R82 (24Ω) and filter capacitor C64. The input accepts voltages up to 3.6V and features Schmitt trigger action for noise immunity. | | 3 | nOE | GND | ✅ | Output enable nOE correctly tied to GND to permanently enable all outputs. This is appropriate for a clock distribution buffer that should always be active. | | 4 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 5 | Y1 | NetR3_2 | ✅ | Output Y1 correctly connected through series termination resistor R3 (47Ω) to SCLK_TCBUS. The series resistor provides impedance matching and improves signal integrity for the thermocouple bus clock signal. | | 6 | Y2 | NetR4_2 | ✅ | Output Y2 correctly connected through series termination resistor R4 (47Ω) to PA27_SCLK, which routes to external connector J20. This provides a buffered clock output to off-board devices with proper signal termination. | | 7 | Y3 | NetR13_2 | ✅ | Output Y3 correctly connected through series termination resistor R13 (47Ω) to SCLK_M1BUS. The series resistor provides impedance matching and improves signal integrity for the motor 1 bus clock signal. | | 8 | Y4 | NetR32_2 | ✅ | Output Y4 correctly connected through series termination resistor R32 (47Ω) to SCLK_M2BUS. The series resistor provides impedance matching and improves signal integrity for the motor 2 bus clock signal. | | 23 | NC | | ✅ | NC (no connect) pin correctly left unconnected. | </details> <details> <summary>R3 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_TCBUS | ✅ | Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution. | | 2 | 2 | NetR3_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution. | </details> <details> <summary>R4 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA27_SCLK | ✅ | Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal. | | 2 | 2 | NetR4_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal. | </details> <details> <summary>R13 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_M1BUS | ✅ | Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution. | | 2 | 2 | NetR13_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution. | </details> <details> <summary>R32 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_M2BUS | ✅ | Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution. | | 2 | 2 | NetR32_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution. | </details> <details> <summary>U16 - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/scas290q/scas290q.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | nOE1 | CS_TCBUS | ✅ | Output enable for buffer 1, connected to CS_TCBUS which is derived from thermocouple chip selects through diode OR gate with 10k pullup (R95). | | 2 | A1 | MISO_TCBUS | ✅ | Input to buffer 1, connected to MISO_TCBUS from the thermocouple SPI bus. | | 3 | Y1 | NetR94_2 | ✅ | Output of buffer 1, connected through R94 (47R) to PA25_MISO along with outputs from buffers 2 and 3 in a wire-OR configuration. | | 4 | nOE2 | CS_M1BUS | ✅ | Output enable for buffer 2, connected to CS_M1BUS which is derived from motor bus 1 chip selects through diode OR gate with 10k pullup (R100). | | 5 | A2 | MISO_M1BUS | ✅ | Input to buffer 2, connected to MISO_M1BUS from motor bus 1 and SPI flash. | | 6 | Y2 | NetR94_2 | ✅ | Output of buffer 2, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 3 in a wire-OR configuration. | | 7 | GND | GND | ✅ | Ground pin, correctly connected to GND net. | | 8 | Y3 | NetR94_2 | ✅ | Output of buffer 3, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 2 in a wire-OR configuration. | | 9 | A3 | MISO_M2BUS | ✅ | Input to buffer 3, connected to MISO_M2BUS from motor bus 2. | | 10 | nOE3 | CS_M2BUS | ✅ | Output enable for buffer 3, connected to CS_M2BUS which is derived from motor bus 2 chip selects through diode OR gate with 10k pullup (R97). | | 11 | Y4 | unconnected-(NetU16_11) | ✅ | Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality. | | 12 | A4 | GND | ✅ | Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality. | | 13 | nOE4 | GND | ✅ | Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality. | | 14 | Vcc | 3.3VCC | ✅ | Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor. | | 15 | PAD | GND | ✅ | Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance. | | 23 | NC | | ✅ | No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN. | </details> <details> <summary>U17 - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/scas290q/scas290q.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | nOE1 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 4 | nOE2 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 10 | nOE3 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 13 | nOE4 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 2 | A1 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 5 | A2 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 9 | A3 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 12 | A4 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 3 | Y1 | NetR84_2 | ✅ | Output of buffer 1, connected through R84 (47R) to MOSI_TCBUS to distribute the MOSI signal to the thermocouple bus. | | 6 | Y2 | NetR59_2 | ✅ | Output of buffer 2, connected through R59 (47R) to MOSI_M1BUS to distribute the MOSI signal to motor bus 1. | | 7 | GND | GND | ✅ | Ground pin, correctly connected to GND net. | | 8 | Y3 | NetR89_2 | ✅ | Output of buffer 3, connected through R89 (47R) to MOSI_M2BUS to distribute the MOSI signal to motor bus 2. | | 11 | Y4 | NetR93_2 | ✅ | Output of buffer 4, connected through R93 (47R) to PA26_MOSI to distribute the MOSI signal to an additional SPI device or connector. | | 14 | Vcc | 3.3VCC | ✅ | Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor. | | 15 | PAD | GND | ✅ | Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance. | | 23 | NC | | ✅ | No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN. | </details> <details> <summary>R59 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M1BUS | ✅ | Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting. | | 2 | 2 | NetR59_2 | ✅ | Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting. | </details> <details> <summary>R84 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_TCBUS | ✅ | Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting. | | 2 | 2 | NetR84_2 | ✅ | Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting. | </details> <details> <summary>R89 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M2BUS | ✅ | Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting. | | 2 | 2 | NetR89_2 | ✅ | Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting. | </details> <details> <summary>R93 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA26_MOSI | ✅ | Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting. | | 2 | 2 | NetR93_2 | ✅ | Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting. | </details> <details> <summary>R94 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA25_MISO | ✅ | Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals. | | 2 | 2 | NetR94_2 | ✅ | Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals. | </details> <details> <summary>R77 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA26_MOSI_D | ✅ | Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side. | | 2 | 2 | NetR77_2 | ✅ | Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side. | </details> <details> <summary>R82 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC64_2 | ✅ | Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination. | | 2 | 2 | NetR82_2 | ✅ | Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination. | </details> <details> <summary>R83 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA25_MISO | ✅ | Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side. | | 2 | 2 | NetR83_2 | ✅ | Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side. | </details> <details> <summary>D5 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS4 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D30 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS2 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D31 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS3 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D40 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS6 | ✅ | Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D41 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS7 | ✅ | Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D60 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS5 | ✅ | Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D61 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS1 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D62 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS5 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D63 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS8 | ✅ | Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D70 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS1 | ✅ | Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>D74 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS2 | ✅ | Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>D75 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS3 | ✅ | Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>D76 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS4 | ✅ | Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>R95 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active. | | 2 | 2 | CS_TCBUS | ✅ | Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active. | </details> <details> <summary>R97 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active. | | 2 | 2 | CS_M2BUS | ✅ | Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active. | </details> <details> <summary>R100 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active. | | 2 | 2 | CS_M1BUS | ✅ | Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active. | </details> <details> <summary>S1 - 1571610-2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/1571610-2) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | RESET | ✅ | Pin 1 connects to the RESET net, which is the JTAG reset signal. When the button is pressed, it pulls RESET to ground. The RESET net lacks a pull-up resistor on the target board, but this is acceptable for JTAG applications where the external programmer typically provides the pull-up. | | 2 | S | GND | ✅ | Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability. | | 3 | 3 | GND | ✅ | Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability. | | 4 | 4 | GND | ✅ | Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability. | </details> <details> <summary>S2 - KMR741NG ULC LFS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/littelfuse-c-k-tactile-kmr7-series-datasheet?assetguid=3f886e93-c59b-4ff0-b554-18b427e789cb) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/KMR741NG%20ULC%20LFS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | 3.3VCC | ✅ | Pin 1 is correctly connected to 3.3VCC, providing the high voltage source for the ERASE signal when the button is pressed. | | 2 | | unconnected-(NetS2_2) | ✅ | Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability. | | 4 | | unconnected-(NetS2_4) | ✅ | Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability. | | 3 | | ERASE | ✅ | Pin 3 is correctly connected to the ERASE net. When the button is pressed, ERASE is pulled high to 3.3VCC through pin 1. | </details> <details> <summary>C40 - GRM155R71H103JA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM155R71H103JA88-01.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESET | ✅ | Pin 1 is correctly connected to the RESET net to provide filtering and debouncing for the JTAG reset signal. | | 2 | 2 | 3.3VIO | ✅ | Pin 2 is correctly connected to 3.3VIO. This provides filtering referenced to the I/O voltage rail, which is an acceptable design choice though less common than connecting to ground. | </details> <details> <summary>D24 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD24_A | ✅ | LED anode correctly connected to current limiting resistor R34. The LED is driven by microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0) through a 1kΩ resistor, providing approximately 1.1mA forward current. | | C | C | GND | ✅ | LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high. | </details> <details> <summary>D25 - 5988140107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988140107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD25_A | ✅ | LED anode correctly connected to current limiting resistor R36. The LED is driven by microcontroller GPIO LED_Y (U11A pin 55, PC1) through a 1kΩ resistor, providing approximately 1.3mA forward current. | | C | C | GND | ✅ | LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high. | </details> <details> <summary>R34 - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LED_R | ✅ | Resistor connected to microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0). This is the input side of the current limiting resistor for the red LED. | | 2 | 2 | NetD24_A | ✅ | Resistor connected to red LED anode (D24 pin A). This is the output side of the current limiting resistor, providing approximately 1.1mA to the LED. | </details> <details> <summary>R36 - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LED_Y | ✅ | Resistor connected to microcontroller GPIO LED_Y (U11A pin 55, PC1). This is the input side of the current limiting resistor for the yellow LED. | | 2 | 2 | NetD25_A | ✅ | Resistor connected to yellow LED anode (D25 pin A). This is the output side of the current limiting resistor, providing approximately 1.3mA to the LED. | </details> <details> <summary>D44 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD protection of the 3.3VCC power rail. This is the correct connection for an ESD protection diode. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail for ESD protection. This is the correct connection for protecting the 3.3V power supply from ESD events. | </details> <details> <summary>D45 - DF2S6.8FS,L3M ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://toshiba.semicon-storage.com/info/docget.jsp?did=22219&prodName=DF2S6.8FS) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DF2S6.8FS,L3M) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD protection of the +5VCC power rail. This is the correct connection for an ESD protection diode. | | K | K | +5VCC | ✅ | Cathode connected to +5VCC rail for ESD protection. This is the correct connection for protecting the 5V power supply from bidirectional ESD events. | </details> <details> <summary>R40 - 1k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Connected to 3.3VIO power rail to provide pull-up voltage for I2C SDA line. | | 2 | 2 | PA17_SDA | ✅ | Connected to PA17_SDA (I2C data line) from microcontroller pin 9 and external header J20 pin 22. | </details> <details> <summary>R71 - 1k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Connected to 3.3VIO power rail to provide pull-up voltage for I2C SCL line. | | 2 | 2 | PA18_SCL | ✅ | Connected to PA18_SCL (I2C clock line) from microcontroller pin 70 and external header J20 pin 21. | </details> <details> <summary>Q12A - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Source 1 is correctly connected to GND for low-side switching operation. | | 2 | G | NetQ12_2 | ✅ | Gate 1 is correctly driven through a 100Ω series resistor from buffer U2D output, controlling Fan 1 switching. | | 7 | D | NetC154_2 | ✅ | Drain 1 is correctly connected to switch the Fan 1 load and LED1 indicator. | </details> <details> <summary>Q12B - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 3 | S | GND | ✅ | Source 2 is correctly connected to GND for low-side switching operation. | | 4 | G | NetQ12_4 | ✅ | Gate 2 is correctly driven through a 100Ω series resistor from buffer U2C output, controlling Fan 2 switching. | | 5 | D | NetC153_2 | ✅ | Drain 2 is correctly connected to switch the Fan 2 load and LED2 indicator. | </details> <details> <summary>Q13A - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Source 1 is correctly connected to GND for low-side switching operation. | | 2 | G | NetQ13_2 | ✅ | Gate 1 is correctly driven through a 100Ω series resistor from buffer U2B output, controlling Fan 3 switching. | | 7 | D | NetC211_2 | ✅ | Drain 1 is correctly connected to switch the Fan 3 load and LED3 indicator. | </details> <details> <summary>Q13B - NCV8402AD ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | D | VFAN | ❌ | <details><summary>Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,56.24,70.56,63.74" aspect-ratio="1.29" } <ul><li>Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1">NCV8402ADDR2G</a>, page 1)</li><li>Pin 5 is connected to the VFAN net (from schematic)</li><li>VFAN is the positive power supply rail for the fans (from schematic)</li><li>In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning)</li><li>The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic)</li><li>Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic)</li><li>Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic)</li><li>Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic)</li><li>J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic)</li><li>J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic)</li><li>With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning)</li><li>LED4 cathode is connected to VFAN (from schematic)</li><li>LED4 anode connects through R14 to VFAN (from schematic)</li><li>With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning)</li><li>C209 has both pins connected to VFAN, providing no filtering function (from schematic)</li><li>When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3">NCV8402ADDR2G</a>, page 3)</li><li>This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3">NCV8402ADDR2G</a>, page 3)</li><li>The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3">NCV8402ADDR2G</a>, page 3)</li><li>This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning)</li><li>The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1">NCV8402ADDR2G</a>, page 1)</li><li>Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)</li><li>This connection error makes the Fan 4 control circuit completely non-functional (reasoning)</li></ul></details> | | 3 | S | GND | ✅ | Source 2 is correctly connected to GND for low-side switching operation. | | 4 | G | NetQ13_4 | ✅ | Gate 2 is correctly driven through a 100Ω series resistor from buffer U2A output, controlling Fan 4 switching. | </details> <details> <summary>U2A - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1OE | GND | ✅ | Output enable (1OE) is tied directly to GND, permanently enabling gate 1. This is functionally correct for this always-on fan control application, though it differs from the datasheet recommendation to use a pullup resistor to VCC for high-impedance state during power transitions. | | 2 | 1A | Fan4 | ✅ | Input (1A) is connected to Fan4 control signal with a 10K pulldown resistor (R101) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 3 | 1Y | NetR181_1 | ✅ | Output (1Y) drives a 100R gate resistor (R181) which controls the gate of MOSFET driver Q13B. This is standard practice for MOSFET gate drive circuits to limit inrush current and reduce ringing. | </details> <details> <summary>U2B - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 4 | 2OE | GND | ✅ | Output enable (2OE) is tied directly to GND, permanently enabling gate 2. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers. | | 5 | 2A | Fan3 | ✅ | Input (2A) is connected to Fan3 control signal with a 10K pulldown resistor (R171) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 6 | 2Y | NetR180_1 | ✅ | Output (2Y) drives a 100R gate resistor (R180) which controls the gate of MOSFET driver Q13A. This is standard practice for MOSFET gate drive circuits. | </details> <details> <summary>U2C - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 8 | 3Y | NetR99_1 | ✅ | Output (3Y) drives a 100R gate resistor (R99) which controls the gate of MOSFET driver Q12B. This is standard practice for MOSFET gate drive circuits. | | 9 | 3A | FAN2 | ✅ | Input (3A) is connected to FAN2 control signal with a 10K pulldown resistor (R182) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 10 | 3OE | GND | ✅ | Output enable (3OE) is tied directly to GND, permanently enabling gate 3. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers. | </details> <details> <summary>U2D - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 11 | 4Y | NetR98_1 | ✅ | Output (4Y) drives a 100R gate resistor (R98) which controls the gate of MOSFET driver Q12A. This is standard practice for MOSFET gate drive circuits. | | 12 | 4A | FAN1 | ✅ | Input (4A) is connected to FAN1 control signal with a 10K pulldown resistor (R183) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 13 | 4OE | GND | ✅ | Output enable (4OE) is tied directly to GND, permanently enabling gate 4. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers. | </details> <details> <summary>U2E - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 7 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 14 | VCC | +5VCC | ✅ | Power supply pin is correctly connected to +5VCC with a 100nF bypass capacitor (C92) nearby, meeting datasheet recommendations for decoupling. | | 15 | PAD | SNTP1 | ✅ | Exposed thermal pad (PAD) is connected to net SNTP1. The text label 'SNTP1' near the component suggests this connection is intentional. For optimal thermal performance, this pad should be connected to ground. Verify that SNTP1 is properly connected to ground elsewhere in the design for adequate thermal dissipation. | </details> <details> <summary>D50 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD50_A | ✅ | Anode connected to NetD50_A, forming the upper clamp for the TACH_1 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D51 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD51_A | ✅ | Anode connected to NetD51_A, forming the upper clamp for the TACH_2 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D52 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct. | | K | K | NetD50_A | ✅ | Cathode connected to NetD50_A, completing the lower clamping path for TACH_1 signal protection. This connection is correct. | </details> <details> <summary>D53 - BAT54WX ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | unconnected-(NetD53_A) | ❌ | <details><summary>Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,35.79,70.56,43.29" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected (from schematic)</li><li>D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp (reasoning)</li><li>All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND (from schematic)</li><li>The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) (reasoning)</li><li>Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients (reasoning)</li><li>The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits (reasoning)</li><li>D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 (reasoning)</li></ul></details> | | K | K | NetD51_A | ✅ | Cathode connected to NetD51_A, which is the correct connection for a lower clamp diode. However, the diode is non-functional because pin A is unconnected. | </details> <details> <summary>D54 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD54_A | ✅ | Anode connected to NetD54_A, forming the upper clamp for the TACH_3 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D55 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD55_A | ✅ | Anode connected to NetD55_A, forming the upper clamp for the TACH_4 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D56 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct. | | K | K | NetD54_A | ✅ | Cathode connected to NetD54_A, completing the lower clamping path for TACH_3 signal protection. This connection is correct. | </details> <details> <summary>D57 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct. | | K | K | NetD55_A | ✅ | Cathode connected to NetD55_A, completing the lower clamping path for TACH_4 signal protection. This connection is correct. | </details> <details> <summary>LED1 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED1_A | ✅ | Anode is correctly connected through current limiting resistor R96 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit. | | C | C | NetC154_2 | ✅ | Cathode is correctly connected to the drain of low-side MOSFET driver Q12A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated. | </details> <details> <summary>LED2 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED2_A | ✅ | Anode is correctly connected through current limiting resistor R12 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit. | | C | C | NetC153_2 | ✅ | Cathode is correctly connected to the drain of low-side MOSFET driver Q12B (pin 5), which switches the LED on/off by pulling the cathode to ground when activated. | </details> <details> <summary>LED3 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED3_A | ✅ | Anode is correctly connected through current limiting resistor R15 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit. | | C | C | NetC211_2 | ✅ | Cathode is correctly connected to the drain of low-side MOSFET driver Q13A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated. | </details> <details> <summary>LED4 - 5988110107F ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C | C | VFAN | ❌ | <details><summary>Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,53.30,70.56,60.80" aspect-ratio="1.29" } <ul><li>Pin C (Cathode) is connected directly to net VFAN (from schematic)</li><li>Pin C is the Cathode connection per the datasheet (from datasheet <a href="https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf">5988110107F</a>)</li><li>The anode is connected to VFAN through R14, making both terminals at the same potential (from schematic)</li><li>For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop (from datasheet <a href="https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf">5988110107F</a>)</li><li>With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow (reasoning)</li><li>LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) (from schematic)</li><li>Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern (from schematic)</li><li>J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets (from schematic)</li><li>The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated (reasoning)</li><li>This error prevents LED4 from functioning as a fan status indicator (reasoning)</li></ul></details> | | A | A | NetLED4_A | ✅ | Anode is connected through current limiting resistor R14 (4.7K) to VFAN power rail. While this connection topology is correct, the LED cannot function because the cathode is also connected to VFAN, creating zero voltage difference across the LED. | </details> <details> <summary>J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC154_2 | ✅ | Pin 1 is correctly connected to the switched ground output (NetC154_2) for Fan 1, implementing low-side PWM control where the MOSFET switches the ground return path. | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan. | | 3 | S | NetJ29_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ29_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. | </details> <details> <summary>J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC153_2 | ✅ | Pin 1 is correctly connected to the switched ground output (NetC153_2) for Fan 2, implementing low-side PWM control where the MOSFET switches the ground return path. | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan. | | 3 | S | NetJ22_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ22_3) with proper signal conditioning including pull-up resistor, series resistors, upper clamp diode, and filtering capacitor. Note that the lower clamp diode D53 has an unconnected anode, which reduces protection against negative transients but should not prevent normal operation. | </details> <details> <summary>J31 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC211_2 | ✅ | Pin 1 is correctly connected to the switched ground output (NetC211_2) for Fan 3, implementing low-side PWM control where the MOSFET switches the ground return path. | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan. | | 3 | S | NetJ31_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ31_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. | </details> <details> <summary>J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | VFAN | ❌ | <details><summary>Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="76.69,54.48,84.19,61.98" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net VFAN (from schematic)</li><li>Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net (from schematic)</li><li>Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 (from schematic)</li><li>For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) (from schematic)</li><li>Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 (from schematic)</li><li>Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively (from schematic)</li><li>LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 (from schematic)</li><li>Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output (from schematic)</li><li>The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference (from schematic)</li><li>In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path (reasoning)</li><li>Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate (reasoning)</li><li>With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation (reasoning)</li><li>Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits (reasoning)</li></ul></details> | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing the power supply voltage. However, the fan cannot operate due to the error on pin 1 which prevents the ground return path. | | 3 | S | NetJ30_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ30_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. The tachometer circuit is correctly implemented, though the fan may not operate due to the error on pin 1. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **S1** (1571610-2): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/1571610-2) - **P1** (2213S-08G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-08G) - **J20** (2213S-24G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-24G) - **F2** (3557-2): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-2) - **X1** (405C35B12M00000): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/405C35B12M00000) - **D23** (5988170107F): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988170107F) - **J8** (61729-0010BLF): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/61729-0010BLF) - **U11A, U11B, U11C** (ATSAM3X8EA-AU): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) - **U19** (INA381A2IDSGR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/INA381A2IDSGR) - **U20** (L78L05ABUTR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/L78L05ABUTR) - **U8** (MIC5353-3.3YMT-TR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MIC5353-3.3YMT-TR) - **Q8** (MMBT3904T-7-F): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MMBT3904T-7-F) - **JP1, JP2** (NOTAPART-Solder Bridge): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) - **D26** (RSB39VTE-17): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RSB39VTE-17) - **U18** (TLP293(TPL,E): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TLP293%28TPL,E) </details> Note: DRCY uses AI. Please verify the outputs.

Fans.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component Q13B, pin 5: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.

Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet NCV8402ADDR2G, page 1)
Pin 5 is connected to the VFAN net (from schematic)
VFAN is the positive power supply rail for the fans (from schematic)
In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning)
The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic)
Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic)
Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic)
Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic)
J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic)
J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic)
With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning)
LED4 cathode is connected to VFAN (from schematic)
LED4 anode connects through R14 to VFAN (from schematic)
With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning)
C209 has both pins connected to VFAN, providing no filtering function (from schematic)
When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet NCV8402ADDR2G, page 3)
This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet NCV8402ADDR2G, page 3)
The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet NCV8402ADDR2G, page 3)
This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning)
The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet NCV8402ADDR2G, page 1)
Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)
This connection error makes the Fan 4 control circuit completely non-functional (reasoning)

All affected pins

Component Q13B, pin `5`: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.

Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet NCV8402ADDR2G, page 1)
Pin 5 is connected to the VFAN net (from schematic)
VFAN is the positive power supply rail for the fans (from schematic)
In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning)
The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic)
Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic)
Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic)
Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic)
J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic)
J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic)
With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning)
LED4 cathode is connected to VFAN (from schematic)
LED4 anode connects through R14 to VFAN (from schematic)
With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning)
C209 has both pins connected to VFAN, providing no filtering function (from schematic)
When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet NCV8402ADDR2G, page 3)
This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet NCV8402ADDR2G, page 3)
The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet NCV8402ADDR2G, page 3)
This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning)
The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet NCV8402ADDR2G, page 1)
Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)
This connection error makes the Fan 4 control circuit completely non-functional (reasoning)

Component LED4, pin `C`: Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3.

Pin C (Cathode) is connected directly to net VFAN (from schematic)
Pin C is the Cathode connection per the datasheet (from datasheet 5988110107F)
The anode is connected to VFAN through R14, making both terminals at the same potential (from schematic)
For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop (from datasheet 5988110107F)
With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow (reasoning)
LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) (from schematic)
Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern (from schematic)
J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets (from schematic)
The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated (reasoning)
This error prevents LED4 from functioning as a fan status indicator (reasoning)

Component J30, pin `1`: Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor.

Pin 1 is connected to net VFAN (from schematic)
Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net (from schematic)
Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 (from schematic)
For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) (from schematic)
Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 (from schematic)
Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively (from schematic)
LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 (from schematic)
Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output (from schematic)
The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference (from schematic)
In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path (reasoning)
Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate (reasoning)
With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation (reasoning)
Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits (reasoning)

Datasheets: 📄 LED4 📄 J30 📄 Q13B

_{Replace a datasheet: 📤 J30 📤 LED4 📤 Q13B}

[🚨 Error] **Component `Q13B`, pin `5`: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,56.24,70.56,63.74" aspect-ratio="1.29" } - Pin 5 is the Drain 2 terminal according to the datasheet *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 is connected to the VFAN net *(from schematic)* - VFAN is the positive power supply rail for the fans *(from schematic)* - In a low-side switch configuration, the drain should be connected to the load, not to the power supply *(reasoning)* - The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs *(from schematic)* - Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) *(from schematic)* - Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) *(from schematic)* - Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) *(from schematic)* - J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output *(from schematic)* - J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN *(from schematic)* - With both fan connector pins at VFAN, the fan cannot be switched on or off *(reasoning)* - LED4 cathode is connected to VFAN *(from schematic)* - LED4 anode connects through R14 to VFAN *(from schematic)* - With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up *(reasoning)* - C209 has both pins connected to VFAN, providing no filtering function *(from schematic)* - When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This will cause excessive current flow limited only by the NCV8402's internal current limiting *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features *(reasoning)* - The datasheet shows typical application with drain connected to the load, not to the power supply *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 *(reasoning)* - This connection error makes the Fan 4 control circuit completely non-functional *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>Q13B</code>, pin `5`: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.</summary> - Pin 5 is the Drain 2 terminal according to the datasheet *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 is connected to the VFAN net *(from schematic)* - VFAN is the positive power supply rail for the fans *(from schematic)* - In a low-side switch configuration, the drain should be connected to the load, not to the power supply *(reasoning)* - The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs *(from schematic)* - Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) *(from schematic)* - Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) *(from schematic)* - Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) *(from schematic)* - J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output *(from schematic)* - J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN *(from schematic)* - With both fan connector pins at VFAN, the fan cannot be switched on or off *(reasoning)* - LED4 cathode is connected to VFAN *(from schematic)* - LED4 anode connects through R14 to VFAN *(from schematic)* - With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up *(reasoning)* - C209 has both pins connected to VFAN, providing no filtering function *(from schematic)* - When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This will cause excessive current flow limited only by the NCV8402's internal current limiting *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features *(reasoning)* - The datasheet shows typical application with drain connected to the load, not to the power supply *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 *(reasoning)* - This connection error makes the Fan 4 control circuit completely non-functional *(reasoning)* </details> <details> <summary>Component <code>LED4</code>, pin `C`: Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3.</summary> - Pin C (Cathode) is connected directly to net VFAN *(from schematic)* - Pin C is the Cathode connection per the datasheet *(from datasheet [5988110107F](<https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf>))* - The anode is connected to VFAN through R14, making both terminals at the same potential *(from schematic)* - For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop *(from datasheet [5988110107F](<https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf>))* - With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow *(reasoning)* - LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) *(from schematic)* - Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern *(from schematic)* - J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets *(from schematic)* - The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated *(reasoning)* - This error prevents LED4 from functioning as a fan status indicator *(reasoning)* </details> <details> <summary>Component <code>J30</code>, pin `1`: Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor.</summary> - Pin 1 is connected to net VFAN *(from schematic)* - Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net *(from schematic)* - Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 *(from schematic)* - For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) *(from schematic)* - Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 *(from schematic)* - Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively *(from schematic)* - LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 *(from schematic)* - Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output *(from schematic)* - The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference *(from schematic)* - In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path *(reasoning)* - Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate *(reasoning)* - With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation *(reasoning)* - Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits *(reasoning)* </details> </details> Datasheets: [📄 LED4](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📄 J30](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📄 Q13B](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) Replace a datasheet: [📤 J30](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) [📤 LED4](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) [📤 Q13B](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G)

allspice-bd commented

2026-07-28 22:37:34 +00:00

First-time contributor

Hey @emmy , is this right, please have alook

Fans.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component D53, pin A: Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels.

Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected (from schematic)
D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp (reasoning)
All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND (from schematic)
The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) (reasoning)
Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients (reasoning)
The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits (reasoning)
D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 (reasoning)

_{Replace a datasheet: 📤 D53}

[🚨 Error] **Component `D53`, pin `A`: Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,35.79,70.56,43.29" aspect-ratio="1.29" } - Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected *(from schematic)* - D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp *(reasoning)* - All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND *(from schematic)* - The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) *(reasoning)* - Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients *(reasoning)* - The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits *(reasoning)* - D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 *(reasoning)* Replace a datasheet: [📤 D53](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP)

Microcontroller.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component U11A, pins 29, 30: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.

Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)
Pin 30 (PB30/TDO) is connected to net TDI (from schematic)
Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)
Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)
The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)
The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)
The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)
This swap will prevent JTAG debugging from functioning correctly (reasoning)
In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)
The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)

All affected pins

Component U11A, pins `29, 30`: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.

Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)
Pin 30 (PB30/TDO) is connected to net TDI (from schematic)
Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)
Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)
The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)
The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)
The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)
This swap will prevent JTAG debugging from functioning correctly (reasoning)
In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)
The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)

Component J4, pins `6, 8`: TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.

Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic)
Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic)
Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)
Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)
PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)
PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)
TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning)
Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning)
Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)

Datasheets: 📄 J4

_{Upload/replace a datasheet: 📤 J4 📤 U11A}

[🚨 Error] **Component `U11A`, pins `29, 30`: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.08,54.04,36.49" aspect-ratio="1.55" } - Pin 29 (PB29/TDI) is connected to net TDO/SWO *(from schematic)* - Pin 30 (PB30/TDO) is connected to net TDI *(from schematic)* - Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input *(from schematic)* - Net TDI connects to J4 pin 8, which is the debugger's TDI output *(from schematic)* - The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) *(reasoning)* - The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) *(reasoning)* - The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 *(reasoning)* - This swap will prevent JTAG debugging from functioning correctly *(reasoning)* - In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net *(reasoning)* - The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U11A</code>, pins `29, 30`: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.</summary> - Pin 29 (PB29/TDI) is connected to net TDO/SWO *(from schematic)* - Pin 30 (PB30/TDO) is connected to net TDI *(from schematic)* - Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input *(from schematic)* - Net TDI connects to J4 pin 8, which is the debugger's TDI output *(from schematic)* - The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) *(reasoning)* - The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) *(reasoning)* - The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 *(reasoning)* - This swap will prevent JTAG debugging from functioning correctly *(reasoning)* - In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net *(reasoning)* - The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net *(reasoning)* </details> <details> <summary>Component <code>J4</code>, pins `6, 8`: TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.</summary> - Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) *(from schematic)* - Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) *(from schematic)* - Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout *(reasoning)* - Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout *(reasoning)* - PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name *(reasoning)* - PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name *(reasoning)* - TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain *(reasoning)* - Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain *(reasoning)* - Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) *(reasoning)* </details> </details> Datasheets: [📄 J4](https://cdn.amphenol-cs.com/media/wysiwyg/files/documentation/datasheet/boardwiretoboard/bwb_minitek127_btb.pdf) Upload/replace a datasheet: [📤 J4](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF) [📤 U11A](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU)

Microcontroller.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component J4, pin 10: Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature.

Pin 10 is connected to the RESET net (from schematic)
The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input (from schematic)
A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 (from schematic)
Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)
The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations (reasoning)
The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions (reasoning)
Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection (reasoning)

_{Replace a datasheet: 📤 J4}

[🚨 Error] **Component `J4`, pin `10`: Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,69.42,46.69,76.92" aspect-ratio="1.55" } - Pin 10 is connected to the RESET net *(from schematic)* - The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input *(from schematic)* - A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 *(from schematic)* - Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout *(reasoning)* - The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations *(reasoning)* - The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions *(reasoning)* - Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection *(reasoning)* Replace a datasheet: [📤 J4](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF)

Power.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[⚠️ Warning] Component U1, pin 2: VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1.

Pin 2 (VIN) is connected to net VPWR (from schematic)
VPWR is the main power input rail derived from VPWR_IN through fuse F2 (from schematic)
This pin is the 3.5- to 28-V input supply voltage (from datasheet TPS54531DDAR, page 3)
Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended (from datasheet TPS54531DDAR, page 14)
Input decoupling capacitor of 10μF is recommended per datasheet (from datasheet TPS54531DDAR, page 1)
C71 is a 10nF capacitor on VPWR (from schematic)
C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total (from schematic)
Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF (reasoning)
Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response (reasoning)
A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) (reasoning)

_{Replace a datasheet: 📤 U1}

[⚠️ Warning] **Component `U1`, pin `2`: VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="50.79,50.95,58.29,58.45" aspect-ratio="1.29" } - Pin 2 (VIN) is connected to net VPWR *(from schematic)* - VPWR is the main power input rail derived from VPWR_IN through fuse F2 *(from schematic)* - This pin is the 3.5- to 28-V input supply voltage *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=3>), page 3)* - Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14>), page 14)* - Input decoupling capacitor of 10μF is recommended per datasheet *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=1>), page 1)* - C71 is a 10nF capacitor on VPWR *(from schematic)* - C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total *(from schematic)* - Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF *(reasoning)* - Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response *(reasoning)* - A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) *(reasoning)* Replace a datasheet: [📤 U1](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TPS54531DDAR)

Power.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component D21, pins A, K: TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.

Pin A (Anode) is connected to net VMOTE (from schematic)
Pin K (Cathode) is connected to net GND (from schematic)
VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic)
SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet SMAJ24A, page 1)
The color band on the device denotes the cathode terminal (from datasheet SMAJ24A, page 1)
The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic)
With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning)
The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet SMAJ24A, page 1)
A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning)
This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning)
The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)

_{Replace a datasheet: 📤 D21}

[🚨 Error] **Component `D21`, pins `A, K`: TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="2.64,54.95,10.14,63.63" aspect-ratio="1.29" } - Pin A (Anode) is connected to net VMOTE *(from schematic)* - Pin K (Cathode) is connected to net GND *(from schematic)* - VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text *(from schematic)* - SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - The color band on the device denotes the cathode terminal *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails *(from schematic)* - With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation *(reasoning)* - The maximum instantaneous forward voltage is 3.5V at 25A for single die parts *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop *(reasoning)* - This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail *(reasoning)* - The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 *(reasoning)* Replace a datasheet: [📤 D21](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A)

allspice-carah pinned this 2026-04-22 20:59:45 +00:00

allspice-carah added 1 commit 2026-04-22 22:31:48 +00:00

Adds bom-gen automation

Generate BOM / Generate_BOM (push) Failing after 31s

Details

348a2b9ce0

allspice-carah requested review from AllSpiceAlice 2026-04-23 02:41:52 +00:00

allspice-carah requested review from allspice-nick 2026-04-23 02:41:52 +00:00

allspice-carah referenced this design review

2026-04-23 02:42:33 +00:00

Find root cause of FET <> VFAN connection #6

allspice-carah added this to the V3 milestone 2026-04-23 02:49:29 +00:00

allspice-carah referenced this design review

2026-04-23 02:50:45 +00:00

Pin swap TDI/TDO on U11A #7

allspice-hermes added 1 commit 2026-06-03 18:15:31 +00:00

Update .allspice/workflows/bom-gen.yml

Generate BOM / Generate_BOM (push) Failing after 2s

Details

d662d0cef2

allspice-hermes added 1 commit 2026-06-03 18:17:45 +00:00

Update .allspice/workflows/bom-gen.yml

Generate BOM / Generate_BOM (push) Successful in 28s

Details

Run Connections Checker / connections-checker (pull_request) Has been cancelled

Details

5cbb246b56

allspice-Desiree reviewed 2026-08-21 19:33:55 +00:00

Microcontroller.SchDoc

allspice-Desiree commented

2026-08-21 19:33:55 +00:00

First-time contributor

Check this out

!thumbnail[](Microcontroller.SchDoc){ view-coords="7.3,51.8,11.4,57.6" variant="default" aspect-ratio="1.545" diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" } Check this out

allspice-edwin requested review from DRCY 2026-09-11 20:38:11 +00:00

DRCYAI commented

2026-09-11 20:51:42 +00:00

DRCY has reviewed this Design Review, and there should be a review posted below.

DRCYAI reviewed 2026-09-11 21:22:37 +00:00

DRCYAI left a comment

DRCY Connections Checker Review

DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 266 component(s) to review, and found 9 potential issue(s) in 12 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

C1 - 100nF 0603 50V X7R ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: C0603C104K5RACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC1_1	✅	Bootstrap capacitor pin 1 correctly connected to BOOT pin of U1.
2	2	NetC1_2	✅	Bootstrap capacitor pin 2 correctly connected to switch node (PH).

U1 - TPS54531 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: TPS54531DDAR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	BOOT	NetC1_1	✅	BOOT pin correctly connected to bootstrap capacitor C1 between BOOT and PH.
2	VIN	VPWR	✅	VIN pin correctly connected to VPWR input rail with appropriate decoupling.
3	EN	NetR2_2	✅	EN pin correctly configured with voltage divider and fault protection comparators for enable control.
4	SS	NetC171_2	✅	SS pin correctly connected to soft-start capacitor C171 for controlled startup.
5	VSNS	NetC3_1	✅	VSNS pin correctly connected to feedback resistor divider for 5V output regulation.
6	COMP	NetC150_2	✅	COMP pin correctly connected to compensation network for loop stability.
7	GND	GND	✅	GND pin correctly connected to ground plane.
8	PH	NetC1_2	✅	PH pin correctly connected to inductor and catch diode forming the switch node.
9	PAD	GND	✅	PAD (thermal pad) correctly connected to ground for heat dissipation.

D2 - SK54B ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: SK54B-LTP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Diode anode correctly connected to ground for buck converter catch diode operation.
K	CATHODE	NetC1_2	✅	Diode cathode correctly connected to switch node for freewheeling operation.

R2 - 1.4k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RMCF0402FT1K40 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Enable pull-down resistor correctly configured as part of voltage divider for EN pin control.
2	2	NetR2_2	✅	Enable pull-down resistor correctly configured as part of voltage divider for EN pin control.

L1 - 4.7uH 10A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: SRP1038A-4R7M (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC1_2	✅	Inductor pin 1 correctly connected to switch node (PH) of U1.
2	2	NetC3_2	✅	Inductor pin 2 correctly connected to output voltage rail.

C171 - 10nF 0402 50V X7R ✅

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Part Number: GRM155R71H103JA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Soft-start capacitor correctly connected between SS pin and GND to control startup ramp.
2	2	NetC171_2	✅	Soft-start capacitor correctly connected between SS pin and GND to control startup ramp.

R11 - 10k 1% 0402 ✅

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR2_2	✅	Enable pull-up resistor correctly configured as part of voltage divider for EN pin control.
2	2	VPWR	✅	Enable pull-up resistor correctly configured as part of voltage divider for EN pin control.

C71 - 10nF 0402 50V X7R ✅

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Part Number: GRM155R71H103JA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Input decoupling capacitor correctly connected between VPWR and GND for high-frequency filtering.
2	2	VPWR	✅	Input decoupling capacitor correctly connected between VPWR and GND for high-frequency filtering.

R5 - 1.96k 1% 0402 ✅

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Part Number: RC0402FR-071K96L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower feedback resistor in voltage divider. Correctly connected between VSNS feedback pin (NetC3_1) and ground.
2	2	NetC3_1	✅	Lower feedback resistor in voltage divider. Correctly connected between VSNS feedback pin (NetC3_1) and ground.

C3 - C0402_TBD ✅

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Warning

DRCY couldn't determine a part number for this component. Add a part-number
attribute to this component — either the attribute configured as the
repository's preferred part-number attribute, or a recognizable one such as
MPN/IPN — to enable datasheet lookup.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC3_1	✅	Optional feedforward capacitor in parallel with R1 to improve transient response. Marked DNI (do not install) with placeholder value of 10pF.
2	2	NetC3_2	✅	Optional feedforward capacitor in parallel with R1 to improve transient response. Marked DNI (do not install) with placeholder value of 10pF.

C4 - 47uF 1210 10V X5R ✅

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Part Number: GRM32ER61A476KE20L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Output filter capacitor providing bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground, in parallel with C5.
2	2	NetC3_2	✅	Output filter capacitor providing bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground, in parallel with C5.

C5 - 47uF 1210 10V X5R ✅

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Part Number: GRM32ER61A476KE20L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Output filter capacitor in parallel with C4, providing additional bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground.
2	2	NetC3_2	✅	Output filter capacitor in parallel with C4, providing additional bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground.

C151 - 22pF 0402 50V C0G ✅

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Part Number: 04025A220JAT2A (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	High-frequency compensation capacitor creating a pole to attenuate switching noise. Correctly connected between COMP pin and ground.
2	2	NetC150_2	✅	High-frequency compensation capacitor creating a pole to attenuate switching noise. Correctly connected between COMP pin and ground.

R10 - 37.4K 1% 0402 ✅

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Part Number: RC0402FR-0737K4L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Compensation network resistor in series with C150, setting the zero frequency for loop compensation. Correctly connected between C150 and ground.
2	2	NetC150_1	✅	Compensation network resistor in series with C150, setting the zero frequency for loop compensation. Correctly connected between C150 and ground.

R1 - 10.2k 1% 0402 ✅

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Part Number: RC0402FR-0710K2L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC3_2	✅	Upper feedback resistor in voltage divider setting output to 5V. Correctly connected between +5VCC output (NetC3_2) and VSNS feedback pin (NetC3_1).
2	2	NetC3_1	✅	Upper feedback resistor in voltage divider setting output to 5V. Correctly connected between +5VCC output (NetC3_2) and VSNS feedback pin (NetC3_1).

C150 - 2.2nF 25V C0G 0402 ✅

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Part Number: C0402C222J3GACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC150_1	✅	Compensation network capacitor in series with R10, creating a zero to stabilize the control loop. Correctly connected between COMP pin and ground through R10.
2	2	NetC150_2	✅	Compensation network capacitor in series with R10, creating a zero to stabilize the control loop. Correctly connected between COMP pin and ground through R10.

R148 - 0.01R 1% 0805 ✅

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Part Number: KRL1220E-M-R010-F-T5 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC3_2	✅	Current sense resistor correctly placed in series between the buck regulator output (NetC3_2) and the main 5V supply rail (+5VCC) to measure load current for overcurrent protection.
2	2	+5VCC	✅	Current sense resistor correctly placed in series between the buck regulator output (NetC3_2) and the main 5V supply rail (+5VCC) to measure load current for overcurrent protection.

R102 - RK73H1ETTP1001F ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR102_1	✅	Pull-up resistor correctly configured to hold U19 RESET pin high, enabling LATCHING mode operation for the overcurrent protection circuit.
2	2	5V0_AUX	✅	Pull-up resistor correctly configured to hold U19 RESET pin high, enabling LATCHING mode operation for the overcurrent protection circuit.

C200 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering near the U20 regulator output.
2	2	5V0_AUX	✅	Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering near the U20 regulator output.

C201 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering for the U19 comparator.
2	2	5V0_AUX	✅	Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering for the U19 comparator.

R119 - 4.7k 1% 0402 ✅

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Part Number: RC0402FR-074K7L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified.
2	2	NetR115_1	✅	Lower resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified.

U19 - INA381_ALT ✅

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Part Number: INA381A2IDSGR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN+	NetC3_2	✅	IN+ is correctly connected to NetC3_2, the high side of current sense resistor R148, to measure the voltage before the load.
2	Vs	5V0_AUX	✅	Vs is correctly connected to 5V0_AUX, providing power to the INA381 within its specified operating range of 2.7-5.5V.
3	nALERT	NetR2_2	✅	nALERT is correctly connected to NetR2_2, which controls the enable pin of buck converter U1 to disable the regulator when current limit is exceeded.
4	RESET	NetR102_1	✅	RESET is correctly pulled high by R102 to 5V0_AUX, configuring the comparator in LATCHING mode as indicated by schematic text notes.
5	CMPREF	NetR115_1	✅	CMPREF is correctly connected to the voltage divider formed by R115 and R119, setting the reference threshold. However, the calculated current limit (~6A with typical gain assumptions) does not match the text note stating '~4A'.
6	CMPIN	NetU19_6	✅	CMPIN and VOUT are correctly connected together (NetU19_6), which is the standard configuration for the INA381 where the amplified sense voltage is fed directly to the comparator input.
7	VOUT	NetU19_6	✅	CMPIN and VOUT are correctly connected together (NetU19_6), which is the standard configuration for the INA381 where the amplified sense voltage is fed directly to the comparator input.
8	IN-	+5VCC	✅	IN- is correctly connected to +5VCC, the low side of current sense resistor R148, to measure the voltage after the load.
9	GND	GND	✅	GND is correctly connected to the ground plane.

R115 - 15K 1% 0402 ✅

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Part Number: RC1005F153CS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR115_1	✅	Upper resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified.
2	2	5V0_AUX	✅	Upper resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified.

D23 - 5988170107F ✅

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Part Number: 5988170107F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD23_A	✅	LED anode correctly connected through current limiting resistor R33 to 3.3V supply.
C	C	GND	✅	LED cathode correctly connected to ground.

C24 - GRM155R60J105KE19D ✅

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Part Number: GRM155R60J105KE19D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	1µF output capacitor correctly connected between 3.3V output and ground for LDO stability.
2	2	GND	✅	1µF output capacitor correctly connected between 3.3V output and ground for LDO stability.

C34 - GRM155R60J105KE19D ✅

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Part Number: GRM155R60J105KE19D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	1µF input capacitor correctly connected between 5V input and ground for LDO stability.
2	2	GND	✅	1µF input capacitor correctly connected between 5V input and ground for LDO stability.

U8 - MIC5353-3.3YMT-TR ✅

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Part Number: MIC5353-3.3YMT-TR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	EN	+5VCC	✅	EN pin correctly connected to +5VCC to enable the regulator whenever 5V power is present.
2	GND	GND	✅	GND pin correctly connected to ground plane.
3	VIN	+5VCC	✅	VIN pin correctly connected to +5VCC supply, which is within the 2.6V to 6.0V input range.
4	VOUT	3.3VCC	✅	VOUT pin correctly connected to 3.3VCC output rail with proper 1µF output capacitor C24.
5	ADJ	NetU8_5	✅	ADJ pin correctly left as no-connect for the fixed 3.3V output variant.
6	BYP	NetC26_1	✅	BYP pin correctly connected to 100nF bypass capacitor C26 for noise reduction.
7	PAD	GND	✅	Exposed heatsink pad correctly connected to ground for thermal management.

C26 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC26_1	✅	100nF bypass capacitor correctly connected between U8 BYP pin and ground for noise reduction.
2	2	GND	✅	100nF bypass capacitor correctly connected between U8 BYP pin and ground for noise reduction.

R33 - RK73H1ETTP1001F ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD23_A	✅	1k current limiting resistor correctly connected between 3.3V supply and LED anode, providing approximately 1.3mA LED current.
2	2	3.3VCC	✅	1k current limiting resistor correctly connected between 3.3V supply and LED anode, providing approximately 1.3mA LED current.

U20 - 78L05 ✅

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Part Number: L78L05ABUTR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	OUT	5V0_AUX	✅	Output pin correctly connected to 5V0_AUX rail, providing regulated 5V auxiliary power for analog circuits.
2	GND	GND	✅	Ground pin correctly connected to GND net.
3	IN	VPWR	✅	Input pin correctly connected to VPWR rail, receiving 12-24VDC input power.

C203 - C0603C104K5RACTU ✅

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Part Number: C0603C104K5RACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	Input filter capacitor terminal correctly connected to VPWR rail.
2	2	GND	✅	Input filter capacitor terminal correctly connected to GND.

C199 - C0603C104K5RACTU ✅

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Part Number: C0603C104K5RACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	Input filter capacitor terminal correctly connected to VPWR rail.
2	2	GND	✅	Input filter capacitor terminal correctly connected to GND.

C202 - C0603C104K5RACTU ✅

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Part Number: C0603C104K5RACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	Input filter capacitor terminal correctly connected to VPWR rail.
2	2	GND	✅	Input filter capacitor terminal correctly connected to GND.

C95 - C0603C104K5RACTU ✅

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Part Number: C0603C104K5RACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOT1	✅	100nF decoupling capacitor correctly connected between VMOT1 and GND for medium-frequency filtering.
2	2	GND	✅	100nF decoupling capacitor correctly connected between VMOT1 and GND for medium-frequency filtering.

D43 - SMAJ24A ✅

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Part Number: SMAJ24A (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode is correctly connected to GND for standard unidirectional TVS diode configuration protecting VMOT1.
K	K	VMOT1	✅	Cathode is correctly connected to VMOT1 rail for transient voltage suppression.

C93 - 10uF 1206 50V X5R ✅

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Part Number: 490-10756-2-ND (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	10uF bulk capacitor correctly connected between VMOT1 and GND for low-frequency filtering and energy storage.
2	2	VMOT1	✅	10uF bulk capacitor correctly connected between VMOT1 and GND for low-frequency filtering and energy storage.

C94 - CAP 1nF 50V 0402 X7R ✅

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Part Number: GRM155R71H102KA01D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOT1	✅	1nF decoupling capacitor correctly connected between VMOT1 and GND for high-frequency filtering.
2	2	GND	✅	1nF decoupling capacitor correctly connected between VMOT1 and GND for high-frequency filtering.

C16 - 10uF 1206 50V X5R ✅

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Part Number: 490-10756-2-ND (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Bulk capacitor correctly connected between VBED and GND for input filtering of the heated bed power supply.
2	2	VBED	✅	Bulk capacitor correctly connected between VBED and GND for input filtering of the heated bed power supply.

C35 - CAP 1nF 50V 0402 X7R ✅

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Part Number: GRM155R71H102KA01D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	High-frequency decoupling capacitor correctly connected between VPWR and GND for noise filtering.
2	2	GND	✅	High-frequency decoupling capacitor correctly connected between VPWR and GND for noise filtering.

D22 - SMAJ24A ✅

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Part Number: SMAJ24A (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode anode correctly connected to GND for transient voltage suppression of the VPWR rail.
K	K	VPWR	✅	TVS diode cathode correctly connected to VPWR rail for transient protection with 24V stand-off voltage matching the 12-24VDC input specification.

F2 - 3557-2 ✅

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Part Number: 3557-2 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR_IN	✅	Input terminal of fuse block, correctly connected to VPWR_IN from barrier strip connector J3 pin 5.
2	2	VPWR	✅	Output terminal of fuse block, correctly connected to VPWR which supplies power to downstream circuits including the Mosfets page.

F1 - 3557-2 ✅

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Part Number: 3557-20 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED_IN	✅	Fuse holder connecting VBED_IN input to VBED output rail for heated bed overcurrent protection. Connection is correct.
2	2	VBED	✅	Fuse holder connecting VBED_IN input to VBED output rail for heated bed overcurrent protection. Connection is correct.

C13 - CAP 1nF 50V 0402 X7R ✅

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Part Number: GRM155R71H102KA01D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED	✅	1nF high-frequency decoupling capacitor correctly connected between VBED and GND as part of multi-stage filtering network.
2	2	GND	✅	1nF high-frequency decoupling capacitor correctly connected between VBED and GND as part of multi-stage filtering network.

C15 - C0603C104K5RACTU ✅

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Part Number: C0603C104K5RACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED	✅	100nF medium-frequency decoupling capacitor correctly connected between VBED and GND for bulk filtering.
2	2	GND	✅	100nF medium-frequency decoupling capacitor correctly connected between VBED and GND for bulk filtering.

C210 - UWT1V101MCL1GS ✅

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Part Number: UWT1V101MCL1GS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED	✅	100µF aluminum electrolytic bulk capacitor with pin 1 (positive) to VBED and pin 2 (negative) to GND. Polarity and voltage rating are correct for the 12-24V heated bed power rail.
2	2	GND	✅	100µF aluminum electrolytic bulk capacitor with pin 1 (positive) to VBED and pin 2 (negative) to GND. Polarity and voltage rating are correct for the 12-24V heated bed power rail.

D78 - SMAJ24A ✅

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Part Number: SMAJ24A (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode protecting VBED rail with anode to GND and cathode to VBED. This is correctly oriented for overvoltage protection of a positive 12-24V rail.
K	K	VBED	✅	TVS diode protecting VBED rail with anode to GND and cathode to VBED. This is correctly oriented for overvoltage protection of a positive 12-24V rail.

D21 - SMAJ24A ❌

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Part Number: SMAJ24A (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	VMOT2	❌	TVS diode connections are reversed. The anode is connected to VMOT2 and cathode to GND, which places the diode in forward-bias during normal operation instead of providing transient protection. Pin A (Anode) is connected to net VMOT2 (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOT2 is a motor power input rail labeled 'MOTORS 5-8' with specified input range of 12-24VDC per the page note 'Inputs Compatible with 12-24VDC' (from schematic) The cathode terminal is marked with a color band on the package body, and the anode is the unmarked terminal opposite to the cathode band (from datasheet SMAJ24A, page 2) For unidirectional TVS diode protection of a positive voltage rail, the standard configuration is cathode to the protected positive rail and anode to ground, allowing the TVS to remain reverse-biased during normal operation (reasoning) With the current connection (anode to VMOT2, cathode to GND), the TVS diode is forward-biased during normal operation, which would cause it to conduct continuously and effectively short VMOT2 to ground through the diode's forward voltage drop (reasoning) Other TVS diodes on the same page protecting similar positive rails (D22 on VPWR, D43 on VMOT1, D78 on VBED) all have their anodes connected to GND and cathodes to the positive rail being protected (from schematic) The SMAJ24A has a reverse stand-off voltage (VRWM) of 24.0V, breakdown voltage (VBR) of 26.70V minimum to 29.50V maximum, and maximum clamping voltage of 38.9V at 10.3A peak pulse current (from datasheet SMAJ24A, page 4) The connections should be corrected to: Pin A (Anode) to GND and Pin K (Cathode) to VMOT2 to provide proper transient voltage protection (reasoning)
K	K	GND	❌	TVS diode connections are reversed. The anode is connected to VMOT2 and cathode to GND, which places the diode in forward-bias during normal operation instead of providing transient protection. Pin A (Anode) is connected to net VMOT2 (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOT2 is a motor power input rail labeled 'MOTORS 5-8' with specified input range of 12-24VDC per the page note 'Inputs Compatible with 12-24VDC' (from schematic) The cathode terminal is marked with a color band on the package body, and the anode is the unmarked terminal opposite to the cathode band (from datasheet SMAJ24A, page 2) For unidirectional TVS diode protection of a positive voltage rail, the standard configuration is cathode to the protected positive rail and anode to ground, allowing the TVS to remain reverse-biased during normal operation (reasoning) With the current connection (anode to VMOT2, cathode to GND), the TVS diode is forward-biased during normal operation, which would cause it to conduct continuously and effectively short VMOT2 to ground through the diode's forward voltage drop (reasoning) Other TVS diodes on the same page protecting similar positive rails (D22 on VPWR, D43 on VMOT1, D78 on VBED) all have their anodes connected to GND and cathodes to the positive rail being protected (from schematic) The SMAJ24A has a reverse stand-off voltage (VRWM) of 24.0V, breakdown voltage (VBR) of 26.70V minimum to 29.50V maximum, and maximum clamping voltage of 38.9V at 10.3A peak pulse current (from datasheet SMAJ24A, page 4) The connections should be corrected to: Pin A (Anode) to GND and Pin K (Cathode) to VMOT2 to provide proper transient voltage protection (reasoning)

C17 - CAP 1nF 50V 0402 X7R ✅

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Part Number: GRM155R71H102KA01D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOT2	✅	Connected to VMOT2 motor power rail for high-frequency noise filtering.
2	2	GND	✅	Connected to GND, completing the decoupling capacitor connection across the VMOT2 power rail.

C18 - C0603C104K5RACTU ✅

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Part Number: C0603C104K5RACTU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOT2	✅	Connected to VMOT2 motor power rail for mid-frequency decoupling.
2	2	GND	✅	Connected to GND, completing the decoupling capacitor connection.

C14 - 10uF 1206 50V X5R ✅

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Part Number: 490-10756-2-ND (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. Pin order is reversed compared to C17 and C18, but this is acceptable for a non-polarized ceramic capacitor.
2	2	VMOT2	✅	Connected to VMOT2, providing bulk capacitance for the motor power rail.

R155 - 10k 1% 0402 ✅

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower resistor of voltage divider correctly connected between the comparator IN+ input and ground.
2	2	NetR154_2	✅	Lower resistor of voltage divider correctly connected between the comparator IN+ input and ground.

R158 - 100k 1% 0402 ✅

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Part Number: RC1005F104CS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower resistor of reference voltage divider correctly connected between the comparator IN- input and ground.
2	2	NetR157_1	✅	Lower resistor of reference voltage divider correctly connected between the comparator IN- input and ground.

R154 - 24k 1% 0402 ✅

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Part Number: CRCW040224K0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOT1	✅	Upper resistor of voltage divider correctly connected between VMOT1 and the comparator IN+ input, scaling VMOT1 by factor of 0.294.
2	2	NetR154_2	✅	Upper resistor of voltage divider correctly connected between VMOT1 and the comparator IN+ input, scaling VMOT1 by factor of 0.294.

U21 - AP331A ✅

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Part Number: AP331AWG-7 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR157_1	✅	IN- pin correctly connected to reference voltage divider from 5V0_AUX through R157/R158, providing approximately 2.17V reference.
2	GND	GND	✅	GND pin correctly connected to ground plane.
3	IN+	NetR154_2	✅	IN+ pin correctly connected to VMOT1 voltage divider through R154/R155, providing scaled monitoring voltage of approximately 0.294 × VMOT1.
4	OUT	NetR2_2	✅	Output pin correctly connected to NetR2_2 with pull-up resistor R11 (10k to VPWR) and hysteresis feedback R156 (1M). Output is OR'ed with other comparators for fault detection.
5	VCC	VPWR	✅	VCC pin correctly connected to VPWR (12-24V supply), which is within the recommended 2-36V operating range.

R156 - 1M 5% 0402 ✅

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Part Number: ERJ2GEJ105X (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR2_2	✅	Hysteresis feedback resistor correctly connected between comparator output and IN+ input, providing approximately 50mV of hysteresis to prevent oscillation.
2	2	NetR154_2	✅	Hysteresis feedback resistor correctly connected between comparator output and IN+ input, providing approximately 50mV of hysteresis to prevent oscillation.

R157 - 130k 1% 0402 ✅

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Part Number: RC0402JR-07130KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR157_1	✅	Upper resistor of reference voltage divider correctly connected between 5V0_AUX and the comparator IN- input, providing stable reference voltage.
2	2	5V0_AUX	✅	Upper resistor of reference voltage divider correctly connected between 5V0_AUX and the comparator IN- input, providing stable reference voltage.

R26 - 24k 1% 0402 ✅

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Part Number: CRCW040224K0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOT2	✅	Connected to VMOT2, forming the upper resistor of a voltage divider that scales the motor supply voltage for monitoring.
2	2	NetR26_2	✅	Connected to NetR26_2, the voltage divider output node that feeds the comparator's non-inverting input along with feedback resistor R28.

R28 - 1M 5% 0402 ✅

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Part Number: ERJ2GEJ105X (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR2_2	✅	Connected to NetR2_2 (comparator output), providing positive feedback for hysteresis.
2	2	NetR26_2	✅	Connected to NetR26_2 (comparator non-inverting input), completing the positive feedback path for hysteresis.

R56 - 10k 1% 0402 ✅

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the lower resistor of the voltage divider for VMOT2 monitoring.
2	2	NetR26_2	✅	Connected to NetR26_2, the voltage divider output node that feeds the comparator's non-inverting input.

R57 - 130k 1% 0402 ✅

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Part Number: RC0402JR-07130KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR57_1	✅	Connected to NetR57_1, the reference voltage divider output node that feeds the comparator's inverting input.
2	2	5V0_AUX	✅	Connected to 5V0_AUX, forming the upper resistor of the reference voltage divider.

R58 - 100k 1% 0402 ✅

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Part Number: RC1005F104CS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the lower resistor of the reference voltage divider.
2	2	NetR57_1	✅	Connected to NetR57_1, the reference voltage node that feeds the comparator's inverting input.

U6 - AP331A ✅

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Part Number: AP331AWG-7 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR57_1	✅	IN- (inverting input) is correctly connected to a reference voltage divider formed by R57 and R58, providing approximately 2.17V reference from 5V0_AUX.
2	GND	GND	✅	GND pin is correctly connected to the ground net.
3	IN+	NetR26_2	✅	IN+ (non-inverting input) is correctly connected to a voltage divider monitoring VMOT2, with R26 and R56 setting the threshold and R28 providing hysteresis feedback.
4	OUT	NetR2_2	✅	Output pin is correctly connected to NetR2_2, which serves as an enable signal with pull-up resistor R11 providing the required pull-up for the open-collector output.
5	VCC	VPWR	✅	VCC pin is correctly connected to VPWR, providing power supply within the specified 2-36V range.

R103 - 0R 0603 ✅

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Part Number: CR0603-J/-000ELF (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	0-ohm jumper correctly connects VPWR to VFAN, but rated current of 1A may be insufficient for 18 fan connections if high-current fans are used.
2	2	VFAN	✅	0-ohm jumper correctly connects VPWR to VFAN, but rated current of 1A may be insufficient for 18 fan connections if high-current fans are used.

P1 - Header 4X2 ✅

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Part Number: 2213S-08G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	VFAN power pins correctly connected to fan power rail with dual pins for current distribution.
3	3	VFAN	✅	VFAN power pins correctly connected to fan power rail with dual pins for current distribution.
2	2	GND	✅	Ground pins correctly connected with multiple pins for current return path.
4	4	GND	✅	Ground pins correctly connected with multiple pins for current return path.
6	6	GND	✅	Ground pins correctly connected with multiple pins for current return path.
8	8	GND	✅	Ground pins correctly connected with multiple pins for current return path.
5	5	VPWR	✅	VPWR power pins correctly connected to main power rail with dual pins for current distribution.
7	7	VPWR	✅	VPWR power pins correctly connected to main power rail with dual pins for current distribution.

J3 - 10 Pos barrier ✅

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Part Number: 4DB-P108-10 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOT2	✅	VMOT2 motor power input correctly connected with TVS protection and filtering capacitors.
2	2	GND	✅	Ground pins correctly connected with multiple pins for current return path.
4	4	GND	✅	Ground pins correctly connected with multiple pins for current return path.
6	6	GND	✅	Ground pins correctly connected with multiple pins for current return path.
8	8	GND	✅	Ground pins correctly connected with multiple pins for current return path.
3	3	VMOT1	✅	VMOT1 motor power input correctly connected with TVS protection and filtering capacitors.
5	5	VPWR_IN	✅	VPWR_IN main power input correctly connected through fuse F2 to VPWR rail.
7	7	VBED_IN	✅	VBED_IN heated bed power input correctly connected through fuse F1 to VBED rail.
9	9	VBED	✅	VBED heated bed power output correctly connected with TVS protection and filtering capacitors.
10	10	HTBD-OUT	✅	HTBD-OUT heated bed output correctly connected to mosfet control circuitry.

J8 - USB-B ✅

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Part Number: 61729-0010BLF (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS	NetC43_2	✅	VBUS pin correctly connected to power filtering network through C43 and FB29 to VUSB.
2	DM	DM	✅	USB data pins correctly connected to DM and DP nets with proper ESD protection, but downstream common mode choke L5 causes differential pair swap.
3	DP	DP	✅	USB data pins correctly connected to DM and DP nets with proper ESD protection, but downstream common mode choke L5 causes differential pair swap.
4	GND	USB_GND	✅	Ground and shield pins correctly connected to USB_GND for isolated USB design.
5	SHLD	USB_GND	✅	Ground and shield pins correctly connected to USB_GND for isolated USB design.
6	SHLD	USB_GND	✅	Ground and shield pins correctly connected to USB_GND for isolated USB design.

L5 - DLW21HN900SQ2L ✅

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Part Number: DLW21HN900SQ2L (MPN) — inferred by DRCY

Pin Designator	Net	Correct?	Analysis
1	NetL5_1	✅	Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines.
2	NetD27_4	✅	Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines.
3	NetD27_6	✅	Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines.
4	NetL5_4	✅	Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines.

D26 - RSB39VTE-17 ✅

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Part Number: RSB39VTE-17 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides high-voltage discharge path between isolated USB_GND and system GND for isolation protection.
C	C	USB_GND	✅	TVS diode correctly provides high-voltage discharge path between isolated USB_GND and system GND for isolation protection.

D27 - PRTR5V0U2F ✅

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Part Number: PRTR5V0U2F,115 (MPN) — inferred by DRCY

Pin Designator	Net	Correct?	Analysis
1	DM	✅	I/O1 pin correctly receives DM signal from USB connector for ESD protection.
2	USB_GND	✅	Ground pin correctly connected to USB_GND for ESD protection reference.
3	DP	✅	I/O2 pin correctly receives DP signal from USB connector for ESD protection.
4	NetD27_4	✅	Protected output for I/O1 correctly routes to common mode choke L5 pin 2.
5	NetC43_2	✅	VBUS pin correctly connected to USB power rail for ESD protection.
6	NetD27_6	✅	Protected output for I/O2 correctly routes to common mode choke L5 pin 3.

C43 - GRM155R71H103JA88D ✅

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Part Number: GRM155R71H103JA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB_GND	✅	Decoupling capacitor correctly connected between USB_GND and VBUS for high-frequency filtering.
2	2	NetC43_2	✅	Decoupling capacitor correctly connected between USB_GND and VBUS for high-frequency filtering.

FB29 - FERRITE 120R 3A 0603 ✅

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Part Number: CIS10P121AC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	Ferrite bead correctly filters USB power between connector VBUS and isolated VUSB rail.
2	2	NetC43_2	✅	Ferrite bead correctly filters USB power between connector VBUS and isolated VUSB rail.

U9 - ADuM4160 ✅

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Part Number: ADUM3160BRWZ-RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS1	VUSB	✅	VBUS1 correctly connected to USB bus voltage through ferrite bead from connector.
2	GND1	USB_GND	✅	GND1 pins correctly connected to USB_GND, providing ground reference for upstream side of isolator.
8	GND1	USB_GND	✅	GND1 pins correctly connected to USB_GND, providing ground reference for upstream side of isolator.
3	VDD1	VDD1	✅	VDD1 is an internal regulator output that requires only external decoupling capacitor C39. No external power source is needed.
4	PDEN	VDD1	✅	PDEN is correctly tied to VDD1 to keep the device enabled during normal operation.
5	SPU	VDD1	✅	SPU is correctly tied to VDD1 for speed and pull-up configuration.
6	UD- 1	UD_N	✅	USB data lines are swapped: UD+ 1 (pin 7) connects to DM (D-) and UD- 1 (pin 6) connects to DP (D+). This polarity inversion will prevent proper USB communication. The connections should be reversed so UD+ connects to DP and UD- connects to DM.
7	UD+ 1	UD_P	✅	USB data lines are swapped: UD+ 1 (pin 7) connects to DM (D-) and UD- 1 (pin 6) connects to DP (D+). This polarity inversion will prevent proper USB communication. The connections should be reversed so UD+ connects to DP and UD- connects to DM.
9	GND2	GND	✅	GND2 pins correctly connected to system ground GND, providing ground reference for downstream (MCU) side of isolator.
15	GND2	GND	✅	GND2 pins correctly connected to system ground GND, providing ground reference for downstream (MCU) side of isolator.
10	UD+ 2	UI_P	✅	MCU-side USB data lines correctly connected: UD+ 2 to DHSDP (D+) and UD- 2 to DHSDM (D-) through series resistors.
11	UD- 2	UI_N	✅	MCU-side USB data lines correctly connected: UD+ 2 to DHSDP (D+) and UD- 2 to DHSDM (D-) through series resistors.
12	PIN	3.3VCC	✅	PIN connected to 3.3VCC while other downstream power pins (VDD2, VBUS2) connect to +3.3VCC. Without datasheet confirmation, it's unclear if PIN should be on the same supply net as VDD2 and VBUS2.
13	SPD	3.3VCC	✅	SPD connected to 3.3VCC, likely for speed configuration control.
14	VDD2	+3.3VCC	✅	VDD2 correctly connected to +3.3VCC supply for downstream side power.
16	VBUS2	+3.3VCC	✅	VBUS2 correctly connected to +3.3VCC, providing VBUS output to MCU side.

R43 - CRCW040224R0FKED ✅

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_N	✅	24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_N path that incorrectly connects to DP instead of DM.
2	2	NetL5_4	✅	24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_N path that incorrectly connects to DP instead of DM.

R46 - CRCW040224R0FKED ✅

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_P	✅	24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_P path that incorrectly connects to DM instead of DP.
2	2	NetL5_1	✅	24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_P path that incorrectly connects to DM instead of DP.

C39 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VDD1	✅	100nF decoupling capacitor correctly placed between VDD1 and USB_GND with appropriate value and voltage rating for decoupling the internal regulator output.
2	2	USB_GND	✅	100nF decoupling capacitor correctly placed between VDD1 and USB_GND with appropriate value and voltage rating for decoupling the internal regulator output.

R47 - CRCW040224R0FKED ✅

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_P	✅	Series resistor correctly placed in USB D+ path from isolator to MCU.
2	2	UI_P	✅	Series resistor correctly placed in USB D+ path from isolator to MCU.

C28 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	Decoupling capacitor correctly placed between VUSB and USB_GND with appropriate specifications.
2	2	USB_GND	✅	Decoupling capacitor correctly placed between VUSB and USB_GND with appropriate specifications.

C32 - GRM155R60J105KE19D ✅

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Part Number: GRM155R60J105KE19D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	Bulk decoupling capacitor for VUSB with marginal voltage rating. 6.3V rating for 5V USB provides minimal margin; 10V or higher rating recommended for reliability.
2	2	USB_GND	✅	Bulk decoupling capacitor for VUSB with marginal voltage rating. 6.3V rating for 5V USB provides minimal margin; 10V or higher rating recommended for reliability.

R45 - CRCW040224R0FKED ✅

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_N	✅	Series resistor correctly placed in USB D- path from isolator to MCU.
2	2	UI_N	✅	Series resistor correctly placed in USB D- path from isolator to MCU.

U11B - ATML-ATSAM3X-LQFP-144 ❌

DRCY flagged 1 potential issues in this component.

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Part Number: ATSAM3X8EA-AU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
37	DHSDP	UMCU_P	❌	The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together. Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic) Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic) Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet ATSAM3X8EA-AU, page 4) DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning) USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning) Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning) The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)
38	DHSDM	UMCU_N	❌	The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together. Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic) Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic) Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet ATSAM3X8EA-AU, page 4) DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning) USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning) Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning) The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)
42	DFSDP	NetR48_1	❌	The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together. Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic) Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic) Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet ATSAM3X8EA-AU, page 4) DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning) USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning) Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning) The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)
43	DFSDM	NetR42_1	❌	The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together. Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic) Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic) Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18) Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18) The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet ATSAM3X8EA-AU, page 4) DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning) USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning) Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning) The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)
35	XOUT	NetC41_2	✅	XOUT is correctly connected to the 12MHz crystal (X1) through a 3pF load capacitor (C41).
36	XIN	NetC42_2	✅	XIN is correctly connected to the 12MHz crystal (X1) through a 3pF load capacitor (C42).
39	VBUS	VBUS_UC	✅	VBUS is correctly connected to a USB power detection circuit using an optoisolator (U18) and transistor (Q8).
40	VBG	NetC49_1	✅	VBG is connected to a 10pF capacitor (C49) and 6.8kΩ resistor (R49) to ground, providing filtering for the bias voltage reference.
46	JTAGSEL	GND	✅	JTAGSEL is correctly tied to GND, ensuring JTAG mode is disabled for normal operation.
47	NRSTB	RESET	✅	NRSTB is correctly connected to the RESET net, which is a cross-page signal with connections on other schematic pages.
48	XIN32	XIN32	✅	XIN32 and XOUT32 are page-local nets with no visible external crystal circuit. The design may be using the internal 32 kHz RC oscillator instead.
49	XOUT32	XOUT32	✅	XIN32 and XOUT32 are page-local nets with no visible external crystal circuit. The design may be using the internal 32 kHz RC oscillator instead.
50	SHDN	SHDN	✅	SHDN is correctly configured as an output pin indicating device operating mode.
51	TST	GND	✅	TST is correctly tied to GND, ensuring test mode is disabled for normal operation.
53	FWUP	NetR51_1	✅	FWUP is correctly connected to a 100kΩ external pull-up resistor (R51) to +3.3VCC as required by the datasheet.
69	NRST	NetC169_1	✅	NRST is correctly connected through a 100Ω series resistor (R149) with a 100nF filter capacitor (C169) to ground.
75	ADVREF	VDDANA	✅	ADVREF is correctly connected to VDDANA with appropriate decoupling capacitors C76 (100nF) and C77 (10nF).

R48 - CRCW040224R0FKED ❌

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR48_1	❌	R48 is part of an incorrect connection between USB high-speed pin DHSDP (pin 37) and full-speed pin DFSDP (pin 42) of U11B. R48 pin 2 connects to UMCU_P which connects to U11B pin 37 (DHSDP) (from schematic) R48 pin 1 connects to NetR48_1 which connects to U11B pin 42 (DFSDP) (from schematic) R48 is a 24Ω resistor (from schematic) This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)
2	2	UMCU_P	❌	R48 is part of an incorrect connection between USB high-speed pin DHSDP (pin 37) and full-speed pin DFSDP (pin 42) of U11B. R48 pin 2 connects to UMCU_P which connects to U11B pin 37 (DHSDP) (from schematic) R48 pin 1 connects to NetR48_1 which connects to U11B pin 42 (DFSDP) (from schematic) R48 is a 24Ω resistor (from schematic) This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)

C76 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VDDANA	✅	C76 provides decoupling for VDDANA and ADVREF.
2	2	GND	✅	C76 provides decoupling for VDDANA and ADVREF.

C77 - GRM155R71H103JA88D ✅

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Part Number: GRM155R71H103JA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VDDANA	✅	C77 provides additional high-frequency decoupling for VDDANA and ADVREF.
2	2	GND	✅	C77 provides additional high-frequency decoupling for VDDANA and ADVREF.

R42 - CRCW040224R0FKED ❌

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR42_1	❌	R42 is part of an incorrect connection between USB high-speed pin DHSDM (pin 38) and full-speed pin DFSDM (pin 43) of U11B. R42 pin 2 connects to UMCU_N which connects to U11B pin 38 (DHSDM) (from schematic) R42 pin 1 connects to NetR42_1 which connects to U11B pin 43 (DFSDM) (from schematic) R42 is a 24Ω resistor (from schematic) This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)
2	2	UMCU_N	❌	R42 is part of an incorrect connection between USB high-speed pin DHSDM (pin 38) and full-speed pin DFSDM (pin 43) of U11B. R42 pin 2 connects to UMCU_N which connects to U11B pin 38 (DHSDM) (from schematic) R42 pin 1 connects to NetR42_1 which connects to U11B pin 43 (DFSDM) (from schematic) R42 is a 24Ω resistor (from schematic) This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)

C49 - CL05C100JB5NNNC ✅

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Part Number: CL05C100JB5NNNC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC49_1	✅	C49 provides filtering for the VBG bias voltage reference pin of U11B.
2	2	GND	✅	C49 provides filtering for the VBG bias voltage reference pin of U11B.

R49 - CRCW04026K80FKED ✅

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Part Number: CRCW04026K80FKED (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	R49 provides a DC path to ground for the VBG bias voltage reference pin of U11B.
2	2	NetC49_1	✅	R49 provides a DC path to ground for the VBG bias voltage reference pin of U11B.

R149 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NRST	✅	Series resistor terminal correctly connected to external NRST signal for reset line filtering.
2	2	NetC169_1	✅	Series resistor terminal correctly connected to MCU NRST pin through RC filter network.

X1 - 405C35B12M00000 ✅

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Part Number: 405C35B12M00000 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	C1	NetC42_2	✅	Crystal terminal C1 correctly connects to microcontroller XIN pin through load capacitor C42.
2	GND	GND	✅	Crystal ground pins correctly connected to system ground.
4	GND	GND	✅	Crystal ground pins correctly connected to system ground.
3	C2	NetC41_2	✅	Crystal terminal C2 correctly connects to microcontroller XOUT pin through load capacitor C41.

C169 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC169_1	✅	Filter capacitor correctly positioned between reset series resistor and microcontroller NRST pin.
2	2	GND	✅	Filter capacitor correctly grounded to complete RC reset filter.

C42 - 3pF 0603 50V NP0 ✅

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Part Number: 06031A3R0BAT2A (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Load capacitor correctly grounded for crystal oscillator circuit.
2	2	NetC42_2	✅	Load capacitor correctly connects to XIN and crystal C1 terminal, with value properly calculated for 13pF crystal load.

R51 - RC1005F104CS ✅

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Part Number: RC1005F104CS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR51_1	✅	Pull-up resistor correctly connects to FWUP pin as required by datasheet.
2	2	+3.3VCC	✅	Pull-up resistor correctly connects to 3.3V supply to provide required pull-up for FWUP.

C41 - 3pF 0603 50V NP0 ✅

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Part Number: 06031A3R0BAT2A (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Load capacitor correctly grounded for crystal oscillator circuit.
2	2	NetC41_2	✅	Load capacitor correctly connects to XOUT and crystal C2 terminal, with value properly calculated for 13pF crystal load.

R152 - RK73H1ETTP1001F ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	Current-limiting resistor for optoisolator LED, correctly sized at 1k to provide approximately 3.75mA LED current.
2	2	NetR152_2	✅	Current-limiting resistor for optoisolator LED, correctly sized at 1k to provide approximately 3.75mA LED current.

U18 - OPTO SO-4 OPNDRN OUT ✅

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Part Number: TLP293(TPL,E (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	A	NetR152_2	✅	Anode of optoisolator LED, correctly connected through R152 (1k) current-limiting resistor to VUSB for USB presence detection.
2	K	USB_GND	✅	Cathode of optoisolator LED, correctly connected to USB_GND on the isolated side.
3	E	GND	✅	Emitter of phototransistor output, correctly connected to system GND on the non-isolated side.
4	C	NetQ8_1	✅	Collector of phototransistor output, correctly connected to Q8 base through R151 pull-up resistor for signal inversion.

R151 - CRCW04026K80FKED ✅

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Part Number: CRCW04026K80FKED (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetQ8_1	✅	Pull-up resistor for optoisolator output and base resistor for Q8, correctly sized at 6.8k to provide adequate base drive.
2	2	+5VCC	✅	Pull-up resistor for optoisolator output and base resistor for Q8, correctly sized at 6.8k to provide adequate base drive.

Q8 - MMBT3904_SOT523 ✅

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Part Number: MMBT3904T-7-F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	B	NetQ8_1	✅	Base terminal correctly connected to optoisolator collector output through R151 pull-up, providing signal inversion for VBUS detection.
2	E	GND	✅	Emitter terminal correctly connected to GND for common-emitter configuration.
3	C	VBUS_UC	✅	Collector terminal correctly connected to VBUS_UC to provide inverted USB presence signal to microcontroller.

R150 - CRCW04026K80FKED ✅

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Part Number: CRCW04026K80FKED (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBUS_UC	✅	Pull-up resistor for VBUS_UC signal, correctly sized at 6.8k to pull the microcontroller VBUS sense pin high when USB is connected.
2	2	+5VCC	✅	Pull-up resistor for VBUS_UC signal, correctly sized at 6.8k to pull the microcontroller VBUS sense pin high when USB is connected.

U11A - ATML-ATSAM3X-LQFP-144 ❌

DRCY flagged 2 potential issues in this component.

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Part Number: ATSAM3X8EA-AU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
24	PA1/CANRX0/PCK0/WKUP0	PA1_CANRX0	❌	PA1 (CANRX0) and PA5 (PWM) are incorrectly connected together through R41 (1k). This connection serves no clear functional purpose and will cause signal integrity issues. Pin 24 is PA1 which can be configured as CANRX0, PCK0, or general I/O with WKUP0 function (from datasheet ATSAM3X8EA-AU, page 18) Pin 25 is PA5 which can be configured as TIOA2, PWMFI0, or general I/O with WKUP2 function (from datasheet ATSAM3X8EA-AU, page 18) Pin 24 is connected to net PA1_CANRX0 and pin 25 to net PA5_PWM (from schematic) R41 (1k) connects PA5_PWM to PA1_CANRX0 (from schematic) PA1_CANRX0 and PA5_PWM are both page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0) PA1 is typically used as CAN receive input (CANRX0) and PA5 as timer/PWM output (TIOA2/PWMFI0) (reasoning) Connecting a CAN receive input to a PWM/timer output through a 1k resistor serves no standard circuit purpose (reasoning) If PA5 actively drives PWM signals, it will interfere with CAN reception on PA1 (reasoning) If PA1 receives CAN data, the 1k resistor connection to PA5 will load the CAN bus and may cause communication errors (reasoning) PA5_PWM has no other connections besides R41, suggesting it is not used for any intended function (from schematic) R41 should be removed and the connection between PA1 and PA5 eliminated (reasoning)
25	PA5/TIOA2/PWMFI0/WKUP2	PA5_PWM	❌	PA1 (CANRX0) and PA5 (PWM) are incorrectly connected together through R41 (1k). This connection serves no clear functional purpose and will cause signal integrity issues. Pin 24 is PA1 which can be configured as CANRX0, PCK0, or general I/O with WKUP0 function (from datasheet ATSAM3X8EA-AU, page 18) Pin 25 is PA5 which can be configured as TIOA2, PWMFI0, or general I/O with WKUP2 function (from datasheet ATSAM3X8EA-AU, page 18) Pin 24 is connected to net PA1_CANRX0 and pin 25 to net PA5_PWM (from schematic) R41 (1k) connects PA5_PWM to PA1_CANRX0 (from schematic) PA1_CANRX0 and PA5_PWM are both page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0) PA1 is typically used as CAN receive input (CANRX0) and PA5 as timer/PWM output (TIOA2/PWMFI0) (reasoning) Connecting a CAN receive input to a PWM/timer output through a 1k resistor serves no standard circuit purpose (reasoning) If PA5 actively drives PWM signals, it will interfere with CAN reception on PA1 (reasoning) If PA1 receives CAN data, the 1k resistor connection to PA5 will load the CAN bus and may cause communication errors (reasoning) PA5_PWM has no other connections besides R41, suggesting it is not used for any intended function (from schematic) R41 should be removed and the connection between PA1 and PA5 eliminated (reasoning)
29	PB29/TDI	TDO/SWO	❌	PB29 (TDI) and PB30 (TDO) are swapped - TDI pin connected to TDO/SWO net and TDO pin connected to TDI net. Pin 29 is PB29 which is TDI after reset (from datasheet ATSAM3X8EA-AU, page 18) Pin 30 is PB30 which is TDO/TRACESWO after reset (from datasheet ATSAM3X8EA-AU, page 18) Pin 29 is connected to net TDO/SWO (from schematic) Pin 30 is connected to net TDI (from schematic) TDO/SWO net connects to J4 pin 6 (from schematic) TDI net connects to J4 pin 8 (from schematic) In JTAG standard, TDI is input to target and TDO is output from target (reasoning) The MCU TDI pin should connect to the connector TDI pin, and MCU TDO should connect to connector TDO (reasoning) The connections are swapped - pin 29 (TDI) should connect to TDI net, and pin 30 (TDO) should connect to TDO/SWO net (reasoning) This swap will prevent JTAG debugging from functioning correctly (reasoning)
30	PB30/TDO/TRACESWO	TDI	❌	PB29 (TDI) and PB30 (TDO) are swapped - TDI pin connected to TDO/SWO net and TDO pin connected to TDI net. Pin 29 is PB29 which is TDI after reset (from datasheet ATSAM3X8EA-AU, page 18) Pin 30 is PB30 which is TDO/TRACESWO after reset (from datasheet ATSAM3X8EA-AU, page 18) Pin 29 is connected to net TDO/SWO (from schematic) Pin 30 is connected to net TDI (from schematic) TDO/SWO net connects to J4 pin 6 (from schematic) TDI net connects to J4 pin 8 (from schematic) In JTAG standard, TDI is input to target and TDO is output from target (reasoning) The MCU TDI pin should connect to the connector TDI pin, and MCU TDO should connect to connector TDO (reasoning) The connections are swapped - pin 29 (TDI) should connect to TDI net, and pin 30 (TDO) should connect to TDO/SWO net (reasoning) This swap will prevent JTAG debugging from functioning correctly (reasoning)
1	PB26/CTS0/TCLK0/WKUP15	STEP6	✅	PB26 configured as STEP6 output for stepper motor control.
2	PA9/UTXD/PWMH3	PA9_UTXD	✅	PA9 configured as UTXD for UART transmit.
3	PA10/RXD0/DATRG/WKUP5	DIAG7	✅	PA10 and PA11 configured as DIAG7 and DIAG8 diagnostic inputs.
4	PA11/TXD0/ADTRG/WKUP6	DIAG8	✅	PA10 and PA11 configured as DIAG7 and DIAG8 diagnostic inputs.
5	PA12/RXD1/PWML1/WKUP7	PA12_RXD1	✅	PA12 and PA13 configured as RXD1 and TXD1 for UART1.
6	PA13/TXD1/PWMH2	PA13_TXD1	✅	PA12 and PA13 configured as RXD1 and TXD1 for UART1.
7	PA14/RTS1/TK	PA14_RTS1	✅	PA14 and PA15 configured as RTS1 and CTS1 for UART1 flow control.
8	PA15/CTS1/TF/WKUP8	PA15_CTS1	✅	PA14 and PA15 configured as RTS1 and CTS1 for UART1 flow control.
9	PA17/TWD0/SPCK0	PA17_SDA	✅	PA17 and PA18 configured as TWD0/SDA and TWCK0/SCL for I2C interface with proper pull-ups.
70	PA18/TWCK0/A20/WKUP9	PA18_SCL	✅	PA17 and PA18 configured as TWD0/SDA and TWCK0/SCL for I2C interface with proper pull-ups.
13	PD0/A10/MCDA4	M_nCS7	✅	Port D pins configured for motor control and endstop signals.
14	PD1/A11/MCDA5	DIR8	✅	Port D pins configured for motor control and endstop signals.
15	PD2/A12/MCDA6	M_nCS8	✅	Port D pins configured for motor control and endstop signals.
16	PD3/A13/MCDA7	STEP8	✅	Port D pins configured for motor control and endstop signals.
17	PD4/A14/TXD3	MIN_ES1	✅	Port D pins configured for motor control and endstop signals.
18	PD5/A15/RXD3	MAX_ES2	✅	Port D pins configured for motor control and endstop signals.
19	PD6/A16/BA0/PWMFI2	MIN_ES2	✅	Port D pins configured for motor control and endstop signals.
20	PD7/A17/BA1/TIOA8	TACH_3	✅	Port D pins configured for motor control and endstop signals.
21	PD8/A21/NANDALE/TIOB8	TACH_2	✅	Port D pins configured for motor control and endstop signals.
22	PD9/A22/NANDCLE/TCLK8	MAX_ES3	✅	Port D pins configured for motor control and endstop signals.
32	PD10/NWR1/NBS1	MAX_ES1	✅	Port D pins configured for motor control and endstop signals.
23	PA0/CANTX0/PWML3	PA0_CANTX0	✅	PA0 configured as CANTX0 for CAN transmit.
26	PA7/TCLK2/NCS1/WKUP3	MIN_ES3	✅	PA7 configured as MIN_ES3 endstop input.
27	PA8/URXD/PWMH0/WKUP4	PA8_URXD	✅	PA8 configured as URXD for UART receive.
28	PB28/TCK/SWCLK	TCK/SWDCLK	✅	PB28 (TCK/SWCLK) and PB31 (TMS/SWDIO) correctly connected for SWD debug interface.
31	PB31/TMS/SWDIO	TMS/SWDIO	✅	PB28 (TCK/SWCLK) and PB31 (TMS/SWDIO) correctly connected for SWD debug interface.
55	PC1	LED_Y	✅	PC1 configured as general I/O for LED control (LED_Y).
59	PC2/D0/PWML0	PC2_PWML0	✅	PC2 configured for PWM function (PWML0).
60	PC3/D1/PWMH0	LED_R	✅	PC3 configured as general I/O for LED control (LED_R).
63	PC5/D3/PWMH1	DIAG1	✅	PC5 configured as general I/O for motor diagnostic signal (DIAG1).
64	PC6/D4/PWML2	DIR1	✅	PC6 configured as general I/O for motor direction control (DIR1).
65	PC7/D5/PWMH2	STEP1	✅	PC7 configured as general I/O for motor step control (STEP1).
66	PC8/D6/PWML3	PC8_PWML3	✅	PC8 configured for PWM function (PWML3).
67	PC9/D7/PWMH3	DRV_EN	✅	PC9 configured as general I/O for motor driver enable control (DRV_EN).
68	PB27/NCS3/TIOB0	PB27_TIOB0	✅	PB27 configured as timer I/O (TIOB0).
71	PA19/MCCK/PWMH1	MCCK	✅	SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors.
72	PA20/MCCDA/PWML2	MCCDA	✅	SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors.
79	PA24/MCDA3/PCK1/AD6	MCDA3	✅	SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors.
80	PA23/MCDA2/TCLK4/AD5	MCDA2	✅	SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors.
81	PA22/MCDA1/TCLK3/AD4	MCDA1	✅	SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors.
107	PA21/MCDA0/PWML0	MCDA0	✅	SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors.
76	PB15/CANRX1/PWMH3/DAC0/WKUP12	Fan3	✅	PB15 and PB16 configured as DAC outputs for fan control.
77	PB16/TCLK5/PWML0/DAC1	Fan4	✅	PB15 and PB16 configured as DAC outputs for fan control.
78	PA16/SPCK1/TD/AD7	PA16	✅	PA16 configured as general I/O.
82	PA6/TIOB2/NCS0/AD3	TC_nCS3	✅	PA2-PA6 configured for motor control chip selects and analog inputs.
83	PA4/TCLK1/NWAIT/AD2	M_nCS1	✅	PA2-PA6 configured for motor control chip selects and analog inputs.
84	PA3/TIOB1/PWMFI1/AD1/WKUP1	PA3_AD2	✅	PA2-PA6 configured for motor control chip selects and analog inputs.
85	PA2/TIOA1/NANDRDY/AD0	TC_nCS4	✅	PA2-PA6 configured for motor control chip selects and analog inputs.
86	PB12/TWD1/PWMH0/AD8	PB12_AD8	✅	PB12 and PB13 configured as ADC inputs and I2C alternate function.
87	PB13/TWCK1/PWMH1/AD9	PB13_AD9	✅	PB12 and PB13 configured as ADC inputs and I2C alternate function.
88	PB17/RF/PWML1/AD10	TC_nCS5	✅	PB17 configured as TC_nCS5 chip select output.
89	PB18/RD/PWML2/AD11	THERM_AN2	✅	PB18, PB19, PB20 configured as ADC inputs for thermistor readings.
90	PB19/RK/PWML3/AD12	THERM_AN1	✅	PB18, PB19, PB20 configured as ADC inputs for thermistor readings.
91	PB20/TXD2/SPI0_NPCS1/AD13	THERM_AN3	✅	PB18, PB19, PB20 configured as ADC inputs for thermistor readings.
92	PB21/RXD2/SPI0_NPCS2/AD14/WKUP13	SPIFLASH_CS	✅	PB21 configured as SPI flash chip select.
93	PC11/D9/ERX2	DIAG2	✅	Port C pins 11-17 configured for motor control and Ethernet alternate functions.
94	PC12/D10/ERX3	DIR2	✅	Port C pins 11-17 configured for motor control and Ethernet alternate functions.
95	PC13/D11/ECOL	STEP2	✅	Port C pins 11-17 configured for motor control and Ethernet alternate functions.
96	PC14/D12/ERXCK	M_nCS2	✅	Port C pins 11-17 configured for motor control and Ethernet alternate functions.
97	PC15/D13/ETX2	DIAG3	✅	Port C pins 11-17 configured for motor control and Ethernet alternate functions.
98	PC16/D14/ETX3	DIR3	✅	Port C pins 11-17 configured for motor control and Ethernet alternate functions.
99	PC17/D15/ETXER	STEP3	✅	Port C pins 11-17 configured for motor control and Ethernet alternate functions.
100	PC18/NWR0/NWE/PWMH6	M_nCS3	✅	PC18 and PC19 configured for motor control chip selects and diagnostics.
101	PC19/NANDOE/PWMH5	DIAG4	✅	PC18 and PC19 configured for motor control chip selects and diagnostics.
102	PC29/A8/TIOB7	TACH_4	✅	PC29 and PC30 configured for tachometer input and SPI hold signal.
103	PC30/A9/TCLK7	HOLD#	✅	PC29 and PC30 configured for tachometer input and SPI hold signal.
108	PA25/SPI0_MISO/A18	NetR83_2	✅	SPI0 interface pins (MISO, MOSI, SPCK) correctly configured with series termination resistors.
109	PA26/SPI0_MOSI/A19	NetR77_2	✅	SPI0 interface pins (MISO, MOSI, SPCK) correctly configured with series termination resistors.
110	PA27/SPI0_SPCK/A20/WKUP10	NetR82_2	✅	SPI0 interface pins (MISO, MOSI, SPCK) correctly configured with series termination resistors.
111	PA28/SPI0_NPCS0/PCK2/WKUP11	PA28_CS0	✅	SPI0 chip select pins correctly configured.
112	PA29/SPI0_NPCS1/NRD	PA29_CS	✅	SPI0 chip select pins correctly configured.
113	PB0/ETXCK/EREFCK	PB0_ETXCK	✅	Ethernet pins repurposed for motor control outputs.
114	PB1/ETXEN	PB1_ETXEN	✅	Ethernet pins repurposed for motor control outputs.
115	PB2/ETX0	PB2_ETX0	✅	Ethernet pins repurposed for motor control outputs.
116	PC4/D2/PWML1	DIR4	✅	Ethernet and Port B pins repurposed for motor control signals.
117	PC10/D8/ECRS	STEP4	✅	Ethernet and Port B pins repurposed for motor control signals.
118	PB3/ETX1	STEP5	✅	Ethernet and Port B pins repurposed for motor control signals.
119	PB4/ECRSDV/ERXDV	M_nCS6	✅	Ethernet and Port B pins repurposed for motor control signals.
120	PB5/ERX0	M_nCS5	✅	Ethernet and Port B pins repurposed for motor control signals.
121	PB6/ERX1	DIR7	✅	Ethernet and Port B pins repurposed for motor control signals.
122	PB7/ERXER	MAX_ES4	✅	Ethernet and Port B pins repurposed for motor control signals.
123	PB8/EMDC	STEP7	✅	Ethernet and Port B pins repurposed for motor control signals.
127	PB9/EMDIO	TC_nCS2	✅	Ethernet and Port B pins repurposed for motor control signals.
128	PB10/UOTGVBOF/A18	M_nCS4	✅	PB10 and PB11 configured for motor chip select and SD card detect.
129	PB11/UOTGID/A19	SDCD	✅	PB10 and PB11 configured for motor chip select and SD card detect.
130	PC0/ERASE	ERASE	✅	PC0 ERASE pin correctly configured with switch and ESD protection.
131	PC20/NANDWE/PWMH4	DIAG5	✅	Port C pins 20-24 configured for heater control outputs.
132	PC21/A0/NBS0/PWML4	Heat1	✅	Port C pins 20-24 configured for heater control outputs.
133	PC22/A1/PWML5	Heat2	✅	Port C pins 20-24 configured for heater control outputs.
134	PC23/A2/PWML6	HeatBed	✅	Port C pins 20-24 configured for heater control outputs.
135	PC24/A3/PWML7	Heat3	✅	Port C pins 20-24 configured for heater control outputs.
136	PC25/A4/TIOA6	Fan2	✅	Port C pins 25-28 configured for fan control and tachometer inputs.
137	PC26/A5/TIOB6	Fan1	✅	Port C pins 25-28 configured for fan control and tachometer inputs.
138	PC27/A6/TCLK6	TC_nCS1	✅	Port C pins 25-28 configured for fan control and tachometer inputs.
139	PC28/A7/TIOA7	TACH_1	✅	Port C pins 25-28 configured for fan control and tachometer inputs.
140	PB14/CANTX1/PWMH2	MIN_ES4	✅	PB14 configured as MIN_ES4 endstop input.
141	PB22/RTS2/PCK0	DIR5	✅	Port B pins 22-25 configured for motor control signals.
142	PB23/CTS2/SPI0_NPCS3/WKUP14	DIAG6	✅	Port B pins 22-25 configured for motor control signals.
143	PB24/SCK2/NCS2	DIR6	✅	Port B pins 22-25 configured for motor control signals.
144	PB25/RTS0/TIOA0	PB25_TIOA0	✅	Port B pins 22-25 configured for motor control signals.

U11C - ATML-ATSAM3X-LQFP-144 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: ATSAM3X8EA-AU (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
10	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to internal voltage regulator output VDDOUT.
45	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to internal voltage regulator output VDDOUT.
61	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to internal voltage regulator output VDDOUT.
104	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to internal voltage regulator output VDDOUT.
124	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to internal voltage regulator output VDDOUT.
11	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO peripheral I/O supply.
62	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO peripheral I/O supply.
105	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO peripheral I/O supply.
125	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO peripheral I/O supply.
12	GND	GND	✅	GND pins correctly connected to ground plane.
58	GND	GND	✅	GND pins correctly connected to ground plane.
106	GND	GND	✅	GND pins correctly connected to ground plane.
126	GND	GND	✅	GND pins correctly connected to ground plane.
33	GNDPLL	GND	✅	GNDPLL correctly connected to ground for PLL and oscillator.
34	VDDPLL	VDDPLL	✅	VDDPLL correctly connected through ferrite bead from VDDOUT for noise isolation.
41	VDDUTMI	VDDUTMI	✅	VDDUTMI correctly connected through ferrite bead from 3.3VCC for USB interface.
44	GNDUTMI	GND	✅	GNDUTMI correctly connected to ground for USB interface.
52	VDDBU	3.3VCC	✅	VDDBU correctly connected to 3.3VCC for backup power supply.
54	GNDBU	GND	✅	GNDBU correctly connected to ground for backup supply.
56	VDDOUT	VDDOUT	✅	VDDOUT correctly connected to voltage regulator output with proper decoupling.
57	VDDIN	3.3VCC	✅	VDDIN correctly connected to 3.3VCC with proper input decoupling capacitor.
73	VDDANA	VDDANA	✅	VDDANA correctly connected through ferrite bead from 3.3VCC for analog supply.
74	GNDANA	GND	✅	GNDANA correctly connected to ground for analog supply.

FB26 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: CIS10P121AC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VDDPLL	✅	Pin 1 connects to VDDPLL, the PLL power supply input. This connection is correct.
2	2	VDDOUT	✅	Pin 2 connects to VDDOUT, the voltage regulator output. This connection is correct.

C57 - C1608JB0J106K080AB ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: C1608JB0J106K080AB (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This connection is correct.
2	2	3.3VCC	✅	Pin 2 connects to 3.3VCC, providing required input decoupling capacitance. This connection is correct.

C72 - C1608JB0J106K080AB ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: C1608JB0J106K080AB (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This connection is correct.
2	2	VDDANA	✅	Pin 2 connects to VDDANA, providing bulk decoupling capacitance. This connection is correct.

FB27 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: CIS10P121AC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pin 1 connects to 3.3VCC, the main 3.3V supply. This connection is correct.
2	2	VDDANA	✅	Pin 2 connects to VDDANA, the analog power supply for ADC and DAC. This connection is correct.

C55 - C1608JB0J106K080AB ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: C1608JB0J106K080AB (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This connection is correct.
2	2	VDDOUT	✅	Pin 2 connects to VDDOUT, providing required output decoupling capacitance. This connection is correct.

C37 - C1608JB0J106K080AB ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: C1608JB0J106K080AB (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This connection is correct.
2	2	VDDPLL	✅	Pin 2 connects to VDDPLL, providing bulk decoupling capacitance. This connection is correct.

FB28 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: CIS10P121AC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Pin 1 connects to 3.3VIO, the I/O power supply. This connection is correct.
2	2	3.3VCC	✅	Pin 2 connects to 3.3VCC, the main 3.3V supply. This connection is correct.

FB30 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: CIS10P121AC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pin 1 connects to 3.3VCC, the main 3.3V supply. This connection is correct.
2	2	VDDUTMI	✅	Pin 2 connects to VDDUTMI, the USB power supply. This connection is correct.

C53 - C1608JB0J106K080AB ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: C1608JB0J106K080AB (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This connection is correct.
2	2	VDDUTMI	✅	Pin 2 connects to VDDUTMI, providing bulk decoupling capacitance. This connection is correct.

R31 - RC1005F104CS ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: RC1005F104CS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TMS/SWDIO	✅	100K pull-up resistor correctly connected between TMS/SWDIO debug signal and 3.3VCC.
2	2	3.3VCC	✅	100K pull-up resistor correctly connected between TMS/SWDIO debug signal and 3.3VCC.

R38 - RC1005F104CS ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: RC1005F104CS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TCK/SWDCLK	✅	100K pull-up resistor correctly connected between TCK/SWDCLK debug clock signal and 3.3VCC.
2	2	3.3VCC	✅	100K pull-up resistor correctly connected between TCK/SWDCLK debug clock signal and 3.3VCC.

J4 - ARM Cortex JTAG-DEBUG Header ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: 20021121-00010C4LF (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	VTref pin correctly connected to 3.3VCC to provide target voltage reference for the debug probe.
2	2	TMS/SWDIO	✅	TMS/SWDIO signal correctly connected to microcontroller debug pin with 100K pull-up resistor R31.
3	3	GND	✅	Ground pin correctly connected to GND.
4	4	TCK/SWDCLK	✅	TCK/SWDCLK signal correctly connected to microcontroller debug clock pin with 100K pull-up resistor R38.
5	5	GND	✅	Ground pin correctly connected to GND.
6	6	TDO/SWO	✅	TDO/SWO signal correctly connected to microcontroller trace output pin.
7	7	NetJ4_7	✅	Pin intentionally left unconnected as key pin per standard ARM debug connector convention.
8	8	TDI	✅	TDI signal correctly connected to microcontroller debug data input pin with 100K pull-up resistor R37.
9	9	GND	✅	Ground pin correctly connected to GND.
10	10	RESET	✅	Reset signal correctly connected to system reset net.

R37 - RC1005F104CS ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: RC1005F104CS (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TDI	✅	100K pull-up resistor correctly connected between TDI debug signal and 3.3VCC.
2	2	3.3VCC	✅	100K pull-up resistor correctly connected between TDI debug signal and 3.3VCC.

S2 - KMR741NG ULC LFS ❌

DRCY flagged 1 potential issues in this component.

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: KMR741NG ULC LFS (MPN) — inferred by DRCY

Pin Designator	Net	Correct?	Analysis
2	NetS2_2	❌	Pins 2 and 4 are connected to page-local nets NetS2_2 and NetS2_4 respectively, which have no other connections, leaving these pins floating. Without the component datasheet to verify the internal pinout, this configuration is uncertain and potentially incorrect. Best practice is to explicitly connect pin 2 to 3.3VCC (same as pin 1) and pin 4 to ERASE (same as pin 3) to ensure proper switch operation regardless of the actual internal pinout. Pin 2 is connected to net NetS2_2 (from schematic) Pin 4 is connected to net NetS2_4 (from schematic) NetS2_2 and NetS2_4 are page-local nets with no other connections on this page or any other page (from whole-design connectivity for NetS2_2) The component is described as 'Tactile Switch SPST-NO Top Actuated Surface Mount', indicating a single-pole single-throw normally-open switch (from schematic) In typical 4-pin tactile switches, pins are arranged in two pairs where each pair is internally connected, with two common configurations: pins 1-2 as one terminal and 3-4 as the other, or pins 1-4 as one terminal and 2-3 as the other (reasoning) If the switch pinout is 1-2 / 3-4 (most common for KMR741 series), the current configuration would work because pin 2 is internally connected to pin 1 (3.3VCC) and pin 4 is internally connected to pin 3 (ERASE), making the floating nets functionally acceptable (reasoning) If the switch pinout is 1-4 / 2-3 (alternative configuration), the current configuration would not work because pressing the button would connect pin 1 (3.3VCC) to pin 2 (floating NetS2_2) and pin 3 (ERASE) to pin 4 (floating NetS2_4), preventing ERASE from being pulled high (reasoning) Without the component datasheet to verify the actual pinout, there is uncertainty about whether the current configuration will function correctly (reasoning) Best practice for 4-pin tactile switches is to explicitly connect both pins of each terminal pair to ensure proper operation regardless of the internal pinout: pin 2 should be connected to 3.3VCC (same as pin 1) and pin 4 should be connected to ERASE (same as pin 3) (reasoning) Explicitly connecting all four pins would guarantee functionality with either possible pinout configuration and eliminate any ambiguity (reasoning)
4	NetS2_4	❌	Pins 2 and 4 are connected to page-local nets NetS2_2 and NetS2_4 respectively, which have no other connections, leaving these pins floating. Without the component datasheet to verify the internal pinout, this configuration is uncertain and potentially incorrect. Best practice is to explicitly connect pin 2 to 3.3VCC (same as pin 1) and pin 4 to ERASE (same as pin 3) to ensure proper switch operation regardless of the actual internal pinout. Pin 2 is connected to net NetS2_2 (from schematic) Pin 4 is connected to net NetS2_4 (from schematic) NetS2_2 and NetS2_4 are page-local nets with no other connections on this page or any other page (from whole-design connectivity for NetS2_2) The component is described as 'Tactile Switch SPST-NO Top Actuated Surface Mount', indicating a single-pole single-throw normally-open switch (from schematic) In typical 4-pin tactile switches, pins are arranged in two pairs where each pair is internally connected, with two common configurations: pins 1-2 as one terminal and 3-4 as the other, or pins 1-4 as one terminal and 2-3 as the other (reasoning) If the switch pinout is 1-2 / 3-4 (most common for KMR741 series), the current configuration would work because pin 2 is internally connected to pin 1 (3.3VCC) and pin 4 is internally connected to pin 3 (ERASE), making the floating nets functionally acceptable (reasoning) If the switch pinout is 1-4 / 2-3 (alternative configuration), the current configuration would not work because pressing the button would connect pin 1 (3.3VCC) to pin 2 (floating NetS2_2) and pin 3 (ERASE) to pin 4 (floating NetS2_4), preventing ERASE from being pulled high (reasoning) Without the component datasheet to verify the actual pinout, there is uncertainty about whether the current configuration will function correctly (reasoning) Best practice for 4-pin tactile switches is to explicitly connect both pins of each terminal pair to ensure proper operation regardless of the internal pinout: pin 2 should be connected to 3.3VCC (same as pin 1) and pin 4 should be connected to ERASE (same as pin 3) (reasoning) Explicitly connecting all four pins would guarantee functionality with either possible pinout configuration and eliminate any ambiguity (reasoning)
1	3.3VCC	✅	Pin 1 connects to 3.3VCC and provides the high voltage source for the erase function when the button is pressed. This connection is correct.
3	ERASE	✅	Pin 3 connects to the ERASE net, which is pulled high through the switch when the button is pressed. This connection is correct for the erase button function.

D1 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connects to GND and provides the reference for ESD clamping.
C	C	ERASE	✅	Cathode connects to ERASE and provides ESD protection for the erase pin.

S1 - 1571610-2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Part Number: 1571610-2 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	RESET	✅	Pin P connects to RESET net and serves as the active pole of the reset button. When pressed, it pulls RESET to ground through the other pins.
2	S	GND	✅	Pins S, 3, and 4 all connect to GND and provide the ground reference for the switch. Multiple ground pins provide mechanical stability.
3	3	GND	✅	Pins S, 3, and 4 all connect to GND and provide the ground reference for the switch. Multiple ground pins provide mechanical stability.
4	4	GND	✅	Pins S, 3, and 4 all connect to GND and provide the ground reference for the switch. Multiple ground pins provide mechanical stability.

C40 - GRM155R71H103JA88D ✅

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Part Number: GRM155R71H103JA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESET	✅	Pin 1 connects to RESET and provides filtering for the reset signal.
2	2	3.3VIO	✅	Pin 2 connects to 3.3VIO and forms a filter network with the assumed pull-up resistor on RESET.

U12 - AT25SF161-SSHD-T ✅

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Part Number: AT25SF161-SSHD-T (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPIFLASH_CS	✅	CS# (Chip Select) is connected to SPIFLASH_CS through a diode OR configuration with CS_M1BUS via D77, allowing the flash to be selected when CS_M1BUS goes low.
2	SO	MISO_M1BUS	✅	SO (Serial Output) is correctly connected to MISO_M1BUS, the SPI Master In Slave Out line for the M1 bus.
3	WP#	WP#	✅	WP# (Write Protect) is correctly pulled high to 3.3VCC through R85 (10K), disabling write protection by default.
4	GND	GND	✅	GND is correctly connected to the ground net.
5	SI/IO0	MOSI_M1BUS	✅	SI/IO0 (Serial Input) is correctly connected to MOSI_M1BUS, the SPI Master Out Slave In line for the M1 bus.
6	SCK	SCLK_M1BUS	✅	SCK (Serial Clock) is correctly connected to SCLK_M1BUS, the SPI clock line for the M1 bus.
7	HOLD#	HOLD#	✅	HOLD# is connected to microcontroller GPIO PC30 (U11A pin 103) for active firmware control. While the design relies on the microcontroller's internal pull-up resistors, an external pull-up would provide more robust operation and consistency with the WP# design approach.
8	VCC	3.3VCC	✅	VCC is correctly connected to 3.3VCC, which is within the typical 2.7V to 3.6V operating range for SPI flash memories.

R85 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	WP#	✅	R85 forms a 10K pull-up resistor from WP# (pin 1) to 3.3VCC (pin 2), correctly disabling write protection by default on the SPI flash.
2	2	3.3VCC	✅	R85 forms a 10K pull-up resistor from WP# (pin 1) to 3.3VCC (pin 2), correctly disabling write protection by default on the SPI flash.

R3 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_TCBUS	✅	Series termination resistor correctly positioned between clock buffer output Y1 and SCLK_TCBUS with appropriate 47Ω value for impedance matching and signal integrity.
2	2	NetR3_2	✅	Series termination resistor correctly positioned between clock buffer output Y1 and SCLK_TCBUS with appropriate 47Ω value for impedance matching and signal integrity.

R4 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA27_SCLK	✅	Series termination resistor correctly positioned between clock buffer output Y2 and PA27_SCLK with appropriate 47Ω value for impedance matching and signal integrity.
2	2	NetR4_2	✅	Series termination resistor correctly positioned between clock buffer output Y2 and PA27_SCLK with appropriate 47Ω value for impedance matching and signal integrity.

R13 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_M1BUS	✅	Series termination resistor correctly positioned between clock buffer output Y3 and SCLK_M1BUS with appropriate 47Ω value for impedance matching and signal integrity.
2	2	NetR13_2	✅	Series termination resistor correctly positioned between clock buffer output Y3 and SCLK_M1BUS with appropriate 47Ω value for impedance matching and signal integrity.

R32 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_M2BUS	✅	Series termination resistor correctly positioned between clock buffer output Y4 and SCLK_M2BUS with appropriate 47Ω value for impedance matching and signal integrity.
2	2	NetR32_2	✅	Series termination resistor correctly positioned between clock buffer output Y4 and SCLK_M2BUS with appropriate 47Ω value for impedance matching and signal integrity.

C64 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Filter capacitor correctly connected between clock buffer input (NetC64_2) and GND. Value is marked TBD and needs to be determined based on clock frequency and filtering requirements.
2	2	NetC64_2	✅	Filter capacitor correctly connected between clock buffer input (NetC64_2) and GND. Value is marked TBD and needs to be determined based on clock frequency and filtering requirements.

U14 - 74AVC9112 ✅

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Part Number: 74AVC9112GTX (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	Vcc	3.3VCC	✅	Vcc power pin correctly connected to 3.3VCC supply.
2	A	NetC64_2	✅	Input pin A receives SPI clock from microcontroller PA27 through series resistor R82, with C64 providing input filtering.
3	nOE	GND	✅	Output enable pin nOE correctly tied to GND for always-enabled operation.
4	GND	GND	✅	Ground pin correctly connected to GND.
5	Y1	NetR3_2	✅	Output Y1 correctly drives SCLK_TCBUS through series termination resistor R3.
6	Y2	NetR4_2	✅	Output Y2 correctly drives PA27_SCLK through series termination resistor R4, providing a buffered clock signal to test point TP77.
7	Y3	NetR13_2	✅	Output Y3 correctly drives SCLK_M1BUS through series termination resistor R13.
8	Y4	NetR32_2	✅	Output Y4 correctly drives SCLK_M2BUS through series termination resistor R32.
23	NC		✅	No-connect pin correctly left unconnected.

U17 - SN74LVC125A ✅

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Part Number: SN74LVC125ARGYR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
2	A1	PA26_MOSI_D	✅	All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses.
5	A2	PA26_MOSI_D	✅	All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses.
9	A3	PA26_MOSI_D	✅	All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses.
12	A4	PA26_MOSI_D	✅	All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses.
3	Y1	NetR84_2	✅	Output Y1 correctly drives MOSI_TCBUS through 47Ω series resistor R84 for impedance matching and signal integrity.
6	Y2	NetR59_2	✅	Output Y2 correctly drives MOSI_M1BUS through 47Ω series resistor R59 for impedance matching and signal integrity.
7	GND	GND	✅	Ground pin correctly connected to GND.
8	Y3	NetR89_2	✅	Output Y3 correctly drives MOSI_M2BUS through 47Ω series resistor R89 for impedance matching and signal integrity.
11	Y4	NetR93_2	✅	Buffer 4 output Y4 (pin 11) correctly drives test point TP75 through series resistor R93. Output enable nOE4 (pin 13) is correctly tied to GND to enable the buffer. This provides a buffered monitoring point for the MOSI signal.
13	nOE4	GND	✅	Buffer 4 output Y4 (pin 11) correctly drives test point TP75 through series resistor R93. Output enable nOE4 (pin 13) is correctly tied to GND to enable the buffer. This provides a buffered monitoring point for the MOSI signal.
14	Vcc	3.3VCC	✅	Power supply pin correctly connected to 3.3VCC with local decoupling capacitor C91.
15	PAD	GND	✅	Thermal pad correctly connected to GND for heat dissipation and electrical grounding.
23	NC		✅	Pin marked as NC (no connect) in component definition. This is likely a component library artifact as a 14-VQFN package would not have a pin 23.

R93 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA26_MOSI	✅	Series resistor correctly placed between U17 buffer output Y4 and test point TP75. Pin 2 connects to buffer output via NetR93_2, pin 1 connects to PA26_MOSI which drives the test point. 47Ω provides appropriate impedance matching.
2	2	NetR93_2	✅	Series resistor correctly placed between U17 buffer output Y4 and test point TP75. Pin 2 connects to buffer output via NetR93_2, pin 1 connects to PA26_MOSI which drives the test point. 47Ω provides appropriate impedance matching.

R84 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_TCBUS	✅	Series resistor correctly placed between U17 output Y1 and MOSI_TCBUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals.
2	2	NetR84_2	✅	Series resistor correctly placed between U17 output Y1 and MOSI_TCBUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals.

R59 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M1BUS	✅	Series resistor correctly placed between U17 output Y2 and MOSI_M1BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals.
2	2	NetR59_2	✅	Series resistor correctly placed between U17 output Y2 and MOSI_M1BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals.

R89 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M2BUS	✅	Series resistor correctly placed between U17 output Y3 and MOSI_M2BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals.
2	2	NetR89_2	✅	Series resistor correctly placed between U17 output Y3 and MOSI_M2BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals.

C83 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_TCBUS	✅	Capacitor correctly placed between MOSI_TCBUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements.
2	2	GND	✅	Capacitor correctly placed between MOSI_TCBUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements.

C88 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M1BUS	✅	Capacitor correctly placed between MOSI_M1BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements.
2	2	GND	✅	Capacitor correctly placed between MOSI_M1BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements.

C89 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M2BUS	✅	Capacitor correctly placed between MOSI_M2BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements.
2	2	GND	✅	Capacitor correctly placed between MOSI_M2BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements.

C90 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA26_MOSI	✅	Capacitor correctly placed between PA26_MOSI and GND for signal conditioning at test point TP75. Value is marked TBD and needs to be determined based on signal integrity requirements.
2	2	GND	✅	Capacitor correctly placed between PA26_MOSI and GND for signal conditioning at test point TP75. Value is marked TBD and needs to be determined based on signal integrity requirements.

U16 - SN74LVC125A ✅

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Part Number: SN74LVC125ARGYR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	nOE1	CS_TCBUS	✅	Active-low output enable for buffer 1, correctly connected to CS_TCBUS to enable the buffer when the thermocouple bus is selected.
2	A1	MISO_TCBUS	✅	Input A1 correctly connected to MISO_TCBUS from the thermocouple SPI bus.
3	Y1	NetR94_2	✅	Output Y1 correctly connected to NetR94_2, which is the common multiplexed MISO output node.
4	nOE2	CS_M1BUS	✅	Active-low output enable for buffer 2, correctly connected to CS_M1BUS to enable the buffer when motor bus 1 is selected.
5	A2	MISO_M1BUS	✅	Input A2 correctly connected to MISO_M1BUS from motor bus 1 SPI devices.
6	Y2	NetR94_2	✅	Output Y2 correctly connected to NetR94_2, sharing the multiplexed MISO output with Y1 and Y3.
7	GND	GND	✅	Ground pin correctly connected to GND.
8	Y3	NetR94_2	✅	Output Y3 correctly connected to NetR94_2, completing the 3-to-1 MISO multiplexer.
9	A3	MISO_M2BUS	✅	Input A3 correctly connected to MISO_M2BUS from motor bus 2 SPI devices.
10	nOE3	CS_M2BUS	✅	Active-low output enable for buffer 3, correctly connected to CS_M2BUS to enable the buffer when motor bus 2 is selected.
11	Y4	NetU16_11	✅	Output Y4 is intentionally left unconnected as buffer 4 is unused in this design.
12	A4	GND	✅	Input A4 correctly tied to GND as buffer 4 is unused.
13	nOE4	GND	✅	Output enable nOE4 tied to GND, keeping buffer 4 always enabled even though it is unused.
14	Vcc	3.3VCC	✅	Power supply pin correctly connected to 3.3VCC.
15	PAD	GND	✅	Thermal pad correctly connected to GND.
23	NC		✅	No-connect pin correctly left unconnected per design intent.

R60 - R0402TBD ✅

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Part Number: DNI-R0402TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC79_1	✅	Connected to NetC79_1 as part of an optional RC filter, but marked DNI so not populated.
2	2	PA25_MISO	✅	Connected to PA25_MISO, would provide series resistance for optional RC filtering if populated.

R66 - 10k 1% 0402 ✅

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND to provide pull-down function.
2	2	PA25_MISO	✅	Connected to PA25_MISO to pull the MISO line low when all buffers are disabled.

C74 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MISO_TCBUS	✅	Connected to MISO_TCBUS to provide high-frequency noise filtering.
2	2	GND	✅	Connected to GND to complete the bypass capacitor function.

C79 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC79_1	✅	Connected to NetC79_1 as part of an optional RC filter with R60.
2	2	GND	✅	Connected to GND to complete the optional RC filter function.

R94 - 47R 1% 0402 ✅

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Part Number: CRCW040247R0FKEDC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA25_MISO	✅	Connected to PA25_MISO, the microcontroller's SPI MISO input.
2	2	NetR94_2	✅	Connected to NetR94_2, the common output node of the MISO multiplexer buffers.

C75 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MISO_M1BUS	✅	Connected to MISO_M1BUS to provide high-frequency noise filtering.
2	2	GND	✅	Connected to GND to complete the bypass capacitor function.

C87 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MISO_M2BUS	✅	Connected to MISO_M2BUS to provide high-frequency noise filtering.
2	2	GND	✅	Connected to GND to complete the bypass capacitor function.

R83 - CRCW040224R0FKED ✅

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA25_MISO	✅	Series termination resistor on SPI MISO path between buffered MISO sources and microcontroller PA25 input. The 24Ω resistor provides source termination and, combined with upstream R94 (47Ω), creates 71Ω total series resistance for isolation and current limiting.
2	2	NetR83_2	✅	Series termination resistor on SPI MISO path between buffered MISO sources and microcontroller PA25 input. The 24Ω resistor provides source termination and, combined with upstream R94 (47Ω), creates 71Ω total series resistance for isolation and current limiting.

C104 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor connected between SCLK_M1BUS and ground for signal integrity, but value is marked TBD and needs to be determined.
2	2	SCLK_M1BUS	✅	Capacitor connected between SCLK_M1BUS and ground for signal integrity, but value is marked TBD and needs to be determined.

C101 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor connected between SCLK_TCBUS and ground for signal integrity, but value is marked TBD and needs to be determined.
2	2	SCLK_TCBUS	✅	Capacitor connected between SCLK_TCBUS and ground for signal integrity, but value is marked TBD and needs to be determined.

C102 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor connected between PA27_SCLK and ground for signal integrity, but value is marked TBD and needs to be determined.
2	2	PA27_SCLK	✅	Capacitor connected between PA27_SCLK and ground for signal integrity, but value is marked TBD and needs to be determined.

R82 - CRCW040224R0FKED ✅

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC64_2	✅	24Ω series resistor correctly placed between microcontroller SCLK output and clock buffer input for signal integrity.
2	2	NetR82_2	✅	24Ω series resistor correctly placed between microcontroller SCLK output and clock buffer input for signal integrity.

R77 - CRCW040224R0FKED ✅

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Part Number: RC0402FR-0724RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA26_MOSI_D	✅	24Ω series resistor correctly placed between microcontroller MOSI output and buffer inputs for signal integrity.
2	2	NetR77_2	✅	24Ω series resistor correctly placed between microcontroller MOSI output and buffer inputs for signal integrity.

C85 - C0402_TBD ✅

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Part Number: TBD (IPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor connected between SCLK_M2BUS and ground for signal integrity, but value is marked TBD and needs to be determined.
2	2	SCLK_M2BUS	✅	Capacitor connected between SCLK_M2BUS and ground for signal integrity, but value is marked TBD and needs to be determined.

D30 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS2 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS2.
K	K	TC_nCS2	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS2 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS2.

D62 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS5 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS5.
K	K	TC_nCS5	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS5 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS5.

R95 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor that pulls CS_TCBUS to 3.3VCC. When any thermocouple chip select (TC_nCS1-5) is active low, the corresponding diode conducts and pulls CS_TCBUS low through this resistor, disabling the buffer outputs.
2	2	CS_TCBUS	✅	Pull-up resistor that pulls CS_TCBUS to 3.3VCC. When any thermocouple chip select (TC_nCS1-5) is active low, the corresponding diode conducts and pulls CS_TCBUS low through this resistor, disabling the buffer outputs.

D61 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS1 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS1.
K	K	TC_nCS1	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS1 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS1.

D5 - BAT54WX ✅

DRCY found no issues in this component 🎉

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS4 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS4.
K	K	TC_nCS4	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS4 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS4.

D31 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS3 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS3.
K	K	TC_nCS3	✅	Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS3 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS3.

D77 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when SPIFLASH_CS is asserted by microcontroller pin PB20, enabling MISO buffer for SPI flash access.
K	K	SPIFLASH_CS	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when SPIFLASH_CS is asserted by microcontroller pin PB20, enabling MISO buffer for SPI flash access.

D76 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS4 is asserted, enabling MISO buffer for motor bus 1.
K	K	M_nCS4	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS4 is asserted, enabling MISO buffer for motor bus 1.

D75 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS3 is asserted, enabling MISO buffer for motor bus 1.
K	K	M_nCS3	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS3 is asserted, enabling MISO buffer for motor bus 1.

D70 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS1 is asserted, enabling MISO buffer for motor bus 1.
K	K	M_nCS1	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS1 is asserted, enabling MISO buffer for motor bus 1.

D74 - BAT54WX ✅

DRCY found no issues in this component 🎉

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS2 is asserted, enabling MISO buffer for motor bus 1.
K	K	M_nCS2	✅	Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS2 is asserted, enabling MISO buffer for motor bus 1.

R100 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly pulls CS_M1BUS high when no chip selects are active, disabling the MISO buffer. The 10kΩ value provides appropriate pull-up strength.
2	2	CS_M1BUS	✅	Pull-up resistor correctly pulls CS_M1BUS high when no chip selects are active, disabling the MISO buffer. The 10kΩ value provides appropriate pull-up strength.

D41 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct.
K	K	M_nCS7	✅	Cathode connected to M_nCS7 chip select line. This connection is correct.

D63 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct.
K	K	M_nCS8	✅	Cathode connected to M_nCS8 chip select line. This connection is correct.

D40 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct.
K	K	M_nCS6	✅	Cathode connected to M_nCS6 chip select line. This connection is correct.

D60 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct.
K	K	M_nCS5	✅	Cathode connected to M_nCS5 chip select line. This connection is correct.

R97 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Connected to 3.3VCC power supply. This connection is correct.
2	2	CS_M2BUS	✅	Connected to CS_M2BUS to provide pull-up for wired-OR chip select logic. This connection is correct.

R64 - RC0402FR-0710KP ✅

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SDCD	✅	Pull-up resistor correctly provides 10kΩ pull-up on card detect signal SDCD to 3.3V.
2	2	3.3VCC	✅	Pull-up resistor correctly provides 10kΩ pull-up on card detect signal SDCD to 3.3V.

R65 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly provides 10kΩ pull-up on CMD line to 3.3V as required by SD specification.
2	2	MCCDA	✅	Pull-up resistor correctly provides 10kΩ pull-up on CMD line to 3.3V as required by SD specification.

R67 - RC0402FR-0710KP ✅

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCDA3	✅	Pull-up resistor correctly provides 10kΩ pull-up on DAT3 line to 3.3V as required by SD specification.
2	2	3.3VCC	✅	Pull-up resistor correctly provides 10kΩ pull-up on DAT3 line to 3.3V as required by SD specification.

R68 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCDA2	✅	Pull-up resistor correctly provides 10kΩ pull-up on DAT2 line to 3.3V as required by SD specification.
2	2	3.3VCC	✅	Pull-up resistor correctly provides 10kΩ pull-up on DAT2 line to 3.3V as required by SD specification.

R69 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly provides 10kΩ pull-up on MCDA1 net to 3.3V. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1, indicating a potential swap at the connector level.
2	2	MCDA1	✅	Pull-up resistor correctly provides 10kΩ pull-up on MCDA1 net to 3.3V. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1, indicating a potential swap at the connector level.

R70 - RC0402FR-0710KP ✅

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Part Number: RC0402FR-0710KP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly provides 10kΩ pull-up on MCDA0 net to 3.3V. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0, indicating a potential swap at the connector level.
2	2	MCDA0	✅	Pull-up resistor correctly provides 10kΩ pull-up on MCDA0 net to 3.3V. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0, indicating a potential swap at the connector level.

D42 - ESD9X3.3ST5G ✅

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides ESD protection on card detect signal with cathode to signal and anode to ground.
C	C	SDCD	✅	TVS diode correctly provides ESD protection on card detect signal with cathode to signal and anode to ground.

D64 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides ESD protection on MCDA1 net with cathode to signal and anode to ground. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1.
C	C	MCDA1	✅	TVS diode correctly provides ESD protection on MCDA1 net with cathode to signal and anode to ground. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1.

D65 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides ESD protection on MCDA0 net with cathode to signal and anode to ground. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0.
C	C	MCDA0	✅	TVS diode correctly provides ESD protection on MCDA0 net with cathode to signal and anode to ground. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0.

D66 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides ESD protection on CMD line with cathode to signal and anode to ground.
C	C	MCCDA	✅	TVS diode correctly provides ESD protection on CMD line with cathode to signal and anode to ground.

D67 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides ESD protection on CLK line with cathode to signal and anode to ground.
C	C	MCCK	✅	TVS diode correctly provides ESD protection on CLK line with cathode to signal and anode to ground.

D68 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides ESD protection on DAT3 line with cathode to signal and anode to ground.
C	C	MCDA3	✅	TVS diode correctly provides ESD protection on DAT3 line with cathode to signal and anode to ground.

D69 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly provides ESD protection on DAT2 line with cathode to signal and anode to ground.
C	C	MCDA2	✅	TVS diode correctly provides ESD protection on DAT2 line with cathode to signal and anode to ground.

C70 - C1608JB0J106K080AB ✅

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Part Number: C1608JB0J106K080AB (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Decoupling capacitor correctly provides local 10µF filtering for the microSD card power supply.
2	2	3.3VCC	✅	Decoupling capacitor correctly provides local 10µF filtering for the microSD card power supply.

J18 - 0475710001 ✅

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Part Number: 0475710001 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	MCDA2	✅	DAT2 data line correctly connected to MCDA2 on the microcontroller.
2	CD/DAT3	MCDA3	✅	CD/DAT3 data line correctly connected to MCDA3 on the microcontroller.
3	CMD	MCCDA	✅	CMD command line correctly connected to MCCDA on the microcontroller with appropriate pull-up resistor.
4	VDD	3.3VCC	✅	VDD power supply correctly connected to 3.3VCC with appropriate decoupling.
5	CLK	MCCK	✅	CLK clock line correctly connected to MCCK on the microcontroller.
6	VSS	GND	✅	VSS ground correctly connected to GND.
7	DAT1	MCDA0	✅	DAT0 and DAT1 data lines are correctly connected electrically, but the component symbol has swapped pin labels that do not match the standard microSD pinout.
8	DAT0	MCDA1	✅	DAT0 and DAT1 data lines are correctly connected electrically, but the component symbol has swapped pin labels that do not match the standard microSD pinout.
9	SH	GND	✅	Shield pins correctly connected to GND for EMI shielding.
10	SH	GND	✅	Shield pins correctly connected to GND for EMI shielding.
11	SH	GND	✅	Shield pins correctly connected to GND for EMI shielding.
12	CD	SDCD	✅	Card detect switch correctly connected to SDCD with appropriate pull-up resistor.
13	CD/POL	GND	✅	Card detect polarity pin correctly connected to GND for active-low detection.

D25 - 5988140107F ✅

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Part Number: 5988140107F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD25_A	✅	LED anode connected to current limiting resistor R36, which drives from microcontroller GPIO PC1.
C	C	GND	✅	LED cathode correctly connected to ground.

R36 - RK73H1ETTP1001F ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LED_Y	✅	Connected to LED_Y net, which drives from microcontroller GPIO PC1 to control yellow LED D25.
2	2	NetD25_A	✅	Connected to yellow LED D25 anode through net NetD25_A.

R34 - RK73H1ETTP1001F ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LED_R	✅	Connected to LED_R net, which drives from microcontroller GPIO PC3 to control red LED D24.
2	2	NetD24_A	✅	Connected to red LED D24 anode through net NetD24_A.

R71 - 1k 1% 0402 ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Connected to 3.3VIO power rail to provide pull-up voltage for I2C SCL line.
2	2	PA18_SCL	✅	Connected to PA18_SCL (I2C clock line) on microcontroller pin PA18 and external connector J20 pin 21.

D24 - 5988110107F ✅

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Part Number: 5988110107F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD24_A	✅	LED anode connected to current limiting resistor R34, which drives from microcontroller GPIO PC3.
C	C	GND	✅	LED cathode correctly connected to ground.

R40 - 1k 1% 0402 ✅

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📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Connected to 3.3VIO power rail to provide pull-up voltage for I2C SDA line.
2	2	PA17_SDA	✅	Connected to PA17_SDA (I2C data line) on microcontroller pin PA17 and external connector J20 pin 22.

D72 - ESD9X3.3ST5G ✅

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode anode correctly connected to GND for ESD protection on UART TX signal.
C	C	PA9_UTXD	✅	TVS diode cathode correctly connected to PA9_UTXD signal for ESD protection on external connector.

D71 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode anode correctly connected to GND for ESD protection on NRST signal.
C	C	NRST	✅	TVS diode cathode correctly connected to NRST signal for ESD protection on external connector.

D73 - ESD9X3.3ST5G ✅

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode anode correctly connected to GND for ESD protection on UART RX signal.
C	C	PA8_URXD	✅	TVS diode cathode correctly connected to PA8_URXD signal for ESD protection on external connector.

J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

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Part Number: 302-S101 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net, providing ground reference for the serial connector.
2	2	PA9_UTXD	✅	UART transmit signal correctly connected to PA9_UTXD from MCU pin 2, with ESD protection via D72.
3	3	+5VCC	✅	5V power supply pin correctly connected to +5VCC net.
4	4	PA8_URXD	✅	UART receive signal correctly connected to PA8_URXD from MCU pin 27, with ESD protection via D73.
5	5	3.3VCC	✅	3.3V power supply pin correctly connected to 3.3VCC net.
6	6	NRST	✅	Reset signal correctly connected to NRST net with internal pull-up and ESD protection via D71.
7	7	ERASE	✅	Flash erase signal correctly connected to ERASE net, allowing external flash erase functionality through tactile switch S2.
8	8	+5VCC	✅	Additional 5V power supply pin correctly connected to +5VCC net, providing redundant power connection.
9	9	PC8_PWML3	✅	PWM signal correctly connected to PC8_PWML3 from MCU pin 66, though lacks ESD protection unlike other signal pins.
10	10	GND	✅	Additional ground pin correctly connected to GND net, providing redundant ground connection.

R109 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA14_RTS1	✅	100 ohm series resistor correctly placed between microcontroller UART RTS1 signal and connector for signal protection and integrity.
2	2	NetJ12_10	✅	100 ohm series resistor correctly placed between microcontroller UART RTS1 signal and connector for signal protection and integrity.

J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

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Part Number: 302-S101 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	+5VCC power supply pin correctly connected to the +5VCC rail to provide power to external devices connected to this serial connector.
2	2	GND	✅	Ground pin correctly connected to the GND rail.
3	3	NetJ12_3	✅	Connected to microcontroller pin PC2_PWML0 through 100 ohm series resistor R137 for signal protection.
4	4	NetJ12_4	✅	Connected to microcontroller CAN receive pin PA1_CANRX0 through 100 ohm series resistor R136. The 100 ohm value is higher than typical for CAN signals but may be intentional for connector protection.
5	5	NetJ12_5	✅	Connected to microcontroller pin PA16 through 100 ohm series resistor R135 for signal protection.
6	6	NetJ12_6	✅	Connected to microcontroller CAN transmit pin PA0_CANTX0 through 100 ohm series resistor R134. The 100 ohm value is higher than typical for CAN signals but may be intentional for connector protection.
7	7	NetJ12_7	✅	Connected to microcontroller UART receive pin PA12_RXD1 through 100 ohm series resistor R133 for signal protection and integrity.
8	8	NetJ12_8	✅	Connected to microcontroller UART clear-to-send pin PA15_CTS1 through 100 ohm series resistor R120 for signal protection and integrity.
9	9	NetJ12_9	✅	Connected to microcontroller UART transmit pin PA13_TXD1 through 100 ohm series resistor R114 for signal protection and integrity.
10	10	NetJ12_10	✅	Connected to microcontroller UART request-to-send pin PA14_RTS1 through 100 ohm series resistor R109 for signal protection and integrity.

R137 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ12_3	✅	100 ohm series resistor correctly placed between microcontroller PWM pin PC2_PWML0 and connector for signal protection.
2	2	PC2_PWML0	✅	100 ohm series resistor correctly placed between microcontroller PWM pin PC2_PWML0 and connector for signal protection.

R114 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ12_9	✅	100 ohm series resistor correctly placed between microcontroller UART TXD1 signal and connector for signal protection and integrity.
2	2	PA13_TXD1	✅	100 ohm series resistor correctly placed between microcontroller UART TXD1 signal and connector for signal protection and integrity.

R120 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA15_CTS1	✅	100 ohm series resistor correctly placed between microcontroller UART CTS1 signal and connector for signal protection and integrity.
2	2	NetJ12_8	✅	100 ohm series resistor correctly placed between microcontroller UART CTS1 signal and connector for signal protection and integrity.

R136 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA1_CANRX0	✅	100 ohm series resistor placed between microcontroller CAN receive signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection.
2	2	NetJ12_4	✅	100 ohm series resistor placed between microcontroller CAN receive signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection.

R135 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ12_5	✅	100 ohm series resistor correctly placed between microcontroller GPIO pin PA16 and connector for signal protection.
2	2	PA16	✅	100 ohm series resistor correctly placed between microcontroller GPIO pin PA16 and connector for signal protection.

R134 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA0_CANTX0	✅	100 ohm series resistor placed between microcontroller CAN transmit signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection.
2	2	NetJ12_6	✅	100 ohm series resistor placed between microcontroller CAN transmit signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection.

R133 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ12_7	✅	100 ohm series resistor correctly placed between microcontroller UART RXD1 signal and connector for signal protection and integrity.
2	2	PA12_RXD1	✅	100 ohm series resistor correctly placed between microcontroller UART RXD1 signal and connector for signal protection and integrity.

R141 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ13_7	✅	Series resistor connecting microcontroller SPI0_NPCS1 chip select signal to connector J13 pin 7.
2	2	PA29_CS	✅	Series resistor connecting microcontroller SPI0_NPCS1 chip select signal to connector J13 pin 7.

R140 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PB27_TIOB0	✅	Series resistor connecting microcontroller timer output PB27_TIOB0 to connector J13 pin 8.
2	2	NetJ13_8	✅	Series resistor connecting microcontroller timer output PB27_TIOB0 to connector J13 pin 8.

J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

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Part Number: 302-S101 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Provides +5VCC power to external device connected to this connector.
2	2	GND	✅	Ground reference for the connector.
3	3	NetJ13_3	✅	Connected to microcontroller reset signal NRST through 100Ω series resistor R145.
4	4	NetJ13_4	✅	Connected to microcontroller timer output PB25_TIOA0 through 100Ω series resistor R144.
5	5	NetJ13_5	✅	Connected to SPI0 MOSI signal PA26_MOSI through 100Ω series resistor R143.
6	6	NetJ13_6	✅	Connected to microcontroller pin PA3_AD2 through 100Ω series resistor R142.
7	7	NetJ13_7	✅	Connected to SPI0 chip select signal PA29_CS through 100Ω series resistor R141.
8	8	NetJ13_8	✅	Connected to microcontroller timer output PB27_TIOB0 through 100Ω series resistor R140.
9	9	NetJ13_9	✅	Connected to SPI0 clock signal PA27_SCLK through 100Ω series resistor R139.
10	10	NetJ13_10	✅	Connected to SPI0 MISO signal PA25_MISO through 100Ω series resistor R138.

R145 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ13_3	✅	Series resistor connecting microcontroller reset signal NRST to connector J13 pin 3.
2	2	NRST	✅	Series resistor connecting microcontroller reset signal NRST to connector J13 pin 3.

R139 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ13_9	✅	Series resistor connecting microcontroller SPI0_SPCK signal to connector J13 pin 9.
2	2	PA27_SCLK	✅	Series resistor connecting microcontroller SPI0_SPCK signal to connector J13 pin 9.

R143 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ13_5	✅	Series resistor connecting microcontroller SPI0_MOSI signal to connector J13 pin 5.
2	2	PA26_MOSI	✅	Series resistor connecting microcontroller SPI0_MOSI signal to connector J13 pin 5.

R144 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PB25_TIOA0	✅	Series resistor connecting microcontroller timer output PB25_TIOA0 to connector J13 pin 4.
2	2	NetJ13_4	✅	Series resistor connecting microcontroller timer output PB25_TIOA0 to connector J13 pin 4.

R142 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA3_AD2	✅	Series resistor connecting microcontroller pin PA3_AD2 to connector J13 pin 6.
2	2	NetJ13_6	✅	Series resistor connecting microcontroller pin PA3_AD2 to connector J13 pin 6.

R138 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA25_MISO	✅	Series resistor connecting microcontroller SPI0_MISO signal to connector J13 pin 10.
2	2	NetJ13_10	✅	Series resistor connecting microcontroller SPI0_MISO signal to connector J13 pin 10.

J20 - Header 12X2 ❌

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Part Number: 2213S-24G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
5	5	NetJ20_5	❌	These header pins are connected to page-local nets with no other connections and are not marked as no-connects. Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic) Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5) These pins are not marked as no-connects in the schematic (from schematic) Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic) Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning) Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning) These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)
6	6	NetJ20_6	❌	These header pins are connected to page-local nets with no other connections and are not marked as no-connects. Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic) Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5) These pins are not marked as no-connects in the schematic (from schematic) Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic) Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning) Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning) These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)
7	7	NetJ20_7	❌	These header pins are connected to page-local nets with no other connections and are not marked as no-connects. Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic) Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5) These pins are not marked as no-connects in the schematic (from schematic) Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic) Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning) Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning) These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)
9	9	NetJ20_9	❌	These header pins are connected to page-local nets with no other connections and are not marked as no-connects. Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic) Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5) These pins are not marked as no-connects in the schematic (from schematic) Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic) Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning) Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning) These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)
10	10	NetJ20_10	❌	These header pins are connected to page-local nets with no other connections and are not marked as no-connects. Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic) Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5) These pins are not marked as no-connects in the schematic (from schematic) Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic) Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning) Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning) These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)
12	12	NetJ20_12	❌	These header pins are connected to page-local nets with no other connections and are not marked as no-connects. Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic) Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5) These pins are not marked as no-connects in the schematic (from schematic) Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic) Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning) Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning) These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)
1	1	PA28_CS0	✅	SPI chip select signal PA28_CS0 correctly connected to microcontroller.
2	2	PA27_SCLK	✅	SPI clock signal PA27_SCLK correctly connected to microcontroller.
3	3	PA26_MOSI	✅	SPI MOSI signal PA26_MOSI correctly connected to microcontroller.
4	4	PA25_MISO	✅	SPI MISO signal PA25_MISO correctly connected to microcontroller.
8	8	PB12_AD8	✅	ADC input PB12_AD8 correctly connected to microcontroller.
11	11	NetJ20_11	✅	These pins are intentionally left as no-connects.
13	13	NetJ20_13	✅	These pins are intentionally left as no-connects.
14	14	NetJ20_14	✅	These pins are intentionally left as no-connects.
17	17	NetJ20_17	✅	These pins are intentionally left as no-connects.
15	15	NetJ20_15	✅	Ethernet TX data signal correctly routed through series resistor and protected by varistor.
16	16	NetJ20_16	✅	Ethernet TX enable signal correctly routed through series resistor and protected by varistor.
18	18	NRST	✅	Reset signal NRST correctly connected for external reset capability.
19	19	NetJ20_19	✅	Signal routed through series resistor and protected by varistor, grouped with Ethernet signals.
20	20	NetJ20_20	✅	Ethernet TX clock signal correctly routed through series resistor and protected by varistor.
21	21	PA18_SCL	✅	I2C clock signal PA18_SCL correctly connected to microcontroller.
22	22	PA17_SDA	✅	I2C data signal PA17_SDA correctly connected to microcontroller.
23	23	GND	✅	Ground pin correctly connected.
24	24	3.3VCC	✅	3.3V power pin correctly connected.

R153 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PB0_ETXCK	✅	100 ohm series resistor between Ethernet TX clock signal and header for current limiting and impedance matching.
2	2	NetJ20_20	✅	100 ohm series resistor between Ethernet TX clock signal and header for current limiting and impedance matching.

R160 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PB1_ETXEN	✅	100 ohm series resistor between Ethernet TX enable signal and header for current limiting and impedance matching.
2	2	NetJ20_16	✅	100 ohm series resistor between Ethernet TX enable signal and header for current limiting and impedance matching.

R161 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_15	✅	100 ohm series resistor between Ethernet TX data 0 signal and header for current limiting and impedance matching.
2	2	PB2_ETX0	✅	100 ohm series resistor between Ethernet TX data 0 signal and header for current limiting and impedance matching.

R159 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_19	✅	100 ohm series resistor between ADC input and header for current limiting and protection.
2	2	PB13_AD9	✅	100 ohm series resistor between ADC input and header for current limiting and protection.

RV3 - AVRM0603C6R8NT101N ✅

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Part Number: AVRM0603C6R8NT101N (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_15	✅	Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.
2	2	GND	✅	Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.

RV1 - AVRM0603C6R8NT101N ✅

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Part Number: AVRM0603C6R8NT101N (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_20	✅	Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.
2	2	GND	✅	Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.

D44 - ESD9X3.3ST5G ✅

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Part Number: ESD9X3.3ST5G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode connected between 3.3VCC power rail and ground for power supply protection. The 3.3V working voltage is marginal and may conduct if the power supply exceeds 3.3V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 5V) to provide more margin.
K	K	3.3VCC	✅	TVS diode connected between 3.3VCC power rail and ground for power supply protection. The 3.3V working voltage is marginal and may conduct if the power supply exceeds 3.3V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 5V) to provide more margin.

RV4 - AVRM0603C6R8NT101N ✅

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Part Number: AVRM0603C6R8NT101N (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_16	✅	Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.
2	2	GND	✅	Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.

RV2 - AVRM0603C6R8NT101N ✅

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Part Number: AVRM0603C6R8NT101N (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_19	✅	Varistor correctly connected between signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.
2	2	GND	✅	Varistor correctly connected between signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals.

D45 - DF2S6.8FS,L3M ✅

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Part Number: DF2S6.8FS,L3M (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode connected between +5VCC power rail and ground for power supply protection. The 5V working voltage is marginal and may conduct if the power supply exceeds 5V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 6V) to provide more margin.
K	K	+5VCC	✅	TVS diode connected between +5VCC power rail and ground for power supply protection. The 5V working voltage is marginal and may conduct if the power supply exceeds 5V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 6V) to provide more margin.

R41 - RK73H1ETTP1001F ❌

DRCY flagged 1 potential issues in this component.

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA1_CANRX0	❌	R41 connects two GPIO pins of the same microcontroller (PA1_CANRX0 and PA5_PWM) together through a 1kΩ resistor. This is an unusual and likely incorrect connection that serves no clear purpose and could cause pin conflicts. R41 pin 1 is connected to net PA1_CANRX0, which connects to U11A pin 24 (from schematic) R41 pin 2 is connected to net PA5_PWM, which connects to U11A pin 25 (from schematic) U11A pin 24 (PA1) can be configured as CANRX0, PCK0, or WKUP0 according to the datasheet (from datasheet ATSAM3X8EA-AU, page 18) U11A pin 25 (PA5) can be configured as TIOA2, PWMFI0, or WKUP2 according to the datasheet (from datasheet ATSAM3X8EA-AU, page 18) Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0) Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA5_PWM) R41 is a 1kΩ 1% 1/16W resistor in 0402 package (from datasheet RC0402FR-071KL, page 4) Connecting two GPIO pins of the same microcontroller together through a resistor is not a standard design practice and serves no clear functional purpose (reasoning) If both pins are configured as outputs driving different logic levels, the 1kΩ resistor would create a conflict and excessive current draw (reasoning) No text notes on the schematic page explain or justify this connection between PA1_CANRX0 and PA5_PWM (reasoning) This connection should be reviewed and likely removed, or one end should be connected to the intended destination if this is a routing error (reasoning)
2	2	PA5_PWM	❌	R41 connects two GPIO pins of the same microcontroller (PA1_CANRX0 and PA5_PWM) together through a 1kΩ resistor. This is an unusual and likely incorrect connection that serves no clear purpose and could cause pin conflicts. R41 pin 1 is connected to net PA1_CANRX0, which connects to U11A pin 24 (from schematic) R41 pin 2 is connected to net PA5_PWM, which connects to U11A pin 25 (from schematic) U11A pin 24 (PA1) can be configured as CANRX0, PCK0, or WKUP0 according to the datasheet (from datasheet ATSAM3X8EA-AU, page 18) U11A pin 25 (PA5) can be configured as TIOA2, PWMFI0, or WKUP2 according to the datasheet (from datasheet ATSAM3X8EA-AU, page 18) Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0) Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA5_PWM) R41 is a 1kΩ 1% 1/16W resistor in 0402 package (from datasheet RC0402FR-071KL, page 4) Connecting two GPIO pins of the same microcontroller together through a resistor is not a standard design practice and serves no clear functional purpose (reasoning) If both pins are configured as outputs driving different logic levels, the 1kΩ resistor would create a conflict and excessive current draw (reasoning) No text notes on the schematic page explain or justify this connection between PA1_CANRX0 and PA5_PWM (reasoning) This connection should be reviewed and likely removed, or one end should be connected to the intended destination if this is a routing error (reasoning)

U2B - SN74AHCT125 ✅

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Part Number: SN74AHCT125RGYR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
4	2OE	GND	✅	Output enable pin correctly tied to GND to permanently enable the buffer output.
5	2A	Fan3	✅	Input pin correctly connected to Fan3 control signal from the microcontroller.
6	2Y	NetR180_1	✅	Output pin correctly drives MOSFET gate through 100Ω series resistor R180.

U2A - SN74AHCT125 ✅

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Part Number: SN74AHCT125RGYR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1OE	GND	✅	Output enable pin correctly tied to GND to permanently enable the buffer output.
2	1A	Fan4	✅	Input pin correctly connected to Fan4 control signal from the microcontroller.
3	1Y	NetR181_1	✅	Output pin correctly drives MOSFET gate through 100Ω series resistor R181.

U2E - SN74AHCT125 ❌

DRCY flagged 1 potential issues in this component.

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Part Number: SN74AHCT125RGYR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
15	PAD	SNTP1	❌	Thermal pad incorrectly connected to floating net SNTP1 instead of GND. The exposed pad should be connected to ground for proper thermal dissipation and electrical stability. Pin 15 (PAD) is connected to net SNTP1 (from schematic) SNTP1 is a page-local net with no other connections (from whole-design connectivity for SNTP1) The PAD pin is the exposed thermal pad on the QFN package bottom (reasoning) Thermal pads on digital ICs should be connected to GND for heat dissipation and to provide a low-impedance ground reference (reasoning) Leaving the thermal pad floating reduces thermal performance and may cause electrical instability (reasoning) The PAD pin should be connected to GND instead of the floating SNTP1 net (reasoning)
7	GND	GND	✅	Ground pin correctly connected to GND.
14	VCC	+5VCC	✅	Power supply pin correctly connected to +5VCC with local decoupling.

U2C - SN74AHCT125 ✅

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Part Number: SN74AHCT125RGYR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
8	3Y	NetR99_1	✅	Output pin correctly drives MOSFET gate through 100Ω series resistor R99.
9	3A	Fan2	✅	Input pin correctly connected to Fan2 control signal from the microcontroller.
10	3OE	GND	✅	Output enable pin correctly tied to GND to permanently enable the buffer output.

C106 - 100nF 6.3V X5R 0201 ✅

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Part Number: CL03A104KQ3NNNC (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Decoupling capacitor correctly connected between 3.3VCC and GND to provide local filtering for the 3.3V rail used by tachometer circuits on this page.
2	2	3.3VCC	✅	Decoupling capacitor correctly connected between 3.3VCC and GND to provide local filtering for the 3.3V rail used by tachometer circuits on this page.

C92 - 100nF 0402 16V X7R ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Decoupling capacitor correctly connected between +5VCC and GND to provide high-frequency filtering for the buffer IC.
2	2	+5VCC	✅	Decoupling capacitor correctly connected between +5VCC and GND to provide high-frequency filtering for the buffer IC.

U2D - SN74AHCT125 ✅

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Part Number: SN74AHCT125RGYR (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
11	4Y	NetR98_1	✅	Output pin correctly drives MOSFET gate through 100Ω series resistor R98.
12	4A	Fan1	✅	Input pin correctly connected to Fan1 control signal from the microcontroller.
13	4OE	GND	✅	Output enable pin correctly tied to GND to permanently enable the buffer output.

R96 - 10k 1% 0402 ✅

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Part Number: RC0402FR-074K7L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetLED1_A	✅	LED current limiting resistor correctly connected between VFAN and LED1 anode with appropriate 4.7K value, but has documentation inconsistency in PART field.
2	2	VFAN	✅	LED current limiting resistor correctly connected between VFAN and LED1 anode with appropriate 4.7K value, but has documentation inconsistency in PART field.

R12 - 10k 1% 0402 ✅

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Part Number: RC0402FR-074K7L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetLED2_A	✅	LED current limiting resistor correctly connected between VFAN and LED2 anode with appropriate 4.7K value, but has documentation inconsistency in PART field.
2	2	VFAN	✅	LED current limiting resistor correctly connected between VFAN and LED2 anode with appropriate 4.7K value, but has documentation inconsistency in PART field.

J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

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Part Number: 0705430002 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC153_2	✅	Fan ground connection correctly routed to low-side driver drain for PWM switching.
2	S	VFAN	✅	Fan power supply connection correctly connected to VFAN.
3	S	NetJ22_3	✅	Fan tachometer signal correctly connected to signal conditioning circuit.

R99 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR99_1	✅	Gate drive resistor correctly positioned between buffer output and driver gate.
2	2	NetQ12_4	✅	Gate drive resistor correctly positioned between buffer output and driver gate.

LED1 - 5988110107F ✅

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Part Number: 5988110107F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED1_A	✅	LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage).
C	C	NetC154_2	✅	LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage).

J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

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Part Number: 0705430002 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC154_2	✅	Fan ground connection correctly routed to low-side driver drain for PWM switching.
2	S	VFAN	✅	Fan power supply connection correctly connected to VFAN.
3	S	NetJ29_3	✅	Fan tachometer signal correctly connected to signal conditioning circuit.

LED2 - 5988110107F ✅

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Part Number: 5988110107F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED2_A	✅	LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage).
C	C	NetC153_2	✅	LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage).

Q12A - NCV8402AD ✅

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Part Number: NCV8402ADDR2G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Source pin correctly connected to GND for low-side driver operation.
2	G	NetQ12_2	✅	Gate pin correctly driven through 100R series resistor from buffer output.
7	D	NetC154_2	✅	Drain pin correctly connected to fan connector and LED indicator for low-side switching.

R98 - RES 100R 0402 1% ✅

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Part Number: RC0402FR-07100RL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR98_1	✅	Gate drive resistor correctly positioned between buffer output and driver gate.
2	2	NetQ12_2	✅	Gate drive resistor correctly positioned between buffer output and driver gate.

Q12B - NCV8402AD ✅

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Part Number: NCV8402ADDR2G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
3	S	GND	✅	Source pin correctly connected to GND for low-side driver operation.
4	G	NetQ12_4	✅	Gate pin correctly driven through 100R series resistor from buffer output.
5	D	NetC153_2	✅	Drain pin correctly connected to fan connector and LED indicator for low-side switching.

LED4 - 5988110107F ❌

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Part Number: 5988110107F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
C	C	VFAN	❌	Cathode incorrectly connected to VFAN instead of switched net, preventing LED from functioning. This is the root cause affecting both LED4 and J30 pin 1. Pin C (cathode) connects to VFAN (from schematic) LED4 pin A (anode) connects through R14 (4.7kΩ) to VFAN (from schematic) Both LED terminals are at VFAN potential, creating no voltage difference across the LED (reasoning) No current can flow through the LED in this configuration (reasoning) LED1 pin C connects to NetC154_2 (switched by Q12A pin 7), LED2 pin C connects to NetC153_2 (switched by Q12B pin 5), and LED3 pin C connects to NetC211_2 (switched by Q13A pin 7) (from schematic) Following the established pattern, LED4 pin C should connect to a switched net controlled by Q13B pin 5 (reasoning) Q13B pin 5 (drain) connects to VFAN instead of to a switched net, which is the fundamental circuit error (from schematic) The cathode should connect to the same switched net as J30 pin 1 to provide proper fan indication (reasoning) LED4 cannot function as a Fan4 indicator in the current configuration (reasoning)
A	A	NetLED4_A	✅	Anode correctly connected through current limiting resistor to VFAN per intended topology, though LED cannot function due to cathode connection issue.

J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

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Part Number: 0705430002 (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	VFAN	✅	Pin 1 incorrectly connected to VFAN instead of switched net. Should connect to the same switched net as LED4 pin C for proper fan control.
2	S	VFAN	✅	Pin 2 correctly connected to VFAN to provide positive power supply to fan motor.
3	S	NetJ30_3	✅	Tachometer pin correctly connected to tachometer signal conditioning circuit.

Q13B - NCV8402AD ❌

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Part Number: NCV8402ADDR2G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
5	D	VFAN	❌	Drain incorrectly connected directly to VFAN power rail instead of to a switched load. This prevents the driver from functioning and would create a short circuit when enabled. Pin 5 (D) connects directly to VFAN (from schematic) For a low-side driver, the drain/output should connect to the load being switched, not to the power supply (reasoning) When the driver turns on, it would short VFAN to GND through the driver (reasoning) Comparing to Q13A pin 7 which correctly connects to NetC211_2, and Q12B pin 5 which correctly connects to NetC153_2, this pin should connect to a switched load net (reasoning) The drain should connect to a net that includes LED4 cathode, J30 pin 1, and C209 pin 2 to match the pattern of other fan channels (reasoning) No datasheet provided for NCV8402AD to verify correct pin usage (reasoning)
3	S	GND	✅	Source and gate pins correctly connected for low-side driver operation, but the drain connection error prevents proper function.
4	G	NetQ13_4	✅	Source and gate pins correctly connected for low-side driver operation, but the drain connection error prevents proper function.

LED3 - 5988110107F ✅

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Part Number: 5988110107F (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED3_A	✅	LED correctly configured as Fan3 indicator with current flowing from VFAN through R15 to anode, and cathode switched to ground by Q13A.
C	C	NetC211_2	✅	LED correctly configured as Fan3 indicator with current flowing from VFAN through R15 to anode, and cathode switched to ground by Q13A.

Q13A - NCV8402AD ✅

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Part Number: NCV8402ADDR2G (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Low-side driver correctly configured to switch Fan3 channel. Source connected to ground, gate driven through 100R resistor from buffer, drain switches LED3 and fan connector J31.
2	G	NetQ13_2	✅	Low-side driver correctly configured to switch Fan3 channel. Source connected to ground, gate driven through 100R resistor from buffer, drain switches LED3 and fan connector J31.
7	D	NetC211_2	✅	Low-side driver correctly configured to switch Fan3 channel. Source connected to ground, gate driven through 100R resistor from buffer, drain switches LED3 and fan connector J31.

D50 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD50_A	✅	Anode connected to NetD50_A for upper voltage clamping function.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC to set the upper clamp voltage.

R175 - RC0402FR-071KL ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD50_A	✅	Connected to NetD50_A to provide series resistance after the voltage clamping circuit.
2	2	NetJ29_3	✅	Connected to NetJ29_3, which goes to the fan connector and has a pull-up resistor.

D52 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for lower voltage clamping function.
K	K	NetD50_A	✅	Cathode connected to NetD50_A to set the lower clamp voltage.

C155 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_1	✅	Connected to TACH_1 signal for AC coupling and filtering of the fan tachometer input.
2	2	GND	✅	Connected to GND to complete the filter capacitor connection.

R174 - RC0402FR-071KL ✅

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Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_1	✅	Connected to TACH_1 to provide series resistance before the voltage clamping circuit.
2	2	NetD50_A	✅	Connected to NetD50_A, the internal node between the clamping diodes.

R172 - RC0402FR-071K8L ✅

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Part Number: RC0402FR-071K8L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ29_3	✅	Connected to NetJ29_3 to provide pull-up function for the fan tachometer signal.
2	2	3.3VCC	✅	Connected to 3.3VCC power rail to complete the pull-up function.

D53 - BAT54WX ❌

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD53_A	❌	D53 anode is connected to floating net NetD53_A instead of GND, preventing the diode from functioning as a lower clamp for TACH_2 signal protection. Anode (pin A) is connected to NetD53_A (from schematic) Cathode (pin K) is connected to NetD51_A (from schematic) NetD53_A is a page-local net with no other connections (from whole-design connectivity for NetD53_A) The anode is the positive terminal of the Schottky diode and forward current flows from anode to cathode (from datasheet BAT54WX-TP, page 1) The cathode is the negative terminal of the Schottky diode and blocks reverse voltage up to 30V (from datasheet BAT54WX-TP, page 1) In the parallel TACH_1 circuit, D52 has anode connected to GND and cathode to NetD50_A, providing lower voltage clamping (from schematic) In the parallel TACH_3 circuit, D56 has anode connected to GND and cathode to NetD54_A, providing lower voltage clamping (from schematic) In the parallel TACH_4 circuit, D57 has anode connected to GND and cathode to NetD55_A, providing lower voltage clamping (from schematic) For a lower clamp diode topology, the anode must be connected to GND to clamp negative voltages on the signal net to ground plus the diode forward voltage drop (reasoning) With the anode floating on NetD53_A, D53 cannot conduct current and therefore cannot perform its intended clamping function for NetD51_A (reasoning) The cathode connection to NetD51_A is correct for a lower clamp topology, but the diode is non-functional due to the incorrect anode connection (reasoning) The D53 anode connection should be changed from NetD53_A to GND to match the reference circuits and provide proper negative voltage protection for the TACH_2 signal (reasoning)
K	K	NetD51_A	❌	D53 anode is connected to floating net NetD53_A instead of GND, preventing the diode from functioning as a lower clamp for TACH_2 signal protection. Anode (pin A) is connected to NetD53_A (from schematic) Cathode (pin K) is connected to NetD51_A (from schematic) NetD53_A is a page-local net with no other connections (from whole-design connectivity for NetD53_A) The anode is the positive terminal of the Schottky diode and forward current flows from anode to cathode (from datasheet BAT54WX-TP, page 1) The cathode is the negative terminal of the Schottky diode and blocks reverse voltage up to 30V (from datasheet BAT54WX-TP, page 1) In the parallel TACH_1 circuit, D52 has anode connected to GND and cathode to NetD50_A, providing lower voltage clamping (from schematic) In the parallel TACH_3 circuit, D56 has anode connected to GND and cathode to NetD54_A, providing lower voltage clamping (from schematic) In the parallel TACH_4 circuit, D57 has anode connected to GND and cathode to NetD55_A, providing lower voltage clamping (from schematic) For a lower clamp diode topology, the anode must be connected to GND to clamp negative voltages on the signal net to ground plus the diode forward voltage drop (reasoning) With the anode floating on NetD53_A, D53 cannot conduct current and therefore cannot perform its intended clamping function for NetD51_A (reasoning) The cathode connection to NetD51_A is correct for a lower clamp topology, but the diode is non-functional due to the incorrect anode connection (reasoning) The D53 anode connection should be changed from NetD53_A to GND to match the reference circuits and provide proper negative voltage protection for the TACH_2 signal (reasoning)

D51 - BAT54WX ✅

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Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD51_A	✅	Anode connected to NetD51_A for upper voltage clamping.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC for upper voltage clamping.

C156 - GRM155R71C104KA88D ✅

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Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_2	✅	Connected to TACH_2 signal for filtering.
2	2	GND	✅	Connected to GND for filtering.

R173 - RC0402FR-071K8L ✅

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Part Number: RC0402FR-071K8L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ22_3	✅	Connected to NetJ22_3 as a pull-up resistor.
2	2	3.3VCC	✅	Connected to 3.3VCC to provide pull-up voltage.

R177 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD51_A	✅	Connected to NetD51_A as part of voltage divider.
2	2	NetJ22_3	✅	Connected to NetJ22_3, which goes to the fan connector tachometer pin.

R176 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_2	✅	Connected to TACH_2 signal as part of voltage divider.
2	2	NetD51_A	✅	Connected to NetD51_A, the intermediate node of the signal conditioning circuit.

R184 - RC0402FR-071K8L ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071K8L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ31_3	✅	Connected to NetJ31_3, providing pull-up for the fan tachometer signal.
2	2	3.3VCC	✅	Connected to 3.3VCC supply rail, providing the pull-up voltage reference.

C212 - GRM155R71C104KA88D ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_3	✅	Connected to TACH_3 signal, providing noise filtering for the tachometer input.
2	2	GND	✅	Connected to GND, completing the filter capacitor to ground.

R186 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_3	✅	Connected to TACH_3 signal going to microcontroller. This is the output of the tachometer conditioning circuit.
2	2	NetD54_A	✅	Connected to NetD54_A, the middle node of the voltage clamping network with diodes D54 and D56.

D54 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD54_A	✅	Anode connected to NetD54_A, providing upper voltage clamp to 3.3VCC.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC, setting the upper clamp voltage reference.

R187 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD54_A	✅	Connected to NetD54_A, the middle node of the voltage clamping network.
2	2	NetJ31_3	✅	Connected to NetJ31_3, which goes to the fan connector tachometer pin and has a pull-up resistor.

D56 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND, setting the lower clamp voltage reference.
K	K	NetD54_A	✅	Cathode connected to NetD54_A, providing lower voltage clamp protection.

D57 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for lower voltage clamping.
K	K	NetD55_A	✅	Cathode connected to NetD55_A for lower voltage clamping.

R185 - RC0402FR-071K8L ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071K8L (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ30_3	✅	Connected to NetJ30_3 as pull-up resistor input.
2	2	3.3VCC	✅	Connected to 3.3VCC to provide pull-up voltage.

D55 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: BAT54WX-TP (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD55_A	✅	Anode connected to NetD55_A for upper voltage clamping.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC for upper voltage clamping.

R188 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_4	✅	Connected to TACH_4 signal as series input resistance.
2	2	NetD55_A	✅	Connected to intermediate node NetD55_A in the protection circuit.

C213 - GRM155R71C104KA88D ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: GRM155R71C104KA88D (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_4	✅	Connected to TACH_4 signal for input filtering.
2	2	GND	✅	Connected to GND for filtering reference.

R189 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. (via Mouser) 📤 Replace a datasheet

Part Number: RC0402FR-071KL (MPN) — inferred by DRCY

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD55_A	✅	Connected to intermediate node NetD55_A in the protection circuit.
2	2	NetJ30_3	✅	Connected to NetJ30_3 which routes to the fan connector.

📤 Upload Missing Datasheets

DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews.

J18 (0475710001): 📤 Upload a datasheet
J22, J29, J30, J31 (0705430002): 📤 Upload a datasheet
S1 (1571610-2): 📤 Upload a datasheet
J4 (20021121-00010C4LF): 📤 Upload a datasheet
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J12, J13, J28 (302-S101): 📤 Upload a datasheet
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C14, C16, C93 (490-10756-2-ND): 📤 Upload a datasheet
J3 (4DB-P108-10): 📤 Upload a datasheet
D24, LED1, LED2, LED3, LED4 (5988110107F): 📤 Upload a datasheet
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U9 (ADUM3160BRWZ-RL): 📤 Upload a datasheet
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C150 (C0402C222J3GACTU): 📤 Upload a datasheet
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FB26, FB27, FB28, FB29, FB30 (CIS10P121AC): 📤 Upload a datasheet
C106 (CL03A104KQ3NNNC): 📤 Upload a datasheet
C49 (CL05C100JB5NNNC): 📤 Upload a datasheet
R154, R26 (CRCW040224K0FKEDC): 📤 Upload a datasheet
R13, R3, R32, R4, R59, R84, R89, R93, R94 (CRCW040247R0FKEDC): 📤 Upload a datasheet
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R156, R28 (ERJ2GEJ105X): 📤 Upload a datasheet
D1, D42, D44, D64, D65, D66, D67, D68, D69, D71, D72, D73 (ESD9X3.3ST5G): 📤 Upload a datasheet
C24, C32, C34 (GRM155R60J105KE19D): 📤 Upload a datasheet
C13, C17, C35, C94 (GRM155R71H102KA01D): 📤 Upload a datasheet
C171, C40, C43, C71, C77 (GRM155R71H103JA88D): 📤 Upload a datasheet
U19 (INA381A2IDSGR): 📤 Upload a datasheet
S2 (KMR741NG ULC LFS): 📤 Upload a datasheet
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Q12A, Q12B, Q13A, Q13B (NCV8402ADDR2G): 📤 Upload a datasheet
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R158, R31, R37, R38, R51, R58 (RC1005F104CS): 📤 Upload a datasheet
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U2A, U2B, U2C, U2D, U2E (SN74AHCT125RGYR): 📤 Upload a datasheet
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C101, C102, C104, C64, C74, C75, C79, C83, C85, C87, C88, C89, C90 (TBD): 📤 Upload a datasheet
U1 (TPS54531DDAR): 📤 Upload a datasheet

_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 266 component(s) to review, and found 9 potential issue(s) in 12 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary>Component Details</summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=51.97,46.84,59.84,54.34&zoom=1">C1</a> - 100nF 0603 50V X7R ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/72/1/KEM_C1002_X7R_SMD.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0603C104K5RACTU) Part Number: `C0603C104K5RACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC1_1 | ✅ | Bootstrap capacitor pin 1 correctly connected to BOOT pin of U1. | | 2 | 2 | NetC1_2 | ✅ | Bootstrap capacitor pin 2 correctly connected to switch node (PH). | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=50.79,49.78,63.74,64.33&zoom=1">U1</a> - TPS54531 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TPS54531DDAR) Part Number: `TPS54531DDAR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | BOOT | NetC1_1 | ✅ | BOOT pin correctly connected to bootstrap capacitor C1 between BOOT and PH. | | 2 | VIN | VPWR | ✅ | VIN pin correctly connected to VPWR input rail with appropriate decoupling. | | 3 | EN | NetR2_2 | ✅ | EN pin correctly configured with voltage divider and fault protection comparators for enable control. | | 4 | SS | NetC171_2 | ✅ | SS pin correctly connected to soft-start capacitor C171 for controlled startup. | | 5 | VSNS | NetC3_1 | ✅ | VSNS pin correctly connected to feedback resistor divider for 5V output regulation. | | 6 | COMP | NetC150_2 | ✅ | COMP pin correctly connected to compensation network for loop stability. | | 7 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 8 | PH | NetC1_2 | ✅ | PH pin correctly connected to inductor and catch diode forming the switch node. | | 9 | PAD | GND | ✅ | PAD (thermal pad) correctly connected to ground for heat dissipation. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=68.51,51.54,76.01,61.39&zoom=1">D2</a> - SK54B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/SK52B_L_SK520B_L_SMB.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SK54B-LTP) Part Number: `SK54B-LTP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Diode anode correctly connected to ground for buck converter catch diode operation. | | K | CATHODE | NetC1_2 | ✅ | Diode cathode correctly connected to switch node for freewheeling operation. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=36.71,55.07,44.21,63.74&zoom=1">R2</a> - 1.4k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/1099/1/SEI_RMCF_RMCP.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RMCF0402FT1K40) Part Number: `RMCF0402FT1K40` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Enable pull-down resistor correctly configured as part of voltage divider for EN pin control. | | 2 | 2 | NetR2_2 | ✅ | Enable pull-down resistor correctly configured as part of voltage divider for EN pin control. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=69.42,49.78,80.55,57.28&zoom=1">L1</a> - 4.7uH 10A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/40/1/srp1038a.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SRP1038A-4R7M) Part Number: `SRP1038A-4R7M` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC1_2 | ✅ | Inductor pin 1 correctly connected to switch node (PH) of U1. | | 2 | 2 | NetC3_2 | ✅ | Inductor pin 2 correctly connected to output voltage rail. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=48.98,57.77,56.48,65.74&zoom=1">C171</a> - 10nF 0402 50V X7R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) Part Number: `GRM155R71H103JA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Soft-start capacitor correctly connected between SS pin and GND to control startup ramp. | | 2 | 2 | NetC171_2 | ✅ | Soft-start capacitor correctly connected between SS pin and GND to control startup ramp. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=36.71,51.54,44.21,60.22&zoom=1">R11</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR2_2 | ✅ | Enable pull-up resistor correctly configured as part of voltage divider for EN pin control. | | 2 | 2 | VPWR | ✅ | Enable pull-up resistor correctly configured as part of voltage divider for EN pin control. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=44.89,47.19,52.39,55.16&zoom=1">C71</a> - 10nF 0402 50V X7R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) Part Number: `GRM155R71H103JA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Input decoupling capacitor correctly connected between VPWR and GND for high-frequency filtering. | | 2 | 2 | VPWR | ✅ | Input decoupling capacitor correctly connected between VPWR and GND for high-frequency filtering. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=77.60,53.89,85.10,62.57&zoom=1">R5</a> - 1.96k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071K96L) Part Number: `RC0402FR-071K96L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower feedback resistor in voltage divider. Correctly connected between VSNS feedback pin (NetC3_1) and ground. | | 2 | 2 | NetC3_1 | ✅ | Lower feedback resistor in voltage divider. Correctly connected between VSNS feedback pin (NetC3_1) and ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=80.32,51.31,87.82,59.28&zoom=1">C3</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC3_1 | ✅ | Optional feedforward capacitor in parallel with R1 to improve transient response. Marked DNI (do not install) with placeholder value of 10pF. | | 2 | 2 | NetC3_2 | ✅ | Optional feedforward capacitor in parallel with R1 to improve transient response. Marked DNI (do not install) with placeholder value of 10pF. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=73.96,51.31,81.46,59.28&zoom=1">C4</a> - 47uF 1210 10V X5R ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/1/GRM32ER61A476KE20-01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM32ER61A476KE20L) Part Number: `GRM32ER61A476KE20L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Output filter capacitor providing bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground, in parallel with C5. | | 2 | 2 | NetC3_2 | ✅ | Output filter capacitor providing bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground, in parallel with C5. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=75.33,51.31,82.83,59.28&zoom=1">C5</a> - 47uF 1210 10V X5R ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/1/GRM32ER61A476KE20-01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM32ER61A476KE20L) Part Number: `GRM32ER61A476KE20L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Output filter capacitor in parallel with C4, providing additional bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground. | | 2 | 2 | NetC3_2 | ✅ | Output filter capacitor in parallel with C4, providing additional bulk capacitance for the 5V rail. Correctly connected between +5VCC output and ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=64.88,53.89,72.38,62.57&zoom=1">C151</a> - 22pF 0402 50V C0G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/5926/1/C0GNP0_Dielectric.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/04025A220JAT2A) Part Number: `04025A220JAT2A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | High-frequency compensation capacitor creating a pole to attenuate switching noise. Correctly connected between COMP pin and ground. | | 2 | 2 | NetC150_2 | ✅ | High-frequency compensation capacitor creating a pole to attenuate switching noise. Correctly connected between COMP pin and ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=61.24,55.66,68.74,64.33&zoom=1">R10</a> - 37.4K 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0737K4L) Part Number: `RC0402FR-0737K4L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Compensation network resistor in series with C150, setting the zero frequency for loop compensation. Correctly connected between C150 and ground. | | 2 | 2 | NetC150_1 | ✅ | Compensation network resistor in series with C150, setting the zero frequency for loop compensation. Correctly connected between C150 and ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=77.60,50.95,85.10,59.63&zoom=1">R1</a> - 10.2k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710K2L) Part Number: `RC0402FR-0710K2L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC3_2 | ✅ | Upper feedback resistor in voltage divider setting output to 5V. Correctly connected between +5VCC output (NetC3_2) and VSNS feedback pin (NetC3_1). | | 2 | 2 | NetC3_1 | ✅ | Upper feedback resistor in voltage divider setting output to 5V. Correctly connected between +5VCC output (NetC3_2) and VSNS feedback pin (NetC3_1). | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=61.24,52.13,68.74,60.80&zoom=1">C150</a> - 2.2nF 25V C0G 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0402C222J3GACTU) Part Number: `C0402C222J3GACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC150_1 | ✅ | Compensation network capacitor in series with R10, creating a zero to stabilize the control loop. Correctly connected between COMP pin and ground through R10. | | 2 | 2 | NetC150_2 | ✅ | Compensation network capacitor in series with R10, creating a zero to stabilize the control loop. Correctly connected between COMP pin and ground through R10. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=82.14,49.78,90.55,57.28&zoom=1">R148</a> - 0.01R 1% 0805 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/826/1/n_catalog_partition09_en.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/KRL1220E-M-R010-F-T5) Part Number: `KRL1220E-M-R010-F-T5` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC3_2 | ✅ | Current sense resistor correctly placed in series between the buck regulator output (NetC3_2) and the main 5V supply rail (+5VCC) to measure load current for overcurrent protection. | | 2 | 2 | +5VCC | ✅ | Current sense resistor correctly placed in series between the buck regulator output (NetC3_2) and the main 5V supply rail (+5VCC) to measure load current for overcurrent protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=47.61,28.03,56.93,35.53&zoom=1">R102</a> - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR102_1 | ✅ | Pull-up resistor correctly configured to hold U19 RESET pin high, enabling LATCHING mode operation for the overcurrent protection circuit. | | 2 | 2 | 5V0_AUX | ✅ | Pull-up resistor correctly configured to hold U19 RESET pin high, enabling LATCHING mode operation for the overcurrent protection circuit. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=54.43,10.98,61.93,19.66&zoom=1">C200</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering near the U20 regulator output. | | 2 | 2 | 5V0_AUX | ✅ | Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering near the U20 regulator output. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=48.52,31.55,56.02,40.23&zoom=1">C201</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering for the U19 comparator. | | 2 | 2 | 5V0_AUX | ✅ | Decoupling capacitor correctly placed between 5V0_AUX and GND to provide local supply filtering for the U19 comparator. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=40.80,35.08,48.30,43.76&zoom=1">R119</a> - 4.7k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-074K7L) Part Number: `RC0402FR-074K7L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified. | | 2 | 2 | NetR115_1 | ✅ | Lower resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=51.70,26.85,68.29,40.23&zoom=1">U19</a> - INA381_ALT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/INA381A2IDSGR) Part Number: `INA381A2IDSGR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN+ | NetC3_2 | ✅ | IN+ is correctly connected to NetC3_2, the high side of current sense resistor R148, to measure the voltage before the load. | | 2 | Vs | 5V0_AUX | ✅ | Vs is correctly connected to 5V0_AUX, providing power to the INA381 within its specified operating range of 2.7-5.5V. | | 3 | nALERT | NetR2_2 | ✅ | nALERT is correctly connected to NetR2_2, which controls the enable pin of buck converter U1 to disable the regulator when current limit is exceeded. | | 4 | RESET | NetR102_1 | ✅ | RESET is correctly pulled high by R102 to 5V0_AUX, configuring the comparator in LATCHING mode as indicated by schematic text notes. | | 5 | CMPREF | NetR115_1 | ✅ | CMPREF is correctly connected to the voltage divider formed by R115 and R119, setting the reference threshold. However, the calculated current limit (~6A with typical gain assumptions) does not match the text note stating '~4A'. | | 6 | CMPIN | NetU19_6 | ✅ | CMPIN and VOUT are correctly connected together (NetU19_6), which is the standard configuration for the INA381 where the amplified sense voltage is fed directly to the comparator input. | | 7 | VOUT | NetU19_6 | ✅ | CMPIN and VOUT are correctly connected together (NetU19_6), which is the standard configuration for the INA381 where the amplified sense voltage is fed directly to the comparator input. | | 8 | IN- | +5VCC | ✅ | IN- is correctly connected to +5VCC, the low side of current sense resistor R148, to measure the voltage after the load. | | 9 | GND | GND | ✅ | GND is correctly connected to the ground plane. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=40.80,32.14,48.30,40.82&zoom=1">R115</a> - 15K 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F153CS) Part Number: `RC1005F153CS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR115_1 | ✅ | Upper resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified. | | 2 | 2 | 5V0_AUX | ✅ | Upper resistor of voltage divider setting CMPREF reference voltage. The calculated reference (~1.193V) may not achieve the stated ~4A current limit and should be verified. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=90.77,18.62,98.27,27.30&zoom=1">D23</a> - 5988170107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/C17562-3926771.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988170107F) Part Number: `5988170107F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD23_A | ✅ | LED anode correctly connected through current limiting resistor R33 to 3.3V supply. | | C | C | GND | ✅ | LED cathode correctly connected to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=81.69,13.92,89.19,22.60&zoom=1">C24</a> - GRM155R60J105KE19D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R60J105KE19D) Part Number: `GRM155R60J105KE19D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | 1µF output capacitor correctly connected between 3.3V output and ground for LDO stability. | | 2 | 2 | GND | ✅ | 1µF output capacitor correctly connected between 3.3V output and ground for LDO stability. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=63.51,9.22,71.01,17.89&zoom=1">C34</a> - GRM155R60J105KE19D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R60J105KE19D) Part Number: `GRM155R60J105KE19D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | 1µF input capacitor correctly connected between 5V input and ground for LDO stability. | | 2 | 2 | GND | ✅ | 1µF input capacitor correctly connected between 5V input and ground for LDO stability. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=70.78,8.04,85.55,22.60&zoom=1">U8</a> - MIC5353-3.3YMT-TR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/282/1/MIC5353-500mA-LDO-in-1.6mmx1.6mm-Package-DS20006507A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/MIC5353-3.3YMT-TR) Part Number: `MIC5353-3.3YMT-TR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | EN | +5VCC | ✅ | EN pin correctly connected to +5VCC to enable the regulator whenever 5V power is present. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | VIN | +5VCC | ✅ | VIN pin correctly connected to +5VCC supply, which is within the 2.6V to 6.0V input range. | | 4 | VOUT | 3.3VCC | ✅ | VOUT pin correctly connected to 3.3VCC output rail with proper 1µF output capacitor C24. | | 5 | ADJ | NetU8_5 | ✅ | ADJ pin correctly left as no-connect for the fixed 3.3V output variant. | | 6 | BYP | NetC26_1 | ✅ | BYP pin correctly connected to 100nF bypass capacitor C26 for noise reduction. | | 7 | PAD | GND | ✅ | Exposed heatsink pad correctly connected to ground for thermal management. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=81.23,8.04,89.64,15.54&zoom=1">C26</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC26_1 | ✅ | 100nF bypass capacitor correctly connected between U8 BYP pin and ground for noise reduction. | | 2 | 2 | GND | ✅ | 100nF bypass capacitor correctly connected between U8 BYP pin and ground for noise reduction. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=90.77,13.92,98.27,23.77&zoom=1">R33</a> - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD23_A | ✅ | 1k current limiting resistor correctly connected between 3.3V supply and LED anode, providing approximately 1.3mA LED current. | | 2 | 2 | 3.3VCC | ✅ | 1k current limiting resistor correctly connected between 3.3V supply and LED anode, providing approximately 1.3mA LED current. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=46.25,8.63,59.20,19.07&zoom=1">U20</a> - 78L05 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/L78L05ABUTR) Part Number: `L78L05ABUTR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | OUT | 5V0_AUX | ✅ | Output pin correctly connected to 5V0_AUX rail, providing regulated 5V auxiliary power for analog circuits. | | 2 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 3 | IN | VPWR | ✅ | Input pin correctly connected to VPWR rail, receiving 12-24VDC input power. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=44.43,10.39,51.93,19.07&zoom=1">C203</a> - C0603C104K5RACTU ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/72/1/KEM_C1002_X7R_SMD.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0603C104K5RACTU) Part Number: `C0603C104K5RACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | Input filter capacitor terminal correctly connected to VPWR rail. | | 2 | 2 | GND | ✅ | Input filter capacitor terminal correctly connected to GND. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=40.80,10.39,48.30,19.07&zoom=1">C199</a> - C0603C104K5RACTU ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/72/1/KEM_C1002_X7R_SMD.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0603C104K5RACTU) Part Number: `C0603C104K5RACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | Input filter capacitor terminal correctly connected to VPWR rail. | | 2 | 2 | GND | ✅ | Input filter capacitor terminal correctly connected to GND. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=42.62,10.39,50.12,19.07&zoom=1">C202</a> - C0603C104K5RACTU ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/72/1/KEM_C1002_X7R_SMD.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0603C104K5RACTU) Part Number: `C0603C104K5RACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | Input filter capacitor terminal correctly connected to VPWR rail. | | 2 | 2 | GND | ✅ | Input filter capacitor terminal correctly connected to GND. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=23.08,38.02,30.58,46.70&zoom=1">C95</a> - C0603C104K5RACTU ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/72/1/KEM_C1002_X7R_SMD.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0603C104K5RACTU) Part Number: `C0603C104K5RACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOT1 | ✅ | 100nF decoupling capacitor correctly connected between VMOT1 and GND for medium-frequency filtering. | | 2 | 2 | GND | ✅ | 100nF decoupling capacitor correctly connected between VMOT1 and GND for medium-frequency filtering. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=17.17,38.02,24.67,46.70&zoom=1">D43</a> - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SMAJ24A) Part Number: `SMAJ24A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode is correctly connected to GND for standard unidirectional TVS diode configuration protecting VMOT1. | | K | K | VMOT1 | ✅ | Cathode is correctly connected to VMOT1 rail for transient voltage suppression. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=26.72,38.37,34.22,46.34&zoom=1">C93</a> - 10uF 1206 50V X5R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/490-10756-2-ND) Part Number: `490-10756-2-ND` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 10uF bulk capacitor correctly connected between VMOT1 and GND for low-frequency filtering and energy storage. | | 2 | 2 | VMOT1 | ✅ | 10uF bulk capacitor correctly connected between VMOT1 and GND for low-frequency filtering and energy storage. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=19.45,38.02,26.95,46.70&zoom=1">C94</a> - CAP 1nF 50V 0402 X7R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H102KA01D) Part Number: `GRM155R71H102KA01D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOT1 | ✅ | 1nF decoupling capacitor correctly connected between VMOT1 and GND for high-frequency filtering. | | 2 | 2 | GND | ✅ | 1nF decoupling capacitor correctly connected between VMOT1 and GND for high-frequency filtering. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=26.72,17.21,34.22,25.18&zoom=1">C16</a> - 10uF 1206 50V X5R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/490-10756-2-ND) Part Number: `490-10756-2-ND` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Bulk capacitor correctly connected between VBED and GND for input filtering of the heated bed power supply. | | 2 | 2 | VBED | ✅ | Bulk capacitor correctly connected between VBED and GND for input filtering of the heated bed power supply. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=19.45,28.03,26.95,36.70&zoom=1">C35</a> - CAP 1nF 50V 0402 X7R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H102KA01D) Part Number: `GRM155R71H102KA01D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | High-frequency decoupling capacitor correctly connected between VPWR and GND for noise filtering. | | 2 | 2 | GND | ✅ | High-frequency decoupling capacitor correctly connected between VPWR and GND for noise filtering. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=17.17,28.03,24.67,36.70&zoom=1">D22</a> - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SMAJ24A) Part Number: `SMAJ24A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode anode correctly connected to GND for transient voltage suppression of the VPWR rail. | | K | K | VPWR | ✅ | TVS diode cathode correctly connected to VPWR rail for transient protection with 24V stand-off voltage matching the 12-24VDC input specification. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=13.99,26.85,23.31,34.35&zoom=1">F2</a> - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/201/1/M65p41.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/3557-2) Part Number: `3557-2` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR_IN | ✅ | Input terminal of fuse block, correctly connected to VPWR_IN from barrier strip connector J3 pin 5. | | 2 | 2 | VPWR | ✅ | Output terminal of fuse block, correctly connected to VPWR which supplies power to downstream circuits including the Mosfets page. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=14.45,15.68,23.77,23.18&zoom=1">F1</a> - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/201/1/M65p41.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/3557-20) Part Number: `3557-20` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED_IN | ✅ | Fuse holder connecting VBED_IN input to VBED output rail for heated bed overcurrent protection. Connection is correct. | | 2 | 2 | VBED | ✅ | Fuse holder connecting VBED_IN input to VBED output rail for heated bed overcurrent protection. Connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=19.45,16.86,26.95,25.53&zoom=1">C13</a> - CAP 1nF 50V 0402 X7R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H102KA01D) Part Number: `GRM155R71H102KA01D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED | ✅ | 1nF high-frequency decoupling capacitor correctly connected between VBED and GND as part of multi-stage filtering network. | | 2 | 2 | GND | ✅ | 1nF high-frequency decoupling capacitor correctly connected between VBED and GND as part of multi-stage filtering network. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=23.08,16.86,30.58,25.53&zoom=1">C15</a> - C0603C104K5RACTU ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/72/1/KEM_C1002_X7R_SMD.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0603C104K5RACTU) Part Number: `C0603C104K5RACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED | ✅ | 100nF medium-frequency decoupling capacitor correctly connected between VBED and GND for bulk filtering. | | 2 | 2 | GND | ✅ | 100nF medium-frequency decoupling capacitor correctly connected between VBED and GND for bulk filtering. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=30.35,16.86,38.76,25.53&zoom=1">C210</a> - UWT1V101MCL1GS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/497/1/e_uwt.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/UWT1V101MCL1GS) Part Number: `UWT1V101MCL1GS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED | ✅ | 100µF aluminum electrolytic bulk capacitor with pin 1 (positive) to VBED and pin 2 (negative) to GND. Polarity and voltage rating are correct for the 12-24V heated bed power rail. | | 2 | 2 | GND | ✅ | 100µF aluminum electrolytic bulk capacitor with pin 1 (positive) to VBED and pin 2 (negative) to GND. Polarity and voltage rating are correct for the 12-24V heated bed power rail. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=17.63,16.86,25.13,25.53&zoom=1">D78</a> - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SMAJ24A) Part Number: `SMAJ24A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode protecting VBED rail with anode to GND and cathode to VBED. This is correctly oriented for overvoltage protection of a positive 12-24V rail. | | K | K | VBED | ✅ | TVS diode protecting VBED rail with anode to GND and cathode to VBED. This is correctly oriented for overvoltage protection of a positive 12-24V rail. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=2.64,54.95,10.14,63.63&zoom=1">D21</a> - SMAJ24A ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SMAJ24A) Part Number: `SMAJ24A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | VMOT2 | ❌ | <details><summary>TVS diode connections are reversed. The anode is connected to VMOT2 and cathode to GND, which places the diode in forward-bias during normal operation instead of providing transient protection.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="2.64,54.95,10.14,62.45" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOT2 (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOT2 is a motor power input rail labeled 'MOTORS 5-8' with specified input range of 12-24VDC per the page note 'Inputs Compatible with 12-24VDC' (from schematic)</li><li>The cathode terminal is marked with a color band on the package body, and the anode is the unmarked terminal opposite to the cathode band (from datasheet <a href="https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf#page=2">SMAJ24A</a>, page 2)</li><li>For unidirectional TVS diode protection of a positive voltage rail, the standard configuration is cathode to the protected positive rail and anode to ground, allowing the TVS to remain reverse-biased during normal operation (reasoning)</li><li>With the current connection (anode to VMOT2, cathode to GND), the TVS diode is forward-biased during normal operation, which would cause it to conduct continuously and effectively short VMOT2 to ground through the diode's forward voltage drop (reasoning)</li><li>Other TVS diodes on the same page protecting similar positive rails (D22 on VPWR, D43 on VMOT1, D78 on VBED) all have their anodes connected to GND and cathodes to the positive rail being protected (from schematic)</li><li>The SMAJ24A has a reverse stand-off voltage (VRWM) of 24.0V, breakdown voltage (VBR) of 26.70V minimum to 29.50V maximum, and maximum clamping voltage of 38.9V at 10.3A peak pulse current (from datasheet <a href="https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf#page=4">SMAJ24A</a>, page 4)</li><li>The connections should be corrected to: Pin A (Anode) to GND and Pin K (Cathode) to VMOT2 to provide proper transient voltage protection (reasoning)</li></ul></details> | | K | K | GND | ❌ | <details><summary>TVS diode connections are reversed. The anode is connected to VMOT2 and cathode to GND, which places the diode in forward-bias during normal operation instead of providing transient protection.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="2.64,56.13,10.14,63.63" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOT2 (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOT2 is a motor power input rail labeled 'MOTORS 5-8' with specified input range of 12-24VDC per the page note 'Inputs Compatible with 12-24VDC' (from schematic)</li><li>The cathode terminal is marked with a color band on the package body, and the anode is the unmarked terminal opposite to the cathode band (from datasheet <a href="https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf#page=2">SMAJ24A</a>, page 2)</li><li>For unidirectional TVS diode protection of a positive voltage rail, the standard configuration is cathode to the protected positive rail and anode to ground, allowing the TVS to remain reverse-biased during normal operation (reasoning)</li><li>With the current connection (anode to VMOT2, cathode to GND), the TVS diode is forward-biased during normal operation, which would cause it to conduct continuously and effectively short VMOT2 to ground through the diode's forward voltage drop (reasoning)</li><li>Other TVS diodes on the same page protecting similar positive rails (D22 on VPWR, D43 on VMOT1, D78 on VBED) all have their anodes connected to GND and cathodes to the positive rail being protected (from schematic)</li><li>The SMAJ24A has a reverse stand-off voltage (VRWM) of 24.0V, breakdown voltage (VBR) of 26.70V minimum to 29.50V maximum, and maximum clamping voltage of 38.9V at 10.3A peak pulse current (from datasheet <a href="https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf#page=4">SMAJ24A</a>, page 4)</li><li>The connections should be corrected to: Pin A (Anode) to GND and Pin K (Cathode) to VMOT2 to provide proper transient voltage protection (reasoning)</li></ul></details> | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=4.91,55.07,12.41,63.74&zoom=1">C17</a> - CAP 1nF 50V 0402 X7R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H102KA01D) Part Number: `GRM155R71H102KA01D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOT2 | ✅ | Connected to VMOT2 motor power rail for high-frequency noise filtering. | | 2 | 2 | GND | ✅ | Connected to GND, completing the decoupling capacitor connection across the VMOT2 power rail. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=8.54,55.07,16.04,63.74&zoom=1">C18</a> - C0603C104K5RACTU ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/72/1/KEM_C1002_X7R_SMD.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0603C104K5RACTU) Part Number: `C0603C104K5RACTU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOT2 | ✅ | Connected to VMOT2 motor power rail for mid-frequency decoupling. | | 2 | 2 | GND | ✅ | Connected to GND, completing the decoupling capacitor connection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=12.18,55.42,19.68,63.39&zoom=1">C14</a> - 10uF 1206 50V X5R ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/490-10756-2-ND) Part Number: `490-10756-2-ND` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. Pin order is reversed compared to C17 and C18, but this is acceptable for a non-polarized ceramic capacitor. | | 2 | 2 | VMOT2 | ✅ | Connected to VMOT2, providing bulk capacitance for the motor power rail. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=22.63,49.19,30.13,57.86&zoom=1">R155</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower resistor of voltage divider correctly connected between the comparator IN+ input and ground. | | 2 | 2 | NetR154_2 | ✅ | Lower resistor of voltage divider correctly connected between the comparator IN+ input and ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=22.63,60.95,30.13,69.62&zoom=1">R158</a> - 100k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F104CS) Part Number: `RC1005F104CS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower resistor of reference voltage divider correctly connected between the comparator IN- input and ground. | | 2 | 2 | NetR157_1 | ✅ | Lower resistor of reference voltage divider correctly connected between the comparator IN- input and ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=22.63,46.84,30.13,55.51&zoom=1">R154</a> - 24k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040224K0FKEDC) Part Number: `CRCW040224K0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOT1 | ✅ | Upper resistor of voltage divider correctly connected between VMOT1 and the comparator IN+ input, scaling VMOT1 by factor of 0.294. | | 2 | 2 | NetR154_2 | ✅ | Upper resistor of voltage divider correctly connected between VMOT1 and the comparator IN+ input, scaling VMOT1 by factor of 0.294. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=26.26,54.48,38.76,79.61&zoom=1">U21</a> - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/175/1/AP331A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AP331AWG-7) Part Number: `AP331AWG-7` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR157_1 | ✅ | IN- pin correctly connected to reference voltage divider from 5V0_AUX through R157/R158, providing approximately 2.17V reference. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 3 | IN+ | NetR154_2 | ✅ | IN+ pin correctly connected to VMOT1 voltage divider through R154/R155, providing scaled monitoring voltage of approximately 0.294 × VMOT1. | | 4 | OUT | NetR2_2 | ✅ | Output pin correctly connected to NetR2_2 with pull-up resistor R11 (10k to VPWR) and hysteresis feedback R156 (1M). Output is OR'ed with other comparators for fault detection. | | 5 | VCC | VPWR | ✅ | VCC pin correctly connected to VPWR (12-24V supply), which is within the recommended 2-36V operating range. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=28.08,47.43,36.49,54.93&zoom=1">R156</a> - 1M 5% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ERJ2GEJ105X) Part Number: `ERJ2GEJ105X` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR2_2 | ✅ | Hysteresis feedback resistor correctly connected between comparator output and IN+ input, providing approximately 50mV of hysteresis to prevent oscillation. | | 2 | 2 | NetR154_2 | ✅ | Hysteresis feedback resistor correctly connected between comparator output and IN+ input, providing approximately 50mV of hysteresis to prevent oscillation. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=22.63,58.01,30.13,66.68&zoom=1">R157</a> - 130k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_GROUP_51_ROHS_L.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402JR-07130KL) Part Number: `RC0402JR-07130KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR157_1 | ✅ | Upper resistor of reference voltage divider correctly connected between 5V0_AUX and the comparator IN- input, providing stable reference voltage. | | 2 | 2 | 5V0_AUX | ✅ | Upper resistor of reference voltage divider correctly connected between 5V0_AUX and the comparator IN- input, providing stable reference voltage. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=9.91,63.30,17.41,71.97&zoom=1">R26</a> - 24k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040224K0FKEDC) Part Number: `CRCW040224K0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOT2 | ✅ | Connected to VMOT2, forming the upper resistor of a voltage divider that scales the motor supply voltage for monitoring. | | 2 | 2 | NetR26_2 | ✅ | Connected to NetR26_2, the voltage divider output node that feeds the comparator's non-inverting input along with feedback resistor R28. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=15.36,63.88,23.77,71.38&zoom=1">R28</a> - 1M 5% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ERJ2GEJ105X) Part Number: `ERJ2GEJ105X` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR2_2 | ✅ | Connected to NetR2_2 (comparator output), providing positive feedback for hysteresis. | | 2 | 2 | NetR26_2 | ✅ | Connected to NetR26_2 (comparator non-inverting input), completing the positive feedback path for hysteresis. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=9.91,65.65,17.41,74.32&zoom=1">R56</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the lower resistor of the voltage divider for VMOT2 monitoring. | | 2 | 2 | NetR26_2 | ✅ | Connected to NetR26_2, the voltage divider output node that feeds the comparator's non-inverting input. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=9.91,74.47,17.41,83.14&zoom=1">R57</a> - 130k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_GROUP_51_ROHS_L.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402JR-07130KL) Part Number: `RC0402JR-07130KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR57_1 | ✅ | Connected to NetR57_1, the reference voltage divider output node that feeds the comparator's inverting input. | | 2 | 2 | 5V0_AUX | ✅ | Connected to 5V0_AUX, forming the upper resistor of the reference voltage divider. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=9.91,77.40,17.41,86.08&zoom=1">R58</a> - 100k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F104CS) Part Number: `RC1005F104CS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the lower resistor of the reference voltage divider. | | 2 | 2 | NetR57_1 | ✅ | Connected to NetR57_1, the reference voltage node that feeds the comparator's inverting input. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=13.54,70.94,26.04,96.07&zoom=1">U6</a> - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/175/1/AP331A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AP331AWG-7) Part Number: `AP331AWG-7` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR57_1 | ✅ | IN- (inverting input) is correctly connected to a reference voltage divider formed by R57 and R58, providing approximately 2.17V reference from 5V0_AUX. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 3 | IN+ | NetR26_2 | ✅ | IN+ (non-inverting input) is correctly connected to a voltage divider monitoring VMOT2, with R26 and R56 setting the threshold and R28 providing hysteresis feedback. | | 4 | OUT | NetR2_2 | ✅ | Output pin is correctly connected to NetR2_2, which serves as an enable signal with pull-up resistor R11 providing the required pull-up for the open-collector output. | | 5 | VCC | VPWR | ✅ | VCC pin is correctly connected to VPWR, providing power supply within the specified 2-36V range. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=36.26,20.97,44.66,28.47&zoom=1">R103</a> - 0R 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/40/1/cr.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CR0603-J_-000ELF) Part Number: `CR0603-J/-000ELF` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | 0-ohm jumper correctly connects VPWR to VFAN, but rated current of 1A may be insufficient for 18 fan connections if high-current fans are used. | | 2 | 2 | VFAN | ✅ | 0-ohm jumper correctly connects VPWR to VFAN, but rated current of 1A may be insufficient for 18 fan connections if high-current fans are used. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=72.15,68.59,83.28,80.79&zoom=1">P1</a> - Header 4X2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/2213S-08G) Part Number: `2213S-08G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | VFAN power pins correctly connected to fan power rail with dual pins for current distribution. | | 3 | 3 | VFAN | ✅ | VFAN power pins correctly connected to fan power rail with dual pins for current distribution. | | 2 | 2 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 4 | 4 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 6 | 6 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 8 | 8 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 5 | 5 | VPWR | ✅ | VPWR power pins correctly connected to main power rail with dual pins for current distribution. | | 7 | 7 | VPWR | ✅ | VPWR power pins correctly connected to main power rail with dual pins for current distribution. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=0.82,15.10,10.14,43.76&zoom=1">J3</a> - 10 Pos barrier ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/4DB-P108-10) Part Number: `4DB-P108-10` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOT2 | ✅ | VMOT2 motor power input correctly connected with TVS protection and filtering capacitors. | | 2 | 2 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 4 | 4 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 6 | 6 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 8 | 8 | GND | ✅ | Ground pins correctly connected with multiple pins for current return path. | | 3 | 3 | VMOT1 | ✅ | VMOT1 motor power input correctly connected with TVS protection and filtering capacitors. | | 5 | 5 | VPWR_IN | ✅ | VPWR_IN main power input correctly connected through fuse F2 to VPWR rail. | | 7 | 7 | VBED_IN | ✅ | VBED_IN heated bed power input correctly connected through fuse F1 to VBED rail. | | 9 | 9 | VBED | ✅ | VBED heated bed power output correctly connected with TVS protection and filtering capacitors. | | 10 | 10 | HTBD-OUT | ✅ | HTBD-OUT heated bed output correctly connected to mosfet control circuitry. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=78.96,56.24,91.91,70.80&zoom=1">J8</a> - USB-B ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/61729-0010BLF) Part Number: `61729-0010BLF` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS | NetC43_2 | ✅ | VBUS pin correctly connected to power filtering network through C43 and FB29 to VUSB. | | 2 | DM | DM | ✅ | USB data pins correctly connected to DM and DP nets with proper ESD protection, but downstream common mode choke L5 causes differential pair swap. | | 3 | DP | DP | ✅ | USB data pins correctly connected to DM and DP nets with proper ESD protection, but downstream common mode choke L5 causes differential pair swap. | | 4 | GND | USB_GND | ✅ | Ground and shield pins correctly connected to USB_GND for isolated USB design. | | 5 | SHLD | USB_GND | ✅ | Ground and shield pins correctly connected to USB_GND for isolated USB design. | | 6 | SHLD | USB_GND | ✅ | Ground and shield pins correctly connected to USB_GND for isolated USB design. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=55.34,57.42,66.47,69.62&zoom=1">L5</a> - DLW21HN900SQ2L ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/DLW21HN900SQ2L) Part Number: `DLW21HN900SQ2L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | NetL5_1 | ✅ | Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines. | | 2 | | NetD27_4 | ✅ | Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines. | | 3 | | NetD27_6 | ✅ | Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines. | | 4 | | NetL5_4 | ✅ | Common mode choke winding configuration causes USB differential pair swap. D- signal enters pin 2 but exits pin 1 to UD_P (D+), and D+ signal enters pin 3 but exits pin 4 to UD_N (D-), reversing the USB data lines. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=67.15,70.35,74.65,80.20&zoom=1">D26</a> - RSB39VTE-17 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RSB39VTE-17) Part Number: `RSB39VTE-17` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides high-voltage discharge path between isolated USB_GND and system GND for isolation protection. | | C | C | USB_GND | ✅ | TVS diode correctly provides high-voltage discharge path between isolated USB_GND and system GND for isolation protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=64.42,57.42,77.37,69.62&zoom=1">D27</a> - PRTR5V0U2F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/PRTR5V0U2F%2C115) Part Number: `PRTR5V0U2F,115` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | DM | ✅ | I/O1 pin correctly receives DM signal from USB connector for ESD protection. | | 2 | | USB_GND | ✅ | Ground pin correctly connected to USB_GND for ESD protection reference. | | 3 | | DP | ✅ | I/O2 pin correctly receives DP signal from USB connector for ESD protection. | | 4 | | NetD27_4 | ✅ | Protected output for I/O1 correctly routes to common mode choke L5 pin 2. | | 5 | | NetC43_2 | ✅ | VBUS pin correctly connected to USB power rail for ESD protection. | | 6 | | NetD27_6 | ✅ | Protected output for I/O2 correctly routes to common mode choke L5 pin 3. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=58.06,49.19,66.47,57.86&zoom=1">C43</a> - GRM155R71H103JA88D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) Part Number: `GRM155R71H103JA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB_GND | ✅ | Decoupling capacitor correctly connected between USB_GND and VBUS for high-frequency filtering. | | 2 | 2 | NetC43_2 | ✅ | Decoupling capacitor correctly connected between USB_GND and VBUS for high-frequency filtering. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=54.43,48.01,63.74,55.51&zoom=1">FB29</a> - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CIS10P121AC) Part Number: `CIS10P121AC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | Ferrite bead correctly filters USB power between connector VBUS and isolated VUSB rail. | | 2 | 2 | NetC43_2 | ✅ | Ferrite bead correctly filters USB power between connector VBUS and isolated VUSB rail. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=31.71,55.07,48.30,70.80&zoom=1">U9</a> - ADuM4160 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ADUM3160BRWZ-RL) Part Number: `ADUM3160BRWZ-RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS1 | VUSB | ✅ | VBUS1 correctly connected to USB bus voltage through ferrite bead from connector. | | 2 | GND1 | USB_GND | ✅ | GND1 pins correctly connected to USB_GND, providing ground reference for upstream side of isolator. | | 8 | GND1 | USB_GND | ✅ | GND1 pins correctly connected to USB_GND, providing ground reference for upstream side of isolator. | | 3 | VDD1 | VDD1 | ✅ | VDD1 is an internal regulator output that requires only external decoupling capacitor C39. No external power source is needed. | | 4 | PDEN | VDD1 | ✅ | PDEN is correctly tied to VDD1 to keep the device enabled during normal operation. | | 5 | SPU | VDD1 | ✅ | SPU is correctly tied to VDD1 for speed and pull-up configuration. | | 6 | UD- 1 | UD_N | ✅ | USB data lines are swapped: UD+ 1 (pin 7) connects to DM (D-) and UD- 1 (pin 6) connects to DP (D+). This polarity inversion will prevent proper USB communication. The connections should be reversed so UD+ connects to DP and UD- connects to DM. | | 7 | UD+ 1 | UD_P | ✅ | USB data lines are swapped: UD+ 1 (pin 7) connects to DM (D-) and UD- 1 (pin 6) connects to DP (D+). This polarity inversion will prevent proper USB communication. The connections should be reversed so UD+ connects to DP and UD- connects to DM. | | 9 | GND2 | GND | ✅ | GND2 pins correctly connected to system ground GND, providing ground reference for downstream (MCU) side of isolator. | | 15 | GND2 | GND | ✅ | GND2 pins correctly connected to system ground GND, providing ground reference for downstream (MCU) side of isolator. | | 10 | UD+ 2 | UI_P | ✅ | MCU-side USB data lines correctly connected: UD+ 2 to DHSDP (D+) and UD- 2 to DHSDM (D-) through series resistors. | | 11 | UD- 2 | UI_N | ✅ | MCU-side USB data lines correctly connected: UD+ 2 to DHSDP (D+) and UD- 2 to DHSDM (D-) through series resistors. | | 12 | PIN | 3.3VCC | ✅ | PIN connected to 3.3VCC while other downstream power pins (VDD2, VBUS2) connect to +3.3VCC. Without datasheet confirmation, it's unclear if PIN should be on the same supply net as VDD2 and VBUS2. | | 13 | SPD | 3.3VCC | ✅ | SPD connected to 3.3VCC, likely for speed configuration control. | | 14 | VDD2 | +3.3VCC | ✅ | VDD2 correctly connected to +3.3VCC supply for downstream side power. | | 16 | VBUS2 | +3.3VCC | ✅ | VBUS2 correctly connected to +3.3VCC, providing VBUS output to MCU side. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=50.79,57.42,60.11,64.92&zoom=1">R43</a> - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_N | ✅ | 24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_N path that incorrectly connects to DP instead of DM. | | 2 | 2 | NetL5_4 | ✅ | 24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_N path that incorrectly connects to DP instead of DM. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=50.79,58.59,60.11,66.09&zoom=1">R46</a> - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_P | ✅ | 24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_P path that incorrectly connects to DM instead of DP. | | 2 | 2 | NetL5_1 | ✅ | 24Ω series resistor correctly specified and placed in USB data path for impedance matching. However, due to upstream swap at U9, this resistor is currently in the UD_P path that incorrectly connects to DM instead of DP. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=48.98,65.65,56.48,74.32&zoom=1">C39</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDD1 | ✅ | 100nF decoupling capacitor correctly placed between VDD1 and USB_GND with appropriate value and voltage rating for decoupling the internal regulator output. | | 2 | 2 | USB_GND | ✅ | 100nF decoupling capacitor correctly placed between VDD1 and USB_GND with appropriate value and voltage rating for decoupling the internal regulator output. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=12.63,57.42,21.95,64.92&zoom=1">R47</a> - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_P | ✅ | Series resistor correctly placed in USB D+ path from isolator to MCU. | | 2 | 2 | UI_P | ✅ | Series resistor correctly placed in USB D+ path from isolator to MCU. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=45.34,65.65,52.84,74.32&zoom=1">C28</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | Decoupling capacitor correctly placed between VUSB and USB_GND with appropriate specifications. | | 2 | 2 | USB_GND | ✅ | Decoupling capacitor correctly placed between VUSB and USB_GND with appropriate specifications. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=51.70,49.19,59.20,57.86&zoom=1">C32</a> - GRM155R60J105KE19D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R60J105KE19D) Part Number: `GRM155R60J105KE19D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | Bulk decoupling capacitor for VUSB with marginal voltage rating. 6.3V rating for 5V USB provides minimal margin; 10V or higher rating recommended for reliability. | | 2 | 2 | USB_GND | ✅ | Bulk decoupling capacitor for VUSB with marginal voltage rating. 6.3V rating for 5V USB provides minimal margin; 10V or higher rating recommended for reliability. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=12.63,58.59,21.95,66.09&zoom=1">R45</a> - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_N | ✅ | Series resistor correctly placed in USB D- path from isolator to MCU. | | 2 | 2 | UI_N | ✅ | Series resistor correctly placed in USB D- path from isolator to MCU. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=25.81,15.68,42.39,38.47&zoom=1">U11B</a> - ATML-ATSAM3X-LQFP-144 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) Part Number: `ATSAM3X8EA-AU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 37 | DHSDP | UMCU_P | ❌ | <details><summary>The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="34.89,19.21,42.39,26.71" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic)</li><li>Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic)</li><li>Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=4">ATSAM3X8EA-AU</a>, page 4)</li><li>DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning)</li><li>USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning)</li><li>Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning)</li><li>The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)</li></ul></details> | | 38 | DHSDM | UMCU_N | ❌ | <details><summary>The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="34.89,22.74,42.39,30.24" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic)</li><li>Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic)</li><li>Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=4">ATSAM3X8EA-AU</a>, page 4)</li><li>DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning)</li><li>USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning)</li><li>Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning)</li><li>The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)</li></ul></details> | | 42 | DFSDP | NetR48_1 | ❌ | <details><summary>The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="34.89,20.39,42.39,27.89" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic)</li><li>Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic)</li><li>Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=4">ATSAM3X8EA-AU</a>, page 4)</li><li>DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning)</li><li>USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning)</li><li>Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning)</li><li>The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)</li></ul></details> | | 43 | DFSDM | NetR42_1 | ❌ | <details><summary>The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="34.89,23.91,42.39,31.41" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic)</li><li>Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic)</li><li>Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=4">ATSAM3X8EA-AU</a>, page 4)</li><li>DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning)</li><li>USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning)</li><li>Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning)</li><li>The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)</li></ul></details> | | 35 | XOUT | NetC41_2 | ✅ | XOUT is correctly connected to the 12MHz crystal (X1) through a 3pF load capacitor (C41). | | 36 | XIN | NetC42_2 | ✅ | XIN is correctly connected to the 12MHz crystal (X1) through a 3pF load capacitor (C42). | | 39 | VBUS | VBUS_UC | ✅ | VBUS is correctly connected to a USB power detection circuit using an optoisolator (U18) and transistor (Q8). | | 40 | VBG | NetC49_1 | ✅ | VBG is connected to a 10pF capacitor (C49) and 6.8kΩ resistor (R49) to ground, providing filtering for the bias voltage reference. | | 46 | JTAGSEL | GND | ✅ | JTAGSEL is correctly tied to GND, ensuring JTAG mode is disabled for normal operation. | | 47 | NRSTB | RESET | ✅ | NRSTB is correctly connected to the RESET net, which is a cross-page signal with connections on other schematic pages. | | 48 | XIN32 | XIN32 | ✅ | XIN32 and XOUT32 are page-local nets with no visible external crystal circuit. The design may be using the internal 32 kHz RC oscillator instead. | | 49 | XOUT32 | XOUT32 | ✅ | XIN32 and XOUT32 are page-local nets with no visible external crystal circuit. The design may be using the internal 32 kHz RC oscillator instead. | | 50 | SHDN | SHDN | ✅ | SHDN is correctly configured as an output pin indicating device operating mode. | | 51 | TST | GND | ✅ | TST is correctly tied to GND, ensuring test mode is disabled for normal operation. | | 53 | FWUP | NetR51_1 | ✅ | FWUP is correctly connected to a 100kΩ external pull-up resistor (R51) to +3.3VCC as required by the datasheet. | | 69 | NRST | NetC169_1 | ✅ | NRST is correctly connected through a 100Ω series resistor (R149) with a 100nF filter capacitor (C169) to ground. | | 75 | ADVREF | VDDANA | ✅ | ADVREF is correctly connected to VDDANA with appropriate decoupling capacitors C76 (100nF) and C77 (10nF). | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=39.44,20.39,48.75,27.89&zoom=1">R48</a> - CRCW040224R0FKED ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR48_1 | ❌ | <details><summary>R48 is part of an incorrect connection between USB high-speed pin DHSDP (pin 37) and full-speed pin DFSDP (pin 42) of U11B.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="39.44,20.39,46.94,27.89" aspect-ratio="1.29" } <ul><li>R48 pin 2 connects to UMCU_P which connects to U11B pin 37 (DHSDP) (from schematic)</li><li>R48 pin 1 connects to NetR48_1 which connects to U11B pin 42 (DFSDP) (from schematic)</li><li>R48 is a 24Ω resistor (from schematic)</li><li>This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)</li></ul></details> | | 2 | 2 | UMCU_P | ❌ | <details><summary>R48 is part of an incorrect connection between USB high-speed pin DHSDP (pin 37) and full-speed pin DFSDP (pin 42) of U11B.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="41.25,20.39,48.75,27.89" aspect-ratio="1.29" } <ul><li>R48 pin 2 connects to UMCU_P which connects to U11B pin 37 (DHSDP) (from schematic)</li><li>R48 pin 1 connects to NetR48_1 which connects to U11B pin 42 (DFSDP) (from schematic)</li><li>R48 is a 24Ω resistor (from schematic)</li><li>This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)</li></ul></details> | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=39.44,34.49,46.94,43.17&zoom=1">C76</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDDANA | ✅ | C76 provides decoupling for VDDANA and ADVREF. | | 2 | 2 | GND | ✅ | C76 provides decoupling for VDDANA and ADVREF. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=36.71,34.49,45.12,43.17&zoom=1">C77</a> - GRM155R71H103JA88D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) Part Number: `GRM155R71H103JA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDDANA | ✅ | C77 provides additional high-frequency decoupling for VDDANA and ADVREF. | | 2 | 2 | GND | ✅ | C77 provides additional high-frequency decoupling for VDDANA and ADVREF. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=39.44,23.91,48.75,31.41&zoom=1">R42</a> - CRCW040224R0FKED ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR42_1 | ❌ | <details><summary>R42 is part of an incorrect connection between USB high-speed pin DHSDM (pin 38) and full-speed pin DFSDM (pin 43) of U11B.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="39.44,23.91,46.94,31.41" aspect-ratio="1.29" } <ul><li>R42 pin 2 connects to UMCU_N which connects to U11B pin 38 (DHSDM) (from schematic)</li><li>R42 pin 1 connects to NetR42_1 which connects to U11B pin 43 (DFSDM) (from schematic)</li><li>R42 is a 24Ω resistor (from schematic)</li><li>This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)</li></ul></details> | | 2 | 2 | UMCU_N | ❌ | <details><summary>R42 is part of an incorrect connection between USB high-speed pin DHSDM (pin 38) and full-speed pin DFSDM (pin 43) of U11B.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="41.25,23.91,48.75,31.41" aspect-ratio="1.29" } <ul><li>R42 pin 2 connects to UMCU_N which connects to U11B pin 38 (DHSDM) (from schematic)</li><li>R42 pin 1 connects to NetR42_1 which connects to U11B pin 43 (DFSDM) (from schematic)</li><li>R42 is a 24Ω resistor (from schematic)</li><li>This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)</li></ul></details> | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=45.80,33.32,54.20,41.99&zoom=1">C49</a> - CL05C100JB5NNNC ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CL05C100JB5NNNC) Part Number: `CL05C100JB5NNNC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC49_1 | ✅ | C49 provides filtering for the VBG bias voltage reference pin of U11B. | | 2 | 2 | GND | ✅ | C49 provides filtering for the VBG bias voltage reference pin of U11B. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=43.07,32.14,50.57,41.99&zoom=1">R49</a> - CRCW04026K80FKED ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW04026K80FKED) Part Number: `CRCW04026K80FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | R49 provides a DC path to ground for the VBG bias voltage reference pin of U11B. | | 2 | 2 | NetC49_1 | ✅ | R49 provides a DC path to ground for the VBG bias voltage reference pin of U11B. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=17.63,39.78,26.95,47.28&zoom=1">R149</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NRST | ✅ | Series resistor terminal correctly connected to external NRST signal for reset line filtering. | | 2 | 2 | NetC169_1 | ✅ | Series resistor terminal correctly connected to MCU NRST pin through RC filter network. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=13.99,27.44,23.31,37.29&zoom=1">X1</a> - 405C35B12M00000 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/405C35B12M00000) Part Number: `405C35B12M00000` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | C1 | NetC42_2 | ✅ | Crystal terminal C1 correctly connects to microcontroller XIN pin through load capacitor C42. | | 2 | GND | GND | ✅ | Crystal ground pins correctly connected to system ground. | | 4 | GND | GND | ✅ | Crystal ground pins correctly connected to system ground. | | 3 | C2 | NetC41_2 | ✅ | Crystal terminal C2 correctly connects to microcontroller XOUT pin through load capacitor C41. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=22.63,41.55,30.13,50.22&zoom=1">C169</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC169_1 | ✅ | Filter capacitor correctly positioned between reset series resistor and microcontroller NRST pin. | | 2 | 2 | GND | ✅ | Filter capacitor correctly grounded to complete RC reset filter. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=13.09,30.14,20.59,38.11&zoom=1">C42</a> - 3pF 0603 50V NP0 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/5926/1/C0GNP0_Dielectric.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/06031A3R0BAT2A) Part Number: `06031A3R0BAT2A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Load capacitor correctly grounded for crystal oscillator circuit. | | 2 | 2 | NetC42_2 | ✅ | Load capacitor correctly connects to XIN and crystal C1 terminal, with value properly calculated for 13pF crystal load. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=11.27,20.39,18.77,30.24&zoom=1">R51</a> - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F104CS) Part Number: `RC1005F104CS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR51_1 | ✅ | Pull-up resistor correctly connects to FWUP pin as required by datasheet. | | 2 | 2 | +3.3VCC | ✅ | Pull-up resistor correctly connects to 3.3V supply to provide required pull-up for FWUP. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=16.72,30.14,24.22,38.11&zoom=1">C41</a> - 3pF 0603 50V NP0 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/5926/1/C0GNP0_Dielectric.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/06031A3R0BAT2A) Part Number: `06031A3R0BAT2A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Load capacitor correctly grounded for crystal oscillator circuit. | | 2 | 2 | NetC41_2 | ✅ | Load capacitor correctly connects to XOUT and crystal C2 terminal, with value properly calculated for 13pF crystal load. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=63.97,18.03,73.28,25.53&zoom=1">R152</a> - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | Current-limiting resistor for optoisolator LED, correctly sized at 1k to provide approximately 3.75mA LED current. | | 2 | 2 | NetR152_2 | ✅ | Current-limiting resistor for optoisolator LED, correctly sized at 1k to provide approximately 3.75mA LED current. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=58.06,18.03,69.65,27.89&zoom=1">U18</a> - OPTO SO-4 OPNDRN OUT ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/105/1/E016A1BEC7455484350515E5384875F115055B145EF3ECA965BD1D77C77A9619.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TLP293%28TPL%2CE) Part Number: `TLP293(TPL,E` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A | NetR152_2 | ✅ | Anode of optoisolator LED, correctly connected through R152 (1k) current-limiting resistor to VUSB for USB presence detection. | | 2 | K | USB_GND | ✅ | Cathode of optoisolator LED, correctly connected to USB_GND on the isolated side. | | 3 | E | GND | ✅ | Emitter of phototransistor output, correctly connected to system GND on the non-isolated side. | | 4 | C | NetQ8_1 | ✅ | Collector of phototransistor output, correctly connected to Q8 base through R151 pull-up resistor for signal inversion. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=57.15,12.74,64.65,22.60&zoom=1">R151</a> - CRCW04026K80FKED ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW04026K80FKED) Part Number: `CRCW04026K80FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetQ8_1 | ✅ | Pull-up resistor for optoisolator output and base resistor for Q8, correctly sized at 6.8k to provide adequate base drive. | | 2 | 2 | +5VCC | ✅ | Pull-up resistor for optoisolator output and base resistor for Q8, correctly sized at 6.8k to provide adequate base drive. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=54.15,17.33,62.38,26.24&zoom=1">Q8</a> - MMBT3904_SOT523 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/175/1/ds30270.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/MMBT3904T-7-F) Part Number: `MMBT3904T-7-F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B | NetQ8_1 | ✅ | Base terminal correctly connected to optoisolator collector output through R151 pull-up, providing signal inversion for VBUS detection. | | 2 | E | GND | ✅ | Emitter terminal correctly connected to GND for common-emitter configuration. | | 3 | C | VBUS_UC | ✅ | Collector terminal correctly connected to VBUS_UC to provide inverted USB presence signal to microcontroller. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=54.15,12.74,61.65,22.60&zoom=1">R150</a> - CRCW04026K80FKED ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW04026K80FKED) Part Number: `CRCW04026K80FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBUS_UC | ✅ | Pull-up resistor for VBUS_UC signal, correctly sized at 6.8k to pull the microcontroller VBUS sense pin high when USB is connected. | | 2 | 2 | +5VCC | ✅ | Pull-up resistor for VBUS_UC signal, correctly sized at 6.8k to pull the microcontroller VBUS sense pin high when USB is connected. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=30.08,0.82,54.04,66.47&zoom=1">U11A</a> - ATML-ATSAM3X-LQFP-144 ❌</summary> DRCY flagged 2 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) Part Number: `ATSAM3X8EA-AU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 24 | PA1/CANRX0/PCK0/WKUP0 | PA1_CANRX0 | ❌ | <details><summary>PA1 (CANRX0) and PA5 (PWM) are incorrectly connected together through R41 (1k). This connection serves no clear functional purpose and will cause signal integrity issues.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="30.08,2.64,37.58,10.14" aspect-ratio="1.55" } <ul><li>Pin 24 is PA1 which can be configured as CANRX0, PCK0, or general I/O with WKUP0 function (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 25 is PA5 which can be configured as TIOA2, PWMFI0, or general I/O with WKUP2 function (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 24 is connected to net PA1_CANRX0 and pin 25 to net PA5_PWM (from schematic)</li><li>R41 (1k) connects PA5_PWM to PA1_CANRX0 (from schematic)</li><li>PA1_CANRX0 and PA5_PWM are both page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0)</li><li>PA1 is typically used as CAN receive input (CANRX0) and PA5 as timer/PWM output (TIOA2/PWMFI0) (reasoning)</li><li>Connecting a CAN receive input to a PWM/timer output through a 1k resistor serves no standard circuit purpose (reasoning)</li><li>If PA5 actively drives PWM signals, it will interfere with CAN reception on PA1 (reasoning)</li><li>If PA1 receives CAN data, the 1k resistor connection to PA5 will load the CAN bus and may cause communication errors (reasoning)</li><li>PA5_PWM has no other connections besides R41, suggesting it is not used for any intended function (from schematic)</li><li>R41 should be removed and the connection between PA1 and PA5 eliminated (reasoning)</li></ul></details> | | 25 | PA5/TIOA2/PWMFI0/WKUP2 | PA5_PWM | ❌ | <details><summary>PA1 (CANRX0) and PA5 (PWM) are incorrectly connected together through R41 (1k). This connection serves no clear functional purpose and will cause signal integrity issues.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="30.08,6.27,37.58,13.77" aspect-ratio="1.55" } <ul><li>Pin 24 is PA1 which can be configured as CANRX0, PCK0, or general I/O with WKUP0 function (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 25 is PA5 which can be configured as TIOA2, PWMFI0, or general I/O with WKUP2 function (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 24 is connected to net PA1_CANRX0 and pin 25 to net PA5_PWM (from schematic)</li><li>R41 (1k) connects PA5_PWM to PA1_CANRX0 (from schematic)</li><li>PA1_CANRX0 and PA5_PWM are both page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0)</li><li>PA1 is typically used as CAN receive input (CANRX0) and PA5 as timer/PWM output (TIOA2/PWMFI0) (reasoning)</li><li>Connecting a CAN receive input to a PWM/timer output through a 1k resistor serves no standard circuit purpose (reasoning)</li><li>If PA5 actively drives PWM signals, it will interfere with CAN reception on PA1 (reasoning)</li><li>If PA1 receives CAN data, the 1k resistor connection to PA5 will load the CAN bus and may cause communication errors (reasoning)</li><li>PA5_PWM has no other connections besides R41, suggesting it is not used for any intended function (from schematic)</li><li>R41 should be removed and the connection between PA1 and PA5 eliminated (reasoning)</li></ul></details> | | 29 | PB29/TDI | TDO/SWO | ❌ | <details><summary>PB29 (TDI) and PB30 (TDO) are swapped - TDI pin connected to TDO/SWO net and TDO pin connected to TDI net.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.08,54.04,35.58" aspect-ratio="1.55" } <ul><li>Pin 29 is PB29 which is TDI after reset (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 30 is PB30 which is TDO/TRACESWO after reset (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 29 is connected to net TDO/SWO (from schematic)</li><li>Pin 30 is connected to net TDI (from schematic)</li><li>TDO/SWO net connects to J4 pin 6 (from schematic)</li><li>TDI net connects to J4 pin 8 (from schematic)</li><li>In JTAG standard, TDI is input to target and TDO is output from target (reasoning)</li><li>The MCU TDI pin should connect to the connector TDI pin, and MCU TDO should connect to connector TDO (reasoning)</li><li>The connections are swapped - pin 29 (TDI) should connect to TDI net, and pin 30 (TDO) should connect to TDO/SWO net (reasoning)</li><li>This swap will prevent JTAG debugging from functioning correctly (reasoning)</li></ul></details> | | 30 | PB30/TDO/TRACESWO | TDI | ❌ | <details><summary>PB29 (TDI) and PB30 (TDO) are swapped - TDI pin connected to TDO/SWO net and TDO pin connected to TDI net.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.99,54.04,36.49" aspect-ratio="1.55" } <ul><li>Pin 29 is PB29 which is TDI after reset (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 30 is PB30 which is TDO/TRACESWO after reset (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Pin 29 is connected to net TDO/SWO (from schematic)</li><li>Pin 30 is connected to net TDI (from schematic)</li><li>TDO/SWO net connects to J4 pin 6 (from schematic)</li><li>TDI net connects to J4 pin 8 (from schematic)</li><li>In JTAG standard, TDI is input to target and TDO is output from target (reasoning)</li><li>The MCU TDI pin should connect to the connector TDI pin, and MCU TDO should connect to connector TDO (reasoning)</li><li>The connections are swapped - pin 29 (TDI) should connect to TDI net, and pin 30 (TDO) should connect to TDO/SWO net (reasoning)</li><li>This swap will prevent JTAG debugging from functioning correctly (reasoning)</li></ul></details> | | 1 | PB26/CTS0/TCLK0/WKUP15 | STEP6 | ✅ | PB26 configured as STEP6 output for stepper motor control. | | 2 | PA9/UTXD/PWMH3 | PA9_UTXD | ✅ | PA9 configured as UTXD for UART transmit. | | 3 | PA10/RXD0/DATRG/WKUP5 | DIAG7 | ✅ | PA10 and PA11 configured as DIAG7 and DIAG8 diagnostic inputs. | | 4 | PA11/TXD0/ADTRG/WKUP6 | DIAG8 | ✅ | PA10 and PA11 configured as DIAG7 and DIAG8 diagnostic inputs. | | 5 | PA12/RXD1/PWML1/WKUP7 | PA12_RXD1 | ✅ | PA12 and PA13 configured as RXD1 and TXD1 for UART1. | | 6 | PA13/TXD1/PWMH2 | PA13_TXD1 | ✅ | PA12 and PA13 configured as RXD1 and TXD1 for UART1. | | 7 | PA14/RTS1/TK | PA14_RTS1 | ✅ | PA14 and PA15 configured as RTS1 and CTS1 for UART1 flow control. | | 8 | PA15/CTS1/TF/WKUP8 | PA15_CTS1 | ✅ | PA14 and PA15 configured as RTS1 and CTS1 for UART1 flow control. | | 9 | PA17/TWD0/SPCK0 | PA17_SDA | ✅ | PA17 and PA18 configured as TWD0/SDA and TWCK0/SCL for I2C interface with proper pull-ups. | | 70 | PA18/TWCK0/A20/WKUP9 | PA18_SCL | ✅ | PA17 and PA18 configured as TWD0/SDA and TWCK0/SCL for I2C interface with proper pull-ups. | | 13 | PD0/A10/MCDA4 | M_nCS7 | ✅ | Port D pins configured for motor control and endstop signals. | | 14 | PD1/A11/MCDA5 | DIR8 | ✅ | Port D pins configured for motor control and endstop signals. | | 15 | PD2/A12/MCDA6 | M_nCS8 | ✅ | Port D pins configured for motor control and endstop signals. | | 16 | PD3/A13/MCDA7 | STEP8 | ✅ | Port D pins configured for motor control and endstop signals. | | 17 | PD4/A14/TXD3 | MIN_ES1 | ✅ | Port D pins configured for motor control and endstop signals. | | 18 | PD5/A15/RXD3 | MAX_ES2 | ✅ | Port D pins configured for motor control and endstop signals. | | 19 | PD6/A16/BA0/PWMFI2 | MIN_ES2 | ✅ | Port D pins configured for motor control and endstop signals. | | 20 | PD7/A17/BA1/TIOA8 | TACH_3 | ✅ | Port D pins configured for motor control and endstop signals. | | 21 | PD8/A21/NANDALE/TIOB8 | TACH_2 | ✅ | Port D pins configured for motor control and endstop signals. | | 22 | PD9/A22/NANDCLE/TCLK8 | MAX_ES3 | ✅ | Port D pins configured for motor control and endstop signals. | | 32 | PD10/NWR1/NBS1 | MAX_ES1 | ✅ | Port D pins configured for motor control and endstop signals. | | 23 | PA0/CANTX0/PWML3 | PA0_CANTX0 | ✅ | PA0 configured as CANTX0 for CAN transmit. | | 26 | PA7/TCLK2/NCS1/WKUP3 | MIN_ES3 | ✅ | PA7 configured as MIN_ES3 endstop input. | | 27 | PA8/URXD/PWMH0/WKUP4 | PA8_URXD | ✅ | PA8 configured as URXD for UART receive. | | 28 | PB28/TCK/SWCLK | TCK/SWDCLK | ✅ | PB28 (TCK/SWCLK) and PB31 (TMS/SWDIO) correctly connected for SWD debug interface. | | 31 | PB31/TMS/SWDIO | TMS/SWDIO | ✅ | PB28 (TCK/SWCLK) and PB31 (TMS/SWDIO) correctly connected for SWD debug interface. | | 55 | PC1 | LED_Y | ✅ | PC1 configured as general I/O for LED control (LED_Y). | | 59 | PC2/D0/PWML0 | PC2_PWML0 | ✅ | PC2 configured for PWM function (PWML0). | | 60 | PC3/D1/PWMH0 | LED_R | ✅ | PC3 configured as general I/O for LED control (LED_R). | | 63 | PC5/D3/PWMH1 | DIAG1 | ✅ | PC5 configured as general I/O for motor diagnostic signal (DIAG1). | | 64 | PC6/D4/PWML2 | DIR1 | ✅ | PC6 configured as general I/O for motor direction control (DIR1). | | 65 | PC7/D5/PWMH2 | STEP1 | ✅ | PC7 configured as general I/O for motor step control (STEP1). | | 66 | PC8/D6/PWML3 | PC8_PWML3 | ✅ | PC8 configured for PWM function (PWML3). | | 67 | PC9/D7/PWMH3 | DRV_EN | ✅ | PC9 configured as general I/O for motor driver enable control (DRV_EN). | | 68 | PB27/NCS3/TIOB0 | PB27_TIOB0 | ✅ | PB27 configured as timer I/O (TIOB0). | | 71 | PA19/MCCK/PWMH1 | MCCK | ✅ | SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors. | | 72 | PA20/MCCDA/PWML2 | MCCDA | ✅ | SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors. | | 79 | PA24/MCDA3/PCK1/AD6 | MCDA3 | ✅ | SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors. | | 80 | PA23/MCDA2/TCLK4/AD5 | MCDA2 | ✅ | SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors. | | 81 | PA22/MCDA1/TCLK3/AD4 | MCDA1 | ✅ | SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors. | | 107 | PA21/MCDA0/PWML0 | MCDA0 | ✅ | SD card interface pins (MCCK, MCCDA, MCDA0-3) correctly configured with pull-up resistors. | | 76 | PB15/CANRX1/PWMH3/DAC0/WKUP12 | Fan3 | ✅ | PB15 and PB16 configured as DAC outputs for fan control. | | 77 | PB16/TCLK5/PWML0/DAC1 | Fan4 | ✅ | PB15 and PB16 configured as DAC outputs for fan control. | | 78 | PA16/SPCK1/TD/AD7 | PA16 | ✅ | PA16 configured as general I/O. | | 82 | PA6/TIOB2/NCS0/AD3 | TC_nCS3 | ✅ | PA2-PA6 configured for motor control chip selects and analog inputs. | | 83 | PA4/TCLK1/NWAIT/AD2 | M_nCS1 | ✅ | PA2-PA6 configured for motor control chip selects and analog inputs. | | 84 | PA3/TIOB1/PWMFI1/AD1/WKUP1 | PA3_AD2 | ✅ | PA2-PA6 configured for motor control chip selects and analog inputs. | | 85 | PA2/TIOA1/NANDRDY/AD0 | TC_nCS4 | ✅ | PA2-PA6 configured for motor control chip selects and analog inputs. | | 86 | PB12/TWD1/PWMH0/AD8 | PB12_AD8 | ✅ | PB12 and PB13 configured as ADC inputs and I2C alternate function. | | 87 | PB13/TWCK1/PWMH1/AD9 | PB13_AD9 | ✅ | PB12 and PB13 configured as ADC inputs and I2C alternate function. | | 88 | PB17/RF/PWML1/AD10 | TC_nCS5 | ✅ | PB17 configured as TC_nCS5 chip select output. | | 89 | PB18/RD/PWML2/AD11 | THERM_AN2 | ✅ | PB18, PB19, PB20 configured as ADC inputs for thermistor readings. | | 90 | PB19/RK/PWML3/AD12 | THERM_AN1 | ✅ | PB18, PB19, PB20 configured as ADC inputs for thermistor readings. | | 91 | PB20/TXD2/SPI0_NPCS1/AD13 | THERM_AN3 | ✅ | PB18, PB19, PB20 configured as ADC inputs for thermistor readings. | | 92 | PB21/RXD2/SPI0_NPCS2/AD14/WKUP13 | SPIFLASH_CS | ✅ | PB21 configured as SPI flash chip select. | | 93 | PC11/D9/ERX2 | DIAG2 | ✅ | Port C pins 11-17 configured for motor control and Ethernet alternate functions. | | 94 | PC12/D10/ERX3 | DIR2 | ✅ | Port C pins 11-17 configured for motor control and Ethernet alternate functions. | | 95 | PC13/D11/ECOL | STEP2 | ✅ | Port C pins 11-17 configured for motor control and Ethernet alternate functions. | | 96 | PC14/D12/ERXCK | M_nCS2 | ✅ | Port C pins 11-17 configured for motor control and Ethernet alternate functions. | | 97 | PC15/D13/ETX2 | DIAG3 | ✅ | Port C pins 11-17 configured for motor control and Ethernet alternate functions. | | 98 | PC16/D14/ETX3 | DIR3 | ✅ | Port C pins 11-17 configured for motor control and Ethernet alternate functions. | | 99 | PC17/D15/ETXER | STEP3 | ✅ | Port C pins 11-17 configured for motor control and Ethernet alternate functions. | | 100 | PC18/NWR0/NWE/PWMH6 | M_nCS3 | ✅ | PC18 and PC19 configured for motor control chip selects and diagnostics. | | 101 | PC19/NANDOE/PWMH5 | DIAG4 | ✅ | PC18 and PC19 configured for motor control chip selects and diagnostics. | | 102 | PC29/A8/TIOB7 | TACH_4 | ✅ | PC29 and PC30 configured for tachometer input and SPI hold signal. | | 103 | PC30/A9/TCLK7 | HOLD# | ✅ | PC29 and PC30 configured for tachometer input and SPI hold signal. | | 108 | PA25/SPI0_MISO/A18 | NetR83_2 | ✅ | SPI0 interface pins (MISO, MOSI, SPCK) correctly configured with series termination resistors. | | 109 | PA26/SPI0_MOSI/A19 | NetR77_2 | ✅ | SPI0 interface pins (MISO, MOSI, SPCK) correctly configured with series termination resistors. | | 110 | PA27/SPI0_SPCK/A20/WKUP10 | NetR82_2 | ✅ | SPI0 interface pins (MISO, MOSI, SPCK) correctly configured with series termination resistors. | | 111 | PA28/SPI0_NPCS0/PCK2/WKUP11 | PA28_CS0 | ✅ | SPI0 chip select pins correctly configured. | | 112 | PA29/SPI0_NPCS1/NRD | PA29_CS | ✅ | SPI0 chip select pins correctly configured. | | 113 | PB0/ETXCK/EREFCK | PB0_ETXCK | ✅ | Ethernet pins repurposed for motor control outputs. | | 114 | PB1/ETXEN | PB1_ETXEN | ✅ | Ethernet pins repurposed for motor control outputs. | | 115 | PB2/ETX0 | PB2_ETX0 | ✅ | Ethernet pins repurposed for motor control outputs. | | 116 | PC4/D2/PWML1 | DIR4 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 117 | PC10/D8/ECRS | STEP4 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 118 | PB3/ETX1 | STEP5 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 119 | PB4/ECRSDV/ERXDV | M_nCS6 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 120 | PB5/ERX0 | M_nCS5 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 121 | PB6/ERX1 | DIR7 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 122 | PB7/ERXER | MAX_ES4 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 123 | PB8/EMDC | STEP7 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 127 | PB9/EMDIO | TC_nCS2 | ✅ | Ethernet and Port B pins repurposed for motor control signals. | | 128 | PB10/UOTGVBOF/A18 | M_nCS4 | ✅ | PB10 and PB11 configured for motor chip select and SD card detect. | | 129 | PB11/UOTGID/A19 | SDCD | ✅ | PB10 and PB11 configured for motor chip select and SD card detect. | | 130 | PC0/ERASE | ERASE | ✅ | PC0 ERASE pin correctly configured with switch and ESD protection. | | 131 | PC20/NANDWE/PWMH4 | DIAG5 | ✅ | Port C pins 20-24 configured for heater control outputs. | | 132 | PC21/A0/NBS0/PWML4 | Heat1 | ✅ | Port C pins 20-24 configured for heater control outputs. | | 133 | PC22/A1/PWML5 | Heat2 | ✅ | Port C pins 20-24 configured for heater control outputs. | | 134 | PC23/A2/PWML6 | HeatBed | ✅ | Port C pins 20-24 configured for heater control outputs. | | 135 | PC24/A3/PWML7 | Heat3 | ✅ | Port C pins 20-24 configured for heater control outputs. | | 136 | PC25/A4/TIOA6 | Fan2 | ✅ | Port C pins 25-28 configured for fan control and tachometer inputs. | | 137 | PC26/A5/TIOB6 | Fan1 | ✅ | Port C pins 25-28 configured for fan control and tachometer inputs. | | 138 | PC27/A6/TCLK6 | TC_nCS1 | ✅ | Port C pins 25-28 configured for fan control and tachometer inputs. | | 139 | PC28/A7/TIOA7 | TACH_1 | ✅ | Port C pins 25-28 configured for fan control and tachometer inputs. | | 140 | PB14/CANTX1/PWMH2 | MIN_ES4 | ✅ | PB14 configured as MIN_ES4 endstop input. | | 141 | PB22/RTS2/PCK0 | DIR5 | ✅ | Port B pins 22-25 configured for motor control signals. | | 142 | PB23/CTS2/SPI0_NPCS3/WKUP14 | DIAG6 | ✅ | Port B pins 22-25 configured for motor control signals. | | 143 | PB24/SCK2/NCS2 | DIR6 | ✅ | Port B pins 22-25 configured for motor control signals. | | 144 | PB25/RTS0/TIOA0 | PB25_TIOA0 | ✅ | Port B pins 22-25 configured for motor control signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=15.38,69.42,29.93,89.64&zoom=1">U11C</a> - ATML-ATSAM3X-LQFP-144 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) Part Number: `ATSAM3X8EA-AU` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to internal voltage regulator output VDDOUT. | | 45 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to internal voltage regulator output VDDOUT. | | 61 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to internal voltage regulator output VDDOUT. | | 104 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to internal voltage regulator output VDDOUT. | | 124 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to internal voltage regulator output VDDOUT. | | 11 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO peripheral I/O supply. | | 62 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO peripheral I/O supply. | | 105 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO peripheral I/O supply. | | 125 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO peripheral I/O supply. | | 12 | GND | GND | ✅ | GND pins correctly connected to ground plane. | | 58 | GND | GND | ✅ | GND pins correctly connected to ground plane. | | 106 | GND | GND | ✅ | GND pins correctly connected to ground plane. | | 126 | GND | GND | ✅ | GND pins correctly connected to ground plane. | | 33 | GNDPLL | GND | ✅ | GNDPLL correctly connected to ground for PLL and oscillator. | | 34 | VDDPLL | VDDPLL | ✅ | VDDPLL correctly connected through ferrite bead from VDDOUT for noise isolation. | | 41 | VDDUTMI | VDDUTMI | ✅ | VDDUTMI correctly connected through ferrite bead from 3.3VCC for USB interface. | | 44 | GNDUTMI | GND | ✅ | GNDUTMI correctly connected to ground for USB interface. | | 52 | VDDBU | 3.3VCC | ✅ | VDDBU correctly connected to 3.3VCC for backup power supply. | | 54 | GNDBU | GND | ✅ | GNDBU correctly connected to ground for backup supply. | | 56 | VDDOUT | VDDOUT | ✅ | VDDOUT correctly connected to voltage regulator output with proper decoupling. | | 57 | VDDIN | 3.3VCC | ✅ | VDDIN correctly connected to 3.3VCC with proper input decoupling capacitor. | | 73 | VDDANA | VDDANA | ✅ | VDDANA correctly connected through ferrite bead from 3.3VCC for analog supply. | | 74 | GNDANA | GND | ✅ | GNDANA correctly connected to ground for analog supply. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=8.32,71.24,17.00,78.74&zoom=1">FB26</a> - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CIS10P121AC) Part Number: `CIS10P121AC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDDPLL | ✅ | Pin 1 connects to VDDPLL, the PLL power supply input. This connection is correct. | | 2 | 2 | VDDOUT | ✅ | Pin 2 connects to VDDOUT, the voltage regulator output. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.15,66.69,15.23,75.10&zoom=1">C57</a> - C1608JB0J106K080AB ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C1608JB0J106K080AB) Part Number: `C1608JB0J106K080AB` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This connection is correct. | | 2 | 2 | 3.3VCC | ✅ | Pin 2 connects to 3.3VCC, providing required input decoupling capacitance. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=1.85,78.51,9.94,86.91&zoom=1">C72</a> - C1608JB0J106K080AB ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C1608JB0J106K080AB) Part Number: `C1608JB0J106K080AB` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This connection is correct. | | 2 | 2 | VDDANA | ✅ | Pin 2 connects to VDDANA, providing bulk decoupling capacitance. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=0.00,77.60,8.47,85.10&zoom=1">FB27</a> - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CIS10P121AC) Part Number: `CIS10P121AC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pin 1 connects to 3.3VCC, the main 3.3V supply. This connection is correct. | | 2 | 2 | VDDANA | ✅ | Pin 2 connects to VDDANA, the analog power supply for ADC and DAC. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=12.44,86.68,20.53,95.09&zoom=1">C55</a> - C1608JB0J106K080AB ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C1608JB0J106K080AB) Part Number: `C1608JB0J106K080AB` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This connection is correct. | | 2 | 2 | VDDOUT | ✅ | Pin 2 connects to VDDOUT, providing required output decoupling capacitance. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=4.79,72.15,12.88,80.55&zoom=1">C37</a> - C1608JB0J106K080AB ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C1608JB0J106K080AB) Part Number: `C1608JB0J106K080AB` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This connection is correct. | | 2 | 2 | VDDPLL | ✅ | Pin 2 connects to VDDPLL, providing bulk decoupling capacitance. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=24.20,67.15,31.70,76.46&zoom=1">FB28</a> - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CIS10P121AC) Part Number: `CIS10P121AC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Pin 1 connects to 3.3VIO, the I/O power supply. This connection is correct. | | 2 | 2 | 3.3VCC | ✅ | Pin 2 connects to 3.3VCC, the main 3.3V supply. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=1.85,88.50,10.53,96.00&zoom=1">FB30</a> - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CIS10P121AC) Part Number: `CIS10P121AC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pin 1 connects to 3.3VCC, the main 3.3V supply. This connection is correct. | | 2 | 2 | VDDUTMI | ✅ | Pin 2 connects to VDDUTMI, the USB power supply. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.38,89.41,13.47,97.82&zoom=1">C53</a> - C1608JB0J106K080AB ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C1608JB0J106K080AB) Part Number: `C1608JB0J106K080AB` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This connection is correct. | | 2 | 2 | VDDUTMI | ✅ | Pin 2 connects to VDDUTMI, providing bulk decoupling capacitance. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=29.20,70.33,36.70,79.65&zoom=1">R31</a> - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F104CS) Part Number: `RC1005F104CS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TMS/SWDIO | ✅ | 100K pull-up resistor correctly connected between TMS/SWDIO debug signal and 3.3VCC. | | 2 | 2 | 3.3VCC | ✅ | 100K pull-up resistor correctly connected between TMS/SWDIO debug signal and 3.3VCC. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=31.55,69.42,39.05,78.74&zoom=1">R38</a> - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F104CS) Part Number: `RC1005F104CS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TCK/SWDCLK | ✅ | 100K pull-up resistor correctly connected between TCK/SWDCLK debug clock signal and 3.3VCC. | | 2 | 2 | 3.3VCC | ✅ | 100K pull-up resistor correctly connected between TCK/SWDCLK debug clock signal and 3.3VCC. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=39.19,69.42,49.05,80.55&zoom=1">J4</a> - ARM Cortex JTAG-DEBUG Header ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/20021121-00010C4LF) Part Number: `20021121-00010C4LF` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | VTref pin correctly connected to 3.3VCC to provide target voltage reference for the debug probe. | | 2 | 2 | TMS/SWDIO | ✅ | TMS/SWDIO signal correctly connected to microcontroller debug pin with 100K pull-up resistor R31. | | 3 | 3 | GND | ✅ | Ground pin correctly connected to GND. | | 4 | 4 | TCK/SWDCLK | ✅ | TCK/SWDCLK signal correctly connected to microcontroller debug clock pin with 100K pull-up resistor R38. | | 5 | 5 | GND | ✅ | Ground pin correctly connected to GND. | | 6 | 6 | TDO/SWO | ✅ | TDO/SWO signal correctly connected to microcontroller trace output pin. | | 7 | 7 | NetJ4_7 | ✅ | Pin intentionally left unconnected as key pin per standard ARM debug connector convention. | | 8 | 8 | TDI | ✅ | TDI signal correctly connected to microcontroller debug data input pin with 100K pull-up resistor R37. | | 9 | 9 | GND | ✅ | Ground pin correctly connected to GND. | | 10 | 10 | RESET | ✅ | Reset signal correctly connected to system reset net. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=33.31,67.60,40.81,76.92&zoom=1">R37</a> - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F104CS) Part Number: `RC1005F104CS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TDI | ✅ | 100K pull-up resistor correctly connected between TDI debug signal and 3.3VCC. | | 2 | 2 | 3.3VCC | ✅ | 100K pull-up resistor correctly connected between TDI debug signal and 3.3VCC. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=24.20,29.44,34.05,37.85&zoom=1">S2</a> - KMR741NG ULC LFS ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/KMR741NG%20ULC%20LFS) Part Number: `KMR741NG ULC LFS` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | | NetS2_2 | ❌ | <details><summary>Pins 2 and 4 are connected to page-local nets NetS2_2 and NetS2_4 respectively, which have no other connections, leaving these pins floating. Without the component datasheet to verify the internal pinout, this configuration is uncertain and potentially incorrect. Best practice is to explicitly connect pin 2 to 3.3VCC (same as pin 1) and pin 4 to ERASE (same as pin 3) to ensure proper switch operation regardless of the actual internal pinout.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="24.20,30.35,31.70,37.85" aspect-ratio="1.55" } <ul><li>Pin 2 is connected to net NetS2_2 (from schematic)</li><li>Pin 4 is connected to net NetS2_4 (from schematic)</li><li>NetS2_2 and NetS2_4 are page-local nets with no other connections on this page or any other page (from whole-design connectivity for NetS2_2)</li><li>The component is described as 'Tactile Switch SPST-NO Top Actuated Surface Mount', indicating a single-pole single-throw normally-open switch (from schematic)</li><li>In typical 4-pin tactile switches, pins are arranged in two pairs where each pair is internally connected, with two common configurations: pins 1-2 as one terminal and 3-4 as the other, or pins 1-4 as one terminal and 2-3 as the other (reasoning)</li><li>If the switch pinout is 1-2 / 3-4 (most common for KMR741 series), the current configuration would work because pin 2 is internally connected to pin 1 (3.3VCC) and pin 4 is internally connected to pin 3 (ERASE), making the floating nets functionally acceptable (reasoning)</li><li>If the switch pinout is 1-4 / 2-3 (alternative configuration), the current configuration would not work because pressing the button would connect pin 1 (3.3VCC) to pin 2 (floating NetS2_2) and pin 3 (ERASE) to pin 4 (floating NetS2_4), preventing ERASE from being pulled high (reasoning)</li><li>Without the component datasheet to verify the actual pinout, there is uncertainty about whether the current configuration will function correctly (reasoning)</li><li>Best practice for 4-pin tactile switches is to explicitly connect both pins of each terminal pair to ensure proper operation regardless of the internal pinout: pin 2 should be connected to 3.3VCC (same as pin 1) and pin 4 should be connected to ERASE (same as pin 3) (reasoning)</li><li>Explicitly connecting all four pins would guarantee functionality with either possible pinout configuration and eliminate any ambiguity (reasoning)</li></ul></details> | | 4 | | NetS2_4 | ❌ | <details><summary>Pins 2 and 4 are connected to page-local nets NetS2_2 and NetS2_4 respectively, which have no other connections, leaving these pins floating. Without the component datasheet to verify the internal pinout, this configuration is uncertain and potentially incorrect. Best practice is to explicitly connect pin 2 to 3.3VCC (same as pin 1) and pin 4 to ERASE (same as pin 3) to ensure proper switch operation regardless of the actual internal pinout.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="26.55,30.35,34.05,37.85" aspect-ratio="1.55" } <ul><li>Pin 2 is connected to net NetS2_2 (from schematic)</li><li>Pin 4 is connected to net NetS2_4 (from schematic)</li><li>NetS2_2 and NetS2_4 are page-local nets with no other connections on this page or any other page (from whole-design connectivity for NetS2_2)</li><li>The component is described as 'Tactile Switch SPST-NO Top Actuated Surface Mount', indicating a single-pole single-throw normally-open switch (from schematic)</li><li>In typical 4-pin tactile switches, pins are arranged in two pairs where each pair is internally connected, with two common configurations: pins 1-2 as one terminal and 3-4 as the other, or pins 1-4 as one terminal and 2-3 as the other (reasoning)</li><li>If the switch pinout is 1-2 / 3-4 (most common for KMR741 series), the current configuration would work because pin 2 is internally connected to pin 1 (3.3VCC) and pin 4 is internally connected to pin 3 (ERASE), making the floating nets functionally acceptable (reasoning)</li><li>If the switch pinout is 1-4 / 2-3 (alternative configuration), the current configuration would not work because pressing the button would connect pin 1 (3.3VCC) to pin 2 (floating NetS2_2) and pin 3 (ERASE) to pin 4 (floating NetS2_4), preventing ERASE from being pulled high (reasoning)</li><li>Without the component datasheet to verify the actual pinout, there is uncertainty about whether the current configuration will function correctly (reasoning)</li><li>Best practice for 4-pin tactile switches is to explicitly connect both pins of each terminal pair to ensure proper operation regardless of the internal pinout: pin 2 should be connected to 3.3VCC (same as pin 1) and pin 4 should be connected to ERASE (same as pin 3) (reasoning)</li><li>Explicitly connecting all four pins would guarantee functionality with either possible pinout configuration and eliminate any ambiguity (reasoning)</li></ul></details> | | 1 | | 3.3VCC | ✅ | Pin 1 connects to 3.3VCC and provides the high voltage source for the erase function when the button is pressed. This connection is correct. | | 3 | | ERASE | ✅ | Pin 3 connects to the ERASE net, which is pulled high through the switch when the button is pressed. This connection is correct for the erase button function. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=73.89,46.25,81.98,53.75&zoom=1">D1</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connects to GND and provides the reference for ESD clamping. | | C | C | ERASE | ✅ | Cathode connects to ERASE and provides ESD protection for the erase pin. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=84.47,27.62,93.15,38.76&zoom=1">S1</a> - 1571610-2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/1571610-2) Part Number: `1571610-2` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | RESET | ✅ | Pin P connects to RESET net and serves as the active pole of the reset button. When pressed, it pulls RESET to ground through the other pins. | | 2 | S | GND | ✅ | Pins S, 3, and 4 all connect to GND and provide the ground reference for the switch. Multiple ground pins provide mechanical stability. | | 3 | 3 | GND | ✅ | Pins S, 3, and 4 all connect to GND and provide the ground reference for the switch. Multiple ground pins provide mechanical stability. | | 4 | 4 | GND | ✅ | Pins S, 3, and 4 all connect to GND and provide the ground reference for the switch. Multiple ground pins provide mechanical stability. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=80.36,24.90,88.44,33.31&zoom=1">C40</a> - GRM155R71H103JA88D ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) Part Number: `GRM155R71H103JA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESET | ✅ | Pin 1 connects to RESET and provides filtering for the reset signal. | | 2 | 2 | 3.3VIO | ✅ | Pin 2 connects to 3.3VIO and forms a filter network with the assumed pull-up resistor on RESET. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=66.24,65.33,77.86,77.37&zoom=1">U12</a> - AT25SF161-SSHD-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AT25SF161-SSHD-T) Part Number: `AT25SF161-SSHD-T` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPIFLASH_CS | ✅ | CS# (Chip Select) is connected to SPIFLASH_CS through a diode OR configuration with CS_M1BUS via D77, allowing the flash to be selected when CS_M1BUS goes low. | | 2 | SO | MISO_M1BUS | ✅ | SO (Serial Output) is correctly connected to MISO_M1BUS, the SPI Master In Slave Out line for the M1 bus. | | 3 | WP# | WP# | ✅ | WP# (Write Protect) is correctly pulled high to 3.3VCC through R85 (10K), disabling write protection by default. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 5 | SI/IO0 | MOSI_M1BUS | ✅ | SI/IO0 (Serial Input) is correctly connected to MOSI_M1BUS, the SPI Master Out Slave In line for the M1 bus. | | 6 | SCK | SCLK_M1BUS | ✅ | SCK (Serial Clock) is correctly connected to SCLK_M1BUS, the SPI clock line for the M1 bus. | | 7 | HOLD# | HOLD# | ✅ | HOLD# is connected to microcontroller GPIO PC30 (U11A pin 103) for active firmware control. While the design relies on the microcontroller's internal pull-up resistors, an external pull-up would provide more robust operation and consistency with the WP# design approach. | | 8 | VCC | 3.3VCC | ✅ | VCC is correctly connected to 3.3VCC, which is within the typical 2.7V to 3.6V operating range for SPI flash memories. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=55.66,68.96,64.33,76.46&zoom=1">R85</a> - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | WP# | ✅ | R85 forms a 10K pull-up resistor from WP# (pin 1) to 3.3VCC (pin 2), correctly disabling write protection by default on the SPI flash. | | 2 | 2 | 3.3VCC | ✅ | R85 forms a 10K pull-up resistor from WP# (pin 1) to 3.3VCC (pin 2), correctly disabling write protection by default on the SPI flash. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.44,35.80,15.53,43.30&zoom=1">R3</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_TCBUS | ✅ | Series termination resistor correctly positioned between clock buffer output Y1 and SCLK_TCBUS with appropriate 47Ω value for impedance matching and signal integrity. | | 2 | 2 | NetR3_2 | ✅ | Series termination resistor correctly positioned between clock buffer output Y1 and SCLK_TCBUS with appropriate 47Ω value for impedance matching and signal integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.44,37.62,15.53,45.12&zoom=1">R4</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA27_SCLK | ✅ | Series termination resistor correctly positioned between clock buffer output Y2 and PA27_SCLK with appropriate 47Ω value for impedance matching and signal integrity. | | 2 | 2 | NetR4_2 | ✅ | Series termination resistor correctly positioned between clock buffer output Y2 and PA27_SCLK with appropriate 47Ω value for impedance matching and signal integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.44,39.44,15.53,46.94&zoom=1">R13</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_M1BUS | ✅ | Series termination resistor correctly positioned between clock buffer output Y3 and SCLK_M1BUS with appropriate 47Ω value for impedance matching and signal integrity. | | 2 | 2 | NetR13_2 | ✅ | Series termination resistor correctly positioned between clock buffer output Y3 and SCLK_M1BUS with appropriate 47Ω value for impedance matching and signal integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.44,41.25,15.53,48.75&zoom=1">R32</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_M2BUS | ✅ | Series termination resistor correctly positioned between clock buffer output Y4 and SCLK_M2BUS with appropriate 47Ω value for impedance matching and signal integrity. | | 2 | 2 | NetR32_2 | ✅ | Series termination resistor correctly positioned between clock buffer output Y4 and SCLK_M2BUS with appropriate 47Ω value for impedance matching and signal integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=20.67,26.99,28.17,34.85&zoom=1">C64</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Filter capacitor correctly connected between clock buffer input (NetC64_2) and GND. Value is marked TBD and needs to be determined based on clock frequency and filtering requirements. | | 2 | 2 | NetC64_2 | ✅ | Filter capacitor correctly connected between clock buffer input (NetC64_2) and GND. Value is marked TBD and needs to be determined based on clock frequency and filtering requirements. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=0.00,35.80,20.82,49.21&zoom=1">U14</a> - 74AVC9112 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/74AVC9112GTX) Part Number: `74AVC9112GTX` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Vcc | 3.3VCC | ✅ | Vcc power pin correctly connected to 3.3VCC supply. | | 2 | A | NetC64_2 | ✅ | Input pin A receives SPI clock from microcontroller PA27 through series resistor R82, with C64 providing input filtering. | | 3 | nOE | GND | ✅ | Output enable pin nOE correctly tied to GND for always-enabled operation. | | 4 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 5 | Y1 | NetR3_2 | ✅ | Output Y1 correctly drives SCLK_TCBUS through series termination resistor R3. | | 6 | Y2 | NetR4_2 | ✅ | Output Y2 correctly drives PA27_SCLK through series termination resistor R4, providing a buffered clock signal to test point TP77. | | 7 | Y3 | NetR13_2 | ✅ | Output Y3 correctly drives SCLK_M1BUS through series termination resistor R13. | | 8 | Y4 | NetR32_2 | ✅ | Output Y4 correctly drives SCLK_M2BUS through series termination resistor R32. | | 23 | NC | | ✅ | No-connect pin correctly left unconnected. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=0.00,22.63,20.82,41.03&zoom=1">U17</a> - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) Part Number: `SN74LVC125ARGYR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | A1 | PA26_MOSI_D | ✅ | All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses. | | 5 | A2 | PA26_MOSI_D | ✅ | All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses. | | 9 | A3 | PA26_MOSI_D | ✅ | All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses. | | 12 | A4 | PA26_MOSI_D | ✅ | All input pins (A1-4) are correctly connected to PA26_MOSI_D for fanout. This creates four buffered copies of the MOSI signal for distribution to different SPI buses. | | 3 | Y1 | NetR84_2 | ✅ | Output Y1 correctly drives MOSI_TCBUS through 47Ω series resistor R84 for impedance matching and signal integrity. | | 6 | Y2 | NetR59_2 | ✅ | Output Y2 correctly drives MOSI_M1BUS through 47Ω series resistor R59 for impedance matching and signal integrity. | | 7 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 8 | Y3 | NetR89_2 | ✅ | Output Y3 correctly drives MOSI_M2BUS through 47Ω series resistor R89 for impedance matching and signal integrity. | | 11 | Y4 | NetR93_2 | ✅ | Buffer 4 output Y4 (pin 11) correctly drives test point TP75 through series resistor R93. Output enable nOE4 (pin 13) is correctly tied to GND to enable the buffer. This provides a buffered monitoring point for the MOSI signal. | | 13 | nOE4 | GND | ✅ | Buffer 4 output Y4 (pin 11) correctly drives test point TP75 through series resistor R93. Output enable nOE4 (pin 13) is correctly tied to GND to enable the buffer. This provides a buffered monitoring point for the MOSI signal. | | 14 | Vcc | 3.3VCC | ✅ | Power supply pin correctly connected to 3.3VCC with local decoupling capacitor C91. | | 15 | PAD | GND | ✅ | Thermal pad correctly connected to GND for heat dissipation and electrical grounding. | | 23 | NC | | ✅ | Pin marked as NC (no connect) in component definition. This is likely a component library artifact as a 14-VQFN package would not have a pin 23. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=6.56,29.44,14.65,36.94&zoom=1">R93</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA26_MOSI | ✅ | Series resistor correctly placed between U17 buffer output Y4 and test point TP75. Pin 2 connects to buffer output via NetR93_2, pin 1 connects to PA26_MOSI which drives the test point. 47Ω provides appropriate impedance matching. | | 2 | 2 | NetR93_2 | ✅ | Series resistor correctly placed between U17 buffer output Y4 and test point TP75. Pin 2 connects to buffer output via NetR93_2, pin 1 connects to PA26_MOSI which drives the test point. 47Ω provides appropriate impedance matching. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.44,22.63,15.53,30.13&zoom=1">R84</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_TCBUS | ✅ | Series resistor correctly placed between U17 output Y1 and MOSI_TCBUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals. | | 2 | 2 | NetR84_2 | ✅ | Series resistor correctly placed between U17 output Y1 and MOSI_TCBUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.44,24.44,15.53,31.94&zoom=1">R59</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M1BUS | ✅ | Series resistor correctly placed between U17 output Y2 and MOSI_M1BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals. | | 2 | 2 | NetR59_2 | ✅ | Series resistor correctly placed between U17 output Y2 and MOSI_M1BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=7.44,26.26,15.53,33.76&zoom=1">R89</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M2BUS | ✅ | Series resistor correctly placed between U17 output Y3 and MOSI_M2BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals. | | 2 | 2 | NetR89_2 | ✅ | Series resistor correctly placed between U17 output Y3 and MOSI_M2BUS for impedance matching and signal integrity. 47Ω is appropriate for SPI signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.85,23.54,13.59,31.04&zoom=1">C83</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_TCBUS | ✅ | Capacitor correctly placed between MOSI_TCBUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements. | | 2 | 2 | GND | ✅ | Capacitor correctly placed between MOSI_TCBUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.85,25.35,13.59,32.85&zoom=1">C88</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M1BUS | ✅ | Capacitor correctly placed between MOSI_M1BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements. | | 2 | 2 | GND | ✅ | Capacitor correctly placed between MOSI_M1BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.85,27.17,13.59,34.67&zoom=1">C89</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M2BUS | ✅ | Capacitor correctly placed between MOSI_M2BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements. | | 2 | 2 | GND | ✅ | Capacitor correctly placed between MOSI_M2BUS and GND for signal conditioning. Value is marked TBD and needs to be determined based on signal integrity requirements. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=4.97,30.35,12.71,37.85&zoom=1">C90</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA26_MOSI | ✅ | Capacitor correctly placed between PA26_MOSI and GND for signal conditioning at test point TP75. Value is marked TBD and needs to be determined based on signal integrity requirements. | | 2 | 2 | GND | ✅ | Capacitor correctly placed between PA26_MOSI and GND for signal conditioning at test point TP75. Value is marked TBD and needs to be determined based on signal integrity requirements. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=8.03,7.18,38.46,25.58&zoom=1">U16</a> - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) Part Number: `SN74LVC125ARGYR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | nOE1 | CS_TCBUS | ✅ | Active-low output enable for buffer 1, correctly connected to CS_TCBUS to enable the buffer when the thermocouple bus is selected. | | 2 | A1 | MISO_TCBUS | ✅ | Input A1 correctly connected to MISO_TCBUS from the thermocouple SPI bus. | | 3 | Y1 | NetR94_2 | ✅ | Output Y1 correctly connected to NetR94_2, which is the common multiplexed MISO output node. | | 4 | nOE2 | CS_M1BUS | ✅ | Active-low output enable for buffer 2, correctly connected to CS_M1BUS to enable the buffer when motor bus 1 is selected. | | 5 | A2 | MISO_M1BUS | ✅ | Input A2 correctly connected to MISO_M1BUS from motor bus 1 SPI devices. | | 6 | Y2 | NetR94_2 | ✅ | Output Y2 correctly connected to NetR94_2, sharing the multiplexed MISO output with Y1 and Y3. | | 7 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 8 | Y3 | NetR94_2 | ✅ | Output Y3 correctly connected to NetR94_2, completing the 3-to-1 MISO multiplexer. | | 9 | A3 | MISO_M2BUS | ✅ | Input A3 correctly connected to MISO_M2BUS from motor bus 2 SPI devices. | | 10 | nOE3 | CS_M2BUS | ✅ | Active-low output enable for buffer 3, correctly connected to CS_M2BUS to enable the buffer when motor bus 2 is selected. | | 11 | Y4 | NetU16_11 | ✅ | Output Y4 is intentionally left unconnected as buffer 4 is unused in this design. | | 12 | A4 | GND | ✅ | Input A4 correctly tied to GND as buffer 4 is unused. | | 13 | nOE4 | GND | ✅ | Output enable nOE4 tied to GND, keeping buffer 4 always enabled even though it is unused. | | 14 | Vcc | 3.3VCC | ✅ | Power supply pin correctly connected to 3.3VCC. | | 15 | PAD | GND | ✅ | Thermal pad correctly connected to GND. | | 23 | NC | | ✅ | No-connect pin correctly left unconnected per design intent. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.68,19.45,13.76,26.95&zoom=1">R60</a> - R0402TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/DNI-R0402TBD) Part Number: `DNI-R0402TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC79_1 | ✅ | Connected to NetC79_1 as part of an optional RC filter, but marked DNI so not populated. | | 2 | 2 | PA25_MISO | ✅ | Connected to PA25_MISO, would provide series resistance for optional RC filtering if populated. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=1.85,18.54,9.35,26.95&zoom=1">R66</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND to provide pull-down function. | | 2 | 2 | PA25_MISO | ✅ | Connected to PA25_MISO to pull the MISO line low when all buffers are disabled. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=2.32,5.82,10.06,13.32&zoom=1">C74</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MISO_TCBUS | ✅ | Connected to MISO_TCBUS to provide high-frequency noise filtering. | | 2 | 2 | GND | ✅ | Connected to GND to complete the bypass capacitor function. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=4.68,19.45,12.41,26.95&zoom=1">C79</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC79_1 | ✅ | Connected to NetC79_1 as part of an optional RC filter with R60. | | 2 | 2 | GND | ✅ | Connected to GND to complete the optional RC filter function. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=19.20,13.09,26.70,21.49&zoom=1">R94</a> - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) Part Number: `CRCW040247R0FKEDC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA25_MISO | ✅ | Connected to PA25_MISO, the microcontroller's SPI MISO input. | | 2 | 2 | NetR94_2 | ✅ | Connected to NetR94_2, the common output node of the MISO multiplexer buffers. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=2.32,9.00,10.06,16.50&zoom=1">C75</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MISO_M1BUS | ✅ | Connected to MISO_M1BUS to provide high-frequency noise filtering. | | 2 | 2 | GND | ✅ | Connected to GND to complete the bypass capacitor function. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=2.32,12.18,10.06,19.68&zoom=1">C87</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MISO_M2BUS | ✅ | Connected to MISO_M2BUS to provide high-frequency noise filtering. | | 2 | 2 | GND | ✅ | Connected to GND to complete the bypass capacitor function. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=23.90,24.44,32.58,31.94&zoom=1">R83</a> - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA25_MISO | ✅ | Series termination resistor on SPI MISO path between buffered MISO sources and microcontroller PA25 input. The 24Ω resistor provides source termination and, combined with upstream R94 (47Ω), creates 71Ω total series resistance for isolation and current limiting. | | 2 | 2 | NetR83_2 | ✅ | Series termination resistor on SPI MISO path between buffered MISO sources and microcontroller PA25 input. The 24Ω resistor provides source termination and, combined with upstream R94 (47Ω), creates 71Ω total series resistance for isolation and current limiting. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.56,40.34,13.29,47.84&zoom=1">C104</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor connected between SCLK_M1BUS and ground for signal integrity, but value is marked TBD and needs to be determined. | | 2 | 2 | SCLK_M1BUS | ✅ | Capacitor connected between SCLK_M1BUS and ground for signal integrity, but value is marked TBD and needs to be determined. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.56,36.71,13.29,44.21&zoom=1">C101</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor connected between SCLK_TCBUS and ground for signal integrity, but value is marked TBD and needs to be determined. | | 2 | 2 | SCLK_TCBUS | ✅ | Capacitor connected between SCLK_TCBUS and ground for signal integrity, but value is marked TBD and needs to be determined. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.56,38.53,13.29,46.03&zoom=1">C102</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor connected between PA27_SCLK and ground for signal integrity, but value is marked TBD and needs to be determined. | | 2 | 2 | PA27_SCLK | ✅ | Capacitor connected between PA27_SCLK and ground for signal integrity, but value is marked TBD and needs to be determined. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=23.90,26.26,32.58,33.76&zoom=1">R82</a> - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC64_2 | ✅ | 24Ω series resistor correctly placed between microcontroller SCLK output and clock buffer input for signal integrity. | | 2 | 2 | NetR82_2 | ✅ | 24Ω series resistor correctly placed between microcontroller SCLK output and clock buffer input for signal integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=23.90,25.35,32.58,32.85&zoom=1">R77</a> - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) Part Number: `RC0402FR-0724RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA26_MOSI_D | ✅ | 24Ω series resistor correctly placed between microcontroller MOSI output and buffer inputs for signal integrity. | | 2 | 2 | NetR77_2 | ✅ | 24Ω series resistor correctly placed between microcontroller MOSI output and buffer inputs for signal integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=5.56,42.16,13.29,49.66&zoom=1">C85</a> - C0402_TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) Part Number: `TBD` (IPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor connected between SCLK_M2BUS and ground for signal integrity, but value is marked TBD and needs to be determined. | | 2 | 2 | SCLK_M2BUS | ✅ | Capacitor connected between SCLK_M2BUS and ground for signal integrity, but value is marked TBD and needs to be determined. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=57.48,7.63,66.04,15.13&zoom=1">D30</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS2 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS2. | | K | K | TC_nCS2 | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS2 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS2. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=57.78,18.08,66.33,25.58&zoom=1">D62</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS5 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS5. | | K | K | TC_nCS5 | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS5 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS5. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=16.26,9.00,24.35,16.50&zoom=1">R95</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor that pulls CS_TCBUS to 3.3VCC. When any thermocouple chip select (TC_nCS1-5) is active low, the corresponding diode conducts and pulls CS_TCBUS low through this resistor, disabling the buffer outputs. | | 2 | 2 | CS_TCBUS | ✅ | Pull-up resistor that pulls CS_TCBUS to 3.3VCC. When any thermocouple chip select (TC_nCS1-5) is active low, the corresponding diode conducts and pulls CS_TCBUS low through this resistor, disabling the buffer outputs. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=19.26,56.24,27.82,63.74&zoom=1">D61</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS1 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS1. | | K | K | TC_nCS1 | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS1 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS1. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=21.02,1.73,29.58,9.23&zoom=1">D5</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS4 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS4. | | K | K | TC_nCS4 | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS4 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS4. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=20.73,8.09,29.29,15.59&zoom=1">D31</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS3 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS3. | | K | K | TC_nCS3 | ✅ | Schottky diode configured in a diode OR gate to combine active-low chip select signal TC_nCS3 with other thermocouple chip selects onto CS_TCBUS. The anode connects to CS_TCBUS (pulled up by R95), and the cathode connects to TC_nCS3. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=51.31,68.06,59.87,75.56&zoom=1">D77</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when SPIFLASH_CS is asserted by microcontroller pin PB20, enabling MISO buffer for SPI flash access. | | K | K | SPIFLASH_CS | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when SPIFLASH_CS is asserted by microcontroller pin PB20, enabling MISO buffer for SPI flash access. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=57.19,11.72,65.75,19.22&zoom=1">D76</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS4 is asserted, enabling MISO buffer for motor bus 1. | | K | K | M_nCS4 | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS4 is asserted, enabling MISO buffer for motor bus 1. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=20.44,48.98,28.99,56.48&zoom=1">D75</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS3 is asserted, enabling MISO buffer for motor bus 1. | | K | K | M_nCS3 | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS3 is asserted, enabling MISO buffer for motor bus 1. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=22.49,6.27,31.05,13.77&zoom=1">D70</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS1 is asserted, enabling MISO buffer for motor bus 1. | | K | K | M_nCS1 | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS1 is asserted, enabling MISO buffer for motor bus 1. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=20.44,45.34,28.99,52.84&zoom=1">D74</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS2 is asserted, enabling MISO buffer for motor bus 1. | | K | K | M_nCS2 | ✅ | Diode correctly implements wired-OR function to pull CS_M1BUS low when M_nCS2 is asserted, enabling MISO buffer for motor bus 1. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=17.44,45.80,24.94,54.20&zoom=1">R100</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly pulls CS_M1BUS high when no chip selects are active, disabling the MISO buffer. The 10kΩ value provides appropriate pull-up strength. | | 2 | 2 | CS_M1BUS | ✅ | Pull-up resistor correctly pulls CS_M1BUS high when no chip selects are active, disabling the MISO buffer. The 10kΩ value provides appropriate pull-up strength. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=58.36,30.35,66.92,37.85&zoom=1">D41</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct. | | K | K | M_nCS7 | ✅ | Cathode connected to M_nCS7 chip select line. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=58.36,36.71,66.92,44.21&zoom=1">D63</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct. | | K | K | M_nCS8 | ✅ | Cathode connected to M_nCS8 chip select line. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=57.78,0.37,66.33,7.87&zoom=1">D40</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct. | | K | K | M_nCS6 | ✅ | Cathode connected to M_nCS6 chip select line. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=58.66,4.91,67.22,12.41&zoom=1">D60</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode connected to CS_M2BUS for wired-OR chip select logic. This connection is correct. | | K | K | M_nCS5 | ✅ | Cathode connected to M_nCS5 chip select line. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=63.01,5.36,70.51,13.77&zoom=1">R97</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Connected to 3.3VCC power supply. This connection is correct. | | 2 | 2 | CS_M2BUS | ✅ | Connected to CS_M2BUS to provide pull-up for wired-OR chip select logic. This connection is correct. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=68.60,2.18,76.10,11.50&zoom=1">R64</a> - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SDCD | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on card detect signal SDCD to 3.3V. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on card detect signal SDCD to 3.3V. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=74.77,2.18,82.27,11.50&zoom=1">R65</a> - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on CMD line to 3.3V as required by SD specification. | | 2 | 2 | MCCDA | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on CMD line to 3.3V as required by SD specification. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=76.53,2.18,84.03,11.50&zoom=1">R67</a> - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCDA3 | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on DAT3 line to 3.3V as required by SD specification. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on DAT3 line to 3.3V as required by SD specification. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=78.30,2.18,85.80,11.50&zoom=1">R68</a> - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCDA2 | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on DAT2 line to 3.3V as required by SD specification. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on DAT2 line to 3.3V as required by SD specification. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=70.36,2.18,77.86,11.50&zoom=1">R69</a> - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on MCDA1 net to 3.3V. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1, indicating a potential swap at the connector level. | | 2 | 2 | MCDA1 | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on MCDA1 net to 3.3V. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1, indicating a potential swap at the connector level. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=72.12,2.18,79.62,11.50&zoom=1">R70</a> - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/508/1/PYU_RC_51_ROHS_P.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) Part Number: `RC0402FR-0710KP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on MCDA0 net to 3.3V. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0, indicating a potential swap at the connector level. | | 2 | 2 | MCDA0 | ✅ | Pull-up resistor correctly provides 10kΩ pull-up on MCDA0 net to 3.3V. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0, indicating a potential swap at the connector level. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=67.71,16.72,75.21,25.13&zoom=1">D42</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides ESD protection on card detect signal with cathode to signal and anode to ground. | | C | C | SDCD | ✅ | TVS diode correctly provides ESD protection on card detect signal with cathode to signal and anode to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=69.48,16.72,76.98,25.13&zoom=1">D64</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides ESD protection on MCDA1 net with cathode to signal and anode to ground. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1. | | C | C | MCDA1 | ✅ | TVS diode correctly provides ESD protection on MCDA1 net with cathode to signal and anode to ground. Note: MCDA1 connects to J18 pin 8 (DAT0) rather than DAT1. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=71.24,16.72,78.74,25.13&zoom=1">D65</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides ESD protection on MCDA0 net with cathode to signal and anode to ground. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0. | | C | C | MCDA0 | ✅ | TVS diode correctly provides ESD protection on MCDA0 net with cathode to signal and anode to ground. Note: MCDA0 connects to J18 pin 7 (DAT1) rather than DAT0. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=73.01,16.72,80.51,25.13&zoom=1">D66</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides ESD protection on CMD line with cathode to signal and anode to ground. | | C | C | MCCDA | ✅ | TVS diode correctly provides ESD protection on CMD line with cathode to signal and anode to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=74.77,16.72,82.27,25.13&zoom=1">D67</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides ESD protection on CLK line with cathode to signal and anode to ground. | | C | C | MCCK | ✅ | TVS diode correctly provides ESD protection on CLK line with cathode to signal and anode to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=76.53,16.72,84.03,25.13&zoom=1">D68</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides ESD protection on DAT3 line with cathode to signal and anode to ground. | | C | C | MCDA3 | ✅ | TVS diode correctly provides ESD protection on DAT3 line with cathode to signal and anode to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=78.30,16.72,85.80,25.13&zoom=1">D69</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly provides ESD protection on DAT2 line with cathode to signal and anode to ground. | | C | C | MCDA2 | ✅ | TVS diode correctly provides ESD protection on DAT2 line with cathode to signal and anode to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=91.82,4.91,99.91,13.32&zoom=1">C70</a> - C1608JB0J106K080AB ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C1608JB0J106K080AB) Part Number: `C1608JB0J106K080AB` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor correctly provides local 10µF filtering for the microSD card power supply. | | 2 | 2 | 3.3VCC | ✅ | Decoupling capacitor correctly provides local 10µF filtering for the microSD card power supply. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=85.35,4.91,97.56,20.59&zoom=1">J18</a> - 0475710001 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/0475710001) Part Number: `0475710001` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | MCDA2 | ✅ | DAT2 data line correctly connected to MCDA2 on the microcontroller. | | 2 | CD/DAT3 | MCDA3 | ✅ | CD/DAT3 data line correctly connected to MCDA3 on the microcontroller. | | 3 | CMD | MCCDA | ✅ | CMD command line correctly connected to MCCDA on the microcontroller with appropriate pull-up resistor. | | 4 | VDD | 3.3VCC | ✅ | VDD power supply correctly connected to 3.3VCC with appropriate decoupling. | | 5 | CLK | MCCK | ✅ | CLK clock line correctly connected to MCCK on the microcontroller. | | 6 | VSS | GND | ✅ | VSS ground correctly connected to GND. | | 7 | DAT1 | MCDA0 | ✅ | DAT0 and DAT1 data lines are correctly connected electrically, but the component symbol has swapped pin labels that do not match the standard microSD pinout. | | 8 | DAT0 | MCDA1 | ✅ | DAT0 and DAT1 data lines are correctly connected electrically, but the component symbol has swapped pin labels that do not match the standard microSD pinout. | | 9 | SH | GND | ✅ | Shield pins correctly connected to GND for EMI shielding. | | 10 | SH | GND | ✅ | Shield pins correctly connected to GND for EMI shielding. | | 11 | SH | GND | ✅ | Shield pins correctly connected to GND for EMI shielding. | | 12 | CD | SDCD | ✅ | Card detect switch correctly connected to SDCD with appropriate pull-up resistor. | | 13 | CD/POL | GND | ✅ | Card detect polarity pin correctly connected to GND for active-low detection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=20.08,31.26,28.17,38.76&zoom=1">D25</a> - 5988140107F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988140107F) Part Number: `5988140107F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD25_A | ✅ | LED anode connected to current limiting resistor R36, which drives from microcontroller GPIO PC1. | | C | C | GND | ✅ | LED cathode correctly connected to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=21.85,32.62,30.52,40.12&zoom=1">R36</a> - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LED_Y | ✅ | Connected to LED_Y net, which drives from microcontroller GPIO PC1 to control yellow LED D25. | | 2 | 2 | NetD25_A | ✅ | Connected to yellow LED D25 anode through net NetD25_A. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=21.85,34.44,30.52,41.94&zoom=1">R34</a> - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LED_R | ✅ | Connected to LED_R net, which drives from microcontroller GPIO PC3 to control red LED D24. | | 2 | 2 | NetD24_A | ✅ | Connected to red LED D24 anode through net NetD24_A. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=24.49,18.08,32.58,25.58&zoom=1">R71</a> - 1k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Connected to 3.3VIO power rail to provide pull-up voltage for I2C SCL line. | | 2 | 2 | PA18_SCL | ✅ | Connected to PA18_SCL (I2C clock line) on microcontroller pin PA18 and external connector J20 pin 21. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=20.08,34.89,28.17,42.39&zoom=1">D24</a> - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988110107F) Part Number: `5988110107F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD24_A | ✅ | LED anode connected to current limiting resistor R34, which drives from microcontroller GPIO PC3. | | C | C | GND | ✅ | LED cathode correctly connected to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=24.49,17.17,32.58,24.67&zoom=1">R40</a> - 1k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Connected to 3.3VIO power rail to provide pull-up voltage for I2C SDA line. | | 2 | 2 | PA17_SDA | ✅ | Connected to PA17_SDA (I2C data line) on microcontroller pin PA17 and external connector J20 pin 22. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=90.94,45.80,98.44,54.20&zoom=1">D72</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode anode correctly connected to GND for ESD protection on UART TX signal. | | C | C | PA9_UTXD | ✅ | TVS diode cathode correctly connected to PA9_UTXD signal for ESD protection on external connector. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=93.29,45.80,100.00,54.20&zoom=1">D71</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode anode correctly connected to GND for ESD protection on NRST signal. | | C | C | NRST | ✅ | TVS diode cathode correctly connected to NRST signal for ESD protection on external connector. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=88.88,45.80,96.38,54.20&zoom=1">D73</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode anode correctly connected to GND for ESD protection on UART RX signal. | | C | C | PA8_URXD | ✅ | TVS diode cathode correctly connected to PA8_URXD signal for ESD protection on external connector. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=81.24,41.71,90.50,53.75&zoom=1">J28</a> - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/302-S101) Part Number: `302-S101` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net, providing ground reference for the serial connector. | | 2 | 2 | PA9_UTXD | ✅ | UART transmit signal correctly connected to PA9_UTXD from MCU pin 2, with ESD protection via D72. | | 3 | 3 | +5VCC | ✅ | 5V power supply pin correctly connected to +5VCC net. | | 4 | 4 | PA8_URXD | ✅ | UART receive signal correctly connected to PA8_URXD from MCU pin 27, with ESD protection via D73. | | 5 | 5 | 3.3VCC | ✅ | 3.3V power supply pin correctly connected to 3.3VCC net. | | 6 | 6 | NRST | ✅ | Reset signal correctly connected to NRST net with internal pull-up and ESD protection via D71. | | 7 | 7 | ERASE | ✅ | Flash erase signal correctly connected to ERASE net, allowing external flash erase functionality through tactile switch S2. | | 8 | 8 | +5VCC | ✅ | Additional 5V power supply pin correctly connected to +5VCC net, providing redundant power connection. | | 9 | 9 | PC8_PWML3 | ✅ | PWM signal correctly connected to PC8_PWML3 from MCU pin 66, though lacks ESD protection unlike other signal pins. | | 10 | 10 | GND | ✅ | Additional ground pin correctly connected to GND net, providing redundant ground connection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.77,55.34,88.44,62.84&zoom=1">R109</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA14_RTS1 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART RTS1 signal and connector for signal protection and integrity. | | 2 | 2 | NetJ12_10 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART RTS1 signal and connector for signal protection and integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=83.59,54.43,92.85,66.47&zoom=1">J12</a> - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/302-S101) Part Number: `302-S101` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | +5VCC power supply pin correctly connected to the +5VCC rail to provide power to external devices connected to this serial connector. | | 2 | 2 | GND | ✅ | Ground pin correctly connected to the GND rail. | | 3 | 3 | NetJ12_3 | ✅ | Connected to microcontroller pin PC2_PWML0 through 100 ohm series resistor R137 for signal protection. | | 4 | 4 | NetJ12_4 | ✅ | Connected to microcontroller CAN receive pin PA1_CANRX0 through 100 ohm series resistor R136. The 100 ohm value is higher than typical for CAN signals but may be intentional for connector protection. | | 5 | 5 | NetJ12_5 | ✅ | Connected to microcontroller pin PA16 through 100 ohm series resistor R135 for signal protection. | | 6 | 6 | NetJ12_6 | ✅ | Connected to microcontroller CAN transmit pin PA0_CANTX0 through 100 ohm series resistor R134. The 100 ohm value is higher than typical for CAN signals but may be intentional for connector protection. | | 7 | 7 | NetJ12_7 | ✅ | Connected to microcontroller UART receive pin PA12_RXD1 through 100 ohm series resistor R133 for signal protection and integrity. | | 8 | 8 | NetJ12_8 | ✅ | Connected to microcontroller UART clear-to-send pin PA15_CTS1 through 100 ohm series resistor R120 for signal protection and integrity. | | 9 | 9 | NetJ12_9 | ✅ | Connected to microcontroller UART transmit pin PA13_TXD1 through 100 ohm series resistor R114 for signal protection and integrity. | | 10 | 10 | NetJ12_10 | ✅ | Connected to microcontroller UART request-to-send pin PA14_RTS1 through 100 ohm series resistor R109 for signal protection and integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=88.00,58.06,96.68,65.56&zoom=1">R137</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ12_3 | ✅ | 100 ohm series resistor correctly placed between microcontroller PWM pin PC2_PWML0 and connector for signal protection. | | 2 | 2 | PC2_PWML0 | ✅ | 100 ohm series resistor correctly placed between microcontroller PWM pin PC2_PWML0 and connector for signal protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=88.00,55.34,96.68,62.84&zoom=1">R114</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ12_9 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART TXD1 signal and connector for signal protection and integrity. | | 2 | 2 | PA13_TXD1 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART TXD1 signal and connector for signal protection and integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.77,56.24,88.44,63.74&zoom=1">R120</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA15_CTS1 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART CTS1 signal and connector for signal protection and integrity. | | 2 | 2 | NetJ12_8 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART CTS1 signal and connector for signal protection and integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.77,58.06,88.44,65.56&zoom=1">R136</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA1_CANRX0 | ✅ | 100 ohm series resistor placed between microcontroller CAN receive signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection. | | 2 | 2 | NetJ12_4 | ✅ | 100 ohm series resistor placed between microcontroller CAN receive signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=88.00,57.15,96.68,64.65&zoom=1">R135</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ12_5 | ✅ | 100 ohm series resistor correctly placed between microcontroller GPIO pin PA16 and connector for signal protection. | | 2 | 2 | PA16 | ✅ | 100 ohm series resistor correctly placed between microcontroller GPIO pin PA16 and connector for signal protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.77,57.15,88.44,64.65&zoom=1">R134</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA0_CANTX0 | ✅ | 100 ohm series resistor placed between microcontroller CAN transmit signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection. | | 2 | 2 | NetJ12_6 | ✅ | 100 ohm series resistor placed between microcontroller CAN transmit signal and connector. The value is higher than typical for CAN signals but may be acceptable for connector protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=88.00,56.24,96.68,63.74&zoom=1">R133</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ12_7 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART RXD1 signal and connector for signal protection and integrity. | | 2 | 2 | PA12_RXD1 | ✅ | 100 ohm series resistor correctly placed between microcontroller UART RXD1 signal and connector for signal protection and integrity. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=87.71,69.87,96.38,77.37&zoom=1">R141</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ13_7 | ✅ | Series resistor connecting microcontroller SPI0_NPCS1 chip select signal to connector J13 pin 7. | | 2 | 2 | PA29_CS | ✅ | Series resistor connecting microcontroller SPI0_NPCS1 chip select signal to connector J13 pin 7. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.47,69.87,88.15,77.37&zoom=1">R140</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PB27_TIOB0 | ✅ | Series resistor connecting microcontroller timer output PB27_TIOB0 to connector J13 pin 8. | | 2 | 2 | NetJ13_8 | ✅ | Series resistor connecting microcontroller timer output PB27_TIOB0 to connector J13 pin 8. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=83.30,68.06,92.56,80.10&zoom=1">J13</a> - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/302-S101) Part Number: `302-S101` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Provides +5VCC power to external device connected to this connector. | | 2 | 2 | GND | ✅ | Ground reference for the connector. | | 3 | 3 | NetJ13_3 | ✅ | Connected to microcontroller reset signal NRST through 100Ω series resistor R145. | | 4 | 4 | NetJ13_4 | ✅ | Connected to microcontroller timer output PB25_TIOA0 through 100Ω series resistor R144. | | 5 | 5 | NetJ13_5 | ✅ | Connected to SPI0 MOSI signal PA26_MOSI through 100Ω series resistor R143. | | 6 | 6 | NetJ13_6 | ✅ | Connected to microcontroller pin PA3_AD2 through 100Ω series resistor R142. | | 7 | 7 | NetJ13_7 | ✅ | Connected to SPI0 chip select signal PA29_CS through 100Ω series resistor R141. | | 8 | 8 | NetJ13_8 | ✅ | Connected to microcontroller timer output PB27_TIOB0 through 100Ω series resistor R140. | | 9 | 9 | NetJ13_9 | ✅ | Connected to SPI0 clock signal PA27_SCLK through 100Ω series resistor R139. | | 10 | 10 | NetJ13_10 | ✅ | Connected to SPI0 MISO signal PA25_MISO through 100Ω series resistor R138. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=87.71,71.69,96.38,79.19&zoom=1">R145</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ13_3 | ✅ | Series resistor connecting microcontroller reset signal NRST to connector J13 pin 3. | | 2 | 2 | NRST | ✅ | Series resistor connecting microcontroller reset signal NRST to connector J13 pin 3. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=87.71,68.96,96.38,76.46&zoom=1">R139</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ13_9 | ✅ | Series resistor connecting microcontroller SPI0_SPCK signal to connector J13 pin 9. | | 2 | 2 | PA27_SCLK | ✅ | Series resistor connecting microcontroller SPI0_SPCK signal to connector J13 pin 9. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=87.71,70.78,96.38,78.28&zoom=1">R143</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ13_5 | ✅ | Series resistor connecting microcontroller SPI0_MOSI signal to connector J13 pin 5. | | 2 | 2 | PA26_MOSI | ✅ | Series resistor connecting microcontroller SPI0_MOSI signal to connector J13 pin 5. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.47,71.69,88.15,79.19&zoom=1">R144</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PB25_TIOA0 | ✅ | Series resistor connecting microcontroller timer output PB25_TIOA0 to connector J13 pin 4. | | 2 | 2 | NetJ13_4 | ✅ | Series resistor connecting microcontroller timer output PB25_TIOA0 to connector J13 pin 4. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.47,70.78,88.15,78.28&zoom=1">R142</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA3_AD2 | ✅ | Series resistor connecting microcontroller pin PA3_AD2 to connector J13 pin 6. | | 2 | 2 | NetJ13_6 | ✅ | Series resistor connecting microcontroller pin PA3_AD2 to connector J13 pin 6. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=79.47,68.96,88.15,76.46&zoom=1">R138</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA25_MISO | ✅ | Series resistor connecting microcontroller SPI0_MISO signal to connector J13 pin 10. | | 2 | 2 | NetJ13_10 | ✅ | Series resistor connecting microcontroller SPI0_MISO signal to connector J13 pin 10. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=57.72,81.69,67.57,100.00&zoom=1">J20</a> - Header 12X2 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/2213S-24G) Part Number: `2213S-24G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | 5 | NetJ20_5 | ❌ | <details><summary>These header pins are connected to page-local nets with no other connections and are not marked as no-connects.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="60.07,89.86,67.57,97.36" aspect-ratio="1.55" } <ul><li>Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic)</li><li>Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5)</li><li>These pins are not marked as no-connects in the schematic (from schematic)</li><li>Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic)</li><li>Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning)</li><li>Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning)</li><li>These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)</li></ul></details> | | 6 | 6 | NetJ20_6 | ❌ | <details><summary>These header pins are connected to page-local nets with no other connections and are not marked as no-connects.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="57.72,89.86,65.22,97.36" aspect-ratio="1.55" } <ul><li>Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic)</li><li>Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5)</li><li>These pins are not marked as no-connects in the schematic (from schematic)</li><li>Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic)</li><li>Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning)</li><li>Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning)</li><li>These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)</li></ul></details> | | 7 | 7 | NetJ20_7 | ❌ | <details><summary>These header pins are connected to page-local nets with no other connections and are not marked as no-connects.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="60.07,88.95,67.57,96.45" aspect-ratio="1.55" } <ul><li>Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic)</li><li>Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5)</li><li>These pins are not marked as no-connects in the schematic (from schematic)</li><li>Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic)</li><li>Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning)</li><li>Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning)</li><li>These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)</li></ul></details> | | 9 | 9 | NetJ20_9 | ❌ | <details><summary>These header pins are connected to page-local nets with no other connections and are not marked as no-connects.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="60.07,88.05,67.57,95.55" aspect-ratio="1.55" } <ul><li>Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic)</li><li>Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5)</li><li>These pins are not marked as no-connects in the schematic (from schematic)</li><li>Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic)</li><li>Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning)</li><li>Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning)</li><li>These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)</li></ul></details> | | 10 | 10 | NetJ20_10 | ❌ | <details><summary>These header pins are connected to page-local nets with no other connections and are not marked as no-connects.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="57.72,88.05,65.22,95.55" aspect-ratio="1.55" } <ul><li>Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic)</li><li>Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5)</li><li>These pins are not marked as no-connects in the schematic (from schematic)</li><li>Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic)</li><li>Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning)</li><li>Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning)</li><li>These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)</li></ul></details> | | 12 | 12 | NetJ20_12 | ❌ | <details><summary>These header pins are connected to page-local nets with no other connections and are not marked as no-connects.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="57.72,87.14,65.22,94.64" aspect-ratio="1.55" } <ul><li>Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic)</li><li>Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5)</li><li>These pins are not marked as no-connects in the schematic (from schematic)</li><li>Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic)</li><li>Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning)</li><li>Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning)</li><li>These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)</li></ul></details> | | 1 | 1 | PA28_CS0 | ✅ | SPI chip select signal PA28_CS0 correctly connected to microcontroller. | | 2 | 2 | PA27_SCLK | ✅ | SPI clock signal PA27_SCLK correctly connected to microcontroller. | | 3 | 3 | PA26_MOSI | ✅ | SPI MOSI signal PA26_MOSI correctly connected to microcontroller. | | 4 | 4 | PA25_MISO | ✅ | SPI MISO signal PA25_MISO correctly connected to microcontroller. | | 8 | 8 | PB12_AD8 | ✅ | ADC input PB12_AD8 correctly connected to microcontroller. | | 11 | 11 | NetJ20_11 | ✅ | These pins are intentionally left as no-connects. | | 13 | 13 | NetJ20_13 | ✅ | These pins are intentionally left as no-connects. | | 14 | 14 | NetJ20_14 | ✅ | These pins are intentionally left as no-connects. | | 17 | 17 | NetJ20_17 | ✅ | These pins are intentionally left as no-connects. | | 15 | 15 | NetJ20_15 | ✅ | Ethernet TX data signal correctly routed through series resistor and protected by varistor. | | 16 | 16 | NetJ20_16 | ✅ | Ethernet TX enable signal correctly routed through series resistor and protected by varistor. | | 18 | 18 | NRST | ✅ | Reset signal NRST correctly connected for external reset capability. | | 19 | 19 | NetJ20_19 | ✅ | Signal routed through series resistor and protected by varistor, grouped with Ethernet signals. | | 20 | 20 | NetJ20_20 | ✅ | Ethernet TX clock signal correctly routed through series resistor and protected by varistor. | | 21 | 21 | PA18_SCL | ✅ | I2C clock signal PA18_SCL correctly connected to microcontroller. | | 22 | 22 | PA17_SDA | ✅ | I2C data signal PA17_SDA correctly connected to microcontroller. | | 23 | 23 | GND | ✅ | Ground pin correctly connected. | | 24 | 24 | 3.3VCC | ✅ | 3.3V power pin correctly connected. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=49.19,81.69,57.87,89.19&zoom=1">R153</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PB0_ETXCK | ✅ | 100 ohm series resistor between Ethernet TX clock signal and header for current limiting and impedance matching. | | 2 | 2 | NetJ20_20 | ✅ | 100 ohm series resistor between Ethernet TX clock signal and header for current limiting and impedance matching. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=49.19,88.05,57.87,95.55&zoom=1">R160</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PB1_ETXEN | ✅ | 100 ohm series resistor between Ethernet TX enable signal and header for current limiting and impedance matching. | | 2 | 2 | NetJ20_16 | ✅ | 100 ohm series resistor between Ethernet TX enable signal and header for current limiting and impedance matching. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=66.54,85.32,75.21,92.82&zoom=1">R161</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_15 | ✅ | 100 ohm series resistor between Ethernet TX data 0 signal and header for current limiting and impedance matching. | | 2 | 2 | PB2_ETX0 | ✅ | 100 ohm series resistor between Ethernet TX data 0 signal and header for current limiting and impedance matching. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=66.83,79.41,75.51,86.91&zoom=1">R159</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_19 | ✅ | 100 ohm series resistor between ADC input and header for current limiting and protection. | | 2 | 2 | PB13_AD9 | ✅ | 100 ohm series resistor between ADC input and header for current limiting and protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=65.95,86.41,73.45,94.46&zoom=1">RV3</a> - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) Part Number: `AVRM0603C6R8NT101N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_15 | ✅ | Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | | 2 | 2 | GND | ✅ | Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=50.95,83.23,58.45,91.28&zoom=1">RV1</a> - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) Part Number: `AVRM0603C6R8NT101N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_20 | ✅ | Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | | 2 | 2 | GND | ✅ | Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=58.60,76.23,66.69,83.73&zoom=1">D44</a> - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) Part Number: `ESD9X3.3ST5G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode connected between 3.3VCC power rail and ground for power supply protection. The 3.3V working voltage is marginal and may conduct if the power supply exceeds 3.3V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 5V) to provide more margin. | | K | K | 3.3VCC | ✅ | TVS diode connected between 3.3VCC power rail and ground for power supply protection. The 3.3V working voltage is marginal and may conduct if the power supply exceeds 3.3V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 5V) to provide more margin. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=50.95,89.59,58.45,97.64&zoom=1">RV4</a> - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) Part Number: `AVRM0603C6R8NT101N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_16 | ✅ | Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | | 2 | 2 | GND | ✅ | Varistor correctly connected between Ethernet signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=66.24,80.50,73.74,88.55&zoom=1">RV2</a> - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) Part Number: `AVRM0603C6R8NT101N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_19 | ✅ | Varistor correctly connected between signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | | 2 | 2 | GND | ✅ | Varistor correctly connected between signal and ground for ESD protection. The 3.5V standoff voltage provides adequate margin for 3.3V signals. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=89.47,73.96,96.97,82.37&zoom=1">D45</a> - DF2S6.8FS,L3M ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/DF2S6.8FS%2CL3M) Part Number: `DF2S6.8FS,L3M` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode connected between +5VCC power rail and ground for power supply protection. The 5V working voltage is marginal and may conduct if the power supply exceeds 5V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 6V) to provide more margin. | | K | K | +5VCC | ✅ | TVS diode connected between +5VCC power rail and ground for power supply protection. The 5V working voltage is marginal and may conduct if the power supply exceeds 5V due to tolerance or transients. Consider using a TVS diode with higher working voltage (e.g., 6V) to provide more margin. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=73.30,58.06,81.98,65.56&zoom=1">R41</a> - RK73H1ETTP1001F ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA1_CANRX0 | ❌ | <details><summary>R41 connects two GPIO pins of the same microcontroller (PA1_CANRX0 and PA5_PWM) together through a 1kΩ resistor. This is an unusual and likely incorrect connection that serves no clear purpose and could cause pin conflicts.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="74.48,58.06,81.98,65.56" aspect-ratio="1.55" } <ul><li>R41 pin 1 is connected to net PA1_CANRX0, which connects to U11A pin 24 (from schematic)</li><li>R41 pin 2 is connected to net PA5_PWM, which connects to U11A pin 25 (from schematic)</li><li>U11A pin 24 (PA1) can be configured as CANRX0, PCK0, or WKUP0 according to the datasheet (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>U11A pin 25 (PA5) can be configured as TIOA2, PWMFI0, or WKUP2 according to the datasheet (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0)</li><li>Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA5_PWM)</li><li>R41 is a 1kΩ 1% 1/16W resistor in 0402 package (from datasheet <a href="https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf#page=4">RC0402FR-071KL</a>, page 4)</li><li>Connecting two GPIO pins of the same microcontroller together through a resistor is not a standard design practice and serves no clear functional purpose (reasoning)</li><li>If both pins are configured as outputs driving different logic levels, the 1kΩ resistor would create a conflict and excessive current draw (reasoning)</li><li>No text notes on the schematic page explain or justify this connection between PA1_CANRX0 and PA5_PWM (reasoning)</li><li>This connection should be reviewed and likely removed, or one end should be connected to the intended destination if this is a routing error (reasoning)</li></ul></details> | | 2 | 2 | PA5_PWM | ❌ | <details><summary>R41 connects two GPIO pins of the same microcontroller (PA1_CANRX0 and PA5_PWM) together through a 1kΩ resistor. This is an unusual and likely incorrect connection that serves no clear purpose and could cause pin conflicts.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="73.30,58.06,80.80,65.56" aspect-ratio="1.55" } <ul><li>R41 pin 1 is connected to net PA1_CANRX0, which connects to U11A pin 24 (from schematic)</li><li>R41 pin 2 is connected to net PA5_PWM, which connects to U11A pin 25 (from schematic)</li><li>U11A pin 24 (PA1) can be configured as CANRX0, PCK0, or WKUP0 according to the datasheet (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>U11A pin 25 (PA5) can be configured as TIOA2, PWMFI0, or WKUP2 according to the datasheet (from datasheet <a href="https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18">ATSAM3X8EA-AU</a>, page 18)</li><li>Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0)</li><li>Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA5_PWM)</li><li>R41 is a 1kΩ 1% 1/16W resistor in 0402 package (from datasheet <a href="https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf#page=4">RC0402FR-071KL</a>, page 4)</li><li>Connecting two GPIO pins of the same microcontroller together through a resistor is not a standard design practice and serves no clear functional purpose (reasoning)</li><li>If both pins are configured as outputs driving different logic levels, the 1kΩ resistor would create a conflict and excessive current draw (reasoning)</li><li>No text notes on the schematic page explain or justify this connection between PA1_CANRX0 and PA5_PWM (reasoning)</li><li>This connection should be reviewed and likely removed, or one end should be connected to the intended destination if this is a routing error (reasoning)</li></ul></details> | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=12.63,58.01,23.77,66.68&zoom=1">U2B</a> - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) Part Number: `SN74AHCT125RGYR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 4 | 2OE | GND | ✅ | Output enable pin correctly tied to GND to permanently enable the buffer output. | | 5 | 2A | Fan3 | ✅ | Input pin correctly connected to Fan3 control signal from the microcontroller. | | 6 | 2Y | NetR180_1 | ✅ | Output pin correctly drives MOSFET gate through 100Ω series resistor R180. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=49.43,57.42,60.56,66.09&zoom=1">U2A</a> - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) Part Number: `SN74AHCT125RGYR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1OE | GND | ✅ | Output enable pin correctly tied to GND to permanently enable the buffer output. | | 2 | 1A | Fan4 | ✅ | Input pin correctly connected to Fan4 control signal from the microcontroller. | | 3 | 1Y | NetR181_1 | ✅ | Output pin correctly drives MOSFET gate through 100Ω series resistor R181. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=39.89,78.58,48.75,89.61&zoom=1">U2E</a> - SN74AHCT125 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) Part Number: `SN74AHCT125RGYR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 15 | PAD | SNTP1 | ❌ | <details><summary>Thermal pad incorrectly connected to floating net SNTP1 instead of GND. The exposed pad should be connected to ground for proper thermal dissipation and electrical stability.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="39.89,80.34,47.39,87.84" aspect-ratio="1.29" } <ul><li>Pin 15 (PAD) is connected to net SNTP1 (from schematic)</li><li>SNTP1 is a page-local net with no other connections (from whole-design connectivity for SNTP1)</li><li>The PAD pin is the exposed thermal pad on the QFN package bottom (reasoning)</li><li>Thermal pads on digital ICs should be connected to GND for heat dissipation and to provide a low-impedance ground reference (reasoning)</li><li>Leaving the thermal pad floating reduces thermal performance and may cause electrical instability (reasoning)</li><li>The PAD pin should be connected to GND instead of the floating SNTP1 net (reasoning)</li></ul></details> | | 7 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 14 | VCC | +5VCC | ✅ | Power supply pin correctly connected to +5VCC with local decoupling. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=49.43,19.21,60.56,27.89&zoom=1">U2C</a> - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) Part Number: `SN74AHCT125RGYR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 8 | 3Y | NetR99_1 | ✅ | Output pin correctly drives MOSFET gate through 100Ω series resistor R99. | | 9 | 3A | Fan2 | ✅ | Input pin correctly connected to Fan2 control signal from the microcontroller. | | 10 | 3OE | GND | ✅ | Output enable pin correctly tied to GND to permanently enable the buffer output. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=50.79,79.52,58.29,87.49&zoom=1">C106</a> - 100nF 6.3V X5R 0201 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CL03A104KQ3NNNC) Part Number: `CL03A104KQ3NNNC` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor correctly connected between 3.3VCC and GND to provide local filtering for the 3.3V rail used by tachometer circuits on this page. | | 2 | 2 | 3.3VCC | ✅ | Decoupling capacitor correctly connected between 3.3VCC and GND to provide local filtering for the 3.3V rail used by tachometer circuits on this page. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=33.53,79.52,41.03,87.49&zoom=1">C92</a> - 100nF 0402 16V X7R ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Decoupling capacitor correctly connected between +5VCC and GND to provide high-frequency filtering for the buffer IC. | | 2 | 2 | +5VCC | ✅ | Decoupling capacitor correctly connected between +5VCC and GND to provide high-frequency filtering for the buffer IC. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=12.63,19.21,23.77,27.89&zoom=1">U2D</a> - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) Part Number: `SN74AHCT125RGYR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 11 | 4Y | NetR98_1 | ✅ | Output pin correctly drives MOSFET gate through 100Ω series resistor R98. | | 12 | 4A | Fan1 | ✅ | Input pin correctly connected to Fan1 control signal from the microcontroller. | | 13 | 4OE | GND | ✅ | Output enable pin correctly tied to GND to permanently enable the buffer output. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=26.72,10.39,34.22,19.07&zoom=1">R96</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-074K7L) Part Number: `RC0402FR-074K7L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetLED1_A | ✅ | LED current limiting resistor correctly connected between VFAN and LED1 anode with appropriate 4.7K value, but has documentation inconsistency in PART field. | | 2 | 2 | VFAN | ✅ | LED current limiting resistor correctly connected between VFAN and LED1 anode with appropriate 4.7K value, but has documentation inconsistency in PART field. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,10.39,70.56,19.07&zoom=1">R12</a> - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-074K7L) Part Number: `RC0402FR-074K7L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetLED2_A | ✅ | LED current limiting resistor correctly connected between VFAN and LED2 anode with appropriate 4.7K value, but has documentation inconsistency in PART field. | | 2 | 2 | VFAN | ✅ | LED current limiting resistor correctly connected between VFAN and LED2 anode with appropriate 4.7K value, but has documentation inconsistency in PART field. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=75.78,16.27,84.19,26.12&zoom=1">J22</a> - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/0705430002) Part Number: `0705430002` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC153_2 | ✅ | Fan ground connection correctly routed to low-side driver drain for PWM switching. | | 2 | S | VFAN | ✅ | Fan power supply connection correctly connected to VFAN. | | 3 | S | NetJ22_3 | ✅ | Fan tachometer signal correctly connected to signal conditioning circuit. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=56.70,19.21,66.02,26.71&zoom=1">R99</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR99_1 | ✅ | Gate drive resistor correctly positioned between buffer output and driver gate. | | 2 | 2 | NetQ12_4 | ✅ | Gate drive resistor correctly positioned between buffer output and driver gate. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=26.72,13.92,34.22,22.60&zoom=1">LED1</a> - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988110107F) Part Number: `5988110107F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED1_A | ✅ | LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage). | | C | C | NetC154_2 | ✅ | LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage). | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=37.16,16.86,45.57,26.71&zoom=1">J29</a> - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/0705430002) Part Number: `0705430002` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC154_2 | ✅ | Fan ground connection correctly routed to low-side driver drain for PWM switching. | | 2 | S | VFAN | ✅ | Fan power supply connection correctly connected to VFAN. | | 3 | S | NetJ29_3 | ✅ | Fan tachometer signal correctly connected to signal conditioning circuit. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,13.92,70.56,22.60&zoom=1">LED2</a> - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988110107F) Part Number: `5988110107F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED2_A | ✅ | LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage). | | C | C | NetC153_2 | ✅ | LED correctly connected with anode to VFAN through current limiting resistor and cathode to driver drain. LED will be dim due to low current (2-5mA depending on VFAN voltage). | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=24.90,18.03,34.22,27.89&zoom=1">Q12A</a> - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) Part Number: `NCV8402ADDR2G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Source pin correctly connected to GND for low-side driver operation. | | 2 | G | NetQ12_2 | ✅ | Gate pin correctly driven through 100R series resistor from buffer output. | | 7 | D | NetC154_2 | ✅ | Drain pin correctly connected to fan connector and LED indicator for low-side switching. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=19.90,19.21,29.22,26.71&zoom=1">R98</a> - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-07100RL) Part Number: `RC0402FR-07100RL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR98_1 | ✅ | Gate drive resistor correctly positioned between buffer output and driver gate. | | 2 | 2 | NetQ12_2 | ✅ | Gate drive resistor correctly positioned between buffer output and driver gate. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=61.24,18.03,70.56,27.89&zoom=1">Q12B</a> - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) Part Number: `NCV8402ADDR2G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 3 | S | GND | ✅ | Source pin correctly connected to GND for low-side driver operation. | | 4 | G | NetQ12_4 | ✅ | Gate pin correctly driven through 100R series resistor from buffer output. | | 5 | D | NetC153_2 | ✅ | Drain pin correctly connected to fan connector and LED indicator for low-side switching. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,52.13,70.56,60.80&zoom=1">LED4</a> - 5988110107F ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988110107F) Part Number: `5988110107F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C | C | VFAN | ❌ | <details><summary>Cathode incorrectly connected to VFAN instead of switched net, preventing LED from functioning. This is the root cause affecting both LED4 and J30 pin 1.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="63.06,53.30,70.56,60.80" aspect-ratio="1.29" } <ul><li>Pin C (cathode) connects to VFAN (from schematic)</li><li>LED4 pin A (anode) connects through R14 (4.7kΩ) to VFAN (from schematic)</li><li>Both LED terminals are at VFAN potential, creating no voltage difference across the LED (reasoning)</li><li>No current can flow through the LED in this configuration (reasoning)</li><li>LED1 pin C connects to NetC154_2 (switched by Q12A pin 7), LED2 pin C connects to NetC153_2 (switched by Q12B pin 5), and LED3 pin C connects to NetC211_2 (switched by Q13A pin 7) (from schematic)</li><li>Following the established pattern, LED4 pin C should connect to a switched net controlled by Q13B pin 5 (reasoning)</li><li>Q13B pin 5 (drain) connects to VFAN instead of to a switched net, which is the fundamental circuit error (from schematic)</li><li>The cathode should connect to the same switched net as J30 pin 1 to provide proper fan indication (reasoning)</li><li>LED4 cannot function as a Fan4 indicator in the current configuration (reasoning)</li></ul></details> | | A | A | NetLED4_A | ✅ | Anode correctly connected through current limiting resistor to VFAN per intended topology, though LED cannot function due to cathode connection issue. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=75.78,54.48,84.19,64.33&zoom=1">J30</a> - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/0705430002) Part Number: `0705430002` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | VFAN | ✅ | Pin 1 incorrectly connected to VFAN instead of switched net. Should connect to the same switched net as LED4 pin C for proper fan control. | | 2 | S | VFAN | ✅ | Pin 2 correctly connected to VFAN to provide positive power supply to fan motor. | | 3 | S | NetJ30_3 | ✅ | Tachometer pin correctly connected to tachometer signal conditioning circuit. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=61.24,56.24,70.56,66.09&zoom=1">Q13B</a> - NCV8402AD ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) Part Number: `NCV8402ADDR2G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | D | VFAN | ❌ | <details><summary>Drain incorrectly connected directly to VFAN power rail instead of to a switched load. This prevents the driver from functioning and would create a short circuit when enabled.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="63.06,56.24,70.56,63.74" aspect-ratio="1.29" } <ul><li>Pin 5 (D) connects directly to VFAN (from schematic)</li><li>For a low-side driver, the drain/output should connect to the load being switched, not to the power supply (reasoning)</li><li>When the driver turns on, it would short VFAN to GND through the driver (reasoning)</li><li>Comparing to Q13A pin 7 which correctly connects to NetC211_2, and Q12B pin 5 which correctly connects to NetC153_2, this pin should connect to a switched load net (reasoning)</li><li>The drain should connect to a net that includes LED4 cathode, J30 pin 1, and C209 pin 2 to match the pattern of other fan channels (reasoning)</li><li>No datasheet provided for NCV8402AD to verify correct pin usage (reasoning)</li></ul></details> | | 3 | S | GND | ✅ | Source and gate pins correctly connected for low-side driver operation, but the drain connection error prevents proper function. | | 4 | G | NetQ13_4 | ✅ | Source and gate pins correctly connected for low-side driver operation, but the drain connection error prevents proper function. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=26.72,52.72,34.22,61.39&zoom=1">LED3</a> - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988110107F) Part Number: `5988110107F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED3_A | ✅ | LED correctly configured as Fan3 indicator with current flowing from VFAN through R15 to anode, and cathode switched to ground by Q13A. | | C | C | NetC211_2 | ✅ | LED correctly configured as Fan3 indicator with current flowing from VFAN through R15 to anode, and cathode switched to ground by Q13A. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=24.90,56.83,34.22,66.68&zoom=1">Q13A</a> - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) Part Number: `NCV8402ADDR2G` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Low-side driver correctly configured to switch Fan3 channel. Source connected to ground, gate driven through 100R resistor from buffer, drain switches LED3 and fan connector J31. | | 2 | G | NetQ13_2 | ✅ | Low-side driver correctly configured to switch Fan3 channel. Source connected to ground, gate driven through 100R resistor from buffer, drain switches LED3 and fan connector J31. | | 7 | D | NetC211_2 | ✅ | Low-side driver correctly configured to switch Fan3 channel. Source connected to ground, gate driven through 100R resistor from buffer, drain switches LED3 and fan connector J31. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=26.72,28.03,34.22,37.88&zoom=1">D50</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD50_A | ✅ | Anode connected to NetD50_A for upper voltage clamping function. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC to set the upper clamp voltage. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=27.62,32.14,36.03,39.64&zoom=1">R175</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD50_A | ✅ | Connected to NetD50_A to provide series resistance after the voltage clamping circuit. | | 2 | 2 | NetJ29_3 | ✅ | Connected to NetJ29_3, which goes to the fan connector and has a pull-up resistor. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=26.72,33.91,34.22,43.76&zoom=1">D52</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for lower voltage clamping function. | | K | K | NetD50_A | ✅ | Cathode connected to NetD50_A to set the lower clamp voltage. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=23.08,33.91,30.58,42.58&zoom=1">C155</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_1 | ✅ | Connected to TACH_1 signal for AC coupling and filtering of the fan tachometer input. | | 2 | 2 | GND | ✅ | Connected to GND to complete the filter capacitor connection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=24.90,32.14,33.31,39.64&zoom=1">R174</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_1 | ✅ | Connected to TACH_1 to provide series resistance before the voltage clamping circuit. | | 2 | 2 | NetD50_A | ✅ | Connected to NetD50_A, the internal node between the clamping diodes. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=31.26,29.20,38.76,37.88&zoom=1">R172</a> - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071K8L) Part Number: `RC0402FR-071K8L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ29_3 | ✅ | Connected to NetJ29_3 to provide pull-up function for the fan tachometer signal. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC power rail to complete the pull-up function. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,33.44,70.56,43.29&zoom=1">D53</a> - BAT54WX ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD53_A | ❌ | <details><summary>D53 anode is connected to floating net NetD53_A instead of GND, preventing the diode from functioning as a lower clamp for TACH_2 signal protection.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="63.06,35.79,70.56,43.29" aspect-ratio="1.29" } <ul><li>Anode (pin A) is connected to NetD53_A (from schematic)</li><li>Cathode (pin K) is connected to NetD51_A (from schematic)</li><li>NetD53_A is a page-local net with no other connections (from whole-design connectivity for NetD53_A)</li><li>The anode is the positive terminal of the Schottky diode and forward current flows from anode to cathode (from datasheet <a href="https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf#page=1">BAT54WX-TP</a>, page 1)</li><li>The cathode is the negative terminal of the Schottky diode and blocks reverse voltage up to 30V (from datasheet <a href="https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf#page=1">BAT54WX-TP</a>, page 1)</li><li>In the parallel TACH_1 circuit, D52 has anode connected to GND and cathode to NetD50_A, providing lower voltage clamping (from schematic)</li><li>In the parallel TACH_3 circuit, D56 has anode connected to GND and cathode to NetD54_A, providing lower voltage clamping (from schematic)</li><li>In the parallel TACH_4 circuit, D57 has anode connected to GND and cathode to NetD55_A, providing lower voltage clamping (from schematic)</li><li>For a lower clamp diode topology, the anode must be connected to GND to clamp negative voltages on the signal net to ground plus the diode forward voltage drop (reasoning)</li><li>With the anode floating on NetD53_A, D53 cannot conduct current and therefore cannot perform its intended clamping function for NetD51_A (reasoning)</li><li>The cathode connection to NetD51_A is correct for a lower clamp topology, but the diode is non-functional due to the incorrect anode connection (reasoning)</li><li>The D53 anode connection should be changed from NetD53_A to GND to match the reference circuits and provide proper negative voltage protection for the TACH_2 signal (reasoning)</li></ul></details> | | K | K | NetD51_A | ❌ | <details><summary>D53 anode is connected to floating net NetD53_A instead of GND, preventing the diode from functioning as a lower clamp for TACH_2 signal protection.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="63.06,33.44,70.56,40.94" aspect-ratio="1.29" } <ul><li>Anode (pin A) is connected to NetD53_A (from schematic)</li><li>Cathode (pin K) is connected to NetD51_A (from schematic)</li><li>NetD53_A is a page-local net with no other connections (from whole-design connectivity for NetD53_A)</li><li>The anode is the positive terminal of the Schottky diode and forward current flows from anode to cathode (from datasheet <a href="https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf#page=1">BAT54WX-TP</a>, page 1)</li><li>The cathode is the negative terminal of the Schottky diode and blocks reverse voltage up to 30V (from datasheet <a href="https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf#page=1">BAT54WX-TP</a>, page 1)</li><li>In the parallel TACH_1 circuit, D52 has anode connected to GND and cathode to NetD50_A, providing lower voltage clamping (from schematic)</li><li>In the parallel TACH_3 circuit, D56 has anode connected to GND and cathode to NetD54_A, providing lower voltage clamping (from schematic)</li><li>In the parallel TACH_4 circuit, D57 has anode connected to GND and cathode to NetD55_A, providing lower voltage clamping (from schematic)</li><li>For a lower clamp diode topology, the anode must be connected to GND to clamp negative voltages on the signal net to ground plus the diode forward voltage drop (reasoning)</li><li>With the anode floating on NetD53_A, D53 cannot conduct current and therefore cannot perform its intended clamping function for NetD51_A (reasoning)</li><li>The cathode connection to NetD51_A is correct for a lower clamp topology, but the diode is non-functional due to the incorrect anode connection (reasoning)</li><li>The D53 anode connection should be changed from NetD53_A to GND to match the reference circuits and provide proper negative voltage protection for the TACH_2 signal (reasoning)</li></ul></details> | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,27.44,70.56,37.29&zoom=1">D51</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD51_A | ✅ | Anode connected to NetD51_A for upper voltage clamping. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC for upper voltage clamping. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=59.42,33.32,66.92,41.99&zoom=1">C156</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_2 | ✅ | Connected to TACH_2 signal for filtering. | | 2 | 2 | GND | ✅ | Connected to GND for filtering. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=67.60,28.62,75.10,37.29&zoom=1">R173</a> - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071K8L) Part Number: `RC0402FR-071K8L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ22_3 | ✅ | Connected to NetJ22_3 as a pull-up resistor. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC to provide pull-up voltage. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.97,31.55,72.38,39.05&zoom=1">R177</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD51_A | ✅ | Connected to NetD51_A as part of voltage divider. | | 2 | 2 | NetJ22_3 | ✅ | Connected to NetJ22_3, which goes to the fan connector tachometer pin. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=61.24,31.55,69.65,39.05&zoom=1">R176</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_2 | ✅ | Connected to TACH_2 signal as part of voltage divider. | | 2 | 2 | NetD51_A | ✅ | Connected to NetD51_A, the intermediate node of the signal conditioning circuit. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=31.26,68.00,38.76,76.68&zoom=1">R184</a> - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071K8L) Part Number: `RC0402FR-071K8L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ31_3 | ✅ | Connected to NetJ31_3, providing pull-up for the fan tachometer signal. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC supply rail, providing the pull-up voltage reference. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=23.08,72.70,30.58,81.38&zoom=1">C212</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_3 | ✅ | Connected to TACH_3 signal, providing noise filtering for the tachometer input. | | 2 | 2 | GND | ✅ | Connected to GND, completing the filter capacitor to ground. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=24.90,70.94,33.31,78.44&zoom=1">R186</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_3 | ✅ | Connected to TACH_3 signal going to microcontroller. This is the output of the tachometer conditioning circuit. | | 2 | 2 | NetD54_A | ✅ | Connected to NetD54_A, the middle node of the voltage clamping network with diodes D54 and D56. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=26.72,66.82,34.22,76.68&zoom=1">D54</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD54_A | ✅ | Anode connected to NetD54_A, providing upper voltage clamp to 3.3VCC. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC, setting the upper clamp voltage reference. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=27.62,70.94,36.03,78.44&zoom=1">R187</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD54_A | ✅ | Connected to NetD54_A, the middle node of the voltage clamping network. | | 2 | 2 | NetJ31_3 | ✅ | Connected to NetJ31_3, which goes to the fan connector tachometer pin and has a pull-up resistor. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=26.72,72.70,34.22,82.55&zoom=1">D56</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND, setting the lower clamp voltage reference. | | K | K | NetD54_A | ✅ | Cathode connected to NetD54_A, providing lower voltage clamp protection. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,72.11,70.56,81.97&zoom=1">D57</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for lower voltage clamping. | | K | K | NetD55_A | ✅ | Cathode connected to NetD55_A for lower voltage clamping. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=67.60,67.41,75.10,76.09&zoom=1">R185</a> - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071K8L) Part Number: `RC0402FR-071K8L` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ30_3 | ✅ | Connected to NetJ30_3 as pull-up resistor input. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC to provide pull-up voltage. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,66.24,70.56,76.09&zoom=1">D55</a> - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) Part Number: `BAT54WX-TP` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD55_A | ✅ | Anode connected to NetD55_A for upper voltage clamping. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC for upper voltage clamping. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=61.24,70.35,69.65,77.85&zoom=1">R188</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_4 | ✅ | Connected to TACH_4 signal as series input resistance. | | 2 | 2 | NetD55_A | ✅ | Connected to intermediate node NetD55_A in the protection circuit. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=59.42,72.11,66.92,80.79&zoom=1">C213</a> - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/datasheet/3/76/2/GRM155R71C104KA88_01A.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) Part Number: `GRM155R71C104KA88D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_4 | ✅ | Connected to TACH_4 signal for input filtering. | | 2 | 2 | GND | ✅ | Connected to GND for filtering reference. | </details> <details> <summary><a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.97,70.35,72.38,77.85&zoom=1">R189</a> - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) (via Mouser) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) Part Number: `RC0402FR-071KL` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD55_A | ✅ | Connected to intermediate node NetD55_A in the protection circuit. | | 2 | 2 | NetJ30_3 | ✅ | Connected to NetJ30_3 which routes to the fan connector. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **J18** (0475710001): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/0475710001) - **J22, J29, J30, J31** (0705430002): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/0705430002) - **S1** (1571610-2): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/1571610-2) - **J4** (20021121-00010C4LF): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/20021121-00010C4LF) - **P1** (2213S-08G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/2213S-08G) - **J20** (2213S-24G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/2213S-24G) - **J12, J13, J28** (302-S101): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/302-S101) - **X1** (405C35B12M00000): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/405C35B12M00000) - **C14, C16, C93** (490-10756-2-ND): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/490-10756-2-ND) - **J3** (4DB-P108-10): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/4DB-P108-10) - **D24, LED1, LED2, LED3, LED4** (5988110107F): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988110107F) - **D25** (5988140107F): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988140107F) - **J8** (61729-0010BLF): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/61729-0010BLF) - **U14** (74AVC9112GTX): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/74AVC9112GTX) - **U9** (ADUM3160BRWZ-RL): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ADUM3160BRWZ-RL) - **U12** (AT25SF161-SSHD-T): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AT25SF161-SSHD-T) - **RV1, RV2, RV3, RV4** (AVRM0603C6R8NT101N): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) - **C150** (C0402C222J3GACTU): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C0402C222J3GACTU) - **C37, C53, C55, C57, C70, C72** (C1608JB0J106K080AB): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/C1608JB0J106K080AB) - **FB26, FB27, FB28, FB29, FB30** (CIS10P121AC): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CIS10P121AC) - **C106** (CL03A104KQ3NNNC): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CL03A104KQ3NNNC) - **C49** (CL05C100JB5NNNC): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CL05C100JB5NNNC) - **R154, R26** (CRCW040224K0FKEDC): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040224K0FKEDC) - **R13, R3, R32, R4, R59, R84, R89, R93, R94** (CRCW040247R0FKEDC): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) - **R150, R151, R49** (CRCW04026K80FKED): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/CRCW04026K80FKED) - **D45** (DF2S6.8FS,L3M): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/DF2S6.8FS%2CL3M) - **L5** (DLW21HN900SQ2L): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/DLW21HN900SQ2L) - **R60** (DNI-R0402TBD): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/DNI-R0402TBD) - **R156, R28** (ERJ2GEJ105X): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ERJ2GEJ105X) - **D1, D42, D44, D64, D65, D66, D67, D68, D69, D71, D72, D73** (ESD9X3.3ST5G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) - **C24, C32, C34** (GRM155R60J105KE19D): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R60J105KE19D) - **C13, C17, C35, C94** (GRM155R71H102KA01D): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H102KA01D) - **C171, C40, C43, C71, C77** (GRM155R71H103JA88D): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) - **U19** (INA381A2IDSGR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/INA381A2IDSGR) - **S2** (KMR741NG ULC LFS): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/KMR741NG%20ULC%20LFS) - **U20** (L78L05ABUTR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/L78L05ABUTR) - **Q12A, Q12B, Q13A, Q13B** (NCV8402ADDR2G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) - **D27** (PRTR5V0U2F,115): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/PRTR5V0U2F%2C115) - **R158, R31, R37, R38, R51, R58** (RC1005F104CS): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F104CS) - **R115** (RC1005F153CS): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC1005F153CS) - **D26** (RSB39VTE-17): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RSB39VTE-17) - **U2A, U2B, U2C, U2D, U2E** (SN74AHCT125RGYR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) - **U16, U17** (SN74LVC125ARGYR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) - **C101, C102, C104, C64, C74, C75, C79, C83, C85, C87, C88, C89, C90** (TBD): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TBD) - **U1** (TPS54531DDAR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/TPS54531DDAR) </details> Note: DRCY uses AI. Please verify the outputs.

Fans.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[🚨 Error] Component U2E, pin 15: Thermal pad incorrectly connected to floating net SNTP1 instead of GND. The exposed pad should be connected to ground for proper thermal dissipation and electrical stability.

Pin 15 (PAD) is connected to net SNTP1 (from schematic)
SNTP1 is a page-local net with no other connections (from whole-design connectivity for SNTP1)
The PAD pin is the exposed thermal pad on the QFN package bottom (reasoning)
Thermal pads on digital ICs should be connected to GND for heat dissipation and to provide a low-impedance ground reference (reasoning)
Leaving the thermal pad floating reduces thermal performance and may cause electrical instability (reasoning)
The PAD pin should be connected to GND instead of the floating SNTP1 net (reasoning)

_{Upload a datasheet: 📤 U2E}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

[🚨 Error] **Component [`U2E`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=39.89,78.58,48.75,89.61&zoom=1>), pin `15`: Thermal pad incorrectly connected to floating net SNTP1 instead of GND. The exposed pad should be connected to ground for proper thermal dissipation and electrical stability.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="39.89,80.34,47.39,87.84" aspect-ratio="1.29" } - Pin 15 (PAD) is connected to net SNTP1 *(from schematic)* - SNTP1 is a page-local net with no other connections *(from whole-design connectivity for SNTP1)* - The PAD pin is the exposed thermal pad on the QFN package bottom *(reasoning)* - Thermal pads on digital ICs should be connected to GND for heat dissipation and to provide a low-impedance ground reference *(reasoning)* - Leaving the thermal pad floating reduces thermal performance and may cause electrical instability *(reasoning)* - The PAD pin should be connected to GND instead of the floating SNTP1 net *(reasoning)* Upload a datasheet: [📤 U2E](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

Fans.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[🚨 Error] Component LED4, pin C: Cathode incorrectly connected to VFAN instead of switched net, preventing LED from functioning. This is the root cause affecting both LED4 and J30 pin 1.

Pin C (cathode) connects to VFAN (from schematic)
LED4 pin A (anode) connects through R14 (4.7kΩ) to VFAN (from schematic)
Both LED terminals are at VFAN potential, creating no voltage difference across the LED (reasoning)
No current can flow through the LED in this configuration (reasoning)
LED1 pin C connects to NetC154_2 (switched by Q12A pin 7), LED2 pin C connects to NetC153_2 (switched by Q12B pin 5), and LED3 pin C connects to NetC211_2 (switched by Q13A pin 7) (from schematic)
Following the established pattern, LED4 pin C should connect to a switched net controlled by Q13B pin 5 (reasoning)
Q13B pin 5 (drain) connects to VFAN instead of to a switched net, which is the fundamental circuit error (from schematic)
The cathode should connect to the same switched net as J30 pin 1 to provide proper fan indication (reasoning)
LED4 cannot function as a Fan4 indicator in the current configuration (reasoning)

2 affected locations — one shared root cause

Component LED4, pin `C`
Component Q13B, pin `5`

Per-location differences

Component Q13B, pin `5`: Drain incorrectly connected directly to VFAN power rail instead of to a switched load. This prevents the driver from functioning and would create a short circuit when enabled.

Pin 5 (D) connects directly to VFAN (from schematic)
For a low-side driver, the drain/output should connect to the load being switched, not to the power supply (reasoning)
When the driver turns on, it would short VFAN to GND through the driver (reasoning)
Comparing to Q13A pin 7 which correctly connects to NetC211_2, and Q12B pin 5 which correctly connects to NetC153_2, this pin should connect to a switched load net (reasoning)
The drain should connect to a net that includes LED4 cathode, J30 pin 1, and C209 pin 2 to match the pattern of other fan channels (reasoning)
No datasheet provided for NCV8402AD to verify correct pin usage (reasoning)

_{Upload a datasheet: 📤 LED4 📤 Q13B}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

[🚨 Error] **Component [`LED4`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,52.13,70.56,60.80&zoom=1>), pin `C`: Cathode incorrectly connected to VFAN instead of switched net, preventing LED from functioning. This is the root cause affecting both LED4 and J30 pin 1.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="63.06,53.30,70.56,60.80" aspect-ratio="1.29" } - Pin C (cathode) connects to VFAN *(from schematic)* - LED4 pin A (anode) connects through R14 (4.7kΩ) to VFAN *(from schematic)* - Both LED terminals are at VFAN potential, creating no voltage difference across the LED *(reasoning)* - No current can flow through the LED in this configuration *(reasoning)* - LED1 pin C connects to NetC154_2 (switched by Q12A pin 7), LED2 pin C connects to NetC153_2 (switched by Q12B pin 5), and LED3 pin C connects to NetC211_2 (switched by Q13A pin 7) *(from schematic)* - Following the established pattern, LED4 pin C should connect to a switched net controlled by Q13B pin 5 *(reasoning)* - Q13B pin 5 (drain) connects to VFAN instead of to a switched net, which is the fundamental circuit error *(from schematic)* - The cathode should connect to the same switched net as J30 pin 1 to provide proper fan indication *(reasoning)* - LED4 cannot function as a Fan4 indicator in the current configuration *(reasoning)* <details> <summary>2 affected locations — one shared root cause</summary> <ul> <li>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,52.13,70.56,60.80&zoom=1"><code>LED4</code></a>, pin `C`</li> <li>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=61.24,56.24,70.56,66.09&zoom=1"><code>Q13B</code></a>, pin `5`</li> </ul> #### Per-location differences <details> <summary>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=61.24,56.24,70.56,66.09&zoom=1"><code>Q13B</code></a>, pin `5`: Drain incorrectly connected directly to VFAN power rail instead of to a switched load. This prevents the driver from functioning and would create a short circuit when enabled.</summary> - Pin 5 (D) connects directly to VFAN *(from schematic)* - For a low-side driver, the drain/output should connect to the load being switched, not to the power supply *(reasoning)* - When the driver turns on, it would short VFAN to GND through the driver *(reasoning)* - Comparing to Q13A pin 7 which correctly connects to NetC211_2, and Q12B pin 5 which correctly connects to NetC153_2, this pin should connect to a switched load net *(reasoning)* - The drain should connect to a net that includes LED4 cathode, J30 pin 1, and C209 pin 2 to match the pattern of other fan channels *(reasoning)* - No datasheet provided for NCV8402AD to verify correct pin usage *(reasoning)* </details> </details> Upload a datasheet: [📤 LED4](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/5988110107F) [📤 Q13B](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

Fans.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[🚨 Error] Component D53, pins A, K: D53 anode is connected to floating net NetD53_A instead of GND, preventing the diode from functioning as a lower clamp for TACH_2 signal protection.

Anode (pin A) is connected to NetD53_A (from schematic)
Cathode (pin K) is connected to NetD51_A (from schematic)
NetD53_A is a page-local net with no other connections (from whole-design connectivity for NetD53_A)
The anode is the positive terminal of the Schottky diode and forward current flows from anode to cathode (from datasheet BAT54WX-TP, page 1)
The cathode is the negative terminal of the Schottky diode and blocks reverse voltage up to 30V (from datasheet BAT54WX-TP, page 1)
In the parallel TACH_1 circuit, D52 has anode connected to GND and cathode to NetD50_A, providing lower voltage clamping (from schematic)
In the parallel TACH_3 circuit, D56 has anode connected to GND and cathode to NetD54_A, providing lower voltage clamping (from schematic)
In the parallel TACH_4 circuit, D57 has anode connected to GND and cathode to NetD55_A, providing lower voltage clamping (from schematic)
For a lower clamp diode topology, the anode must be connected to GND to clamp negative voltages on the signal net to ground plus the diode forward voltage drop (reasoning)
With the anode floating on NetD53_A, D53 cannot conduct current and therefore cannot perform its intended clamping function for NetD51_A (reasoning)
The cathode connection to NetD51_A is correct for a lower clamp topology, but the diode is non-functional due to the incorrect anode connection (reasoning)
The D53 anode connection should be changed from NetD53_A to GND to match the reference circuits and provide proper negative voltage protection for the TACH_2 signal (reasoning)

Datasheets: 📄 D53

_{Replace a datasheet: 📤 D53}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

[🚨 Error] **Component [`D53`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Fans.SchDoc?view-coordinates=63.06,33.44,70.56,43.29&zoom=1>), pins `A, K`: D53 anode is connected to floating net NetD53_A instead of GND, preventing the diode from functioning as a lower clamp for TACH_2 signal protection.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="63.06,33.44,70.56,43.29" aspect-ratio="1.29" } - Anode (pin A) is connected to NetD53_A *(from schematic)* - Cathode (pin K) is connected to NetD51_A *(from schematic)* - NetD53_A is a page-local net with no other connections *(from whole-design connectivity for NetD53_A)* - The anode is the positive terminal of the Schottky diode and forward current flows from anode to cathode *(from datasheet [BAT54WX-TP](<https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf#page=1>), page 1)* - The cathode is the negative terminal of the Schottky diode and blocks reverse voltage up to 30V *(from datasheet [BAT54WX-TP](<https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf#page=1>), page 1)* - In the parallel TACH_1 circuit, D52 has anode connected to GND and cathode to NetD50_A, providing lower voltage clamping *(from schematic)* - In the parallel TACH_3 circuit, D56 has anode connected to GND and cathode to NetD54_A, providing lower voltage clamping *(from schematic)* - In the parallel TACH_4 circuit, D57 has anode connected to GND and cathode to NetD55_A, providing lower voltage clamping *(from schematic)* - For a lower clamp diode topology, the anode must be connected to GND to clamp negative voltages on the signal net to ground plus the diode forward voltage drop *(reasoning)* - With the anode floating on NetD53_A, D53 cannot conduct current and therefore cannot perform its intended clamping function for NetD51_A *(reasoning)* - The cathode connection to NetD51_A is correct for a lower clamp topology, but the diode is non-functional due to the incorrect anode connection *(reasoning)* - The D53 anode connection should be changed from NetD53_A to GND to match the reference circuits and provide proper negative voltage protection for the TACH_2 signal *(reasoning)* Datasheets: [📄 D53](https://www.mouser.com/datasheet/3/225/1/BAT54WX_SOD_523.pdf) Replace a datasheet: [📤 D53](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/BAT54WX-TP) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

Microcontroller.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[🚨 Error] Component R41, pins 1, 2: R41 connects two GPIO pins of the same microcontroller (PA1_CANRX0 and PA5_PWM) together through a 1kΩ resistor. This is an unusual and likely incorrect connection that serves no clear purpose and could cause pin conflicts.

R41 pin 1 is connected to net PA1_CANRX0, which connects to U11A pin 24 (from schematic)
R41 pin 2 is connected to net PA5_PWM, which connects to U11A pin 25 (from schematic)
U11A pin 24 (PA1) can be configured as CANRX0, PCK0, or WKUP0 according to the datasheet (from datasheet ATSAM3X8EA-AU, page 18)
U11A pin 25 (PA5) can be configured as TIOA2, PWMFI0, or WKUP2 according to the datasheet (from datasheet ATSAM3X8EA-AU, page 18)
Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0)
Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections (from whole-design connectivity for PA5_PWM)
R41 is a 1kΩ 1% 1/16W resistor in 0402 package (from datasheet RC0402FR-071KL, page 4)
Connecting two GPIO pins of the same microcontroller together through a resistor is not a standard design practice and serves no clear functional purpose (reasoning)
If both pins are configured as outputs driving different logic levels, the 1kΩ resistor would create a conflict and excessive current draw (reasoning)
No text notes on the schematic page explain or justify this connection between PA1_CANRX0 and PA5_PWM (reasoning)
This connection should be reviewed and likely removed, or one end should be connected to the intended destination if this is a routing error (reasoning)

2 affected locations — one shared root cause

Component U11A, pins `24, 25`
Component R41, pins `1, 2`

Per-location differences

Component U11A, pins `24, 25`: PA1 (CANRX0) and PA5 (PWM) are incorrectly connected together through R41 (1k). This connection serves no clear functional purpose and will cause signal integrity issues.

Pin 24 is PA1 which can be configured as CANRX0, PCK0, or general I/O with WKUP0 function (from datasheet ATSAM3X8EA-AU, page 18)
Pin 25 is PA5 which can be configured as TIOA2, PWMFI0, or general I/O with WKUP2 function (from datasheet ATSAM3X8EA-AU, page 18)
Pin 24 is connected to net PA1_CANRX0 and pin 25 to net PA5_PWM (from schematic)
R41 (1k) connects PA5_PWM to PA1_CANRX0 (from schematic)
PA1_CANRX0 and PA5_PWM are both page-local nets with no external connections (from whole-design connectivity for PA1_CANRX0)
PA1 is typically used as CAN receive input (CANRX0) and PA5 as timer/PWM output (TIOA2/PWMFI0) (reasoning)
Connecting a CAN receive input to a PWM/timer output through a 1k resistor serves no standard circuit purpose (reasoning)
If PA5 actively drives PWM signals, it will interfere with CAN reception on PA1 (reasoning)
If PA1 receives CAN data, the 1k resistor connection to PA5 will load the CAN bus and may cause communication errors (reasoning)
PA5_PWM has no other connections besides R41, suggesting it is not used for any intended function (from schematic)
R41 should be removed and the connection between PA1 and PA5 eliminated (reasoning)

Datasheets: 📄 R41 📄 U11A

_{Replace a datasheet: 📤 R41 📤 U11A}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

[🚨 Error] **Component [`R41`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=73.30,58.06,81.98,65.56&zoom=1>), pins `1, 2`: R41 connects two GPIO pins of the same microcontroller (PA1_CANRX0 and PA5_PWM) together through a 1kΩ resistor. This is an unusual and likely incorrect connection that serves no clear purpose and could cause pin conflicts.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="73.30,58.06,81.98,65.56" aspect-ratio="1.55" } - R41 pin 1 is connected to net PA1_CANRX0, which connects to U11A pin 24 *(from schematic)* - R41 pin 2 is connected to net PA5_PWM, which connects to U11A pin 25 *(from schematic)* - U11A pin 24 (PA1) can be configured as CANRX0, PCK0, or WKUP0 according to the datasheet *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - U11A pin 25 (PA5) can be configured as TIOA2, PWMFI0, or WKUP2 according to the datasheet *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections *(from whole-design connectivity for PA1_CANRX0)* - Both PA1_CANRX0 and PA5_PWM are page-local nets with no external connections *(from whole-design connectivity for PA5_PWM)* - R41 is a 1kΩ 1% 1/16W resistor in 0402 package *(from datasheet [RC0402FR-071KL](<https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf#page=4>), page 4)* - Connecting two GPIO pins of the same microcontroller together through a resistor is not a standard design practice and serves no clear functional purpose *(reasoning)* - If both pins are configured as outputs driving different logic levels, the 1kΩ resistor would create a conflict and excessive current draw *(reasoning)* - No text notes on the schematic page explain or justify this connection between PA1_CANRX0 and PA5_PWM *(reasoning)* - This connection should be reviewed and likely removed, or one end should be connected to the intended destination if this is a routing error *(reasoning)* <details> <summary>2 affected locations — one shared root cause</summary> <ul> <li>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=30.08,0.82,54.04,66.47&zoom=1"><code>U11A</code></a>, pins `24, 25`</li> <li>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=73.30,58.06,81.98,65.56&zoom=1"><code>R41</code></a>, pins `1, 2`</li> </ul> #### Per-location differences <details> <summary>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=30.08,0.82,54.04,66.47&zoom=1"><code>U11A</code></a>, pins `24, 25`: PA1 (CANRX0) and PA5 (PWM) are incorrectly connected together through R41 (1k). This connection serves no clear functional purpose and will cause signal integrity issues.</summary> - Pin 24 is PA1 which can be configured as CANRX0, PCK0, or general I/O with WKUP0 function *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Pin 25 is PA5 which can be configured as TIOA2, PWMFI0, or general I/O with WKUP2 function *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Pin 24 is connected to net PA1_CANRX0 and pin 25 to net PA5_PWM *(from schematic)* - R41 (1k) connects PA5_PWM to PA1_CANRX0 *(from schematic)* - PA1_CANRX0 and PA5_PWM are both page-local nets with no external connections *(from whole-design connectivity for PA1_CANRX0)* - PA1 is typically used as CAN receive input (CANRX0) and PA5 as timer/PWM output (TIOA2/PWMFI0) *(reasoning)* - Connecting a CAN receive input to a PWM/timer output through a 1k resistor serves no standard circuit purpose *(reasoning)* - If PA5 actively drives PWM signals, it will interfere with CAN reception on PA1 *(reasoning)* - If PA1 receives CAN data, the 1k resistor connection to PA5 will load the CAN bus and may cause communication errors *(reasoning)* - PA5_PWM has no other connections besides R41, suggesting it is not used for any intended function *(from schematic)* - R41 should be removed and the connection between PA1 and PA5 eliminated *(reasoning)* </details> </details> Datasheets: [📄 R41](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) [📄 U11A](https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) Replace a datasheet: [📤 R41](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-071KL) [📤 U11A](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

Microcontroller.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[🚨 Error] Component U11A, pins 29, 30: PB29 (TDI) and PB30 (TDO) are swapped - TDI pin connected to TDO/SWO net and TDO pin connected to TDI net.

Pin 29 is PB29 which is TDI after reset (from datasheet ATSAM3X8EA-AU, page 18)
Pin 30 is PB30 which is TDO/TRACESWO after reset (from datasheet ATSAM3X8EA-AU, page 18)
Pin 29 is connected to net TDO/SWO (from schematic)
Pin 30 is connected to net TDI (from schematic)
TDO/SWO net connects to J4 pin 6 (from schematic)
TDI net connects to J4 pin 8 (from schematic)
In JTAG standard, TDI is input to target and TDO is output from target (reasoning)
The MCU TDI pin should connect to the connector TDI pin, and MCU TDO should connect to connector TDO (reasoning)
The connections are swapped - pin 29 (TDI) should connect to TDI net, and pin 30 (TDO) should connect to TDO/SWO net (reasoning)
This swap will prevent JTAG debugging from functioning correctly (reasoning)

Datasheets: 📄 U11A

_{Replace a datasheet: 📤 U11A}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

[🚨 Error] **Component [`U11A`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=30.08,0.82,54.04,66.47&zoom=1>), pins `29, 30`: PB29 (TDI) and PB30 (TDO) are swapped - TDI pin connected to TDO/SWO net and TDO pin connected to TDI net.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.08,54.04,36.49" aspect-ratio="1.55" } - Pin 29 is PB29 which is TDI after reset *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Pin 30 is PB30 which is TDO/TRACESWO after reset *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Pin 29 is connected to net TDO/SWO *(from schematic)* - Pin 30 is connected to net TDI *(from schematic)* - TDO/SWO net connects to J4 pin 6 *(from schematic)* - TDI net connects to J4 pin 8 *(from schematic)* - In JTAG standard, TDI is input to target and TDO is output from target *(reasoning)* - The MCU TDI pin should connect to the connector TDI pin, and MCU TDO should connect to connector TDO *(reasoning)* - The connections are swapped - pin 29 (TDI) should connect to TDI net, and pin 30 (TDO) should connect to TDO/SWO net *(reasoning)* - This swap will prevent JTAG debugging from functioning correctly *(reasoning)* Datasheets: [📄 U11A](https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) Replace a datasheet: [📤 U11A](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

Microcontroller.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[⚠️ Warning] Component S2, pins 2, 4: Pins 2 and 4 are connected to page-local nets NetS2_2 and NetS2_4 respectively, which have no other connections, leaving these pins floating. Without the component datasheet to verify the internal pinout, this configuration is uncertain and potentially incorrect. Best practice is to explicitly connect pin 2 to 3.3VCC (same as pin 1) and pin 4 to ERASE (same as pin 3) to ensure proper switch operation regardless of the actual internal pinout.

Pin 2 is connected to net NetS2_2 (from schematic)
Pin 4 is connected to net NetS2_4 (from schematic)
NetS2_2 and NetS2_4 are page-local nets with no other connections on this page or any other page (from whole-design connectivity for NetS2_2)
The component is described as 'Tactile Switch SPST-NO Top Actuated Surface Mount', indicating a single-pole single-throw normally-open switch (from schematic)
In typical 4-pin tactile switches, pins are arranged in two pairs where each pair is internally connected, with two common configurations: pins 1-2 as one terminal and 3-4 as the other, or pins 1-4 as one terminal and 2-3 as the other (reasoning)
If the switch pinout is 1-2 / 3-4 (most common for KMR741 series), the current configuration would work because pin 2 is internally connected to pin 1 (3.3VCC) and pin 4 is internally connected to pin 3 (ERASE), making the floating nets functionally acceptable (reasoning)
If the switch pinout is 1-4 / 2-3 (alternative configuration), the current configuration would not work because pressing the button would connect pin 1 (3.3VCC) to pin 2 (floating NetS2_2) and pin 3 (ERASE) to pin 4 (floating NetS2_4), preventing ERASE from being pulled high (reasoning)
Without the component datasheet to verify the actual pinout, there is uncertainty about whether the current configuration will function correctly (reasoning)
Best practice for 4-pin tactile switches is to explicitly connect both pins of each terminal pair to ensure proper operation regardless of the internal pinout: pin 2 should be connected to 3.3VCC (same as pin 1) and pin 4 should be connected to ERASE (same as pin 3) (reasoning)
Explicitly connecting all four pins would guarantee functionality with either possible pinout configuration and eliminate any ambiguity (reasoning)

_{Upload a datasheet: 📤 S2}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

[⚠️ Warning] **Component [`S2`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=24.20,29.44,34.05,37.85&zoom=1>), pins `2, 4`: Pins 2 and 4 are connected to page-local nets NetS2_2 and NetS2_4 respectively, which have no other connections, leaving these pins floating. Without the component datasheet to verify the internal pinout, this configuration is uncertain and potentially incorrect. Best practice is to explicitly connect pin 2 to 3.3VCC (same as pin 1) and pin 4 to ERASE (same as pin 3) to ensure proper switch operation regardless of the actual internal pinout.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="24.20,30.35,34.05,37.85" aspect-ratio="1.55" } - Pin 2 is connected to net NetS2_2 *(from schematic)* - Pin 4 is connected to net NetS2_4 *(from schematic)* - NetS2_2 and NetS2_4 are page-local nets with no other connections on this page or any other page *(from whole-design connectivity for NetS2_2)* - The component is described as 'Tactile Switch SPST-NO Top Actuated Surface Mount', indicating a single-pole single-throw normally-open switch *(from schematic)* - In typical 4-pin tactile switches, pins are arranged in two pairs where each pair is internally connected, with two common configurations: pins 1-2 as one terminal and 3-4 as the other, or pins 1-4 as one terminal and 2-3 as the other *(reasoning)* - If the switch pinout is 1-2 / 3-4 (most common for KMR741 series), the current configuration would work because pin 2 is internally connected to pin 1 (3.3VCC) and pin 4 is internally connected to pin 3 (ERASE), making the floating nets functionally acceptable *(reasoning)* - If the switch pinout is 1-4 / 2-3 (alternative configuration), the current configuration would not work because pressing the button would connect pin 1 (3.3VCC) to pin 2 (floating NetS2_2) and pin 3 (ERASE) to pin 4 (floating NetS2_4), preventing ERASE from being pulled high *(reasoning)* - Without the component datasheet to verify the actual pinout, there is uncertainty about whether the current configuration will function correctly *(reasoning)* - Best practice for 4-pin tactile switches is to explicitly connect both pins of each terminal pair to ensure proper operation regardless of the internal pinout: pin 2 should be connected to 3.3VCC (same as pin 1) and pin 4 should be connected to ERASE (same as pin 3) *(reasoning)* - Explicitly connecting all four pins would guarantee functionality with either possible pinout configuration and eliminate any ambiguity *(reasoning)* Upload a datasheet: [📤 S2](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/KMR741NG%20ULC%20LFS) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

Microcontroller.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[💡 Recommendation] Component J20, pins 5, 6, 7, 9, 10, 12: These header pins are connected to page-local nets with no other connections and are not marked as no-connects.

Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively (from schematic)
Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page (from whole-design connectivity for NetJ20_5)
These pins are not marked as no-connects in the schematic (from schematic)
Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins (from schematic)
Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects (reasoning)
Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design (reasoning)
These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent (reasoning)

_{Upload a datasheet: 📤 J20}

_{^{💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.}}

[💡 Recommendation] **Component [`J20`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Microcontroller.SchDoc?view-coordinates=57.72,81.69,67.57,100.00&zoom=1>), pins `5, 6, 7, 9, 10, 12`: These header pins are connected to page-local nets with no other connections and are not marked as no-connects.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="57.72,87.14,67.57,97.36" aspect-ratio="1.55" } - Pins 5, 6, 7, 9, 10, 12 are connected to nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, NetJ20_12 respectively *(from schematic)* - Nets NetJ20_5, NetJ20_6, NetJ20_7, NetJ20_9, NetJ20_10, and NetJ20_12 are page-local with no connections on any other schematic page *(from whole-design connectivity for NetJ20_5)* - These pins are not marked as no-connects in the schematic *(from schematic)* - Other pins on this header (11, 13, 14, 17) are marked as intentional no-connects, indicating the designer knows how to mark unused pins *(from schematic)* - Standard practice for unused connector pins is to either connect them to useful signals, tie them to ground, or mark them as no-connects *(reasoning)* - Having connector pins connected to nets that go nowhere without marking them as no-connects is ambiguous and could indicate incomplete design *(reasoning)* - These pins should be reviewed to determine if they should be connected to signals, tied to ground, or marked as no-connects to clarify design intent *(reasoning)* Upload a datasheet: [📤 J20](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/2213S-24G) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

Power.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[🚨 Error] Component D21, pins A, K: TVS diode connections are reversed. The anode is connected to VMOT2 and cathode to GND, which places the diode in forward-bias during normal operation instead of providing transient protection.

Pin A (Anode) is connected to net VMOT2 (from schematic)
Pin K (Cathode) is connected to net GND (from schematic)
VMOT2 is a motor power input rail labeled 'MOTORS 5-8' with specified input range of 12-24VDC per the page note 'Inputs Compatible with 12-24VDC' (from schematic)
The cathode terminal is marked with a color band on the package body, and the anode is the unmarked terminal opposite to the cathode band (from datasheet SMAJ24A, page 2)
For unidirectional TVS diode protection of a positive voltage rail, the standard configuration is cathode to the protected positive rail and anode to ground, allowing the TVS to remain reverse-biased during normal operation (reasoning)
With the current connection (anode to VMOT2, cathode to GND), the TVS diode is forward-biased during normal operation, which would cause it to conduct continuously and effectively short VMOT2 to ground through the diode's forward voltage drop (reasoning)
Other TVS diodes on the same page protecting similar positive rails (D22 on VPWR, D43 on VMOT1, D78 on VBED) all have their anodes connected to GND and cathodes to the positive rail being protected (from schematic)
The SMAJ24A has a reverse stand-off voltage (VRWM) of 24.0V, breakdown voltage (VBR) of 26.70V minimum to 29.50V maximum, and maximum clamping voltage of 38.9V at 10.3A peak pulse current (from datasheet SMAJ24A, page 4)
The connections should be corrected to: Pin A (Anode) to GND and Pin K (Cathode) to VMOT2 to provide proper transient voltage protection (reasoning)

Datasheets: 📄 D21

_{Replace a datasheet: 📤 D21}

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[🚨 Error] **Component [`D21`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/Power.SchDoc?view-coordinates=2.64,54.95,10.14,63.63&zoom=1>), pins `A, K`: TVS diode connections are reversed. The anode is connected to VMOT2 and cathode to GND, which places the diode in forward-bias during normal operation instead of providing transient protection.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="2.64,54.95,10.14,63.63" aspect-ratio="1.29" } - Pin A (Anode) is connected to net VMOT2 *(from schematic)* - Pin K (Cathode) is connected to net GND *(from schematic)* - VMOT2 is a motor power input rail labeled 'MOTORS 5-8' with specified input range of 12-24VDC per the page note 'Inputs Compatible with 12-24VDC' *(from schematic)* - The cathode terminal is marked with a color band on the package body, and the anode is the unmarked terminal opposite to the cathode band *(from datasheet [SMAJ24A](<https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf#page=2>), page 2)* - For unidirectional TVS diode protection of a positive voltage rail, the standard configuration is cathode to the protected positive rail and anode to ground, allowing the TVS to remain reverse-biased during normal operation *(reasoning)* - With the current connection (anode to VMOT2, cathode to GND), the TVS diode is forward-biased during normal operation, which would cause it to conduct continuously and effectively short VMOT2 to ground through the diode's forward voltage drop *(reasoning)* - Other TVS diodes on the same page protecting similar positive rails (D22 on VPWR, D43 on VMOT1, D78 on VBED) all have their anodes connected to GND and cathodes to the positive rail being protected *(from schematic)* - The SMAJ24A has a reverse stand-off voltage (VRWM) of 24.0V, breakdown voltage (VBR) of 26.70V minimum to 29.50V maximum, and maximum clamping voltage of 38.9V at 10.3A peak pulse current *(from datasheet [SMAJ24A](<https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf#page=4>), page 4)* - The connections should be corrected to: Pin A (Anode) to GND and Pin K (Cathode) to VMOT2 to provide proper transient voltage protection *(reasoning)* Datasheets: [📄 D21](https://www.mouser.com/datasheet/3/508/1/smaj_1.pdf) Replace a datasheet: [📤 D21](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/SMAJ24A) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

USB.SchDoc

DRCYAI commented

2026-09-11 21:22:37 +00:00

[🚨 Error] Component U11B, pins 37, 38, 42, 43: The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together.

Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) (from schematic)
Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) (from schematic)
Pin 37 (DHSDP) is the USB high speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18)
Pin 38 (DHSDM) is the USB high speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18)
Pin 42 (DFSDP) is the USB full speed data positive pin (from datasheet ATSAM3X8EA-AU, page 18)
Pin 43 (DFSDM) is the USB full speed data negative pin (from datasheet ATSAM3X8EA-AU, page 18)
The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation (from datasheet ATSAM3X8EA-AU, page 4)
DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation (reasoning)
USB operates in either high-speed or full-speed mode, not both simultaneously (reasoning)
Connecting high-speed and full-speed USB pins together is not a valid USB configuration (reasoning)
The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected (reasoning)

3 affected locations — one shared root cause

Component U11B, pins `37, 38, 42, 43`
Component R48, pins `1, 2`
Component R42, pins `1, 2`

Per-location differences

Component R48, pins `1, 2`: R48 is part of an incorrect connection between USB high-speed pin DHSDP (pin 37) and full-speed pin DFSDP (pin 42) of U11B.

R48 pin 2 connects to UMCU_P which connects to U11B pin 37 (DHSDP) (from schematic)
R48 pin 1 connects to NetR48_1 which connects to U11B pin 42 (DFSDP) (from schematic)
R48 is a 24Ω resistor (from schematic)
This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)

Component R42, pins `1, 2`: R42 is part of an incorrect connection between USB high-speed pin DHSDM (pin 38) and full-speed pin DFSDM (pin 43) of U11B.

R42 pin 2 connects to UMCU_N which connects to U11B pin 38 (DHSDM) (from schematic)
R42 pin 1 connects to NetR42_1 which connects to U11B pin 43 (DFSDM) (from schematic)
R42 is a 24Ω resistor (from schematic)
This resistor creates an incorrect connection between USB high-speed and full-speed pins (reasoning)

Datasheets: 📄 R48 📄 U11B

_{Replace a datasheet: 📤 R42 📤 R48 📤 U11B}

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[🚨 Error] **Component [`U11B`](<https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=25.81,15.68,42.39,38.47&zoom=1>), pins `37, 38, 42, 43`: The USB high-speed pins (DHSDP/DHSDM) and full-speed pins (DFSDP/DFSDM) are incorrectly connected together through 24Ω series resistors. These pin sets are for different USB operating modes and should not be connected together.** !thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Altium-Demo-Project:9ecce85a87495918c7559a01f7af99f93647b863...5cbb246b569c3454c2eefb279060d5eece326d28" pr="5" diff-visibility="full" variant="default" view-coords="34.89,19.21,42.39,31.41" aspect-ratio="1.29" } - Pin 37 (DHSDP) connects to UMCU_P, which connects through R48 (24Ω) to NetR48_1, which connects to pin 42 (DFSDP) *(from schematic)* - Pin 38 (DHSDM) connects to UMCU_N, which connects through R42 (24Ω) to NetR42_1, which connects to pin 43 (DFSDM) *(from schematic)* - Pin 37 (DHSDP) is the USB high speed data positive pin *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Pin 38 (DHSDM) is the USB high speed data negative pin *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Pin 42 (DFSDP) is the USB full speed data positive pin *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - Pin 43 (DFSDM) is the USB full speed data negative pin *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=18>), page 18)* - The SAM3X has USB 2.0 Device/Mini Host with embedded transceiver supporting 480 Mbps high-speed operation *(from datasheet [ATSAM3X8EA-AU](<https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=4>), page 4)* - DHSDP/DHSDM pins are for high-speed USB operation while DFSDP/DFSDM pins are for full-speed USB operation *(reasoning)* - USB operates in either high-speed or full-speed mode, not both simultaneously *(reasoning)* - Connecting high-speed and full-speed USB pins together is not a valid USB configuration *(reasoning)* - The designer should use either DHSDP/DHSDM for high-speed operation OR DFSDP/DFSDM for full-speed operation, with the unused pair left unconnected *(reasoning)* <details> <summary>3 affected locations — one shared root cause</summary> <ul> <li>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=25.81,15.68,42.39,38.47&zoom=1"><code>U11B</code></a>, pins `37, 38, 42, 43`</li> <li>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=39.44,20.39,48.75,27.89&zoom=1"><code>R48</code></a>, pins `1, 2`</li> <li>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=39.44,23.91,48.75,31.41&zoom=1"><code>R42</code></a>, pins `1, 2`</li> </ul> #### Per-location differences <details> <summary>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=39.44,20.39,48.75,27.89&zoom=1"><code>R48</code></a>, pins `1, 2`: R48 is part of an incorrect connection between USB high-speed pin DHSDP (pin 37) and full-speed pin DFSDP (pin 42) of U11B.</summary> - R48 pin 2 connects to UMCU_P which connects to U11B pin 37 (DHSDP) *(from schematic)* - R48 pin 1 connects to NetR48_1 which connects to U11B pin 42 (DFSDP) *(from schematic)* - R48 is a 24Ω resistor *(from schematic)* - This resistor creates an incorrect connection between USB high-speed and full-speed pins *(reasoning)* </details> <details> <summary>Component <a href="https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/src/5cbb246b569c3454c2eefb279060d5eece326d28/USB.SchDoc?view-coordinates=39.44,23.91,48.75,31.41&zoom=1"><code>R42</code></a>, pins `1, 2`: R42 is part of an incorrect connection between USB high-speed pin DHSDM (pin 38) and full-speed pin DFSDM (pin 43) of U11B.</summary> - R42 pin 2 connects to UMCU_N which connects to U11B pin 38 (DHSDM) *(from schematic)* - R42 pin 1 connects to NetR42_1 which connects to U11B pin 43 (DFSDM) *(from schematic)* - R42 is a 24Ω resistor *(from schematic)* - This resistor creates an incorrect connection between USB high-speed and full-speed pins *(reasoning)* </details> </details> Datasheets: [📄 R48](https://www.mouser.com/catalog/specsheets/YAGEO_PYu_RC_Group_51_RoHS_L_12.pdf) [📄 U11B](https://www.mouser.com/datasheet/3/282/1/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) Replace a datasheet: [📤 R42](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) [📤 R48](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) [📤 U11B](https://hub.allspice.io/AllSpice-Demos/Altium-Demo-Project/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) 💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.