AllSpice-Demos/Altium-Demo
AllSpice-Demos/Altium-Demo
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Add ESD Protection to Endstops #2

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AllSpiceAlice wants to merge 8 commits from develop into main
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merge into: AllSpice-Demos:main
Conversation 30 Commits 8 Changes 5 +17 -4
AllSpiceAlice commented 2024-07-28 22:47:58 +00:00
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Resolved Issues

  • Closes #5 Remove debug header to prevent misconnection

  • Closes #4 Replace LED with Part from Approved Parts List

  • Closes #3 Fix 5V Power Trace width

  • Add protection to endstops

  • Add LEDs to Fans

Description

V3 adds more protection to external cables/sensors and improves data transmission.
Resolves manufacturing and customer issues from V2.

EndStops.SchDoc

  • Add protection diode to endstops
  • Remove e-stop Endstop channel

Connectors.SchDoc

  • Move mounting holes and fiducials from Connectors to Power

Fans.SchDoc

  • Add LEDs to Fans
  • Fix Fan input protection

Microcontroller.SchDoc

  • Add protection diodes to MicroSD
  • Update bypass caps
  • Add inline resistors to SERCOM
  • Add yellow LED to PC1

Motor.SchDoc

  • Fix MOSI/MISO swap
  • Add protection circuitry to Motor

Power.SchDoc

  • Add fuses to VBED, VPWR_IN
  • Update +5V DCDC Regulator compensation and enable

Thermisters.SchDoc

  • Add 3rd thermister channel

Thermocouples.SchDoc

  • Fix MOSI/MISO Swap
  • Remove _DRDY and _FAULT

USB.SchDoc

  • Add more filters to USB
  • Fix oscillator caps
  • Change isoisolator bias

Design Review Checklist

Process
  • Commits in correct branch @gautam at 3/19/25 @ 14:00
  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained
System
  • Power
    • Sufficient power supplied from upstream source
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • I/Os are specified
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review
Components
  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power
Schematics
  • Document
    • Dot on each connection
    • No four-point connections
    • Title block completed for each sheet
    • All components have reference designators and values
    • Multi-part components don't have unplaced symbols
    • Page title present and consistent on all pages if not in title block
    • Symbols identify open collector/drain pins and internal pulled up/down pins
    • Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
    • Components follow preferred reference designator pattern
  • External I/O
    • Filtered for EMI
    • Protected against electrostatic discharge (ESD)
    • Unused inputs terminated
  • Microcontrollers / ICs
    • Predictable or controlled power-up state
      • Reset filtered
    • Sufficient bypass capacitance
    • Oscillators checked for reliable startup
    • Pullups on open-collector pins
    • Logic-low and logic-high voltage levels checked
    • No-connect pins labeled NC
    • Clock lines with series/parallel termination
    • Check for latchup & off-voltage
    • Check datasheet errata/apnotes
  • Busses
    • UART/USART TX->RX and RX<-TX
    • I2C pullups per capacitance
    • Bus timing checked
  • Analog
    • Adequate power rails
    • Amplifier stability
    • Rate-of-rise/fall checked
  • General
    • Bulk capacitance
    • Polarized components
    • Reverse voltage on electrolytics
    • Cap derating for MTBF
    • LDO capacitance
    • Comparator slew/timing
    • Opamp common mode input range
    • Custom part pin verification
    • BJT base-emitter reverse current
    • Consistent power net names
    • Debug features included
PCB

  • Manufacturing

    • Requirements on fab layer
      • Plating: material + thickness
      • Stack-up, trace/space, hole size
      • PCB/silkscreen color
      • Impedance, blind/buried vias
      • Panelization, routing, drill table
      • Specs > tolerance
    • Power plane spacing minimized
    • Proper solder paste & fiducials

  • Footprints

    • Pin 1 marked
    • Polarity marked (diodes, LEDs, caps)
    • Dimensions vs datasheet
    • Thermal pads present

  • Placement

    • Accessible jumpers, debug
    • Correct resistor placement
    • SMPS loop minimized
    • Cap & driver proximity
    • SMT top / THT bottom

  • Clearance

    • Keep-outs honored
    • Clearance per voltage rating
    • Avoid edge components

  • Mechanical

    • CAD uploaded
    • Connector + harness clearance
    • Isolated mounting holes
    • Defined outline/enclosure
    • Rounded internal corners

  • Electrical

    • All nets routed
    • Analog/digital common joined once
    • ERC passes
    • Isolation barriers OK

  • Signal Integrity

    • Ground plane gaps minimized
    • No gaps under high-speed signals
    • No stubs, impedance matched pairs
    • Terminated lines
    • Short crystal paths
    • Guard ring
    • Avoid under/noisy components
    • RF via fencing < 1/20 λ
    • Shield can option

  • Copper Pour

    • All planes poured
    • No high-impedance paths
    • No pour between IC pins

  • Traces

    • Oblique trace angles
    • Correct width/via size
    • No pin-to-pin shortcuts
    • Smooth bends for impedance

  • Thermal

    • Separate heat sources
    • Thermal vias in pads

  • Testing

    • Critical test points added
    • Ground near analog test points

  • Silk screen

    • Rev, date, serial space
    • No silk on pads/vias
    • 2-direction readable text
    • Legible font
    • Connector pinouts
    • Fuse specs
    • Functional groups
    • Test points, LEDs, buttons, jumpers labeled
## Resolved Issues - Closes #5 Remove debug header to prevent misconnection - Closes #4 Replace LED with Part from Approved Parts List - Closes #3 Fix 5V Power Trace width - Add protection to endstops - Add LEDs to Fans ## Description V3 adds more protection to external cables/sensors and improves data transmission. Resolves manufacturing and customer issues from V2. ### EndStops.SchDoc - Add protection diode to endstops - Remove e-stop Endstop channel ### Connectors.SchDoc - Move mounting holes and fiducials from Connectors to Power ### Fans.SchDoc - Add LEDs to Fans - Fix Fan input protection ### Microcontroller.SchDoc - Add protection diodes to MicroSD - Update bypass caps - Add inline resistors to SERCOM - Add yellow LED to PC1 ### Motor.SchDoc - Fix MOSI/MISO swap - Add protection circuitry to Motor ### Power.SchDoc - Add fuses to VBED, VPWR_IN - Update +5V DCDC Regulator compensation and enable ### Thermisters.SchDoc - Add 3rd thermister channel ### Thermocouples.SchDoc - Fix MOSI/MISO Swap - Remove _DRDY and _FAULT ### USB.SchDoc - Add more filters to USB - Fix oscillator caps - Change isoisolator bias --- ## Design Review Checklist <details> <summary>Process</summary> - [x] Commits in correct branch @gautam at 3/19/25 @ 14:00 - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [x] Power - [ ] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [ ] Voltage - [ ] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [x] Components follow preferred reference designator pattern - [x] External I/O - [x] Filtered for EMI - [x] Protected against electrostatic discharge (ESD) - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Predictable or controlled power-up state - [x] Reset filtered - [x] Sufficient bypass capacitance - [x] Oscillators checked for reliable startup - [x] Pullups on open-collector pins - [x] Logic-low and logic-high voltage levels checked - [x] No-connect pins labeled NC - [x] Clock lines with series/parallel termination - [x] Check for latchup & off-voltage - [x] Check datasheet errata/apnotes - [ ] Busses - [ ] UART/USART TX->RX and RX<-TX - [ ] I2C pullups [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Bus timing checked - [x] Analog - [x] Adequate power rails - [x] Amplifier stability - [x] Rate-of-rise/fall checked - [ ] General - [ ] Bulk capacitance - [ ] Polarized components - [ ] Reverse voltage on electrolytics - [ ] Cap derating for MTBF - [x] LDO capacitance - [ ] Comparator slew/timing - [ ] Opamp common mode input range - [ ] Custom part pin verification - [ ] BJT base-emitter reverse current - [ ] Consistent power net names - [ ] Debug features included </details> <details> <summary>PCB</summary> - [x] Manufacturing - [x] Requirements on `fab` layer - [x] Plating: material + thickness - [x] Stack-up, trace/space, hole size - [x] PCB/silkscreen color - [x] Impedance, blind/buried vias - [x] Panelization, routing, drill table - [x] Specs > tolerance - [x] Power plane spacing minimized - [x] Proper solder paste & fiducials - [x] Footprints - [x] Pin 1 marked - [x] Polarity marked (diodes, LEDs, caps) - [x] Dimensions vs datasheet - [x] Thermal pads present - [x] Placement - [x] Accessible jumpers, debug - [x] Correct resistor placement - [x] SMPS loop minimized - [x] Cap & driver proximity - [x] SMT top / THT bottom - [x] Clearance - [x] Keep-outs honored - [x] Clearance per voltage rating - [x] Avoid edge components - [x] Mechanical - [x] CAD uploaded - [x] Connector + harness clearance - [x] Isolated mounting holes - [x] Defined outline/enclosure - [x] Rounded internal corners - [x] Electrical - [x] All nets routed - [x] Analog/digital common joined once - [x] ERC passes - [x] Isolation barriers OK - [x] Signal Integrity - [x] Ground plane gaps minimized - [x] No gaps under high-speed signals - [x] No stubs, impedance matched pairs - [x] Terminated lines - [x] Short crystal paths - [x] Guard ring - [x] Avoid under/noisy components - [x] RF via fencing < 1/20 λ - [x] Shield can option - [x] Copper Pour - [x] All planes poured - [x] No high-impedance paths - [x] No pour between IC pins - [x] Traces - [x] Oblique trace angles - [x] Correct width/via size - [x] No pin-to-pin shortcuts - [x] Smooth bends for impedance - [x] Thermal - [x] Separate heat sources - [x] Thermal vias in pads - [x] Testing - [x] Critical test points added - [x] Ground near analog test points - [ ] Silk screen - [x] Rev, date, serial space - [x] No silk on pads/vias - [ ] 2-direction readable text - [ ] Legible font - [ ] Connector pinouts - [ ] Fuse specs - [ ] Functional groups - [ ] Test points, LEDs, buttons, jumpers labeled </details> <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
AllSpiceAlice added 1 commit 2024-07-28 22:47:58 +00:00
AllSpiceAlice requested review from RevaReviewa 2024-07-28 22:49:36 +00:00
AllSpiceAlice requested review from MikaChanical 2024-07-28 22:49:36 +00:00
AllSpiceAlice requested review from PavelInPurchasing 2024-07-28 22:49:37 +00:00
AllSpiceAlice requested review from Allie 2024-07-28 22:49:37 +00:00
AllSpiceAlice requested review from marcus 2024-07-28 22:49:37 +00:00
AllSpiceAlice requested review from brendan 2024-07-28 22:49:37 +00:00
AllSpiceAlice requested review from gautam 2024-07-28 22:49:37 +00:00
AllSpiceAlice added the
priority/4 - high
documentation
dfm
firmware
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 labels 2024-07-28 22:49:56 +00:00
AllSpiceAlice added 1 commit 2024-07-28 22:51:17 +00:00
AllSpiceAlice added 1 commit 2024-07-28 22:51:52 +00:00
AllSpiceAlice added 1 commit 2024-07-28 22:53:03 +00:00
AllSpiceAlice added 1 commit 2024-07-28 23:02:29 +00:00
RevaReviewa commented 2024-07-28 23:12:21 +00:00
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@daniel, can we remove the E-Stop channel? It's not hooked up to an interrupt and can't actually es-stop.

@daniel, can we remove the E-Stop channel? It's not hooked up to an interrupt and can't actually es-stop.
daniel-allspice reviewed 2024-07-28 23:20:05 +00:00
EndStops.SchDoc
daniel-allspice commented 2024-07-28 23:20:05 +00:00
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@RevaReviewa, the extra endstop channel has been removed. Thank you!

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="4.8,40.4,49.6,60.8" aspect-ratio="1.286" } @RevaReviewa, the extra endstop channel has been removed. Thank you!
❤️ 1
brendan marked this conversation as resolved
PavelInPurchasing reviewed 2024-07-28 23:23:42 +00:00
Fans.SchDoc
PavelInPurchasing commented 2024-07-28 23:23:42 +00:00
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@daniel, can you replace the LED with something from the approved parts list? We're about to remove this LED because it is end-of-life EOL.

!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="21.3,8.6,37.4,29.5" aspect-ratio="1.286" } @daniel, can you replace the LED with something from the approved parts list? We're about to remove this LED because it is end-of-life EOL.
👍 1
daniel-allspice commented 2024-07-28 23:25:04 +00:00
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@PavelInPurchasing, I've switched to a standard APL LED. Thank you! 🙏

@PavelInPurchasing, I've switched to a standard APL LED. Thank you! 🙏
brendan marked this conversation as resolved
RevaReviewa reviewed 2024-07-28 23:27:03 +00:00
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RevaReviewa commented 2024-07-28 23:27:03 +00:00
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@daniel, why did we remove the debug header?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="17.9,3.2,33.8,21.9" aspect-ratio="1.347" } @daniel, why did we remove the debug header?
daniel-allspice commented 2024-07-28 23:28:05 +00:00
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It's the same connector as one of the fan drivers, so technicians and end-users were accidentally pluging in debug equipment into the fan drivers and vice-versa. This was to make it accident-proof.

It's the same connector as one of the fan drivers, so technicians and end-users were accidentally pluging in debug equipment into the fan drivers and vice-versa. This was to make it accident-proof.
RevaReviewa commented 2024-07-28 23:28:39 +00:00
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That makes sense, thank you.

That makes sense, thank you.
brendan marked this conversation as resolved
daniel-allspice reviewed 2024-07-28 23:30:24 +00:00
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daniel-allspice commented 2024-07-28 23:30:24 +00:00
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@AllSpiceAlice , can you have someone on your team review the new 5V power trace thickness?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="62.1,11.7,82.9,34.8" aspect-ratio="1.347" } @AllSpiceAlice , can you have someone on your team review the new 5V power trace thickness?
AllSpiceAlice commented 2024-07-28 23:31:52 +00:00
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Thank you @daniel, this looks great. All the changes were so quick. Thank you for the expedited layout changes! 🚀

Thank you @daniel, this looks great. All the changes were so quick. Thank you for the expedited layout changes! 🚀
brendan marked this conversation as resolved
MikaChanical reviewed 2024-07-28 23:42:06 +00:00
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MikaChanical commented 2024-07-28 23:42:06 +00:00
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@AllSpiceAlice, new mounting holes are perfect. 🥇

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="53.0,0.4,64.8,15.4" aspect-ratio="1.347" } @AllSpiceAlice, new mounting holes are perfect. 🥇
allspice-hermes commented 2024-10-04 17:42:15 +00:00
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Can we make sure that they have the right measures? I thought they were smaller @AllSpiceAlice @MikaChanical

Can we make sure that they have the right measures? I thought they were smaller @AllSpiceAlice @MikaChanical
allspice-hermes marked this conversation as resolved
brendan reviewed 2024-08-15 15:39:24 +00:00
brendan reviewed 2024-08-28 13:56:08 +00:00
brendan added this to the V4 Release milestone 2024-08-28 14:08:50 +00:00
gautam reviewed 2024-09-05 15:39:46 +00:00
EndStops.SchDoc
gautam commented 2024-09-05 15:39:46 +00:00
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@daniel What's up with this?

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="51.6,15.4,93.9,37.3" aspect-ratio="1.286" } @daniel What's up with this?
AllSpiceAlice commented 2024-09-05 21:19:11 +00:00
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We wanted to add ESD protection. The users kept frying the boards when connecting cables.

We wanted to add ESD protection. The users kept frying the boards when connecting cables.
AllSpiceAlice reviewed 2024-09-11 17:30:34 +00:00
Fans.SchDoc
AllSpiceAlice commented 2024-09-11 17:30:34 +00:00
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@MikaChanical , is this correct

!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="63.0,27.8,77.1,37.7" aspect-ratio="1.286" } @MikaChanical , is this correct
allspice-hermes changed title from Add ESD Protection to Endstops to WIP: Add ESD Protection to Endstops 2024-09-13 00:05:31 +00:00
allspice-hermes changed title from WIP: Add ESD Protection to Endstops to Add ESD Protection to Endstops 2024-09-13 00:05:44 +00:00
brendan reviewed 2024-10-09 22:25:26 +00:00
AllSpiceAlice reviewed 2024-11-26 18:42:21 +00:00
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AllSpiceAlice commented 2024-11-26 18:42:21 +00:00
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@daniel why was this debug header removed

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="18.0,3.1,32.0,13.0" aspect-ratio="1.347" } @daniel why was this debug header removed
brendan marked this conversation as resolved
AllSpiceAlice reviewed 2024-12-05 20:07:17 +00:00
EndStops.SchDoc
AllSpiceAlice commented 2024-12-05 20:07:17 +00:00
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@daniel-allspice , why did we remove this channel?

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="4.4,37.9,50.7,62.0" aspect-ratio="1.286" } @daniel-allspice , why did we remove this channel?
gautam reviewed 2025-01-10 18:30:03 +00:00
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gautam commented 2025-01-10 18:30:03 +00:00
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Can you double check the trace here, @daniel-allspice?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="60.6,12.2,86.0,31.4" aspect-ratio="1.347" } Can you double check the trace here, @daniel-allspice?
AllSpiceAlice reviewed 2025-01-17 16:21:09 +00:00
EndStops.SchDoc
AllSpiceAlice commented 2025-01-17 16:21:09 +00:00
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@AllSpiceAlice , can you check this part number ESD9X3.3ST5G

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="46.4,26.0,96.5,54.1" aspect-ratio="1.286" } @AllSpiceAlice , can you check this part number ESD9X3.3ST5G
gautam reviewed 2025-01-23 23:53:21 +00:00
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gautam commented 2025-01-23 23:53:18 +00:00
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@marcus , could you verify this please?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="37,38" diff-visibility="full" variant="default" view-coords="18.6,1.5,69.9,12.8" aspect-ratio="1.347" } @marcus , could you verify this please?
Ghost approved these changes 2025-04-09 17:55:17 +00:00
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Ghost commented 2025-04-09 17:54:57 +00:00
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@daniel are we replacing this?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="69.5,20.7,73.3,26.0" aspect-ratio="1.344" } @daniel are we replacing this?
AllSpiceAlice reviewed 2025-04-11 19:16:42 +00:00
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AllSpiceAlice commented 2025-04-11 19:16:42 +00:00
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@allspicealice Can you verify the new mounting hole position?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="92.4,92.0,99.7,99.1" aspect-ratio="1.347" } @allspicealice Can you verify the new mounting hole position?
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allspice-thomas reviewed 2025-04-23 10:37:47 +00:00
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allspice-thomas commented 2025-04-23 10:37:47 +00:00
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Is this ok? @allspice-thomas

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="59.6,14.0,84.9,30.8" aspect-ratio="1.347" } Is this ok? @allspice-thomas
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Ghost reviewed 2025-04-23 18:15:39 +00:00
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Ghost commented 2025-04-23 18:15:39 +00:00
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@daniel-allspice whats the reference design for this?

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="6.2,59.7,46.7,78.7" aspect-ratio="1.285" } @daniel-allspice whats the reference design for this?
nico reviewed 2025-05-06 14:37:11 +00:00
gautam added 2 commits 2025-05-13 00:49:50 +00:00
Update generate-bom to 0.8
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Merge pull request 'gautam-patch-1' (#56) from gautam-patch-1 into develop
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fd1861e074 
Reviewed-on: #56
AllSpiceAlice reviewed 2025-05-13 16:39:27 +00:00
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AllSpiceAlice commented 2025-05-13 16:39:27 +00:00
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@AllSpiceAlice , please double check the pitch on this footprint. 😸

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...fd1861e0747666a30bf72889c64facfa72fe36e4" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="35.1,45.4,39.5,50.1" aspect-ratio="1.347" } @AllSpiceAlice , please double check the pitch on this footprint. 😸
allspice-thomas requested review from allspice-thomas 2025-06-04 22:35:12 +00:00
AllSpiceAlice pinned this 2025-06-05 15:34:22 +00:00
gautam reviewed 2025-06-09 16:28:10 +00:00
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gautam commented 2025-06-09 16:28:10 +00:00
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@daniel-allspice Please verify before next release.

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...fd1861e0747666a30bf72889c64facfa72fe36e4" pr="2" diff-visibility="full" variant="default" view-coords="58.7,15.4,85.2,37.1" aspect-ratio="1.286" } @daniel-allspice Please verify before next release.
AllSpiceAlice unpinned this 2025-06-11 02:59:33 +00:00
AllSpiceAlice added 1 commit 2025-06-11 03:02:41 +00:00
Add convert BOM to Excel action
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nick reviewed 2025-06-13 18:01:20 +00:00
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nick commented 2025-06-13 18:01:19 +00:00
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@daniel-allspice are these vias large enough for the current flow.

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...0bc943ff507ffbde40e78c0345bdade66f500f9f" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="63.1,16.6,66.9,21.0" aspect-ratio="1.347" } @daniel-allspice are these vias large enough for the current flow.
nick removed review request for marcus 2025-06-13 18:04:34 +00:00
nick pinned this 2025-06-13 18:05:46 +00:00
nick unpinned this 2025-06-13 18:06:32 +00:00
AllSpiceAlice pinned this 2025-06-13 22:36:13 +00:00
gautam reviewed 2025-07-09 19:10:23 +00:00
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gautam commented 2025-07-09 19:10:23 +00:00
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@daniel-allspice Did we really mean to axe this?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...0bc943ff507ffbde40e78c0345bdade66f500f9f" pr="2" layers="33" diff-visibility="full" variant="default" view-coords="18.5,2.9,33.2,16.4" aspect-ratio="1.347" } @daniel-allspice Did we really mean to axe this?
gautam reviewed 2025-07-15 18:27:14 +00:00
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gautam commented 2025-07-15 18:27:14 +00:00
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@AllSpiceAlice Hey does this really need a 10mil trace?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...0bc943ff507ffbde40e78c0345bdade66f500f9f" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="62.1,14.4,86.5,32.2" aspect-ratio="1.347" } @AllSpiceAlice Hey does this really need a 10mil trace?
allspice-thomas unpinned this 2025-07-18 17:21:07 +00:00
gautam reviewed 2025-07-23 18:22:29 +00:00
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gautam commented 2025-07-23 18:22:29 +00:00
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@daniel-allspice Please verify this diode availability.

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...0bc943ff507ffbde40e78c0345bdade66f500f9f" pr="2" diff-visibility="full" variant="default" view-coords="68.2,19.8,84.0,35.2" aspect-ratio="1.286" } @daniel-allspice Please verify this diode availability.
gautam reviewed 2025-08-01 15:58:38 +00:00
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gautam commented 2025-08-01 15:58:38 +00:00
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@allspice-thomas Hey Thomas, did we mean to fully get rid of this?

!thumbnail[](EndStops.SchDoc){ view-coords="5.3,43.0,48.1,58.9" variant="default" aspect-ratio="1.286" diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...0bc943ff507ffbde40e78c0345bdade66f500f9f" pr="2" diff-visibility="full" } @allspice-thomas Hey Thomas, did we mean to fully get rid of this?
gautam reviewed 2025-08-20 02:19:23 +00:00
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gautam commented 2025-08-20 02:19:22 +00:00
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@nick Can you cross-check with the mechanical team to see if this mounting hole change will be okay?

!thumbnail[](Archimajor.PcbDoc){ view-coords="90.9,88.8,100.2,98.9" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" variant="default" aspect-ratio="1.347" diff="AllSpice-Demos/Altium-Demo:48b12293a9d0ff06769d46a5b4b2429278233dc9...0bc943ff507ffbde40e78c0345bdade66f500f9f" pr="2" diff-visibility="full" } @nick Can you cross-check with the mechanical team to see if this mounting hole change will be okay?
allspice-thomas approved these changes 2025-10-17 18:29:55 +00:00
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Look all good

Look all good
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