AllSpice-Demos/Altium-Demo

Fork 1

Add ESD Protection to Endstops #2

Open

AllSpiceAlice wants to merge 5 commits from develop into main

AllSpiceAlice commented

2024-07-28 22:47:58 +00:00

Owner

Resolved Issues

Closes #5 Remove debug header to prevent misconnection
Closes #4 Replace LED with Part from Approved Parts List
Closes #3 Fix 5V Power Trace width
Add protection to endstops
Add LEDs to Fans

Description

V3 adds more protection to external cables/sensors and improves data transmission

Resolves manufacturing and customer issues from V2

EndStops.SchDoc

Add protection diode to endstops
Remove e-stop Endstop channel

Connectors.SchDoc

Move mounting holes and fiducials from Connectors to Power

Fans.SchDoc

Add LEDs to Fans
Fix Fan input protection

Microcontroller.SchDoc

Add protection diodes to MicroSD
Update bypass caps
Add inline resistors to SERCOM
Add yellow LED to PC1

Motor.SchDoc

Fix MOSI/MISO swap
Add protection circuitry to Motor

Power.SchDoc

Add fuses to VBED, VPWR_IN
Update +5V DCDC Regulator compensation and enable

Thermisters.SchDoc

Add 3rd thermister channel

Thermocouples.SchDoc

Fix MOSI/MISO Swap
Remove _DRDY and _FAULT

USB.SchDoc

Add more filters to USB
Fix oscillator caps
Change isoisolator bias

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
- Components follow preferred reference designator pattern
External I/O
- Filtered for EMI
- Protected against electrostatic discharge (ESD)
- Unused inputs terminated
Microcontrollers / ICs
- Predictable or controlled power-up state
  - Reset filtered
- Sufficient bypass capacitance
- Oscillators checked for reliable startup
- Pullups on open-collector pins
- Logic-low and logic-high voltage levels checked
- No-connect pins labeled NC
- Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
- Check for input voltages applied with power off and CMOS latchup possibilities
- Check the data sheet errata and apnotes for weird IC behaviors
Busses
- UART/USART TX->RX and RX<-TX
- I2C SDA and SCL pullup with appropriate value per capacitance
- Setup, hold, access times for data and address busses
Analog
- Sufficient power rails for analog circuits
- Amplifiers checked for stability
- Consider signal rate-of-rise and fall for noise radiation
General
- Sufficient bulk capacitance calculated
- Polarized components checked
- Electrolytic/tantalum capacitors checked for no reverse voltage
- Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
- Sufficient capacitance on low dropout voltage regulators
- Sufficient time delays and slew rates for comparators
- Sufficient common mode input voltage rating on opamps
- Check pin numbers of all custom-generated parts
- Check reverse base-emitter current/voltage on bipolar transistors
- Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
- Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default

PCB

Manufacturing
- PCB manufacturing requirements noted on fab layer
  - Plating specified
    - Plating material
    - Plating thickness
  - Layer stack-up specified
  - Minimum trace/space specified
  - Minimum hole size specified
  - PCB color specified
  - Silkscreen color specified
  - Controlled impedance specified
  - Blind or buried vias specified
  - Panelization specified
    - External routing specified (ex. v-groove vs route)
  - Drill table generated
  - All specifications exceed manufacturing tolerance
- Space between power planes minimized
- Solder paste openings proper size
- Fiducials placed if necessary
Footprints
- Pin 1 marked in a consistent manner
- Component polarity marked
  - Diodes, LEDs
  - Electrolytic, tantalum capacitors
  - Keyed components like connectors
- Footprint dimensions cross-checked with datasheet recommendation
- Sufficient thermal pads on high-power components or nets
Placement
- Jumpers accessible
- Debug connectors accessible
- Filter resistors closer to source
- Termination resistors close to target
- Small loop path on switch-mode power supplies
- Bypass capacitors close to ICs
- Bypass capacitors close to connectors
- Drivers / receivers close to connectors
- SMT components on top side, through-hole components on bottom side if possible
Clearance
- Keep-out areas honored
  - Around mounting holes
  - For programming tools
  - For assembly tools (wrenches, screwdrivers etc.)
  - For connectors
- Trace-to-trace clearance based upon voltage rating
- Component size based upon voltage rating
- Keep components away from board edge
Mechanical
- CAD file uploaded
- Clearance above connectors
- Clearance below through-hole components
- Enough space for the minimum bending radius of the wire harness
- Mounting holes electrically isolated if necessary
  - Mounting holes have via stitching
- Hole diameters leave margin for plating
- Board outline defined
- Mechanical enclosure defined
- Internal corners are rounded and can be milled
Electrical
- All traces are routed
- Analog and digital commons joined at only one point
- ERC passes
- Isolation barriers are large enough
Signal integrity
- Gaps in ground planes checked and minimized
- High-speed signals avoid gaps in ground planes
- Stubs minimized for high-speed signals
- Differential pair spacing based upon impedance matching
- Transmission lines terminated with an appropriate impedance
- Crystal connections kept short
- Guard ring around crystals
- Traces avoided under sensitive components
- Traces avoided under noisy components
- Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
- Option for a shielding can over sensitive circuitry e.g. RF?
Copper pour
- All planes have been poured
- Planes and pours checked for high-impedance paths
- No pour between adjacent pins on ICs
Traces
- Trace-pad connections sufficiently obtuse (angle 90 deg or more)
- Trace widths sufficient for the current draw and max heating
- No connections between adjacent pins on ICs
- Vias for internal power traces sufficiently large
- Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
Thermal
- Temperature sensitive components placed away from hot components
- Thermal vias in thermal pads
Testing
- Test points on PCBs for critical circuits, hard to reach nets
- Ground connection points close to analog test points
Silk screen
- Notes and documentation
  - Updated revision number
  - Updated date
  - Blank space designated for a serial / assembly number
- No silk screen over pads / vias
- Text is readable from at most two directions
- Silk screen size / font will legible after printing
- Connector pin-outs labeled
- Fuse size and type marked on PCB
- Functional groups marked
- Functionality labeled
  - Test points
  - LEDs
  - Buttons
  - Connectors/terminals
  - Jumpers/fuses

## Resolved Issues - Closes #5 Remove debug header to prevent misconnection - Closes #4 Replace LED with Part from Approved Parts List - Closes #3 Fix 5V Power Trace width - Add protection to endstops - Add LEDs to Fans ## Description V3 adds more protection to external cables/sensors and improves data transmission Resolves manufacturing and customer issues from V2 ### EndStops.SchDoc - Add protection diode to endstops - Remove e-stop Endstop channel ### Connectors.SchDoc - Move mounting holes and fiducials from Connectors to Power ### Fans.SchDoc - Add LEDs to Fans - Fix Fan input protection ### Microcontroller.SchDoc - Add protection diodes to MicroSD - Update bypass caps - Add inline resistors to SERCOM - Add yellow LED to PC1 ### Motor.SchDoc - Fix MOSI/MISO swap - Add protection circuitry to Motor ### Power.SchDoc - Add fuses to VBED, VPWR_IN - Update +5V DCDC Regulator compensation and enable ### Thermisters.SchDoc - Add 3rd thermister channel ### Thermocouples.SchDoc - Fix MOSI/MISO Swap - Remove _DRDY and _FAULT ### USB.SchDoc - Add more filters to USB - Fix oscillator caps - Change isoisolator bias ## Design Review Checklist ### Process - [x] Commits in correct branch - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained ### System - [x] Power - [x] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review ### Components - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power ### Schematics - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [x] Components follow preferred reference designator pattern  - [x] External I/O - [x] Filtered for EMI - [x] Protected against electrostatic discharge (ESD) - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Predictable or controlled power-up state - [x] Reset filtered - [x] Sufficient bypass capacitance - [x] Oscillators checked for reliable startup - [x] Pullups on open-collector pins - [x] Logic-low and logic-high voltage levels checked - [x] No-connect pins labeled NC - [x] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination - [x] Check for input voltages applied with power off and CMOS latchup possibilities - [x] Check the data sheet errata and apnotes for weird IC behaviors - [ ] Busses - [ ] UART/USART TX->RX and RX<-TX - [ ] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Setup, hold, access times for data and address busses - [x] Analog - [x] Sufficient power rails for analog circuits - [x] Amplifiers checked for stability - [x] Consider signal rate-of-rise and fall for noise radiation - [ ] General - [ ] Sufficient bulk capacitance calculated - [ ] Polarized components checked - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF - [x] Sufficient capacitance on low dropout voltage regulators - [ ] Sufficient time delays and slew rates for comparators - [ ] Sufficient common mode input voltage rating on opamps - [ ] Check pin numbers of all custom-generated parts - [ ] Check reverse base-emitter current/voltage on bipolar transistors - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default ### PCB - [x] Manufacturing - [x] PCB manufacturing requirements noted on `fab` layer - [x] Plating specified - [x] Plating material - [x] Plating thickness - [x] Layer stack-up specified - [x] Minimum trace/space specified - [x] Minimum hole size specified - [x] PCB color specified - [x] Silkscreen color specified - [x] Controlled impedance specified - [x] Blind or buried vias specified - [x] Panelization specified - [x] External routing specified (ex. v-groove vs route) - [x] Drill table generated - [x] All specifications exceed manufacturing tolerance - [x] Space between power planes minimized - [x] Solder paste openings proper size - [x] Fiducials placed if necessary - [x] Footprints - [x] Pin 1 marked in a consistent manner - [x] Component polarity marked - [x] Diodes, LEDs - [x] Electrolytic, tantalum capacitors - [x] Keyed components like connectors - [x] Footprint dimensions cross-checked with datasheet recommendation - [x] Sufficient thermal pads on high-power components or nets - [x] Placement - [x] Jumpers accessible - [x] Debug connectors accessible - [x] Filter resistors closer to source - [x] Termination resistors close to target - [x] Small loop path on switch-mode power supplies - [x] Bypass capacitors close to ICs - [x] Bypass capacitors close to connectors - [x] Drivers / receivers close to connectors - [x] SMT components on top side, through-hole components on bottom side if possible - [x] Clearance - [x] Keep-out areas honored - [x] Around mounting holes - [x] For programming tools - [x] For assembly tools (wrenches, screwdrivers etc.) - [x] For connectors - [x] Trace-to-trace clearance based upon voltage rating - [x] Component size based upon voltage rating - [x] Keep components away from board edge - [x] Mechanical - [x] CAD file uploaded - [x] Clearance above connectors - [x] Clearance below through-hole components - [x] Enough space for the minimum bending radius of the wire harness - [x] Mounting holes electrically isolated if necessary - [x] Mounting holes have via stitching - [x] Hole diameters leave margin for plating - [x] Board outline defined - [x] Mechanical enclosure defined - [x] Internal corners are rounded and can be milled - [x] Electrical - [x] All traces are routed - [x] Analog and digital commons joined at only one point - [x] ERC passes - [x] Isolation barriers are large enough - [x] Signal integrity - [x] Gaps in ground planes checked and minimized - [x] High-speed signals avoid gaps in ground planes - [x] Stubs minimized for high-speed signals - [x] Differential pair spacing based upon impedance matching - [x] Transmission lines terminated with an appropriate impedance - [x] Crystal connections kept short - [x] Guard ring around crystals - [x] Traces avoided under sensitive components - [x] Traces avoided under noisy components - [x] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda) - [x] Option for a shielding can over sensitive circuitry e.g. RF? - [x] Copper pour - [x] All planes have been poured - [x] Planes and pours checked for high-impedance paths - [x] No pour between adjacent pins on ICs - [x] Traces - [x] Trace-pad connections sufficiently obtuse (angle 90 deg or more) - [x] Trace widths sufficient for the current draw and max heating - [x] No connections between adjacent pins on ICs - [x] Vias for internal power traces sufficiently large - [x] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces - [x] Thermal - [x] Temperature sensitive components placed away from hot components - [x] Thermal vias in thermal pads - [x] Testing - [x] Test points on PCBs for critical circuits, hard to reach nets - [x] Ground connection points close to analog test points - [ ] Silk screen - [x] Notes and documentation - [x] Updated revision number - [x] Updated date - [x] Blank space designated for a serial / assembly number - [x] No silk screen over pads / vias - [ ] Text is readable from at most two directions - [ ] Silk screen size / font will legible after printing - [ ] Connector pin-outs labeled - [ ] Fuse size and type marked on PCB - [ ] Functional groups marked - [ ] Functionality labeled - [ ] Test points - [ ] LEDs - [ ] Buttons - [ ] Connectors/terminals - [ ] Jumpers/fuses

AllSpiceAlice added 1 commit 2024-07-28 22:47:58 +00:00

Add ESD Protection to Endstops 35b7d09b73

AllSpiceAlice requested review from RevaReviewa 2024-07-28 22:49:36 +00:00

AllSpiceAlice requested review from MikaChanical 2024-07-28 22:49:36 +00:00

AllSpiceAlice requested review from PavelInPurchasing 2024-07-28 22:49:37 +00:00

AllSpiceAlice requested review from Allie 2024-07-28 22:49:37 +00:00

AllSpiceAlice requested review from marcus 2024-07-28 22:49:37 +00:00

AllSpiceAlice requested review from brendan 2024-07-28 22:49:37 +00:00

AllSpiceAlice requested review from gautam 2024-07-28 22:49:37 +00:00

AllSpiceAlice added the

labels 2024-07-28 22:49:56 +00:00

AllSpiceAlice added 1 commit 2024-07-28 22:51:17 +00:00

Update BOM 21c1e55002

AllSpiceAlice added 1 commit 2024-07-28 22:51:52 +00:00

Add ESD Protection to fans 10c9814198

AllSpiceAlice added 1 commit 2024-07-28 22:53:03 +00:00

Layout changes for V4, Add mounting holes, remove redundant comonents 67663ce7a4

AllSpiceAlice added 1 commit 2024-07-28 23:02:29 +00:00

Update 5V Trace width 7eaa84ee12

RevaReviewa commented

2024-07-28 23:12:21 +00:00

Member

@daniel, can we remove the E-Stop channel? It's not hooked up to an interrupt and can't actually es-stop.

daniel-allspice reviewed 2024-07-28 23:20:05 +00:00

EndStops.SchDoc

daniel-allspice commented

2024-07-28 23:20:05 +00:00

Member

@RevaReviewa, the extra endstop channel has been removed. Thank you!

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="4.8,40.4,49.6,60.8" aspect-ratio="1.286" } @RevaReviewa, the extra endstop channel has been removed. Thank you!

❤️ 1

brendan marked this conversation as resolved

PavelInPurchasing reviewed 2024-07-28 23:23:42 +00:00

Fans.SchDoc

PavelInPurchasing commented

2024-07-28 23:23:42 +00:00

Member

@daniel, can you replace the LED with something from the approved parts list? We're about to remove this LED because it is end-of-life EOL.

!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="21.3,8.6,37.4,29.5" aspect-ratio="1.286" } @daniel, can you replace the LED with something from the approved parts list? We're about to remove this LED because it is end-of-life EOL.

👍 1

daniel-allspice commented

2024-07-28 23:25:04 +00:00

Member

@PavelInPurchasing, I've switched to a standard APL LED. Thank you! 🙏

brendan marked this conversation as resolved

RevaReviewa reviewed 2024-07-28 23:27:03 +00:00

Archimajor.PcbDoc

RevaReviewa commented

2024-07-28 23:27:03 +00:00

Member

@daniel, why did we remove the debug header?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="17.9,3.2,33.8,21.9" aspect-ratio="1.347" } @daniel, why did we remove the debug header?

daniel-allspice commented

2024-07-28 23:28:05 +00:00

Member

It's the same connector as one of the fan drivers, so technicians and end-users were accidentally pluging in debug equipment into the fan drivers and vice-versa. This was to make it accident-proof.

RevaReviewa commented

2024-07-28 23:28:39 +00:00

Member

That makes sense, thank you.

brendan marked this conversation as resolved

daniel-allspice reviewed 2024-07-28 23:30:24 +00:00

Archimajor.PcbDoc

daniel-allspice commented

2024-07-28 23:30:24 +00:00

Member

@AllSpiceAlice , can you have someone on your team review the new 5V power trace thickness?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="62.1,11.7,82.9,34.8" aspect-ratio="1.347" } @AllSpiceAlice , can you have someone on your team review the new 5V power trace thickness?

AllSpiceAlice commented

2024-07-28 23:31:52 +00:00

Author

Owner

Thank you @daniel, this looks great. All the changes were so quick. Thank you for the expedited layout changes! 🚀

brendan marked this conversation as resolved

MikaChanical reviewed 2024-07-28 23:42:06 +00:00

Archimajor.PcbDoc

MikaChanical commented

2024-07-28 23:42:06 +00:00

Member

@AllSpiceAlice, new mounting holes are perfect. 🥇

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="53.0,0.4,64.8,15.4" aspect-ratio="1.347" } @AllSpiceAlice, new mounting holes are perfect. 🥇

allspice-hermes commented

2024-10-04 17:42:15 +00:00

Owner

Can we make sure that they have the right measures? I thought they were smaller @AllSpiceAlice @MikaChanical

brendan marked this conversation as resolved

PavelInPurchasing referenced this pull request

2024-07-28 23:43:54 +00:00

Replace LED with part from Approved Parts List (APL) #4

brendan reviewed 2024-08-15 15:39:24 +00:00

brendan reviewed 2024-08-28 13:56:08 +00:00

brendan added this to the V4 Release milestone 2024-08-28 14:08:50 +00:00

gautam reviewed 2024-09-05 15:39:46 +00:00

EndStops.SchDoc

gautam commented

2024-09-05 15:39:46 +00:00

Owner

@daniel What's up with this?

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="51.6,15.4,93.9,37.3" aspect-ratio="1.286" } @daniel What's up with this?

AllSpiceAlice commented

2024-09-05 21:19:11 +00:00

Author

Owner

We wanted to add ESD protection. The users kept frying the boards when connecting cables.

AllSpiceAlice reviewed 2024-09-11 17:30:34 +00:00

Fans.SchDoc

AllSpiceAlice commented

2024-09-11 17:30:34 +00:00

Author

Owner

@MikaChanical , is this correct

!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="63.0,27.8,77.1,37.7" aspect-ratio="1.286" } @MikaChanical , is this correct

allspice-hermes changed title from ~~Add ESD Protection to Endstops~~ to WIP: Add ESD Protection to Endstops

2024-09-13 00:05:31 +00:00

allspice-hermes changed title from ~~WIP: Add ESD Protection to Endstops~~ to Add ESD Protection to Endstops

2024-09-13 00:05:44 +00:00

brendan referenced this pull request

2024-09-18 21:12:53 +00:00

Test #18

brendan referenced this pull request

2024-09-19 15:24:22 +00:00

Test #19

brendan reviewed 2024-10-09 22:25:26 +00:00

brendan referenced this pull request

2024-10-15 18:22:29 +00:00

Test #21

brendan referenced this pull request

2024-10-29 15:26:50 +00:00

Test #26

brendan referenced this pull request

2024-11-06 20:34:06 +00:00

Test #27

AllSpiceAlice reviewed 2024-11-26 18:42:21 +00:00

Archimajor.PcbDoc

AllSpiceAlice commented

2024-11-26 18:42:21 +00:00

Author

Owner

@daniel why was this debug header removed

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="18.0,3.1,32.0,13.0" aspect-ratio="1.347" } @daniel why was this debug header removed

brendan referenced this pull request

2024-11-26 20:33:44 +00:00

Test #35

AllSpiceAlice reviewed 2024-12-05 20:07:17 +00:00

EndStops.SchDoc

AllSpiceAlice commented

2024-12-05 20:07:17 +00:00

Author

Owner

@daniel-allspice , why did we remove this channel?

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-Demos/Altium-Demo:c285374952fcea88c33ee99a6badbfa58c18cc50...7eaa84ee12e13afc3adee15ebf0e4f30f55007c4" pr="2" diff-visibility="full" variant="default" view-coords="4.4,37.9,50.7,62.0" aspect-ratio="1.286" } @daniel-allspice , why did we remove this channel?