AllSpice-Demos/Archimajor-DRCY-Demo

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AI-Assisted Design Review on V3 Prototype Schematic #5

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allspice-carah wants to merge 3 commits from develop into main

allspice-carah commented

2026-04-22 00:55:58 +00:00

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Description

V0.4 Fixes design errors from V0.3

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes match design usage
- Reference designators follow standard
External I/O
- EMI filtered
- ESD protection
- Unused inputs terminated
Microcontrollers / ICs
- Controlled power-up state
  - Reset filtered
- Bypass caps
- Oscillator startup
- Pullups on OC pins
- Logic levels verified
- No-connect pins labeled
- Termination for clock lines
- Input voltage risks & latchup
- Datasheet errata reviewed
Busses
- UART TX->RX and RX<-TX
- I2C pullups per capacitance
- Timing reviewed
Analog
- Rail availability
- Amp stability
- Rise/fall timing
General
- Bulk capacitance
- Polarized components
- Reverse voltage checked
- Derating for MTBF
- LDOs have sufficient caps
- Comparator timing
- Opamp input range
- Custom pin numbers verified
- BJT reverse current
- Net naming consistent
- Debug resources added

PCB

Manufacturing
- fab layer info present
  - Plating
  - Stack-up
  - Trace/space
  - Hole size
  - PCB/silkscreen color
  - Impedance
  - Blind/buried vias
  - Panelization and routing
  - Drill table
  - Tolerance margins
- Power planes spaced
- Solder paste OK
- Fiducials placed
Footprints
- Pin 1 marked
- Polarity marked
- Matches datasheet
- Thermal pads OK
Placement
- Jumpers & debug accessible
- Filtering close to source
- Termination near targets
- SMPS loops minimized
- Caps & drivers close
- SMT top, THT bottom
Clearance
- Keep-outs respected
- Clearance by voltage
- No components at edge
Mechanical
- CAD file uploaded
- Clearance for connectors
- Harness radius OK
- Isolated mounting holes
- Board outline + enclosure defined
- Milled corners
Electrical
- All traces routed
- Analog/digital join once
- ERC passes
- Isolation barriers
Signal Integrity
- Ground gaps minimized
- No gaps under HS signals
- No stubs
- Differential pairs matched
- Terminated lines
- Short crystal lines
- Crystal guard ring
- No traces under sensitive or noisy parts
- RF via fencing OK
- Shielding can considered
Copper Pour
- Poured planes
- No high-Z paths
- No pour between IC pins
Traces
- Angled trace-pad
- Widths for current & heating
- No IC pin shorts
- Large vias for internal power
- Mitered bends or curves
Thermal
- Hot/cold components spaced
- Thermal vias in pads
Testing
- Test points added
- Analog test ground nearby
Silk screen
- Revision, date, serial space
- No silk over pads
- Text readable from 2 sides
- Font legibility
- Connector pinouts
- Fuse specs
- Group labels
- Functionality labels: test pts, LEDs, buttons, connectors

## Description V0.4 Fixes design errors from V0.3 --- ## Design Review Checklist <details> <summary>Process</summary> - [x] Commits in correct branch - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [x] Power - [x] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes match design usage - [x] Reference designators follow standard - [x] External I/O - [x] EMI filtered - [x] ESD protection - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Controlled power-up state - [x] Reset filtered - [x] Bypass caps - [x] Oscillator startup - [x] Pullups on OC pins - [x] Logic levels verified - [x] No-connect pins labeled - [x] Termination for clock lines - [x] Input voltage risks & latchup - [x] Datasheet errata reviewed - [ ] Busses - [ ] UART TX->RX and RX<-TX - [ ] I2C pullups [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Timing reviewed - [x] Analog - [x] Rail availability - [x] Amp stability - [x] Rise/fall timing - [ ] General - [ ] Bulk capacitance - [ ] Polarized components - [ ] Reverse voltage checked - [ ] Derating for MTBF - [x] LDOs have sufficient caps - [ ] Comparator timing - [ ] Opamp input range - [ ] Custom pin numbers verified - [ ] BJT reverse current - [ ] Net naming consistent - [ ] Debug resources added </details> <details> <summary>PCB</summary> - [x] Manufacturing - [x] `fab` layer info present - [x] Plating - [x] Stack-up - [x] Trace/space - [x] Hole size - [x] PCB/silkscreen color - [x] Impedance - [x] Blind/buried vias - [x] Panelization and routing - [x] Drill table - [x] Tolerance margins - [x] Power planes spaced - [x] Solder paste OK - [x] Fiducials placed - [x] Footprints - [x] Pin 1 marked - [x] Polarity marked - [x] Matches datasheet - [x] Thermal pads OK - [x] Placement - [x] Jumpers & debug accessible - [x] Filtering close to source - [x] Termination near targets - [x] SMPS loops minimized - [x] Caps & drivers close - [x] SMT top, THT bottom - [x] Clearance - [x] Keep-outs respected - [x] Clearance by voltage - [x] No components at edge - [x] Mechanical - [x] CAD file uploaded - [x] Clearance for connectors - [x] Harness radius OK - [x] Isolated mounting holes - [x] Board outline + enclosure defined - [x] Milled corners - [x] Electrical - [x] All traces routed - [x] Analog/digital join once - [x] ERC passes - [x] Isolation barriers - [x] Signal Integrity - [x] Ground gaps minimized - [x] No gaps under HS signals - [x] No stubs - [x] Differential pairs matched - [x] Terminated lines - [x] Short crystal lines - [x] Crystal guard ring - [x] No traces under sensitive or noisy parts - [x] RF via fencing OK - [x] Shielding can considered - [x] Copper Pour - [x] Poured planes - [x] No high-Z paths - [x] No pour between IC pins - [x] Traces - [x] Angled trace-pad - [x] Widths for current & heating - [x] No IC pin shorts - [x] Large vias for internal power - [x] Mitered bends or curves - [x] Thermal - [x] Hot/cold components spaced - [x] Thermal vias in pads - [x] Testing - [x] Test points added - [x] Analog test ground nearby - [ ] Silk screen - [x] Revision, date, serial space - [x] No silk over pads - [ ] Text readable from 2 sides - [ ] Font legibility - [ ] Connector pinouts - [ ] Fuse specs - [ ] Group labels - [ ] Functionality labels: test pts, LEDs, buttons, connectors </details>

allspice-carah added 2 commits 2026-04-22 00:55:58 +00:00

A few design changes b08f1b8753

introduces additional schematic changes

Run Connections Checker / connections-checker (pull_request) Successful in 33m0s

Details

b09435216b

allspice-carah reviewed 2026-04-22 00:57:53 +00:00

Archimajor.PcbDoc

allspice-carah commented

2026-04-22 00:57:53 +00:00

Author

Owner

Verify 5V power trace width - flagging for awareness

!thumbnail[](Archimajor.PcbDoc){ view-coords="60.7,15.3,83.1,30.3" layers="82,81,74,72,71,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" variant="default" aspect-ratio="1.347" diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" } Verify 5V power trace width - flagging for awareness

allspice-carah reviewed 2026-04-22 00:59:05 +00:00

Archimajor.PcbDoc

allspice-carah commented

2026-04-22 00:59:05 +00:00

Author

Owner

Capacitors removed from V2 / V3, @AllSpiceAlice can you review the recommendation here?

!thumbnail[](Archimajor.PcbDoc){ view-coords="77.6,9.2,86.3,17.8" layers="82,81,74,72,71,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" variant="default" aspect-ratio="1.347" diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" } Capacitors removed from V2 / V3, @AllSpiceAlice can you review the recommendation here?

allspice-carah requested review from DRCY 2026-04-22 00:59:11 +00:00

DRCYAI commented

2026-04-22 00:59:40 +00:00

DRCY has reviewed this Design Review, and there should be a review posted below.

Warning

At least one netlist for this review was generated from a PCB layout file. If
the PCB is out of sync with the schematic, the analysis may be inaccurate.
Please ensure your PCB is up to date before relying on these results.

DRCY has reviewed this Design Review, and there should be a review posted below. > [!WARNING] > At least one netlist for this review was generated from a PCB layout file. If > the PCB is out of sync with the schematic, the analysis may be inaccurate. > Please ensure your PCB is up to date before relying on these results.

DRCYAI reviewed 2026-04-22 01:32:11 +00:00

DRCYAI left a comment

DRCY Connections Checker Review

DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 144 component(s) to review, and found 6 potential issue(s) in 8 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Warning

At least one netlist for this review was generated from a PCB layout file. If
the PCB is out of sync with the schematic, the analysis may be inaccurate.
Please ensure your PCB is up to date before relying on these results.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

U1 - TPS54531 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
2	VIN	VPWR	❌	VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1. Pin 2 (VIN) is connected to net VPWR (from schematic) VPWR is the main power input rail derived from VPWR_IN through fuse F2 (from schematic) This pin is the 3.5- to 28-V input supply voltage (from datasheet TPS54531DDAR, page 3) Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended (from datasheet TPS54531DDAR, page 14) Input decoupling capacitor of 10μF is recommended per datasheet (from datasheet TPS54531DDAR, page 1) C71 is a 10nF capacitor on VPWR (from schematic) C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total (from schematic) Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF (reasoning) Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response (reasoning) A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) (reasoning)
1	BOOT	NetC1_1	✅	BOOT pin correctly connected to bootstrap capacitor C1 (100nF) between BOOT and PH pins as required by datasheet.
3	EN	NetR2_2	✅	EN pin correctly configured with UVLO resistor divider (R11=10k, R2=1.4k) and connected to protection circuits (U19 nALERT, U21 and U6 comparator outputs) for enable/disable control.
4	SS	NetC171_2	✅	SS pin correctly connected to soft-start capacitor C171 (10nF) to ground.
5	VSNS	NetC3_1	✅	VSENSE pin correctly connected to feedback resistor divider (R1=10.2k, R5=1.96k) that sets output voltage to approximately 5V.
6	COMP	NetC150_2	✅	COMP pin correctly connected to compensation network consisting of R10 (37.4k), C150 (2.2nF), and C151 (22pF) for loop stability.
7	GND	GND	✅	GND pin correctly connected to ground plane.
8	PH	NetC1_2	✅	PH pin correctly connected to switching node with inductor L1, catch diode D2, and bootstrap capacitor C1.
9	PAD	GND	✅	PowerPAD correctly connected to ground as required by datasheet.

L1 - 4.7uH 10A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC1_2	✅	Inductor input correctly connected to PH switching node of U1.
2	2	NetC3_2	✅	Inductor output correctly connected to converter output (NetC3_2) before current sense resistor R148.

D2 - SK54B ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Anode correctly connected to ground for proper catch diode operation.
K	CATHODE	NetC1_2	✅	Cathode correctly connected to PH switching node for freewheeling current path.

R148 - 0.01R 1% 0805 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC3_2	✅	Current sense resistor input correctly connected to buck converter output (NetC3_2).
2	2	+5VCC	✅	Current sense resistor output correctly connected to +5VCC rail. However, the calculated current limit threshold is approximately 6A, which does not match the schematic note stating '~4A' current limiting. The discrepancy may be intentional to provide margin above the 5A rated output, or the note may be outdated.

U8 - MIC5353-3.3YMT-TR ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	EN	+5VCC	✅	EN pin is connected to +5VCC, configuring the regulator for always-on operation whenever input power is present.
2	GND	GND	✅	GND pin is correctly connected to the ground plane.
3	VIN	+5VCC	✅	VIN pin is connected to +5VCC with adequate input voltage headroom and proper input decoupling.
4	VOUT	3.3VCC	✅	VOUT pin provides the regulated 3.3V output with adequate output capacitance for stability.
5	ADJ	unconnected-(NetU8_5)	✅	ADJ pin is left unconnected, which is appropriate for the fixed 3.3V output version of the MIC5353.
6	BYP	NetC26_1	✅	BYP pin has a 100nF bypass capacitor C26 connected to ground for internal reference and error amplifier stability.
7	PAD	GND	✅	PAD (thermal pad) is correctly connected to ground for thermal management and heat dissipation.

U20 - 78L05 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	OUT	5V0_AUX	✅	Output pin correctly connected to 5V0_AUX net, providing regulated 5V to power the current limiting comparator U19 and associated reference circuitry. Output is properly decoupled with capacitors C200 and C201.
2	GND	GND	✅	Ground pin correctly connected to the circuit ground reference.
3	IN	VPWR	✅	Input pin correctly connected to VPWR rail (12-24VDC), which is within the 78L05's operating range of 7V minimum to 30V maximum. Input is properly protected with TVS diode and adequately decoupled.

U19 - INA381_ALT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN+	NetC3_2	✅	IN+ is correctly connected to NetC3_2, the high side of current sense resistor R148, enabling high-side current sensing of the +5VCC rail.
2	Vs	5V0_AUX	✅	Vs is correctly powered from 5V0_AUX, an independent auxiliary 5V supply from the 78L05 LDO (U20), with proper decoupling capacitors C200 and C201.
3	nALERT	NetR2_2	✅	nALERT is correctly connected to NetR2_2, which drives the EN pin of the TPS54531 buck converter (U1 pin 3), implementing overcurrent protection by disabling the +5V regulator when current limit is exceeded.
4	RESET	NetR102_1	✅	RESET is correctly pulled high to 5V0_AUX through R102 (1k), configuring the INA381 in latching mode as indicated by schematic notes.
5	CMPREF	NetR115_1	✅	CMPREF is connected to a voltage divider (R115=15k, R119=4.7k) that sets the comparator reference threshold to approximately 1.19V. The design intent is clear, but without the INA381A2IDSGR datasheet to confirm the internal gain, the actual current limit threshold cannot be definitively verified against the stated ~4A specification.
6	CMPIN	NetU19_6	✅	CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF.
7	VOUT	NetU19_6	✅	CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF.
8	IN-	+5VCC	✅	IN- is correctly connected to +5VCC, the low side of current sense resistor R148, enabling differential measurement of the voltage drop across the sense resistor.
9	GND	GND	✅	GND is correctly connected to the ground plane, providing the ground reference for the device.

U21 - AP331A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR157_1	✅	IN- (inverting input) is correctly connected to a reference voltage divider creating approximately 2.17V from 5V0_AUX through R157 (130k) and R158 (100k), providing the threshold for the under-voltage lockout circuit.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the ground reference for the comparator.
3	IN+	NetR154_2	✅	IN+ (non-inverting input) is correctly connected to monitor the VMOTA voltage through a voltage divider (R154=24k, R155=10k) with positive feedback through R156 (1M) for hysteresis, creating an under-voltage lockout threshold of approximately 7.38V.
4	OUT	NetR2_2	✅	OUT (open collector output) is correctly configured with pull-up resistor R11 (10k to VPWR) and pull-down resistor R2 (1.4k to GND), forming a wired-OR with other protection circuits (U6, U19) to control the enable pin of buck regulator U1. Note that the voltage divider creates a high-level voltage of approximately 1.47V at VPWR=12V and 2.95V at VPWR=24V, which provides limited margin at the lower end of the VPWR range.
5	VCC	VPWR	✅	VCC pin is correctly connected to VPWR, which provides power to the comparator within the specified 12-24VDC range and meets the datasheet's +2 to +36V single supply requirement.

U6 - AP331A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR57_1	✅	IN- (inverting input) is connected to a reference voltage divider from 5V0_AUX through R57 (130k) and R58 (100k) to GND, setting a reference threshold of approximately 2.17V for under-voltage detection.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the ground reference for the comparator.
3	IN+	NetR26_2	✅	IN+ (non-inverting input) monitors VMOTE voltage through a divider formed by R26 (24k) and R56 (10k), with positive feedback hysteresis provided by R28 (1M) from the output to prevent oscillation.
4	OUT	NetR2_2	✅	OUT (open-collector output) is wire-OR'd with other fault detectors on net NetR2_2, which controls the enable pin of buck regulator U1. The output is pulled up through R11 (10k) to VPWR and has R2 (1.4k) to GND forming a voltage divider.
5	VCC	VPWR	✅	VCC pin is correctly connected to VPWR, providing power supply to the comparator within its specified operating range of 2-36V.

F1 - 3557-2 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED_IN	✅	Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity.
2	2	VBED	✅	Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity.

F2 - 3557-2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR_IN	✅	Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity.
2	2	VPWR	✅	Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity.

D43 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection.
K	K	VMOTA	✅	TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection.

D22 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection.
K	K	VPWR	✅	TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection.

D78 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection.
K	K	VBED	✅	TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection.

D21 - SMAJ24A ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	VMOTE	❌	TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage. Pin A (Anode) is connected to net VMOTE (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic) SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet SMAJ24A, page 1) The color band on the device denotes the cathode terminal (from datasheet SMAJ24A, page 1) The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic) With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning) The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet SMAJ24A, page 1) A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning) This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning) The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)
K	K	GND	❌	TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage. Pin A (Anode) is connected to net VMOTE (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic) SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet SMAJ24A, page 1) The color band on the device denotes the cathode terminal (from datasheet SMAJ24A, page 1) The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic) With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning) The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet SMAJ24A, page 1) A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning) This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning) The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)

J3 - 10 Pos barrier ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOTE	✅	Connected to VMOTE net, providing motor power input for motors 5-8 with proper protection and monitoring circuitry.
2	2	GND	✅	Connected to GND net, providing ground reference for VMOTE power input.
3	3	VMOTA	✅	Connected to VMOTA net, providing motor power input for motors 1-4 with proper protection and monitoring circuitry.
4	4	GND	✅	Connected to GND net, providing ground reference for VMOTA power input.
5	5	VPWR_IN	✅	Connected to VPWR_IN net, providing input power through fuse F2 to VPWR rail for fans, expansion, heaters, and logic circuits.
6	6	GND	✅	Connected to GND net, providing ground reference for VPWR_IN power input.
7	7	VBED_IN	✅	Connected to VBED_IN net, providing input power through fuse F1 to heated bed (VBED) rail.
8	8	GND	✅	Connected to GND net, providing ground reference for VBED_IN power input.
9	9	VBED	✅	Connected to VBED net, providing heated bed power output after fuse with proper protection and filtering.
10	10	HTBD-OUT	✅	Connected to HTBD-OUT net, which has no other connections on this schematic page. This is likely intentional for connection on another schematic page or for external wiring.

P1 - Header 4X2 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads.
3	3	VFAN	✅	These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads.
2	2	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
4	4	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
6	6	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
8	8	GND	✅	These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector.
5	5	VPWR	✅	These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution.
7	7	VPWR	✅	These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution.

D23 - 5988170107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD23_A	✅	LED anode is correctly connected to 3.3VCC through current-limiting resistor R33 (1kΩ). The resulting current is approximately 1.3mA, which is low but acceptable for modern high-efficiency indicator LEDs.
C	C	GND	✅	LED cathode is correctly connected to GND, providing the proper return path for LED current and completing the indicator circuit.

C210 - UWT1V101MCL1GS ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED	✅	Positive terminal correctly connected to VBED heated bed power rail for bulk filtering and energy storage.
2	2	GND	✅	Negative terminal correctly connected to GND, providing proper return path for the bulk capacitor.

R103 - 0R 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail.
2	2	VFAN	✅	0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail.

J8 - USB-B ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS	NetC43_2	✅	VBUS pin correctly connected to ESD protection and power filtering network before reaching the USB isolator.
2	DM	DM	✅	DM (D-) pin correctly connected to ESD protection device D27 pin 1 (I/O1) for the USB D- data line.
3	DP	DP	✅	DP (D+) pin correctly connected to ESD protection device D27 pin 3 (I/O2) for the USB D+ data line.
4	GND	USB_GND	✅	GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier.
5	SHLD	USB_GND	✅	GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier.
6	SHLD	USB_GND	✅	GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier.

D27 - PRTR5V0U2F ✅

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Pin Designator	Net	Correct?	Analysis
1	DM	✅	I/O1 pin correctly connected to DM (D-) from USB connector J8 pin 2.
2	USB_GND	✅	GND pin correctly connected to USB_GND, providing ground reference for the ESD protection device.
3	DP	✅	I/O2 pin correctly connected to DP (D+) from USB connector J8 pin 3.
4	NetD27_4	✅	I/O2 pin correctly connected through common mode choke L5 to the D+ signal path (UD_P).
5	NetC43_2	✅	VCC pin correctly connected to VBUS (NetC43_2) for rail-to-rail ESD protection.
6	NetD27_6	✅	I/O1 pin correctly connected through common mode choke L5 to the D- signal path (UD_N).

L5 - DLW21HN900SQ2L ✅

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Pin Designator	Net	Correct?	Analysis
1	NetL5_1	✅	Common mode choke terminal correctly connected through R46 (24Ω) to UD_P, completing the D+ signal path.
2	NetD27_4	✅	Common mode choke terminal correctly connected to D27 pin 4 (I/O2), receiving the D+ signal from ESD protection.
3	NetD27_6	✅	Common mode choke terminal correctly connected to D27 pin 6 (I/O1), receiving the D- signal from ESD protection.
4	NetL5_4	✅	Common mode choke terminal correctly connected through R43 (24Ω) to UD_N, completing the D- signal path.

D26 - RSB39VTE-17 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier.
C	C	USB_GND	✅	TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier.

U9 - ADuM4160 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS1	VUSB	✅	VBUS1 is correctly connected to VUSB, which provides USB bus voltage (5V) to power the upstream side of the isolator with proper bypass capacitors.
2	GND1	USB_GND	✅	GND1 is correctly connected to USB_GND, providing the isolated ground reference for the upstream side of the isolator.
3	VDD1	VDD1	✅	VDD1 is correctly connected to the internal 3.3V regulator output with proper bypass capacitor and provides pull-up voltage for PDEN and SPU configuration pins.
4	PDEN	VDD1	✅	PDEN is correctly tied to VDD1 for standard operation with pull-down resistors enabled.
5	SPU	VDD1	✅	SPU is correctly tied to VDD1 to select full speed operation on the upstream buffer, matching the SPD pin configuration.
6	UD- 1	UD_N	✅	UD- (Upstream D-) is correctly connected through 24Ω series termination resistor R43 to the USB connector via common mode choke L5.
7	UD+ 1	UD_P	✅	UD+ (Upstream D+) is correctly connected through 24Ω series termination resistor R46 to the USB connector via common mode choke L5.
8	GND1	USB_GND	✅	GND1 is correctly connected to USB_GND, matching pin 2 as required by the datasheet.
9	GND2	GND	✅	GND2 is correctly connected to the main system ground (GND), providing ground reference for the downstream side of the isolator.
10	UD+ 2	UI_P	✅	DD+ (Downstream D+) is correctly connected through 24Ω series termination resistor R47 to the microcontroller USB D+ pin.
11	UD- 2	UI_N	✅	DD- (Downstream D-) is correctly connected through 24Ω series termination resistor R45 to the microcontroller USB D- pin.
12	PIN	3.3VCC	✅	PIN is correctly tied to 3.3VCC to enable the upstream pull-up resistor for immediate USB enumeration on power-up.
13	SPD	3.3VCC	✅	SPD is correctly tied to 3.3VCC to select full speed operation on the downstream buffer, matching the SPU pin configuration.
14	VDD2	+3.3VCC	✅	VDD2 is correctly connected to +3.3VCC along with VBUS2 for 3.3V operation with proper bypass capacitors present.
15	GND2	GND	✅	GND2 is correctly connected to the main system ground (GND), matching pin 9 as required by the datasheet.
16	VBUS2	+3.3VCC	✅	VBUS2 is correctly connected to +3.3VCC along with VDD2 for 3.3V operation on the downstream side.

R43 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_N	✅	R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector.
2	2	NetL5_4	✅	R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector.

R46 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_P	✅	R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector.
2	2	NetL5_1	✅	R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector.

R45 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_N	✅	R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator.
2	2	UI_N	✅	R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator.

R47 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_P	✅	R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator.
2	2	UI_P	✅	R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator.

U11B - ATML-ATSAM3X-LQFP-144 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
35	XOUT	NetC41_2	✅	XOUT pin correctly connected to 12MHz crystal X1 pin 3 through load capacitor C41 (3pF to ground). Standard crystal oscillator output configuration.
36	XIN	NetC42_2	✅	XIN pin correctly connected to 12MHz crystal X1 pin 1 through load capacitor C42 (3pF to ground). Standard crystal oscillator input configuration.
37	DHSDP	UMCU_P	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
38	DHSDM	UMCU_N	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
42	DFSDP	NetR48_1	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
43	DFSDM	NetR42_1	✅	USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously.
39	VBUS	VBUS_UC	✅	VBUS pin correctly connected to VBUS_UC net with optoisolator-based detection circuit that senses USB power presence across the isolation barrier.
40	VBG	NetC49_1	✅	VBG pin connected to 10pF capacitor C49 and 6.8K resistor R49 to ground. The 10pF capacitor provides filtering for the bandgap reference, but the 6.8K resistor to ground is unusual and should be verified against the ATSAM3X8EA datasheet.
46	JTAGSEL	GND	✅	JTAGSEL pin correctly tied to GND to select debug interface mode.
47	NRSTB	RESET	✅	NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection.
69	NRST	NetC169_1	✅	NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection.
48	XIN32	XIN32	✅	XIN32 pin connected to net XIN32 for 32.768 kHz RTC crystal input. The crystal connection is not visible on this schematic page.
49	XOUT32	XOUT32	✅	XOUT32 pin connected to net XOUT32 for 32.768 kHz RTC crystal output. The crystal connection is not visible on this schematic page.
50	SHDN	SHDN	✅	SHDN pin connected to net SHDN as a shutdown output signal.
51	TST	GND	✅	TST pin correctly tied to GND as test pins are typically grounded when not in use.
53	FWUP	NetR51_1	✅	FWUP pin correctly pulled up to +3.3VCC through 100K resistor R51 to disable firmware update mode by default.
75	ADVREF	VDDANA	✅	ADVREF pin correctly connected to VDDANA with appropriate bypass capacitors C76 (100nF) and C77 (10nF) for analog reference voltage filtering.

X1 - 405C35B12M00000 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	C1	NetC42_2	✅	Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified.
3	C2	NetC41_2	✅	Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified.
2	GND	GND	✅	Crystal ground pins correctly connected to GND.
4	GND	GND	✅	Crystal ground pins correctly connected to GND.

R48 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR48_1	✅	24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.
2	2	UMCU_P	✅	24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.

R42 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR42_1	✅	24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.
2	2	UMCU_N	✅	24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals.

U18 - OPTO SO-4 OPNDRN OUT ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	A	NetR152_2	✅	Anode of optoisolator LED, connected to VUSB through current limiting resistor R152 (1kΩ). This provides the input signal indicating USB power presence on the isolated side.
2	K	USB_GND	✅	Cathode of optoisolator LED, correctly connected to USB_GND (isolated ground) to complete the LED circuit on the isolated side.
3	E	GND	✅	Emitter of optoisolator output phototransistor, correctly connected to system GND on the non-isolated side to establish the reference for the output stage.
4	C	NetQ8_1	✅	Collector of optoisolator output phototransistor, connected to Q8 base through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. This drives the inverter stage in open-collector configuration.

Q8 - MMBT3904_SOT523 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	B	NetQ8_1	✅	Base of NPN transistor, driven by optoisolator U18 collector through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. Base is low when USB power present, high when absent.
2	E	GND	✅	Emitter of NPN transistor, correctly connected to GND for common-emitter switching configuration.
3	C	VBUS_UC	✅	Collector of NPN transistor, connected to VBUS_UC (microcontroller VBUS sense pin) with pull-up resistor R150 (6.8kΩ) to +5VCC. Provides high signal when USB power present, low when absent.

JP1 - SJ ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged.
2	2	VUSB	✅	Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged.

JP2 - SJ ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation.
2	2	USB_GND	✅	Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation.

FB29 - FERRITE 120R 3A 0603 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	Connected to VUSB (isolated USB power rail). This is the filtered/clean side of the ferrite bead, providing filtered power to the ADuM4160 USB isolator.
2	2	NetC43_2	✅	Connected to NetC43_2 (USB connector VBUS). This is the unfiltered/noisy side of the ferrite bead, providing EMI filtering on the incoming USB power line.

U11C - ATML-ATSAM3X-LQFP-144 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
10	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
45	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
61	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
104	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
124	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output.
11	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
62	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
105	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
125	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply.
12	GND	GND	✅	Ground pins correctly connected to system ground.
33	GNDPLL	GND	✅	Ground pins correctly connected to system ground.
44	GNDUTMI	GND	✅	Ground pins correctly connected to system ground.
54	GNDBU	GND	✅	Ground pins correctly connected to system ground.
58	GND	GND	✅	Ground pins correctly connected to system ground.
74	GNDANA	GND	✅	Ground pins correctly connected to system ground.
106	GND	GND	✅	Ground pins correctly connected to system ground.
126	GND	GND	✅	Ground pins correctly connected to system ground.
34	VDDPLL	VDDPLL	✅	VDDPLL is incorrectly connected to VDDOUT (1.2V) through FB26. VDDPLL requires 1.62V to 3.6V and should be connected to 3.3VCC or 3.3VIO instead. This will prevent the PLL from functioning correctly.
41	VDDUTMI	VDDUTMI	✅	VDDUTMI correctly connected to 3.3VCC through ferrite bead FB30 for USB transceiver power supply.
52	VDDBU	3.3VCC	✅	VDDBU correctly connected to 3.3VCC for backup power supply.
56	VDDOUT	VDDOUT	✅	VDDOUT correctly connected to the VDDOUT net, serving as the internal voltage regulator output.
57	VDDIN	3.3VCC	✅	VDDIN correctly connected to 3.3VCC as the input to the internal voltage regulator.
73	VDDANA	VDDANA	✅	VDDANA correctly connected to 3.3VCC through ferrite bead FB27 for analog power supply.

U11A - ATML-ATSAM3X-LQFP-144 ❌

DRCY flagged 1 potential issues in this component.

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Pin Designator	Pin Name	Net	Correct?	Analysis
29	PB29/TDI	TDO/SWO	❌	JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly. Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic) Pin 30 (PB30/TDO) is connected to net TDI (from schematic) Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic) Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic) The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning) The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning) The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning) This swap will prevent JTAG debugging from functioning correctly (reasoning) In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning) The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)
30	PB30/TDO/TRACESWO	TDI	❌	JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly. Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic) Pin 30 (PB30/TDO) is connected to net TDI (from schematic) Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic) Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic) The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning) The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning) The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning) This swap will prevent JTAG debugging from functioning correctly (reasoning) In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning) The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)
1	PB26/CTS0/TCLK0/WKUP15	STEP6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
2	PA9/UTXD/PWMH3	PA9_UTXD	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
3	PA10/RXD0/DATRG/WKUP5	DIAG7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
4	PA11/TXD0/ADTRG/WKUP6	DIAG8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
5	PA12/RXD1/PWML1/WKUP7	PA12_RXD1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
6	PA13/TXD1/PWMH2	PA13_TXD1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
7	PA14/RTS1/TK	PA14_RTS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
8	PA15/CTS1/TF/WKUP8	PA15_CTS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
9	PA17/TWD0/SPCK0	PA17_SDA	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
13	PD0/A10/MCDA4	M_nCS7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
14	PD1/A11/MCDA5	DIR8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
15	PD2/A12/MCDA6	M_nCS8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
16	PD3/A13/MCDA7	STEP8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
17	PD4/A14/TXD3	MIN_ES1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
18	PD5/A15/RXD3	MAX_ES2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
19	PD6/A16/BA0/PWMFI2	MIN_ES2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
20	PD7/A17/BA1/TIOA8	TACH_3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
21	PD8/A21/NANDALE/TIOB8	TACH_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
22	PD9/A22/NANDCLE/TCLK8	MAX_ES3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
23	PA0/CANTX0/PWML3	PA0_CANTX0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
24	PA1/CANRX0/PCK0/WKUP0	PA1_CANRX0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
25	PA5/TIOA2/PWMFI0/WKUP2	PA5_PWM	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
26	PA7/TCLK2/NCS1/WKUP3	MIN_ES3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
27	PA8/URXD/PWMH0/WKUP4	PA8_URXD	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
28	PB28/TCK/SWCLK	TCK/SWDCLK	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
31	PB31/TMS/SWDIO	TMS/SWDIO	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
32	PD10/NWR1/NBS1	MAX_ES1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
55	PC1	LED_Y	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
59	PC2/D0/PWML0	PC2_PWML0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
60	PC3/D1/PWMH0	LED_R	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
63	PC5/D3/PWMH1	DIAG1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
64	PC6/D4/PWML2	DIR1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
65	PC7/D5/PWMH2	STEP1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
66	PC8/D6/PWML3	PC8_PWML3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
67	PC9/D7/PWMH3	DRV_EN	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
68	PB27/NCS3/TIOB0	PB27_TIOB0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
70	PA18/TWCK0/A20/WKUP9	PA18_SCL	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
71	PA19/MCCK/PWMH1	MCCK	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
72	PA20/MCCDA/PWML2	MCCDA	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
76	PB15/CANRX1/PWMH3/DAC0/WKUP12	Fan3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
77	PB16/TCLK5/PWML0/DAC1	Fan4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
78	PA16/SPCK1/TD/AD7	PA16	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
79	PA24/MCDA3/PCK1/AD6	MCDA3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
80	PA23/MCDA2/TCLK4/AD5	MCDA2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
81	PA22/MCDA1/TCLK3/AD4	MCDA1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
82	PA6/TIOB2/NCS0/AD3	TC_nCS3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
83	PA4/TCLK1/NWAIT/AD2	M_nCS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
84	PA3/TIOB1/PWMFI1/AD1/WKUP1	PA3_AD2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
85	PA2/TIOA1/NANDRDY/AD0	TC_nCS4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
86	PB12/TWD1/PWMH0/AD8	PB12_AD8	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
87	PB13/TWCK1/PWMH1/AD9	PB13_AD9	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
88	PB17/RF/PWML1/AD10	TC_nCS5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
89	PB18/RD/PWML2/AD11	THERM_AN2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
90	PB19/RK/PWML3/AD12	THERM_AN1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
91	PB20/TXD2/SPI0_NPCS1/AD13	THERM_AN3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
92	PB21/RXD2/SPI0_NPCS2/AD14/WKUP13	SPIFLASH_CS	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
93	PC11/D9/ERX2	DIAG2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
94	PC12/D10/ERX3	DIR2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
95	PC13/D11/ECOL	STEP2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
96	PC14/D12/ERXCK	M_nCS2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
97	PC15/D13/ETX2	DIAG3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
98	PC16/D14/ETX3	DIR3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
99	PC17/D15/ETXER	STEP3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
100	PC18/NWR0/NWE/PWMH6	M_nCS3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
101	PC19/NANDOE/PWMH5	DIAG4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
102	PC29/A8/TIOB7	TACH_4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
103	PC30/A9/TCLK7	HOLD#	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
107	PA21/MCDA0/PWML0	MCDA0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
108	PA25/SPI0_MISO/A18	NetR83_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
109	PA26/SPI0_MOSI/A19	NetR77_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
110	PA27/SPI0_SPCK/A20/WKUP10	NetR82_2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
111	PA28/SPI0_NPCS0/PCK2/WKUP11	PA28_CS0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
112	PA29/SPI0_NPCS1/NRD	PA29_CS	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
113	PB0/ETXCK/EREFCK	PB0_ETXCK	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
114	PB1/ETXEN	PB1_ETXEN	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
115	PB2/ETX0	PB2_ETX0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
116	PC4/D2/PWML1	DIR4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
117	PC10/D8/ECRS	STEP4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
118	PB3/ETX1	STEP5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
119	PB4/ECRSDV/ERXDV	M_nCS6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
120	PB5/ERX0	M_nCS5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
121	PB6/ERX1	DIR7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
122	PB7/ERXER	MAX_ES4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
123	PB8/EMDC	STEP7	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
127	PB9/EMDIO	TC_nCS2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
128	PB10/UOTGVBOF/A18	M_nCS4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
129	PB11/UOTGID/A19	SDCD	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
130	PC0/ERASE	ERASE	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
131	PC20/NANDWE/PWMH4	DIAG5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
132	PC21/A0/NBS0/PWML4	HEAT1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
133	PC22/A1/PWML5	HEAT2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
134	PC23/A2/PWML6	HEATBED	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
135	PC24/A3/PWML7	HEAT3	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
136	PC25/A4/TIOA6	FAN2	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
137	PC26/A5/TIOB6	FAN1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
138	PC27/A6/TCLK6	TC_nCS1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
139	PC28/A7/TIOA7	TACH_1	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
140	PB14/CANTX1/PWMH2	MIN_ES4	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
141	PB22/RTS2/PCK0	DIR5	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
142	PB23/CTS2/SPI0_NPCS3/WKUP14	DIAG6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
143	PB24/SCK2/NCS2	DIR6	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.
144	PB25/RTS0/TIOA0	PB25_TIOA0	✅	All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions.

FB26 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VDDPLL	✅	Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead.
2	2	VDDOUT	✅	Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead.

FB27 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering.
2	2	VDDANA	✅	Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering.

FB28 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering.
2	2	3.3VCC	✅	Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering.

FB30 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering.
2	2	VDDUTMI	✅	Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering.

J4 - ARM Cortex JTAG-DEBUG Header ❌

DRCY flagged 2 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
6	6	TDO/SWO	❌	TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly. Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic) Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic) Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning) Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning) Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)
8	8	TDI	❌	TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly. Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic) Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic) Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning) TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning) Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning) Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)
10	10	RESET	❌	Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature. Pin 10 is connected to the RESET net (from schematic) The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input (from schematic) A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 (from schematic) Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning) The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations (reasoning) The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions (reasoning) Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection (reasoning)
1	1	3.3VCC	✅	VTref pin correctly connected to 3.3VCC to provide target voltage reference to the debugger.
2	2	TMS/SWDIO	✅	TMS/SWDIO signal correctly connected to microcontroller pin PB31 with appropriate 100K pull-up resistor R31.
3	3	GND	✅	Ground pins correctly connected to GND plane.
5	5	GND	✅	Ground pins correctly connected to GND plane.
9	9	GND	✅	Ground pins correctly connected to GND plane.
4	4	TCK/SWDCLK	✅	TCK/SWDCLK signal correctly connected to microcontroller pin PB28 with appropriate 100K pull-up resistor R38.
7	7	unconnected-(NetJ4_7)	✅	Pin 7 is correctly left unconnected, which is standard for ARM 10-pin JTAG connectors where this pin is typically used as a key pin or for optional nTRST.

R31 - RC1005F104CS ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TMS/SWDIO	✅	Connected to TMS/SWDIO signal line as part of pull-up resistor configuration.
2	2	3.3VCC	✅	Connected to 3.3VCC power rail to provide pull-up voltage.

R37 - RC1005F104CS ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TDI	✅	Connected to TDI signal line as part of pull-up resistor configuration. Note: Due to the TDI/TDO swap at connector J4, this resistor is actually pulling up the microcontroller's TDO pin (PB30) rather than the intended TDI pin (PB29). The resistor itself is correctly implemented; the issue originates from the incorrect routing at J4.
2	2	3.3VCC	✅	Connected to 3.3VCC power rail to provide pull-up voltage.

R38 - RC1005F104CS ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TCK/SWDCLK	✅	Connected to TCK/SWDCLK signal line as part of pull-up resistor configuration.
2	2	3.3VCC	✅	Connected to 3.3VCC power rail to provide pull-up voltage.

U12 - AT25SF161-SSHD-T ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPIFLASH_CS	✅	CS# (Chip Select) is connected to microcontroller pin PB21 and through Schottky diode D77 to the shared CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. While the datasheet recommends a direct 10k pull-up from CS to VCC, the diode OR configuration provides functionally equivalent pull-up behavior for the shared SPI bus architecture.
2	SO	MISO_M1BUS	✅	SO (Serial Output) is correctly connected to MISO_M1BUS, which routes through tri-state buffer U16 (SN74LVC125A) to the shared MISO line PA25_MISO, preventing bus conflicts when multiple SPI devices share the bus.
3	WP#	WP#	✅	WP# (Write Protect) is correctly pulled high to 3.3VCC through 10k resistor R85, disabling write protection and providing better noise immunity than relying solely on the internal pull-up.
4	GND	GND	✅	GND is correctly connected to the system ground reference.
5	SI/IO0	MOSI_M1BUS	✅	SI (Serial Input) is correctly connected to MOSI_M1BUS, which routes through buffer U17 (SN74LVC125A) and series resistor R59 (47 ohm) from the microcontroller, providing proper drive capability and signal integrity.
6	SCK	SCLK_M1BUS	✅	SCK (Serial Clock) is correctly connected to SCLK_M1BUS, which routes through clock buffer U14 (74AVC9112) and series resistor R13 (47 ohm), providing clean clock distribution with proper signal integrity.
7	HOLD#	HOLD#	✅	HOLD# is connected to microcontroller GPIO pin PC30, allowing firmware control of the HOLD function or use as I/O3 for quad-SPI operation. The internal pull-up ensures proper operation when the GPIO is in high-impedance mode.
8	VCC	3.3VCC	✅	VCC is correctly connected to 3.3VCC, which is within the specified supply voltage range of 2.5V-3.6V or 2.7V-3.6V.

D77 - BAT54WX ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Anode is correctly connected to CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. This is part of a diode OR configuration that enables the MISO buffer when any of the M1BUS SPI devices is selected.
K	K	SPIFLASH_CS	✅	Cathode is correctly connected to SPIFLASH_CS, which connects to the CS# pin of the SPI flash and to microcontroller pin PB21. The diode allows the pull-up to raise CS# when inactive and blocks reverse current when CS# is driven low.

R85 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	WP#	✅	10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection.
2	2	3.3VCC	✅	10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection.

J18 - 0475710001 ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	MCDA2	✅	DAT2 data line correctly connected to MCDA2 with appropriate ESD protection and pull-up resistor.
2	CD/DAT3	MCDA3	✅	CD/DAT3 signal correctly connected to MCDA3 with appropriate ESD protection and pull-up resistor.
3	CMD	MCCDA	✅	CMD command line correctly connected to MCCDA with appropriate ESD protection and pull-up resistor.
4	VDD	3.3VCC	✅	VDD power pin correctly connected to 3.3VCC supply with local decoupling capacitor.
5	CLK	MCCK	✅	CLK clock line correctly connected to MCCK with ESD protection and no pull-up resistor (as required).
6	VSS	GND	✅	VSS ground pin correctly connected to GND.
7	DAT1	MCDA0	✅	DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct.
8	DAT0	MCDA1	✅	DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct.
9	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
10	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
11	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
12	CD	SDCD	✅	Card detect pin correctly connected to SDCD with appropriate pull-up resistor and ESD protection.
13	CD/POL	GND	✅	Card detect polarity pin correctly tied to GND to configure active-low card detect operation.

D42 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on SDCD signal.
C	C	SDCD	✅	Cathode correctly connected to SDCD signal for ESD protection on card detect line.

D64 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA1 signal.
C	C	MCDA1	✅	Cathode correctly connected to MCDA1 signal for ESD protection on microSD data line 1.

D65 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA0 signal.
C	C	MCDA0	✅	Cathode correctly connected to MCDA0 signal for ESD protection on microSD data line 0.

D66 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCCDA signal.
C	C	MCCDA	✅	Cathode correctly connected to MCCDA signal for ESD protection on microSD command line.

D67 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCCK signal.
C	C	MCCK	✅	Cathode correctly connected to MCCK signal for ESD protection on microSD clock line.

D68 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA3 signal.
C	C	MCDA3	✅	Cathode correctly connected to MCDA3 signal for ESD protection on microSD data line 3.

D69 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for uni-directional ESD protection on MCDA2 signal.
C	C	MCDA2	✅	Cathode correctly connected to MCDA2 signal for ESD protection on microSD data line 2.

R64 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SDCD	✅	Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply.
2	2	3.3VCC	✅	Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply.

R65 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply.
2	2	MCCDA	✅	Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply.

R67 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCDA3	✅	Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply.
2	2	3.3VCC	✅	Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply.

R68 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCDA2	✅	Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply.
2	2	3.3VCC	✅	Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply.

R69 - RC0402FR-0710KP ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply.
2	2	MCDA1	✅	Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply.

R70 - RC0402FR-0710KP ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply.
2	2	MCDA0	✅	Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply.

J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header.
2	2	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
3	3	NetJ12_3	✅	Signal pin connected to PC2_PWML0 through 100Ω series resistor R137. The resistor provides current limiting and ESD protection for the PWM output signal.
4	4	NetJ12_4	✅	Signal pin connected to PA1_CANRX0 through 100Ω series resistor R136. The resistor provides current limiting and ESD protection for the CAN receive signal.
5	5	NetJ12_5	✅	Signal pin connected to PA16 through 100Ω series resistor R135. The resistor provides current limiting and ESD protection for the general purpose I/O signal.
6	6	NetJ12_6	✅	Signal pin connected to PA0_CANTX0 through 100Ω series resistor R134. The resistor provides current limiting and ESD protection for the CAN transmit signal.
7	7	NetJ12_7	✅	Signal pin connected to PA12_RXD1 through 100Ω series resistor R133. The resistor provides current limiting and ESD protection for the UART receive signal.
8	8	NetJ12_8	✅	Signal pin connected to PA15_CTS1 through 100Ω series resistor R120. The resistor provides current limiting and ESD protection for the UART clear-to-send signal.
9	9	NetJ12_9	✅	Signal pin connected to PA13_TXD1 through 100Ω series resistor R114. The resistor provides current limiting and ESD protection for the UART transmit signal.
10	10	NetJ12_10	✅	Signal pin connected to PA14_RTS1 through 100Ω series resistor R109. The resistor provides current limiting and ESD protection for the UART request-to-send signal.

J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

DRCY found no issues in this component 🎉

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header.
2	2	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
3	3	NetJ13_3	✅	Signal pin connected to NRST through 100Ω series resistor R145. The resistor provides current limiting and ESD protection for the reset signal.
4	4	NetJ13_4	✅	Signal pin connected to PB25_TIOA0 through 100Ω series resistor R144. The resistor provides current limiting and ESD protection for the timer I/O signal.
5	5	NetJ13_5	✅	Signal pin connected to PA26_MOSI through 100Ω series resistor R143. The resistor provides current limiting and ESD protection for the SPI master-out-slave-in signal.
6	6	NetJ13_6	✅	Signal pin connected to PA3_AD2 through 100Ω series resistor R142. The resistor provides current limiting and ESD protection for the ADC input signal.
7	7	NetJ13_7	✅	Signal pin connected to PA29_CS through 100Ω series resistor R141. The resistor provides current limiting and ESD protection for the SPI chip select signal.
8	8	NetJ13_8	✅	Signal pin connected to PB27_TIOB0 through 100Ω series resistor R140. The resistor provides current limiting and ESD protection for the timer I/O signal.
9	9	NetJ13_9	✅	Signal pin connected to PA27_SCLK through 100Ω series resistor R139. The resistor provides current limiting and ESD protection for the SPI clock signal.
10	10	NetJ13_10	✅	Signal pin connected to PA25_MISO through 100Ω series resistor R138. The resistor provides current limiting and ESD protection for the SPI master-in-slave-out signal.

J20 - Header 12X2 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA28_CS0	✅	SPI chip select signal connected directly to PA28_CS0 on microcontroller without series protection resistor.
2	2	PA27_SCLK	✅	SPI clock signal connected directly to PA27_SCLK on microcontroller without series protection resistor.
3	3	PA26_MOSI	✅	SPI MOSI signal connected directly to PA26_MOSI on microcontroller without series protection resistor.
4	4	PA25_MISO	✅	SPI MISO signal connected directly to PA25_MISO on microcontroller without series protection resistor.
5	5	unconnected-(NetJ20_5)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
6	6	unconnected-(NetJ20_6)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
7	7	unconnected-(NetJ20_7)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
9	9	unconnected-(NetJ20_9)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
10	10	unconnected-(NetJ20_10)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
11	11	unconnected-(NetJ20_11)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
12	12	unconnected-(NetJ20_12)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
13	13	unconnected-(NetJ20_13)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
14	14	unconnected-(NetJ20_14)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
17	17	unconnected-(NetJ20_17)	✅	Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector.
8	8	PB12_AD8	✅	ADC input signal connected directly to PB12_AD8 on microcontroller without series protection resistor.
15	15	NetJ20_15	✅	Ethernet transmit data signal connected to PB2_ETX0 through 100Ω series resistor R161 and protected by 6.8V varistor RV3. This provides comprehensive protection for the Ethernet signal.
16	16	NetJ20_16	✅	Ethernet transmit enable signal connected to PB1_ETXEN through 100Ω series resistor R160 and protected by 6.8V varistor RV4. This provides comprehensive protection for the Ethernet signal.
18	18	NRST	✅	Reset signal connected directly to NRST microcontroller reset signal without series protection resistor.
19	19	NetJ20_19	✅	Analog/digital I/O signal connected to PB13_AD9 through 100Ω series resistor R159 and protected by 6.8V varistor RV2. This provides comprehensive protection for the signal.
20	20	NetJ20_20	✅	Ethernet transmit clock signal connected to PB0_ETXCK through 100Ω series resistor R153 and protected by 6.8V varistor RV1. This provides comprehensive protection for the Ethernet signal.
21	21	PA18_SCL	✅	I2C clock signal connected directly to PA18_SCL on microcontroller without series protection resistor.
22	22	PA17_SDA	✅	I2C data signal connected directly to PA17_SDA on microcontroller without series protection resistor.
23	23	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
24	24	3.3VCC	✅	Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header.

J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device.
2	2	PA9_UTXD	✅	UART transmit signal connected to PA9_UTXD with ESD protection diode D72. The diode provides unidirectional ESD protection for the signal.
3	3	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header.
4	4	PA8_URXD	✅	UART receive signal connected to PA8_URXD with ESD protection diode D73. The diode provides unidirectional ESD protection for the signal.
5	5	3.3VCC	✅	Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header.
6	6	NRST	✅	Reset signal connected to NRST with ESD protection diode D71. The diode provides unidirectional ESD protection for the reset signal.
7	7	ERASE	✅	Erase signal connected to ERASE with ESD protection diode D1. The diode provides unidirectional ESD protection for the erase control signal.
8	8	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. This is a second 5V power pin on the same connector.
9	9	PC8_PWML3	✅	PWM signal connected directly to PC8_PWML3 on microcontroller without series protection resistor or ESD diode. This lacks the protection provided to other signals on this connector.
10	10	GND	✅	Ground reference pin connected to GND net. Provides ground return path for external device. This is a second ground pin on the same connector.

D71 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	NRST	✅	Cathode connected to NRST signal for ESD protection. This is correct for protecting the reset pin exposed on external connectors.

D72 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	PA9_UTXD	✅	Cathode connected to PA9_UTXD signal for ESD protection. This is correct for protecting the UART transmit pin exposed on external connector J28.

D73 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	PA8_URXD	✅	Cathode connected to PA8_URXD signal for ESD protection. This is correct for protecting the UART receive pin exposed on external connector J28.

D1 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection.
C	C	ERASE	✅	Cathode connected to ERASE signal for ESD protection. This is correct for protecting the erase pin exposed on external connector J28.

RV1 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_20	✅	Connected to NetJ20_20 which connects to PB0_ETXCK via series resistor R153. This provides bidirectional ESD protection for the Ethernet transmit clock signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

RV2 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_19	✅	Connected to NetJ20_19 which connects to PB13_AD9 via series resistor R159. This provides bidirectional ESD protection for the ADC input signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

RV3 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_15	✅	Connected to NetJ20_15 which connects to PB2_ETX0 via series resistor R161. This provides bidirectional ESD protection for the Ethernet transmit data signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

RV4 - AVRM0603C6R8NT101N ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_16	✅	Connected to NetJ20_16 which connects to PB1_ETXEN via series resistor R160. This provides bidirectional ESD protection for the Ethernet transmit enable signal.
2	2	GND	✅	Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection.

U14 - 74AVC9112 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	Vcc	3.3VCC	✅	Vcc pin correctly connected to 3.3VCC power supply. The 3.3V supply voltage is within the device's specified operating range of 0.8V to 3.6V, and proper decoupling is provided by C67 (100nF).
2	A	NetC64_2	✅	Data input A correctly connected to microcontroller SPI clock output PA27/SPI0_SPCK through source termination resistor R82 (24Ω) and filter capacitor C64. The input accepts voltages up to 3.6V and features Schmitt trigger action for noise immunity.
3	nOE	GND	✅	Output enable nOE correctly tied to GND to permanently enable all outputs. This is appropriate for a clock distribution buffer that should always be active.
4	GND	GND	✅	Ground pin correctly connected to GND.
5	Y1	NetR3_2	✅	Output Y1 correctly connected through series termination resistor R3 (47Ω) to SCLK_TCBUS. The series resistor provides impedance matching and improves signal integrity for the thermocouple bus clock signal.
6	Y2	NetR4_2	✅	Output Y2 correctly connected through series termination resistor R4 (47Ω) to PA27_SCLK, which routes to external connector J20. This provides a buffered clock output to off-board devices with proper signal termination.
7	Y3	NetR13_2	✅	Output Y3 correctly connected through series termination resistor R13 (47Ω) to SCLK_M1BUS. The series resistor provides impedance matching and improves signal integrity for the motor 1 bus clock signal.
8	Y4	NetR32_2	✅	Output Y4 correctly connected through series termination resistor R32 (47Ω) to SCLK_M2BUS. The series resistor provides impedance matching and improves signal integrity for the motor 2 bus clock signal.
23	NC		✅	NC (no connect) pin correctly left unconnected.

R3 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_TCBUS	✅	Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution.
2	2	NetR3_2	✅	Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution.

R4 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA27_SCLK	✅	Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal.
2	2	NetR4_2	✅	Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal.

R13 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_M1BUS	✅	Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution.
2	2	NetR13_2	✅	Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution.

R32 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SCLK_M2BUS	✅	Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution.
2	2	NetR32_2	✅	Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution.

U16 - SN74LVC125A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	nOE1	CS_TCBUS	✅	Output enable for buffer 1, connected to CS_TCBUS which is derived from thermocouple chip selects through diode OR gate with 10k pullup (R95).
2	A1	MISO_TCBUS	✅	Input to buffer 1, connected to MISO_TCBUS from the thermocouple SPI bus.
3	Y1	NetR94_2	✅	Output of buffer 1, connected through R94 (47R) to PA25_MISO along with outputs from buffers 2 and 3 in a wire-OR configuration.
4	nOE2	CS_M1BUS	✅	Output enable for buffer 2, connected to CS_M1BUS which is derived from motor bus 1 chip selects through diode OR gate with 10k pullup (R100).
5	A2	MISO_M1BUS	✅	Input to buffer 2, connected to MISO_M1BUS from motor bus 1 and SPI flash.
6	Y2	NetR94_2	✅	Output of buffer 2, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 3 in a wire-OR configuration.
7	GND	GND	✅	Ground pin, correctly connected to GND net.
8	Y3	NetR94_2	✅	Output of buffer 3, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 2 in a wire-OR configuration.
9	A3	MISO_M2BUS	✅	Input to buffer 3, connected to MISO_M2BUS from motor bus 2.
10	nOE3	CS_M2BUS	✅	Output enable for buffer 3, connected to CS_M2BUS which is derived from motor bus 2 chip selects through diode OR gate with 10k pullup (R97).
11	Y4	unconnected-(NetU16_11)	✅	Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality.
12	A4	GND	✅	Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality.
13	nOE4	GND	✅	Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality.
14	Vcc	3.3VCC	✅	Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor.
15	PAD	GND	✅	Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance.
23	NC		✅	No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN.

U17 - SN74LVC125A ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	nOE1	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
4	nOE2	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
10	nOE3	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
13	nOE4	GND	✅	Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application.
2	A1	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
5	A2	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
9	A3	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
12	A4	PA26_MOSI_D	✅	Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal.
3	Y1	NetR84_2	✅	Output of buffer 1, connected through R84 (47R) to MOSI_TCBUS to distribute the MOSI signal to the thermocouple bus.
6	Y2	NetR59_2	✅	Output of buffer 2, connected through R59 (47R) to MOSI_M1BUS to distribute the MOSI signal to motor bus 1.
7	GND	GND	✅	Ground pin, correctly connected to GND net.
8	Y3	NetR89_2	✅	Output of buffer 3, connected through R89 (47R) to MOSI_M2BUS to distribute the MOSI signal to motor bus 2.
11	Y4	NetR93_2	✅	Output of buffer 4, connected through R93 (47R) to PA26_MOSI to distribute the MOSI signal to an additional SPI device or connector.
14	Vcc	3.3VCC	✅	Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor.
15	PAD	GND	✅	Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance.
23	NC		✅	No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN.

R59 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M1BUS	✅	Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting.
2	2	NetR59_2	✅	Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting.

R84 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_TCBUS	✅	Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting.
2	2	NetR84_2	✅	Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting.

R89 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MOSI_M2BUS	✅	Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting.
2	2	NetR89_2	✅	Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting.

R93 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA26_MOSI	✅	Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting.
2	2	NetR93_2	✅	Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting.

R94 - 47R 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA25_MISO	✅	Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals.
2	2	NetR94_2	✅	Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals.

R77 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA26_MOSI_D	✅	Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side.
2	2	NetR77_2	✅	Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side.

R82 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC64_2	✅	Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination.
2	2	NetR82_2	✅	Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination.

R83 - CRCW040224R0FKED ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA25_MISO	✅	Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side.
2	2	NetR83_2	✅	Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side.

D5 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS4	✅	Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing.

D30 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS2	✅	Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing.

D31 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS3	✅	Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing.

D40 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS6	✅	Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing.

D41 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS7	✅	Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing.

D60 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS5	✅	Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing.

D61 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS1	✅	Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing.

D62 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing.
K	K	TC_nCS5	✅	Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing.

D63 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing.
K	K	M_nCS8	✅	Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing.

D70 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS1	✅	Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing.

D74 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS2	✅	Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing.

D75 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS3	✅	Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing.

D76 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing.
K	K	M_nCS4	✅	Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing.

R95 - 10k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active.
2	2	CS_TCBUS	✅	Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active.

R97 - 10k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active.
2	2	CS_M2BUS	✅	Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active.

R100 - 10k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VCC	✅	Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active.
2	2	CS_M1BUS	✅	Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active.

S1 - 1571610-2 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	RESET	✅	Pin 1 connects to the RESET net, which is the JTAG reset signal. When the button is pressed, it pulls RESET to ground. The RESET net lacks a pull-up resistor on the target board, but this is acceptable for JTAG applications where the external programmer typically provides the pull-up.
2	S	GND	✅	Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability.
3	3	GND	✅	Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability.
4	4	GND	✅	Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability.

S2 - KMR741NG ULC LFS ✅

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Pin Designator	Net	Correct?	Analysis
1	3.3VCC	✅	Pin 1 is correctly connected to 3.3VCC, providing the high voltage source for the ERASE signal when the button is pressed.
2	unconnected-(NetS2_2)	✅	Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability.
4	unconnected-(NetS2_4)	✅	Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability.
3	ERASE	✅	Pin 3 is correctly connected to the ERASE net. When the button is pressed, ERASE is pulled high to 3.3VCC through pin 1.

C40 - GRM155R71H103JA88D ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESET	✅	Pin 1 is correctly connected to the RESET net to provide filtering and debouncing for the JTAG reset signal.
2	2	3.3VIO	✅	Pin 2 is correctly connected to 3.3VIO. This provides filtering referenced to the I/O voltage rail, which is an acceptable design choice though less common than connecting to ground.

D24 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD24_A	✅	LED anode correctly connected to current limiting resistor R34. The LED is driven by microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0) through a 1kΩ resistor, providing approximately 1.1mA forward current.
C	C	GND	✅	LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high.

D25 - 5988140107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD25_A	✅	LED anode correctly connected to current limiting resistor R36. The LED is driven by microcontroller GPIO LED_Y (U11A pin 55, PC1) through a 1kΩ resistor, providing approximately 1.3mA forward current.
C	C	GND	✅	LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high.

R34 - RK73H1ETTP1001F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LED_R	✅	Resistor connected to microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0). This is the input side of the current limiting resistor for the red LED.
2	2	NetD24_A	✅	Resistor connected to red LED anode (D24 pin A). This is the output side of the current limiting resistor, providing approximately 1.1mA to the LED.

R36 - RK73H1ETTP1001F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LED_Y	✅	Resistor connected to microcontroller GPIO LED_Y (U11A pin 55, PC1). This is the input side of the current limiting resistor for the yellow LED.
2	2	NetD25_A	✅	Resistor connected to yellow LED anode (D25 pin A). This is the output side of the current limiting resistor, providing approximately 1.3mA to the LED.

D44 - ESD9X3.3ST5G ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD protection of the 3.3VCC power rail. This is the correct connection for an ESD protection diode.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail for ESD protection. This is the correct connection for protecting the 3.3V power supply from ESD events.

D45 - DF2S6.8FS,L3M ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND for ESD protection of the +5VCC power rail. This is the correct connection for an ESD protection diode.
K	K	+5VCC	✅	Cathode connected to +5VCC rail for ESD protection. This is the correct connection for protecting the 5V power supply from bidirectional ESD events.

R40 - 1k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Connected to 3.3VIO power rail to provide pull-up voltage for I2C SDA line.
2	2	PA17_SDA	✅	Connected to PA17_SDA (I2C data line) from microcontroller pin 9 and external header J20 pin 22.

R71 - 1k 1% 0402 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	3.3VIO	✅	Connected to 3.3VIO power rail to provide pull-up voltage for I2C SCL line.
2	2	PA18_SCL	✅	Connected to PA18_SCL (I2C clock line) from microcontroller pin 70 and external header J20 pin 21.

Q12A - NCV8402AD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Source 1 is correctly connected to GND for low-side switching operation.
2	G	NetQ12_2	✅	Gate 1 is correctly driven through a 100Ω series resistor from buffer U2D output, controlling Fan 1 switching.
7	D	NetC154_2	✅	Drain 1 is correctly connected to switch the Fan 1 load and LED1 indicator.

Q12B - NCV8402AD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
3	S	GND	✅	Source 2 is correctly connected to GND for low-side switching operation.
4	G	NetQ12_4	✅	Gate 2 is correctly driven through a 100Ω series resistor from buffer U2C output, controlling Fan 2 switching.
5	D	NetC153_2	✅	Drain 2 is correctly connected to switch the Fan 2 load and LED2 indicator.

Q13A - NCV8402AD ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Source 1 is correctly connected to GND for low-side switching operation.
2	G	NetQ13_2	✅	Gate 1 is correctly driven through a 100Ω series resistor from buffer U2B output, controlling Fan 3 switching.
7	D	NetC211_2	✅	Drain 1 is correctly connected to switch the Fan 3 load and LED3 indicator.

Q13B - NCV8402AD ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
5	D	VFAN	❌	Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on. Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet NCV8402ADDR2G, page 1) Pin 5 is connected to the VFAN net (from schematic) VFAN is the positive power supply rail for the fans (from schematic) In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning) The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic) Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic) Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic) Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic) J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic) J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic) With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning) LED4 cathode is connected to VFAN (from schematic) LED4 anode connects through R14 to VFAN (from schematic) With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning) C209 has both pins connected to VFAN, providing no filtering function (from schematic) When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet NCV8402ADDR2G, page 3) This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet NCV8402ADDR2G, page 3) The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet NCV8402ADDR2G, page 3) This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning) The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet NCV8402ADDR2G, page 1) Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning) This connection error makes the Fan 4 control circuit completely non-functional (reasoning)
3	S	GND	✅	Source 2 is correctly connected to GND for low-side switching operation.
4	G	NetQ13_4	✅	Gate 2 is correctly driven through a 100Ω series resistor from buffer U2A output, controlling Fan 4 switching.

U2A - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
1	1OE	GND	✅	Output enable (1OE) is tied directly to GND, permanently enabling gate 1. This is functionally correct for this always-on fan control application, though it differs from the datasheet recommendation to use a pullup resistor to VCC for high-impedance state during power transitions.
2	1A	Fan4	✅	Input (1A) is connected to Fan4 control signal with a 10K pulldown resistor (R101) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
3	1Y	NetR181_1	✅	Output (1Y) drives a 100R gate resistor (R181) which controls the gate of MOSFET driver Q13B. This is standard practice for MOSFET gate drive circuits to limit inrush current and reduce ringing.

U2B - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
4	2OE	GND	✅	Output enable (2OE) is tied directly to GND, permanently enabling gate 2. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers.
5	2A	Fan3	✅	Input (2A) is connected to Fan3 control signal with a 10K pulldown resistor (R171) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
6	2Y	NetR180_1	✅	Output (2Y) drives a 100R gate resistor (R180) which controls the gate of MOSFET driver Q13A. This is standard practice for MOSFET gate drive circuits.

U2C - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
8	3Y	NetR99_1	✅	Output (3Y) drives a 100R gate resistor (R99) which controls the gate of MOSFET driver Q12B. This is standard practice for MOSFET gate drive circuits.
9	3A	FAN2	✅	Input (3A) is connected to FAN2 control signal with a 10K pulldown resistor (R182) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
10	3OE	GND	✅	Output enable (3OE) is tied directly to GND, permanently enabling gate 3. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers.

U2D - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
11	4Y	NetR98_1	✅	Output (4Y) drives a 100R gate resistor (R98) which controls the gate of MOSFET driver Q12A. This is standard practice for MOSFET gate drive circuits.
12	4A	FAN1	✅	Input (4A) is connected to FAN1 control signal with a 10K pulldown resistor (R183) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs.
13	4OE	GND	✅	Output enable (4OE) is tied directly to GND, permanently enabling gate 4. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers.

U2E - SN74AHCT125 ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
7	GND	GND	✅	Ground pin is correctly connected to the GND net.
14	VCC	+5VCC	✅	Power supply pin is correctly connected to +5VCC with a 100nF bypass capacitor (C92) nearby, meeting datasheet recommendations for decoupling.
15	PAD	SNTP1	✅	Exposed thermal pad (PAD) is connected to net SNTP1. The text label 'SNTP1' near the component suggests this connection is intentional. For optimal thermal performance, this pad should be connected to ground. Verify that SNTP1 is properly connected to ground elsewhere in the design for adequate thermal dissipation.

D50 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD50_A	✅	Anode connected to NetD50_A, forming the upper clamp for the TACH_1 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D51 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD51_A	✅	Anode connected to NetD51_A, forming the upper clamp for the TACH_2 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D52 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct.
K	K	NetD50_A	✅	Cathode connected to NetD50_A, completing the lower clamping path for TACH_1 signal protection. This connection is correct.

D53 - BAT54WX ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	unconnected-(NetD53_A)	❌	Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels. Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected (from schematic) D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp (reasoning) All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND (from schematic) The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) (reasoning) Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients (reasoning) The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits (reasoning) D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 (reasoning)
K	K	NetD51_A	✅	Cathode connected to NetD51_A, which is the correct connection for a lower clamp diode. However, the diode is non-functional because pin A is unconnected.

D54 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD54_A	✅	Anode connected to NetD54_A, forming the upper clamp for the TACH_3 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D55 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD55_A	✅	Anode connected to NetD55_A, forming the upper clamp for the TACH_4 signal protection circuit. This connection is correct.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct.

D56 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct.
K	K	NetD54_A	✅	Cathode connected to NetD54_A, completing the lower clamping path for TACH_3 signal protection. This connection is correct.

D57 - BAT54WX ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct.
K	K	NetD55_A	✅	Cathode connected to NetD55_A, completing the lower clamping path for TACH_4 signal protection. This connection is correct.

LED1 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED1_A	✅	Anode is correctly connected through current limiting resistor R96 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit.
C	C	NetC154_2	✅	Cathode is correctly connected to the drain of low-side MOSFET driver Q12A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated.

LED2 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED2_A	✅	Anode is correctly connected through current limiting resistor R12 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit.
C	C	NetC153_2	✅	Cathode is correctly connected to the drain of low-side MOSFET driver Q12B (pin 5), which switches the LED on/off by pulling the cathode to ground when activated.

LED3 - 5988110107F ✅

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Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED3_A	✅	Anode is correctly connected through current limiting resistor R15 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit.
C	C	NetC211_2	✅	Cathode is correctly connected to the drain of low-side MOSFET driver Q13A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated.

LED4 - 5988110107F ❌

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Pin Designator	Pin Name	Net	Correct?	Analysis
C	C	VFAN	❌	Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3. Pin C (Cathode) is connected directly to net VFAN (from schematic) Pin C is the Cathode connection per the datasheet (from datasheet 5988110107F) The anode is connected to VFAN through R14, making both terminals at the same potential (from schematic) For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop (from datasheet 5988110107F) With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow (reasoning) LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) (from schematic) Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern (from schematic) J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets (from schematic) The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated (reasoning) This error prevents LED4 from functioning as a fan status indicator (reasoning)
A	A	NetLED4_A	✅	Anode is connected through current limiting resistor R14 (4.7K) to VFAN power rail. While this connection topology is correct, the LED cannot function because the cathode is also connected to VFAN, creating zero voltage difference across the LED.

J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC154_2	✅	Pin 1 is correctly connected to the switched ground output (NetC154_2) for Fan 1, implementing low-side PWM control where the MOSFET switches the ground return path.
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan.
3	S	NetJ29_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ29_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor.

J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC153_2	✅	Pin 1 is correctly connected to the switched ground output (NetC153_2) for Fan 2, implementing low-side PWM control where the MOSFET switches the ground return path.
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan.
3	S	NetJ22_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ22_3) with proper signal conditioning including pull-up resistor, series resistors, upper clamp diode, and filtering capacitor. Note that the lower clamp diode D53 has an unconnected anode, which reduces protection against negative transients but should not prevent normal operation.

J31 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC211_2	✅	Pin 1 is correctly connected to the switched ground output (NetC211_2) for Fan 3, implementing low-side PWM control where the MOSFET switches the ground return path.
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan.
3	S	NetJ31_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ31_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor.

J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	VFAN	❌	Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor. Pin 1 is connected to net VFAN (from schematic) Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net (from schematic) Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 (from schematic) For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) (from schematic) Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 (from schematic) Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively (from schematic) LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 (from schematic) Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output (from schematic) The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference (from schematic) In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path (reasoning) Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate (reasoning) With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation (reasoning) Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits (reasoning)
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN, providing the power supply voltage. However, the fan cannot operate due to the error on pin 1 which prevents the ground return path.
3	S	NetJ30_3	✅	Pin 3 is correctly connected to the tachometer signal path (NetJ30_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. The tachometer circuit is correctly implemented, though the fan may not operate due to the error on pin 1.

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_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 144 component(s) to review, and found 6 potential issue(s) in 8 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. > [!WARNING] > At least one netlist for this review was generated from a PCB layout file. If > the PCB is out of sync with the schematic, the analysis may be inaccurate. > Please ensure your PCB is up to date before relying on these results. <details> <summary>Component Details</summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary>U1 - TPS54531 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftps54531) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TPS54531DDAR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | VIN | VPWR | ❌ | <details><summary>VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="50.79,50.95,58.29,58.45" aspect-ratio="1.29" } <ul><li>Pin 2 (VIN) is connected to net VPWR (from schematic)</li><li>VPWR is the main power input rail derived from VPWR_IN through fuse F2 (from schematic)</li><li>This pin is the 3.5- to 28-V input supply voltage (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=3">TPS54531DDAR</a>, page 3)</li><li>Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14">TPS54531DDAR</a>, page 14)</li><li>Input decoupling capacitor of 10μF is recommended per datasheet (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=1">TPS54531DDAR</a>, page 1)</li><li>C71 is a 10nF capacitor on VPWR (from schematic)</li><li>C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total (from schematic)</li><li>Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF (reasoning)</li><li>Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response (reasoning)</li><li>A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) (reasoning)</li></ul></details> | | 1 | BOOT | NetC1_1 | ✅ | BOOT pin correctly connected to bootstrap capacitor C1 (100nF) between BOOT and PH pins as required by datasheet. | | 3 | EN | NetR2_2 | ✅ | EN pin correctly configured with UVLO resistor divider (R11=10k, R2=1.4k) and connected to protection circuits (U19 nALERT, U21 and U6 comparator outputs) for enable/disable control. | | 4 | SS | NetC171_2 | ✅ | SS pin correctly connected to soft-start capacitor C171 (10nF) to ground. | | 5 | VSNS | NetC3_1 | ✅ | VSENSE pin correctly connected to feedback resistor divider (R1=10.2k, R5=1.96k) that sets output voltage to approximately 5V. | | 6 | COMP | NetC150_2 | ✅ | COMP pin correctly connected to compensation network consisting of R10 (37.4k), C150 (2.2nF), and C151 (22pF) for loop stability. | | 7 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 8 | PH | NetC1_2 | ✅ | PH pin correctly connected to switching node with inductor L1, catch diode D2, and bootstrap capacitor C1. | | 9 | PAD | GND | ✅ | PowerPAD correctly connected to ground as required by datasheet. | </details> <details> <summary>L1 - 4.7uH 10A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.bourns.com/docs/Product-Datasheets/SRP1038A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SRP1038A-4R7M) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC1_2 | ✅ | Inductor input correctly connected to PH switching node of U1. | | 2 | 2 | NetC3_2 | ✅ | Inductor output correctly connected to converter output (NetC3_2) before current sense resistor R148. | </details> <details> <summary>D2 - SK54B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/SK52B-L_SK520B-L%28SMB%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SK54B-LTP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode correctly connected to ground for proper catch diode operation. | | K | CATHODE | NetC1_2 | ✅ | Cathode correctly connected to PH switching node for freewheeling current path. | </details> <details> <summary>R148 - 0.01R 1% 0805 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.susumu.co.jp/common/pdf/n_catalog_partition09_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/KRL1220E-M-R010-F-T5) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC3_2 | ✅ | Current sense resistor input correctly connected to buck converter output (NetC3_2). | | 2 | 2 | +5VCC | ✅ | Current sense resistor output correctly connected to +5VCC rail. However, the calculated current limit threshold is approximately 6A, which does not match the schematic note stating '~4A' current limiting. The discrepancy may be intentional to provide margin above the 5A rated output, or the note may be outdated. | </details> <details> <summary>U8 - MIC5353-3.3YMT-TR ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MIC5353-3.3YMT-TR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | EN | +5VCC | ✅ | EN pin is connected to +5VCC, configuring the regulator for always-on operation whenever input power is present. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground plane. | | 3 | VIN | +5VCC | ✅ | VIN pin is connected to +5VCC with adequate input voltage headroom and proper input decoupling. | | 4 | VOUT | 3.3VCC | ✅ | VOUT pin provides the regulated 3.3V output with adequate output capacitance for stability. | | 5 | ADJ | unconnected-(NetU8_5) | ✅ | ADJ pin is left unconnected, which is appropriate for the fixed 3.3V output version of the MIC5353. | | 6 | BYP | NetC26_1 | ✅ | BYP pin has a 100nF bypass capacitor C26 connected to ground for internal reference and error amplifier stability. | | 7 | PAD | GND | ✅ | PAD (thermal pad) is correctly connected to ground for thermal management and heat dissipation. | </details> <details> <summary>U20 - 78L05 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/L78L05ABUTR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | OUT | 5V0_AUX | ✅ | Output pin correctly connected to 5V0_AUX net, providing regulated 5V to power the current limiting comparator U19 and associated reference circuitry. Output is properly decoupled with capacitors C200 and C201. | | 2 | GND | GND | ✅ | Ground pin correctly connected to the circuit ground reference. | | 3 | IN | VPWR | ✅ | Input pin correctly connected to VPWR rail (12-24VDC), which is within the 78L05's operating range of 7V minimum to 30V maximum. Input is properly protected with TVS diode and adequately decoupled. | </details> <details> <summary>U19 - INA381_ALT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/INA381A2IDSGR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN+ | NetC3_2 | ✅ | IN+ is correctly connected to NetC3_2, the high side of current sense resistor R148, enabling high-side current sensing of the +5VCC rail. | | 2 | Vs | 5V0_AUX | ✅ | Vs is correctly powered from 5V0_AUX, an independent auxiliary 5V supply from the 78L05 LDO (U20), with proper decoupling capacitors C200 and C201. | | 3 | nALERT | NetR2_2 | ✅ | nALERT is correctly connected to NetR2_2, which drives the EN pin of the TPS54531 buck converter (U1 pin 3), implementing overcurrent protection by disabling the +5V regulator when current limit is exceeded. | | 4 | RESET | NetR102_1 | ✅ | RESET is correctly pulled high to 5V0_AUX through R102 (1k), configuring the INA381 in latching mode as indicated by schematic notes. | | 5 | CMPREF | NetR115_1 | ✅ | CMPREF is connected to a voltage divider (R115=15k, R119=4.7k) that sets the comparator reference threshold to approximately 1.19V. The design intent is clear, but without the INA381A2IDSGR datasheet to confirm the internal gain, the actual current limit threshold cannot be definitively verified against the stated ~4A specification. | | 6 | CMPIN | NetU19_6 | ✅ | CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF. | | 7 | VOUT | NetU19_6 | ✅ | CMPIN and VOUT are correctly connected together on net NetU19_6, implementing the standard INA381 configuration where the amplified differential voltage is fed directly to the comparator input for comparison against CMPREF. | | 8 | IN- | +5VCC | ✅ | IN- is correctly connected to +5VCC, the low side of current sense resistor R148, enabling differential measurement of the voltage drop across the sense resistor. | | 9 | GND | GND | ✅ | GND is correctly connected to the ground plane, providing the ground reference for the device. | </details> <details> <summary>U21 - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP331A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AP331AWG-7) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR157_1 | ✅ | IN- (inverting input) is correctly connected to a reference voltage divider creating approximately 2.17V from 5V0_AUX through R157 (130k) and R158 (100k), providing the threshold for the under-voltage lockout circuit. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the comparator. | | 3 | IN+ | NetR154_2 | ✅ | IN+ (non-inverting input) is correctly connected to monitor the VMOTA voltage through a voltage divider (R154=24k, R155=10k) with positive feedback through R156 (1M) for hysteresis, creating an under-voltage lockout threshold of approximately 7.38V. | | 4 | OUT | NetR2_2 | ✅ | OUT (open collector output) is correctly configured with pull-up resistor R11 (10k to VPWR) and pull-down resistor R2 (1.4k to GND), forming a wired-OR with other protection circuits (U6, U19) to control the enable pin of buck regulator U1. Note that the voltage divider creates a high-level voltage of approximately 1.47V at VPWR=12V and 2.95V at VPWR=24V, which provides limited margin at the lower end of the VPWR range. | | 5 | VCC | VPWR | ✅ | VCC pin is correctly connected to VPWR, which provides power to the comparator within the specified 12-24VDC range and meets the datasheet's +2 to +36V single supply requirement. | </details> <details> <summary>U6 - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP331A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AP331AWG-7) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR57_1 | ✅ | IN- (inverting input) is connected to a reference voltage divider from 5V0_AUX through R57 (130k) and R58 (100k) to GND, setting a reference threshold of approximately 2.17V for under-voltage detection. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the comparator. | | 3 | IN+ | NetR26_2 | ✅ | IN+ (non-inverting input) monitors VMOTE voltage through a divider formed by R26 (24k) and R56 (10k), with positive feedback hysteresis provided by R28 (1M) from the output to prevent oscillation. | | 4 | OUT | NetR2_2 | ✅ | OUT (open-collector output) is wire-OR'd with other fault detectors on net NetR2_2, which controls the enable pin of buck regulator U1. The output is pulled up through R11 (10k) to VPWR and has R2 (1.4k) to GND forming a voltage divider. | | 5 | VCC | VPWR | ✅ | VCC pin is correctly connected to VPWR, providing power supply to the comparator within its specified operating range of 2-36V. | </details> <details> <summary>F1 - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.keyelco.com/userAssets/file/K75p47.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-20) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED_IN | ✅ | Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity. | | 2 | 2 | VBED | ✅ | Fuse holder connecting VBED_IN (pin 1) to VBED (pin 2) for heated bed power protection. Both pins are passive contacts with no polarity. | </details> <details> <summary>F2 - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-2) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR_IN | ✅ | Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity. | | 2 | 2 | VPWR | ✅ | Fuse holder connecting VPWR_IN (pin 1) to VPWR (pin 2) for main power rail protection. Both pins are passive contacts with no polarity. | </details> <details> <summary>D43 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection. | | K | K | VMOTA | ✅ | TVS diode correctly connected to protect VMOTA power rail. Anode connected to GND, cathode connected to VMOTA, providing proper transient overvoltage protection. | </details> <details> <summary>D22 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection. | | K | K | VPWR | ✅ | TVS diode correctly connected to protect VPWR power rail. Anode connected to GND, cathode connected to VPWR, providing proper transient overvoltage protection. | </details> <details> <summary>D78 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection. | | K | K | VBED | ✅ | TVS diode correctly connected to protect VBED power rail. Anode connected to GND, cathode connected to VBED, providing proper transient overvoltage protection. | </details> <details> <summary>D21 - SMAJ24A ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | VMOTE | ❌ | <details><summary>TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="2.64,54.95,10.14,62.45" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOTE (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic)</li><li>SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The color band on the device denotes the cathode terminal (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic)</li><li>With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning)</li><li>The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning)</li><li>This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning)</li><li>The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)</li></ul></details> | | K | K | GND | ❌ | <details><summary>TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="2.64,56.13,10.14,63.63" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOTE (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic)</li><li>SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The color band on the device denotes the cathode terminal (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic)</li><li>With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning)</li><li>The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning)</li><li>This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning)</li><li>The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)</li></ul></details> | </details> <details> <summary>J3 - 10 Pos barrier ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/4DB-P108-10) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOTE | ✅ | Connected to VMOTE net, providing motor power input for motors 5-8 with proper protection and monitoring circuitry. | | 2 | 2 | GND | ✅ | Connected to GND net, providing ground reference for VMOTE power input. | | 3 | 3 | VMOTA | ✅ | Connected to VMOTA net, providing motor power input for motors 1-4 with proper protection and monitoring circuitry. | | 4 | 4 | GND | ✅ | Connected to GND net, providing ground reference for VMOTA power input. | | 5 | 5 | VPWR_IN | ✅ | Connected to VPWR_IN net, providing input power through fuse F2 to VPWR rail for fans, expansion, heaters, and logic circuits. | | 6 | 6 | GND | ✅ | Connected to GND net, providing ground reference for VPWR_IN power input. | | 7 | 7 | VBED_IN | ✅ | Connected to VBED_IN net, providing input power through fuse F1 to heated bed (VBED) rail. | | 8 | 8 | GND | ✅ | Connected to GND net, providing ground reference for VBED_IN power input. | | 9 | 9 | VBED | ✅ | Connected to VBED net, providing heated bed power output after fuse with proper protection and filtering. | | 10 | 10 | HTBD-OUT | ✅ | Connected to HTBD-OUT net, which has no other connections on this schematic page. This is likely intentional for connection on another schematic page or for external wiring. | </details> <details> <summary>P1 - Header 4X2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-08G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads. | | 3 | 3 | VFAN | ✅ | These pins provide VFAN power output, which is derived from VPWR through 0-ohm jumper resistor R103. Two pins in parallel increase current handling capability for fan and expansion loads. | | 2 | 2 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 4 | 4 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 6 | 6 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 8 | 8 | GND | ✅ | These pins are all connected to ground, providing multiple return paths for current. Four ground pins reduce inductance and improve current handling for the power distribution connector. | | 5 | 5 | VPWR | ✅ | These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution. | | 7 | 7 | VPWR | ✅ | These pins provide VPWR power output, which is the main 12-24VDC power rail after fuse F2. Two pins in parallel increase current capability for the main power distribution. | </details> <details> <summary>D23 - 5988170107F ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988170107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD23_A | ✅ | LED anode is correctly connected to 3.3VCC through current-limiting resistor R33 (1kΩ). The resulting current is approximately 1.3mA, which is low but acceptable for modern high-efficiency indicator LEDs. | | C | C | GND | ✅ | LED cathode is correctly connected to GND, providing the proper return path for LED current and completing the indicator circuit. | </details> <details> <summary>C210 - UWT1V101MCL1GS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.nichicon.co.jp/english/series_items/catalog_pdf/e-uwt.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/UWT1V101MCL1GS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED | ✅ | Positive terminal correctly connected to VBED heated bed power rail for bulk filtering and energy storage. | | 2 | 2 | GND | ✅ | Negative terminal correctly connected to GND, providing proper return path for the bulk capacitor. | </details> <details> <summary>R103 - 0R 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://bourns.com/docs/product-datasheets/cr.pdf?sfvrsn=574d41f6_14) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CR0603-J_-000ELF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | 0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail. | | 2 | 2 | VFAN | ✅ | 0-ohm jumper connecting VPWR to VFAN power rail. Pin 1 connects to VPWR (main power rail), and pin 2 connects to VFAN (fan power distribution). This provides design flexibility to power fans from the main VPWR rail. | </details> <details> <summary>J8 - USB-B ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/61729-0010BLF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS | NetC43_2 | ✅ | VBUS pin correctly connected to ESD protection and power filtering network before reaching the USB isolator. | | 2 | DM | DM | ✅ | DM (D-) pin correctly connected to ESD protection device D27 pin 1 (I/O1) for the USB D- data line. | | 3 | DP | DP | ✅ | DP (D+) pin correctly connected to ESD protection device D27 pin 3 (I/O2) for the USB D+ data line. | | 4 | GND | USB_GND | ✅ | GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier. | | 5 | SHLD | USB_GND | ✅ | GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier. | | 6 | SHLD | USB_GND | ✅ | GND and shield pins correctly connected to USB_GND, which is the isolated ground domain for the USB side of the isolation barrier. | </details> <details> <summary>D27 - PRTR5V0U2F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2F_PRTR5V0U2K.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/PRTR5V0U2F,115) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | DM | ✅ | I/O1 pin correctly connected to DM (D-) from USB connector J8 pin 2. | | 2 | | USB_GND | ✅ | GND pin correctly connected to USB_GND, providing ground reference for the ESD protection device. | | 3 | | DP | ✅ | I/O2 pin correctly connected to DP (D+) from USB connector J8 pin 3. | | 4 | | NetD27_4 | ✅ | I/O2 pin correctly connected through common mode choke L5 to the D+ signal path (UD_P). | | 5 | | NetC43_2 | ✅ | VCC pin correctly connected to VBUS (NetC43_2) for rail-to-rail ESD protection. | | 6 | | NetD27_6 | ✅ | I/O1 pin correctly connected through common mode choke L5 to the D- signal path (UD_N). | </details> <details> <summary>L5 - DLW21HN900SQ2L ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/commonModeChokeCoilCommonModeNoiseFilter/EFLC0005_PDF_COMMONMODECHOKECOILCOMMONMODENOISEFILTER?lastModifiedDatetime=20250707191631) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DLW21HN900SQ2L) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | NetL5_1 | ✅ | Common mode choke terminal correctly connected through R46 (24Ω) to UD_P, completing the D+ signal path. | | 2 | | NetD27_4 | ✅ | Common mode choke terminal correctly connected to D27 pin 4 (I/O2), receiving the D+ signal from ESD protection. | | 3 | | NetD27_6 | ✅ | Common mode choke terminal correctly connected to D27 pin 6 (I/O1), receiving the D- signal from ESD protection. | | 4 | | NetL5_4 | ✅ | Common mode choke terminal correctly connected through R43 (24Ω) to UD_N, completing the D- signal path. | </details> <details> <summary>D26 - RSB39VTE-17 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RSB39VTE-17) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier. | | C | C | USB_GND | ✅ | TVS diode correctly connected between isolated ground domains (anode to GND, cathode to USB_GND) to provide ESD protection across the isolation barrier. | </details> <details> <summary>U9 - ADuM4160 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM3160.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ADUM3160BRWZ-RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS1 | VUSB | ✅ | VBUS1 is correctly connected to VUSB, which provides USB bus voltage (5V) to power the upstream side of the isolator with proper bypass capacitors. | | 2 | GND1 | USB_GND | ✅ | GND1 is correctly connected to USB_GND, providing the isolated ground reference for the upstream side of the isolator. | | 3 | VDD1 | VDD1 | ✅ | VDD1 is correctly connected to the internal 3.3V regulator output with proper bypass capacitor and provides pull-up voltage for PDEN and SPU configuration pins. | | 4 | PDEN | VDD1 | ✅ | PDEN is correctly tied to VDD1 for standard operation with pull-down resistors enabled. | | 5 | SPU | VDD1 | ✅ | SPU is correctly tied to VDD1 to select full speed operation on the upstream buffer, matching the SPD pin configuration. | | 6 | UD- 1 | UD_N | ✅ | UD- (Upstream D-) is correctly connected through 24Ω series termination resistor R43 to the USB connector via common mode choke L5. | | 7 | UD+ 1 | UD_P | ✅ | UD+ (Upstream D+) is correctly connected through 24Ω series termination resistor R46 to the USB connector via common mode choke L5. | | 8 | GND1 | USB_GND | ✅ | GND1 is correctly connected to USB_GND, matching pin 2 as required by the datasheet. | | 9 | GND2 | GND | ✅ | GND2 is correctly connected to the main system ground (GND), providing ground reference for the downstream side of the isolator. | | 10 | UD+ 2 | UI_P | ✅ | DD+ (Downstream D+) is correctly connected through 24Ω series termination resistor R47 to the microcontroller USB D+ pin. | | 11 | UD- 2 | UI_N | ✅ | DD- (Downstream D-) is correctly connected through 24Ω series termination resistor R45 to the microcontroller USB D- pin. | | 12 | PIN | 3.3VCC | ✅ | PIN is correctly tied to 3.3VCC to enable the upstream pull-up resistor for immediate USB enumeration on power-up. | | 13 | SPD | 3.3VCC | ✅ | SPD is correctly tied to 3.3VCC to select full speed operation on the downstream buffer, matching the SPU pin configuration. | | 14 | VDD2 | +3.3VCC | ✅ | VDD2 is correctly connected to +3.3VCC along with VBUS2 for 3.3V operation with proper bypass capacitors present. | | 15 | GND2 | GND | ✅ | GND2 is correctly connected to the main system ground (GND), matching pin 9 as required by the datasheet. | | 16 | VBUS2 | +3.3VCC | ✅ | VBUS2 is correctly connected to +3.3VCC along with VDD2 for 3.3V operation on the downstream side. | </details> <details> <summary>R43 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_N | ✅ | R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector. | | 2 | 2 | NetL5_4 | ✅ | R43 provides the required 24Ω series termination for the upstream USB D- line between the isolator and the USB connector. | </details> <details> <summary>R46 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_P | ✅ | R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector. | | 2 | 2 | NetL5_1 | ✅ | R46 provides the required 24Ω series termination for the upstream USB D+ line between the isolator and the USB connector. | </details> <details> <summary>R45 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_N | ✅ | R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator. | | 2 | 2 | UI_N | ✅ | R45 provides the required 24Ω series termination for the downstream USB D- line between the microcontroller and the isolator. | </details> <details> <summary>R47 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_P | ✅ | R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator. | | 2 | 2 | UI_P | ✅ | R47 provides the required 24Ω series termination for the downstream USB D+ line between the microcontroller and the isolator. | </details> <details> <summary>U11B - ATML-ATSAM3X-LQFP-144 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 35 | XOUT | NetC41_2 | ✅ | XOUT pin correctly connected to 12MHz crystal X1 pin 3 through load capacitor C41 (3pF to ground). Standard crystal oscillator output configuration. | | 36 | XIN | NetC42_2 | ✅ | XIN pin correctly connected to 12MHz crystal X1 pin 1 through load capacitor C42 (3pF to ground). Standard crystal oscillator input configuration. | | 37 | DHSDP | UMCU_P | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 38 | DHSDM | UMCU_N | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 42 | DFSDP | NetR48_1 | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 43 | DFSDM | NetR42_1 | ✅ | USB data pins are incorrectly connected. Both DHSDP/DHSDM (pins 37/38) and DFSDP/DFSDM (pins 42/43) are connected to the same external USB signals UMCU_P/UMCU_N through series resistors. The ATSAM3X8EA has two separate USB device controllers (UDP and UDPHS) that should not be connected to the same external signals simultaneously. | | 39 | VBUS | VBUS_UC | ✅ | VBUS pin correctly connected to VBUS_UC net with optoisolator-based detection circuit that senses USB power presence across the isolation barrier. | | 40 | VBG | NetC49_1 | ✅ | VBG pin connected to 10pF capacitor C49 and 6.8K resistor R49 to ground. The 10pF capacitor provides filtering for the bandgap reference, but the 6.8K resistor to ground is unusual and should be verified against the ATSAM3X8EA datasheet. | | 46 | JTAGSEL | GND | ✅ | JTAGSEL pin correctly tied to GND to select debug interface mode. | | 47 | NRSTB | RESET | ✅ | NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection. | | 69 | NRST | NetC169_1 | ✅ | NRSTB (pin 47) and NRST (pin 69) are connected together through 100 ohm series resistor R149 with 100nF bypass capacitor C169 on NRST. This provides reset signal filtering and protection. | | 48 | XIN32 | XIN32 | ✅ | XIN32 pin connected to net XIN32 for 32.768 kHz RTC crystal input. The crystal connection is not visible on this schematic page. | | 49 | XOUT32 | XOUT32 | ✅ | XOUT32 pin connected to net XOUT32 for 32.768 kHz RTC crystal output. The crystal connection is not visible on this schematic page. | | 50 | SHDN | SHDN | ✅ | SHDN pin connected to net SHDN as a shutdown output signal. | | 51 | TST | GND | ✅ | TST pin correctly tied to GND as test pins are typically grounded when not in use. | | 53 | FWUP | NetR51_1 | ✅ | FWUP pin correctly pulled up to +3.3VCC through 100K resistor R51 to disable firmware update mode by default. | | 75 | ADVREF | VDDANA | ✅ | ADVREF pin correctly connected to VDDANA with appropriate bypass capacitors C76 (100nF) and C77 (10nF) for analog reference voltage filtering. | </details> <details> <summary>X1 - 405C35B12M00000 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/405C35B12M00000) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | C1 | NetC42_2 | ✅ | Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified. | | 3 | C2 | NetC41_2 | ✅ | Crystal pins C1 and C2 connected to microcontroller XIN and XOUT through 3pF load capacitors. The 3pF capacitors are significantly smaller than the calculated requirement for the crystal's 13pF load capacitance specification. This configuration may work if the ATSAM3X8EA has sufficient internal programmable load capacitors, but should be verified. | | 2 | GND | GND | ✅ | Crystal ground pins correctly connected to GND. | | 4 | GND | GND | ✅ | Crystal ground pins correctly connected to GND. | </details> <details> <summary>R48 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR48_1 | ✅ | 24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | | 2 | 2 | UMCU_P | ✅ | 24 ohm series resistor connected between microcontroller DFSDP pin (U11B pin 42) and UMCU_P net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | </details> <details> <summary>R42 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR42_1 | ✅ | 24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | | 2 | 2 | UMCU_N | ✅ | 24 ohm series resistor connected between microcontroller DFSDM pin (U11B pin 43) and UMCU_N net. The resistor value and placement are appropriate for USB impedance matching, but this resistor is part of an incorrect USB configuration where both USB device controllers are connected to the same external signals. | </details> <details> <summary>U18 - OPTO SO-4 OPNDRN OUT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TLP293%28TPL,E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A | NetR152_2 | ✅ | Anode of optoisolator LED, connected to VUSB through current limiting resistor R152 (1kΩ). This provides the input signal indicating USB power presence on the isolated side. | | 2 | K | USB_GND | ✅ | Cathode of optoisolator LED, correctly connected to USB_GND (isolated ground) to complete the LED circuit on the isolated side. | | 3 | E | GND | ✅ | Emitter of optoisolator output phototransistor, correctly connected to system GND on the non-isolated side to establish the reference for the output stage. | | 4 | C | NetQ8_1 | ✅ | Collector of optoisolator output phototransistor, connected to Q8 base through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. This drives the inverter stage in open-collector configuration. | </details> <details> <summary>Q8 - MMBT3904_SOT523 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MMBT3904T-7-F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B | NetQ8_1 | ✅ | Base of NPN transistor, driven by optoisolator U18 collector through net NetQ8_1 with pull-up resistor R151 (6.8kΩ) to +5VCC. Base is low when USB power present, high when absent. | | 2 | E | GND | ✅ | Emitter of NPN transistor, correctly connected to GND for common-emitter switching configuration. | | 3 | C | VBUS_UC | ✅ | Collector of NPN transistor, connected to VBUS_UC (microcontroller VBUS sense pin) with pull-up resistor R150 (6.8kΩ) to +5VCC. Provides high signal when USB power present, low when absent. | </details> <details> <summary>JP1 - SJ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged. | | 2 | 2 | VUSB | ✅ | Solder jumper connecting +5VCC (system 5V rail) to VUSB (isolated USB power rail from ADuM4160). Allows optional powering of the system from USB when bridged. | </details> <details> <summary>JP2 - SJ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation. | | 2 | 2 | USB_GND | ✅ | Solder jumper connecting GND (system ground) to USB_GND (isolated USB ground). Allows optional connection of ground planes across the isolation barrier, useful for testing or non-isolated operation. | </details> <details> <summary>FB29 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | Connected to VUSB (isolated USB power rail). This is the filtered/clean side of the ferrite bead, providing filtered power to the ADuM4160 USB isolator. | | 2 | 2 | NetC43_2 | ✅ | Connected to NetC43_2 (USB connector VBUS). This is the unfiltered/noisy side of the ferrite bead, providing EMI filtering on the incoming USB power line. | </details> <details> <summary>U11C - ATML-ATSAM3X-LQFP-144 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 45 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 61 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 104 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 124 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT, the internal voltage regulator output. | | 11 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 62 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 105 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 125 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO through ferrite bead FB28 for I/O power supply. | | 12 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 33 | GNDPLL | GND | ✅ | Ground pins correctly connected to system ground. | | 44 | GNDUTMI | GND | ✅ | Ground pins correctly connected to system ground. | | 54 | GNDBU | GND | ✅ | Ground pins correctly connected to system ground. | | 58 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 74 | GNDANA | GND | ✅ | Ground pins correctly connected to system ground. | | 106 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 126 | GND | GND | ✅ | Ground pins correctly connected to system ground. | | 34 | VDDPLL | VDDPLL | ✅ | VDDPLL is incorrectly connected to VDDOUT (1.2V) through FB26. VDDPLL requires 1.62V to 3.6V and should be connected to 3.3VCC or 3.3VIO instead. This will prevent the PLL from functioning correctly. | | 41 | VDDUTMI | VDDUTMI | ✅ | VDDUTMI correctly connected to 3.3VCC through ferrite bead FB30 for USB transceiver power supply. | | 52 | VDDBU | 3.3VCC | ✅ | VDDBU correctly connected to 3.3VCC for backup power supply. | | 56 | VDDOUT | VDDOUT | ✅ | VDDOUT correctly connected to the VDDOUT net, serving as the internal voltage regulator output. | | 57 | VDDIN | 3.3VCC | ✅ | VDDIN correctly connected to 3.3VCC as the input to the internal voltage regulator. | | 73 | VDDANA | VDDANA | ✅ | VDDANA correctly connected to 3.3VCC through ferrite bead FB27 for analog power supply. | </details> <details> <summary>U11A - ATML-ATSAM3X-LQFP-144 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 29 | PB29/TDI | TDO/SWO | ❌ | <details><summary>JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.08,54.04,35.58" aspect-ratio="1.55" } <ul><li>Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)</li><li>Pin 30 (PB30/TDO) is connected to net TDI (from schematic)</li><li>Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)</li><li>Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)</li><li>The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)</li><li>The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)</li><li>The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)</li><li>This swap will prevent JTAG debugging from functioning correctly (reasoning)</li><li>In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)</li><li>The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)</li></ul></details> | | 30 | PB30/TDO/TRACESWO | TDI | ❌ | <details><summary>JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.99,54.04,36.49" aspect-ratio="1.55" } <ul><li>Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)</li><li>Pin 30 (PB30/TDO) is connected to net TDI (from schematic)</li><li>Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)</li><li>Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)</li><li>The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)</li><li>The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)</li><li>The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)</li><li>This swap will prevent JTAG debugging from functioning correctly (reasoning)</li><li>In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)</li><li>The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)</li></ul></details> | | 1 | PB26/CTS0/TCLK0/WKUP15 | STEP6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 2 | PA9/UTXD/PWMH3 | PA9_UTXD | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 3 | PA10/RXD0/DATRG/WKUP5 | DIAG7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 4 | PA11/TXD0/ADTRG/WKUP6 | DIAG8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 5 | PA12/RXD1/PWML1/WKUP7 | PA12_RXD1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 6 | PA13/TXD1/PWMH2 | PA13_TXD1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 7 | PA14/RTS1/TK | PA14_RTS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 8 | PA15/CTS1/TF/WKUP8 | PA15_CTS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 9 | PA17/TWD0/SPCK0 | PA17_SDA | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 13 | PD0/A10/MCDA4 | M_nCS7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 14 | PD1/A11/MCDA5 | DIR8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 15 | PD2/A12/MCDA6 | M_nCS8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 16 | PD3/A13/MCDA7 | STEP8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 17 | PD4/A14/TXD3 | MIN_ES1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 18 | PD5/A15/RXD3 | MAX_ES2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 19 | PD6/A16/BA0/PWMFI2 | MIN_ES2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 20 | PD7/A17/BA1/TIOA8 | TACH_3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 21 | PD8/A21/NANDALE/TIOB8 | TACH_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 22 | PD9/A22/NANDCLE/TCLK8 | MAX_ES3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 23 | PA0/CANTX0/PWML3 | PA0_CANTX0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 24 | PA1/CANRX0/PCK0/WKUP0 | PA1_CANRX0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 25 | PA5/TIOA2/PWMFI0/WKUP2 | PA5_PWM | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 26 | PA7/TCLK2/NCS1/WKUP3 | MIN_ES3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 27 | PA8/URXD/PWMH0/WKUP4 | PA8_URXD | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 28 | PB28/TCK/SWCLK | TCK/SWDCLK | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 31 | PB31/TMS/SWDIO | TMS/SWDIO | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 32 | PD10/NWR1/NBS1 | MAX_ES1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 55 | PC1 | LED_Y | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 59 | PC2/D0/PWML0 | PC2_PWML0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 60 | PC3/D1/PWMH0 | LED_R | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 63 | PC5/D3/PWMH1 | DIAG1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 64 | PC6/D4/PWML2 | DIR1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 65 | PC7/D5/PWMH2 | STEP1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 66 | PC8/D6/PWML3 | PC8_PWML3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 67 | PC9/D7/PWMH3 | DRV_EN | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 68 | PB27/NCS3/TIOB0 | PB27_TIOB0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 70 | PA18/TWCK0/A20/WKUP9 | PA18_SCL | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 71 | PA19/MCCK/PWMH1 | MCCK | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 72 | PA20/MCCDA/PWML2 | MCCDA | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 76 | PB15/CANRX1/PWMH3/DAC0/WKUP12 | Fan3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 77 | PB16/TCLK5/PWML0/DAC1 | Fan4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 78 | PA16/SPCK1/TD/AD7 | PA16 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 79 | PA24/MCDA3/PCK1/AD6 | MCDA3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 80 | PA23/MCDA2/TCLK4/AD5 | MCDA2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 81 | PA22/MCDA1/TCLK3/AD4 | MCDA1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 82 | PA6/TIOB2/NCS0/AD3 | TC_nCS3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 83 | PA4/TCLK1/NWAIT/AD2 | M_nCS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 84 | PA3/TIOB1/PWMFI1/AD1/WKUP1 | PA3_AD2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 85 | PA2/TIOA1/NANDRDY/AD0 | TC_nCS4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 86 | PB12/TWD1/PWMH0/AD8 | PB12_AD8 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 87 | PB13/TWCK1/PWMH1/AD9 | PB13_AD9 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 88 | PB17/RF/PWML1/AD10 | TC_nCS5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 89 | PB18/RD/PWML2/AD11 | THERM_AN2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 90 | PB19/RK/PWML3/AD12 | THERM_AN1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 91 | PB20/TXD2/SPI0_NPCS1/AD13 | THERM_AN3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 92 | PB21/RXD2/SPI0_NPCS2/AD14/WKUP13 | SPIFLASH_CS | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 93 | PC11/D9/ERX2 | DIAG2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 94 | PC12/D10/ERX3 | DIR2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 95 | PC13/D11/ECOL | STEP2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 96 | PC14/D12/ERXCK | M_nCS2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 97 | PC15/D13/ETX2 | DIAG3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 98 | PC16/D14/ETX3 | DIR3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 99 | PC17/D15/ETXER | STEP3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 100 | PC18/NWR0/NWE/PWMH6 | M_nCS3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 101 | PC19/NANDOE/PWMH5 | DIAG4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 102 | PC29/A8/TIOB7 | TACH_4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 103 | PC30/A9/TCLK7 | HOLD# | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 107 | PA21/MCDA0/PWML0 | MCDA0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 108 | PA25/SPI0_MISO/A18 | NetR83_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 109 | PA26/SPI0_MOSI/A19 | NetR77_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 110 | PA27/SPI0_SPCK/A20/WKUP10 | NetR82_2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 111 | PA28/SPI0_NPCS0/PCK2/WKUP11 | PA28_CS0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 112 | PA29/SPI0_NPCS1/NRD | PA29_CS | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 113 | PB0/ETXCK/EREFCK | PB0_ETXCK | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 114 | PB1/ETXEN | PB1_ETXEN | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 115 | PB2/ETX0 | PB2_ETX0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 116 | PC4/D2/PWML1 | DIR4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 117 | PC10/D8/ECRS | STEP4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 118 | PB3/ETX1 | STEP5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 119 | PB4/ECRSDV/ERXDV | M_nCS6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 120 | PB5/ERX0 | M_nCS5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 121 | PB6/ERX1 | DIR7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 122 | PB7/ERXER | MAX_ES4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 123 | PB8/EMDC | STEP7 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 127 | PB9/EMDIO | TC_nCS2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 128 | PB10/UOTGVBOF/A18 | M_nCS4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 129 | PB11/UOTGID/A19 | SDCD | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 130 | PC0/ERASE | ERASE | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 131 | PC20/NANDWE/PWMH4 | DIAG5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 132 | PC21/A0/NBS0/PWML4 | HEAT1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 133 | PC22/A1/PWML5 | HEAT2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 134 | PC23/A2/PWML6 | HEATBED | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 135 | PC24/A3/PWML7 | HEAT3 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 136 | PC25/A4/TIOA6 | FAN2 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 137 | PC26/A5/TIOB6 | FAN1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 138 | PC27/A6/TCLK6 | TC_nCS1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 139 | PC28/A7/TIOA7 | TACH_1 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 140 | PB14/CANTX1/PWMH2 | MIN_ES4 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 141 | PB22/RTS2/PCK0 | DIR5 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 142 | PB23/CTS2/SPI0_NPCS3/WKUP14 | DIAG6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 143 | PB24/SCK2/NCS2 | DIR6 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | | 144 | PB25/RTS0/TIOA0 | PB25_TIOA0 | ✅ | All other GPIO and peripheral pins are correctly connected for their intended functions including UART, SPI, I2C, CAN, SD card interface, ADC inputs, PWM outputs, stepper motor control, endstops, diagnostic signals, and other application-specific functions. | </details> <details> <summary>FB26 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDDPLL | ✅ | Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead. | | 2 | 2 | VDDOUT | ✅ | Ferrite bead incorrectly connects VDDPLL to VDDOUT (1.2V). This is part of the same fundamental issue as U11C pin 34 - VDDPLL requires 1.62V minimum and should be connected to 3.3VCC or 3.3VIO instead. | </details> <details> <summary>FB27 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering. | | 2 | 2 | VDDANA | ✅ | Ferrite bead correctly connects 3.3VCC to VDDANA for analog power supply filtering. | </details> <details> <summary>FB28 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering. | | 2 | 2 | 3.3VCC | ✅ | Ferrite bead correctly connects 3.3VCC to 3.3VIO for I/O power supply filtering. | </details> <details> <summary>FB30 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering. | | 2 | 2 | VDDUTMI | ✅ | Ferrite bead correctly connects 3.3VCC to VDDUTMI for USB transceiver power supply filtering. | </details> <details> <summary>J4 - ARM Cortex JTAG-DEBUG Header ❌</summary> DRCY flagged 2 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://cdn.amphenol-cs.com/media/wysiwyg/files/documentation/datasheet/boardwiretoboard/bwb_minitek127_btb.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 6 | 6 | TDO/SWO | ❌ | <details><summary>TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,71.24,46.69,78.74" aspect-ratio="1.55" } <ul><li>Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic)</li><li>Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic)</li><li>Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning)</li><li>Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning)</li><li>Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)</li></ul></details> | | 8 | 8 | TDI | ❌ | <details><summary>TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,70.33,46.69,77.83" aspect-ratio="1.55" } <ul><li>Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic)</li><li>Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic)</li><li>Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)</li><li>TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning)</li><li>Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning)</li><li>Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)</li></ul></details> | | 10 | 10 | RESET | ❌ | <details><summary>Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,69.42,46.69,76.92" aspect-ratio="1.55" } <ul><li>Pin 10 is connected to the RESET net (from schematic)</li><li>The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input (from schematic)</li><li>A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 (from schematic)</li><li>Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)</li><li>The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations (reasoning)</li><li>The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions (reasoning)</li><li>Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection (reasoning)</li></ul></details> | | 1 | 1 | 3.3VCC | ✅ | VTref pin correctly connected to 3.3VCC to provide target voltage reference to the debugger. | | 2 | 2 | TMS/SWDIO | ✅ | TMS/SWDIO signal correctly connected to microcontroller pin PB31 with appropriate 100K pull-up resistor R31. | | 3 | 3 | GND | ✅ | Ground pins correctly connected to GND plane. | | 5 | 5 | GND | ✅ | Ground pins correctly connected to GND plane. | | 9 | 9 | GND | ✅ | Ground pins correctly connected to GND plane. | | 4 | 4 | TCK/SWDCLK | ✅ | TCK/SWDCLK signal correctly connected to microcontroller pin PB28 with appropriate 100K pull-up resistor R38. | | 7 | 7 | unconnected-(NetJ4_7) | ✅ | Pin 7 is correctly left unconnected, which is standard for ARM 10-pin JTAG connectors where this pin is typically used as a key pin or for optional nTRST. | </details> <details> <summary>R31 - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TMS/SWDIO | ✅ | Connected to TMS/SWDIO signal line as part of pull-up resistor configuration. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC power rail to provide pull-up voltage. | </details> <details> <summary>R37 - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TDI | ✅ | Connected to TDI signal line as part of pull-up resistor configuration. Note: Due to the TDI/TDO swap at connector J4, this resistor is actually pulling up the microcontroller's TDO pin (PB30) rather than the intended TDI pin (PB29). The resistor itself is correctly implemented; the issue originates from the incorrect routing at J4. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC power rail to provide pull-up voltage. | </details> <details> <summary>R38 - RC1005F104CS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TCK/SWDCLK | ✅ | Connected to TCK/SWDCLK signal line as part of pull-up resistor configuration. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC power rail to provide pull-up voltage. | </details> <details> <summary>U12 - AT25SF161-SSHD-T ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25sf161b-datasheet?language=en) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AT25SF161-SSHD-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPIFLASH_CS | ✅ | CS# (Chip Select) is connected to microcontroller pin PB21 and through Schottky diode D77 to the shared CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. While the datasheet recommends a direct 10k pull-up from CS to VCC, the diode OR configuration provides functionally equivalent pull-up behavior for the shared SPI bus architecture. | | 2 | SO | MISO_M1BUS | ✅ | SO (Serial Output) is correctly connected to MISO_M1BUS, which routes through tri-state buffer U16 (SN74LVC125A) to the shared MISO line PA25_MISO, preventing bus conflicts when multiple SPI devices share the bus. | | 3 | WP# | WP# | ✅ | WP# (Write Protect) is correctly pulled high to 3.3VCC through 10k resistor R85, disabling write protection and providing better noise immunity than relying solely on the internal pull-up. | | 4 | GND | GND | ✅ | GND is correctly connected to the system ground reference. | | 5 | SI/IO0 | MOSI_M1BUS | ✅ | SI (Serial Input) is correctly connected to MOSI_M1BUS, which routes through buffer U17 (SN74LVC125A) and series resistor R59 (47 ohm) from the microcontroller, providing proper drive capability and signal integrity. | | 6 | SCK | SCLK_M1BUS | ✅ | SCK (Serial Clock) is correctly connected to SCLK_M1BUS, which routes through clock buffer U14 (74AVC9112) and series resistor R13 (47 ohm), providing clean clock distribution with proper signal integrity. | | 7 | HOLD# | HOLD# | ✅ | HOLD# is connected to microcontroller GPIO pin PC30, allowing firmware control of the HOLD function or use as I/O3 for quad-SPI operation. The internal pull-up ensures proper operation when the GPIO is in high-impedance mode. | | 8 | VCC | 3.3VCC | ✅ | VCC is correctly connected to 3.3VCC, which is within the specified supply voltage range of 2.5V-3.6V or 2.7V-3.6V. | </details> <details> <summary>D77 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Anode is correctly connected to CS_M1BUS, which has a 10k pull-up resistor R100 to 3.3VCC. This is part of a diode OR configuration that enables the MISO buffer when any of the M1BUS SPI devices is selected. | | K | K | SPIFLASH_CS | ✅ | Cathode is correctly connected to SPIFLASH_CS, which connects to the CS# pin of the SPI flash and to microcontroller pin PB21. The diode allows the pull-up to raise CS# when inactive and blocks reverse current when CS# is driven low. | </details> <details> <summary>R85 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | WP# | ✅ | 10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection. | | 2 | 2 | 3.3VCC | ✅ | 10k pull-up resistor correctly connected between WP# (pin 1) and 3.3VCC (pin 2), ensuring the Write Protect pin of the SPI flash is held high to disable write protection. | </details> <details> <summary>J18 - 0475710001 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-47309-001.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0475710001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | MCDA2 | ✅ | DAT2 data line correctly connected to MCDA2 with appropriate ESD protection and pull-up resistor. | | 2 | CD/DAT3 | MCDA3 | ✅ | CD/DAT3 signal correctly connected to MCDA3 with appropriate ESD protection and pull-up resistor. | | 3 | CMD | MCCDA | ✅ | CMD command line correctly connected to MCCDA with appropriate ESD protection and pull-up resistor. | | 4 | VDD | 3.3VCC | ✅ | VDD power pin correctly connected to 3.3VCC supply with local decoupling capacitor. | | 5 | CLK | MCCK | ✅ | CLK clock line correctly connected to MCCK with ESD protection and no pull-up resistor (as required). | | 6 | VSS | GND | ✅ | VSS ground pin correctly connected to GND. | | 7 | DAT1 | MCDA0 | ✅ | DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct. | | 8 | DAT0 | MCDA1 | ✅ | DAT0 and DAT1 data lines are correctly connected. Physical pin 7 (DAT0) connects to MCDA0 and physical pin 8 (DAT1) connects to MCDA1. Note: The schematic symbol has misleading pin labels (pin 7 labeled 'DAT1', pin 8 labeled 'DAT0') that should be corrected, but the electrical connections are correct. | | 9 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 10 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 11 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 12 | CD | SDCD | ✅ | Card detect pin correctly connected to SDCD with appropriate pull-up resistor and ESD protection. | | 13 | CD/POL | GND | ✅ | Card detect polarity pin correctly tied to GND to configure active-low card detect operation. | </details> <details> <summary>D42 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on SDCD signal. | | C | C | SDCD | ✅ | Cathode correctly connected to SDCD signal for ESD protection on card detect line. | </details> <details> <summary>D64 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA1 signal. | | C | C | MCDA1 | ✅ | Cathode correctly connected to MCDA1 signal for ESD protection on microSD data line 1. | </details> <details> <summary>D65 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA0 signal. | | C | C | MCDA0 | ✅ | Cathode correctly connected to MCDA0 signal for ESD protection on microSD data line 0. | </details> <details> <summary>D66 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCCDA signal. | | C | C | MCCDA | ✅ | Cathode correctly connected to MCCDA signal for ESD protection on microSD command line. | </details> <details> <summary>D67 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCCK signal. | | C | C | MCCK | ✅ | Cathode correctly connected to MCCK signal for ESD protection on microSD clock line. | </details> <details> <summary>D68 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA3 signal. | | C | C | MCDA3 | ✅ | Cathode correctly connected to MCDA3 signal for ESD protection on microSD data line 3. | </details> <details> <summary>D69 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for uni-directional ESD protection on MCDA2 signal. | | C | C | MCDA2 | ✅ | Cathode correctly connected to MCDA2 signal for ESD protection on microSD data line 2. | </details> <details> <summary>R64 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SDCD | ✅ | Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly connected between SDCD card detect signal and 3.3VCC supply. | </details> <details> <summary>R65 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply. | | 2 | 2 | MCCDA | ✅ | Pull-up resistor correctly connected between MCCDA command line and 3.3VCC supply. | </details> <details> <summary>R67 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCDA3 | ✅ | Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA3 data line and 3.3VCC supply. | </details> <details> <summary>R68 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCDA2 | ✅ | Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA2 data line and 3.3VCC supply. | </details> <details> <summary>R69 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply. | | 2 | 2 | MCDA1 | ✅ | Pull-up resistor correctly connected between MCDA1 data line and 3.3VCC supply. | </details> <details> <summary>R70 - RC0402FR-0710KP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply. | | 2 | 2 | MCDA0 | ✅ | Pull-up resistor correctly connected between MCDA0 data line and 3.3VCC supply. | </details> <details> <summary>J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. | | 2 | 2 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 3 | 3 | NetJ12_3 | ✅ | Signal pin connected to PC2_PWML0 through 100Ω series resistor R137. The resistor provides current limiting and ESD protection for the PWM output signal. | | 4 | 4 | NetJ12_4 | ✅ | Signal pin connected to PA1_CANRX0 through 100Ω series resistor R136. The resistor provides current limiting and ESD protection for the CAN receive signal. | | 5 | 5 | NetJ12_5 | ✅ | Signal pin connected to PA16 through 100Ω series resistor R135. The resistor provides current limiting and ESD protection for the general purpose I/O signal. | | 6 | 6 | NetJ12_6 | ✅ | Signal pin connected to PA0_CANTX0 through 100Ω series resistor R134. The resistor provides current limiting and ESD protection for the CAN transmit signal. | | 7 | 7 | NetJ12_7 | ✅ | Signal pin connected to PA12_RXD1 through 100Ω series resistor R133. The resistor provides current limiting and ESD protection for the UART receive signal. | | 8 | 8 | NetJ12_8 | ✅ | Signal pin connected to PA15_CTS1 through 100Ω series resistor R120. The resistor provides current limiting and ESD protection for the UART clear-to-send signal. | | 9 | 9 | NetJ12_9 | ✅ | Signal pin connected to PA13_TXD1 through 100Ω series resistor R114. The resistor provides current limiting and ESD protection for the UART transmit signal. | | 10 | 10 | NetJ12_10 | ✅ | Signal pin connected to PA14_RTS1 through 100Ω series resistor R109. The resistor provides current limiting and ESD protection for the UART request-to-send signal. | </details> <details> <summary>J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. | | 2 | 2 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 3 | 3 | NetJ13_3 | ✅ | Signal pin connected to NRST through 100Ω series resistor R145. The resistor provides current limiting and ESD protection for the reset signal. | | 4 | 4 | NetJ13_4 | ✅ | Signal pin connected to PB25_TIOA0 through 100Ω series resistor R144. The resistor provides current limiting and ESD protection for the timer I/O signal. | | 5 | 5 | NetJ13_5 | ✅ | Signal pin connected to PA26_MOSI through 100Ω series resistor R143. The resistor provides current limiting and ESD protection for the SPI master-out-slave-in signal. | | 6 | 6 | NetJ13_6 | ✅ | Signal pin connected to PA3_AD2 through 100Ω series resistor R142. The resistor provides current limiting and ESD protection for the ADC input signal. | | 7 | 7 | NetJ13_7 | ✅ | Signal pin connected to PA29_CS through 100Ω series resistor R141. The resistor provides current limiting and ESD protection for the SPI chip select signal. | | 8 | 8 | NetJ13_8 | ✅ | Signal pin connected to PB27_TIOB0 through 100Ω series resistor R140. The resistor provides current limiting and ESD protection for the timer I/O signal. | | 9 | 9 | NetJ13_9 | ✅ | Signal pin connected to PA27_SCLK through 100Ω series resistor R139. The resistor provides current limiting and ESD protection for the SPI clock signal. | | 10 | 10 | NetJ13_10 | ✅ | Signal pin connected to PA25_MISO through 100Ω series resistor R138. The resistor provides current limiting and ESD protection for the SPI master-in-slave-out signal. | </details> <details> <summary>J20 - Header 12X2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-24G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA28_CS0 | ✅ | SPI chip select signal connected directly to PA28_CS0 on microcontroller without series protection resistor. | | 2 | 2 | PA27_SCLK | ✅ | SPI clock signal connected directly to PA27_SCLK on microcontroller without series protection resistor. | | 3 | 3 | PA26_MOSI | ✅ | SPI MOSI signal connected directly to PA26_MOSI on microcontroller without series protection resistor. | | 4 | 4 | PA25_MISO | ✅ | SPI MISO signal connected directly to PA25_MISO on microcontroller without series protection resistor. | | 5 | 5 | unconnected-(NetJ20_5) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 6 | 6 | unconnected-(NetJ20_6) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 7 | 7 | unconnected-(NetJ20_7) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 9 | 9 | unconnected-(NetJ20_9) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 10 | 10 | unconnected-(NetJ20_10) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 11 | 11 | unconnected-(NetJ20_11) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 12 | 12 | unconnected-(NetJ20_12) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 13 | 13 | unconnected-(NetJ20_13) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 14 | 14 | unconnected-(NetJ20_14) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 17 | 17 | unconnected-(NetJ20_17) | ✅ | Unconnected pins with no electrical connection. This is acceptable for unused positions on a connector. | | 8 | 8 | PB12_AD8 | ✅ | ADC input signal connected directly to PB12_AD8 on microcontroller without series protection resistor. | | 15 | 15 | NetJ20_15 | ✅ | Ethernet transmit data signal connected to PB2_ETX0 through 100Ω series resistor R161 and protected by 6.8V varistor RV3. This provides comprehensive protection for the Ethernet signal. | | 16 | 16 | NetJ20_16 | ✅ | Ethernet transmit enable signal connected to PB1_ETXEN through 100Ω series resistor R160 and protected by 6.8V varistor RV4. This provides comprehensive protection for the Ethernet signal. | | 18 | 18 | NRST | ✅ | Reset signal connected directly to NRST microcontroller reset signal without series protection resistor. | | 19 | 19 | NetJ20_19 | ✅ | Analog/digital I/O signal connected to PB13_AD9 through 100Ω series resistor R159 and protected by 6.8V varistor RV2. This provides comprehensive protection for the signal. | | 20 | 20 | NetJ20_20 | ✅ | Ethernet transmit clock signal connected to PB0_ETXCK through 100Ω series resistor R153 and protected by 6.8V varistor RV1. This provides comprehensive protection for the Ethernet signal. | | 21 | 21 | PA18_SCL | ✅ | I2C clock signal connected directly to PA18_SCL on microcontroller without series protection resistor. | | 22 | 22 | PA17_SDA | ✅ | I2C data signal connected directly to PA17_SDA on microcontroller without series protection resistor. | | 23 | 23 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 24 | 24 | 3.3VCC | ✅ | Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header. | </details> <details> <summary>J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. | | 2 | 2 | PA9_UTXD | ✅ | UART transmit signal connected to PA9_UTXD with ESD protection diode D72. The diode provides unidirectional ESD protection for the signal. | | 3 | 3 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. | | 4 | 4 | PA8_URXD | ✅ | UART receive signal connected to PA8_URXD with ESD protection diode D73. The diode provides unidirectional ESD protection for the signal. | | 5 | 5 | 3.3VCC | ✅ | Power supply pin connected to 3.3VCC rail. Provides 3.3V power to external device connected to this header. | | 6 | 6 | NRST | ✅ | Reset signal connected to NRST with ESD protection diode D71. The diode provides unidirectional ESD protection for the reset signal. | | 7 | 7 | ERASE | ✅ | Erase signal connected to ERASE with ESD protection diode D1. The diode provides unidirectional ESD protection for the erase control signal. | | 8 | 8 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external device connected to this header. This is a second 5V power pin on the same connector. | | 9 | 9 | PC8_PWML3 | ✅ | PWM signal connected directly to PC8_PWML3 on microcontroller without series protection resistor or ESD diode. This lacks the protection provided to other signals on this connector. | | 10 | 10 | GND | ✅ | Ground reference pin connected to GND net. Provides ground return path for external device. This is a second ground pin on the same connector. | </details> <details> <summary>D71 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | NRST | ✅ | Cathode connected to NRST signal for ESD protection. This is correct for protecting the reset pin exposed on external connectors. | </details> <details> <summary>D72 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | PA9_UTXD | ✅ | Cathode connected to PA9_UTXD signal for ESD protection. This is correct for protecting the UART transmit pin exposed on external connector J28. | </details> <details> <summary>D73 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | PA8_URXD | ✅ | Cathode connected to PA8_URXD signal for ESD protection. This is correct for protecting the UART receive pin exposed on external connector J28. | </details> <details> <summary>D1 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD clamping. This is the correct polarity for unidirectional ESD protection. | | C | C | ERASE | ✅ | Cathode connected to ERASE signal for ESD protection. This is correct for protecting the erase pin exposed on external connector J28. | </details> <details> <summary>RV1 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_20 | ✅ | Connected to NetJ20_20 which connects to PB0_ETXCK via series resistor R153. This provides bidirectional ESD protection for the Ethernet transmit clock signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>RV2 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_19 | ✅ | Connected to NetJ20_19 which connects to PB13_AD9 via series resistor R159. This provides bidirectional ESD protection for the ADC input signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>RV3 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_15 | ✅ | Connected to NetJ20_15 which connects to PB2_ETX0 via series resistor R161. This provides bidirectional ESD protection for the Ethernet transmit data signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>RV4 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_16 | ✅ | Connected to NetJ20_16 which connects to PB1_ETXEN via series resistor R160. This provides bidirectional ESD protection for the Ethernet transmit enable signal. | | 2 | 2 | GND | ✅ | Connected to GND for bidirectional ESD clamping. This is correct for varistor-based ESD protection. | </details> <details> <summary>U14 - 74AVC9112 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://assets.nexperia.com/documents/data-sheet/74AVC9112.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/74AVC9112GTX) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Vcc | 3.3VCC | ✅ | Vcc pin correctly connected to 3.3VCC power supply. The 3.3V supply voltage is within the device's specified operating range of 0.8V to 3.6V, and proper decoupling is provided by C67 (100nF). | | 2 | A | NetC64_2 | ✅ | Data input A correctly connected to microcontroller SPI clock output PA27/SPI0_SPCK through source termination resistor R82 (24Ω) and filter capacitor C64. The input accepts voltages up to 3.6V and features Schmitt trigger action for noise immunity. | | 3 | nOE | GND | ✅ | Output enable nOE correctly tied to GND to permanently enable all outputs. This is appropriate for a clock distribution buffer that should always be active. | | 4 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 5 | Y1 | NetR3_2 | ✅ | Output Y1 correctly connected through series termination resistor R3 (47Ω) to SCLK_TCBUS. The series resistor provides impedance matching and improves signal integrity for the thermocouple bus clock signal. | | 6 | Y2 | NetR4_2 | ✅ | Output Y2 correctly connected through series termination resistor R4 (47Ω) to PA27_SCLK, which routes to external connector J20. This provides a buffered clock output to off-board devices with proper signal termination. | | 7 | Y3 | NetR13_2 | ✅ | Output Y3 correctly connected through series termination resistor R13 (47Ω) to SCLK_M1BUS. The series resistor provides impedance matching and improves signal integrity for the motor 1 bus clock signal. | | 8 | Y4 | NetR32_2 | ✅ | Output Y4 correctly connected through series termination resistor R32 (47Ω) to SCLK_M2BUS. The series resistor provides impedance matching and improves signal integrity for the motor 2 bus clock signal. | | 23 | NC | | ✅ | NC (no connect) pin correctly left unconnected. | </details> <details> <summary>R3 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_TCBUS | ✅ | Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution. | | 2 | 2 | NetR3_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y1 and SCLK_TCBUS. The 47Ω value provides impedance matching for the thermocouple bus clock distribution. | </details> <details> <summary>R4 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA27_SCLK | ✅ | Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal. | | 2 | 2 | NetR4_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y2 and PA27_SCLK. The 47Ω value provides impedance matching for the external connector clock signal. | </details> <details> <summary>R13 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_M1BUS | ✅ | Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution. | | 2 | 2 | NetR13_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y3 and SCLK_M1BUS. The 47Ω value provides impedance matching for the motor 1 bus clock distribution. | </details> <details> <summary>R32 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SCLK_M2BUS | ✅ | Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution. | | 2 | 2 | NetR32_2 | ✅ | Series termination resistor correctly placed between clock buffer output Y4 and SCLK_M2BUS. The 47Ω value provides impedance matching for the motor 2 bus clock distribution. | </details> <details> <summary>U16 - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/scas290q/scas290q.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | nOE1 | CS_TCBUS | ✅ | Output enable for buffer 1, connected to CS_TCBUS which is derived from thermocouple chip selects through diode OR gate with 10k pullup (R95). | | 2 | A1 | MISO_TCBUS | ✅ | Input to buffer 1, connected to MISO_TCBUS from the thermocouple SPI bus. | | 3 | Y1 | NetR94_2 | ✅ | Output of buffer 1, connected through R94 (47R) to PA25_MISO along with outputs from buffers 2 and 3 in a wire-OR configuration. | | 4 | nOE2 | CS_M1BUS | ✅ | Output enable for buffer 2, connected to CS_M1BUS which is derived from motor bus 1 chip selects through diode OR gate with 10k pullup (R100). | | 5 | A2 | MISO_M1BUS | ✅ | Input to buffer 2, connected to MISO_M1BUS from motor bus 1 and SPI flash. | | 6 | Y2 | NetR94_2 | ✅ | Output of buffer 2, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 3 in a wire-OR configuration. | | 7 | GND | GND | ✅ | Ground pin, correctly connected to GND net. | | 8 | Y3 | NetR94_2 | ✅ | Output of buffer 3, connected through R94 (47R) to PA25_MISO along with outputs from buffers 1 and 2 in a wire-OR configuration. | | 9 | A3 | MISO_M2BUS | ✅ | Input to buffer 3, connected to MISO_M2BUS from motor bus 2. | | 10 | nOE3 | CS_M2BUS | ✅ | Output enable for buffer 3, connected to CS_M2BUS which is derived from motor bus 2 chip selects through diode OR gate with 10k pullup (R97). | | 11 | Y4 | unconnected-(NetU16_11) | ✅ | Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality. | | 12 | A4 | GND | ✅ | Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality. | | 13 | nOE4 | GND | ✅ | Buffer 4 is unused with output unconnected (pin 11), input tied to GND (pin 12), and output enable tied to GND (pin 13, always enabled). This configuration wastes a small amount of power but does not affect circuit functionality. | | 14 | Vcc | 3.3VCC | ✅ | Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor. | | 15 | PAD | GND | ✅ | Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance. | | 23 | NC | | ✅ | No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN. | </details> <details> <summary>U17 - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/scas290q/scas290q.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | nOE1 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 4 | nOE2 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 10 | nOE3 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 13 | nOE4 | GND | ✅ | Output enable pins for all four buffers, all tied to GND to keep buffers permanently enabled for MOSI fanout application. | | 2 | A1 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 5 | A2 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 9 | A3 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 12 | A4 | PA26_MOSI_D | ✅ | Input pins for all four buffers, all connected to PA26_MOSI_D to implement a 1-to-4 fanout of the MOSI signal. | | 3 | Y1 | NetR84_2 | ✅ | Output of buffer 1, connected through R84 (47R) to MOSI_TCBUS to distribute the MOSI signal to the thermocouple bus. | | 6 | Y2 | NetR59_2 | ✅ | Output of buffer 2, connected through R59 (47R) to MOSI_M1BUS to distribute the MOSI signal to motor bus 1. | | 7 | GND | GND | ✅ | Ground pin, correctly connected to GND net. | | 8 | Y3 | NetR89_2 | ✅ | Output of buffer 3, connected through R89 (47R) to MOSI_M2BUS to distribute the MOSI signal to motor bus 2. | | 11 | Y4 | NetR93_2 | ✅ | Output of buffer 4, connected through R93 (47R) to PA26_MOSI to distribute the MOSI signal to an additional SPI device or connector. | | 14 | Vcc | 3.3VCC | ✅ | Power supply pin, correctly connected to 3.3VCC with proper bypass capacitor. | | 15 | PAD | GND | ✅ | Thermal/ground pad, correctly connected to GND for proper thermal dissipation and electrical performance. | | 23 | NC | | ✅ | No-connect pin with no net connection. This pin designation appears to be a component library artifact as the RGY package is a 14-pin VQFN. | </details> <details> <summary>R59 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M1BUS | ✅ | Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting. | | 2 | 2 | NetR59_2 | ✅ | Series resistor between U17 buffer 2 output and MOSI_M1BUS, providing signal integrity and current limiting. | </details> <details> <summary>R84 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_TCBUS | ✅ | Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting. | | 2 | 2 | NetR84_2 | ✅ | Series resistor between U17 buffer 1 output and MOSI_TCBUS, providing signal integrity and current limiting. | </details> <details> <summary>R89 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MOSI_M2BUS | ✅ | Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting. | | 2 | 2 | NetR89_2 | ✅ | Series resistor between U17 buffer 3 output and MOSI_M2BUS, providing signal integrity and current limiting. | </details> <details> <summary>R93 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA26_MOSI | ✅ | Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting. | | 2 | 2 | NetR93_2 | ✅ | Series resistor between U17 buffer 4 output and PA26_MOSI, providing signal integrity and current limiting. | </details> <details> <summary>R94 - 47R 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040247R0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA25_MISO | ✅ | Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals. | | 2 | 2 | NetR94_2 | ✅ | Series resistor between wire-ORed U16 buffer outputs and PA25_MISO, providing current limiting for multiplexed MISO signals. | </details> <details> <summary>R77 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA26_MOSI_D | ✅ | Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side. | | 2 | 2 | NetR77_2 | ✅ | Series resistor between microcontroller MOSI pin and PA26_MOSI_D, providing series termination on the driver side. | </details> <details> <summary>R82 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC64_2 | ✅ | Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination. | | 2 | 2 | NetR82_2 | ✅ | Series resistor between clock buffer output and microcontroller SCLK pin, providing series termination. | </details> <details> <summary>R83 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA25_MISO | ✅ | Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side. | | 2 | 2 | NetR83_2 | ✅ | Series resistor between PA25_MISO and microcontroller MISO pin, providing series termination on the receiver side. | </details> <details> <summary>D5 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS4 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS4 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D30 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS2 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS2 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D31 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS3 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS3 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D40 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS6 | ✅ | Schottky diode in OR gate configuration connecting M_nCS6 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D41 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS7 | ✅ | Schottky diode in OR gate configuration connecting M_nCS7 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D60 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS5 | ✅ | Schottky diode in OR gate configuration connecting M_nCS5 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D61 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS1 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS1 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D62 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing. | | K | K | TC_nCS5 | ✅ | Schottky diode in OR gate configuration connecting TC_nCS5 to CS_TCBUS for chip select multiplexing. | </details> <details> <summary>D63 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing. | | K | K | M_nCS8 | ✅ | Schottky diode in OR gate configuration connecting M_nCS8 to CS_M2BUS for chip select multiplexing. | </details> <details> <summary>D70 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS1 | ✅ | Schottky diode in OR gate configuration connecting M_nCS1 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>D74 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS2 | ✅ | Schottky diode in OR gate configuration connecting M_nCS2 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>D75 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS3 | ✅ | Schottky diode in OR gate configuration connecting M_nCS3 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>D76 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing. | | K | K | M_nCS4 | ✅ | Schottky diode in OR gate configuration connecting M_nCS4 to CS_M1BUS for chip select multiplexing. | </details> <details> <summary>R95 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active. | | 2 | 2 | CS_TCBUS | ✅ | Pullup resistor for CS_TCBUS, ensuring the bus select signal is high when no chip select is active. | </details> <details> <summary>R97 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active. | | 2 | 2 | CS_M2BUS | ✅ | Pullup resistor for CS_M2BUS, ensuring the bus select signal is high when no chip select is active. | </details> <details> <summary>R100 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VCC | ✅ | Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active. | | 2 | 2 | CS_M1BUS | ✅ | Pullup resistor for CS_M1BUS, ensuring the bus select signal is high when no chip select is active. | </details> <details> <summary>S1 - 1571610-2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/1571610-2) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | RESET | ✅ | Pin 1 connects to the RESET net, which is the JTAG reset signal. When the button is pressed, it pulls RESET to ground. The RESET net lacks a pull-up resistor on the target board, but this is acceptable for JTAG applications where the external programmer typically provides the pull-up. | | 2 | S | GND | ✅ | Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability. | | 3 | 3 | GND | ✅ | Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability. | | 4 | 4 | GND | ✅ | Pins 2, 3, and 4 are all correctly connected to GND, providing the return path when the switch is pressed and ensuring mechanical stability. | </details> <details> <summary>S2 - KMR741NG ULC LFS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/littelfuse-c-k-tactile-kmr7-series-datasheet?assetguid=3f886e93-c59b-4ff0-b554-18b427e789cb) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/KMR741NG%20ULC%20LFS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | 3.3VCC | ✅ | Pin 1 is correctly connected to 3.3VCC, providing the high voltage source for the ERASE signal when the button is pressed. | | 2 | | unconnected-(NetS2_2) | ✅ | Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability. | | 4 | | unconnected-(NetS2_4) | ✅ | Pins 2 and 4 are left unconnected. While the switch will function correctly with only pins 1 and 3 connected, connecting these pins would provide better mechanical stability and reliability. | | 3 | | ERASE | ✅ | Pin 3 is correctly connected to the ERASE net. When the button is pressed, ERASE is pulled high to 3.3VCC through pin 1. | </details> <details> <summary>C40 - GRM155R71H103JA88D ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM155R71H103JA88-01.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/GRM155R71H103JA88D) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESET | ✅ | Pin 1 is correctly connected to the RESET net to provide filtering and debouncing for the JTAG reset signal. | | 2 | 2 | 3.3VIO | ✅ | Pin 2 is correctly connected to 3.3VIO. This provides filtering referenced to the I/O voltage rail, which is an acceptable design choice though less common than connecting to ground. | </details> <details> <summary>D24 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD24_A | ✅ | LED anode correctly connected to current limiting resistor R34. The LED is driven by microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0) through a 1kΩ resistor, providing approximately 1.1mA forward current. | | C | C | GND | ✅ | LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high. | </details> <details> <summary>D25 - 5988140107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988140107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD25_A | ✅ | LED anode correctly connected to current limiting resistor R36. The LED is driven by microcontroller GPIO LED_Y (U11A pin 55, PC1) through a 1kΩ resistor, providing approximately 1.3mA forward current. | | C | C | GND | ✅ | LED cathode correctly connected to ground. This completes the LED current path when the GPIO drives high. | </details> <details> <summary>R34 - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LED_R | ✅ | Resistor connected to microcontroller GPIO LED_R (U11A pin 60, PC3/D1/PWMH0). This is the input side of the current limiting resistor for the red LED. | | 2 | 2 | NetD24_A | ✅ | Resistor connected to red LED anode (D24 pin A). This is the output side of the current limiting resistor, providing approximately 1.1mA to the LED. | </details> <details> <summary>R36 - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LED_Y | ✅ | Resistor connected to microcontroller GPIO LED_Y (U11A pin 55, PC1). This is the input side of the current limiting resistor for the yellow LED. | | 2 | 2 | NetD25_A | ✅ | Resistor connected to yellow LED anode (D25 pin A). This is the output side of the current limiting resistor, providing approximately 1.3mA to the LED. | </details> <details> <summary>D44 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD protection of the 3.3VCC power rail. This is the correct connection for an ESD protection diode. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail for ESD protection. This is the correct connection for protecting the 3.3V power supply from ESD events. | </details> <details> <summary>D45 - DF2S6.8FS,L3M ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://toshiba.semicon-storage.com/info/docget.jsp?did=22219&prodName=DF2S6.8FS) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DF2S6.8FS,L3M) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND for ESD protection of the +5VCC power rail. This is the correct connection for an ESD protection diode. | | K | K | +5VCC | ✅ | Cathode connected to +5VCC rail for ESD protection. This is the correct connection for protecting the 5V power supply from bidirectional ESD events. | </details> <details> <summary>R40 - 1k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Connected to 3.3VIO power rail to provide pull-up voltage for I2C SDA line. | | 2 | 2 | PA17_SDA | ✅ | Connected to PA17_SDA (I2C data line) from microcontroller pin 9 and external header J20 pin 22. | </details> <details> <summary>R71 - 1k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3.3VIO | ✅ | Connected to 3.3VIO power rail to provide pull-up voltage for I2C SCL line. | | 2 | 2 | PA18_SCL | ✅ | Connected to PA18_SCL (I2C clock line) from microcontroller pin 70 and external header J20 pin 21. | </details> <details> <summary>Q12A - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Source 1 is correctly connected to GND for low-side switching operation. | | 2 | G | NetQ12_2 | ✅ | Gate 1 is correctly driven through a 100Ω series resistor from buffer U2D output, controlling Fan 1 switching. | | 7 | D | NetC154_2 | ✅ | Drain 1 is correctly connected to switch the Fan 1 load and LED1 indicator. | </details> <details> <summary>Q12B - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 3 | S | GND | ✅ | Source 2 is correctly connected to GND for low-side switching operation. | | 4 | G | NetQ12_4 | ✅ | Gate 2 is correctly driven through a 100Ω series resistor from buffer U2C output, controlling Fan 2 switching. | | 5 | D | NetC153_2 | ✅ | Drain 2 is correctly connected to switch the Fan 2 load and LED2 indicator. | </details> <details> <summary>Q13A - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Source 1 is correctly connected to GND for low-side switching operation. | | 2 | G | NetQ13_2 | ✅ | Gate 1 is correctly driven through a 100Ω series resistor from buffer U2B output, controlling Fan 3 switching. | | 7 | D | NetC211_2 | ✅ | Drain 1 is correctly connected to switch the Fan 3 load and LED3 indicator. | </details> <details> <summary>Q13B - NCV8402AD ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | D | VFAN | ❌ | <details><summary>Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,56.24,70.56,63.74" aspect-ratio="1.29" } <ul><li>Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1">NCV8402ADDR2G</a>, page 1)</li><li>Pin 5 is connected to the VFAN net (from schematic)</li><li>VFAN is the positive power supply rail for the fans (from schematic)</li><li>In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning)</li><li>The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic)</li><li>Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic)</li><li>Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic)</li><li>Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic)</li><li>J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic)</li><li>J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic)</li><li>With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning)</li><li>LED4 cathode is connected to VFAN (from schematic)</li><li>LED4 anode connects through R14 to VFAN (from schematic)</li><li>With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning)</li><li>C209 has both pins connected to VFAN, providing no filtering function (from schematic)</li><li>When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3">NCV8402ADDR2G</a>, page 3)</li><li>This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3">NCV8402ADDR2G</a>, page 3)</li><li>The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3">NCV8402ADDR2G</a>, page 3)</li><li>This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning)</li><li>The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1">NCV8402ADDR2G</a>, page 1)</li><li>Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)</li><li>This connection error makes the Fan 4 control circuit completely non-functional (reasoning)</li></ul></details> | | 3 | S | GND | ✅ | Source 2 is correctly connected to GND for low-side switching operation. | | 4 | G | NetQ13_4 | ✅ | Gate 2 is correctly driven through a 100Ω series resistor from buffer U2A output, controlling Fan 4 switching. | </details> <details> <summary>U2A - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1OE | GND | ✅ | Output enable (1OE) is tied directly to GND, permanently enabling gate 1. This is functionally correct for this always-on fan control application, though it differs from the datasheet recommendation to use a pullup resistor to VCC for high-impedance state during power transitions. | | 2 | 1A | Fan4 | ✅ | Input (1A) is connected to Fan4 control signal with a 10K pulldown resistor (R101) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 3 | 1Y | NetR181_1 | ✅ | Output (1Y) drives a 100R gate resistor (R181) which controls the gate of MOSFET driver Q13B. This is standard practice for MOSFET gate drive circuits to limit inrush current and reduce ringing. | </details> <details> <summary>U2B - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 4 | 2OE | GND | ✅ | Output enable (2OE) is tied directly to GND, permanently enabling gate 2. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers. | | 5 | 2A | Fan3 | ✅ | Input (2A) is connected to Fan3 control signal with a 10K pulldown resistor (R171) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 6 | 2Y | NetR180_1 | ✅ | Output (2Y) drives a 100R gate resistor (R180) which controls the gate of MOSFET driver Q13A. This is standard practice for MOSFET gate drive circuits. | </details> <details> <summary>U2C - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 8 | 3Y | NetR99_1 | ✅ | Output (3Y) drives a 100R gate resistor (R99) which controls the gate of MOSFET driver Q12B. This is standard practice for MOSFET gate drive circuits. | | 9 | 3A | FAN2 | ✅ | Input (3A) is connected to FAN2 control signal with a 10K pulldown resistor (R182) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 10 | 3OE | GND | ✅ | Output enable (3OE) is tied directly to GND, permanently enabling gate 3. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers. | </details> <details> <summary>U2D - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 11 | 4Y | NetR98_1 | ✅ | Output (4Y) drives a 100R gate resistor (R98) which controls the gate of MOSFET driver Q12A. This is standard practice for MOSFET gate drive circuits. | | 12 | 4A | FAN1 | ✅ | Input (4A) is connected to FAN1 control signal with a 10K pulldown resistor (R183) providing a defined low state when not driven, which is correct per datasheet recommendations for CMOS inputs. | | 13 | 4OE | GND | ✅ | Output enable (4OE) is tied directly to GND, permanently enabling gate 4. This is functionally correct for this always-on fan control application, consistent with the design approach for all four buffers. | </details> <details> <summary>U2E - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 7 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 14 | VCC | +5VCC | ✅ | Power supply pin is correctly connected to +5VCC with a 100nF bypass capacitor (C92) nearby, meeting datasheet recommendations for decoupling. | | 15 | PAD | SNTP1 | ✅ | Exposed thermal pad (PAD) is connected to net SNTP1. The text label 'SNTP1' near the component suggests this connection is intentional. For optimal thermal performance, this pad should be connected to ground. Verify that SNTP1 is properly connected to ground elsewhere in the design for adequate thermal dissipation. | </details> <details> <summary>D50 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD50_A | ✅ | Anode connected to NetD50_A, forming the upper clamp for the TACH_1 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D51 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD51_A | ✅ | Anode connected to NetD51_A, forming the upper clamp for the TACH_2 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D52 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct. | | K | K | NetD50_A | ✅ | Cathode connected to NetD50_A, completing the lower clamping path for TACH_1 signal protection. This connection is correct. | </details> <details> <summary>D53 - BAT54WX ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | unconnected-(NetD53_A) | ❌ | <details><summary>Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,35.79,70.56,43.29" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected (from schematic)</li><li>D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp (reasoning)</li><li>All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND (from schematic)</li><li>The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) (reasoning)</li><li>Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients (reasoning)</li><li>The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits (reasoning)</li><li>D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 (reasoning)</li></ul></details> | | K | K | NetD51_A | ✅ | Cathode connected to NetD51_A, which is the correct connection for a lower clamp diode. However, the diode is non-functional because pin A is unconnected. | </details> <details> <summary>D54 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD54_A | ✅ | Anode connected to NetD54_A, forming the upper clamp for the TACH_3 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D55 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD55_A | ✅ | Anode connected to NetD55_A, forming the upper clamp for the TACH_4 signal protection circuit. This connection is correct. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC rail, providing the upper voltage reference for signal clamping. This connection is correct. | </details> <details> <summary>D56 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct. | | K | K | NetD54_A | ✅ | Cathode connected to NetD54_A, completing the lower clamping path for TACH_3 signal protection. This connection is correct. | </details> <details> <summary>D57 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND, providing the lower voltage reference for signal clamping. This connection is correct. | | K | K | NetD55_A | ✅ | Cathode connected to NetD55_A, completing the lower clamping path for TACH_4 signal protection. This connection is correct. | </details> <details> <summary>LED1 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED1_A | ✅ | Anode is correctly connected through current limiting resistor R96 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit. | | C | C | NetC154_2 | ✅ | Cathode is correctly connected to the drain of low-side MOSFET driver Q12A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated. | </details> <details> <summary>LED2 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED2_A | ✅ | Anode is correctly connected through current limiting resistor R12 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit. | | C | C | NetC153_2 | ✅ | Cathode is correctly connected to the drain of low-side MOSFET driver Q12B (pin 5), which switches the LED on/off by pulling the cathode to ground when activated. | </details> <details> <summary>LED3 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED3_A | ✅ | Anode is correctly connected through current limiting resistor R15 (4.7K) to VFAN power rail, providing proper current limiting for the LED in this low-side switched indicator circuit. | | C | C | NetC211_2 | ✅ | Cathode is correctly connected to the drain of low-side MOSFET driver Q13A (pin 7), which switches the LED on/off by pulling the cathode to ground when activated. | </details> <details> <summary>LED4 - 5988110107F ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C | C | VFAN | ❌ | <details><summary>Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,53.30,70.56,60.80" aspect-ratio="1.29" } <ul><li>Pin C (Cathode) is connected directly to net VFAN (from schematic)</li><li>Pin C is the Cathode connection per the datasheet (from datasheet <a href="https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf">5988110107F</a>)</li><li>The anode is connected to VFAN through R14, making both terminals at the same potential (from schematic)</li><li>For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop (from datasheet <a href="https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf">5988110107F</a>)</li><li>With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow (reasoning)</li><li>LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) (from schematic)</li><li>Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern (from schematic)</li><li>J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets (from schematic)</li><li>The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated (reasoning)</li><li>This error prevents LED4 from functioning as a fan status indicator (reasoning)</li></ul></details> | | A | A | NetLED4_A | ✅ | Anode is connected through current limiting resistor R14 (4.7K) to VFAN power rail. While this connection topology is correct, the LED cannot function because the cathode is also connected to VFAN, creating zero voltage difference across the LED. | </details> <details> <summary>J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC154_2 | ✅ | Pin 1 is correctly connected to the switched ground output (NetC154_2) for Fan 1, implementing low-side PWM control where the MOSFET switches the ground return path. | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan. | | 3 | S | NetJ29_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ29_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. | </details> <details> <summary>J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC153_2 | ✅ | Pin 1 is correctly connected to the switched ground output (NetC153_2) for Fan 2, implementing low-side PWM control where the MOSFET switches the ground return path. | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan. | | 3 | S | NetJ22_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ22_3) with proper signal conditioning including pull-up resistor, series resistors, upper clamp diode, and filtering capacitor. Note that the lower clamp diode D53 has an unconnected anode, which reduces protection against negative transients but should not prevent normal operation. | </details> <details> <summary>J31 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC211_2 | ✅ | Pin 1 is correctly connected to the switched ground output (NetC211_2) for Fan 3, implementing low-side PWM control where the MOSFET switches the ground return path. | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing constant unswitched power to the fan. | | 3 | S | NetJ31_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ31_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. | </details> <details> <summary>J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | VFAN | ❌ | <details><summary>Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="76.69,54.48,84.19,61.98" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net VFAN (from schematic)</li><li>Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net (from schematic)</li><li>Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 (from schematic)</li><li>For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) (from schematic)</li><li>Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 (from schematic)</li><li>Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively (from schematic)</li><li>LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 (from schematic)</li><li>Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output (from schematic)</li><li>The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference (from schematic)</li><li>In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path (reasoning)</li><li>Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate (reasoning)</li><li>With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation (reasoning)</li><li>Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits (reasoning)</li></ul></details> | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN, providing the power supply voltage. However, the fan cannot operate due to the error on pin 1 which prevents the ground return path. | | 3 | S | NetJ30_3 | ✅ | Pin 3 is correctly connected to the tachometer signal path (NetJ30_3) with proper signal conditioning including pull-up resistor, series resistors for current limiting, ESD protection diodes, and filtering capacitor. The tachometer circuit is correctly implemented, though the fan may not operate due to the error on pin 1. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **S1** (1571610-2): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/1571610-2) - **P1** (2213S-08G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-08G) - **J20** (2213S-24G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-24G) - **F2** (3557-2): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-2) - **X1** (405C35B12M00000): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/405C35B12M00000) - **D23** (5988170107F): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988170107F) - **J8** (61729-0010BLF): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/61729-0010BLF) - **U11A, U11B, U11C** (ATSAM3X8EA-AU): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) - **U19** (INA381A2IDSGR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/INA381A2IDSGR) - **U20** (L78L05ABUTR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/L78L05ABUTR) - **U8** (MIC5353-3.3YMT-TR): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MIC5353-3.3YMT-TR) - **Q8** (MMBT3904T-7-F): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MMBT3904T-7-F) - **JP1, JP2** (NOTAPART-Solder Bridge): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) - **D26** (RSB39VTE-17): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RSB39VTE-17) - **U18** (TLP293(TPL,E): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TLP293%28TPL,E) </details> Note: DRCY uses AI. Please verify the outputs.

Fans.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component Q13B, pin 5: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.

Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet NCV8402ADDR2G, page 1)
Pin 5 is connected to the VFAN net (from schematic)
VFAN is the positive power supply rail for the fans (from schematic)
In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning)
The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic)
Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic)
Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic)
Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic)
J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic)
J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic)
With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning)
LED4 cathode is connected to VFAN (from schematic)
LED4 anode connects through R14 to VFAN (from schematic)
With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning)
C209 has both pins connected to VFAN, providing no filtering function (from schematic)
When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet NCV8402ADDR2G, page 3)
This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet NCV8402ADDR2G, page 3)
The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet NCV8402ADDR2G, page 3)
This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning)
The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet NCV8402ADDR2G, page 1)
Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)
This connection error makes the Fan 4 control circuit completely non-functional (reasoning)

All affected pins

Component Q13B, pin `5`: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.

Pin 5 is the Drain 2 terminal according to the datasheet (from datasheet NCV8402ADDR2G, page 1)
Pin 5 is connected to the VFAN net (from schematic)
VFAN is the positive power supply rail for the fans (from schematic)
In a low-side switch configuration, the drain should be connected to the load, not to the power supply (reasoning)
The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs (from schematic)
Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) (from schematic)
Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) (from schematic)
Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) (from schematic)
J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output (from schematic)
J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN (from schematic)
With both fan connector pins at VFAN, the fan cannot be switched on or off (reasoning)
LED4 cathode is connected to VFAN (from schematic)
LED4 anode connects through R14 to VFAN (from schematic)
With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up (reasoning)
C209 has both pins connected to VFAN, providing no filtering function (from schematic)
When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical (from datasheet NCV8402ADDR2G, page 3)
This will cause excessive current flow limited only by the NCV8402's internal current limiting (from datasheet NCV8402ADDR2G, page 3)
The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V (from datasheet NCV8402ADDR2G, page 3)
This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features (reasoning)
The datasheet shows typical application with drain connected to the load, not to the power supply (from datasheet NCV8402ADDR2G, page 1)
Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)
This connection error makes the Fan 4 control circuit completely non-functional (reasoning)

Component LED4, pin `C`: Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3.

Pin C (Cathode) is connected directly to net VFAN (from schematic)
Pin C is the Cathode connection per the datasheet (from datasheet 5988110107F)
The anode is connected to VFAN through R14, making both terminals at the same potential (from schematic)
For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop (from datasheet 5988110107F)
With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow (reasoning)
LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) (from schematic)
Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern (from schematic)
J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets (from schematic)
The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated (reasoning)
This error prevents LED4 from functioning as a fan status indicator (reasoning)

Component J30, pin `1`: Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor.

Pin 1 is connected to net VFAN (from schematic)
Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net (from schematic)
Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 (from schematic)
For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) (from schematic)
Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 (from schematic)
Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively (from schematic)
LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 (from schematic)
Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output (from schematic)
The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference (from schematic)
In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path (reasoning)
Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate (reasoning)
With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation (reasoning)
Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits (reasoning)

Datasheets: 📄 LED4 📄 J30 📄 Q13B

_{Replace a datasheet: 📤 J30 📤 LED4 📤 Q13B}

[🚨 Error] **Component `Q13B`, pin `5`: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,56.24,70.56,63.74" aspect-ratio="1.29" } - Pin 5 is the Drain 2 terminal according to the datasheet *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 is connected to the VFAN net *(from schematic)* - VFAN is the positive power supply rail for the fans *(from schematic)* - In a low-side switch configuration, the drain should be connected to the load, not to the power supply *(reasoning)* - The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs *(from schematic)* - Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) *(from schematic)* - Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) *(from schematic)* - Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) *(from schematic)* - J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output *(from schematic)* - J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN *(from schematic)* - With both fan connector pins at VFAN, the fan cannot be switched on or off *(reasoning)* - LED4 cathode is connected to VFAN *(from schematic)* - LED4 anode connects through R14 to VFAN *(from schematic)* - With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up *(reasoning)* - C209 has both pins connected to VFAN, providing no filtering function *(from schematic)* - When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This will cause excessive current flow limited only by the NCV8402's internal current limiting *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features *(reasoning)* - The datasheet shows typical application with drain connected to the load, not to the power supply *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 *(reasoning)* - This connection error makes the Fan 4 control circuit completely non-functional *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>Q13B</code>, pin `5`: Drain 2 is incorrectly connected directly to VFAN power supply instead of a switched output net. This prevents Fan 4 from being controlled, causes LED4 to be non-functional, and would create a short circuit from VFAN to GND when the MOSFET turns on.</summary> - Pin 5 is the Drain 2 terminal according to the datasheet *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 is connected to the VFAN net *(from schematic)* - VFAN is the positive power supply rail for the fans *(from schematic)* - In a low-side switch configuration, the drain should be connected to the load, not to the power supply *(reasoning)* - The other three channels (Q12A, Q12B, Q13A) all have their drains connected to switched output nets that drive fan connectors and LEDs *(from schematic)* - Q12A pin 7 connects to NetC154_2 (J29 pin 1, LED1 cathode, C154 pin 2) *(from schematic)* - Q12B pin 5 connects to NetC153_2 (J22 pin 1, LED2 cathode, C153 pin 2) *(from schematic)* - Q13A pin 7 connects to NetC211_2 (J31 pin 1, LED3 cathode, C211 pin 2) *(from schematic)* - J30 pin 1 (Fan 4 connector negative terminal) is connected directly to VFAN instead of to a switched output *(from schematic)* - J30 pin 2 (Fan 4 connector positive terminal) is also connected to VFAN *(from schematic)* - With both fan connector pins at VFAN, the fan cannot be switched on or off *(reasoning)* - LED4 cathode is connected to VFAN *(from schematic)* - LED4 anode connects through R14 to VFAN *(from schematic)* - With both LED4 terminals at VFAN potential, there is no voltage drop across the LED and it cannot light up *(reasoning)* - C209 has both pins connected to VFAN, providing no filtering function *(from schematic)* - When Q13B gate is driven high, the MOSFET will turn on and attempt to pull VFAN to GND through the low RDS(on) of 165mΩ typical *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This will cause excessive current flow limited only by the NCV8402's internal current limiting *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - The current limit is specified as 3.7-5.0 A at VGS=5V or 4.2-5.4 A at VGS=10V *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=3>), page 3)* - This configuration wastes power, may cause thermal issues, and will trigger the device's self-protection features *(reasoning)* - The datasheet shows typical application with drain connected to the load, not to the power supply *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 should be connected to a new switched output net (similar to NetC154_2, NetC153_2, or NetC211_2) along with J30 pin 1, LED4 cathode, and C209 pin 2 *(reasoning)* - This connection error makes the Fan 4 control circuit completely non-functional *(reasoning)* </details> <details> <summary>Component <code>LED4</code>, pin `C`: Cathode is incorrectly connected directly to VFAN power rail instead of to Q13B drain. This creates zero voltage difference across the LED since the anode is also connected to VFAN through R14, preventing the LED from ever illuminating. The cathode should be connected to Q13B drain (pin 5) to match the working configuration of LED1, LED2, and LED3.</summary> - Pin C (Cathode) is connected directly to net VFAN *(from schematic)* - Pin C is the Cathode connection per the datasheet *(from datasheet [5988110107F](<https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf>))* - The anode is connected to VFAN through R14, making both terminals at the same potential *(from schematic)* - For an LED to conduct, the anode must be at a higher potential than the cathode by at least the forward voltage drop *(from datasheet [5988110107F](<https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf>))* - With both terminals at VFAN potential, there is zero voltage across the LED and no current will flow *(reasoning)* - LED1, LED2, and LED3 all have their cathodes connected to the drain of their respective low-side MOSFET drivers (Q12A pin 7, Q12B pin 5, Q13A pin 7) *(from schematic)* - Q13B pin 5 (Drain) is connected to VFAN instead of to LED4 cathode, breaking the expected circuit pattern *(from schematic)* - J30 pin 1 is also connected to VFAN, whereas J29, J22, and J31 pin 1 are connected to their respective LED cathode and driver drain nets *(from schematic)* - The correct configuration would be: LED4 cathode connected to Q13B drain (pin 5), forming a switched node that can be pulled to ground when Q13B is activated *(reasoning)* - This error prevents LED4 from functioning as a fan status indicator *(reasoning)* </details> <details> <summary>Component <code>J30</code>, pin `1`: Pin 1 is incorrectly connected to VFAN instead of to a switched ground output from Q13B. This is a critical routing error that prevents Fan 4 from operating because the fan has no ground return path. With both pins 1 and 2 at VFAN potential, there is no voltage difference to drive current through the fan motor.</summary> - Pin 1 is connected to net VFAN *(from schematic)* - Q13B drain (pin 5) is also incorrectly connected to VFAN instead of to a switched output net *(from schematic)* - Q13B is part of the NCV8402AD dual low-side driver with pin 3 (source) connected to GND and pin 4 (gate) connected to control signal NetQ13_4 *(from schematic)* - For Fans 1, 2, and 3, pin 1 of their respective connectors (J29, J22, J31) is correctly connected to switched ground outputs (NetC154_2, NetC153_2, NetC211_2) *(from schematic)* - Q13A (the other half of the same dual driver as Q13B) correctly has its drain (pin 7) connected to switched output NetC211_2 which goes to J31 pin 1 *(from schematic)* - Q12A and Q12B (the other dual driver) also correctly have their drains connected to switched outputs that go to J29 pin 1 and J22 pin 1 respectively *(from schematic)* - LED4 cathode is incorrectly connected to VFAN instead of to a switched output, which prevents the LED from lighting and is inconsistent with LED1, LED2, and LED3 *(from schematic)* - Capacitor C209 has both pins connected to VFAN, which is inconsistent with C154, C153, and C211 that have one pin on VFAN and the other on the switched output *(from schematic)* - The control signal path from Fan4 through buffer U2A and gate resistor R181 to Q13B gate is correctly implemented, indicating this is a routing error rather than an intentional design difference *(from schematic)* - In a low-side driver configuration, the MOSFET drain must connect to the load (fan ground return) and the source must connect to ground to provide a switched ground path *(reasoning)* - Standard 3-wire PC fans require pin 1 to be ground for the fan motor to operate *(reasoning)* - With both J30 pins 1 and 2 at VFAN potential, there is no voltage difference across the fan motor, preventing any current flow and fan operation *(reasoning)* - Pin 1 should be connected to Q13B drain (pin 5), LED4 cathode, and C209 pin 2 on a switched output net (such as NetC209_2), similar to the other three fan circuits *(reasoning)* </details> </details> Datasheets: [📄 LED4](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📄 J30](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📄 Q13B](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) Replace a datasheet: [📤 J30](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) [📤 LED4](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) [📤 Q13B](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G)

Fans.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component D53, pin A: Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels.

Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected (from schematic)
D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp (reasoning)
All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND (from schematic)
The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) (reasoning)
Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients (reasoning)
The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits (reasoning)
D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 (reasoning)

_{Replace a datasheet: 📤 D53}

[🚨 Error] **Component `D53`, pin `A`: Anode is unconnected, which is incorrect. This pin should be connected to GND to provide lower voltage clamping for the TACH_2 signal, matching the configuration of D52, D56, and D57 on the other TACH channels.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="63.06,35.79,70.56,43.29" aspect-ratio="1.29" } - Pin A (Anode) is connected to net unconnected-(NetD53_A), indicating it is not connected *(from schematic)* - D53 is intended to be the lower clamping diode for the TACH_2 signal path, paired with D51 as the upper clamp *(reasoning)* - All other TACH channels have properly connected lower clamping diodes: D52 for TACH_1, D56 for TACH_3, and D57 for TACH_4, all with anodes connected to GND *(from schematic)* - The design pattern for all four TACH signals should be identical: upper clamp (anode to signal, cathode to 3.3VCC) and lower clamp (anode to GND, cathode to signal) *(reasoning)* - Without the anode connected to GND, D53 cannot provide lower voltage clamping, leaving the TACH_2 signal unprotected from negative voltage transients *(reasoning)* - The unconnected anode breaks the symmetry of the four identical TACH signal conditioning circuits *(reasoning)* - D53 anode must be connected to GND to provide proper bidirectional ESD protection for TACH_2 *(reasoning)* Replace a datasheet: [📤 D53](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP)

Microcontroller.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component U11A, pins 29, 30: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.

Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)
Pin 30 (PB30/TDO) is connected to net TDI (from schematic)
Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)
Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)
The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)
The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)
The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)
This swap will prevent JTAG debugging from functioning correctly (reasoning)
In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)
The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)

All affected pins

Component U11A, pins `29, 30`: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.

Pin 29 (PB29/TDI) is connected to net TDO/SWO (from schematic)
Pin 30 (PB30/TDO) is connected to net TDI (from schematic)
Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input (from schematic)
Net TDI connects to J4 pin 8, which is the debugger's TDI output (from schematic)
The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) (reasoning)
The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) (reasoning)
The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 (reasoning)
This swap will prevent JTAG debugging from functioning correctly (reasoning)
In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net (reasoning)
The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net (reasoning)

Component J4, pins `6, 8`: TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.

Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) (from schematic)
Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) (from schematic)
Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)
Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)
PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)
PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name (reasoning)
TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain (reasoning)
Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain (reasoning)
Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) (reasoning)

Datasheets: 📄 J4

_{Upload/replace a datasheet: 📤 J4 📤 U11A}

[🚨 Error] **Component `U11A`, pins `29, 30`: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="46.54,28.08,54.04,36.49" aspect-ratio="1.55" } - Pin 29 (PB29/TDI) is connected to net TDO/SWO *(from schematic)* - Pin 30 (PB30/TDO) is connected to net TDI *(from schematic)* - Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input *(from schematic)* - Net TDI connects to J4 pin 8, which is the debugger's TDI output *(from schematic)* - The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) *(reasoning)* - The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) *(reasoning)* - The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 *(reasoning)* - This swap will prevent JTAG debugging from functioning correctly *(reasoning)* - In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net *(reasoning)* - The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U11A</code>, pins `29, 30`: JTAG pins TDI and TDO are swapped. Pin 29 (PB29/TDI) is connected to TDO/SWO net, and pin 30 (PB30/TDO) is connected to TDI net. This will prevent JTAG debugging from functioning correctly.</summary> - Pin 29 (PB29/TDI) is connected to net TDO/SWO *(from schematic)* - Pin 30 (PB30/TDO) is connected to net TDI *(from schematic)* - Net TDO/SWO connects to J4 pin 6, which is the debugger's TDO input *(from schematic)* - Net TDI connects to J4 pin 8, which is the debugger's TDI output *(from schematic)* - The microcontroller's TDI input (PB29) should connect to the debugger's TDI output (J4 pin 8) *(reasoning)* - The microcontroller's TDO output (PB30) should connect to the debugger's TDO input (J4 pin 6) *(reasoning)* - The current connections are reversed - PB29 connects to J4 pin 6 and PB30 connects to J4 pin 8 *(reasoning)* - This swap will prevent JTAG debugging from functioning correctly *(reasoning)* - In SWD mode, this also affects SWO functionality - PB30 (SWO output) is connected to the TDI net instead of TDO/SWO net *(reasoning)* - The nets should be swapped: PB29 should connect to TDI net, and PB30 should connect to TDO/SWO net *(reasoning)* </details> <details> <summary>Component <code>J4</code>, pins `6, 8`: TDO and TDI signals are swapped. Pin 6 (which should be TDO/SWO) incorrectly connects to U11A pin 29 (PB29/TDI), while pin 8 (which should be TDI) incorrectly connects to U11A pin 30 (PB30/TDO/TRACESWO). These connections must be reversed for JTAG debugging to function correctly.</summary> - Pin 6 is connected to the TDO/SWO net, which routes to U11A pin 29 (PB29/TDI) *(from schematic)* - Pin 8 is connected to the TDI net, which routes to U11A pin 30 (PB30/TDO/TRACESWO) *(from schematic)* - Pin 6 is SWO/TDO in the standard ARM 10-pin JTAG/SWD connector pinout *(reasoning)* - Pin 8 is TDI in the standard ARM 10-pin JTAG/SWD connector pinout *(reasoning)* - PB29 is the TDI pin on the ATSAM3X8EA microcontroller based on its pin name *(reasoning)* - PB30 is the TDO/TRACESWO pin on the ATSAM3X8EA microcontroller based on its pin name *(reasoning)* - TDI (Test Data In) and TDO (Test Data Out) are distinct JTAG signals with opposite data flow directions in the JTAG chain *(reasoning)* - Swapping TDI and TDO will prevent JTAG debugging from functioning correctly as the debugger will be unable to shift data through the scan chain *(reasoning)* - Recommendation: Connect J4 pin 6 to U11A pin 30 (PB30/TDO/TRACESWO) and J4 pin 8 to U11A pin 29 (PB29/TDI) *(reasoning)* </details> </details> Datasheets: [📄 J4](https://cdn.amphenol-cs.com/media/wysiwyg/files/documentation/datasheet/boardwiretoboard/bwb_minitek127_btb.pdf) Upload/replace a datasheet: [📤 J4](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF) [📤 U11A](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU)

Microcontroller.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component J4, pin 10: Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature.

Pin 10 is connected to the RESET net (from schematic)
The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input (from schematic)
A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 (from schematic)
Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout (reasoning)
The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations (reasoning)
The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions (reasoning)
Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection (reasoning)

_{Replace a datasheet: 📤 J4}

[🚨 Error] **Component `J4`, pin `10`: Reset pin connects to RESET net instead of the microcontroller's NRST net. The RESET net does not connect to the microcontroller's reset input, preventing the JTAG debugger from resetting the target MCU, which is a critical debugging feature.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="39.19,69.42,46.69,76.92" aspect-ratio="1.55" } - Pin 10 is connected to the RESET net *(from schematic)* - The RESET net connects to reset button S1, capacitor C40, test point TP56, and TVS diode D71, but does not connect to the microcontroller's reset input *(from schematic)* - A separate NRST net exists that connects to J20 pin 18, R145, J13 pin 6, and J28 pin 6 *(from schematic)* - Pin 10 is nRESET in the standard ARM 10-pin JTAG/SWD connector pinout *(reasoning)* - The JTAG debugger's reset signal must connect to the target microcontroller's reset input to allow the debugger to reset the MCU during debugging operations *(reasoning)* - The current connection prevents the JTAG debugger from resetting the microcontroller, which is essential for debugging workflows such as halting at reset or recovering from fault conditions *(reasoning)* - Recommendation: Connect the RESET net to the NRST net, possibly through a series resistor (e.g., 100-330 ohms) to allow debugger control of the MCU reset while maintaining protection *(reasoning)* Replace a datasheet: [📤 J4](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF)

Power.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[⚠️ Warning] Component U1, pin 2: VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1.

Pin 2 (VIN) is connected to net VPWR (from schematic)
VPWR is the main power input rail derived from VPWR_IN through fuse F2 (from schematic)
This pin is the 3.5- to 28-V input supply voltage (from datasheet TPS54531DDAR, page 3)
Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended (from datasheet TPS54531DDAR, page 14)
Input decoupling capacitor of 10μF is recommended per datasheet (from datasheet TPS54531DDAR, page 1)
C71 is a 10nF capacitor on VPWR (from schematic)
C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total (from schematic)
Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF (reasoning)
Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response (reasoning)
A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) (reasoning)

_{Replace a datasheet: 📤 U1}

[⚠️ Warning] **Component `U1`, pin `2`: VIN pin connected to VPWR supply rail, but insufficient input decoupling capacitance present. Datasheet recommends 10μF, but only approximately 310nF total ceramic capacitance is visible near U1.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="50.79,50.95,58.29,58.45" aspect-ratio="1.29" } - Pin 2 (VIN) is connected to net VPWR *(from schematic)* - VPWR is the main power input rail derived from VPWR_IN through fuse F2 *(from schematic)* - This pin is the 3.5- to 28-V input supply voltage *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=3>), page 3)* - Requires input decoupling capacitor, typically 10 μF. High-quality ceramic type X5R or X7R recommended *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14>), page 14)* - Input decoupling capacitor of 10μF is recommended per datasheet *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=1>), page 1)* - C71 is a 10nF capacitor on VPWR *(from schematic)* - C199, C202, and C203 are 100nF capacitors on VPWR, providing 300nF total *(from schematic)* - Total ceramic capacitance on VPWR near U1 is approximately 310nF, which is significantly less than the recommended 10μF *(reasoning)* - Insufficient input capacitance can cause stability issues, increased input ripple, and poor transient response *(reasoning)* - A dedicated 10μF or larger X5R/X7R ceramic capacitor should be added close to U1 VIN pin (pin 2) and GND pin (pin 7) *(reasoning)* Replace a datasheet: [📤 U1](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TPS54531DDAR)

Power.SchDoc

DRCYAI commented

2026-04-22 01:32:11 +00:00

[🚨 Error] Component D21, pins A, K: TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.

Pin A (Anode) is connected to net VMOTE (from schematic)
Pin K (Cathode) is connected to net GND (from schematic)
VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text (from schematic)
SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage (from datasheet SMAJ24A, page 1)
The color band on the device denotes the cathode terminal (from datasheet SMAJ24A, page 1)
The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails (from schematic)
With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation (reasoning)
The maximum instantaneous forward voltage is 3.5V at 25A for single die parts (from datasheet SMAJ24A, page 1)
A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop (reasoning)
This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail (reasoning)
The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 (reasoning)

_{Replace a datasheet: 📤 D21}

[🚨 Error] **Component `D21`, pins `A, K`: TVS diode is incorrectly connected with reversed polarity. Anode is connected to VMOTE and cathode to GND, which is opposite to the correct configuration. This will cause the diode to be forward-biased during normal operation, clamping VMOTE to approximately 1-3.5V and preventing the rail from reaching its intended 12-24V operating voltage.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="5" diff-visibility="full" variant="default" view-coords="2.64,54.95,10.14,63.63" aspect-ratio="1.29" } - Pin A (Anode) is connected to net VMOTE *(from schematic)* - Pin K (Cathode) is connected to net GND *(from schematic)* - VMOTE is a motor power supply rail for motors 5-8, expected to operate at 12-24VDC based on page text *(from schematic)* - SMAJ24A is a unidirectional TVS diode with 24V reverse standoff voltage and 38.9V clamping voltage *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - The color band on the device denotes the cathode terminal *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - The other three TVS diodes on this schematic (D43, D22, D78) all have their anodes connected to GND and cathodes to their respective power rails *(from schematic)* - With the anode at positive voltage (VMOTE) and cathode at ground, the diode will be forward-biased during normal operation *(reasoning)* - The maximum instantaneous forward voltage is 3.5V at 25A for single die parts *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - A forward-biased TVS diode will conduct continuously, creating a short circuit path from VMOTE to GND through the forward voltage drop *(reasoning)* - This will prevent VMOTE from reaching its intended 12-24V operating voltage and will likely cause the diode or upstream circuitry to fail *(reasoning)* - The connections should be reversed: anode (A) to GND and cathode (K) to VMOTE to provide proper TVS protection matching the configuration of D43, D22, and D78 *(reasoning)* Replace a datasheet: [📤 D21](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A)