AllSpice-Demos/Cadence-System-Capture-Demo
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Check DDR trace matching #8

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opened 2025-05-20 04:38:31 +00:00 by MikaChanical · 1 comment
MikaChanical commented 2025-05-20 04:38:31 +00:00
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@daniel-allspice, I think this signal is part of a differential pair. Do we need to match it's pair with more symmetry, or can it handle this amount of mismatch?

Originally posted by @MikaChanical in https://hub.allspice.io/AllSpice-Demos/Cadence-System-Capture-Demo/pulls/2/files#diff-e8fe56cd4d62da54d15803041a180cbf774be15e-issuecomment-32767

!thumbnail[](parallella.brd){ diff="AllSpice-Demos/Cadence-System-Capture-Demo:59a3e45856df4717fd20eb5cc7d1d362951b2226...5b5d616e4cb81299fdcaf1675a82216258d14b81" pr="2" layers="3" diff-visibility="full" variant="default" view-coords="24.2,35.2,47.4,56.5" aspect-ratio="1.475" } @daniel-allspice, I think this signal is part of a differential pair. Do we need to match it's pair with more symmetry, or can it handle this amount of mismatch? _Originally posted by @MikaChanical in https://hub.allspice.io/AllSpice-Demos/Cadence-System-Capture-Demo/pulls/2/files#diff-e8fe56cd4d62da54d15803041a180cbf774be15e-issuecomment-32767_
MikaChanical commented 2025-05-20 04:38:49 +00:00
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MikaChanical added this to the V3 Project update milestone 2025-05-20 04:38:59 +00:00
daniel-allspice was assigned by MikaChanical 2025-05-20 04:39:03 +00:00
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Reference: AllSpice-Demos/Cadence-System-Capture-Demo#8
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