AllSpice-Demos/Cadence-System-Capture-Demo

Fork 0

Fix power issues, add fault LED #2

Open

AllSpiceAlice wants to merge 2 commits from develop into main

AllSpiceAlice commented

2025-05-20 03:28:46 +00:00

Owner

Resolved Issues

...
Resolves #3 Track down source of J11 position (and fix J11 position)
Resolves #4 Update PCB Traces to 5A trace (5P0V, 5P0V_IN)
Resolves #5 Replace part not on Approved Parts List (APL)
Resolves #6 Update Firmware .h for Power Fault Flag signal
Resolves #7 Fix large traces shorting BGA pads
Resolves #8 Check DDR Trace matching

Description

...
Increase power on critical traces. Add power fault monitoring. Add fault LED.

Design Review Checklist

Process

@allspice-carah

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes on symbols with multi-function pins match usage
- Components follow preferred reference designator pattern
External I/O
- Filtered for EMI
- Protected against ESD
- Unused inputs terminated
Microcontrollers / ICs
- Predictable or controlled power-up state
  - Reset filtered
- Sufficient bypass capacitance
- Oscillators checked for reliable startup
- Pullups on open-collector pins
- Logic-low and logic-high voltage levels checked
- No-connect pins labeled NC
- Clock lines terminated
- Check for power-off voltage & CMOS latchup
- Review datasheet errata/apnotes
Busses
- UART TX/RX pairs correct
- I2C SDA/SCL pullups per TI guideline
- Setup/hold/access times considered
Analog
- Sufficient power rails
- Amplifier stability
- Rise/fall rate considerations
General
- Bulk capacitance calculated
- Polarized components checked
- No reverse voltage on electrolytic/tantalum
- Derating checked
- Capacitance on LDOs
- Comparator delays/slew rates
- Opamp common-mode range
- Custom part pin numbers verified
- Transistor reverse current/voltage
- Consistent power net naming
- Debug features included

## Resolved Issues  ... Resolves #3 Track down source of J11 position (and fix J11 position) Resolves #4 Update PCB Traces to 5A trace (5P0V, 5P0V_IN) Resolves #5 Replace part not on Approved Parts List (APL) Resolves #6 Update Firmware .h for Power Fault Flag signal Resolves #7 Fix large traces shorting BGA pads Resolves #8 Check DDR Trace matching ## Description  ... Increase power on critical traces. Add power fault monitoring. Add fault LED. ## Design Review Checklist <details> <summary>Process</summary> @allspice-carah - [ ] Commits in correct branch - [ ] Schematic and PCB file names follow standard - [ ] Export necessary review files (3D model, BOM, etc.) - [ ] Update relevant system architecture documents - [ ] Update project README page - [ ] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [ ] Power - [ ] Sufficient power supplied from upstream source - [ ] Supply rated for necessary country specifications - [ ] Estimated total worst-case power supply draw - [ ] Connectors - [ ] I/Os are specified - [ ] Sufficient Current and Voltage rating - [ ] Mating connectors have matching pinout - [ ] Same contact material specified for mating connectors - [ ] Testing - [ ] Test procedure written - [ ] Environmental - [ ] Specified min/max operating temperature - [ ] Specified min/max storage temperature - [ ] Specified min/max humidity - [ ] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [ ] Unpopulated components are denoted DNI - [ ] Components meet environmental specifications - [ ] All components have quantity, reference designator and description - [ ] Suggested and alternate manufacturers listed - [ ] Price and stock checked for each component - [ ] Component derating - [ ] Voltage - [ ] Current - [ ] Power at worst-case operating temperature - [ ] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [ ] Document - [ ] Dot on each connection - [ ] No four-point connections - [ ] Title block completed for each sheet - [ ] All components have reference designators and values - [ ] Multi-part components don't have unplaced symbols - [ ] Page title present and consistent on all pages if not in title block - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins - [ ] Pin names and attributes on symbols with multi-function pins match usage - [ ] Components follow preferred reference designator pattern - [ ] External I/O - [ ] Filtered for EMI - [ ] Protected against ESD - [ ] Unused inputs terminated - [ ] Microcontrollers / ICs - [ ] Predictable or controlled power-up state - [ ] Reset filtered - [ ] Sufficient bypass capacitance - [ ] Oscillators checked for reliable startup - [ ] Pullups on open-collector pins - [ ] Logic-low and logic-high voltage levels checked - [ ] No-connect pins labeled NC - [ ] Clock lines terminated - [ ] Check for power-off voltage & CMOS latchup - [ ] Review datasheet errata/apnotes - [ ] Busses - [ ] UART TX/RX pairs correct - [ ] I2C SDA/SCL pullups per [TI guideline](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Setup/hold/access times considered - [ ] Analog - [ ] Sufficient power rails - [ ] Amplifier stability - [ ] Rise/fall rate considerations - [ ] General - [ ] Bulk capacitance calculated - [ ] Polarized components checked - [ ] No reverse voltage on electrolytic/tantalum - [ ] Derating checked - [ ] Capacitance on LDOs - [ ] Comparator delays/slew rates - [ ] Opamp common-mode range - [ ] Custom part pin numbers verified - [ ] Transistor reverse current/voltage - [ ] Consistent power net naming - [ ] Debug features included </details> <details>

AllSpiceAlice added 2 commits 2025-05-20 03:28:47 +00:00

Merge pull request 'Copy main to develop to start work on develop-main' (#1 ) from main into develop

Generate BOM / Generate_BOM (push) Successful in 15s

Details

1dac01af29

Reviewed-on: #1

Update PCB + Sch

Generate BOM / Generate_BOM (push) Successful in 14s

Details

5b5d616e4c

AllSpiceAlice requested review from MikaChanical 2025-05-20 03:29:02 +00:00

AllSpiceAlice requested review from PavelInPurchasing 2025-05-20 03:29:02 +00:00

AllSpiceAlice requested review from daniel-allspice 2025-05-20 03:29:02 +00:00

MikaChanical reviewed 2025-05-20 03:36:28 +00:00

parallella.brd

MikaChanical commented

2025-05-20 03:36:28 +00:00

Member

@AllSpiceAlice, can you check the design spec for this connector position? It moved, but it's still not in the correct location. Can you track down the source of the incorrect position before fixing this? I'd like to keep this error from propagating into documentation.

!thumbnail[](parallella.brd){ diff="AllSpice-Demos/Cadence-System-Capture-Demo:59a3e45856df4717fd20eb5cc7d1d362951b2226...5b5d616e4cb81299fdcaf1675a82216258d14b81" pr="2" layers="81,82,66,41,64,39,38,36,34,57" diff-visibility="full" variant="default" view-coords="15.5,74.3,40.1,94.9" aspect-ratio="1.475" } @AllSpiceAlice, can you check the design spec for this connector position? It moved, but it's still not in the correct location. Can you track down the source of the incorrect position before fixing this? I'd like to keep this error from propagating into documentation.

RevaReviewa added the

priority/5 - critical

labels 2025-05-20 03:44:52 +00:00

RevaReviewa added this to the V3 Project update milestone 2025-05-20 03:44:56 +00:00

RevaReviewa reviewed 2025-05-20 03:48:11 +00:00

parallella.sdax

RevaReviewa commented

2025-05-20 03:48:11 +00:00

Member

@daniel-allspice, can you create a quick slide for Monday's team meeting on annotation best practices. With all due respect, I think some of the newer team members could use some tutorial on good documentation. 1. This needs to be captured as an issue, this needs to be added to the requirements table, otherwise we can't add it. This is the equivalent of a TBD. Thank you 🍨

!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Cadence-System-Capture-Demo:59a3e45856df4717fd20eb5cc7d1d362951b2226...5b5d616e4cb81299fdcaf1675a82216258d14b81" pr="2" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="32.3,6.9,50.3,22.1" aspect-ratio="1.320" } @daniel-allspice, can you create a quick slide for Monday's team meeting on annotation best practices. With all due respect, I think some of the newer team members could use some tutorial on good documentation. 1. This needs to be captured as an issue, this needs to be added to the requirements table, otherwise we can't add it. This is the equivalent of a TBD. </rant> Thank you 🍨

allspice-thomas commented

2025-09-05 14:13:50 +00:00

Owner

Fixed this

PavelInPurchasing reviewed 2025-05-20 04:06:58 +00:00

parallella.sdax

PavelInPurchasing commented

2025-05-20 03:55:15 +00:00

Member

@AllSpiceAlice, this part number changed, but not to something on the Approved parts list? Can you update your Actions to check against the APL? For now, pick something manually so we can update our planning ASAP. 🙏 🚀

!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Cadence-System-Capture-Demo:59a3e45856df4717fd20eb5cc7d1d362951b2226...5b5d616e4cb81299fdcaf1675a82216258d14b81" pr="2" doc-id="1debcbe71fa0156db005" diff-visibility="full" variant="default" view-coords="60.1,49.1,74.8,62.3" aspect-ratio="1.318" } @AllSpiceAlice, this part number changed, but not to something on the Approved parts list? Can you update your Actions to check against the APL? For now, pick something manually so we can update our planning ASAP. 🙏 🚀

brendan marked this conversation as resolved

RevaReviewa reviewed 2025-05-20 04:10:10 +00:00

parallella.sdax

RevaReviewa commented

2025-05-20 04:10:10 +00:00

Member

@daniel-allspice , can you update the firmware team about this new Power fault flag? The checks can't check if the signals aren't added. 🥫 💯

RevaReviewa reviewed 2025-05-20 04:32:53 +00:00

parallella.brd

RevaReviewa commented

2025-05-20 04:32:53 +00:00

Member

@AllSpiceAlice , 1) Can you fix these giant traces on the BGA? 2) Can you figure out how only SOME of the traces got updated and why they weren't all affected? I'm worried this might happen again.

!thumbnail[](parallella.brd){ diff="AllSpice-Demos/Cadence-System-Capture-Demo:59a3e45856df4717fd20eb5cc7d1d362951b2226...5b5d616e4cb81299fdcaf1675a82216258d14b81" pr="2" layers="81,82,1,67,42,65,40,37,35,33,34,57" diff-visibility="full" variant="default" view-coords="30.7,29.9,61.9,68.7" aspect-ratio="1.475" } @AllSpiceAlice , 1) Can you fix these giant traces on the BGA? 2) Can you figure out how only SOME of the traces got updated and why they weren't all affected? I'm worried this might happen again.

MikaChanical reviewed 2025-05-20 04:38:11 +00:00

parallella.brd

MikaChanical commented

2025-05-20 04:38:11 +00:00

Member

@daniel-allspice, I think this signal is part of a differential pair. Do we need to match it's pair with more symmetry, or can it handle this amount of mismatch?

!thumbnail[](parallella.brd){ diff="AllSpice-Demos/Cadence-System-Capture-Demo:59a3e45856df4717fd20eb5cc7d1d362951b2226...5b5d616e4cb81299fdcaf1675a82216258d14b81" pr="2" layers="3" diff-visibility="full" variant="default" view-coords="24.2,35.2,47.4,56.5" aspect-ratio="1.475" } @daniel-allspice, I think this signal is part of a differential pair. Do we need to match it's pair with more symmetry, or can it handle this amount of mismatch?

Screenshot 2025-05-19 at 11.35.58 PM.png

86 KiB