AllSpice-Demos/Cyclone-HDL-Demo
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AllSpiceAlice commented 2025-07-30 21:33:10 +00:00
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Resolved Issues

  • Closes #9

  • Closes #3

  • Closes #5

  • Add protection to endstops

  • Add LEDs to Fans

Design Review Checklist

Process
  • Commits in correct branch @gautam at 3/19/25 @ 14:00
  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained
System
  • Power
    • Sufficient power supplied from upstream source
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • I/Os are specified
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review
Components
  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power
Schematics
  • Document
    • Dot on each connection
    • No four-point connections
    • Title block completed for each sheet
    • All components have reference designators and values
    • Multi-part components don't have unplaced symbols
    • Page title present and consistent on all pages if not in title block
    • Symbols identify open collector/drain pins and internal pulled up/down pins
    • Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
    • Components follow preferred reference designator pattern
  • External I/O
    • Filtered for EMI
    • Protected against electrostatic discharge (ESD)
    • Unused inputs terminated
  • Microcontrollers / ICs
    • Predictable or controlled power-up state
      • Reset filtered
    • Sufficient bypass capacitance
    • Oscillators checked for reliable startup
    • Pullups on open-collector pins
    • Logic-low and logic-high voltage levels checked
    • No-connect pins labeled NC
    • Clock lines with series/parallel termination
    • Check for latchup & off-voltage
    • Check datasheet errata/apnotes
  • Busses
    • UART/USART TX->RX and RX<-TX
    • I2C pullups per capacitance
    • Bus timing checked
  • Analog
    • Adequate power rails
    • Amplifier stability
    • Rate-of-rise/fall checked
  • General
    • Bulk capacitance
    • Polarized components
    • Reverse voltage on electrolytics
    • Cap derating for MTBF
    • LDO capacitance
    • Comparator slew/timing
    • Opamp common mode input range
    • Custom part pin verification
    • BJT base-emitter reverse current
    • Consistent power net names
    • Debug features included
PCB

  • Manufacturing

    • Requirements on fab layer
      • Plating: material + thickness
      • Stack-up, trace/space, hole size
      • PCB/silkscreen color
      • Impedance, blind/buried vias
      • Panelization, routing, drill table
      • Specs > tolerance
    • Power plane spacing minimized
    • Proper solder paste & fiducials

  • Footprints

    • Pin 1 marked
    • Polarity marked (diodes, LEDs, caps)
    • Dimensions vs datasheet
    • Thermal pads present

  • Placement

    • Accessible jumpers, debug
    • Correct resistor placement
    • SMPS loop minimized
    • Cap & driver proximity
    • SMT top / THT bottom

  • Clearance

    • Keep-outs honored
    • Clearance per voltage rating
    • Avoid edge components

  • Mechanical

    • CAD uploaded
    • Connector + harness clearance
    • Isolated mounting holes
    • Defined outline/enclosure
    • Rounded internal corners

  • Electrical

    • All nets routed
    • Analog/digital common joined once
    • ERC passes
    • Isolation barriers OK

  • Signal Integrity

    • Ground plane gaps minimized
    • No gaps under high-speed signals
    • No stubs, impedance matched pairs
    • Terminated lines
    • Short crystal paths
    • Guard ring
    • Avoid under/noisy components
    • RF via fencing < 1/20 λ
    • Shield can option

  • Copper Pour

    • All planes poured
    • No high-impedance paths
    • No pour between IC pins

  • Traces

    • Oblique trace angles
    • Correct width/via size
    • No pin-to-pin shortcuts
    • Smooth bends for impedance

  • Thermal

    • Separate heat sources
    • Thermal vias in pads

  • Testing

    • Critical test points added
    • Ground near analog test points

  • Silk screen

    • Rev, date, serial space
    • No silk on pads/vias
    • 2-direction readable text
    • Legible font
    • Connector pinouts
    • Fuse specs
    • Functional groups
    • Test points, LEDs, buttons, jumpers labeled
## Resolved Issues - Closes #9 - Closes #3 - Closes #5 - Add protection to endstops - Add LEDs to Fans ## Design Review Checklist <details> <summary>Process</summary> - [x] Commits in correct branch @gautam at 3/19/25 @ 14:00 - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [x] Power - [ ] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [ ] Voltage - [ ] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [x] Components follow preferred reference designator pattern - [x] External I/O - [x] Filtered for EMI - [x] Protected against electrostatic discharge (ESD) - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Predictable or controlled power-up state - [x] Reset filtered - [x] Sufficient bypass capacitance - [x] Oscillators checked for reliable startup - [x] Pullups on open-collector pins - [x] Logic-low and logic-high voltage levels checked - [x] No-connect pins labeled NC - [x] Clock lines with series/parallel termination - [x] Check for latchup & off-voltage - [x] Check datasheet errata/apnotes - [ ] Busses - [ ] UART/USART TX->RX and RX<-TX - [ ] I2C pullups [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Bus timing checked - [x] Analog - [x] Adequate power rails - [x] Amplifier stability - [x] Rate-of-rise/fall checked - [ ] General - [ ] Bulk capacitance - [ ] Polarized components - [ ] Reverse voltage on electrolytics - [ ] Cap derating for MTBF - [x] LDO capacitance - [ ] Comparator slew/timing - [ ] Opamp common mode input range - [ ] Custom part pin verification - [ ] BJT base-emitter reverse current - [ ] Consistent power net names - [ ] Debug features included </details> <details> <summary>PCB</summary> - [x] Manufacturing - [x] Requirements on `fab` layer - [x] Plating: material + thickness - [x] Stack-up, trace/space, hole size - [x] PCB/silkscreen color - [x] Impedance, blind/buried vias - [x] Panelization, routing, drill table - [x] Specs > tolerance - [x] Power plane spacing minimized - [x] Proper solder paste & fiducials - [x] Footprints - [x] Pin 1 marked - [x] Polarity marked (diodes, LEDs, caps) - [x] Dimensions vs datasheet - [x] Thermal pads present - [x] Placement - [x] Accessible jumpers, debug - [x] Correct resistor placement - [x] SMPS loop minimized - [x] Cap & driver proximity - [x] SMT top / THT bottom - [x] Clearance - [x] Keep-outs honored - [x] Clearance per voltage rating - [x] Avoid edge components - [x] Mechanical - [x] CAD uploaded - [x] Connector + harness clearance - [x] Isolated mounting holes - [x] Defined outline/enclosure - [x] Rounded internal corners - [x] Electrical - [x] All nets routed - [x] Analog/digital common joined once - [x] ERC passes - [x] Isolation barriers OK - [x] Signal Integrity - [x] Ground plane gaps minimized - [x] No gaps under high-speed signals - [x] No stubs, impedance matched pairs - [x] Terminated lines - [x] Short crystal paths - [x] Guard ring - [x] Avoid under/noisy components - [x] RF via fencing < 1/20 λ - [x] Shield can option - [x] Copper Pour - [x] All planes poured - [x] No high-impedance paths - [x] No pour between IC pins - [x] Traces - [x] Oblique trace angles - [x] Correct width/via size - [x] No pin-to-pin shortcuts - [x] Smooth bends for impedance - [x] Thermal - [x] Separate heat sources - [x] Thermal vias in pads - [x] Testing - [x] Critical test points added - [x] Ground near analog test points - [ ] Silk screen - [x] Rev, date, serial space - [x] No silk on pads/vias - [ ] 2-direction readable text - [ ] Legible font - [ ] Connector pinouts - [ ] Fuse specs - [ ] Functional groups - [ ] Test points, LEDs, buttons, jumpers labeled </details> <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
AllSpiceAlice added 1 commit 2025-07-30 21:33:10 +00:00
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AllSpiceAlice reviewed 2025-07-30 21:54:02 +00:00
CycloneV_RunBMC_SCH/ssmc_runbmc.cpm
AllSpiceAlice commented 2025-07-30 21:54:02 +00:00
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@daniel-allspice , have we run a simulation across frequencies for this ferrite bead? We have runaway oscillation frequencies to worry about.

!thumbnail[](CycloneV_RunBMC_SCH/ssmc_runbmc.cpm){ view-coords="61.7,49.2,86.8,73.5" variant="default" aspect-ratio="1.559" doc-id="c2ad2c651480f9497ded" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...c8fff01dfc1a530420287b983e188375bc4193e9" pr="2" diff-visibility="full" } @daniel-allspice , have we run a simulation across frequencies for this ferrite bead? We have runaway oscillation frequencies to worry about.
AllSpiceAlice added 1 commit 2025-07-30 21:58:53 +00:00
PCB updates
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MikaChanical reviewed 2025-07-30 21:59:56 +00:00
CycloneV_RunBMC.brd
MikaChanical commented 2025-07-30 21:59:56 +00:00
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@daniel-allspice, thank you for moving this switch to match the mechanical spec. I'll close out the issue.

!thumbnail[](CycloneV_RunBMC.brd){ view-coords="57.0,40.2,66.2,60.1" layers="81,82,1,2,3,4,5,6,7,8,9,10,11,32,67,66,42,41,65,64,40,39,37,38,35,36,33,34,57" variant="default" aspect-ratio="1.315" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice, thank you for moving this switch to match the mechanical spec. I'll close out the issue.
MikaChanical reviewed 2025-07-30 22:01:43 +00:00
CycloneV_RunBMC.brd
MikaChanical commented 2025-07-30 22:01:42 +00:00
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@daniel-allspice , can you move RB21 again? It's too close to the edge of the board still. Great job moving it away from the connector.

!thumbnail[](CycloneV_RunBMC.brd){ view-coords="22.7,7.7,29.8,14.6" layers="81,82,1,2,3,4,5,6,7,8,9,10,11,32,67,66,42,41,65,64,40,39,37,38,35,36,33,34,57" variant="default" aspect-ratio="1.315" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice , can you move RB21 again? It's too close to the edge of the board still. Great job moving it away from the connector.
MikaChanical reviewed 2025-07-30 22:05:12 +00:00
CycloneV_RunBMC.brd
MikaChanical commented 2025-07-30 22:05:12 +00:00
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@daniel-allspice, can you add a visual marking with the distance to the mounting hole? We have a number of the old units in the field and I'd like it to be obvious if this is fixed. Let's also make a giant arrow to Pin 1

!thumbnail[](CycloneV_RunBMC.brd){ view-coords="5.2,77.2,26.6,91.7" layers="65,40,37,33,57,103" variant="default" aspect-ratio="1.315" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice, can you add a visual marking with the distance to the mounting hole? We have a number of the old units in the field and I'd like it to be obvious if this is fixed. Let's also make a giant arrow to Pin 1
RevaReviewa reviewed 2025-07-30 22:08:24 +00:00
CycloneV_RunBMC_SCH/ssmc_runbmc.cpm
RevaReviewa commented 2025-07-30 22:08:24 +00:00
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@daniel-allspice, please add a design note why we removed this. The reference design from the previous rev is still in use and people are adding the same extra bypass caps.

!thumbnail[](CycloneV_RunBMC_SCH/ssmc_runbmc.cpm){ view-coords="17.3,47.2,83.3,72.9" variant="default" aspect-ratio="1.559" doc-id="d77b9dc16ce2f02d9ae2" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice, please add a design note why we removed this. The reference design from the previous rev is still in use and people are adding the same extra bypass caps.
RevaReviewa reviewed 2025-07-30 22:11:53 +00:00
CycloneV_RunBMC_SCH/ssmc_runbmc.cpm
RevaReviewa commented 2025-07-30 22:11:53 +00:00
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@daniel-allspice , can we add an attribute for "DNI" instead of using a separate component part number for populated vs non-populated components? It's less work. O(1) vs O(n2)

!thumbnail[](CycloneV_RunBMC_SCH/ssmc_runbmc.cpm){ view-coords="53.4,43.3,67.5,57.5" variant="default" aspect-ratio="1.559" doc-id="a16631fb7b90e1f612d2" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice , can we add an attribute for "DNI" instead of using a separate component part number for populated vs non-populated components? It's less work. O(1) vs O(n2)
PavelInPurchasing reviewed 2025-07-30 22:14:55 +00:00
CycloneV_RunBMC_SCH/ssmc_runbmc.cpm
PavelInPurchasing commented 2025-07-30 22:14:55 +00:00
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@daniel-allspice, can you see which of the zero ohm resistors we can replace with traces? That $0.00 component is costing us $0.25 to place.

!thumbnail[](CycloneV_RunBMC_SCH/ssmc_runbmc.cpm){ view-coords="5.9,57.1,18.2,69.4" variant="default" aspect-ratio="1.559" doc-id="9cc92844db33deec9ea5" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice, can you see which of the zero ohm resistors we can replace with traces? That $0.00 component is costing us $0.25 to place.
PavelInPurchasing reviewed 2025-07-30 22:16:55 +00:00
CycloneV_RunBMC_SCH/ssmc_runbmc.cpm
PavelInPurchasing commented 2025-07-30 22:16:55 +00:00
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@daniel-allspice. The contractor is great, but they're using different part numbers for our common passives. Can you 1) replace the components from our APL? 2) Send the Approved parts list to the contractor so we don't have to swap them out again.

!thumbnail[](CycloneV_RunBMC_SCH/ssmc_runbmc.cpm){ view-coords="6.2,4.8,41.2,46.4" variant="default" aspect-ratio="1.559" doc-id="a0b9e4717566d7b9acab" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice. The contractor is great, but they're using different part numbers for our common passives. Can you 1) replace the components from our APL? 2) Send the Approved parts list to the contractor so we don't have to swap them out again.
RevaReviewa reviewed 2025-07-30 22:18:43 +00:00
CycloneV_RunBMC_SCH/ssmc_runbmc.cpm
RevaReviewa commented 2025-07-30 22:18:43 +00:00
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@daniel-allspice , can you update the layout notes for components that need to be placed closed to other components?

!thumbnail[](CycloneV_RunBMC_SCH/ssmc_runbmc.cpm){ view-coords="27.4,43.9,42.2,74.2" variant="default" aspect-ratio="1.559" doc-id="3c0597691125062808db" diff="AllSpice-Demos/Cyclone-HDL-Demo:63a5cf2ee0c9bb7fda471b6cf4a656243006a708...564ec5f6d9a59a0437dbb0d6689dc4550ee4c2ea" pr="2" diff-visibility="full" } @daniel-allspice , can you update the layout notes for components that need to be placed closed to other components?
AllSpiceAlice added 1 commit 2025-07-31 16:12:12 +00:00
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AllSpiceAlice requested review from daniel-allspice 2025-07-31 16:19:31 +00:00
AllSpiceAlice requested review from gautam 2025-07-31 16:19:32 +00:00
AllSpiceAlice requested review from MikaChanical 2025-07-31 16:19:32 +00:00
AllSpiceAlice requested review from PavelInPurchasing 2025-07-31 16:19:33 +00:00
AllSpiceAlice requested review from RevaReviewa 2025-07-31 16:19:33 +00:00
AllSpiceAlice added this to the V2 Cost reduction - High Volume release milestone 2025-07-31 20:59:16 +00:00
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AllSpiceAlice added 1 commit 2025-08-04 17:02:05 +00:00
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allspice-thomas requested review from allspice-thomas 2025-11-19 19:09:30 +00:00
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