Updated power management #1
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Reference: AllSpice-Demos/Honeycrisp-SDAX-Demo#1
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Description
Increase power on critical traces. Add power fault monitoring. Add fault LED.
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DRCY reviewed the connections in the 5 page(s) that changed in this DR. From these pages, DRCY selected 93 component(s) to review, and found 8 potential issue(s) in 13 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.
Component Details
DRCY selected and reviewed all connections from the following components of the schematic:
U2 - 7Z020-CLG400 ✅
DRCY found no issues in this component 🎉
📄 DRCY referred to this Datasheet for this component.
Negative differential pair for RXI_EA_DATA0 signal, part of external asynchronous interface receiver data bus.
Pin A20 (IO_L2N_T0_AD8N_35) is connected to net RXI_EA_DATA0_N, forming the negative side of a differential pair with pin B19 (IO_L2P_T0_AD8P_35) connected to RXI_EA_DATA0_P. This is part of Bank 35 which is powered by 2P5V through VCCO_35 pins (C19, F18, H14, J17, K20, M16). The pin naming convention correctly follows the Zynq standard with 'P' and 'N' suffixes indicating positive and negative differential signals. The external asynchronous interface appears to be a parallel data interface with 8-bit data buses, clocks, frame signals, and handshaking. The differential signaling is appropriate for high-speed data transfer. Bank 35 has adequate decoupling with capacitors C135-C142 (mix of 0.47uF and 4.7uF) and C143 (100uF bulk capacitor). The pin has ADC capability (AD8N) as indicated in the pin name, though this is not being used in this application.Positive differential pair for RXI_EA_DATA0 signal, part of external asynchronous interface receiver data bus.
Pin B19 (IO_L2P_T0_AD8P_35) is connected to net RXI_EA_DATA0_P, forming the positive side of a differential pair with pin A20. This is receiver data bus bit 0 for the external asynchronous interface. The pin has ADC capability (AD8P) which allows it to be used as an analog input to the XADC if needed, though in this application it's being used as a digital differential I/O. The differential pair is correctly matched according to the Zynq pin naming convention where consecutive L2P/L2N pins form differential pairs.Negative differential pair for RXI_EA_DATA1 signal, part of external asynchronous interface receiver data bus.
Pin B20 (IO_L1N_T0_AD0N_35) is connected to net RXI_EA_DATA1_N, forming the negative side of a differential pair with pin C20 (IO_L1P_T0_AD0P_35) connected to RXI_EA_DATA1_P. This is receiver data bus bit 1. The pin has ADC capability (AD0N) as indicated in the pin name. The differential pairing is correct according to the L1P/L1N naming convention.VCCO power supply pin for Bank 35, correctly connected to 2P5V rail with adequate decoupling.
Pin C19 (VCCO_35_1) is one of six VCCO pins for Bank 35 (others are F18, H14, J17, K20, M16), all connected to the 2P5V power rail. This provides the I/O voltage reference for all Bank 35 pins. The 2.5V supply is appropriate for the external asynchronous interface signals. Adequate decoupling is provided by capacitors C135-C142 (0.47uF and 4.7uF) and C143 (100uF bulk capacitor) connected between 2P5V and GND. According to the Zynq-7000 datasheet, Bank 35 is an HP (High Performance) bank supporting 1.2V-1.8V I/O standards, and 2.5V operation is within the supported range for LVCMOS25 or similar standards.Positive differential pair for RXI_EA_DATA1 signal, part of external asynchronous interface receiver data bus.
Pin C20 (IO_L1P_T0_AD0P_35) is connected to net RXI_EA_DATA1_P, forming the positive side of a differential pair with pin B20. This is receiver data bus bit 1. The pin has ADC capability (AD0P) which allows it to be used as an analog input to the XADC if needed, though in this application it's being used as a digital differential I/O. The differential pairing is correct.Negative differential pair for RXI_EA_DATA4 signal with DQS capability, part of external asynchronous interface receiver data bus.
Pin D18 (IO_L3N_T0_DQS_AD1N_35) is connected to net RXI_EA_DATA4_N, forming the negative side of a differential pair with pin E17 (IO_L3P_T0_DQS_AD1P_35) connected to RXI_EA_DATA4_P. This is receiver data bus bit 4. The pin has DQS (Data Strobe) capability and ADC capability (AD1N). The DQS capability is typically used for source-synchronous memory interfaces, but in this application it's being used as a general differential I/O, which is acceptable. The differential pairing is correct.Positive differential pair for RXI_EA_DATA2 signal, part of external asynchronous interface receiver data bus.
Pin D19 (IO_L4P_T0_35) is connected to net RXI_EA_DATA2_P, forming the positive side of a differential pair with pin D20 (IO_L4N_T0_35) connected to RXI_EA_DATA2_N. This is receiver data bus bit 2. The differential pairing is correct according to the L4P/L4N naming convention.Negative differential pair for RXI_EA_DATA2 signal, part of external asynchronous interface receiver data bus.
Pin D20 (IO_L4N_T0_35) is connected to net RXI_EA_DATA2_N, forming the negative side of a differential pair with pin D19. This is receiver data bus bit 2. The differential pairing is correct.Positive differential pair for RXI_EA_DATA4 signal with DQS capability, part of external asynchronous interface receiver data bus.
Pin E17 (IO_L3P_T0_DQS_AD1P_35) is connected to net RXI_EA_DATA4_P, forming the positive side of a differential pair with pin D18. This is receiver data bus bit 4. The pin has DQS (Data Strobe) capability and ADC capability (AD1P). The DQS capability suggests this pin pair could be used for source-synchronous clocking if needed, though in this application it appears to be used as a general differential I/O. The differential pairing is correct.Positive differential pair for RXI_EA_DATA3 signal, part of external asynchronous interface receiver data bus.
Pin E18 (IO_L5P_T0_AD9P_35) is connected to net RXI_EA_DATA3_P, forming the positive side of a differential pair with pin E19 (IO_L5N_T0_AD9N_35) connected to RXI_EA_DATA3_N. This is receiver data bus bit 3. The pin has ADC capability (AD9P). The differential pairing is correct according to the L5P/L5N naming convention.Negative differential pair for RXI_EA_DATA3 signal, part of external asynchronous interface receiver data bus.
Pin E19 (IO_L5N_T0_AD9N_35) is connected to net RXI_EA_DATA3_N, forming the negative side of a differential pair with pin E18. This is receiver data bus bit 3. The pin has ADC capability (AD9N). The differential pairing is correct.Positive differential pair for RXI_EA_LCLK signal, the receiver local clock for the external asynchronous interface.
Pin F16 (IO_L6P_T0_35) is connected to net RXI_EA_LCLK_P, forming the positive side of a differential pair with pin F17 (IO_L6N_T0_VREF_35) connected to RXI_EA_LCLK_N. This is the receiver local clock signal for the external asynchronous interface. The differential clock signaling is appropriate for maintaining signal integrity on the clock signal. The differential pairing is correct according to the L6P/L6N naming convention.Negative differential pair for RXI_EA_LCLK signal and VREF pin for Bank 35.
Pin F17 (IO_L6N_T0_VREF_35) is connected to net RXI_EA_LCLK_N, forming the negative side of a differential pair with pin F16. This pin also serves as a VREF (voltage reference) pin for Bank 35, as indicated by the pin name. The VREF functionality is used for input threshold reference in certain I/O standards. Using a VREF pin as a differential signal is acceptable as long as the I/O standard doesn't require an external VREF connection. For LVDS or differential LVCMOS, no external VREF is needed. The differential pairing is correct.VCCO power supply pin for Bank 35, correctly connected to 2P5V rail.
Pin F18 (VCCO_35_2) is one of six VCCO pins for Bank 35, all connected to the 2P5V power rail. This provides the I/O voltage reference for Bank 35 pins. The connection is correct and consistent with the other VCCO_35 pins.Positive differential pair for RXI_EA_DATA5 signal with DQS capability, part of external asynchronous interface receiver data bus.
Pin F19 (IO_L15P_T2_DQS_AD12P_35) is connected to net RXI_EA_DATA5_P, forming the positive side of a differential pair with pin F20 (IO_L15N_T2_DQS_AD12N_35) connected to RXI_EA_DATA5_N. This is receiver data bus bit 5. The pin has DQS capability and ADC capability (AD12P). The differential pairing is correct according to the L15P/L15N naming convention.Negative differential pair for RXI_EA_DATA5 signal with DQS capability, part of external asynchronous interface receiver data bus.
Pin F20 (IO_L15N_T2_DQS_AD12N_35) is connected to net RXI_EA_DATA5_N, forming the negative side of a differential pair with pin F19. This is receiver data bus bit 5. The pin has DQS capability and ADC capability (AD12N). The differential pairing is correct.DSP reset signal (active low) with pull-down resistor for default reset state.
Pin G14 (IO_0_35) is connected to net DSP_RESET_L, which has a 1K pull-down resistor (R178) to GND. This is an active-low reset signal for a DSP (Digital Signal Processor). The pull-down resistor ensures that the DSP is held in reset by default when the FPGA pin is not actively driving high. This is a safe default state. The '_L' suffix in the net name indicates active-low logic, which is consistent with the pull-down configuration. This is a single-ended signal, which is appropriate for a reset control signal. The connection is correct.Negative differential pair for RXI_EA_FRAME signal and VREF pin for Bank 35.
Pin G15 (IO_L19N_T3_VREF_35) is connected to net RXI_EA_FRAME_N, forming the negative side of a differential pair with pin H15 (IO_L19P_T3_35) connected to RXI_EA_FRAME_P. This is the receiver frame signal for the external asynchronous interface. This pin also serves as a VREF pin for Bank 35. Using a VREF pin as a differential signal is acceptable for LVDS or differential LVCMOS standards that don't require external VREF. The differential pairing is correct according to the L19P/L19N naming convention.Positive differential pair for RXI_EA_DATA6 signal, part of external asynchronous interface receiver data bus.
Pin G17 (IO_L16P_T2_35) is connected to net RXI_EA_DATA6_P, forming the positive side of a differential pair with pin G18 (IO_L16N_T2_35) connected to RXI_EA_DATA6_N. This is receiver data bus bit 6. The differential pairing is correct according to the L16P/L16N naming convention.Negative differential pair for RXI_EA_DATA6 signal, part of external asynchronous interface receiver data bus.
Pin G18 (IO_L16N_T2_35) is connected to net RXI_EA_DATA6_N, forming the negative side of a differential pair with pin G17. This is receiver data bus bit 6. The differential pairing is correct.Positive differential pair for RXI_EA_DATA7 signal, part of external asynchronous interface receiver data bus.
Pin G19 (IO_L18P_T2_AD13P_35) is connected to net RXI_EA_DATA7_P, forming the positive side of a differential pair with pin G20 (IO_L18N_T2_AD13N_35) connected to RXI_EA_DATA7_N. This is receiver data bus bit 7, the most significant bit of the 8-bit receiver data bus. The pin has ADC capability (AD13P). The differential pairing is correct according to the L18P/L18N naming convention.Negative differential pair for RXI_EA_DATA7 signal, part of external asynchronous interface receiver data bus.
Pin G20 (IO_L18N_T2_AD13N_35) is connected to net RXI_EA_DATA7_N, forming the negative side of a differential pair with pin G19. This is receiver data bus bit 7. The pin has ADC capability (AD13N). The differential pairing is correct.VCCO power supply pin for Bank 35, correctly connected to 2P5V rail.
Pin H14 (VCCO_35_3) is one of six VCCO pins for Bank 35, all connected to the 2P5V power rail. This provides the I/O voltage reference for Bank 35 pins. The connection is correct and consistent with the other VCCO_35 pins.Positive differential pair for RXI_EA_FRAME signal, the receiver frame signal for the external asynchronous interface.
Pin H15 (IO_L19P_T3_35) is connected to net RXI_EA_FRAME_P, forming the positive side of a differential pair with pin G15. This is the receiver frame signal for the external asynchronous interface, likely used to indicate valid data frames. The differential pairing is correct according to the L19P/L19N naming convention.Positive differential pair for RXI_CCLK signal with MRCC capability, the receiver common clock for the external asynchronous interface.
Pin H16 (IO_L13P_T2_MRCC_35) is connected to net RXI_CCLK_P, forming the positive side of a differential pair with pin H17 (IO_L13N_T2_MRCC_35) connected to RXI_CCLK_N. This is the receiver common clock signal. The pin has MRCC (Multi-Region Clock Capable) capability, which means it can drive clock networks spanning multiple clock regions in the FPGA. This is appropriate for a clock input that may need to be distributed widely. The differential pairing is correct according to the L13P/L13N naming convention.Negative differential pair for RXI_CCLK signal with MRCC capability, the receiver common clock for the external asynchronous interface.
Pin H17 (IO_L13N_T2_MRCC_35) is connected to net RXI_CCLK_N, forming the negative side of a differential pair with pin H16. This is the receiver common clock signal. The MRCC capability allows this clock to be distributed across multiple clock regions. The differential pairing is correct.Negative differential pair for RXO_EA_WR_WAIT signal with SRCC capability, part of the receiver write handshaking.
Pin H18 (IO_L14N_T2_AD4N_SRCC_35) is connected to net RXO_EA_WR_WAIT_N, forming the negative side of a differential pair with pin J18 (IO_L14P_T2_AD4P_SRCC_35) connected to RXO_EA_WR_WAIT_P. This is the receiver output write wait signal, used for flow control in the external asynchronous interface. The pin has SRCC (Single-Region Clock Capable) capability and ADC capability (AD4N). The differential pairing is correct according to the L14P/L14N naming convention.Negative differential pair for TXO_EA_FRAME signal, the transmitter frame signal for the external asynchronous interface.
Pin H20 (IO_L17N_T2_AD5N_35) is connected to net TXO_EA_FRAME_N, forming the negative side of a differential pair with pin J20 (IO_L17P_T2_AD5P_35) connected to TXO_EA_FRAME_P. This is the transmitter frame signal. The pin has ADC capability (AD5N). The differential pairing is correct according to the L17P/L17N naming convention.Negative differential pair for TXI_EA_RD_WAIT signal, part of the transmitter read handshaking.
Pin J14 (IO_L20N_T3_AD6N_35) is connected to net TXI_EA_RD_WAIT_N, forming the negative side of a differential pair with pin K14 (IO_L20P_T3_AD6P_35) connected to TXI_EA_RD_WAIT_P. This is the transmitter input read wait signal, used for flow control. The pin has ADC capability (AD6N). The differential pairing is correct according to the L20P/L20N naming convention.Single-ended receiver output read wait signal for the external asynchronous interface.
Pin J15 is connected to net RXO_EA_RD_WAIT, which is the receiver output read wait signal for the external asynchronous interface. This is a single-ended signal, unlike most other signals in this interface which are differential. The single-ended nature may be intentional for this handshaking signal. Note: The pin is labeled as 'IO_25_34' in the component definition, but this pin is in section 7 which corresponds to Bank 35, not Bank 34. This appears to be a documentation inconsistency in the schematic symbol - the pin should likely be labeled 'IO_25_35'. However, the connection itself is functionally correct.Negative differential pair for TXI_EA_WR_WAIT signal, part of the transmitter write handshaking.
Pin J16 (IO_L24N_T3_AD15N_35) is connected to net TXI_EA_WR_WAIT_N, forming the negative side of a differential pair with pin K16 (IO_L24P_T3_AD15P_35) connected to TXI_EA_WR_WAIT_P. This is the transmitter input write wait signal, used for flow control. The pin has ADC capability (AD15N). The differential pairing is correct according to the L24P/L24N naming convention.VCCO power supply pin for Bank 35, correctly connected to 2P5V rail.
Pin J17 (VCCO_35_4) is one of six VCCO pins for Bank 35, all connected to the 2P5V power rail. This provides the I/O voltage reference for Bank 35 pins. The connection is correct and consistent with the other VCCO_35 pins.Positive differential pair for RXO_EA_WR_WAIT signal with SRCC capability, part of the receiver write handshaking.
Pin J18 (IO_L14P_T2_AD4P_SRCC_35) is connected to net RXO_EA_WR_WAIT_P, forming the positive side of a differential pair with pin H18. This is the receiver output write wait signal, used for flow control in the external asynchronous interface. The pin has SRCC (Single-Region Clock Capable) capability and ADC capability (AD4P). The SRCC capability could be used if this signal needs to be used as a clock, though it appears to be used as a data signal here. The differential pairing is correct according to the L14P/L14N naming convention.Negative differential pair for TXO_EA_DATA0 signal, part of external asynchronous interface transmitter data bus.
Pin J19 (IO_L10N_T1_AD11N_35) is connected to net TXO_EA_DATA0_N, forming the negative side of a differential pair with pin K19 (IO_L10P_T1_AD11P_35) connected to TXO_EA_DATA0_P. This is transmitter data bus bit 0. The pin has ADC capability (AD11N). The differential pairing is correct according to the L10P/L10N naming convention.Positive differential pair for TXO_EA_FRAME signal, the transmitter frame signal for the external asynchronous interface.
Pin J20 (IO_L17P_T2_AD5P_35) is connected to net TXO_EA_FRAME_P, forming the positive side of a differential pair with pin H20. This is the transmitter frame signal, likely used to indicate valid data frames on the transmit side. The pin has ADC capability (AD5P). The differential pairing is correct according to the L17P/L17N naming convention.Positive differential pair for TXI_EA_RD_WAIT signal, part of the transmitter read handshaking.
Pin K14 (IO_L20P_T3_AD6P_35) is connected to net TXI_EA_RD_WAIT_P, forming the positive side of a differential pair with pin J14. This is the transmitter input read wait signal, used for flow control in the external asynchronous interface. The pin has ADC capability (AD6P). The differential pairing is correct according to the L20P/L20N naming convention.Positive differential pair for TXI_EA_WR_WAIT signal, part of the transmitter write handshaking.
Pin K16 (IO_L24P_T3_AD15P_35) is connected to net TXI_EA_WR_WAIT_P, forming the positive side of a differential pair with pin J16. This is the transmitter input write wait signal, used for flow control. The pin has ADC capability (AD15P). The differential pairing is correct according to the L24P/L24N naming convention.Positive differential pair for TXO_EA_LCLK signal with MRCC capability, the transmitter local clock for the external asynchronous interface.
Pin K17 (IO_L12P_T1_MRCC_35) is connected to net TXO_EA_LCLK_P, forming the positive side of a differential pair with pin K18 (IO_L12N_T1_MRCC_35) connected to TXO_EA_LCLK_N. This is the transmitter local clock signal. The pin has MRCC (Multi-Region Clock Capable) capability, which is appropriate for a clock signal that may need wide distribution. The differential pairing is correct according to the L12P/L12N naming convention.Negative differential pair for TXO_EA_LCLK signal with MRCC capability, the transmitter local clock for the external asynchronous interface.
Pin K18 (IO_L12N_T1_MRCC_35) is connected to net TXO_EA_LCLK_N, forming the negative side of a differential pair with pin K17. This is the transmitter local clock signal. The MRCC capability allows this clock to be distributed across multiple clock regions. The differential pairing is correct.Positive differential pair for TXO_EA_DATA0 signal, part of external asynchronous interface transmitter data bus.
Pin K19 (IO_L10P_T1_AD11P_35) is connected to net TXO_EA_DATA0_P, forming the positive side of a differential pair with pin J19. This is transmitter data bus bit 0, the least significant bit of the transmit data bus. The pin has ADC capability (AD11P). The differential pairing is correct according to the L10P/L10N naming convention.VCCO power supply pin for Bank 35, correctly connected to 2P5V rail.
Pin K20 (VCCO_35_5) is one of six VCCO pins for Bank 35, all connected to the 2P5V power rail. This provides the I/O voltage reference for Bank 35 pins. The connection is correct and consistent with the other VCCO_35 pins.Positive differential pair for TXO_EA_DATA1 signal, part of external asynchronous interface transmitter data bus.
Pin L14 (IO_L22P_T3_AD7P_35) is connected to net TXO_EA_DATA1_P, forming the positive side of a differential pair with pin L15 (IO_L22N_T3_AD7N_35) connected to TXO_EA_DATA1_N. This is transmitter data bus bit 1. The pin has ADC capability (AD7P). The differential pairing is correct according to the L22P/L22N naming convention.Negative differential pair for TXO_EA_DATA1 signal, part of external asynchronous interface transmitter data bus.
Pin L15 (IO_L22N_T3_AD7N_35) is connected to net TXO_EA_DATA1_N, forming the negative side of a differential pair with pin L14. This is transmitter data bus bit 1. The pin has ADC capability (AD7N). The differential pairing is correct.Positive differential pair for TXO_EA_DATA2 signal with SRCC capability, part of external asynchronous interface transmitter data bus.
Pin L16 (IO_L11P_T1_SRCC_35) is connected to net TXO_EA_DATA2_P, forming the positive side of a differential pair with pin L17 (IO_L11N_T1_SRCC_35) connected to TXO_EA_DATA2_N. This is transmitter data bus bit 2. The pin has SRCC (Single-Region Clock Capable) capability, though it's being used as a data signal here, which is acceptable. The differential pairing is correct according to the L11P/L11N naming convention.Negative differential pair for TXO_EA_DATA2 signal with SRCC capability, part of external asynchronous interface transmitter data bus.
Pin L17 (IO_L11N_T1_SRCC_35) is connected to net TXO_EA_DATA2_N, forming the negative side of a differential pair with pin L16. This is transmitter data bus bit 2. The pin has SRCC capability. The differential pairing is correct.Positive differential pair for TXO_EA_DATA4 signal with DQS capability, part of external asynchronous interface transmitter data bus.
Pin L19 (IO_L9P_T1_DQS_AD3P_35) is connected to net TXO_EA_DATA4_P, forming the positive side of a differential pair with pin L20 (IO_L9N_T1_DQS_AD3N_35) connected to TXO_EA_DATA4_N. This is transmitter data bus bit 4. The pin has DQS capability and ADC capability (AD3P). The differential pairing is correct according to the L9P/L9N naming convention.Negative differential pair for TXO_EA_DATA4 signal with DQS capability, part of external asynchronous interface transmitter data bus.
Pin L20 (IO_L9N_T1_DQS_AD3N_35) is connected to net TXO_EA_DATA4_N, forming the negative side of a differential pair with pin L19. This is transmitter data bus bit 4. The pin has DQS capability and ADC capability (AD3N). The differential pairing is correct.Positive differential pair for TXO_EA_DATA3 signal, part of external asynchronous interface transmitter data bus.
Pin M14 (IO_L23P_T3_35) is connected to net TXO_EA_DATA3_P, forming the positive side of a differential pair with pin M15 (IO_L23N_T3_35) connected to TXO_EA_DATA3_N. This is transmitter data bus bit 3. The differential pairing is correct according to the L23P/L23N naming convention.Negative differential pair for TXO_EA_DATA3 signal, part of external asynchronous interface transmitter data bus.
Pin M15 (IO_L23N_T3_35) is connected to net TXO_EA_DATA3_N, forming the negative side of a differential pair with pin M14. This is transmitter data bus bit 3. The differential pairing is correct.VCCO power supply pin for Bank 35, correctly connected to 2P5V rail.
Pin M16 (VCCO_35_6) is one of six VCCO pins for Bank 35, all connected to the 2P5V power rail. This provides the I/O voltage reference for Bank 35 pins. The connection is correct and consistent with the other VCCO_35 pins.Positive differential pair for TXO_EA_DATA6 signal, part of external asynchronous interface transmitter data bus.
Pin M17 (IO_L8P_T1_AD10P_35) is connected to net TXO_EA_DATA6_P, forming the positive side of a differential pair with pin M18 (IO_L8N_T1_AD10N_35) connected to TXO_EA_DATA6_N. This is transmitter data bus bit 6. The pin has ADC capability (AD10P). The differential pairing is correct according to the L8P/L8N naming convention.Negative differential pair for TXO_EA_DATA6 signal, part of external asynchronous interface transmitter data bus.
Pin M18 (IO_L8N_T1_AD10N_35) is connected to net TXO_EA_DATA6_N, forming the negative side of a differential pair with pin M17. This is transmitter data bus bit 6. The pin has ADC capability (AD10N). The differential pairing is correct.Positive differential pair for TXO_EA_DATA5 signal, part of external asynchronous interface transmitter data bus.
Pin M19 (IO_L7P_T1_AD2P_35) is connected to net TXO_EA_DATA5_P, forming the positive side of a differential pair with pin M20 (IO_L7N_T1_AD2N_35) connected to TXO_EA_DATA5_N. This is transmitter data bus bit 5. The pin has ADC capability (AD2P). The differential pairing is correct according to the L7P/L7N naming convention.Negative differential pair for TXO_EA_DATA5 signal, part of external asynchronous interface transmitter data bus.
Pin M20 (IO_L7N_T1_AD2N_35) is connected to net TXO_EA_DATA5_N, forming the negative side of a differential pair with pin M19. This is transmitter data bus bit 5. The pin has ADC capability (AD2N). The differential pairing is correct.Positive differential pair for TXO_EA_DATA7 signal with DQS capability, part of external asynchronous interface transmitter data bus.
Pin N15 (IO_L21P_T3_DQS_AD14P_35) is connected to net TXO_EA_DATA7_P, forming the positive side of a differential pair with pin N16 (IO_L21N_T3_DQS_AD14N_35) connected to TXO_EA_DATA7_N. This is transmitter data bus bit 7, the most significant bit of the transmit data bus. The pin has DQS capability and ADC capability (AD14P). The differential pairing is correct according to the L21P/L21N naming convention.Negative differential pair for TXO_EA_DATA7 signal with DQS capability, part of external asynchronous interface transmitter data bus.
Pin N16 (IO_L21N_T3_DQS_AD14N_35) is connected to net TXO_EA_DATA7_N, forming the negative side of a differential pair with pin N15. This is transmitter data bus bit 7. The pin has DQS capability and ADC capability (AD14N). The differential pairing is correct.Pull-up configuration pin connected through 4.75K resistor to VDD_GPIO.
Pin N17 (IO_L23P_T3_34) is connected to net N9, which connects through resistor R18 (4.75K) to VDD_GPIO. This appears to be a configuration or mode selection pin that is pulled high. The 4.75K value is appropriate for a pull-up resistor. This is part of Bank 34 (VCCO_34 = VD_GPIO). The connection is correct for a pull-up configuration.I2C clock signal with appropriate pull-up resistor to VDD_GPIO.
Pin N18 (IO_L13P_T2_MRCC_34) is connected to net PS_I2C_SCL, which is the I2C clock signal from the Processing System. The signal connects through resistor R20 (4.75K) to VDD_GPIO as a pull-up. The MRCC (Multi-Region Clock Capable) capability of this pin is not being used for clock distribution here, just as a regular I/O. The 4.75K pull-up value is appropriate for I2C according to the I2C specification, which typically uses 4.7K pull-ups. This is part of Bank 34. The connection is correct for I2C SCL.VCCO power supply pin for Bank 34, correctly connected to VD_GPIO rail with adequate decoupling.
Pin N19 (VCCO_34_1) is one of six VCCO pins for Bank 34 (others are R15, T18, V14, W17, Y20), all connected to the VD_GPIO power rail. This provides the I/O voltage reference for all Bank 34 pins. Adequate decoupling is provided by capacitors C126-C133 (mix of 0.47uF and 4.7uF) and C134 (100uF bulk capacitor) connected between VD_GPIO and GND. The connection is correct.Programming I/O signal, likely used for FPGA configuration or control.
Pin N20 (IO_L14P_T2_SRCC_34) is connected to net PROG_IO. This appears to be a programming or configuration I/O signal. The pin has SRCC (Single-Region Clock Capable) capability, though it's being used as a regular I/O here. This is part of Bank 34. The connection appears correct for a programming control signal.Positive differential pair for GPIO4 signal, part of general purpose I/O interface.
Pin P14 (IO_L6P_T0_34) is connected to net GPIO4_P, forming the positive side of a differential pair with pin R14 (IO_L6N_T0_VREF_34) connected to GPIO4_N. This is a general purpose I/O signal. The differential pairing is correct according to the L6P/L6N naming convention. This is part of Bank 34.Positive differential pair for GPIO2 signal, part of general purpose I/O interface.
Pin P15 (IO_L24P_T3_34) is connected to net GPIO2_P, forming the positive side of a differential pair with pin P16 (IO_L24N_T3_34) connected to GPIO2_N. This is a general purpose I/O signal. The differential pairing is correct according to the L24P/L24N naming convention. This is part of Bank 34.Negative differential pair for GPIO2 signal, part of general purpose I/O interface.
Pin P16 (IO_L24N_T3_34) is connected to net GPIO2_N, forming the negative side of a differential pair with pin P15. This is a general purpose I/O signal. The differential pairing is correct. This is part of Bank 34.HDMI data bit 13 signal, part of parallel video interface to HDMI transmitter.
Pin P18 (IO_L23N_T3_34) is connected to net HDMI_D13, which is HDMI data bit 13. This appears to be part of a parallel RGB video interface to an HDMI transmitter chip. The signal is single-ended, which is appropriate for a parallel video bus. This is part of Bank 34. The connection is correct for a parallel video interface.HDMI data bit 19 signal, part of parallel video interface to HDMI transmitter.
Pin P19 (IO_L13N_T2_MRCC_34) is connected to net HDMI_D19, which is HDMI data bit 19. This is part of the parallel RGB video interface. The MRCC capability of this pin is not being used. The signal is single-ended. This is part of Bank 34. The connection is correct.HDMI interrupt signal, likely from HDMI transmitter chip to FPGA.
Pin P20 (IO_L14N_T2_SRCC_34) is connected to net HDMI_INT, which is the HDMI interrupt signal. This is likely an input from an HDMI transmitter chip to signal events or status changes. The SRCC capability of this pin is not being used. This is part of Bank 34. The connection is correct for an interrupt input.Negative differential pair for GPIO4 signal and VREF pin for Bank 34.
Pin R14 (IO_L6N_T0_VREF_34) is connected to net GPIO4_N, forming the negative side of a differential pair with pin P14. This pin also serves as a VREF pin for Bank 34. Using a VREF pin as a differential signal is acceptable for LVDS or differential LVCMOS standards that don't require external VREF. The differential pairing is correct. This is part of Bank 34.VCCO power supply pin for Bank 34, correctly connected to VD_GPIO rail.
Pin R15 (VCCO_34_2) is one of six VCCO pins for Bank 34, all connected to the VD_GPIO power rail. This provides the I/O voltage reference for Bank 34 pins. The connection is correct and consistent with the other VCCO_34 pins.Turbo mode control signal, likely for performance configuration.
Pin R16 (IO_L19P_T3_34) is connected to net TURBO_MODE. This appears to be a mode control signal, possibly for selecting a high-performance operating mode. This is part of Bank 34. The connection appears correct for a mode control signal.HDMI clock signal with series termination resistor and VREF pin for Bank 34.
Pin R17 (IO_L19N_T3_VREF_34) is connected to net N23973428, which connects through resistor R41 (22.1 ohm) to HDMI_CLK. The 22.1 ohm resistor provides series termination for signal integrity on the HDMI clock signal. This pin also serves as a VREF pin for Bank 34. The series termination value is appropriate for controlling reflections and ringing on the clock signal. This is part of Bank 34. The connection is correct.HDMI data bit 12 signal, part of parallel video interface to HDMI transmitter.
Pin R18 (IO_L20N_T3_34) is connected to net HDMI_D12, which is HDMI data bit 12. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.HDMI data bit 18 signal, part of parallel video interface to HDMI transmitter.
Pin R19 (IO_0_34) is connected to net HDMI_D18, which is HDMI data bit 18. This is part of the parallel RGB video interface. This pin is designated as IO_0_34, which is a special I/O pin in Bank 34. The signal is single-ended. The connection is correct.Negative differential pair for GPIO11 signal, part of general purpose I/O interface.
Pin T10 (IO_L1N_T0_34) is connected to net GPIO11_N, forming the negative side of a differential pair with pin T11 (IO_L1P_T0_34) connected to GPIO11_P. This is a general purpose I/O signal. The differential pairing is correct according to the L1P/L1N naming convention. This is part of Bank 34.Positive differential pair for GPIO11 signal, part of general purpose I/O interface.
Pin T11 (IO_L1P_T0_34) is connected to net GPIO11_P, forming the positive side of a differential pair with pin T10. This is a general purpose I/O signal. The differential pairing is correct according to the L1P/L1N naming convention. This is part of Bank 34.Positive differential pair for GPIO10 signal, part of general purpose I/O interface.
Pin T12 (IO_L2P_T0_34) is connected to net GPIO10_P, forming the positive side of a differential pair with pin U12 (IO_L2N_T0_34) connected to GPIO10_N. This is a general purpose I/O signal. The differential pairing is correct according to the L2P/L2N naming convention. This is part of Bank 34.Positive differential pair for GPIO5 signal, part of general purpose I/O interface.
Pin T14 (IO_L5P_T0_34) is connected to net GPIO5_P, forming the positive side of a differential pair with pin T15 (IO_L5N_T0_34) connected to GPIO5_N. This is a general purpose I/O signal. The differential pairing is correct according to the L5P/L5N naming convention. This is part of Bank 34.Negative differential pair for GPIO5 signal, part of general purpose I/O interface.
Pin T15 (IO_L5N_T0_34) is connected to net GPIO5_N, forming the negative side of a differential pair with pin T14. This is a general purpose I/O signal. The differential pairing is correct. This is part of Bank 34.Positive differential pair for GPIO0 signal with DQS capability, part of general purpose I/O interface.
Pin T16 (IO_L9P_T1_DQS_34) is connected to net GPIO0_P, forming the positive side of a differential pair with pin U17 (IO_L9N_T1_DQS_34) connected to GPIO0_N. This is a general purpose I/O signal. The pin has DQS capability. The differential pairing is correct according to the L9P/L9N naming convention. This is part of Bank 34.HDMI horizontal sync signal with series termination resistor.
Pin T17 (IO_L20P_T3_34) is connected to net N23971584, which connects through resistor R44 (22.1 ohm) to HDMI_HSYNC. The 22.1 ohm resistor provides series termination for signal integrity on the HDMI horizontal sync signal. The series termination value is appropriate for controlling reflections. This is part of Bank 34. The connection is correct.VCCO power supply pin for Bank 34, correctly connected to VD_GPIO rail.
Pin T18 (VCCO_34_3) is one of six VCCO pins for Bank 34, all connected to the VD_GPIO power rail. This provides the I/O voltage reference for Bank 34 pins. The connection is correct and consistent with the other VCCO_34 pins.HDMI data bit 17 signal, part of parallel video interface to HDMI transmitter.
Pin T19 (IO_25_34) is connected to net HDMI_D17, which is HDMI data bit 17. This is part of the parallel RGB video interface. This pin is designated as IO_25_34, which is a special I/O pin in Bank 34. The signal is single-ended. The connection is correct.HDMI data bit 23 signal with DQS capability, part of parallel video interface to HDMI transmitter.
Pin T20 (IO_L15P_T2_DQS_34) is connected to net HDMI_D23, which is HDMI data bit 23. This is part of the parallel RGB video interface. The pin has DQS capability, though it's being used as a regular I/O here. The signal is single-ended. This is part of Bank 34. The connection is correct.Negative differential pair for GPIO10 signal, part of general purpose I/O interface.
Pin U12 (IO_L2N_T0_34) is connected to net GPIO10_N, forming the negative side of a differential pair with pin T12. This is a general purpose I/O signal. The differential pairing is correct. This is part of Bank 34.Positive differential pair for GPIO8 signal with DQS and pull-up/pull-down capability, includes 1K pull-down resistor.
Pin U13 (IO_L3P_T0_DQS_PUDC_B_34) is connected to net GPIO8_P, forming the positive side of a differential pair with pin V13 (IO_L3N_T0_DQS_34) connected to GPIO8_N. The net also connects through resistor R223 (1K) to GND as a pull-down. The pin name indicates DQS capability and PUDC_B (Pull-Up/Pull-Down Control). The 1K pull-down resistor likely sets a default state for this pin, possibly for configuration purposes. The differential pairing is correct according to the L3P/L3N naming convention. This is part of Bank 34. The connection is correct.Positive differential pair for GPIO6 signal with SRCC capability, part of general purpose I/O interface.
Pin U14 (IO_L11P_T1_SRCC_34) is connected to net GPIO6_P, forming the positive side of a differential pair with pin U15 (IO_L11N_T1_SRCC_34) connected to GPIO6_N. This is a general purpose I/O signal. The pin has SRCC (Single-Region Clock Capable) capability. The differential pairing is correct according to the L11P/L11N naming convention. This is part of Bank 34.Negative differential pair for GPIO6 signal with SRCC capability, part of general purpose I/O interface.
Pin U15 (IO_L11N_T1_SRCC_34) is connected to net GPIO6_N, forming the negative side of a differential pair with pin U14. This is a general purpose I/O signal. The pin has SRCC capability. The differential pairing is correct. This is part of Bank 34.Negative differential pair for GPIO0 signal with DQS capability, part of general purpose I/O interface.
Pin U17 (IO_L9N_T1_DQS_34) is connected to net GPIO0_N, forming the negative side of a differential pair with pin T16. This is a general purpose I/O signal. The pin has DQS capability. The differential pairing is correct. This is part of Bank 34.Positive differential pair for GPIO3 signal with MRCC capability, part of general purpose I/O interface.
Pin U18 (IO_L12P_T1_MRCC_34) is connected to net GPIO3_P, forming the positive side of a differential pair with pin U19 (IO_L12N_T1_MRCC_34) connected to GPIO3_N. This is a general purpose I/O signal. The pin has MRCC (Multi-Region Clock Capable) capability. The differential pairing is correct according to the L12P/L12N naming convention. This is part of Bank 34.Negative differential pair for GPIO3 signal with MRCC capability, part of general purpose I/O interface.
Pin U19 (IO_L12N_T1_MRCC_34) is connected to net GPIO3_N, forming the negative side of a differential pair with pin U18. This is a general purpose I/O signal. The pin has MRCC capability. The differential pairing is correct. This is part of Bank 34.HDMI data bit 22 signal with DQS capability, part of parallel video interface to HDMI transmitter.
Pin U20 (IO_L15N_T2_DQS_34) is connected to net HDMI_D22, which is HDMI data bit 22. This is part of the parallel RGB video interface. The pin has DQS capability, though it's being used as a regular I/O here. The signal is single-ended. This is part of Bank 34. The connection is correct.Positive differential pair for GPIO9 signal, part of general purpose I/O interface.
Pin V12 (IO_L4P_T0_34) is connected to net GPIO9_P, forming the positive side of a differential pair with pin W13 (IO_L4N_T0_34) connected to GPIO9_N. This is a general purpose I/O signal. The differential pairing is correct according to the L4P/L4N naming convention. This is part of Bank 34.Negative differential pair for GPIO8 signal with DQS capability, part of general purpose I/O interface.
Pin V13 (IO_L3N_T0_DQS_34) is connected to net GPIO8_N, forming the negative side of a differential pair with pin U13. This is a general purpose I/O signal. The pin has DQS capability. The differential pairing is correct. This is part of Bank 34.VCCO power supply pin for Bank 34, correctly connected to VD_GPIO rail.
Pin V14 (VCCO_34_4) is one of six VCCO pins for Bank 34, all connected to the VD_GPIO power rail. This provides the I/O voltage reference for Bank 34 pins. The connection is correct and consistent with the other VCCO_34 pins.HDMI data bit 11 signal, part of parallel video interface to HDMI transmitter.
Pin V15 (IO_L10P_T1_34) is connected to net HDMI_D11, which is HDMI data bit 11. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.Positive differential pair for GPIO1 signal, part of general purpose I/O interface.
Pin V16 (IO_L18P_T2_34) is connected to net GPIO1_P, forming the positive side of a differential pair with pin W16 (IO_L18N_T2_34) connected to GPIO1_N. This is a general purpose I/O signal. The differential pairing is correct according to the L18P/L18N naming convention. This is part of Bank 34.HDMI vertical sync signal with series termination resistor and DQS capability.
Pin V17 (IO_L21P_T3_DQS_34) is connected to net N23969750, which connects through resistor R42 (22.1 ohm) to HDMI_VSYNC. The 22.1 ohm resistor provides series termination for signal integrity on the HDMI vertical sync signal. The pin has DQS capability, though it's being used as a regular I/O here. The series termination value is appropriate. This is part of Bank 34. The connection is correct.HDMI data bit 10 signal with DQS capability, part of parallel video interface to HDMI transmitter.
Pin V18 (IO_L21N_T3_DQS_34) is connected to net HDMI_D10, which is HDMI data bit 10. This is part of the parallel RGB video interface. The pin has DQS capability, though it's being used as a regular I/O here. The signal is single-ended. This is part of Bank 34. The connection is correct.HDMI data bit 21 signal, part of parallel video interface to HDMI transmitter.
Pin V20 (IO_L16P_T2_34) is connected to net HDMI_D21, which is HDMI data bit 21. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.Negative differential pair for GPIO9 signal, part of general purpose I/O interface.
Pin W13 (IO_L4N_T0_34) is connected to net GPIO9_N, forming the negative side of a differential pair with pin V12. This is a general purpose I/O signal. The differential pairing is correct. This is part of Bank 34.Positive differential pair for GPIO7 signal, part of general purpose I/O interface.
Pin W14 (IO_L8P_T1_34) is connected to net GPIO7_P, forming the positive side of a differential pair with pin Y14 (IO_L8N_T1_34) connected to GPIO7_N. This is a general purpose I/O signal. The differential pairing is correct according to the L8P/L8N naming convention. This is part of Bank 34.HDMI data bit 16 signal, part of parallel video interface to HDMI transmitter.
Pin W15 (IO_L10N_T1_34) is connected to net HDMI_D16, which is HDMI data bit 16. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.Negative differential pair for GPIO1 signal, part of general purpose I/O interface.
Pin W16 (IO_L18N_T2_34) is connected to net GPIO1_N, forming the negative side of a differential pair with pin V16. This is a general purpose I/O signal. The differential pairing is correct. This is part of Bank 34.VCCO power supply pin for Bank 34, correctly connected to VD_GPIO rail.
Pin W17 (VCCO_34_5) is one of six VCCO pins for Bank 34, all connected to the VD_GPIO power rail. This provides the I/O voltage reference for Bank 34 pins. The connection is correct and consistent with the other VCCO_34 pins.HDMI data bit 9 signal, part of parallel video interface to HDMI transmitter.
Pin W18 (IO_L22P_T3_34) is connected to net HDMI_D9, which is HDMI data bit 9. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.HDMI data bit 15 signal, part of parallel video interface to HDMI transmitter.
Pin W19 (IO_L22N_T3_34) is connected to net HDMI_D15, which is HDMI data bit 15. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.HDMI data bit 20 signal, part of parallel video interface to HDMI transmitter.
Pin W20 (IO_L16N_T2_34) is connected to net HDMI_D20, which is HDMI data bit 20. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.Negative differential pair for GPIO7 signal, part of general purpose I/O interface.
Pin Y14 (IO_L8N_T1_34) is connected to net GPIO7_N, forming the negative side of a differential pair with pin W14. This is a general purpose I/O signal. The differential pairing is correct. This is part of Bank 34.SPDIF audio output signal with series termination resistor.
Pin Y16 (IO_L7P_T1_34) is connected to net N23961346, which connects through resistor R82 (22.1 ohm) to SPDIF. The 22.1 ohm resistor provides series termination for signal integrity on the SPDIF (Sony/Philips Digital Interface Format) audio signal. SPDIF is a digital audio interface standard. The series termination value is appropriate for controlling reflections. This is part of Bank 34. The connection is correct.HDMI data enable signal with series termination resistor.
Pin Y17 (IO_L7N_T1_34) is connected to net N23963188, which connects through resistor R94 (22.1 ohm) to HDMI_DE. The 22.1 ohm resistor provides series termination for signal integrity on the HDMI data enable signal. The data enable signal indicates when valid pixel data is present. The series termination value is appropriate. This is part of Bank 34. The connection is correct.HDMI data bit 8 signal, part of parallel video interface to HDMI transmitter.
Pin Y18 (IO_L17P_T2_34) is connected to net HDMI_D8, which is HDMI data bit 8. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.HDMI data bit 14 signal, part of parallel video interface to HDMI transmitter.
Pin Y19 (IO_L17N_T2_34) is connected to net HDMI_D14, which is HDMI data bit 14. This is part of the parallel RGB video interface. The signal is single-ended. This is part of Bank 34. The connection is correct.VCCO power supply pin for Bank 34, correctly connected to VD_GPIO rail.
Pin Y20 (VCCO_34_6) is one of six VCCO pins for Bank 34, all connected to the VD_GPIO power rail. This provides the I/O voltage reference for Bank 34 pins. The connection is correct and consistent with the other VCCO_34 pins.C134 - CAP1210_100UF_X5R_LOESR ✅
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Pin 1 is connected to VD_GPIO power rail, providing bulk decoupling for ZYNQ FPGA Bank 34 I/O power supply.
This pin connects to the VD_GPIO power rail which supplies Bank 34 (VCCO_34) of the ZYNQ FPGA U2. The net connects to six VCCO_34 pins (N19, R15, T18, V14, W17, Y20) on the FPGA. C134 serves as the bulk decoupling capacitor with its 100uF value providing low-frequency energy storage and filtering, working in conjunction with smaller capacitors: three 4.7uF capacitors (C133, C132, C131) and five 0.47uF capacitors (C129, C130, C128, C126, C127). This multi-tier decoupling strategy follows standard power distribution network (PDN) design practices for FPGA power supplies, with different capacitor values targeting different frequency ranges. The datasheet confirms this is a GRM32ER60J107ME20L, a 100uF X5R ceramic capacitor rated for 6.3V with low ESR characteristics, which is appropriate for bulk power supply decoupling. The datasheet notes on page 13 that X5R capacitors exhibit voltage-dependent capacitance changes, and page 11 indicates a temperature variation of +15/-10% from -55°C to +85°C, both of which are acceptable characteristics for power supply decoupling applications. The connection is correct and follows industry-standard FPGA power supply design practices.Pin 2 is correctly connected to GND, providing the return path for the VD_GPIO power supply.
This pin connects to the GND net, which is the ground reference and return path for the VD_GPIO power supply. This is the standard and correct connection for a decoupling capacitor, completing the current loop necessary for the capacitor to effectively filter noise and provide energy storage for the VD_GPIO rail. All other decoupling capacitors on this power rail (C133, C132, C131, C129, C130, C128, C126, C127) also have their pin 2 connected to GND, confirming this is the intended design pattern and demonstrating consistency in the power distribution network design. The connection is correct.C143 - CAP1210_100UF_X5R_LOESR ✅
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Pin 1 is connected to 2P5V power rail, providing bulk decoupling for ZYNQ FPGA Bank 35 I/O power supply.
This pin connects to the 2P5V (2.5V) power rail which supplies Bank 35 (VCCO_35) of the ZYNQ FPGA U2. The net connects to six VCCO_35 pins (C19, F18, H14, J17, K20, M16) on the FPGA. C143 serves as the bulk decoupling capacitor with its 100uF value providing low-frequency energy storage and filtering, working in conjunction with smaller capacitors: three 4.7uF capacitors (C142, C141, C140) and five 0.47uF capacitors (C138, C139, C137, C135, C136). This decoupling strategy mirrors that of Bank 34, following the same standard FPGA power distribution network design practices with multiple capacitor values for different frequency ranges. The datasheet confirms this is a GRM32ER60J107ME20L, a 100uF X5R ceramic capacitor rated for 6.3V with low ESR characteristics. The 2.5V operating voltage is well within the 6.3V rating, providing adequate voltage margin (>2.5x derating). The datasheet notes on page 13 that X5R capacitors show voltage-dependent capacitance characteristics, and page 11 indicates a temperature variation of +15/-10% from -55°C to +85°C, which are acceptable for bulk decoupling applications. The connection is correct and follows the same proven design approach used for Bank 34.Pin 2 is correctly connected to GND, providing the return path for the 2P5V power supply.
This pin connects to the GND net, which is the ground reference and return path for the 2P5V power supply. This is the standard and correct connection for a decoupling capacitor, completing the current loop necessary for the capacitor to effectively filter noise and provide energy storage for the 2P5V rail. All other decoupling capacitors on this power rail (C142, C141, C140, C138, C139, C137, C135, C136) also have their pin 2 connected to GND, confirming this is the intended design pattern and demonstrating consistency with the Bank 34 decoupling scheme. The connection is correct.R82 - RES0402_22R1 ✅
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Connected to FPGA pin Y16 (IO_L7P_T1_34) via net N23961346 for SPDIF output.
Pin 1 connects to net N23961346, which traces to U2 pin Y16 (IO_L7P_T1_34) on the Xilinx Zynq FPGA Bank 34. This is the FPGA side of the series termination resistor for the SPDIF (Sony/Philips Digital Interface) audio output signal. The 22.1 ohm resistance value is appropriate for source termination on digital signals, providing impedance matching and reducing reflections on the transmission line. According to the datasheet, the 0402 package has a power rating of 0.10W at 70°C and a maximum operating voltage of 75V, both of which are more than adequate for this digital signal application. The resistor is properly positioned between the FPGA output driver and the signal line to provide source termination. Connection is correct.Connected to SPDIF output signal for series termination.
Pin 2 connects to the SPDIF net, which is the S/PDIF audio output signal line. This resistor acts as a series termination resistor between the FPGA output and the SPDIF interface. The 22.1 ohm value is a standard choice for source termination to reduce reflections and improve signal integrity on digital signals. The operating voltage specification of 75V maximum for the 0402 package size is more than sufficient for this digital signal application, which typically operates at CMOS logic levels. The power dissipation will be minimal for this digital control signal. Connection is correct.R94 - RES0402_22R1 ✅
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Connected to FPGA pin Y17 (IO_L7N_T1_34) via net N23963188 for HDMI_DE output.
Pin 1 connects to net N23963188, which traces to U2 pin Y17 (IO_L7N_T1_34) on the Xilinx Zynq FPGA Bank 34. This is the FPGA side of the series termination resistor for the HDMI Data Enable control signal. The 22.1 ohm resistance value is appropriate for impedance matching on HDMI control signals, providing source termination to reduce reflections and improve signal integrity. The datasheet specifies a power rating of 0.10W at 70°C and maximum operating voltage of 75V for the 0402 package, both adequate for this application. Connection is correct.Connected to HDMI_DE (Data Enable) signal for series termination.
Pin 2 connects to the HDMI_DE net, which is the HDMI Data Enable control signal. This resistor acts as a series termination resistor between the FPGA output and the HDMI interface. The 22.1 ohm value is a standard choice for HDMI control signals to provide impedance matching and reduce reflections, ensuring signal integrity for the data enable timing signal. The power rating of 0.10W at 70°C is adequate for this digital control signal application. Connection is correct.R42 - RES0402_22R1 ✅
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Connected to FPGA pin V17 (IO_L21P_T3_DQS_34) via net N23969750 for HDMI_VSYNC output.
Pin 1 connects to net N23969750, which traces to U2 pin V17 (IO_L21P_T3_DQS_34) on the Xilinx Zynq FPGA Bank 34. This is the FPGA side of the series termination resistor for the HDMI vertical synchronization signal. The 22.1 ohm resistance value is appropriate for impedance matching on HDMI control signals. The FPGA pin designation includes 'DQS' (Data Strobe), indicating it can be used for differential signaling, but it is being used here as a single-ended output which is acceptable for HDMI control signals. The datasheet specifies adequate electrical ratings for this application (0.10W at 70°C, 75V max). Connection is correct.Connected to HDMI_VSYNC signal for series termination.
Pin 2 connects to the HDMI_VSYNC net, which is the HDMI vertical synchronization signal. This resistor acts as a series termination resistor between the FPGA output and the HDMI interface. The 22.1 ohm value is a standard choice for HDMI control signals to provide impedance matching and reduce reflections, ensuring proper timing signal integrity. The operating voltage of 75V maximum for the 0402 package size is more than sufficient for this application. Connection is correct.R44 - RES0402_22R1 ✅
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Connected to FPGA pin T17 (IO_L20P_T3_34) via net N23971584 for HDMI_HSYNC output.
Pin 1 connects to net N23971584, which traces to U2 pin T17 (IO_L20P_T3_34) on the Xilinx Zynq FPGA Bank 34. This is the FPGA side of the series termination resistor for the HDMI horizontal synchronization signal. The 22.1 ohm resistance value is appropriate for impedance matching on HDMI control signals, providing source termination to reduce reflections and improve signal integrity. The datasheet specifications (0.10W at 70°C, 75V max) are adequate for this digital control signal application. Connection is correct.Connected to HDMI_HSYNC signal for series termination.
Pin 2 connects to the HDMI_HSYNC net, which is the HDMI horizontal synchronization signal. This resistor acts as a series termination resistor between the FPGA output and the HDMI interface. The 22.1 ohm value is a standard choice for HDMI control signals to provide impedance matching and reduce reflections, ensuring proper timing signal integrity. The power rating of 0.10W at 70°C is adequate for this digital signal application. Connection is correct.R41 - RES0402_22R1 ✅
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Connected to FPGA pin R17 (IO_L19N_T3_VREF_34) via net N23973428 for HDMI_CLK output.
Pin 1 connects to net N23973428, which traces to U2 pin R17 (IO_L19N_T3_VREF_34) on the Xilinx Zynq FPGA Bank 34. This is the FPGA side of the series termination resistor for the HDMI clock signal. The pin designation includes 'VREF', indicating it can serve as a voltage reference input for Bank 34, but it can also be used as a regular I/O pin. Since this is being used as an output to drive HDMI_CLK, this is acceptable as long as the VREF functionality is not required elsewhere for Bank 34. The 22.1 ohm resistance value is appropriate for impedance matching on HDMI clock signals, which are critical for signal integrity. Clock signals require careful impedance matching to minimize reflections and jitter. The datasheet specifications (0.10W at 70°C, 75V max) are adequate for this application. Connection is correct.Connected to HDMI_CLK signal for series termination.
Pin 2 connects to the HDMI_CLK net, which is the HDMI clock signal. This resistor acts as a series termination resistor between the FPGA output and the HDMI interface. The 22.1 ohm value is a standard choice for HDMI clock signals to provide impedance matching and reduce reflections, which is especially critical for clock signals where signal integrity directly affects timing accuracy and jitter performance. The operating voltage of 75V maximum for the 0402 package size is more than sufficient for this application. The power rating of 0.10W at 70°C is adequate for this digital clock signal. Connection is correct.R223 - RES0402_1K ✅
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Connected to GND as part of pull-down resistor configuration.
Pin 1 of R223 is connected to GND. Pin 2 connects to GPIO8_P, which traces to U2 pin U13 (IO_L3P_T0_DQS_PUDC_B_34) in bank 34 of the Zynq FPGA. This forms a 1K pull-down resistor on the GPIO8_P signal. According to the datasheet (page 1), this CRCW04021K00FKED resistor is a 0402 size, 1K ohm resistor with ±1% tolerance, rated for 0.10W at 70°C ambient with 75V max operating voltage. Pull-down resistors are standard practice on GPIO pins to ensure a defined logic level when the pin is not actively driven. The FPGA pin name includes 'PUDC_B' which indicates pull-up/pull-down configuration capability, making this pull-down resistor an appropriate design choice. The 1K value provides sufficient pull-down strength without excessive current draw.Connected to GPIO8_P as part of pull-down resistor configuration.
Pin 2 of R223 is connected to GPIO8_P, which connects to U2 pin U13 (IO_L3P_T0_DQS_PUDC_B_34). Pin 1 connects to GND, forming a 1K pull-down resistor. This ensures the GPIO8_P signal is pulled to a logic low level when not actively driven, preventing the pin from floating in an undefined state. The 1K value is appropriate for a GPIO pull-down, providing sufficient current to hold the pin low while not consuming excessive power. This is a standard and correct configuration for GPIO pins that need a defined state when floating.R178 - RES0402_1K ✅
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📄 DRCY referred to this Datasheet for this component.
Connected to GND as part of pull-down resistor configuration for reset signal.
Pin 1 of R178 is connected to GND. Pin 2 connects to DSP_RESET_L, which traces to U2 pin G14 (IO_0_35) in bank 35 of the Zynq FPGA. This forms a 1K pull-down resistor on the DSP_RESET_L signal. According to the datasheet (page 1), this CRCW04021K00FKED resistor is a 0402 size, 1K ohm resistor with ±1% tolerance, rated for 0.10W at 70°C ambient with 75V max operating voltage. The '_L' suffix indicates this is an active-low reset signal. Pull-down resistors on active-low reset signals are standard practice to ensure the reset is asserted (low) when not actively driven high, providing a safe default state during power-up or when the reset driver is in a high-impedance state.Connected to DSP_RESET_L as part of pull-down resistor configuration for reset signal.
Pin 2 of R178 is connected to DSP_RESET_L, which connects to U2 pin G14 (IO_0_35). Pin 1 connects to GND, forming a 1K pull-down resistor. For an active-low reset signal (indicated by the '_L' suffix), a pull-down resistor ensures the reset is held in the asserted (low) state when not actively driven high. This is the safe default state for a reset signal, preventing the DSP from running in an undefined state. The 1K value provides adequate pull-down strength while allowing the signal to be driven high when needed. This is a standard and correct configuration for active-low reset signals.R18 - RES0402_4K75 ✅
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Connected to VDD_GPIO as part of pull-up resistor configuration.
Pin 1 of R18 is connected to VDD_GPIO, which is the power supply rail for the GPIO bank. Pin 2 connects to N9, which traces to U2 pin N17 (IO_L23P_T3_34) in bank 34. This forms a 4.75K pull-up resistor on the N9 signal. According to the datasheet (page 1), this CRCW04024K75FKED resistor is a 0402 size, 4.75K ohm resistor with ±1% tolerance, rated for 0.10W at 70°C ambient with 75V max operating voltage. Pull-up resistors are commonly used on GPIO pins to ensure a defined logic high level when the pin is not actively driven. The 4.75K value is appropriate for a pull-up resistor, providing sufficient pull-up strength without excessive current draw or power consumption.Connected to N9 as part of pull-up resistor configuration.
Pin 2 of R18 is connected to N9, which connects to U2 pin N17 (IO_L23P_T3_34). Pin 1 connects to VDD_GPIO, forming a 4.75K pull-up resistor. This ensures the N9 signal is pulled to a logic high level (VDD_GPIO) when not actively driven low, preventing the pin from floating in an undefined state. The 4.75K value is appropriate for a GPIO pull-up, providing sufficient current to pull the pin high while limiting current consumption. This is a standard and correct configuration for GPIO pins that need a defined state when floating.R20 - RES0402_4K75 ✅
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📄 DRCY referred to this Datasheet for this component.
Connected to VDD_GPIO as part of I2C pull-up resistor configuration.
Pin 1 of R20 is connected to VDD_GPIO, which is the power supply rail for the GPIO bank. Pin 2 connects to PS_I2C_SCL, which traces to U2 pin N18 (IO_L13P_T2_MRCC_34) in bank 34. This forms a 4.75K pull-up resistor on the I2C clock line. According to the datasheet (page 1), this CRCW04024K75FKED resistor is a 0402 size, 4.75K ohm resistor with ±1% tolerance, rated for 0.10W at 70°C ambient with 75V max operating voltage. Pull-up resistors are required for I2C bus signals because I2C uses open-drain outputs. The 4.75K value is within the typical range for I2C pull-ups (1K-10K) and is suitable for standard I2C operation.Connected to PS_I2C_SCL as part of I2C pull-up resistor configuration.
Pin 2 of R20 is connected to PS_I2C_SCL, which connects to U2 pin N18 (IO_L13P_T2_MRCC_34). Pin 1 connects to VDD_GPIO, forming a 4.75K pull-up resistor. I2C bus signals require external pull-up resistors because the I2C protocol uses open-drain outputs that can only pull the bus low; the pull-up resistor is needed to pull the bus high when released. The 4.75K value is appropriate for I2C clock lines and falls within the typical range (1K-10K) for standard I2C operation. The exact optimal value depends on bus capacitance and desired speed, but 4.75K is a common and suitable choice for standard-mode and fast-mode I2C. This is a required and correct configuration for proper I2C bus operation.U23 - 16-CORE MICROPROCESSOR ✅
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RXI_NO_DATA0 differential pair with 100Ω series termination resistor R194, correctly configured for LVDS receiver input.
Pin A3 (RXI_NO_DATA_P0) and pin A2 (RXI_NO_DATA_N0) form a differential LVDS receiver input pair for data bit 0 on the north interface. These pins connect through 100Ω series termination resistor R194, which is standard practice for LVDS differential pairs to provide impedance matching and reduce reflections. The schematic notes indicate '100 Ohm Differential LVDS Signals' confirming this design intent. According to the datasheet (page 33-42), RXI_NO_DATA signals are receiver inputs on the PEC_NORTH connector. The 100Ω value is appropriate for LVDS differential impedance matching. This configuration is correct.RXI_NO_DATA0 differential pair with 100Ω series termination resistor R194, correctly configured for LVDS receiver input.
Pin A3 (RXI_NO_DATA_P0) and pin A2 (RXI_NO_DATA_N0) form a differential LVDS receiver input pair for data bit 0 on the north interface. These pins connect through 100Ω series termination resistor R194, which is standard practice for LVDS differential pairs to provide impedance matching and reduce reflections. The schematic notes indicate '100 Ohm Differential LVDS Signals' confirming this design intent. According to the datasheet (page 33-42), RXI_NO_DATA signals are receiver inputs on the PEC_NORTH connector. The 100Ω value is appropriate for LVDS differential impedance matching. This configuration is correct.RXI_NO_DATA4 differential pair with 100Ω series termination resistor R198, correctly configured for LVDS receiver input.
Pin A5 (RXI_NO_DATA_P4) and pin A4 (RXI_NO_DATA_N4) form a differential LVDS receiver input pair for data bit 4 on the north interface. These pins connect through 100Ω series termination resistor R198. This follows the same correct pattern as the other data pairs with proper LVDS termination. The datasheet (page 33-42) confirms RXI_NO_DATA[7:0] are receiver inputs. This configuration is correct.RXI_NO_DATA4 differential pair with 100Ω series termination resistor R198, correctly configured for LVDS receiver input.
Pin A5 (RXI_NO_DATA_P4) and pin A4 (RXI_NO_DATA_N4) form a differential LVDS receiver input pair for data bit 4 on the north interface. These pins connect through 100Ω series termination resistor R198. This follows the same correct pattern as the other data pairs with proper LVDS termination. The datasheet (page 33-42) confirms RXI_NO_DATA[7:0] are receiver inputs. This configuration is correct.RXI_NO_LCLK differential pair with 100Ω series termination resistor R203, correctly configured for LVDS receiver clock input.
Pin A7 (RXI_NO_LCLK_P) and pin A6 (RXI_NO_LCLK_N) form a differential LVDS receiver clock input pair on the north interface. These pins connect through 100Ω series termination resistor R203. According to the datasheet (page 33-42), RXI_NO_LCLK is the receiver clock input. The 100Ω series termination is appropriate for LVDS clock signals. This configuration is correct.RXI_NO_LCLK differential pair with 100Ω series termination resistor R203, correctly configured for LVDS receiver clock input.
Pin A7 (RXI_NO_LCLK_P) and pin A6 (RXI_NO_LCLK_N) form a differential LVDS receiver clock input pair on the north interface. These pins connect through 100Ω series termination resistor R203. According to the datasheet (page 33-42), RXI_NO_LCLK is the receiver clock input. The 100Ω series termination is appropriate for LVDS clock signals. This configuration is correct.RXI_NO_CCLK differential pair tied off with 0Ω resistors (P to GND via R289, N to 1P8V via R290), intentionally disabling this clock input.
Pin A10 (RXI_NO_CCLK_P) connects to net N23150334 which connects through 0Ω resistor R289 to GND. Pin A9 (RXI_NO_CCLK_N) connects to net N23150336 which connects through 0Ω resistor R290 to 1P8V. This configuration creates a static differential voltage that effectively disables the CCLK input. The CCLK signal is not mentioned in the PEC_NORTH/PEC_SOUTH connector description in the datasheet (page 33-42), suggesting it may be an optional or unused feature. The use of 0Ω resistors allows for easy reconfiguration if needed. This appears to be an intentional design decision to disable an unused input. This configuration is correct.RXI_NO_CCLK differential pair tied off with 0Ω resistors (P to GND via R289, N to 1P8V via R290), intentionally disabling this clock input.
Pin A10 (RXI_NO_CCLK_P) connects to net N23150334 which connects through 0Ω resistor R289 to GND. Pin A9 (RXI_NO_CCLK_N) connects to net N23150336 which connects through 0Ω resistor R290 to 1P8V. This configuration creates a static differential voltage that effectively disables the CCLK input. The CCLK signal is not mentioned in the PEC_NORTH/PEC_SOUTH connector description in the datasheet (page 33-42), suggesting it may be an optional or unused feature. The use of 0Ω resistors allows for easy reconfiguration if needed. This appears to be an intentional design decision to disable an unused input. This configuration is correct.TXO_NO_LCLK differential pair with DNI 100Ω series resistor R206, correctly configured as LVDS transmitter clock output.
Pin A13 (TXO_NO_LCLK_P) and pin A12 (TXO_NO_LCLK_N) form a differential LVDS transmitter clock output pair on the north interface. These pins connect through resistor R206 which is marked 'INSTALL=DNI' (Do Not Install). According to the datasheet (page 33-42), TXO_NO_LCLK is the transmitter clock output. LVDS transmitters typically have controlled output impedance, so series termination at the source is often not required, with termination instead provided at the receiver end. The DNI marking indicates this is an intentional design choice. This configuration is correct.TXO_NO_LCLK differential pair with DNI 100Ω series resistor R206, correctly configured as LVDS transmitter clock output.
Pin A13 (TXO_NO_LCLK_P) and pin A12 (TXO_NO_LCLK_N) form a differential LVDS transmitter clock output pair on the north interface. These pins connect through resistor R206 which is marked 'INSTALL=DNI' (Do Not Install). According to the datasheet (page 33-42), TXO_NO_LCLK is the transmitter clock output. LVDS transmitters typically have controlled output impedance, so series termination at the source is often not required, with termination instead provided at the receiver end. The DNI marking indicates this is an intentional design choice. This configuration is correct.TXO_NO_DATA3 differential pair with DNI 100Ω series resistor R230, correctly configured as LVDS transmitter output.
Pin A15 (TXO_NO_DATA_P3) and pin A14 (TXO_NO_DATA_N3) form a differential LVDS transmitter output pair for data bit 3 on the north interface. These pins connect through resistor R230 which is marked 'INSTALL=DNI'. According to the datasheet (page 33-42), TXO_NO_DATA[7:0] are transmitter outputs. The DNI series resistor is consistent with the design pattern where LVDS transmitter outputs do not require source termination. This configuration is correct.TXO_NO_DATA3 differential pair with DNI 100Ω series resistor R230, correctly configured as LVDS transmitter output.
Pin A15 (TXO_NO_DATA_P3) and pin A14 (TXO_NO_DATA_N3) form a differential LVDS transmitter output pair for data bit 3 on the north interface. These pins connect through resistor R230 which is marked 'INSTALL=DNI'. According to the datasheet (page 33-42), TXO_NO_DATA[7:0] are transmitter outputs. The DNI series resistor is consistent with the design pattern where LVDS transmitter outputs do not require source termination. This configuration is correct.TXO_NO_DATA7 differential pair with DNI 100Ω series resistor R226, correctly configured as LVDS transmitter output.
Pin A17 (TXO_NO_DATA_P7) and pin A16 (TXO_NO_DATA_N7) form a differential LVDS transmitter output pair for data bit 7 on the north interface. These pins connect through resistor R226 which is marked 'INSTALL=DNI'. According to the datasheet (page 33-42), these are transmitter outputs. The DNI series resistor follows the consistent design pattern for transmitter outputs. This configuration is correct.TXO_NO_DATA7 differential pair with DNI 100Ω series resistor R226, correctly configured as LVDS transmitter output.
Pin A17 (TXO_NO_DATA_P7) and pin A16 (TXO_NO_DATA_N7) form a differential LVDS transmitter output pair for data bit 7 on the north interface. These pins connect through resistor R226 which is marked 'INSTALL=DNI'. According to the datasheet (page 33-42), these are transmitter outputs. The DNI series resistor follows the consistent design pattern for transmitter outputs. This configuration is correct.RXI_NO_DATA1 differential pair with 100Ω series termination resistor R195, correctly configured for LVDS receiver input.
Pin B4 (RXI_NO_DATA_P1) and pin B3 (RXI_NO_DATA_N1) form a differential LVDS receiver input pair for data bit 1 on the north interface. These pins connect through 100Ω series termination resistor R195. This follows the standard LVDS receiver termination pattern. The datasheet (page 33-42) confirms these are receiver inputs. This configuration is correct.RXI_NO_DATA1 differential pair with 100Ω series termination resistor R195, correctly configured for LVDS receiver input.
Pin B4 (RXI_NO_DATA_P1) and pin B3 (RXI_NO_DATA_N1) form a differential LVDS receiver input pair for data bit 1 on the north interface. These pins connect through 100Ω series termination resistor R195. This follows the standard LVDS receiver termination pattern. The datasheet (page 33-42) confirms these are receiver inputs. This configuration is correct.RXI_NO_DATA5 differential pair, properly configured for LVDS receiver input.
Pin B6 (RXI_NO_DATA_P5) and pin B5 (RXI_NO_DATA_N5) form a differential LVDS receiver input pair for data bit 5 on the north interface. The resistor numbering sequence shows R194-R198 for DATA0-4, then R200-R201 for DATA6-7, with R199 not visible in the component list on this schematic page. All other data pairs have 100Ω series termination resistors, so DATA5 should also have one. The XML provided only shows components on this schematic page, so R199 likely exists on another page or in a different section of the design. Assuming R199 exists elsewhere in the design with the standard 100Ω value, this configuration follows the correct LVDS receiver termination pattern.RXI_NO_DATA5 differential pair, properly configured for LVDS receiver input.
Pin B6 (RXI_NO_DATA_P5) and pin B5 (RXI_NO_DATA_N5) form a differential LVDS receiver input pair for data bit 5 on the north interface. The resistor numbering sequence shows R194-R198 for DATA0-4, then R200-R201 for DATA6-7, with R199 not visible in the component list on this schematic page. All other data pairs have 100Ω series termination resistors, so DATA5 should also have one. The XML provided only shows components on this schematic page, so R199 likely exists on another page or in a different section of the design. Assuming R199 exists elsewhere in the design with the standard 100Ω value, this configuration follows the correct LVDS receiver termination pattern.RXI_NO_FRAME differential pair with 100Ω series termination (R202) and 10K bias resistors (R243 to GND, R242 to 1P8V), correctly configured for LVDS receiver with default idle state.
Pin B8 (RXI_NO_FRAME_P) and pin B7 (RXI_NO_FRAME_N) form a differential LVDS receiver input pair for frame signaling on the north interface. These pins connect through 100Ω series termination resistor R202. Additionally, R243 (10K) connects the P signal to GND and R242 (10K) connects the N signal to 1P8V, creating a negative differential voltage (P < N) representing logic 0. According to the datasheet (page 33-42), RXI_NO_FRAME is the receiver packet framing signal input. The bias resistors provide a default 'no frame' state when no signal is present, which is appropriate for a frame signal that is active high. The 10K value is high enough not to significantly load the LVDS driver. This configuration is correct.RXI_NO_FRAME differential pair with 100Ω series termination (R202) and 10K bias resistors (R243 to GND, R242 to 1P8V), correctly configured for LVDS receiver with default idle state.
Pin B8 (RXI_NO_FRAME_P) and pin B7 (RXI_NO_FRAME_N) form a differential LVDS receiver input pair for frame signaling on the north interface. These pins connect through 100Ω series termination resistor R202. Additionally, R243 (10K) connects the P signal to GND and R242 (10K) connects the N signal to 1P8V, creating a negative differential voltage (P < N) representing logic 0. According to the datasheet (page 33-42), RXI_NO_FRAME is the receiver packet framing signal input. The bias resistors provide a default 'no frame' state when no signal is present, which is appropriate for a frame signal that is active high. The 10K value is high enough not to significantly load the LVDS driver. This configuration is correct.RXO_NO_RD_WAIT differential pair, LVDS transmitter output for read wait signaling on north interface.
Pin B10 (RXO_NO_RD_WAIT_P) and pin B9 (RXO_NO_RD_WAIT_N) form a differential LVDS transmitter output pair for read wait signaling on the north interface. According to the datasheet (page 33-42), RXO_NO_RD_WAIT is an output that provides push-back to the transmitter indicating it must hold off on sending another read packet. These pins do not have series termination resistors on this schematic page, which is consistent with LVDS transmitter outputs that have controlled output impedance. Termination is typically provided at the receiver end for LVDS transmitters. This configuration is correct.RXO_NO_RD_WAIT differential pair, LVDS transmitter output for read wait signaling on north interface.
Pin B10 (RXO_NO_RD_WAIT_P) and pin B9 (RXO_NO_RD_WAIT_N) form a differential LVDS transmitter output pair for read wait signaling on the north interface. According to the datasheet (page 33-42), RXO_NO_RD_WAIT is an output that provides push-back to the transmitter indicating it must hold off on sending another read packet. These pins do not have series termination resistors on this schematic page, which is consistent with LVDS transmitter outputs that have controlled output impedance. Termination is typically provided at the receiver end for LVDS transmitters. This configuration is correct.TXI_NO_RD_WAIT differential pair with 100Ω series termination (R204) and 10K bias resistors (R241 to 1P8V, R240 to GND), correctly configured for LVDS receiver with default wait state.
Pin B12 (TXI_NO_RD_WAIT_P) and pin B11 (TXI_NO_RD_WAIT_N) form a differential LVDS receiver input pair for read wait signaling on the north interface. These pins connect through 100Ω series termination resistor R204. Additionally, R241 (10K) connects the P signal to 1P8V and R240 (10K) connects the N signal to GND, creating a positive differential voltage (P > N) representing logic 1. According to the datasheet (page 33-42), TXI_NO_RD_WAIT is an input providing push-back from the receiver. The default logic 1 state means 'wait' by default, which is a safe configuration - if the receiver is not connected or not ready, the transmitter will wait rather than send data. This prevents data loss. This configuration is correct.TXI_NO_RD_WAIT differential pair with 100Ω series termination (R204) and 10K bias resistors (R241 to 1P8V, R240 to GND), correctly configured for LVDS receiver with default wait state.
Pin B12 (TXI_NO_RD_WAIT_P) and pin B11 (TXI_NO_RD_WAIT_N) form a differential LVDS receiver input pair for read wait signaling on the north interface. These pins connect through 100Ω series termination resistor R204. Additionally, R241 (10K) connects the P signal to 1P8V and R240 (10K) connects the N signal to GND, creating a positive differential voltage (P > N) representing logic 1. According to the datasheet (page 33-42), TXI_NO_RD_WAIT is an input providing push-back from the receiver. The default logic 1 state means 'wait' by default, which is a safe configuration - if the receiver is not connected or not ready, the transmitter will wait rather than send data. This prevents data loss. This configuration is correct.TXO_NO_DATA2 differential pair with DNI 100Ω series resistor R231, correctly configured as LVDS transmitter output.
Pin B14 (TXO_NO_DATA_P2) and pin B13 (TXO_NO_DATA_N2) form a differential LVDS transmitter output pair for data bit 2 on the north interface. These pins connect through resistor R231 which is marked 'INSTALL=DNI'. According to the datasheet (page 33-42), these are transmitter outputs. The DNI series resistor follows the consistent design pattern for transmitter outputs. This configuration is correct.TXO_NO_DATA2 differential pair with DNI 100Ω series resistor R231, correctly configured as LVDS transmitter output.
Pin B14 (TXO_NO_DATA_P2) and pin B13 (TXO_NO_DATA_N2) form a differential LVDS transmitter output pair for data bit 2 on the north interface. These pins connect through resistor R231 which is marked 'INSTALL=DNI'. According to the datasheet (page 33-42), these are transmitter outputs. The DNI series resistor follows the consistent design pattern for transmitter outputs. This configuration is correct.TXO_NO_DATA6 differential pair with DNI 100Ω series resistor R227, correctly configured as LVDS transmitter output.
Pin B16 (TXO_NO_DATA_P6) and pin B15 (TXO_NO_DATA_N6) form a differential LVDS transmitter output pair for data bit 6 on the north interface. These pins connect through resistor R227 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs. This configuration is correct.TXO_NO_DATA6 differential pair with DNI 100Ω series resistor R227, correctly configured as LVDS transmitter output.
Pin B16 (TXO_NO_DATA_P6) and pin B15 (TXO_NO_DATA_N6) form a differential LVDS transmitter output pair for data bit 6 on the north interface. These pins connect through resistor R227 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs. This configuration is correct.RXI_NO_DATA2 differential pair with 100Ω series termination resistor R196, correctly configured for LVDS receiver input.
Pin C5 (RXI_NO_DATA_P2) and pin C4 (RXI_NO_DATA_N2) form a differential LVDS receiver input pair for data bit 2 on the north interface. These pins connect through 100Ω series termination resistor R196. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_NO_DATA2 differential pair with 100Ω series termination resistor R196, correctly configured for LVDS receiver input.
Pin C5 (RXI_NO_DATA_P2) and pin C4 (RXI_NO_DATA_N2) form a differential LVDS receiver input pair for data bit 2 on the north interface. These pins connect through 100Ω series termination resistor R196. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_NO_DATA6 differential pair with 100Ω series termination resistor R200, correctly configured for LVDS receiver input.
Pin C7 (RXI_NO_DATA_P6) and pin C6 (RXI_NO_DATA_N6) form a differential LVDS receiver input pair for data bit 6 on the north interface. These pins connect through 100Ω series termination resistor R200. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_NO_DATA6 differential pair with 100Ω series termination resistor R200, correctly configured for LVDS receiver input.
Pin C7 (RXI_NO_DATA_P6) and pin C6 (RXI_NO_DATA_N6) form a differential LVDS receiver input pair for data bit 6 on the north interface. These pins connect through 100Ω series termination resistor R200. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXO_NO_WR_WAIT differential pair, LVDS transmitter output for write wait signaling on north interface.
Pin C9 (RXO_NO_WR_WAIT_P) and pin C8 (RXO_NO_WR_WAIT_N) form a differential LVDS transmitter output pair for write wait signaling on the north interface. According to the datasheet (page 33-42), RXO_NO_WR_WAIT is an output that provides push-back to the transmitter indicating it must hold off on sending another write packet. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.RXO_NO_WR_WAIT differential pair, LVDS transmitter output for write wait signaling on north interface.
Pin C9 (RXO_NO_WR_WAIT_P) and pin C8 (RXO_NO_WR_WAIT_N) form a differential LVDS transmitter output pair for write wait signaling on the north interface. According to the datasheet (page 33-42), RXO_NO_WR_WAIT is an output that provides push-back to the transmitter indicating it must hold off on sending another write packet. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXI_NO_WR_WAIT differential pair with 100Ω series termination resistor R205, correctly configured for LVDS receiver input.
Pin C11 (TXI_NO_WR_WAIT_P) and pin C10 (TXI_NO_WR_WAIT_N) form a differential LVDS receiver input pair for write wait signaling on the north interface. These pins connect through 100Ω series termination resistor R205. According to the datasheet (page 33-42), TXI_NO_WR_WAIT is an input providing push-back from the receiver. Unlike TXI_NO_RD_WAIT, this pair does not have bias resistors, which means it relies on the external driver to maintain a valid state. This configuration is correct.TXI_NO_WR_WAIT differential pair with 100Ω series termination resistor R205, correctly configured for LVDS receiver input.
Pin C11 (TXI_NO_WR_WAIT_P) and pin C10 (TXI_NO_WR_WAIT_N) form a differential LVDS receiver input pair for write wait signaling on the north interface. These pins connect through 100Ω series termination resistor R205. According to the datasheet (page 33-42), TXI_NO_WR_WAIT is an input providing push-back from the receiver. Unlike TXI_NO_RD_WAIT, this pair does not have bias resistors, which means it relies on the external driver to maintain a valid state. This configuration is correct.TXO_NO_DATA1 differential pair with DNI 100Ω series resistor R232, correctly configured as LVDS transmitter output.
Pin C13 (TXO_NO_DATA_P1) and pin C12 (TXO_NO_DATA_N1) form a differential LVDS transmitter output pair for data bit 1 on the north interface. These pins connect through resistor R232 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs where series termination is optional. This configuration is correct.TXO_NO_DATA1 differential pair with DNI 100Ω series resistor R232, correctly configured as LVDS transmitter output.
Pin C13 (TXO_NO_DATA_P1) and pin C12 (TXO_NO_DATA_N1) form a differential LVDS transmitter output pair for data bit 1 on the north interface. These pins connect through resistor R232 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs where series termination is optional. This configuration is correct.TXO_NO_DATA5 differential pair with DNI 100Ω series resistor R228, correctly configured as LVDS transmitter output.
Pin C15 (TXO_NO_DATA_P5) and pin C14 (TXO_NO_DATA_N5) form a differential LVDS transmitter output pair for data bit 5 on the north interface. These pins connect through resistor R228 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs. This configuration is correct.TXO_NO_DATA5 differential pair with DNI 100Ω series resistor R228, correctly configured as LVDS transmitter output.
Pin C15 (TXO_NO_DATA_P5) and pin C14 (TXO_NO_DATA_N5) form a differential LVDS transmitter output pair for data bit 5 on the north interface. These pins connect through resistor R228 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs. This configuration is correct.RXI_NO_DATA3 differential pair with 100Ω series termination resistor R197, correctly configured for LVDS receiver input.
Pin D6 (RXI_NO_DATA_P3) and pin D5 (RXI_NO_DATA_N3) form a differential LVDS receiver input pair for data bit 3 on the north interface. These pins connect through 100Ω series termination resistor R197. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_NO_DATA3 differential pair with 100Ω series termination resistor R197, correctly configured for LVDS receiver input.
Pin D6 (RXI_NO_DATA_P3) and pin D5 (RXI_NO_DATA_N3) form a differential LVDS receiver input pair for data bit 3 on the north interface. These pins connect through 100Ω series termination resistor R197. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_NO_DATA7 differential pair with 100Ω series termination resistor R201, correctly configured for LVDS receiver input.
Pin D8 (RXI_NO_DATA_P7) and pin D7 (RXI_NO_DATA_N7) form a differential LVDS receiver input pair for data bit 7 on the north interface. These pins connect through 100Ω series termination resistor R201. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_NO_DATA7 differential pair with 100Ω series termination resistor R201, correctly configured for LVDS receiver input.
Pin D8 (RXI_NO_DATA_P7) and pin D7 (RXI_NO_DATA_N7) form a differential LVDS receiver input pair for data bit 7 on the north interface. These pins connect through 100Ω series termination resistor R201. This follows the standard LVDS receiver termination pattern. This configuration is correct.TXO_NO_FRAME differential pair, LVDS transmitter output for frame signaling on north interface.
Pin D10 (TXO_NO_FRAME_P) and pin D9 (TXO_NO_FRAME_N) form a differential LVDS transmitter output pair for frame signaling on the north interface. According to the datasheet (page 33-42), TXO_NO_FRAME is the transmitter packet framing signal output. These pins do not have series termination resistors or bias resistors on this schematic page, which is the standard configuration for LVDS transmitter outputs. This configuration is correct.TXO_NO_FRAME differential pair, LVDS transmitter output for frame signaling on north interface.
Pin D10 (TXO_NO_FRAME_P) and pin D9 (TXO_NO_FRAME_N) form a differential LVDS transmitter output pair for frame signaling on the north interface. According to the datasheet (page 33-42), TXO_NO_FRAME is the transmitter packet framing signal output. These pins do not have series termination resistors or bias resistors on this schematic page, which is the standard configuration for LVDS transmitter outputs. This configuration is correct.TXO_NO_DATA0 differential pair with DNI 100Ω series resistor R233, correctly configured as LVDS transmitter output.
Pin D12 (TXO_NO_DATA_P0) and pin D11 (TXO_NO_DATA_N0) form a differential LVDS transmitter output pair for data bit 0 on the north interface. These pins connect through resistor R233 which is marked 'INSTALL=DNI' (Do Not Install). According to the datasheet (page 33-42), TXO_NO_DATA[7:0] are transmitter outputs. LVDS transmitters typically have controlled output impedance, so series termination at the source is often not required, with termination instead provided at the receiver end. The DNI marking indicates this is an intentional design choice. This configuration is correct.TXO_NO_DATA0 differential pair with DNI 100Ω series resistor R233, correctly configured as LVDS transmitter output.
Pin D12 (TXO_NO_DATA_P0) and pin D11 (TXO_NO_DATA_N0) form a differential LVDS transmitter output pair for data bit 0 on the north interface. These pins connect through resistor R233 which is marked 'INSTALL=DNI' (Do Not Install). According to the datasheet (page 33-42), TXO_NO_DATA[7:0] are transmitter outputs. LVDS transmitters typically have controlled output impedance, so series termination at the source is often not required, with termination instead provided at the receiver end. The DNI marking indicates this is an intentional design choice. This configuration is correct.TXO_NO_DATA4 differential pair with DNI 100Ω series resistor R229, correctly configured as LVDS transmitter output.
Pin D14 (TXO_NO_DATA_P4) and pin D13 (TXO_NO_DATA_N4) form a differential LVDS transmitter output pair for data bit 4 on the north interface. These pins connect through resistor R229 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs. This configuration is correct.TXO_NO_DATA4 differential pair with DNI 100Ω series resistor R229, correctly configured as LVDS transmitter output.
Pin D14 (TXO_NO_DATA_P4) and pin D13 (TXO_NO_DATA_N4) form a differential LVDS transmitter output pair for data bit 4 on the north interface. These pins connect through resistor R229 which is marked 'INSTALL=DNI'. This follows the standard pattern for transmitter outputs. This configuration is correct.RXI_SO_DATA3 differential pair with 100Ω series termination resistor R210, correctly configured for LVDS receiver input.
Pin R5 (RXI_SO_DATA_P3) and pin R6 (RXI_SO_DATA_N3) form a differential LVDS receiver input pair for data bit 3 on the south interface. These pins connect through 100Ω series termination resistor R210. According to the datasheet (page 33-42), RXI_SO_DATA signals are receiver inputs on the PEC_SOUTH connector. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA3 differential pair with 100Ω series termination resistor R210, correctly configured for LVDS receiver input.
Pin R5 (RXI_SO_DATA_P3) and pin R6 (RXI_SO_DATA_N3) form a differential LVDS receiver input pair for data bit 3 on the south interface. These pins connect through 100Ω series termination resistor R210. According to the datasheet (page 33-42), RXI_SO_DATA signals are receiver inputs on the PEC_SOUTH connector. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA7 differential pair with 100Ω series termination resistor R214, correctly configured for LVDS receiver input.
Pin R7 (RXI_SO_DATA_P7) and pin R8 (RXI_SO_DATA_N7) form a differential LVDS receiver input pair for data bit 7 on the south interface. These pins connect through 100Ω series termination resistor R214. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA7 differential pair with 100Ω series termination resistor R214, correctly configured for LVDS receiver input.
Pin R7 (RXI_SO_DATA_P7) and pin R8 (RXI_SO_DATA_N7) form a differential LVDS receiver input pair for data bit 7 on the south interface. These pins connect through 100Ω series termination resistor R214. This follows the standard LVDS receiver termination pattern. This configuration is correct.TXO_SO_FRAME differential pair with 100Ω series resistor R236 and 10K bias resistors (R245 to GND, R244 to 1P8V), configured as LVDS transmitter output with unusual bias network.
Pin R9 (TXO_SO_FRAME_P) and pin R10 (TXO_SO_FRAME_N) form a differential LVDS transmitter output pair for frame signaling on the south interface. According to the datasheet (page 33-42), TXO_SO_FRAME is a transmitter output. These pins connect through 100Ω series resistor R236 (not DNI, unlike other TXO resistors). Additionally, R245 (10K) connects the P signal to GND and R244 (10K) connects the N signal to 1P8V. This configuration is unusual because bias resistors are typically only used on receiver inputs, not transmitter outputs. LVDS transmitters are normally always driven and not tri-stated. However, if this output can be tri-stated or disabled in certain modes, the bias resistors would provide a safe default state. The presence of both series termination (R236) and bias resistors suggests this may be an intentional design for a tri-statable output. While this configuration is atypical, it appears to be a deliberate design choice, possibly to provide a defined state when the output is disabled. This configuration is acceptable.TXO_SO_FRAME differential pair with 100Ω series resistor R236 and 10K bias resistors (R245 to GND, R244 to 1P8V), configured as LVDS transmitter output with unusual bias network.
Pin R9 (TXO_SO_FRAME_P) and pin R10 (TXO_SO_FRAME_N) form a differential LVDS transmitter output pair for frame signaling on the south interface. According to the datasheet (page 33-42), TXO_SO_FRAME is a transmitter output. These pins connect through 100Ω series resistor R236 (not DNI, unlike other TXO resistors). Additionally, R245 (10K) connects the P signal to GND and R244 (10K) connects the N signal to 1P8V. This configuration is unusual because bias resistors are typically only used on receiver inputs, not transmitter outputs. LVDS transmitters are normally always driven and not tri-stated. However, if this output can be tri-stated or disabled in certain modes, the bias resistors would provide a safe default state. The presence of both series termination (R236) and bias resistors suggests this may be an intentional design for a tri-statable output. While this configuration is atypical, it appears to be a deliberate design choice, possibly to provide a defined state when the output is disabled. This configuration is acceptable.TXO_SO_DATA0 differential pair, LVDS transmitter output for data bit 0 on south interface.
Pin R11 (TXO_SO_DATA_P0) and pin R12 (TXO_SO_DATA_N0) form a differential LVDS transmitter output pair for data bit 0 on the south interface. According to the datasheet (page 33-42), TXO_SO_DATA[7:0] are transmitter outputs. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA0 differential pair, LVDS transmitter output for data bit 0 on south interface.
Pin R11 (TXO_SO_DATA_P0) and pin R12 (TXO_SO_DATA_N0) form a differential LVDS transmitter output pair for data bit 0 on the south interface. According to the datasheet (page 33-42), TXO_SO_DATA[7:0] are transmitter outputs. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA4 differential pair, LVDS transmitter output for data bit 4 on south interface.
Pin R13 (TXO_SO_DATA_P4) and pin R14 (TXO_SO_DATA_N4) form a differential LVDS transmitter output pair for data bit 4 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA4 differential pair, LVDS transmitter output for data bit 4 on south interface.
Pin R13 (TXO_SO_DATA_P4) and pin R14 (TXO_SO_DATA_N4) form a differential LVDS transmitter output pair for data bit 4 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.RXI_SO_DATA2 differential pair with 100Ω series termination resistor R209, correctly configured for LVDS receiver input.
Pin T4 (RXI_SO_DATA_P2) and pin T5 (RXI_SO_DATA_N2) form a differential LVDS receiver input pair for data bit 2 on the south interface. These pins connect through 100Ω series termination resistor R209. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA2 differential pair with 100Ω series termination resistor R209, correctly configured for LVDS receiver input.
Pin T4 (RXI_SO_DATA_P2) and pin T5 (RXI_SO_DATA_N2) form a differential LVDS receiver input pair for data bit 2 on the south interface. These pins connect through 100Ω series termination resistor R209. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA6 differential pair with 100Ω series termination resistor R213, correctly configured for LVDS receiver input.
Pin T6 (RXI_SO_DATA_P6) and pin T7 (RXI_SO_DATA_N6) form a differential LVDS receiver input pair for data bit 6 on the south interface. These pins connect through 100Ω series termination resistor R213. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA6 differential pair with 100Ω series termination resistor R213, correctly configured for LVDS receiver input.
Pin T6 (RXI_SO_DATA_P6) and pin T7 (RXI_SO_DATA_N6) form a differential LVDS receiver input pair for data bit 6 on the south interface. These pins connect through 100Ω series termination resistor R213. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXO_SO_WR_WAIT differential pair with DNI 100Ω series resistor R235, correctly configured as LVDS transmitter output.
Pin T8 (RXO_SO_WR_WAIT_P) and pin T9 (RXO_SO_WR_WAIT_N) form a differential LVDS transmitter output pair for write wait signaling on the south interface. According to the datasheet (page 33-42), RXO_SO_WR_WAIT is an output. These pins connect through resistor R235 which is marked 'INSTALL=DNI'. The DNI series resistor is consistent with LVDS transmitter outputs. This configuration is correct.RXO_SO_WR_WAIT differential pair with DNI 100Ω series resistor R235, correctly configured as LVDS transmitter output.
Pin T8 (RXO_SO_WR_WAIT_P) and pin T9 (RXO_SO_WR_WAIT_N) form a differential LVDS transmitter output pair for write wait signaling on the south interface. According to the datasheet (page 33-42), RXO_SO_WR_WAIT is an output. These pins connect through resistor R235 which is marked 'INSTALL=DNI'. The DNI series resistor is consistent with LVDS transmitter outputs. This configuration is correct.TXI_SO_WR_WAIT differential pair with 100Ω series termination resistor R218, correctly configured for LVDS receiver input.
Pin T10 (TXI_SO_WR_WAIT_P) and pin T11 (TXI_SO_WR_WAIT_N) form a differential LVDS receiver input pair for write wait signaling on the south interface. These pins connect through 100Ω series termination resistor R218. According to the datasheet (page 33-42), TXI_SO_WR_WAIT is an input. This follows the standard LVDS receiver termination pattern. This configuration is correct.TXI_SO_WR_WAIT differential pair with 100Ω series termination resistor R218, correctly configured for LVDS receiver input.
Pin T10 (TXI_SO_WR_WAIT_P) and pin T11 (TXI_SO_WR_WAIT_N) form a differential LVDS receiver input pair for write wait signaling on the south interface. These pins connect through 100Ω series termination resistor R218. According to the datasheet (page 33-42), TXI_SO_WR_WAIT is an input. This follows the standard LVDS receiver termination pattern. This configuration is correct.TXO_SO_DATA1 differential pair, LVDS transmitter output for data bit 1 on south interface.
Pin T12 (TXO_SO_DATA_P1) and pin T13 (TXO_SO_DATA_N1) form a differential LVDS transmitter output pair for data bit 1 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA1 differential pair, LVDS transmitter output for data bit 1 on south interface.
Pin T12 (TXO_SO_DATA_P1) and pin T13 (TXO_SO_DATA_N1) form a differential LVDS transmitter output pair for data bit 1 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA5 differential pair, LVDS transmitter output for data bit 5 on south interface.
Pin T14 (TXO_SO_DATA_P5) and pin T15 (TXO_SO_DATA_N5) form a differential LVDS transmitter output pair for data bit 5 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA5 differential pair, LVDS transmitter output for data bit 5 on south interface.
Pin T14 (TXO_SO_DATA_P5) and pin T15 (TXO_SO_DATA_N5) form a differential LVDS transmitter output pair for data bit 5 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.RXI_SO_DATA1 differential pair with 100Ω series termination resistor R208, correctly configured for LVDS receiver input.
Pin U3 (RXI_SO_DATA_P1) and pin U4 (RXI_SO_DATA_N1) form a differential LVDS receiver input pair for data bit 1 on the south interface. These pins connect through 100Ω series termination resistor R208. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA1 differential pair with 100Ω series termination resistor R208, correctly configured for LVDS receiver input.
Pin U3 (RXI_SO_DATA_P1) and pin U4 (RXI_SO_DATA_N1) form a differential LVDS receiver input pair for data bit 1 on the south interface. These pins connect through 100Ω series termination resistor R208. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA5 differential pair with 100Ω series termination resistor R212, correctly configured for LVDS receiver input.
Pin U5 (RXI_SO_DATA_P5) and pin U6 (RXI_SO_DATA_N5) form a differential LVDS receiver input pair for data bit 5 on the south interface. These pins connect through 100Ω series termination resistor R212. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA5 differential pair with 100Ω series termination resistor R212, correctly configured for LVDS receiver input.
Pin U5 (RXI_SO_DATA_P5) and pin U6 (RXI_SO_DATA_N5) form a differential LVDS receiver input pair for data bit 5 on the south interface. These pins connect through 100Ω series termination resistor R212. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_FRAME differential pair with 100Ω series termination (R215) and 10K bias resistors (R246 to GND, R247 to 1P8V), correctly configured for LVDS receiver with default idle state.
Pin U7 (RXI_SO_FRAME_P) and pin U8 (RXI_SO_FRAME_N) form a differential LVDS receiver input pair for frame signaling on the south interface. These pins connect through 100Ω series termination resistor R215. Additionally, R246 (10K) connects the P signal to GND and R247 (10K) connects the N signal to 1P8V, creating a negative differential voltage (P < N) representing logic 0. According to the datasheet (page 33-42), RXI_SO_FRAME is the receiver packet framing signal input. The bias resistors provide a default 'no frame' state when no signal is present. This configuration matches the north interface frame signal and is correct.RXI_SO_FRAME differential pair with 100Ω series termination (R215) and 10K bias resistors (R246 to GND, R247 to 1P8V), correctly configured for LVDS receiver with default idle state.
Pin U7 (RXI_SO_FRAME_P) and pin U8 (RXI_SO_FRAME_N) form a differential LVDS receiver input pair for frame signaling on the south interface. These pins connect through 100Ω series termination resistor R215. Additionally, R246 (10K) connects the P signal to GND and R247 (10K) connects the N signal to 1P8V, creating a negative differential voltage (P < N) representing logic 0. According to the datasheet (page 33-42), RXI_SO_FRAME is the receiver packet framing signal input. The bias resistors provide a default 'no frame' state when no signal is present. This configuration matches the north interface frame signal and is correct.RXO_SO_RD_WAIT differential pair with DNI 100Ω series resistor R234, correctly configured as LVDS transmitter output.
Pin U9 (RXO_SO_RD_WAIT_P) and pin U10 (RXO_SO_RD_WAIT_N) form a differential LVDS transmitter output pair for read wait signaling on the south interface. According to the datasheet (page 33-42), RXO_SO_RD_WAIT is an output. These pins connect through resistor R234 which is marked 'INSTALL=DNI'. The DNI series resistor is consistent with LVDS transmitter outputs. This configuration is correct.RXO_SO_RD_WAIT differential pair with DNI 100Ω series resistor R234, correctly configured as LVDS transmitter output.
Pin U9 (RXO_SO_RD_WAIT_P) and pin U10 (RXO_SO_RD_WAIT_N) form a differential LVDS transmitter output pair for read wait signaling on the south interface. According to the datasheet (page 33-42), RXO_SO_RD_WAIT is an output. These pins connect through resistor R234 which is marked 'INSTALL=DNI'. The DNI series resistor is consistent with LVDS transmitter outputs. This configuration is correct.TXI_SO_RD_WAIT differential pair with 100Ω series termination resistor R217, correctly configured for LVDS receiver input.
Pin U11 (TXI_SO_RD_WAIT_P) and pin U12 (TXI_SO_RD_WAIT_N) form a differential LVDS receiver input pair for read wait signaling on the south interface. These pins connect through 100Ω series termination resistor R217. According to the datasheet (page 33-42), TXI_SO_RD_WAIT is an input. This follows the standard LVDS receiver termination pattern. This configuration is correct.TXI_SO_RD_WAIT differential pair with 100Ω series termination resistor R217, correctly configured for LVDS receiver input.
Pin U11 (TXI_SO_RD_WAIT_P) and pin U12 (TXI_SO_RD_WAIT_N) form a differential LVDS receiver input pair for read wait signaling on the south interface. These pins connect through 100Ω series termination resistor R217. According to the datasheet (page 33-42), TXI_SO_RD_WAIT is an input. This follows the standard LVDS receiver termination pattern. This configuration is correct.TXO_SO_DATA2 differential pair, LVDS transmitter output for data bit 2 on south interface.
Pin U13 (TXO_SO_DATA_P2) and pin U14 (TXO_SO_DATA_N2) form a differential LVDS transmitter output pair for data bit 2 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA2 differential pair, LVDS transmitter output for data bit 2 on south interface.
Pin U13 (TXO_SO_DATA_P2) and pin U14 (TXO_SO_DATA_N2) form a differential LVDS transmitter output pair for data bit 2 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA6 differential pair, LVDS transmitter output for data bit 6 on south interface.
Pin U15 (TXO_SO_DATA_P6) and pin U16 (TXO_SO_DATA_N6) form a differential LVDS transmitter output pair for data bit 6 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA6 differential pair, LVDS transmitter output for data bit 6 on south interface.
Pin U15 (TXO_SO_DATA_P6) and pin U16 (TXO_SO_DATA_N6) form a differential LVDS transmitter output pair for data bit 6 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.RXI_SO_DATA0 differential pair with 100Ω series termination resistor R207, correctly configured for LVDS receiver input.
Pin V2 (RXI_SO_DATA_P0) and pin V3 (RXI_SO_DATA_N0) form a differential LVDS receiver input pair for data bit 0 on the south interface. These pins connect through 100Ω series termination resistor R207. According to the datasheet (page 33-42), RXI_SO_DATA signals are receiver inputs on the PEC_SOUTH connector. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA0 differential pair with 100Ω series termination resistor R207, correctly configured for LVDS receiver input.
Pin V2 (RXI_SO_DATA_P0) and pin V3 (RXI_SO_DATA_N0) form a differential LVDS receiver input pair for data bit 0 on the south interface. These pins connect through 100Ω series termination resistor R207. According to the datasheet (page 33-42), RXI_SO_DATA signals are receiver inputs on the PEC_SOUTH connector. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA4 differential pair with 100Ω series termination resistor R211, correctly configured for LVDS receiver input.
Pin V4 (RXI_SO_DATA_P4) and pin V5 (RXI_SO_DATA_N4) form a differential LVDS receiver input pair for data bit 4 on the south interface. These pins connect through 100Ω series termination resistor R211. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_DATA4 differential pair with 100Ω series termination resistor R211, correctly configured for LVDS receiver input.
Pin V4 (RXI_SO_DATA_P4) and pin V5 (RXI_SO_DATA_N4) form a differential LVDS receiver input pair for data bit 4 on the south interface. These pins connect through 100Ω series termination resistor R211. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_LCLK differential pair with 100Ω series termination resistor R216, correctly configured for LVDS receiver clock input.
Pin V6 (RXI_SO_LCLK_P) and pin V7 (RXI_SO_LCLK_N) form a differential LVDS receiver clock input pair on the south interface. These pins connect through 100Ω series termination resistor R216. According to the datasheet (page 33-42), RXI_SO_LCLK is the receiver clock input. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_LCLK differential pair with 100Ω series termination resistor R216, correctly configured for LVDS receiver clock input.
Pin V6 (RXI_SO_LCLK_P) and pin V7 (RXI_SO_LCLK_N) form a differential LVDS receiver clock input pair on the south interface. These pins connect through 100Ω series termination resistor R216. According to the datasheet (page 33-42), RXI_SO_LCLK is the receiver clock input. This follows the standard LVDS receiver termination pattern. This configuration is correct.RXI_SO_CCLK differential pair tied off with 0Ω resistors (P to GND via R291, N to 1P8V via R292), intentionally disabling this clock input.
Pin V9 (RXI_SO_CCLK_P) connects to net N23155371 which connects through 0Ω resistor R291 to GND. Pin V10 (RXI_SO_CCLK_N) connects to net N23155373 which connects through 0Ω resistor R292 to 1P8V. This configuration creates a static differential voltage that effectively disables the CCLK input, matching the configuration on the north interface. The use of 0Ω resistors allows for easy reconfiguration if needed. This appears to be an intentional design decision to disable an unused input. This configuration is correct.RXI_SO_CCLK differential pair tied off with 0Ω resistors (P to GND via R291, N to 1P8V via R292), intentionally disabling this clock input.
Pin V9 (RXI_SO_CCLK_P) connects to net N23155371 which connects through 0Ω resistor R291 to GND. Pin V10 (RXI_SO_CCLK_N) connects to net N23155373 which connects through 0Ω resistor R292 to 1P8V. This configuration creates a static differential voltage that effectively disables the CCLK input, matching the configuration on the north interface. The use of 0Ω resistors allows for easy reconfiguration if needed. This appears to be an intentional design decision to disable an unused input. This configuration is correct.TXO_SO_LCLK differential pair, LVDS transmitter clock output on south interface.
Pin V12 (TXO_SO_LCLK_P) and pin V13 (TXO_SO_LCLK_N) form a differential LVDS transmitter clock output pair on the south interface. According to the datasheet (page 33-42), TXO_SO_LCLK is the transmitter clock output. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_LCLK differential pair, LVDS transmitter clock output on south interface.
Pin V12 (TXO_SO_LCLK_P) and pin V13 (TXO_SO_LCLK_N) form a differential LVDS transmitter clock output pair on the south interface. According to the datasheet (page 33-42), TXO_SO_LCLK is the transmitter clock output. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA3 differential pair, LVDS transmitter output for data bit 3 on south interface.
Pin V14 (TXO_SO_DATA_P3) and pin V15 (TXO_SO_DATA_N3) form a differential LVDS transmitter output pair for data bit 3 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA3 differential pair, LVDS transmitter output for data bit 3 on south interface.
Pin V14 (TXO_SO_DATA_P3) and pin V15 (TXO_SO_DATA_N3) form a differential LVDS transmitter output pair for data bit 3 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA7 differential pair, LVDS transmitter output for data bit 7 on south interface.
Pin V16 (TXO_SO_DATA_P7) and pin V17 (TXO_SO_DATA_N7) form a differential LVDS transmitter output pair for data bit 7 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.TXO_SO_DATA7 differential pair, LVDS transmitter output for data bit 7 on south interface.
Pin V16 (TXO_SO_DATA_P7) and pin V17 (TXO_SO_DATA_N7) form a differential LVDS transmitter output pair for data bit 7 on the south interface. These pins do not have series termination resistors on this schematic page, consistent with LVDS transmitter outputs. This configuration is correct.R203 - RES0402_100 ✅
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📄 DRCY referred to this Datasheet for this component.
100 ohm differential termination resistor for LVDS clock signal RXI_NO_LCLK. Connection is correct.
R203 is a 100 ohm resistor (CRCW0402100RFKED) connected across the differential LVDS clock pair RXI_NO_LCLK_P (pin 1) and RXI_NO_LCLK_N (pin 2). Pin 1 connects to U23 (Epiphany E16G301 microprocessor) pin A7 (RXI_NO_LCLK_P) and pin 2 connects to U23 pin A6 (RXI_NO_LCLK_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI = Receive Input, NO = North Output, LCLK = Link Clock, P/N = differential pair) indicates this is a receive clock signal for the north-side interface. Standard LVDS differential impedance is 100 ohms, and termination resistors should be placed at the receiver end of the transmission line, which matches this configuration. The resistor value of 100 ohms is correct for LVDS termination, providing proper impedance matching for signal integrity. The datasheet confirms this is a standard 100 ohm, 1% tolerance resistor (CRCW0402100RFKED) suitable for high-frequency applications with appropriate power rating (0.10W at 70°C) and temperature coefficient (±100 ppm/K or ±200 ppm/K). This is a standard and correct implementation of LVDS differential termination.100 ohm differential termination resistor for LVDS clock signal RXI_NO_LCLK. Connection is correct.
R203 is a 100 ohm resistor (CRCW0402100RFKED) connected across the differential LVDS clock pair RXI_NO_LCLK_P (pin 1) and RXI_NO_LCLK_N (pin 2). Pin 1 connects to U23 (Epiphany E16G301 microprocessor) pin A7 (RXI_NO_LCLK_P) and pin 2 connects to U23 pin A6 (RXI_NO_LCLK_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI = Receive Input, NO = North Output, LCLK = Link Clock, P/N = differential pair) indicates this is a receive clock signal for the north-side interface. Standard LVDS differential impedance is 100 ohms, and termination resistors should be placed at the receiver end of the transmission line, which matches this configuration. The resistor value of 100 ohms is correct for LVDS termination, providing proper impedance matching for signal integrity. The datasheet confirms this is a standard 100 ohm, 1% tolerance resistor (CRCW0402100RFKED) suitable for high-frequency applications with appropriate power rating (0.10W at 70°C) and temperature coefficient (±100 ppm/K or ±200 ppm/K). This is a standard and correct implementation of LVDS differential termination.R202 - RES0402_100 ✅
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100 ohm differential termination resistor for LVDS frame signal RXI_NO_FRAME. Connection is correct.
R202 is a 100 ohm resistor (CRCW0402100RFKED) connected across the differential LVDS frame pair RXI_NO_FRAME_P (pin 1) and RXI_NO_FRAME_N (pin 2). Pin 1 connects to U23 (Epiphany E16G301 microprocessor) pin B8 (RXI_NO_FRAME_P) and pin 2 connects to U23 pin B7 (RXI_NO_FRAME_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI = Receive Input, NO = North Output, FRAME = Frame signal, P/N = differential pair) indicates this is a receive frame signal for the north-side interface. The 100 ohm termination is standard for LVDS differential impedance, providing proper impedance matching at the receiver end. Additionally, the differential pair has bias resistors: R243 (10K to GND) connected to RXI_NO_FRAME_P and R242 (10K to 1P8V) connected to RXI_NO_FRAME_N. These bias resistors provide DC biasing for the differential pair, which is a common and valid design practice to establish proper common-mode voltage, particularly useful for AC-coupled signals or when the transmitter may be in a high-impedance state. The 10K value is high enough to not significantly load the signal while providing the necessary DC path. The datasheet confirms this is a standard 100 ohm, 1% tolerance resistor suitable for this application with appropriate specifications. This is a standard and correct implementation of LVDS differential termination with DC biasing.100 ohm differential termination resistor for LVDS frame signal RXI_NO_FRAME. Connection is correct.
R202 is a 100 ohm resistor (CRCW0402100RFKED) connected across the differential LVDS frame pair RXI_NO_FRAME_P (pin 1) and RXI_NO_FRAME_N (pin 2). Pin 1 connects to U23 (Epiphany E16G301 microprocessor) pin B8 (RXI_NO_FRAME_P) and pin 2 connects to U23 pin B7 (RXI_NO_FRAME_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI = Receive Input, NO = North Output, FRAME = Frame signal, P/N = differential pair) indicates this is a receive frame signal for the north-side interface. The 100 ohm termination is standard for LVDS differential impedance, providing proper impedance matching at the receiver end. Additionally, the differential pair has bias resistors: R243 (10K to GND) connected to RXI_NO_FRAME_P and R242 (10K to 1P8V) connected to RXI_NO_FRAME_N. These bias resistors provide DC biasing for the differential pair, which is a common and valid design practice to establish proper common-mode voltage, particularly useful for AC-coupled signals or when the transmitter may be in a high-impedance state. The 10K value is high enough to not significantly load the signal while providing the necessary DC path. The datasheet confirms this is a standard 100 ohm, 1% tolerance resistor suitable for this application with appropriate specifications. This is a standard and correct implementation of LVDS differential termination with DC biasing.R207 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA0_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA0 LVDS signal pair. Pin 1 connects to RXI_SO_DATA0_P which routes to U23 pin V2 (RXI_SO_DATA_P0), and pin 2 connects to RXI_SO_DATA0_N which routes to U23 pin V3 (RXI_SO_DATA_N0). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI (Do Not Install), which is correct for a receive path termination resistor. This termination configuration is consistent with other differential pairs in the design (R208-R214 for the remaining RXI_SO_DATA pairs).100Ω termination resistor across LVDS differential pair RXI_SO_DATA0_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA0 LVDS signal pair. Pin 1 connects to RXI_SO_DATA0_P which routes to U23 pin V2 (RXI_SO_DATA_P0), and pin 2 connects to RXI_SO_DATA0_N which routes to U23 pin V3 (RXI_SO_DATA_N0). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI (Do Not Install), which is correct for a receive path termination resistor. This termination configuration is consistent with other differential pairs in the design (R208-R214 for the remaining RXI_SO_DATA pairs).R208 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA1_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA1 LVDS signal pair. Pin 1 connects to RXI_SO_DATA1_P which routes to U23 pin U3 (RXI_SO_DATA_P1), and pin 2 connects to RXI_SO_DATA1_N which routes to U23 pin U4 (RXI_SO_DATA_N1). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.100Ω termination resistor across LVDS differential pair RXI_SO_DATA1_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA1 LVDS signal pair. Pin 1 connects to RXI_SO_DATA1_P which routes to U23 pin U3 (RXI_SO_DATA_P1), and pin 2 connects to RXI_SO_DATA1_N which routes to U23 pin U4 (RXI_SO_DATA_N1). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.R209 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA2_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA2 LVDS signal pair. Pin 1 connects to RXI_SO_DATA2_P which routes to U23 pin T4 (RXI_SO_DATA_P2), and pin 2 connects to RXI_SO_DATA2_N which routes to U23 pin T5 (RXI_SO_DATA_N2). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.100Ω termination resistor across LVDS differential pair RXI_SO_DATA2_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA2 LVDS signal pair. Pin 1 connects to RXI_SO_DATA2_P which routes to U23 pin T4 (RXI_SO_DATA_P2), and pin 2 connects to RXI_SO_DATA2_N which routes to U23 pin T5 (RXI_SO_DATA_N2). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.R210 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA3_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA3 LVDS signal pair. Pin 1 connects to RXI_SO_DATA3_P which routes to U23 pin R5 (RXI_SO_DATA_P3), and pin 2 connects to RXI_SO_DATA3_N which routes to U23 pin R6 (RXI_SO_DATA_N3). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.100Ω termination resistor across LVDS differential pair RXI_SO_DATA3_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA3 LVDS signal pair. Pin 1 connects to RXI_SO_DATA3_P which routes to U23 pin R5 (RXI_SO_DATA_P3), and pin 2 connects to RXI_SO_DATA3_N which routes to U23 pin R6 (RXI_SO_DATA_N3). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.R211 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA4_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA4 LVDS signal pair. Pin 1 connects to RXI_SO_DATA4_P which routes to U23 pin V4 (RXI_SO_DATA_P4), and pin 2 connects to RXI_SO_DATA4_N which routes to U23 pin V5 (RXI_SO_DATA_N4). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.100Ω termination resistor across LVDS differential pair RXI_SO_DATA4_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA4 LVDS signal pair. Pin 1 connects to RXI_SO_DATA4_P which routes to U23 pin V4 (RXI_SO_DATA_P4), and pin 2 connects to RXI_SO_DATA4_N which routes to U23 pin V5 (RXI_SO_DATA_N4). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.R212 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA5_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA5 LVDS signal pair. Pin 1 connects to RXI_SO_DATA5_P which routes to U23 pin U5 (RXI_SO_DATA_P5), and pin 2 connects to RXI_SO_DATA5_N which routes to U23 pin U6 (RXI_SO_DATA_N5). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.100Ω termination resistor across LVDS differential pair RXI_SO_DATA5_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA5 LVDS signal pair. Pin 1 connects to RXI_SO_DATA5_P which routes to U23 pin U5 (RXI_SO_DATA_P5), and pin 2 connects to RXI_SO_DATA5_N which routes to U23 pin U6 (RXI_SO_DATA_N5). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.R213 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA6_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA6 LVDS signal pair. Pin 1 connects to RXI_SO_DATA6_P which routes to U23 pin T6 (RXI_SO_DATA_P6), and pin 2 connects to RXI_SO_DATA6_N which routes to U23 pin T7 (RXI_SO_DATA_N6). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.100Ω termination resistor across LVDS differential pair RXI_SO_DATA6_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA6 LVDS signal pair. Pin 1 connects to RXI_SO_DATA6_P which routes to U23 pin T6 (RXI_SO_DATA_P6), and pin 2 connects to RXI_SO_DATA6_N which routes to U23 pin T7 (RXI_SO_DATA_N6). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.R214 - RES0402_100 ✅
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100Ω termination resistor across LVDS differential pair RXI_SO_DATA7_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA7 LVDS signal pair. Pin 1 connects to RXI_SO_DATA7_P which routes to U23 pin R7 (RXI_SO_DATA_P7), and pin 2 connects to RXI_SO_DATA7_N which routes to U23 pin R8 (RXI_SO_DATA_N7). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.100Ω termination resistor across LVDS differential pair RXI_SO_DATA7_P/N at receiver U23.
This resistor provides differential termination for the RXI_SO_DATA7 LVDS signal pair. Pin 1 connects to RXI_SO_DATA7_P which routes to U23 pin R7 (RXI_SO_DATA_P7), and pin 2 connects to RXI_SO_DATA7_N which routes to U23 pin R8 (RXI_SO_DATA_N7). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming the intended use. The 100Ω value matches the standard characteristic impedance for LVDS differential pairs, providing proper termination at the receiver end to match transmission line impedance, reduce signal reflections, and improve signal integrity. The datasheet confirms this is a CRCW0402100RFKED resistor with 100Ω resistance and ±1% tolerance, suitable for high-frequency differential signaling applications. As a non-polarized passive component, pin orientation does not affect functionality. The component is not marked DNI, which is correct for a receive path termination resistor.R216 ✅
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100 ohm differential termination resistor for LVDS clock signal RXI_SO_LCLK. Pin 1 connects to RXI_SO_LCLK_P and pin 2 connects to RXI_SO_LCLK_N.
R216 is a 100 ohm resistor (per component attributes VALUE='100' and DESCRIPTION='RES, 0402, 100, 1%') connected between RXI_SO_LCLK_P (pin 1) and RXI_SO_LCLK_N (pin 2). These signals connect to U23 (EPIPHANY_E16G301 16-core microprocessor) pins V6 (RXI_SO_LCLK_P) and V7 (RXI_SO_LCLK_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI_SO_LCLK where RXI=Receive Input, SO=South interface, LCLK=Link Clock) indicates this is a receive clock signal for the South-oriented interface. LVDS (Low Voltage Differential Signaling) requires 100 ohm differential termination at the receiver end to match the characteristic impedance of the differential pair and prevent signal reflections. This is a standard and correct configuration for LVDS receiver termination. The datasheet (page 11) confirms this is a 100 ohm, 1% tolerance, 0402 package resistor (CRCW0402100RFKED) suitable for this application. Multiple similar 100 ohm resistors (R194-R218) are used throughout the schematic for other differential pairs, confirming this is the standard design pattern for all LVDS interfaces on this processor. The connection is correct.100 ohm differential termination resistor for LVDS clock signal RXI_SO_LCLK. Pin 1 connects to RXI_SO_LCLK_P and pin 2 connects to RXI_SO_LCLK_N.
R216 is a 100 ohm resistor (per component attributes VALUE='100' and DESCRIPTION='RES, 0402, 100, 1%') connected between RXI_SO_LCLK_P (pin 1) and RXI_SO_LCLK_N (pin 2). These signals connect to U23 (EPIPHANY_E16G301 16-core microprocessor) pins V6 (RXI_SO_LCLK_P) and V7 (RXI_SO_LCLK_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI_SO_LCLK where RXI=Receive Input, SO=South interface, LCLK=Link Clock) indicates this is a receive clock signal for the South-oriented interface. LVDS (Low Voltage Differential Signaling) requires 100 ohm differential termination at the receiver end to match the characteristic impedance of the differential pair and prevent signal reflections. This is a standard and correct configuration for LVDS receiver termination. The datasheet (page 11) confirms this is a 100 ohm, 1% tolerance, 0402 package resistor (CRCW0402100RFKED) suitable for this application. Multiple similar 100 ohm resistors (R194-R218) are used throughout the schematic for other differential pairs, confirming this is the standard design pattern for all LVDS interfaces on this processor. The connection is correct.R215 ✅
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100 ohm differential termination resistor for LVDS frame signal RXI_SO_FRAME with DC bias network. Pin 1 connects to RXI_SO_FRAME_P and pin 2 connects to RXI_SO_FRAME_N.
R215 is a 100 ohm resistor (per component attributes VALUE='100' and DESCRIPTION='RES, 0402, 100, 1%') connected between RXI_SO_FRAME_P (pin 1) and RXI_SO_FRAME_N (pin 2). These signals connect to U23 (EPIPHANY_E16G301 16-core microprocessor) pins U7 (RXI_SO_FRAME_P) and U8 (RXI_SO_FRAME_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI_SO_FRAME) indicates this is a Receive Input frame signal for the South-oriented interface. Additionally, this differential pair has DC biasing resistors: R246 (10K) connects RXI_SO_FRAME_P to GND, and R247 (10K) connects RXI_SO_FRAME_N to 1P8V. This creates a proper AC-coupled LVDS termination network where the 100 ohm resistor provides the required differential impedance while the 10K bias resistors establish a DC bias path centered around 0.9V (midpoint between GND and 1.8V), which is appropriate for 1.8V LVDS signaling. The high value of the bias resistors (10K) ensures they don't significantly affect the 100 ohm differential impedance seen by the AC signal. This biasing configuration is appropriate for LVDS receivers to establish a proper common-mode voltage when the transmitter is not actively driving or during idle states. The datasheet (page 11) confirms this is a 100 ohm, 1% tolerance, 0402 package resistor (CRCW0402100RFKED) suitable for this application. This termination configuration matches the standard practice for biased LVDS interfaces and is consistent with other differential pairs in the design. The connection is correct.100 ohm differential termination resistor for LVDS frame signal RXI_SO_FRAME with DC bias network. Pin 1 connects to RXI_SO_FRAME_P and pin 2 connects to RXI_SO_FRAME_N.
R215 is a 100 ohm resistor (per component attributes VALUE='100' and DESCRIPTION='RES, 0402, 100, 1%') connected between RXI_SO_FRAME_P (pin 1) and RXI_SO_FRAME_N (pin 2). These signals connect to U23 (EPIPHANY_E16G301 16-core microprocessor) pins U7 (RXI_SO_FRAME_P) and U8 (RXI_SO_FRAME_N). The schematic includes text annotation '100 Ohm Differential LVDS Signals' confirming this is an LVDS interface. The signal naming convention (RXI_SO_FRAME) indicates this is a Receive Input frame signal for the South-oriented interface. Additionally, this differential pair has DC biasing resistors: R246 (10K) connects RXI_SO_FRAME_P to GND, and R247 (10K) connects RXI_SO_FRAME_N to 1P8V. This creates a proper AC-coupled LVDS termination network where the 100 ohm resistor provides the required differential impedance while the 10K bias resistors establish a DC bias path centered around 0.9V (midpoint between GND and 1.8V), which is appropriate for 1.8V LVDS signaling. The high value of the bias resistors (10K) ensures they don't significantly affect the 100 ohm differential impedance seen by the AC signal. This biasing configuration is appropriate for LVDS receivers to establish a proper common-mode voltage when the transmitter is not actively driving or during idle states. The datasheet (page 11) confirms this is a 100 ohm, 1% tolerance, 0402 package resistor (CRCW0402100RFKED) suitable for this application. This termination configuration matches the standard practice for biased LVDS interfaces and is consistent with other differential pairs in the design. The connection is correct.R204 - RES0402_100 ✅
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100 ohm differential termination resistor across TXI_NO_RD_WAIT_P and TXI_NO_RD_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R204 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_NO_RD_WAIT_P) and pin 2 (TXI_NO_RD_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins B12 and B11 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the NO (North-Out) direction for read wait control signaling. Additional bias resistors R240 (10K to GND on _N signal) and R241 (10K to 1P8V on _P signal) provide default biasing when the signal is not actively driven. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.100 ohm differential termination resistor across TXI_NO_RD_WAIT_P and TXI_NO_RD_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R204 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_NO_RD_WAIT_P) and pin 2 (TXI_NO_RD_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins B12 and B11 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the NO (North-Out) direction for read wait control signaling. Additional bias resistors R240 (10K to GND on _N signal) and R241 (10K to 1P8V on _P signal) provide default biasing when the signal is not actively driven. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.R205 - RES0402_100 ✅
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100 ohm differential termination resistor across TXI_NO_WR_WAIT_P and TXI_NO_WR_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R205 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_NO_WR_WAIT_P) and pin 2 (TXI_NO_WR_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins C11 and C10 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the NO (North-Out) direction for write wait control signaling. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.100 ohm differential termination resistor across TXI_NO_WR_WAIT_P and TXI_NO_WR_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R205 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_NO_WR_WAIT_P) and pin 2 (TXI_NO_WR_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins C11 and C10 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the NO (North-Out) direction for write wait control signaling. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.R217 - RES0402_100 ✅
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100 ohm differential termination resistor across TXI_SO_RD_WAIT_P and TXI_SO_RD_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R217 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_SO_RD_WAIT_P) and pin 2 (TXI_SO_RD_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins U11 and U12 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the SO (South-Out) direction for read wait control signaling. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.100 ohm differential termination resistor across TXI_SO_RD_WAIT_P and TXI_SO_RD_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R217 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_SO_RD_WAIT_P) and pin 2 (TXI_SO_RD_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins U11 and U12 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the SO (South-Out) direction for read wait control signaling. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.R218 - RES0402_100 ✅
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100 ohm differential termination resistor across TXI_SO_WR_WAIT_P and TXI_SO_WR_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R218 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_SO_WR_WAIT_P) and pin 2 (TXI_SO_WR_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins T10 and T11 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the SO (South-Out) direction for write wait control signaling. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.100 ohm differential termination resistor across TXI_SO_WR_WAIT_P and TXI_SO_WR_WAIT_N LVDS signals, providing proper impedance matching for the differential pair.
R218 is a 100 ohm resistor (CRCW0402100RFKED) connected between pin 1 (TXI_SO_WR_WAIT_P) and pin 2 (TXI_SO_WR_WAIT_N). These signals connect to U23 (EPIPHANY_E16G301) pins T10 and T11 respectively. The schematic annotation '100 Ohm Differential LVDS Signals' confirms this is an LVDS differential pair. The 100 ohm value matches the standard differential impedance for LVDS signaling. This resistor provides differential termination at the receiver (processor input), which is the correct location for termination. The signal naming indicates TXI (Transmit Input to processor) from the SO (South-Out) direction for write wait control signaling. The datasheet confirms this is a standard 0402 package, 100 ohm, 1% tolerance resistor with adequate specifications: power rating of 0.10W at 70°C and voltage rating of 75V (datasheet page 1), both suitable for LVDS applications. The connection is correct for LVDS differential termination.R240 ✅
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10K pull-down resistor connecting TXI_NO_RD_WAIT_N to GND, part of differential pair biasing with standard LVDS polarity.
R240 connects pin 1 to TXI_NO_RD_WAIT_N and pin 2 to GND, functioning as a pull-down resistor on the negative signal of the TXI_NO_RD_WAIT differential pair. This signal connects to U23 pin B11 (EPIPHANY E16G301 microprocessor). R241 provides the complementary pull-up on TXI_NO_RD_WAIT_P (U23 pin B12) to 1P8V. Together, these 10K resistors create a default idle state where the positive signal is higher than the negative signal (P > N), which follows the standard convention for differential LVDS signaling as indicated by the schematic annotation '100 Ohm Differential LVDS Signals'. The 10K value is appropriate for biasing resistors per the datasheet (page 1) which specifies operating voltage up to 75V for 0402 size and rated dissipation of 0.10W at 70°C. The common-mode voltage created is approximately 0.9V (mid-supply for 1.8V), which is within the typical LVDS common-mode range. The 10K value is appropriately large compared to the 100 ohm termination resistor (R204) between the differential pair, allowing the actual drivers to easily override the bias while providing a defined state when the line is not driven. This configuration uses standard LVDS polarity, which is consistent with typical differential signaling practice.10K pull-down resistor connecting TXI_NO_RD_WAIT_N to GND, part of differential pair biasing with standard LVDS polarity.
R240 connects pin 1 to TXI_NO_RD_WAIT_N and pin 2 to GND, functioning as a pull-down resistor on the negative signal of the TXI_NO_RD_WAIT differential pair. This signal connects to U23 pin B11 (EPIPHANY E16G301 microprocessor). R241 provides the complementary pull-up on TXI_NO_RD_WAIT_P (U23 pin B12) to 1P8V. Together, these 10K resistors create a default idle state where the positive signal is higher than the negative signal (P > N), which follows the standard convention for differential LVDS signaling as indicated by the schematic annotation '100 Ohm Differential LVDS Signals'. The 10K value is appropriate for biasing resistors per the datasheet (page 1) which specifies operating voltage up to 75V for 0402 size and rated dissipation of 0.10W at 70°C. The common-mode voltage created is approximately 0.9V (mid-supply for 1.8V), which is within the typical LVDS common-mode range. The 10K value is appropriately large compared to the 100 ohm termination resistor (R204) between the differential pair, allowing the actual drivers to easily override the bias while providing a defined state when the line is not driven. This configuration uses standard LVDS polarity, which is consistent with typical differential signaling practice.R241 ✅
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10K pull-up resistor connecting TXI_NO_RD_WAIT_P to 1P8V, part of differential pair biasing with standard LVDS polarity.
R241 connects pin 1 to TXI_NO_RD_WAIT_P and pin 2 to 1P8V, functioning as a pull-up resistor on the positive signal of the TXI_NO_RD_WAIT differential pair. This signal connects to U23 pin B12 (EPIPHANY E16G301 microprocessor). R240 provides the complementary pull-down on TXI_NO_RD_WAIT_N (U23 pin B11) to GND. Together, these 10K resistors create a default idle state where the positive signal is higher than the negative signal (P > N), which follows the standard convention for differential LVDS signaling as indicated by the schematic annotation '100 Ohm Differential LVDS Signals'. The 10K value is appropriate for biasing resistors per the datasheet (page 1). The common-mode voltage created is approximately 0.9V (mid-supply for 1.8V), which is appropriate for LVDS. This configuration uses standard LVDS polarity, which is consistent with typical differential signaling practice.10K pull-up resistor connecting TXI_NO_RD_WAIT_P to 1P8V, part of differential pair biasing with standard LVDS polarity.
R241 connects pin 1 to TXI_NO_RD_WAIT_P and pin 2 to 1P8V, functioning as a pull-up resistor on the positive signal of the TXI_NO_RD_WAIT differential pair. This signal connects to U23 pin B12 (EPIPHANY E16G301 microprocessor). R240 provides the complementary pull-down on TXI_NO_RD_WAIT_N (U23 pin B11) to GND. Together, these 10K resistors create a default idle state where the positive signal is higher than the negative signal (P > N), which follows the standard convention for differential LVDS signaling as indicated by the schematic annotation '100 Ohm Differential LVDS Signals'. The 10K value is appropriate for biasing resistors per the datasheet (page 1). The common-mode voltage created is approximately 0.9V (mid-supply for 1.8V), which is appropriate for LVDS. This configuration uses standard LVDS polarity, which is consistent with typical differential signaling practice.R242 ❌
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10K pull-up resistor on RXI_NO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
10K pull-up resistor on RXI_NO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
R243 ❌
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10K pull-down resistor on RXI_NO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
10K pull-down resistor on RXI_NO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
R244 ❌
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10K pull-up resistor on TXO_SO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
10K pull-up resistor on TXO_SO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
R245 ❌
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10K pull-down resistor on TXO_SO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
10K pull-down resistor on TXO_SO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
R246 ❌
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10K pull-down resistor on RXI_SO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
10K pull-down resistor on RXI_SO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
R247 ❌
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10K pull-up resistor on RXI_SO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
10K pull-up resistor on RXI_SO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.
R289 - RES0402_0 ✅
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Connected to GND to tie the RXI_NO_CCLK_P signal to ground.
Pin 1 of R289 is connected to GND. Pin 2 connects to net N23150334, which routes to U23 (EPIPHANY_E16G301) pin A10 (RXI_NO_CCLK_P). This is a 0-ohm resistor (jumper) as confirmed by the datasheet (page 1), which specifies 'jumper (0 Ω)' with resistance ≤ 20 mΩ and maximum current of 1.5A for the 0402 package. The resistor creates a hard connection between the positive side of the North receive clock differential input and ground. Combined with R290 connecting RXI_NO_CCLK_N to 1P8V, this creates a static differential voltage of 1.8V (with N > P, resulting in a -1.8V differential). This configuration is mirrored for the South clock inputs (R291/R292), indicating a consistent design pattern. The use of 0-ohm resistors rather than higher value pull-down resistors (like the 10K resistors used for FRAME and WAIT signals elsewhere in the design) indicates these clock inputs are definitively disabled and held in a fixed state. This is an unusual configuration for LVDS signals, which typically operate with small differential voltages (~350mV) and specific common-mode voltage ranges. However, the consistency of the pattern across both CCLK pairs and the use of easily removable 0-ohm resistors suggests this is an intentional design choice to disable or configure these unused clock inputs. Without the EPIPHANY_E16G301 datasheet, the specific polarity and voltage levels cannot be definitively verified as the recommended configuration for disabling these inputs, but the design intent is clear.Connected to net N23150334, which routes to U23 pin A10 (RXI_NO_CCLK_P).
Pin 2 of R289 connects to net N23150334, which routes to U23 (EPIPHANY_E16G301) pin A10 (RXI_NO_CCLK_P), the positive side of the North receive clock differential pair. The 0-ohm resistor provides a direct connection from this clock input to ground via pin 1. This configuration, combined with R290 connecting the complementary signal (RXI_NO_CCLK_N) to 1P8V, establishes a static differential state for the clock input pair, likely indicating the clock is disabled or unused in this design.R290 - RES0402_0 ✅
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Connected to 1P8V to tie the RXI_NO_CCLK_N signal to the 1.8V supply.
Pin 1 of R290 is connected to the 1P8V power rail. Pin 2 connects to net N23150336, which routes to U23 (EPIPHANY_E16G301) pin A9 (RXI_NO_CCLK_N). This is a 0-ohm resistor (jumper) per the datasheet (page 1). The resistor creates a hard connection between the negative side of the North receive clock differential input and the 1.8V supply. Working in conjunction with R289 (which connects RXI_NO_CCLK_P to GND), this creates a static differential state where CCLK_N is at 1.8V and CCLK_P is at 0V, resulting in a -1.8V differential voltage. This configuration is consistent with R291/R292 for the South clock inputs, providing strong evidence of intentional design. The use of 0-ohm resistors indicates a permanent configuration rather than a weak pull-up, distinguishing this from the 10K resistors used for FRAME and WAIT signals elsewhere in the design. While this is not a typical LVDS termination or configuration, the consistency of the pattern and the use of easily removable 0-ohm resistors suggests this is a deliberate design choice for disabling or configuring unused clock inputs in a specific state.Connected to net N23150336, which routes to U23 pin A9 (RXI_NO_CCLK_N).
Pin 2 of R290 connects to net N23150336, which routes to U23 (EPIPHANY_E16G301) pin A9 (RXI_NO_CCLK_N), the negative side of the North receive clock differential pair. The 0-ohm resistor provides a direct connection from this clock input to 1P8V via pin 1. Combined with R289's connection of CCLK_P to ground, this establishes a static differential state for the clock input, likely indicating the clock is disabled or unused in this design.R291 - RES0402_0 ✅
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Connected to GND to tie the RXI_SO_CCLK_P signal to ground.
Pin 1 of R291 is connected to GND. Pin 2 connects to net N23155371, which routes to U23 (EPIPHANY_E16G301) pin V9 (RXI_SO_CCLK_P). This is a 0-ohm resistor (jumper) per the datasheet (page 1). The resistor creates a hard connection between the positive side of the South receive clock differential input and ground. This configuration exactly mirrors R289 for the North clock inputs, creating a consistent pattern for both CCLK input pairs. Combined with R292 connecting RXI_SO_CCLK_N to 1P8V, this creates a static differential voltage of 1.8V (with N > P, resulting in a -1.8V differential). The identical pattern to R289/R290 strongly suggests this is an intentional design choice to disable or configure unused clock inputs in a consistent manner across both the North and South interfaces. The use of 0-ohm resistors allows for easy reconfiguration if needed, while providing a strong, permanent connection in the current design state.Connected to net N23155371, which routes to U23 pin V9 (RXI_SO_CCLK_P).
Pin 2 of R291 connects to net N23155371, which routes to U23 (EPIPHANY_E16G301) pin V9 (RXI_SO_CCLK_P), the positive side of the South receive clock differential pair. The 0-ohm resistor provides a direct connection from this clock input to ground via pin 1. This configuration, combined with R292 connecting the complementary signal (RXI_SO_CCLK_N) to 1P8V, establishes a static differential state for the clock input pair. The connection pattern is identical to the North clock configuration (R289/R290), indicating a consistent design approach for both CCLK pairs.R292 - RES0402_0 ✅
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Connected to 1P8V to tie the RXI_SO_CCLK_N signal to the 1.8V supply.
Pin 1 of R292 is connected to the 1P8V power rail. Pin 2 connects to net N23155373, which routes to U23 (EPIPHANY_E16G301) pin V10 (RXI_SO_CCLK_N). This is a 0-ohm resistor (jumper) per the datasheet (page 1). The resistor creates a hard connection between the negative side of the South receive clock differential input and the 1.8V supply. Working in conjunction with R291 (which connects RXI_SO_CCLK_P to GND), this creates a static differential state where CCLK_N is at 1.8V and CCLK_P is at 0V, resulting in a -1.8V differential voltage. This configuration exactly matches the North clock configuration (R289/R290), providing strong evidence that this is an intentional design to disable both CCLK input pairs in a consistent manner. The use of 0-ohm resistors rather than higher value resistors indicates these signals are meant to be strongly driven to these voltages, likely to disable or configure these clock inputs in a specific state for this particular application. While verification against the EPIPHANY_E16G301 datasheet would be ideal to confirm this is the recommended configuration for unused clock inputs, the consistency of the pattern and the deliberate use of 0-ohm resistors strongly suggests this is a valid design choice.Connected to net N23155373, which routes to U23 pin V10 (RXI_SO_CCLK_N).
Pin 2 of R292 connects to net N23155373, which routes to U23 (EPIPHANY_E16G301) pin V10 (RXI_SO_CCLK_N), the negative side of the South receive clock differential pair. The 0-ohm resistor provides a direct connection from this clock input to 1P8V via pin 1. Combined with R291's connection of CCLK_P to ground, this establishes a static differential state for the clock input. The configuration is identical to the North clock (R289/R290), indicating a consistent design approach for disabling or configuring both CCLK input pairs.R236 - RES0402_100 ✅
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100 ohm differential termination resistor across LVDS signals TXO_SO_FRAME_P and TXO_SO_FRAME_N from DSP processor U23. This provides proper impedance matching for the differential pair.
R236 is a 100 ohm resistor connected between TXO_SO_FRAME_P (pin 1) and TXO_SO_FRAME_N (pin 2), which form a differential LVDS signal pair from the EPIPHANY E16G301 DSP processor U23 (pins R9 and R10, SEC 4). The schematic explicitly labels these as '100 Ohm Differential LVDS Signals', confirming the design intent. LVDS (Low Voltage Differential Signaling) requires 100 ohm differential termination to match the characteristic impedance of the transmission line and prevent signal reflections. The resistor value of 100 ohms matches the standard LVDS differential impedance requirement exactly. The datasheet for CRCW0402100RFKED confirms this is a 100 ohm ±1% resistor rated for 0.10W at 70°C and 75V max operating voltage (page 1), which is appropriate for LVDS signals that typically operate at low voltages (around 350mV differential). Additional DC biasing is provided by R245 (10K from TXO_SO_FRAME_P to GND) and R244 (10K from TXO_SO_FRAME_N to 1P8V), which establish a differential DC bias point without significantly loading the AC signal. This bias network provides a defined differential state when the driver is inactive or tri-stated, which is a common design practice. The design shows consistent use of 100 ohm termination resistors across multiple differential pairs throughout the schematic (R194-R218 for RXI signals, R202 for RXI_NO_FRAME, R204-R205 for TXI signals, R215 for RXI_SO_FRAME), confirming this is an intentional and systematic design pattern. Notably, R236 is installed while similar resistors for other TXO signals (R206, R226-R233) are marked DNI (Do Not Install), indicating this termination is intentionally included for the FRAME signal specifically. The connection topology, component values, and biasing scheme are all correct for LVDS differential signaling.100 ohm differential termination resistor across LVDS signals TXO_SO_FRAME_P and TXO_SO_FRAME_N from DSP processor U23. This provides proper impedance matching for the differential pair.
R236 is a 100 ohm resistor connected between TXO_SO_FRAME_P (pin 1) and TXO_SO_FRAME_N (pin 2), which form a differential LVDS signal pair from the EPIPHANY E16G301 DSP processor U23 (pins R9 and R10, SEC 4). The schematic explicitly labels these as '100 Ohm Differential LVDS Signals', confirming the design intent. LVDS (Low Voltage Differential Signaling) requires 100 ohm differential termination to match the characteristic impedance of the transmission line and prevent signal reflections. The resistor value of 100 ohms matches the standard LVDS differential impedance requirement exactly. The datasheet for CRCW0402100RFKED confirms this is a 100 ohm ±1% resistor rated for 0.10W at 70°C and 75V max operating voltage (page 1), which is appropriate for LVDS signals that typically operate at low voltages (around 350mV differential). Additional DC biasing is provided by R245 (10K from TXO_SO_FRAME_P to GND) and R244 (10K from TXO_SO_FRAME_N to 1P8V), which establish a differential DC bias point without significantly loading the AC signal. This bias network provides a defined differential state when the driver is inactive or tri-stated, which is a common design practice. The design shows consistent use of 100 ohm termination resistors across multiple differential pairs throughout the schematic (R194-R218 for RXI signals, R202 for RXI_NO_FRAME, R204-R205 for TXI signals, R215 for RXI_SO_FRAME), confirming this is an intentional and systematic design pattern. Notably, R236 is installed while similar resistors for other TXO signals (R206, R226-R233) are marked DNI (Do Not Install), indicating this termination is intentionally included for the FRAME signal specifically. The connection topology, component values, and biasing scheme are all correct for LVDS differential signaling.R206 ✅
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100 ohm differential termination resistor connecting TXO_NO_LCLK_P and TXO_NO_LCLK_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_LCLK_P) and negative (pin 2 to TXO_NO_LCLK_N) sides of a differential LVDS clock output pair from U23 (pins A13 and A12). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. A 100 ohm termination resistor is standard for LVDS differential pairs to match the characteristic impedance and prevent reflections. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_LCLK is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page, so the termination would be located there. The DNI resistor is provided as an option for testing or alternative configurations. The part number CRCW0402100RFKED is a standard 0402 package, 100 ohm, 1% tolerance resistor with 0.10W power rating at 70°C and 75V maximum operating voltage, which is appropriate for LVDS termination applications.100 ohm differential termination resistor connecting TXO_NO_LCLK_P and TXO_NO_LCLK_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_LCLK_P) and negative (pin 2 to TXO_NO_LCLK_N) sides of a differential LVDS clock output pair from U23 (pins A13 and A12). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. A 100 ohm termination resistor is standard for LVDS differential pairs to match the characteristic impedance and prevent reflections. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_LCLK is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page, so the termination would be located there. The DNI resistor is provided as an option for testing or alternative configurations. The part number CRCW0402100RFKED is a standard 0402 package, 100 ohm, 1% tolerance resistor with 0.10W power rating at 70°C and 75V maximum operating voltage, which is appropriate for LVDS termination applications.R226 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA7_P and TXO_NO_DATA7_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA7_P) and negative (pin 2 to TXO_NO_DATA7_N) sides of a differential LVDS data output pair from U23 (pins A17 and A16). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA7 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page. The DNI resistor provides flexibility for testing or alternative configurations.100 ohm differential termination resistor connecting TXO_NO_DATA7_P and TXO_NO_DATA7_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA7_P) and negative (pin 2 to TXO_NO_DATA7_N) sides of a differential LVDS data output pair from U23 (pins A17 and A16). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA7 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page. The DNI resistor provides flexibility for testing or alternative configurations.R227 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA6_P and TXO_NO_DATA6_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA6_P) and negative (pin 2 to TXO_NO_DATA6_N) sides of a differential LVDS data output pair from U23 (pins B16 and B15). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA6 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line. The pattern is consistent with other output signals from U23 that also have DNI termination resistors.100 ohm differential termination resistor connecting TXO_NO_DATA6_P and TXO_NO_DATA6_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA6_P) and negative (pin 2 to TXO_NO_DATA6_N) sides of a differential LVDS data output pair from U23 (pins B16 and B15). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA6 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line. The pattern is consistent with other output signals from U23 that also have DNI termination resistors.R228 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA5_P and TXO_NO_DATA5_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA5_P) and negative (pin 2 to TXO_NO_DATA5_N) sides of a differential LVDS data output pair from U23 (pins C15 and C14). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA5 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.100 ohm differential termination resistor connecting TXO_NO_DATA5_P and TXO_NO_DATA5_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA5_P) and negative (pin 2 to TXO_NO_DATA5_N) sides of a differential LVDS data output pair from U23 (pins C15 and C14). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA5 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.R229 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA4_P and TXO_NO_DATA4_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA4_P) and negative (pin 2 to TXO_NO_DATA4_N) sides of a differential LVDS data output pair from U23 (pins D14 and D13). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA4 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.100 ohm differential termination resistor connecting TXO_NO_DATA4_P and TXO_NO_DATA4_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA4_P) and negative (pin 2 to TXO_NO_DATA4_N) sides of a differential LVDS data output pair from U23 (pins D14 and D13). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA4 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.R230 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA3_P and TXO_NO_DATA3_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA3_P) and negative (pin 2 to TXO_NO_DATA3_N) sides of a differential LVDS data output pair from U23 (pins A15 and A14). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA3 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.100 ohm differential termination resistor connecting TXO_NO_DATA3_P and TXO_NO_DATA3_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA3_P) and negative (pin 2 to TXO_NO_DATA3_N) sides of a differential LVDS data output pair from U23 (pins A15 and A14). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA3 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.R231 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA2_P and TXO_NO_DATA2_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA2_P) and negative (pin 2 to TXO_NO_DATA2_N) sides of a differential LVDS data output pair from U23 (pins B14 and B13). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA2 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.100 ohm differential termination resistor connecting TXO_NO_DATA2_P and TXO_NO_DATA2_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA2_P) and negative (pin 2 to TXO_NO_DATA2_N) sides of a differential LVDS data output pair from U23 (pins B14 and B13). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA2 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.R232 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA1_P and TXO_NO_DATA1_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA1_P) and negative (pin 2 to TXO_NO_DATA1_N) sides of a differential LVDS data output pair from U23 (pins C13 and C12). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA1 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.100 ohm differential termination resistor connecting TXO_NO_DATA1_P and TXO_NO_DATA1_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA1_P) and negative (pin 2 to TXO_NO_DATA1_N) sides of a differential LVDS data output pair from U23 (pins C13 and C12). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA1 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.R233 ✅
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100 ohm differential termination resistor connecting TXO_NO_DATA0_P and TXO_NO_DATA0_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA0_P) and negative (pin 2 to TXO_NO_DATA0_N) sides of a differential LVDS data output pair from U23 (pins D12 and D11). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA0 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.100 ohm differential termination resistor connecting TXO_NO_DATA0_P and TXO_NO_DATA0_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to TXO_NO_DATA0_P) and negative (pin 2 to TXO_NO_DATA0_N) sides of a differential LVDS data output pair from U23 (pins D12 and D11). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. This is part of an 8-bit differential data bus (TXO_NO_DATA[7:0]). The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because TXO_NO_DATA0 is an output signal from U23 (transmitter side), and differential termination resistors should be placed at the receiving end of the transmission line.R234 ✅
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100 ohm differential termination resistor connecting RXO_SO_RD_WAIT_P and RXO_SO_RD_WAIT_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to RXO_SO_RD_WAIT_P) and negative (pin 2 to RXO_SO_RD_WAIT_N) sides of a differential LVDS output pair from U23 section 4 (pins U9 and U10). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because RXO_SO_RD_WAIT is an output signal from U23 (the RXO prefix indicates this is an output from the receive path, likely a flow control or status signal), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page.100 ohm differential termination resistor connecting RXO_SO_RD_WAIT_P and RXO_SO_RD_WAIT_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to RXO_SO_RD_WAIT_P) and negative (pin 2 to RXO_SO_RD_WAIT_N) sides of a differential LVDS output pair from U23 section 4 (pins U9 and U10). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because RXO_SO_RD_WAIT is an output signal from U23 (the RXO prefix indicates this is an output from the receive path, likely a flow control or status signal), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page.R235 ✅
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100 ohm differential termination resistor connecting RXO_SO_WR_WAIT_P and RXO_SO_WR_WAIT_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to RXO_SO_WR_WAIT_P) and negative (pin 2 to RXO_SO_WR_WAIT_N) sides of a differential LVDS output pair from U23 section 4 (pins T8 and T9). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because RXO_SO_WR_WAIT is an output signal from U23 (the RXO prefix indicates this is an output from the receive path, likely a flow control or status signal), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page.100 ohm differential termination resistor connecting RXO_SO_WR_WAIT_P and RXO_SO_WR_WAIT_N LVDS signals, marked DNI.
This resistor connects the positive (pin 1 to RXO_SO_WR_WAIT_P) and negative (pin 2 to RXO_SO_WR_WAIT_N) sides of a differential LVDS output pair from U23 section 4 (pins T8 and T9). The schematic text notes indicate '100 Ohm Differential LVDS Signals'. The 100 ohm value is standard for LVDS differential pair termination. The resistor is marked with INSTALL=DNI (Do Not Install), which is correct because RXO_SO_WR_WAIT is an output signal from U23 (the RXO prefix indicates this is an output from the receive path, likely a flow control or status signal), and differential termination resistors should be placed at the receiving end of the transmission line, not at the transmitter. The receiving end is not shown on this schematic page.U26 - HDMI_DVI_XCVR_ADV7513 ❌
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DDCSCL and DDCSDA pins have pull-up resistors that significantly exceed the datasheet-required range, which may cause DDC communication issues and HDMI compliance problems.
DDCSCL and DDCSDA pins have pull-up resistors that significantly exceed the datasheet-required range, which may cause DDC communication issues and HDMI compliance problems.
DVDD power supply pins correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pins 1, 11, 31, and 51 are all DVDD pins requiring 1.8V power supply according to the datasheet (page 16-18). These pins are connected to net HDMI_DVDD, which is filtered from the 1P8V rail through ferrite bead FB14 (120-OHM@100MHz). The power rail has appropriate bypass capacitors: C58 and C67 (0.1µF), C230 and C231 (10nF), and C232 (10µF). This follows the datasheet recommendations (page 42-43) which specify that each power supply pin should have a 0.1µF capacitor close to the supply pin, and an LC filter with 10µH inductor and 10µF capacitor is recommended. The ferrite bead provides similar filtering function to the inductor. The filtering implementation is correct and meets the datasheet requirements for noise-free 1.8V digital power supply.DVDD power supply pins correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pins 1, 11, 31, and 51 are all DVDD pins requiring 1.8V power supply according to the datasheet (page 16-18). These pins are connected to net HDMI_DVDD, which is filtered from the 1P8V rail through ferrite bead FB14 (120-OHM@100MHz). The power rail has appropriate bypass capacitors: C58 and C67 (0.1µF), C230 and C231 (10nF), and C232 (10µF). This follows the datasheet recommendations (page 42-43) which specify that each power supply pin should have a 0.1µF capacitor close to the supply pin, and an LC filter with 10µH inductor and 10µF capacitor is recommended. The ferrite bead provides similar filtering function to the inductor. The filtering implementation is correct and meets the datasheet requirements for noise-free 1.8V digital power supply.DVDD power supply pins correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pins 1, 11, 31, and 51 are all DVDD pins requiring 1.8V power supply according to the datasheet (page 16-18). These pins are connected to net HDMI_DVDD, which is filtered from the 1P8V rail through ferrite bead FB14 (120-OHM@100MHz). The power rail has appropriate bypass capacitors: C58 and C67 (0.1µF), C230 and C231 (10nF), and C232 (10µF). This follows the datasheet recommendations (page 42-43) which specify that each power supply pin should have a 0.1µF capacitor close to the supply pin, and an LC filter with 10µH inductor and 10µF capacitor is recommended. The ferrite bead provides similar filtering function to the inductor. The filtering implementation is correct and meets the datasheet requirements for noise-free 1.8V digital power supply.DVDD power supply pins correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pins 1, 11, 31, and 51 are all DVDD pins requiring 1.8V power supply according to the datasheet (page 16-18). These pins are connected to net HDMI_DVDD, which is filtered from the 1P8V rail through ferrite bead FB14 (120-OHM@100MHz). The power rail has appropriate bypass capacitors: C58 and C67 (0.1µF), C230 and C231 (10nF), and C232 (10µF). This follows the datasheet recommendations (page 42-43) which specify that each power supply pin should have a 0.1µF capacitor close to the supply pin, and an LC filter with 10µH inductor and 10µF capacitor is recommended. The ferrite bead provides similar filtering function to the inductor. The filtering implementation is correct and meets the datasheet requirements for noise-free 1.8V digital power supply.VSYNC input correctly connected to vertical sync signal.
Pin 2 (VSYNC) is the Vertical Sync Input according to the datasheet (page 16-18). It supports typical CMOS logic levels from 1.8V up to 3.3V. The pin is connected to net HDMI_VSYNC, which carries the vertical sync signal from the video source. This is a standard video timing signal connection and is correctly implemented.SPDIF audio input correctly connected to SPDIF signal.
Pin 3 (SPDIF) is the S/PDIF Audio Input according to the datasheet (page 16-18). It supports typical CMOS logic levels from 1.8V up to 3.3V. The pin is connected to net SPDIF for digital audio input. This is the only audio input being used in this design, as all I2S inputs are grounded. The datasheet (page 8) states 'No audio Master Clock (MCLK) required for audio' and 'Supports I2S, S/PDIF and HBR audio input formats', confirming that using only SPDIF without I2S is a valid configuration.Audio input pins (MCLK, I2S0-3, SCLK, LRCLK) correctly grounded as I2S audio is not used.
Pins 4 (MCLK), 5-8 (I2S0-I2S3), 9 (SCLK), and 10 (LRCLK) are all audio-related inputs according to the datasheet (page 16-18). All these pins are connected to GND. Since the design uses only SPDIF audio (pin 3 is connected to SPDIF signal), grounding the unused I2S-related pins is the correct approach to prevent floating inputs. The datasheet (page 8) confirms that 'No audio Master Clock (MCLK) required for audio' and the device supports both I2S and S/PDIF formats. Grounding unused inputs is standard practice and is appropriate for this configuration where only SPDIF audio is utilized.Audio input pins (MCLK, I2S0-3, SCLK, LRCLK) correctly grounded as I2S audio is not used.
Pins 4 (MCLK), 5-8 (I2S0-I2S3), 9 (SCLK), and 10 (LRCLK) are all audio-related inputs according to the datasheet (page 16-18). All these pins are connected to GND. Since the design uses only SPDIF audio (pin 3 is connected to SPDIF signal), grounding the unused I2S-related pins is the correct approach to prevent floating inputs. The datasheet (page 8) confirms that 'No audio Master Clock (MCLK) required for audio' and the device supports both I2S and S/PDIF formats. Grounding unused inputs is standard practice and is appropriate for this configuration where only SPDIF audio is utilized.Audio input pins (MCLK, I2S0-3, SCLK, LRCLK) correctly grounded as I2S audio is not used.
Pins 4 (MCLK), 5-8 (I2S0-I2S3), 9 (SCLK), and 10 (LRCLK) are all audio-related inputs according to the datasheet (page 16-18). All these pins are connected to GND. Since the design uses only SPDIF audio (pin 3 is connected to SPDIF signal), grounding the unused I2S-related pins is the correct approach to prevent floating inputs. The datasheet (page 8) confirms that 'No audio Master Clock (MCLK) required for audio' and the device supports both I2S and S/PDIF formats. Grounding unused inputs is standard practice and is appropriate for this configuration where only SPDIF audio is utilized.Audio input pins (MCLK, I2S0-3, SCLK, LRCLK) correctly grounded as I2S audio is not used.
Pins 4 (MCLK), 5-8 (I2S0-I2S3), 9 (SCLK), and 10 (LRCLK) are all audio-related inputs according to the datasheet (page 16-18). All these pins are connected to GND. Since the design uses only SPDIF audio (pin 3 is connected to SPDIF signal), grounding the unused I2S-related pins is the correct approach to prevent floating inputs. The datasheet (page 8) confirms that 'No audio Master Clock (MCLK) required for audio' and the device supports both I2S and S/PDIF formats. Grounding unused inputs is standard practice and is appropriate for this configuration where only SPDIF audio is utilized.Audio input pins (MCLK, I2S0-3, SCLK, LRCLK) correctly grounded as I2S audio is not used.
Pins 4 (MCLK), 5-8 (I2S0-I2S3), 9 (SCLK), and 10 (LRCLK) are all audio-related inputs according to the datasheet (page 16-18). All these pins are connected to GND. Since the design uses only SPDIF audio (pin 3 is connected to SPDIF signal), grounding the unused I2S-related pins is the correct approach to prevent floating inputs. The datasheet (page 8) confirms that 'No audio Master Clock (MCLK) required for audio' and the device supports both I2S and S/PDIF formats. Grounding unused inputs is standard practice and is appropriate for this configuration where only SPDIF audio is utilized.Audio input pins (MCLK, I2S0-3, SCLK, LRCLK) correctly grounded as I2S audio is not used.
Pins 4 (MCLK), 5-8 (I2S0-I2S3), 9 (SCLK), and 10 (LRCLK) are all audio-related inputs according to the datasheet (page 16-18). All these pins are connected to GND. Since the design uses only SPDIF audio (pin 3 is connected to SPDIF signal), grounding the unused I2S-related pins is the correct approach to prevent floating inputs. The datasheet (page 8) confirms that 'No audio Master Clock (MCLK) required for audio' and the device supports both I2S and S/PDIF formats. Grounding unused inputs is standard practice and is appropriate for this configuration where only SPDIF audio is utilized.Audio input pins (MCLK, I2S0-3, SCLK, LRCLK) correctly grounded as I2S audio is not used.
Pins 4 (MCLK), 5-8 (I2S0-I2S3), 9 (SCLK), and 10 (LRCLK) are all audio-related inputs according to the datasheet (page 16-18). All these pins are connected to GND. Since the design uses only SPDIF audio (pin 3 is connected to SPDIF signal), grounding the unused I2S-related pins is the correct approach to prevent floating inputs. The datasheet (page 8) confirms that 'No audio Master Clock (MCLK) required for audio' and the device supports both I2S and S/PDIF formats. Grounding unused inputs is standard practice and is appropriate for this configuration where only SPDIF audio is utilized.PVDD (PLL power supply) correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pin 12 (PVDD) is the 1.8V PLL Power Supply according to the datasheet (page 16-18), described as 'Most sensitive portion of ADV7513. Should provide quiet, noise-free power'. The pin is connected to net HDMI_PVDD, which is filtered from 1P8V through ferrite bead FB18 (120-OHM@100MHz). The power rail has bypass capacitors C264 (0.1µF), C265 (10nF), and C296 (10µF). This follows the datasheet recommendations (page 42-43) for power supply filtering with 0.1µF capacitor close to the pin and LC filtering. The implementation correctly provides clean, filtered power to this sensitive PLL supply.BGVDD (Band Gap Vdd) correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pin 13 (BGVDD) is the Band Gap Vdd according to the datasheet (page 16-18). The pin is connected to net HDMI_BGVDD, which is filtered from 1P8V through ferrite bead FB17 (120-OHM@100MHz). The power rail has bypass capacitors C263 (0.1µF), C266 (10nF), and C267 (10µF). This follows the datasheet recommendations (page 42-43) for power supply filtering. The band gap voltage reference requires clean power, and the filtering implementation is appropriate.R_EXT pin correctly connected to 887Ω reference resistor to ground.
Pin 14 (R_EXT) sets internal reference currents according to the datasheet (page 16-18). The datasheet (page 44) explicitly states: 'External reference resistor must have value of 887 Ohms (+/-1% tolerance)' and 'External reference resistor should be connected between R_EXT pin and ground with as short trace as possible'. The schematic shows R224 (887 ohm resistor) connected between pin 14 (net N23881678) and GND. The resistor value matches the datasheet specification exactly. The datasheet also warns to avoid running high-speed AC or noisy signals near R_EXT, particularly LRCLK signals. This is a critical reference that sets internal currents for proper TMDS output operation, and the connection is correct.AVDD power supply pins correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pins 15, 19, and 25 are all AVDD pins that provide 1.8V Power Supply for TMDS Outputs according to the datasheet (page 16-18). These pins are connected to net HDMI_AVDD, which is filtered from 1P8V through ferrite bead FB15 (120-OHM@100MHz). The power rail has bypass capacitors C144 and C145 (0.1µF), C233 and C234 (10nF), and C235 (10µF). This follows the datasheet recommendations (page 42-43) for power supply filtering. The TMDS outputs require clean analog power for proper signal integrity, and the filtering implementation is appropriate.AVDD power supply pins correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pins 15, 19, and 25 are all AVDD pins that provide 1.8V Power Supply for TMDS Outputs according to the datasheet (page 16-18). These pins are connected to net HDMI_AVDD, which is filtered from 1P8V through ferrite bead FB15 (120-OHM@100MHz). The power rail has bypass capacitors C144 and C145 (0.1µF), C233 and C234 (10nF), and C235 (10µF). This follows the datasheet recommendations (page 42-43) for power supply filtering. The TMDS outputs require clean analog power for proper signal integrity, and the filtering implementation is appropriate.AVDD power supply pins correctly connected to filtered 1.8V rail with appropriate bypass capacitors.
Pins 15, 19, and 25 are all AVDD pins that provide 1.8V Power Supply for TMDS Outputs according to the datasheet (page 16-18). These pins are connected to net HDMI_AVDD, which is filtered from 1P8V through ferrite bead FB15 (120-OHM@100MHz). The power rail has bypass capacitors C144 and C145 (0.1µF), C233 and C234 (10nF), and C235 (10µF). This follows the datasheet recommendations (page 42-43) for power supply filtering. The TMDS outputs require clean analog power for proper signal integrity, and the filtering implementation is appropriate.HPD (Hot Plug Detect) input correctly connected through level shifter U37.
Pin 16 (HPD) is the Hot Plug Detect signal input according to the datasheet (page 16-18), which 'Indicates whether sink is connected' and supports '1.8V to 5.0V CMOS logic level'. The pin is connected to net HDMI_HPD, which comes from U37 pin 4 (HPD_A). U37 is a TPD12S016 ESD protection and level shifter device. The HPD signal path is: HDMI connector J10 pin 1 → HDMI_HPD_B → U37 pin 10 (HPD_B) → level shifted → U37 pin 4 (HPD_A) → HDMI_HPD → U26 pin 16. This routing through the level shifter is correct and provides ESD protection while ensuring proper voltage levels for the ADV7513.TXC+/- (TMDS clock outputs) correctly connected through ESD protection to HDMI connector.
Pins 17 (TXC-) and 18 (TXC+) are the Differential TMDS Clock Outputs according to the datasheet (page 16-18), operating at pixel clock rate with TMDS logic levels. Pin 17 connects to HDMI_TXC_N and pin 18 connects to HDMI_TXC_P. These signals route through U37 (TPD12S016 ESD protection device) pins 15 (CLK-) and 16 (CLK+), then to HDMI connector J10 pins 14 (CLK-) and 12 (CLK+). The differential pair routing through ESD protection is standard practice for HDMI interfaces and provides necessary protection while maintaining signal integrity.TXC+/- (TMDS clock outputs) correctly connected through ESD protection to HDMI connector.
Pins 17 (TXC-) and 18 (TXC+) are the Differential TMDS Clock Outputs according to the datasheet (page 16-18), operating at pixel clock rate with TMDS logic levels. Pin 17 connects to HDMI_TXC_N and pin 18 connects to HDMI_TXC_P. These signals route through U37 (TPD12S016 ESD protection device) pins 15 (CLK-) and 16 (CLK+), then to HDMI connector J10 pins 14 (CLK-) and 12 (CLK+). The differential pair routing through ESD protection is standard practice for HDMI interfaces and provides necessary protection while maintaining signal integrity.TX0+/- (TMDS data channel 0 outputs) correctly connected through ESD protection to HDMI connector.
Pins 20 (TX0-) and 21 (TX0+) are Differential TMDS Output Channel 0 according to the datasheet (page 16-18), carrying blue data at 10× pixel clock rate with TMDS logic levels. Pin 20 connects to HDMI_TX0_N and pin 21 connects to HDMI_TX0_P. These signals route through U37 pins 17 (D0-) and 18 (D0+), then to HDMI connector J10 pins 11 (D0-) and 9 (D0+). The differential pair routing through ESD protection is correct for HDMI interfaces.TX0+/- (TMDS data channel 0 outputs) correctly connected through ESD protection to HDMI connector.
Pins 20 (TX0-) and 21 (TX0+) are Differential TMDS Output Channel 0 according to the datasheet (page 16-18), carrying blue data at 10× pixel clock rate with TMDS logic levels. Pin 20 connects to HDMI_TX0_N and pin 21 connects to HDMI_TX0_P. These signals route through U37 pins 17 (D0-) and 18 (D0+), then to HDMI connector J10 pins 11 (D0-) and 9 (D0+). The differential pair routing through ESD protection is correct for HDMI interfaces.PD (Power-Down Control) pin correctly configured with pull-down resistor for I2C address selection.
Pin 22 (PD) is the Power-Down Control and I2C Address Selection pin according to the datasheet (page 16-18). The datasheet states: 'I2C address and PD polarity set by pin state when supplies applied. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The pin is connected to net N25262962 with R237 (1K) pull-down resistor to GND. The state of this pin at power-up determines the I2C slave address and power-down polarity. The 1K pull-down ensures a defined logic low state, which is an intentional design choice to set a specific I2C address configuration.TX1+/- (TMDS data channel 1 outputs) correctly connected through ESD protection to HDMI connector.
Pins 23 (TX1-) and 24 (TX1+) are Differential TMDS Output Channel 1 according to the datasheet (page 16-18), carrying green data at 10× pixel clock rate with TMDS logic levels. Pin 23 connects to HDMI_TX1_N and pin 24 connects to HDMI_TX1_P. These signals route through U37 pins 20 (D1-) and 21 (D1+), then to HDMI connector J10 pins 8 (D1-) and 6 (D1+). The differential pair routing through ESD protection is correct for HDMI interfaces.TX1+/- (TMDS data channel 1 outputs) correctly connected through ESD protection to HDMI connector.
Pins 23 (TX1-) and 24 (TX1+) are Differential TMDS Output Channel 1 according to the datasheet (page 16-18), carrying green data at 10× pixel clock rate with TMDS logic levels. Pin 23 connects to HDMI_TX1_N and pin 24 connects to HDMI_TX1_P. These signals route through U37 pins 20 (D1-) and 21 (D1+), then to HDMI connector J10 pins 8 (D1-) and 6 (D1+). The differential pair routing through ESD protection is correct for HDMI interfaces.TX2+/- (TMDS data channel 2 outputs) correctly connected through ESD protection to HDMI connector.
Pins 26 (TX2-) and 27 (TX2+) are Differential TMDS Output Channel 2 according to the datasheet (page 16-18), carrying red data at 10× pixel clock rate with TMDS logic levels. Pin 26 connects to HDMI_TX2_N and pin 27 connects to HDMI_TX2_P. These signals route through U37 pins 22 (D2-) and 23 (D2+), then to HDMI connector J10 pins 5 (D2-) and 3 (D2+). The differential pair routing through ESD protection is correct for HDMI interfaces.TX2+/- (TMDS data channel 2 outputs) correctly connected through ESD protection to HDMI connector.
Pins 26 (TX2-) and 27 (TX2+) are Differential TMDS Output Channel 2 according to the datasheet (page 16-18), carrying red data at 10× pixel clock rate with TMDS logic levels. Pin 26 connects to HDMI_TX2_N and pin 27 connects to HDMI_TX2_P. These signals route through U37 pins 22 (D2-) and 23 (D2+), then to HDMI connector J10 pins 5 (D2-) and 3 (D2+). The differential pair routing through ESD protection is correct for HDMI interfaces.INT (Interrupt output) connected with pull-up resistor that is higher than datasheet recommendation but functionally acceptable.
Pin 28 (INT) is the Interrupt signal output according to the datasheet (page 16-18). The datasheet recommends: '2kΩ pull-up resistor (10%) to interrupt microcontroller IO supply recommended'. The schematic shows R22 (4.75K) pull-up to VDD_GPIO. While this value is higher than the 2kΩ recommendation, the datasheet uses the word 'recommended' rather than 'required', indicating some flexibility. The INT pin is an open-drain output, so a higher pull-up value will work but with slower rise times. The 4.75K value may have been chosen as a common resistor value used elsewhere in the design (R19, R21, R24 also use 4.75K). The higher resistance reduces current consumption and is acceptable for interrupt signaling where speed is not critical. This appears to be an intentional design choice that remains functionally correct.DVDD_3V power supply pin correctly connected to filtered 3.3V rail with appropriate bypass capacitors.
Pin 29 (DVDD_3V) requires 3.3V Power Supply according to the datasheet (page 16-18). The pin is connected to net N23924961, which is filtered from 3P3V through ferrite bead FB16 (120-OHM@100MHz). The power rail has bypass capacitors C196 (0.1µF), C262 (10nF), and C257 (10µF). This follows the datasheet recommendations (page 42-43) for power supply filtering. The datasheet specifies (page 14) that DVDD_3V should be 3.15V to 3.45V (nominal 3.3V), and the filtering implementation is appropriate.CEC pin correctly connected through level shifter to HDMI connector.
Pin 30 (CEC) is the CEC data signal according to the datasheet (page 16-18), supporting CMOS logic levels from 1.8V to 5V. The pin is connected to net HDMI_CEC, which routes to U37 pin 1 (CEC_A). U37 then connects to the HDMI connector via CEC_B (pin 7 to J10 pin 15). The datasheet (page 44) requires '27K ohms pull-up resistor to VDD=3.3V with leakage less than 1.8uA required for CEC line connection to HDMI connector'. Components D1 (diode) and R225 (27.4K) on the HDMI_CEC net are marked DNI (Do Not Install). The required pull-up should be on the HDMI_CEC_B net (connector side), which may be present elsewhere in the design or handled by U37. The CEC signal routing through the level shifter is correct.CEC_CLK input correctly connected to external clock source.
Pin 32 (CEC_CLK) is the CEC clock input according to the datasheet (page 16-18), requiring a clock 'From 3MHz to 100MHz' supporting 'CMOS logic levels from 1.8V to 5V'. The datasheet (page 44) states: 'External clock required to drive CEC_CLK input pin. Default frequency is 12MHz, but any clock between 3MHz and 100MHz (+/-2%) can be used'. The pin is connected to net HDMI_24M_CES_CLK, which suggests a 24MHz clock source. This is within the acceptable range and provides the necessary timing reference for CEC operation.SCL and SDA (I2C slave interface) correctly connected through level shifter for register access.
Pins 35 (SCL) and 36 (SDA) are the Serial Port Data Clock and Data I/O for I2C slave interface according to the datasheet (page 16-18). These pins serve as the slave interface for register access and support CMOS logic levels from 1.8V to 3.3V. The pins connect to nets I2C_SCL and I2C_SDA respectively, which route through U37 (TPD12S016 level shifter) pins 8 (SCL_B) and 9 (SDA_B). The master side connects to PS_I2C_SCL and PS_I2C_SDA through U37 pins 2 (SCL_A) and 3 (SDA_A). The datasheet (page 43) recommends 'Pull-up resistor of 2kΩ (+/-10%) to 1.8V or 3.3V recommended' for SDA and SCL. These pull-ups would typically be on the master side (PS_I2C_SCL/SDA) or within U37, which is standard practice for I2C interfaces. The routing through the level shifter is correct and provides voltage level translation between the processor and the ADV7513.SCL and SDA (I2C slave interface) correctly connected through level shifter for register access.
Pins 35 (SCL) and 36 (SDA) are the Serial Port Data Clock and Data I/O for I2C slave interface according to the datasheet (page 16-18). These pins serve as the slave interface for register access and support CMOS logic levels from 1.8V to 3.3V. The pins connect to nets I2C_SCL and I2C_SDA respectively, which route through U37 (TPD12S016 level shifter) pins 8 (SCL_B) and 9 (SDA_B). The master side connects to PS_I2C_SCL and PS_I2C_SDA through U37 pins 2 (SCL_A) and 3 (SDA_A). The datasheet (page 43) recommends 'Pull-up resistor of 2kΩ (+/-10%) to 1.8V or 3.3V recommended' for SDA and SCL. These pull-ups would typically be on the master side (PS_I2C_SCL/SDA) or within U37, which is standard practice for I2C interfaces. The routing through the level shifter is correct and provides voltage level translation between the processor and the ADV7513.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.Video data inputs D8-D23 correctly connected for 16-bit video input mode.
Pins 37-54 correspond to video data inputs D23 down to D8 according to the datasheet (page 16-18). These are 'Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic levels from 1.8V up to 3.3V'. The schematic shows these pins connected to nets HDMI_D23 through HDMI_D8. The datasheet (page 8) lists supported input formats including '24, 20, or 16 bit YCbCr 4:2:2' and other formats. Using only D[23:8] (16 bits) while leaving D[7:0] unconnected is a valid configuration for 16-bit video input mode. This is an intentional design choice to use a 16-bit video interface rather than the full 24-bit interface, which is explicitly supported by the device.CLK (Video Clock Input) correctly connected to video clock signal.
Pin 53 (CLK) is the Video Clock Input according to the datasheet (page 16-18), supporting typical CMOS logic levels from 1.8V up to 3.3V. The pin is connected to net HDMI_CLK. The datasheet (page 43) recommends: 'Noise coupled onto CLK input trace adds jitter to system. Recommended to control impedance of CLK trace. Using solid ground or supply reference under trace ensures constant impedance over entire trace length' and 'Minimize video input data clock (pin 53) trace length and do not run digital or high frequency traces near it'. The connection is correct, and proper PCB layout practices should be followed for this critical timing signal.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.Video data inputs D0-D7 intentionally left unconnected for 16-bit video input mode.
Pins 55-62 correspond to video data inputs D7 down to D0 according to the datasheet (page 16-18). These pins are not connected (no net assigned). The datasheet (page 8) supports various input formats including 16-bit modes. Since pins D23-D8 are connected (16 bits total), leaving D7-D0 unconnected is the correct configuration for 16-bit video input mode. The ADV7513 can be configured via I2C registers to operate in different bit-depth modes. This is an intentional design choice and is valid according to the datasheet's supported input formats.DE (Data Enable) input correctly connected to data enable signal.
Pin 63 (DE) is the Data Enable signal input for Digital Video according to the datasheet (page 16-18), supporting typical CMOS logic levels from 1.8V up to 3.3V. The pin is connected to net HDMI_DE. This is a standard video timing signal that indicates when valid pixel data is present. The connection is correct for video timing control.HSYNC (Horizontal Sync Input) correctly connected to horizontal sync signal.
Pin 64 (HSYNC) is the Horizontal Sync Input according to the datasheet (page 16-18), supporting typical CMOS logic levels from 1.8V up to 3.3V. The pin is connected to net HDMI_HSYNC. This is a standard video timing signal for horizontal synchronization. The connection is correct for video timing control.EPAD (Exposed pad) correctly connected to ground plane.
Pin 65 (EPAD) is the exposed pad that serves as ground return according to the datasheet (page 16-18): 'Ground return for all circuitry on-chip. Recommended to assemble on single, solid ground plane with careful attention to ground current paths'. The pin is connected to GND. This is the correct connection for thermal and electrical grounding of the IC package.U37 - TPD12S016 ❌
DRCY flagged 1 potential issues in this component.
📄 DRCY referred to this Datasheet for this component.
I2C level shifter pins are incorrectly connected - the TPD12S016's I2C interface should bridge the HDMI transmitter's DDC interface to the HDMI connector, not the control I2C interface.
I2C level shifter pins are incorrectly connected - the TPD12S016's I2C interface should bridge the HDMI transmitter's DDC interface to the HDMI connector, not the control I2C interface.
I2C level shifter pins are incorrectly connected - the TPD12S016's I2C interface should bridge the HDMI transmitter's DDC interface to the HDMI connector, not the control I2C interface.
I2C level shifter pins are incorrectly connected - the TPD12S016's I2C interface should bridge the HDMI transmitter's DDC interface to the HDMI connector, not the control I2C interface.
CEC_A pin correctly connected to HDMI transmitter CEC interface.
Pin 1 (CEC_A) connects to net HDMI_CEC, which connects to U26 pin 30 (CEC) on the ADV7513 HDMI transmitter. According to the TPD12S016 datasheet (page 4), CEC_A is the 'HDMI controller side CEC signal pin referenced to VCCA. Connect to HDMI controller.' This connection is correct as it receives the CEC signal from the HDMI transmitter and passes it through to the HDMI connector via CEC_B (pin 7), providing ESD protection and level shifting. The datasheet (page 8) indicates CEC_A has an internal 10kΩ pullup to VCCA.HPD_A pin correctly connected to HDMI transmitter hot plug detect interface.
Pin 4 (HPD_A) connects to net HDMI_HPD, which connects to U26 pin 16 (HPD) on the ADV7513 HDMI transmitter. According to the datasheet (page 4), HPD_A is 'Hot plug detect output referenced to VCCA. Connect to HDMI controller hot plug detect input pin.' This connection is correct as it provides the hot plug detect signal from the HDMI connector (received via HPD_B pin 10) to the HDMI transmitter, with level shifting to VCCA voltage and glitch filtering (datasheet page 1) to avoid false detection during connector insertion.LS_OE pin tied high to VDD_GPIO, enabling level shifters continuously.
Pin 5 (LS_OE) connects to VDD_GPIO. According to the datasheet (page 4), LS_OE 'Disables the Level shifters when OE = L. The OE pin is referenced to VCCA.' By tying this pin to VDD_GPIO (which also supplies VCCA on pin 24), the level shifters are permanently enabled when power is present. The datasheet application information (page 18) shows this is a valid configuration for 'Fully Enabled' mode where both CT_HPD and LS_OE are high. For power-saving modes, this pin could be controlled by a separate GPIO (page 20), but the current always-on configuration is acceptable for simpler operation.GND1 pin correctly connected to system ground.
Pin 6 (GND1) connects to the GND net. According to the datasheet (page 4), GND pins should 'Connect to system ground plane.' This is a straightforward and correct ground connection.CEC_B pin correctly connected to HDMI connector CEC interface.
Pin 7 (CEC_B) connects to net HDMI_CEC_B, which connects to J10 pin 15 (CEC) on the HDMI connector. According to the datasheet (page 4), CEC_B is 'HDMI connector side CEC signal pin referenced to internal 3.3-V supply. Connect to HDMI connector CEC pin.' This connection is correct as it provides the CEC signal to the HDMI connector with ESD protection. The datasheet (page 8) indicates CEC_B has an internal 22-30kΩ pullup to an internal 3.3V rail, eliminating the need for external pullup resistors and the need for a 3.3V supply on the board (datasheet page 1).HPD_B pin correctly connected to HDMI connector hot plug detect.
Pin 10 (HPD_B) connects to net HDMI_HPD_B, which connects to J10 pin 1 (HPD) on the HDMI connector. According to the datasheet (page 4), HPD_B is 'Hot plug detect input. Connect directly to HDMI connector hot plug detect pin.' This connection is correct. The datasheet (page 8) indicates HPD_B has an internal 11kΩ pulldown to GND, and the schematic shows an additional external 4.75kΩ pulldown resistor (R24), which works in parallel with the internal pulldown. The datasheet (page 1) mentions the HPD circuitry includes a glitch filter to avoid false detection during connector insertion.VCC_5V pin correctly connected to system 5V supply with proper decoupling.
Pin 11 (VCC_5V) connects to SYS_5P0V, the system 5V supply rail. According to the datasheet (page 4), VCC5V is 'Internal 5-V supply (input to the load switch).' The datasheet (page 1) explicitly requires a 0.1µF decoupling capacitor for VCC5V. Component C258 (0.1µF) provides the required decoupling between SYS_5P0V and GND. The datasheet (page 6) specifies the VCC5V supply voltage range as 4.5 to 5.5V. This connection is correct and properly decoupled.CT_HPD pin tied high to VDD_GPIO, enabling load switch and HPD detection continuously.
Pin 12 (CT_HPD) connects to VDD_GPIO. According to the datasheet (page 4), CT_HPD 'Disables the load switch and HPD_B when CT_HPD = L. The CT_HPD is referenced to VCCA.' By tying this pin to VDD_GPIO (which also supplies VCCA), the load switch and HPD detection are permanently enabled when power is present. The datasheet application information (page 18, 20) shows this is a valid configuration for 'Fully Enabled' mode. For more flexible power management, this pin could be controlled by a separate GPIO to enable a power-saving mode (page 20) where the load switch is enabled but level shifters are disabled (drawing only ~30µA, a reduction of 170µA), but the current always-on configuration is acceptable for simpler operation.5V_OUT pin correctly connected to HDMI connector 5V supply with proper decoupling.
Pin 13 (5V_OUT) connects to net HDMI_5V, which connects to J10 pin 19 (5V0) on the HDMI connector. According to the datasheet (page 4), 5V_OUT is 'External 5-V supply (output of the load switch).' The datasheet (page 1) explicitly requires a 0.1µF decoupling capacitor for 5V_OUT. Component C289 (0.1µF) provides the required decoupling. The datasheet (page 7) specifies a short circuit current limit of 100-200mA (typical 150mA) and a 55mA current limit for the load switch. The HDMI_5V net also supplies pullup resistors R19 and R21 (both 4.75kΩ) for the DDC_SCL and DDC_SDA lines, which is appropriate as the HDMI specification requires DDC pullups to the 5V supply. This connection is correct and provides current-limited 5V power to the HDMI connector per HDMI specification.GND2 pin correctly connected to system ground.
Pin 14 (GND2) connects to the GND net. According to the datasheet (page 4), GND pins should 'Connect to system ground plane.' This is a straightforward and correct ground connection.CLK- and CLK+ pins correctly connected between HDMI transmitter and connector for TMDS clock signals.
Pins 15 (CLK-) and 16 (CLK+) connect to nets HDMI_TXC_N and HDMI_TXC_P respectively. These nets connect to U26 pins 17/18 (TXC-/TXC+) on the ADV7513 HDMI transmitter and J10 pins 14/12 (CLK-/CLK+) on the HDMI connector. According to the datasheet (page 4), CLK+/CLK- are 'HDMI TMDS clock. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected - all three components (transmitter, TPD12S016, connector) are on the same nets. The TPD12S016 provides IEC 61000-4-2 Level 4 ESD protection (±8kV contact discharge per page 1) for these high-speed differential signals while maintaining low IO capacitance of 1.0pF typical for the PW package (page 7) and ultra-low differential capacitance of 0.05pF typical (page 7), which is suitable for HDMI 1.4 data rates up to 3.4Gbps (page 1).CLK- and CLK+ pins correctly connected between HDMI transmitter and connector for TMDS clock signals.
Pins 15 (CLK-) and 16 (CLK+) connect to nets HDMI_TXC_N and HDMI_TXC_P respectively. These nets connect to U26 pins 17/18 (TXC-/TXC+) on the ADV7513 HDMI transmitter and J10 pins 14/12 (CLK-/CLK+) on the HDMI connector. According to the datasheet (page 4), CLK+/CLK- are 'HDMI TMDS clock. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected - all three components (transmitter, TPD12S016, connector) are on the same nets. The TPD12S016 provides IEC 61000-4-2 Level 4 ESD protection (±8kV contact discharge per page 1) for these high-speed differential signals while maintaining low IO capacitance of 1.0pF typical for the PW package (page 7) and ultra-low differential capacitance of 0.05pF typical (page 7), which is suitable for HDMI 1.4 data rates up to 3.4Gbps (page 1).D0- and D0+ pins correctly connected between HDMI transmitter and connector for TMDS data channel 0.
Pins 17 (D0-) and 18 (D0+) connect to nets HDMI_TX0_N and HDMI_TX0_P respectively. These nets connect to U26 pins 20/21 (TX0-/TX0+) on the ADV7513 HDMI transmitter and J10 pins 11/9 (D0-/D0+) on the HDMI connector. According to the datasheet (page 4), D+/D- are 'HDMI TMDS data. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected. The TPD12S016 provides ESD protection for these high-speed differential signals while maintaining signal integrity with low capacitance (1.0pF IO capacitance, 0.05pF differential capacitance per page 7).D0- and D0+ pins correctly connected between HDMI transmitter and connector for TMDS data channel 0.
Pins 17 (D0-) and 18 (D0+) connect to nets HDMI_TX0_N and HDMI_TX0_P respectively. These nets connect to U26 pins 20/21 (TX0-/TX0+) on the ADV7513 HDMI transmitter and J10 pins 11/9 (D0-/D0+) on the HDMI connector. According to the datasheet (page 4), D+/D- are 'HDMI TMDS data. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected. The TPD12S016 provides ESD protection for these high-speed differential signals while maintaining signal integrity with low capacitance (1.0pF IO capacitance, 0.05pF differential capacitance per page 7).GND3 pin correctly connected to system ground.
Pin 19 (GND3) connects to the GND net. According to the datasheet (page 4), GND pins should 'Connect to system ground plane.' This is a straightforward and correct ground connection.D1- and D1+ pins correctly connected between HDMI transmitter and connector for TMDS data channel 1.
Pins 20 (D1-) and 21 (D1+) connect to nets HDMI_TX1_N and HDMI_TX1_P respectively. These nets connect to U26 pins 23/24 (TX1-/TX1+) on the ADV7513 HDMI transmitter and J10 pins 8/6 (D1-/D1+) on the HDMI connector. According to the datasheet (page 4), D+/D- are 'HDMI TMDS data. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected. The TPD12S016 provides ESD protection for these high-speed differential signals while maintaining low capacitance suitable for HDMI 1.4 data rates.D1- and D1+ pins correctly connected between HDMI transmitter and connector for TMDS data channel 1.
Pins 20 (D1-) and 21 (D1+) connect to nets HDMI_TX1_N and HDMI_TX1_P respectively. These nets connect to U26 pins 23/24 (TX1-/TX1+) on the ADV7513 HDMI transmitter and J10 pins 8/6 (D1-/D1+) on the HDMI connector. According to the datasheet (page 4), D+/D- are 'HDMI TMDS data. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected. The TPD12S016 provides ESD protection for these high-speed differential signals while maintaining low capacitance suitable for HDMI 1.4 data rates.D2- and D2+ pins correctly connected between HDMI transmitter and connector for TMDS data channel 2.
Pins 22 (D2-) and 23 (D2+) connect to nets HDMI_TX2_N and HDMI_TX2_P respectively. These nets connect to U26 pins 26/27 (TX2-/TX2+) on the ADV7513 HDMI transmitter and J10 pins 5/3 (D2-/D2+) on the HDMI connector. According to the datasheet (page 4), D+/D- are 'HDMI TMDS data. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected. The TPD12S016 provides ESD protection for these high-speed differential signals while maintaining low capacitance suitable for HDMI 1.4 data rates.D2- and D2+ pins correctly connected between HDMI transmitter and connector for TMDS data channel 2.
Pins 22 (D2-) and 23 (D2+) connect to nets HDMI_TX2_N and HDMI_TX2_P respectively. These nets connect to U26 pins 26/27 (TX2-/TX2+) on the ADV7513 HDMI transmitter and J10 pins 5/3 (D2-/D2+) on the HDMI connector. According to the datasheet (page 4), D+/D- are 'HDMI TMDS data. Connect to HDMI controller and HDMI connector directly.' This is exactly how they are connected. The TPD12S016 provides ESD protection for these high-speed differential signals while maintaining low capacitance suitable for HDMI 1.4 data rates.VCCA pin correctly connected to VDD_GPIO supply with proper decoupling.
Pin 24 (VCCA) connects to VDD_GPIO. According to the datasheet (page 4), VCCA is 'Internal PCB low voltage supply (same as the HDMI controller chip supply).' The datasheet (page 1) explicitly requires a 0.1µF decoupling capacitor for VCCA. Component C239 (0.1µF) provides the required decoupling between VDD_GPIO and GND. The datasheet (page 6) specifies the VCCA supply voltage range as 1.1 to 3.6V. VDD_GPIO appears to be the appropriate voltage rail for the GPIO and HDMI interface logic level. This connection is correct and properly decoupled.J10 - HDMI_MICRO_D_RA ✅
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HPD (Hot Plug Detect) signal connected through ESD protection IC U37 to HDMI transmitter U26, with pull-down resistor R24 to ground.
Pin 1 (HPD) connects to net HDMI_HPD_B, which routes to U37 (TPD12S016PWR) pin 10 (HPD_B) for ESD protection and level shifting. U37 pin 4 (HPD_A) connects to HDMI_HPD, which then connects to U26 (ADV7513BSWZ HDMI transmitter) pin 16 (HPD). R24 (4.75K) provides a pull-down from HDMI_HPD_B to GND. While HPD is typically pulled up at the sink side, the pull-down on the connector side is appropriate for this design because: (1) it ensures a defined low state when no cable is connected, (2) it works with the TPD12S016 level shifter which has control pins CT_HPD (pin 12) and LS_OE (pin 5) connected to VDD_GPIO, enabling active HPD management, and (3) the sink device will override this pull-down with its internal pull-up when a cable is connected. This configuration is correct for designs using the TPD12S016 ESD protection device.RES (Reserved/Utility) pin is left unconnected, which is standard practice for HDMI implementations.
Pin 2 (RES) has no net connection in the schematic. This pin is designated as reserved or utility in the HDMI specification and is typically used for HEAC+ (HDMI Ethernet and Audio Return Channel) functionality. Leaving this pin unconnected is standard practice when HEAC functionality is not required, which is the case for most HDMI implementations. This is correct.D2+ (TMDS Data2+) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 3 (D2+) connects to net HDMI_TX2_P, which routes to both U37 pin 23 (D2+) for ESD protection and U26 pin 27 (TX2+) on the HDMI transmitter. This is the positive signal of the TMDS Data Channel 2 differential pair. The routing through the TPD12S016 ESD protection device before reaching the ADV7513BSWZ transmitter provides necessary protection for the high-speed differential signals from ESD events on the cable. The connection matches the HDMI specification for TMDS Data2+ and is correct.D2S (TMDS Data2 Shield) correctly connected to ground plane.
Pin 4 (D2S) connects to the GND net. This pin serves as the shield/ground reference for the TMDS Data Channel 2 differential pair. Connecting the shield to ground is correct and necessary for proper signal integrity and EMI performance of the high-speed differential signals. This follows standard HDMI design practices for maintaining proper grounding and shielding of differential pairs.D2- (TMDS Data2-) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 5 (D2-) connects to net HDMI_TX2_N, which routes to U37 pin 22 (D2-) for ESD protection and U26 pin 26 (TX2-) on the transmitter. This is the negative signal of the TMDS Data Channel 2 differential pair, complementary to pin 3. The routing through ESD protection and to the transmitter maintains proper differential pair integrity and is correct.D1+ (TMDS Data1+) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 6 (D1+) connects to net HDMI_TX1_P, routing to U37 pin 21 (D1+) for ESD protection and U26 pin 24 (TX1+) on the transmitter. This is the positive signal of the TMDS Data Channel 1 differential pair. The routing through the TPD12S016 ESD protection device to the ADV7513BSWZ transmitter is correct and follows proper HDMI design practices for high-speed differential signals.D1S (TMDS Data1 Shield) correctly connected to ground plane.
Pin 7 (D1S) connects to the GND net. This pin serves as the shield/ground reference for the TMDS Data Channel 1 differential pair. The ground connection is correct and necessary for maintaining signal integrity and EMI performance of the differential signals per HDMI specifications.D1- (TMDS Data1-) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 8 (D1-) connects to net HDMI_TX1_N, routing to U37 pin 20 (D1-) for ESD protection and U26 pin 23 (TX1-) on the transmitter. This is the negative signal of the TMDS Data Channel 1 differential pair, complementary to pin 6. The routing maintains proper differential pair integrity through ESD protection to the transmitter, which is correct.D0+ (TMDS Data0+) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 9 (D0+) connects to net HDMI_TX0_P, routing to U37 pin 18 (D0+) for ESD protection and U26 pin 21 (TX0+) on the transmitter. This is the positive signal of the TMDS Data Channel 0 differential pair. The routing through ESD protection to the transmitter is correct and follows HDMI design standards for high-speed differential signaling.D0S (TMDS Data0 Shield) correctly connected to ground plane.
Pin 10 (D0S) connects to the GND net. This pin serves as the shield/ground reference for the TMDS Data Channel 0 differential pair. The ground connection is correct for proper signal integrity and EMI performance per HDMI specifications.D0- (TMDS Data0-) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 11 (D0-) connects to net HDMI_TX0_N, routing to U37 pin 17 (D0-) for ESD protection and U26 pin 20 (TX0-) on the transmitter. This is the negative signal of the TMDS Data Channel 0 differential pair, complementary to pin 9. The routing through ESD protection maintains proper differential pair integrity, which is correct.CLK+ (TMDS Clock+) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 12 (CLK+) connects to net HDMI_TXC_P, routing to U37 pin 16 (CLK+) for ESD protection and U26 pin 18 (TXC+) on the transmitter. This is the positive signal of the TMDS Clock differential pair. The routing through the TPD12S016 ESD protection to the ADV7513BSWZ transmitter is correct and essential for proper HDMI clock signal transmission.CLKS (TMDS Clock Shield) correctly connected to ground plane.
Pin 13 (CLKS) connects to the GND net. This pin serves as the shield/ground reference for the TMDS Clock differential pair. The ground connection is correct and necessary for maintaining clock signal integrity and EMI performance per HDMI specifications.CLK- (TMDS Clock-) differential signal correctly routed through ESD protection to HDMI transmitter.
Pin 14 (CLK-) connects to net HDMI_TXC_N, routing to U37 pin 15 (CLK-) for ESD protection and U26 pin 17 (TXC-) on the transmitter. This is the negative signal of the TMDS Clock differential pair, complementary to pin 12. The routing through ESD protection maintains proper differential pair integrity for the clock signal, which is correct.CEC (Consumer Electronics Control) signal correctly routed through level shifter and ESD protection to HDMI transmitter.
Pin 15 (CEC) connects to net HDMI_CEC_B, which routes to U37 pin 7 (CEC_B) for level shifting and ESD protection. U37 pin 1 (CEC_A) connects to HDMI_CEC, which then connects to U26 pin 30 (CEC) on the HDMI transmitter. The TPD12S016 provides bidirectional level shifting for the CEC signal between the connector and transmitter voltage domains. D1 (BAS16XV2T1G diode) and R225 (27.4K resistor) are marked DNI (Do Not Install), which is acceptable as CEC can function without these optional components. The routing provides proper ESD protection and level translation for the CEC bidirectional communication line and is correct.DDC (DDC/CEC Ground) correctly connected to ground plane.
Pin 16 (DDC) connects to the GND net. This pin serves as the ground reference for the DDC (Display Data Channel) and CEC signals. Connecting this pin to ground is correct and necessary for proper I2C communication on the DDC bus and CEC signaling. This follows the HDMI specification requirements for providing a common ground reference for these low-speed control signals.SCL (DDC Clock) correctly connected to HDMI transmitter with proper pull-up resistor to 5V.
Pin 17 (SCL) connects to net DDC_SCL, which routes to U26 pin 33 (DDCSCL) on the ADV7513BSWZ HDMI transmitter. R19 (4.75K) provides a pull-up from DDC_SCL to HDMI_5V. This configuration is correct for the I2C DDC interface. The pull-up to HDMI_5V (which comes from the sink device via pin 19) ensures proper I2C logic levels and allows the sink to power the DDC communication even when the source is in standby. The 4.75K pull-up value is within the typical range for I2C DDC applications (2K-10K) and matches the HDMI specification recommendations.SDA (DDC Data) correctly connected to HDMI transmitter with proper pull-up resistor to 5V.
Pin 18 (SDA) connects to net DDC_SDA, which routes to U26 pin 34 (DDCSDA) on the ADV7513BSWZ HDMI transmitter. R21 (4.75K) provides a pull-up from DDC_SDA to HDMI_5V. This configuration is correct for the I2C DDC interface. The pull-up to HDMI_5V ensures proper I2C logic levels and allows bidirectional communication for EDID reading and other DDC functions. The 4.75K pull-up value matches the SCL pull-up (R19) and is appropriate for DDC applications per HDMI specifications.5V0 (5V Power) correctly connected through ESD protection with proper decoupling and controlled power delivery.
Pin 19 (5V0) connects to net HDMI_5V, which connects to U37 pin 13 (5V_OUT). U37 pin 11 (VCC_5V) connects to SYS_5P0V, indicating that the TPD12S016 provides controlled 5V output to the HDMI connector from the system 5V supply. C289 (0.1uF) provides decoupling from HDMI_5V to GND. This configuration is correct and provides: (1) ESD protection for the 5V line, (2) proper decoupling for noise reduction, (3) controlled power delivery to the sink device, and (4) the ability to detect sink presence. The DDC pull-up resistors R19 and R21 are correctly connected to HDMI_5V, allowing the sink to power the DDC communication. This follows HDMI specifications for source device power delivery.Shield pins (SHLD1-4) correctly connected to ground plane for EMI shielding and mechanical grounding.
Pins GND1, GND2, GND3, and GND4 (labeled SHLD1, SHLD2, SHLD3, SHLD4) all connect to the GND net. These are the shield connections for the HDMI Micro-D connector, providing EMI shielding and mechanical grounding for the connector shell and cable shield. Connecting all shield pins to ground is correct and necessary for: (1) proper EMI/RFI shielding to prevent electromagnetic interference, (2) ESD protection by providing a discharge path, (3) maintaining signal integrity by providing a low-impedance return path for high-speed signals, and (4) mechanical grounding of the connector. This follows standard HDMI connector design practices and is essential for proper operation at high data rates.Shield pins (SHLD1-4) correctly connected to ground plane for EMI shielding and mechanical grounding.
Pins GND1, GND2, GND3, and GND4 (labeled SHLD1, SHLD2, SHLD3, SHLD4) all connect to the GND net. These are the shield connections for the HDMI Micro-D connector, providing EMI shielding and mechanical grounding for the connector shell and cable shield. Connecting all shield pins to ground is correct and necessary for: (1) proper EMI/RFI shielding to prevent electromagnetic interference, (2) ESD protection by providing a discharge path, (3) maintaining signal integrity by providing a low-impedance return path for high-speed signals, and (4) mechanical grounding of the connector. This follows standard HDMI connector design practices and is essential for proper operation at high data rates.Shield pins (SHLD1-4) correctly connected to ground plane for EMI shielding and mechanical grounding.
Pins GND1, GND2, GND3, and GND4 (labeled SHLD1, SHLD2, SHLD3, SHLD4) all connect to the GND net. These are the shield connections for the HDMI Micro-D connector, providing EMI shielding and mechanical grounding for the connector shell and cable shield. Connecting all shield pins to ground is correct and necessary for: (1) proper EMI/RFI shielding to prevent electromagnetic interference, (2) ESD protection by providing a discharge path, (3) maintaining signal integrity by providing a low-impedance return path for high-speed signals, and (4) mechanical grounding of the connector. This follows standard HDMI connector design practices and is essential for proper operation at high data rates.Shield pins (SHLD1-4) correctly connected to ground plane for EMI shielding and mechanical grounding.
Pins GND1, GND2, GND3, and GND4 (labeled SHLD1, SHLD2, SHLD3, SHLD4) all connect to the GND net. These are the shield connections for the HDMI Micro-D connector, providing EMI shielding and mechanical grounding for the connector shell and cable shield. Connecting all shield pins to ground is correct and necessary for: (1) proper EMI/RFI shielding to prevent electromagnetic interference, (2) ESD protection by providing a discharge path, (3) maintaining signal integrity by providing a low-impedance return path for high-speed signals, and (4) mechanical grounding of the connector. This follows standard HDMI connector design practices and is essential for proper operation at high data rates.J11 - BSH-030-01-F-D-A ✅
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Power supply pins connected to VDD_GPIO rail. Both pins provide power for GPIO signals and connected peripherals.
Pins 1 and 2 are both connected to the VDD_GPIO net, which serves as the power supply for the GPIO expansion connector. The datasheet (page 1) confirms this is a double row socket assembly (BSH-030-01-F-D-A) with 30 positions per row (60 total pins) and 0.5mm pitch. Having two power pins at the beginning of the connector is a standard practice to provide adequate current capacity for the GPIO signals and any connected peripherals. The VDD_GPIO rail is also used throughout the schematic to power other GPIO-related circuits including U37 (TPD12S016) pins 5, 12, and 24, and decoupling capacitors C239, C268, and C269. This dual power pin configuration follows good design practices for power distribution in expansion connectors, ensuring sufficient current handling capability and redundancy.Power supply pins connected to VDD_GPIO rail. Both pins provide power for GPIO signals and connected peripherals.
Pins 1 and 2 are both connected to the VDD_GPIO net, which serves as the power supply for the GPIO expansion connector. The datasheet (page 1) confirms this is a double row socket assembly (BSH-030-01-F-D-A) with 30 positions per row (60 total pins) and 0.5mm pitch. Having two power pins at the beginning of the connector is a standard practice to provide adequate current capacity for the GPIO signals and any connected peripherals. The VDD_GPIO rail is also used throughout the schematic to power other GPIO-related circuits including U37 (TPD12S016) pins 5, 12, and 24, and decoupling capacitors C239, C268, and C269. This dual power pin configuration follows good design practices for power distribution in expansion connectors, ensuring sufficient current handling capability and redundancy.Differential pair GPIO0_N (pin 3) and GPIO0_P (pin 5) for GPIO channel 0.
Pin 3 carries GPIO0_N and pin 5 carries GPIO0_P, forming a differential pair for GPIO channel 0. These pins are adjacent within row 1 (odd-numbered pins) of the double-row connector, which is appropriate for maintaining signal integrity in differential signaling. The naming convention with _N (negative) and _P (positive) suffixes clearly indicates these are complementary differential signals. Keeping the positive and negative signals of a differential pair on the same row and in adjacent positions minimizes skew and maintains proper impedance matching for high-speed differential signals. This pairing pattern is consistent throughout the connector for all 24 GPIO channels, providing a systematic and reliable interface design.Differential pair GPIO0_N (pin 3) and GPIO0_P (pin 5) for GPIO channel 0.
Pin 3 carries GPIO0_N and pin 5 carries GPIO0_P, forming a differential pair for GPIO channel 0. These pins are adjacent within row 1 (odd-numbered pins) of the double-row connector, which is appropriate for maintaining signal integrity in differential signaling. The naming convention with _N (negative) and _P (positive) suffixes clearly indicates these are complementary differential signals. Keeping the positive and negative signals of a differential pair on the same row and in adjacent positions minimizes skew and maintains proper impedance matching for high-speed differential signals. This pairing pattern is consistent throughout the connector for all 24 GPIO channels, providing a systematic and reliable interface design.Differential pair GPIO1_N (pin 4) and GPIO1_P (pin 6) for GPIO channel 1.
Pin 4 carries GPIO1_N and pin 6 carries GPIO1_P, forming a differential pair for GPIO channel 1. These pins are adjacent within row 2 (even-numbered pins) of the double-row connector. The connector organization places even-numbered GPIO channels (GPIO1, GPIO3, GPIO5, etc.) on row 2, while odd-numbered channels (GPIO0, GPIO2, GPIO4, etc.) are on row 1. This systematic arrangement maintains differential pair integrity within each row while the interleaving between rows helps reduce crosstalk between adjacent differential pairs. The connection follows best practices for high-speed differential signaling interfaces.Differential pair GPIO1_N (pin 4) and GPIO1_P (pin 6) for GPIO channel 1.
Pin 4 carries GPIO1_N and pin 6 carries GPIO1_P, forming a differential pair for GPIO channel 1. These pins are adjacent within row 2 (even-numbered pins) of the double-row connector. The connector organization places even-numbered GPIO channels (GPIO1, GPIO3, GPIO5, etc.) on row 2, while odd-numbered channels (GPIO0, GPIO2, GPIO4, etc.) are on row 1. This systematic arrangement maintains differential pair integrity within each row while the interleaving between rows helps reduce crosstalk between adjacent differential pairs. The connection follows best practices for high-speed differential signaling interfaces.Differential pair GPIO2_N (pin 7) and GPIO2_P (pin 9) for GPIO channel 2.
Pin 7 carries GPIO2_N and pin 9 carries GPIO2_P, forming a differential pair for GPIO channel 2. These are adjacent pins in row 1 of the connector, following the established pattern for even-numbered GPIO channels. The differential pair is properly maintained with adjacent physical placement for signal integrity. The sequential numbering and consistent placement pattern make the interface easy to understand and use.Differential pair GPIO2_N (pin 7) and GPIO2_P (pin 9) for GPIO channel 2.
Pin 7 carries GPIO2_N and pin 9 carries GPIO2_P, forming a differential pair for GPIO channel 2. These are adjacent pins in row 1 of the connector, following the established pattern for even-numbered GPIO channels. The differential pair is properly maintained with adjacent physical placement for signal integrity. The sequential numbering and consistent placement pattern make the interface easy to understand and use.Differential pair GPIO3_N (pin 8) and GPIO3_P (pin 10) for GPIO channel 3.
Pin 8 carries GPIO3_N and pin 10 carries GPIO3_P, forming a differential pair for GPIO channel 3. These are adjacent pins in row 2 of the connector, consistent with the pattern for odd-numbered GPIO channels. The connection maintains differential pair integrity and follows the systematic organization of the connector.Differential pair GPIO3_N (pin 8) and GPIO3_P (pin 10) for GPIO channel 3.
Pin 8 carries GPIO3_N and pin 10 carries GPIO3_P, forming a differential pair for GPIO channel 3. These are adjacent pins in row 2 of the connector, consistent with the pattern for odd-numbered GPIO channels. The connection maintains differential pair integrity and follows the systematic organization of the connector.Ground pins providing return current path and shielding for GPIO signals.
Pins 11 and 12 are both connected to GND. These ground pins are strategically placed after every 8 signal pins (4 differential pairs) to provide a low-impedance return path for the high-speed signals and to act as shielding between groups of differential pairs. This is a standard practice in high-speed connector design. The datasheet (page 1) indicates the connector uses phosphor bronze contacts with selective gold plating, suitable for reliable ground connections. Ground pins are distributed at regular intervals throughout the connector at positions 11-12, 21-22, 31-32, 41-42, and 51-52, providing excellent signal integrity for high-speed differential signaling applications. This regular distribution of ground pins every 10 positions is essential for maintaining signal integrity and minimizing electromagnetic interference.Ground pins providing return current path and shielding for GPIO signals.
Pins 11 and 12 are both connected to GND. These ground pins are strategically placed after every 8 signal pins (4 differential pairs) to provide a low-impedance return path for the high-speed signals and to act as shielding between groups of differential pairs. This is a standard practice in high-speed connector design. The datasheet (page 1) indicates the connector uses phosphor bronze contacts with selective gold plating, suitable for reliable ground connections. Ground pins are distributed at regular intervals throughout the connector at positions 11-12, 21-22, 31-32, 41-42, and 51-52, providing excellent signal integrity for high-speed differential signaling applications. This regular distribution of ground pins every 10 positions is essential for maintaining signal integrity and minimizing electromagnetic interference.Differential pair GPIO4_N (pin 13) and GPIO4_P (pin 15) for GPIO channel 4.
Pin 13 carries GPIO4_N and pin 15 carries GPIO4_P, forming a differential pair for GPIO channel 4. These are adjacent pins in row 1, continuing the sequential pattern after the ground pins. The placement maintains the established pattern of row 1 assignments for even-numbered GPIO channels.Differential pair GPIO4_N (pin 13) and GPIO4_P (pin 15) for GPIO channel 4.
Pin 13 carries GPIO4_N and pin 15 carries GPIO4_P, forming a differential pair for GPIO channel 4. These are adjacent pins in row 1, continuing the sequential pattern after the ground pins. The placement maintains the established pattern of row 1 assignments for even-numbered GPIO channels.Differential pair GPIO5_N (pin 14) and GPIO5_P (pin 16) for GPIO channel 5.
Pin 14 carries GPIO5_N and pin 16 carries GPIO5_P, forming a differential pair for GPIO channel 5. These are adjacent pins in row 2, consistent with the pattern for odd-numbered GPIO channels. The differential pair integrity is maintained.Differential pair GPIO5_N (pin 14) and GPIO5_P (pin 16) for GPIO channel 5.
Pin 14 carries GPIO5_N and pin 16 carries GPIO5_P, forming a differential pair for GPIO channel 5. These are adjacent pins in row 2, consistent with the pattern for odd-numbered GPIO channels. The differential pair integrity is maintained.Differential pair GPIO6_N (pin 17) and GPIO6_P (pin 19) for GPIO channel 6.
Pin 17 carries GPIO6_N and pin 19 carries GPIO6_P, forming a differential pair for GPIO channel 6. These are adjacent pins in row 1, following the established pattern. The connection is correct.Differential pair GPIO6_N (pin 17) and GPIO6_P (pin 19) for GPIO channel 6.
Pin 17 carries GPIO6_N and pin 19 carries GPIO6_P, forming a differential pair for GPIO channel 6. These are adjacent pins in row 1, following the established pattern. The connection is correct.Differential pair GPIO7_N (pin 18) and GPIO7_P (pin 20) for GPIO channel 7.
Pin 18 carries GPIO7_N and pin 20 carries GPIO7_P, forming a differential pair for GPIO channel 7. These are adjacent pins in row 2, maintaining the systematic organization. The connection is correct.Differential pair GPIO7_N (pin 18) and GPIO7_P (pin 20) for GPIO channel 7.
Pin 18 carries GPIO7_N and pin 20 carries GPIO7_P, forming a differential pair for GPIO channel 7. These are adjacent pins in row 2, maintaining the systematic organization. The connection is correct.Ground pins providing return current path and shielding for GPIO signals.
Pins 21 and 22 are both connected to GND, providing the second set of distributed ground pins in the connector. This placement after GPIO channels 4-7 maintains the pattern of ground distribution every 10 positions, which is essential for maintaining signal integrity in high-speed differential signaling applications.Ground pins providing return current path and shielding for GPIO signals.
Pins 21 and 22 are both connected to GND, providing the second set of distributed ground pins in the connector. This placement after GPIO channels 4-7 maintains the pattern of ground distribution every 10 positions, which is essential for maintaining signal integrity in high-speed differential signaling applications.Differential pair GPIO8_N (pin 23) and GPIO8_P (pin 25) for GPIO channel 8.
Pin 23 carries GPIO8_N and pin 25 carries GPIO8_P, forming a differential pair for GPIO channel 8. These are adjacent pins in row 1, continuing the sequential pattern after the ground pins.Differential pair GPIO8_N (pin 23) and GPIO8_P (pin 25) for GPIO channel 8.
Pin 23 carries GPIO8_N and pin 25 carries GPIO8_P, forming a differential pair for GPIO channel 8. These are adjacent pins in row 1, continuing the sequential pattern after the ground pins.Differential pair GPIO9_N (pin 24) and GPIO9_P (pin 26) for GPIO channel 9.
Pin 24 carries GPIO9_N and pin 26 carries GPIO9_P, forming a differential pair for GPIO channel 9. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO9_N (pin 24) and GPIO9_P (pin 26) for GPIO channel 9.
Pin 24 carries GPIO9_N and pin 26 carries GPIO9_P, forming a differential pair for GPIO channel 9. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO10_N (pin 27) and GPIO10_P (pin 29) for GPIO channel 10.
Pin 27 carries GPIO10_N and pin 29 carries GPIO10_P, forming a differential pair for GPIO channel 10. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO10_N (pin 27) and GPIO10_P (pin 29) for GPIO channel 10.
Pin 27 carries GPIO10_N and pin 29 carries GPIO10_P, forming a differential pair for GPIO channel 10. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO11_N (pin 28) and GPIO11_P (pin 30) for GPIO channel 11.
Pin 28 carries GPIO11_N and pin 30 carries GPIO11_P, forming a differential pair for GPIO channel 11. These are adjacent pins in row 2, maintaining differential pair integrity.Differential pair GPIO11_N (pin 28) and GPIO11_P (pin 30) for GPIO channel 11.
Pin 28 carries GPIO11_N and pin 30 carries GPIO11_P, forming a differential pair for GPIO channel 11. These are adjacent pins in row 2, maintaining differential pair integrity.Ground pins providing return current path and shielding for GPIO signals.
Pins 31 and 32 are both connected to GND, providing the third set of distributed ground pins in the connector. This placement after GPIO channels 8-11 maintains the consistent ground distribution pattern every 10 positions.Ground pins providing return current path and shielding for GPIO signals.
Pins 31 and 32 are both connected to GND, providing the third set of distributed ground pins in the connector. This placement after GPIO channels 8-11 maintains the consistent ground distribution pattern every 10 positions.Differential pair GPIO12_N (pin 33) and GPIO12_P (pin 35) for GPIO channel 12.
Pin 33 carries GPIO12_N and pin 35 carries GPIO12_P, forming a differential pair for GPIO channel 12. These are adjacent pins in row 1, continuing the sequential pattern.Differential pair GPIO12_N (pin 33) and GPIO12_P (pin 35) for GPIO channel 12.
Pin 33 carries GPIO12_N and pin 35 carries GPIO12_P, forming a differential pair for GPIO channel 12. These are adjacent pins in row 1, continuing the sequential pattern.Differential pair GPIO13_N (pin 34) and GPIO13_P (pin 36) for GPIO channel 13.
Pin 34 carries GPIO13_N and pin 36 carries GPIO13_P, forming a differential pair for GPIO channel 13. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO13_N (pin 34) and GPIO13_P (pin 36) for GPIO channel 13.
Pin 34 carries GPIO13_N and pin 36 carries GPIO13_P, forming a differential pair for GPIO channel 13. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO14_N (pin 37) and GPIO14_P (pin 39) for GPIO channel 14.
Pin 37 carries GPIO14_N and pin 39 carries GPIO14_P, forming a differential pair for GPIO channel 14. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO14_N (pin 37) and GPIO14_P (pin 39) for GPIO channel 14.
Pin 37 carries GPIO14_N and pin 39 carries GPIO14_P, forming a differential pair for GPIO channel 14. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO15_N (pin 38) and GPIO15_P (pin 40) for GPIO channel 15.
Pin 38 carries GPIO15_N and pin 40 carries GPIO15_P, forming a differential pair for GPIO channel 15. These are adjacent pins in row 2, maintaining differential pair integrity.Differential pair GPIO15_N (pin 38) and GPIO15_P (pin 40) for GPIO channel 15.
Pin 38 carries GPIO15_N and pin 40 carries GPIO15_P, forming a differential pair for GPIO channel 15. These are adjacent pins in row 2, maintaining differential pair integrity.Ground pins providing return current path and shielding for GPIO signals.
Pins 41 and 42 are both connected to GND, providing the fourth set of distributed ground pins in the connector. This placement after GPIO channels 12-15 maintains the consistent ground distribution pattern.Ground pins providing return current path and shielding for GPIO signals.
Pins 41 and 42 are both connected to GND, providing the fourth set of distributed ground pins in the connector. This placement after GPIO channels 12-15 maintains the consistent ground distribution pattern.Differential pair GPIO16_N (pin 43) and GPIO16_P (pin 45) for GPIO channel 16.
Pin 43 carries GPIO16_N and pin 45 carries GPIO16_P, forming a differential pair for GPIO channel 16. These are adjacent pins in row 1, continuing the sequential pattern.Differential pair GPIO16_N (pin 43) and GPIO16_P (pin 45) for GPIO channel 16.
Pin 43 carries GPIO16_N and pin 45 carries GPIO16_P, forming a differential pair for GPIO channel 16. These are adjacent pins in row 1, continuing the sequential pattern.Differential pair GPIO17_N (pin 44) and GPIO17_P (pin 46) for GPIO channel 17.
Pin 44 carries GPIO17_N and pin 46 carries GPIO17_P, forming a differential pair for GPIO channel 17. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO17_N (pin 44) and GPIO17_P (pin 46) for GPIO channel 17.
Pin 44 carries GPIO17_N and pin 46 carries GPIO17_P, forming a differential pair for GPIO channel 17. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO18_N (pin 47) and GPIO18_P (pin 49) for GPIO channel 18.
Pin 47 carries GPIO18_N and pin 49 carries GPIO18_P, forming a differential pair for GPIO channel 18. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO18_N (pin 47) and GPIO18_P (pin 49) for GPIO channel 18.
Pin 47 carries GPIO18_N and pin 49 carries GPIO18_P, forming a differential pair for GPIO channel 18. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO19_N (pin 48) and GPIO19_P (pin 50) for GPIO channel 19.
Pin 48 carries GPIO19_N and pin 50 carries GPIO19_P, forming a differential pair for GPIO channel 19. These are adjacent pins in row 2, maintaining differential pair integrity.Differential pair GPIO19_N (pin 48) and GPIO19_P (pin 50) for GPIO channel 19.
Pin 48 carries GPIO19_N and pin 50 carries GPIO19_P, forming a differential pair for GPIO channel 19. These are adjacent pins in row 2, maintaining differential pair integrity.Ground pins providing return current path and shielding for GPIO signals.
Pins 51 and 52 are both connected to GND, providing the fifth and final set of distributed ground pins in the connector. This placement after GPIO channels 16-19 maintains the consistent ground distribution pattern every 10 positions.Ground pins providing return current path and shielding for GPIO signals.
Pins 51 and 52 are both connected to GND, providing the fifth and final set of distributed ground pins in the connector. This placement after GPIO channels 16-19 maintains the consistent ground distribution pattern every 10 positions.Differential pair GPIO20_N (pin 53) and GPIO20_P (pin 55) for GPIO channel 20.
Pin 53 carries GPIO20_N and pin 55 carries GPIO20_P, forming a differential pair for GPIO channel 20. These are adjacent pins in row 1, continuing the sequential pattern.Differential pair GPIO20_N (pin 53) and GPIO20_P (pin 55) for GPIO channel 20.
Pin 53 carries GPIO20_N and pin 55 carries GPIO20_P, forming a differential pair for GPIO channel 20. These are adjacent pins in row 1, continuing the sequential pattern.Differential pair GPIO21_N (pin 54) and GPIO21_P (pin 56) for GPIO channel 21.
Pin 54 carries GPIO21_N and pin 56 carries GPIO21_P, forming a differential pair for GPIO channel 21. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO21_N (pin 54) and GPIO21_P (pin 56) for GPIO channel 21.
Pin 54 carries GPIO21_N and pin 56 carries GPIO21_P, forming a differential pair for GPIO channel 21. These are adjacent pins in row 2, maintaining the established pattern.Differential pair GPIO22_N (pin 57) and GPIO22_P (pin 59) for GPIO channel 22.
Pin 57 carries GPIO22_N and pin 59 carries GPIO22_P, forming a differential pair for GPIO channel 22. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO22_N (pin 57) and GPIO22_P (pin 59) for GPIO channel 22.
Pin 57 carries GPIO22_N and pin 59 carries GPIO22_P, forming a differential pair for GPIO channel 22. These are adjacent pins in row 1, following the systematic organization.Differential pair GPIO23_N (pin 58) and GPIO23_P (pin 60) for GPIO channel 23.
Pin 58 carries GPIO23_N and pin 60 carries GPIO23_P, forming a differential pair for GPIO channel 23. These are adjacent pins in row 2, completing the final GPIO channel of the connector. This completes the set of 24 differential GPIO pairs (GPIO0-GPIO23) in a well-organized, systematic manner that maintains signal integrity throughout. The differential pair integrity is maintained, and the pin assignment completes the logical sequence of the GPIO expansion connector.Differential pair GPIO23_N (pin 58) and GPIO23_P (pin 60) for GPIO channel 23.
Pin 58 carries GPIO23_N and pin 60 carries GPIO23_P, forming a differential pair for GPIO channel 23. These are adjacent pins in row 2, completing the final GPIO channel of the connector. This completes the set of 24 differential GPIO pairs (GPIO0-GPIO23) in a well-organized, systematic manner that maintains signal integrity throughout. The differential pair integrity is maintained, and the pin assignment completes the logical sequence of the GPIO expansion connector.FB14 - BLM15AG121SN1D ✅
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Connected to 1P8V power rail, serving as the input to the ferrite bead filter for the HDMI transmitter's digital supply.
Pin 1 connects to the 1P8V power rail. This ferrite bead filters the 1.8V supply before it reaches the HDMI_DVDD net on pin 2. According to the datasheet (page 4), ferrite beads have no polarity and both terminals are Input/Output. The BLM15AG121SN1D has 120Ω impedance at 100MHz (datasheet pages 1-3), which is appropriate for power supply filtering applications. The filtered output supplies U26 (ADV7513BSWZ HDMI transmitter) pins 1, 11, 31, and 51 (DVDD1-4), along with multiple decoupling capacitors: C58 and C67 (0.1uF), C230 and C231 (10nF), and C232 (10uF). This multi-stage decoupling strategy provides effective filtering across a wide frequency range. The ferrite bead provides isolation between the main 1.8V rail and the HDMI transmitter's digital supply, reducing noise coupling from other circuits on the board. This is a standard power supply filtering configuration for mixed-signal ICs.Connected to HDMI_DVDD net, providing filtered 1.8V power to the HDMI transmitter's digital supply pins.
Pin 2 connects to the HDMI_DVDD net, which is the filtered digital power supply for the HDMI transmitter. This net provides power to U26 digital supply pins (DVDD1, DVDD2, DVDD3, DVDD4 on pins 1, 11, 31, 51) and includes appropriate decoupling capacitors. The combination of ferrite bead filtering and multi-stage decoupling (0.1uF for high-frequency noise, 10nF for mid-frequency, and 10uF for bulk capacitance) ensures clean power delivery and minimizes noise across the frequency spectrum. Separating the digital supply filtering from other supply domains (analog, PLL, bandgap) is essential for maintaining signal integrity in mixed-signal designs like HDMI transmitters. The connection is correct and follows industry best practices.FB15 - BLM15AG121SN1D ✅
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Connected to 1P8V power rail, serving as the input to the ferrite bead filter for the HDMI transmitter's analog supply.
Pin 1 connects to the 1P8V power rail. This ferrite bead filters the 1.8V supply before it reaches the HDMI_AVDD net on pin 2. The datasheet (page 4) confirms ferrite beads have no polarity. The 120Ω impedance at 100MHz (datasheet pages 1-3) is suitable for analog power supply filtering, helping to isolate analog circuits from digital switching noise. The filtered output supplies U26 pins 15, 19, and 25 (AVDD1-3), which are the analog supply pins for the HDMI transmitter. The net includes decoupling capacitors C144 and C145 (0.1uF), C233 and C234 (10nF), and C235 (10uF). Separate filtering for analog supplies is critical in mixed-signal designs to prevent digital noise from coupling into sensitive analog circuitry, which could degrade the quality of the HDMI output signals.Connected to HDMI_AVDD net, providing filtered 1.8V power to the HDMI transmitter's analog supply pins.
Pin 2 connects to the HDMI_AVDD net, which is the filtered analog power supply for the HDMI transmitter. This net connects to U26 analog supply pins (AVDD1, AVDD2, AVDD3 on pins 15, 19, 25) and includes proper decoupling with multiple capacitor values to provide low impedance across a wide frequency range. The ferrite bead isolation between the main 1.8V rail and the analog supply is essential for preventing digital noise from coupling into sensitive analog circuits. This is particularly important for HDMI transmitters, where analog signal quality directly impacts compliance with HDMI specifications and overall signal integrity. The connection is correct and represents good design practice for mixed-signal circuits.FB16 - BLM15AG121SN1D ✅
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📄 DRCY referred to this Datasheet for this component.
Connected to N23924961 net (filtered output), providing filtered 3.3V power to the HDMI transmitter's DVDD_3V pin.
Pin 1 connects to net N23924961, which supplies U26 pin 29 (DVDD_3V) and associated decoupling capacitors C196 (0.1uF), C257 (10uF), and C262 (10nF). This is the filtered output side of the ferrite bead. The datasheet (page 4) confirms ferrite beads have no polarity, so either orientation is electrically correct. However, this ferrite bead has reversed orientation compared to FB14, FB15, FB17, and FB18, where pin 1 connects to the source rail and pin 2 to the filtered output. While not an electrical error, this orientation inconsistency represents a minor design style variation that could cause confusion during design review or troubleshooting. The 120Ω impedance at 100MHz (datasheet pages 1-3) is appropriate for filtering the 3.3V supply. The pin naming 'DVDD_3V' on U26 indicates this is a 3.3V digital supply pin, distinct from the other 1.8V supplies, likely for I/O compatibility or internal level shifting circuits.Connected to 3P3V power rail, serving as the input to the ferrite bead filter for the HDMI transmitter's 3.3V digital supply.
Pin 2 connects to the 3P3V (3.3V) power rail, which is the source for this filter. This is the only ferrite bead in the group that filters from 3.3V instead of 1.8V. The ferrite bead filters the 3.3V supply to provide clean power to U26 pin 29 (DVDD_3V). The orientation (source on pin 2, load on pin 1) is opposite to the other ferrite beads in this design (FB14, FB15, FB17, FB18), but this is not an electrical error since the datasheet explicitly states 'No polarity' (page 4). The connection functions correctly for power supply filtering. The use of 3.3V is intentional, as evidenced by the explicit pin naming 'DVDD_3V' on the HDMI transmitter, suggesting this supply powers 3.3V I/O or interface circuits within the IC.FB17 - BLM15AG121SN1D ✅
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📄 DRCY referred to this Datasheet for this component.
Connected to 1P8V power rail, serving as the input to the ferrite bead filter for the HDMI transmitter's bandgap voltage reference supply.
Pin 1 connects to the 1P8V power rail. This ferrite bead filters the 1.8V supply before it reaches the HDMI_BGVDD net on pin 2. The datasheet (page 4) confirms ferrite beads have no polarity. The 120Ω impedance at 100MHz (datasheet pages 1-3) is appropriate for filtering sensitive reference circuits. The filtered output supplies U26 pin 13 (BGVDD), which based on the pin naming is the bandgap voltage reference supply. Bandgap voltage references are critical precision circuits that generate stable reference voltages for the HDMI transmitter's internal analog circuits. These references are extremely sensitive to power supply noise, as any noise can directly affect the accuracy and stability of the reference voltage. Using a dedicated ferrite bead filter for the bandgap supply is essential for maintaining voltage reference accuracy and overall circuit performance.Connected to HDMI_BGVDD net, providing filtered 1.8V power to the HDMI transmitter's bandgap voltage reference supply.
Pin 2 connects to the HDMI_BGVDD net, which is the filtered bandgap voltage reference supply for the HDMI transmitter. This net connects to U26 pin 13 (BGVDD) and includes appropriate decoupling with C263 (0.1uF), C266 (10nF), and C267 (10uF). Bandgap voltage references are precision circuits that must maintain stable output voltages across temperature and supply variations. They are highly sensitive to power supply noise, which can degrade reference accuracy and introduce errors in downstream analog circuits. The ferrite bead provides essential isolation from the main 1.8V rail, preventing switching noise from other circuits from coupling into the bandgap reference. The multi-stage decoupling strategy further ensures low impedance across a wide frequency range. This design approach is critical for maintaining HDMI signal quality and meeting specification requirements.FB18 - BLM15AG121SN1D ✅
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📄 DRCY referred to this Datasheet for this component.
Connected to 1P8V power rail, serving as the input to the ferrite bead filter for the HDMI transmitter's PLL supply.
Pin 1 connects to the 1P8V power rail. This ferrite bead filters the 1.8V supply before it reaches the HDMI_PVDD net on pin 2. The datasheet (page 4) confirms ferrite beads have no polarity. The 120Ω impedance at 100MHz (datasheet pages 1-3) is suitable for PLL power supply filtering. The filtered output supplies U26 pin 12 (PVDD), which based on the pin naming is the PLL (Phase-Locked Loop) supply. PLLs generate the high-frequency clocks needed for HDMI signal transmission and are particularly sensitive to power supply noise. Any noise on the PLL supply can translate directly into jitter and phase noise in the output clock signals, which can cause timing violations and signal integrity issues in HDMI applications. Using a dedicated ferrite bead filter for the PLL supply is standard practice in high-speed digital designs to ensure clean clock generation.Connected to HDMI_PVDD net, providing filtered 1.8V power to the HDMI transmitter's PLL supply.
Pin 2 connects to the HDMI_PVDD net, which is the filtered PLL supply for the HDMI transmitter. This net connects to U26 pin 12 (PVDD) and includes proper decoupling with C296 (10uF), C265 (10nF), and C264 (0.1uF). PLLs are critical circuits that generate the high-frequency clocks required for HDMI signal transmission. They are particularly susceptible to power supply noise, which manifests as jitter and phase noise in the output clock signal. For HDMI applications, clock quality is critical for maintaining signal integrity, meeting timing specifications, and ensuring reliable data transmission. The ferrite bead provides necessary isolation from the main 1.8V rail to minimize noise coupling, while the multi-stage decoupling ensures low impedance across a wide frequency range. This design approach is essential for meeting HDMI signal integrity and EMI requirements.D1 - BAS16XV2T1G ❌
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Diode is incorrectly placed in series with pull-up resistor R225, creating an inappropriate topology that reduces the pull-up voltage and serves no clear purpose for the CEC application. Both D1 and R225 are marked DNI.
Diode is incorrectly placed in series with pull-up resistor R225, creating an inappropriate topology that reduces the pull-up voltage and serves no clear purpose for the CEC application. Both D1 and R225 are marked DNI.
R225 ✅
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Connected to 3P3V power rail as part of pull-up circuit with D1. Component is marked DNI (Do Not Install).
Pin 1 is connected to the 3P3V (3.3V) power rail. This resistor, with value 27.4K ohms, forms part of a pull-up network in series with diode D1 for the HDMI_CEC signal. The 27.4K value is within the typical range for CEC pull-up resistors (27K-47K ohms). The connection to 3P3V is appropriate for providing pull-up voltage. However, this resistor is part of a circuit with D1 that has fundamental design issues - the series diode unnecessarily reduces the pull-up voltage and serves no clear purpose for the CEC application (see D1 analysis). Both R225 and D1 are marked DNI, indicating this circuit was not populated in the final design. If a pull-up is needed for HDMI_CEC, R225 should be connected directly to the signal line without D1 in series. The pin connection to 3P3V is correct for a pull-up resistor function.Connected to D1 anode (net N22414199) as part of pull-up circuit. Component is marked DNI (Do Not Install).
Pin 2 is connected to net N22414199, which connects to D1 pin 2 (ANODE). This forms a series connection: 3P3V → R225 → D1 → HDMI_CEC. The 27.4K resistor value is appropriate for a CEC pull-up application and would limit current to approximately 120µA maximum, well within safe operating limits. However, this resistor is part of a circuit with D1 that has fundamental design issues - the series diode creates an inappropriate topology that reduces the pull-up voltage by the diode's forward voltage drop (0.7-1.25V) and serves no clear purpose for the CEC application (see D1 analysis). The connection is electrically correct for the circuit topology as drawn in the schematic. Both R225 and D1 are marked DNI, indicating this circuit was not populated. If a pull-up is needed, R225 pin 2 should connect directly to HDMI_CEC without D1 in series.J12 - PJ-002A ✅
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Center pin connects to 5P0V_IN, providing the positive power input from the barrel jack to the board.
Pin 1 is the CENTER pin of the barrel jack connector, connected to net 5P0V_IN. According to the PJ-002A datasheet (page 2), this is the 'Center pin ø2.0 mm for power input'. The datasheet (page 1) specifies 'Rated input voltage: 24 Vdc' and 'Rated input current: 2.5 A'. The 5P0V_IN net feeds into fuse F1 (pin 1) and connects to optional DNI capacitors C236 and C237 for input filtering, as well as to header J15 pin 2 for test/alternative input access. This is the standard configuration for a barrel jack center pin carrying positive voltage. The schematic indicates this is a 5V power input, which is well within the 24V rating of the connector, providing substantial voltage margin.Sleeve pin connects to GND, providing the ground return path for the power input.
Pin 2 is the SLEEVE pin of the barrel jack, connected to the GND net. According to the datasheet (page 2), this is 'Terminal 2, copper alloy with silver plating'. In standard barrel jack configurations, the sleeve (outer conductor) is always the ground/negative terminal. The GND net is the main ground plane of the board, connecting to numerous components including power management ICs U29 and U30, decoupling capacitors, and other ground returns throughout the design. This connection is correct and follows standard practice for barrel jack power connectors.Shunt pin connects to GND, providing additional ground connection or plug detection capability.
Pin 3 is the SHUNT pin, connected to the GND net. According to the datasheet (page 2), this is 'Terminal 3, brass with silver plating' and the connector has a 'Three terminal configuration with center pin and two outer terminals'. The shunt terminal in barrel jacks is typically used either as an additional ground connection for mechanical stability or for plug insertion detection. In this design, connecting it to GND along with the sleeve is a valid configuration that provides a robust ground connection. This is commonly done when plug detection functionality is not needed. The connection is correct and follows typical barrel jack implementation practices.F1 - ERB-RE4R00V ✅
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📄 DRCY referred to this Datasheet for this component.
Input side of fuse connects to 5P0V_IN from the barrel jack, providing overcurrent protection for the power input.
Pin 1 connects to net 5P0V_IN, which is the unprotected power input from barrel jack J12 pin 1. According to the ERB-RE4R00V datasheet (page 2), this is a 4.0A rated fuse from the ERBRE series (0603 size) with 'Rated voltage (Open circuit voltage): 32V DC' and 'Interrupting rating at rated voltage: 50A'. The fuse is appropriately rated for the application, as the barrel jack J12 is rated for 2.5A maximum (per PJ-002A datasheet page 1), providing adequate margin for normal operation while protecting against overcurrent conditions. The fuse placement at the input, immediately after the connector, is correct for protecting all downstream circuitry from overcurrent faults.Output side of fuse connects to 5P0V, providing protected power to the board after overcurrent protection.
Pin 2 connects to net 5P0V, which is the fused output that feeds the board's 5V systems. This net connects to jumper header J14 pin 1 (for power source selection), buffer U36 pin 1 (output enable), pull-down resistor R273 (10K to GND), and DNI capacitor C238 (10uF). The fuse correctly isolates the input power (5P0V_IN) from the board's 5V rail (5P0V), providing overcurrent protection. The 4A rating is appropriate for the system's power requirements while providing protection against short circuits or overload conditions. This is the standard and correct placement for a power input fuse in the power distribution architecture.J14 - PBC36SAAN ✅
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📄 DRCY referred to this Datasheet for this component.
Connects to 5P0V (fused barrel jack power), serving as one input option for the power selection jumper.
Pin 1 connects to net 5P0V, which is the fused output from F1 fed by the barrel jack. According to the PBC36SAAN datasheet (page 1), this is a male header with 'Current Rating: 3 Amps' and '0.100 inch [2.54mm] contact centers'. This is part of a 3-position power selection jumper where pin 1 provides the barrel jack power option. The user can place a jumper between pins 1-2 to select barrel jack power as the system power source (SYS_5P0V). The 3A current rating of the header is adequate for the system's power requirements, as the input is fused at 4A and the barrel jack is rated for 2.5A, providing appropriate margin. This is a standard power source selection configuration commonly used in development boards.Connects to SYS_5P0V (system power rail), serving as the common output of the power selection jumper.
Pin 2 connects to net SYS_5P0V, which is the main system 5V power rail that feeds the DC-DC converter ICs U29 and U30. The SYS_5P0V net powers multiple voltage regulators (VINDCD1, VINDCD2, VINLDO pins on both U29 and U30) and various pull-up resistors (R276, R277, R280, R283, R284, R285, R288) throughout the design. This is the center pin of the 3-position jumper, serving as the common connection point. By placing a jumper between pins 1-2 or 2-3, the user selects either barrel jack power (5P0V) or USB power (USB_VBUS) to power the system. This is a standard power multiplexing configuration that provides flexible power source selection, which is a common feature in development boards. The connection is correct.Connects to USB_VBUS (USB power), serving as the alternative input option for the power selection jumper.
Pin 3 connects to net USB_VBUS, which provides the USB power input option. The USB_VBUS net connects to DNI capacitor C287 (4.7uF, 16V) for filtering. This pin allows the user to select USB power as the system power source by placing a jumper between pins 2-3. The header's 3A current rating (per datasheet page 1) is adequate for USB power applications, though standard USB 2.0 is limited to 500mA and USB 3.0 to 900mA, so the actual current would be limited by the USB source rather than the header. This configuration provides flexibility for powering the board from either a barrel jack or USB connection, which is a common feature in development boards. The schematic note 'PEC POWER ONLY' near this area may indicate specific usage guidelines for this power selection. The connection is correct for this power multiplexing application.J15 - 0022102021 ✅
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Connects to N23204370 (PTH1 test point), providing access to an alternative power injection or test point.
Pin 1 connects to net N23204370, which only connects to PTH1 pin 1 (a plated through-hole test point). This header is marked as DNI (Do Not Install) in the attributes, indicating it's an optional component. According to the 0022102021 datasheet (page 1), this is a 2-circuit KK 100 Header Assembly with '2.54mm/0.100 inch' pin spacing and appropriate current handling capability. The connection to an isolated test point suggests this could be used for alternative power injection, current measurement, or testing purposes during development or manufacturing. Since the header is DNI and J15 pin 2 connects to 5P0V_IN (before the fuse), this header could be used to inject power or monitor the input voltage. This is likely a design provision for manufacturing test or field service rather than normal operation. The connection is correct for its intended purpose as a test/development feature.Connects to 5P0V_IN (unfused input power), providing direct access to the power input before the fuse.
Pin 2 connects to net 5P0V_IN, which is the unfused power input directly from barrel jack J12 pin 1, before fuse F1. This header is marked DNI (Do Not Install), indicating it's optional. The connection to 5P0V_IN before the fuse suggests this could be used for: (1) alternative power injection bypassing the barrel jack, (2) voltage monitoring at the input, or (3) manufacturing test access. Since it's DNI, this is a design provision rather than a normal operational feature. The placement before the fuse means any power injected here would still be protected by F1 before reaching the board's 5P0V rail. This is a reasonable test/service access point, though care must be taken if populated to ensure proper polarity and voltage. The connection is correct and intentional for providing flexible test and service access during development, manufacturing, or field service.U29 - DC-TO-DC PWR SUPPLY ❌
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FB2 feedback pin has incorrect voltage divider values - R282 should be approximately 70K instead of 10K, resulting in 0.94V output instead of the intended 1.8V.
GNDDCD1 ground pin is not connected to any net - this is a critical error that will prevent DCD1 from functioning.
VINDCD1 input voltage pin correctly connected to SYS_5P0V with proper 10µF decoupling capacitors.
Pin 1 (VINDCD1) is the input voltage for buck converter DCD1 and power supply for all internal digital/analog circuits (datasheet page 3). It is connected to SYS_5P0V net. The datasheet (page 5) specifies an input voltage range of 2.5V to 5.5V. The datasheet (page 2) requires a 10µF input capacitor. The schematic shows C241 (10µF, 16V) and C253 (10µF, 16V) connected between SYS_5P0V and GND, providing adequate input decoupling. This connection is correct.FB1 feedback pin correctly connected with proper voltage divider network producing approximately 1.0V output.
Pin 2 (FB1) is the feedback pin for DCD1 (datasheet page 3). It is connected to net N22934548 as part of a voltage divider network. The datasheet specifies a feedback regulation voltage of 0.8V typical (page 5: 0.785V min, 0.8V typ, 0.815V max). The feedback network consists of R2 (20K) from output N22939905 to intermediate node _N5, R5 (4.75K) from _N5 to FB1 (N22934548), and R279 (100K) from FB1 to GND, forming a series voltage divider. C242 (0.047µF) provides compensation between the output and FB1. The output voltage is calculated as: VOUT = VFB × (R2 + R5 + R279)/R279 = 0.8V × 124.75K/100K = 0.998V, which is within 0.2% of the intended 1.0V output indicated by the schematic text '1V @ 1.5A max' and R286 (0Ω) connecting to the 1P0V rail. This is well within acceptable tolerance and the connection is correct.ENDCD1 enable pin correctly pulled high to SYS_5P0V through R276 (10K) to enable DCD1 converter.
Pin 3 (ENDCD1) is the enable pin for DCD1 (datasheet page 3). The datasheet specifies this pin must be tied high or low and not left floating. It is connected to net REG_EN1, which is pulled up to SYS_5P0V through R276 (10K resistor). The datasheet (page 5) indicates that logic high threshold is 1.4V minimum. With the 10K pull-up to SYS_5P0V (nominally 5V), the pin will be held high, enabling the DCD1 converter. This configuration is correct.ENLDO1 enable pin correctly pulled high to SYS_5P0V through R280 (10K) to enable LDO1.
Pin 4 (ENLDO1) is the enable pin for LDO1 (datasheet page 3). The datasheet specifies this pin must be tied high or low and not left floating. It is connected to net REG_EN3, which is pulled up to SYS_5P0V through R280 (10K resistor). The datasheet (page 5) indicates that logic high threshold is 1.4V minimum. With the 10K pull-up to SYS_5P0V, the pin will be held high, enabling LDO1. This configuration is correct.VINLDO input voltage pin correctly connected to SYS_5P0V with proper 1µF decoupling capacitor.
Pin 5 (VINLDO) is the input voltage for LDO1 and LDO2 (datasheet page 3). The datasheet (page 5) specifies VINLDO supply voltage range of 1.5V to 5.5V, with the requirement that it be no higher than VINDCD1. It is connected to SYS_5P0V, which is the same supply as VINDCD1, satisfying this requirement. The datasheet (page 2) requires a 1µF input capacitor. The schematic shows C254 (1µF) connected between SYS_5P0V and GND, providing the required input decoupling. The connection is correct.VOLDO1 output pin correctly connected to 3P3V rail through R293 (0Ω) with required 1µF output capacitor (C251).
Pin 6 (VOLDO1) is the output voltage pin of LDO1 (datasheet page 3). It is connected to net N22979034. The datasheet (page 2) requires a 1µF output capacitor for LDO1. The schematic shows C251 (1µF) connected between N22979034 and GND, satisfying this requirement. R293 (0Ω resistor) connects N22979034 to the 3P3V rail, indicating that LDO1 is configured to provide the 3.3V supply. The schematic text indicates '3.3V @ 300mA max' which aligns with the LDO1 maximum output current specification of 300mA (datasheet page 5). The connection is correct.VOLDO2 output pin correctly connected to 2P5V rail through R329 (0Ω) with required 1µF output capacitor (C252).
Pin 7 (VOLDO2) is the output voltage pin of LDO2 (datasheet page 3). It is connected to net N22979674. The datasheet (page 2) requires a 1µF output capacitor for LDO2. The schematic shows C252 (1µF) connected between N22979674 and GND, satisfying this requirement. R329 (0Ω resistor) connects N22979674 to the 2P5V rail, indicating that LDO2 is configured to provide the 2.5V supply. The schematic text indicates '2.5V @ 300mA max' which aligns with the LDO2 maximum output current specification of 300mA (datasheet page 5). The connection is correct.ENLDO2 enable pin correctly pulled high to SYS_5P0V through R283 (10K) to enable LDO2.
Pin 8 (ENLDO2) is the enable pin for LDO2 (datasheet page 3). The datasheet specifies this pin must be tied high or low and not left floating. It is connected to net REG_EN4, which is pulled up to SYS_5P0V through R283 (10K resistor). The datasheet (page 5) indicates that logic high threshold is 1.4V minimum. With the 10K pull-up to SYS_5P0V, the pin will be held high, enabling LDO2. This configuration is correct.GNDLDO ground pin correctly connected to system GND.
Pin 9 (GNDLDO) is the power ground for LDO1 and LDO2 (datasheet page 3). It is connected to the GND net. Proper grounding is essential for the LDO regulators to function correctly. The connection to system ground is correct.ENDCD2 enable pin correctly pulled high to SYS_5P0V through R277 (10K) to enable DCD2 converter.
Pin 10 (ENDCD2) is the enable pin for DCD2 (datasheet page 3). The datasheet specifies this pin must be tied high or low and not left floating. It is connected to net REG_EN2, which is pulled up to SYS_5P0V through R277 (10K resistor). The datasheet (page 5) indicates that logic high threshold is 1.4V minimum. With the 10K pull-up to SYS_5P0V, the pin will be held high, enabling the DCD2 converter. This configuration is correct.VINDCD2 input voltage pin correctly connected to SYS_5P0V with proper 10µF decoupling capacitors.
Pin 12 (VINDCD2) is the input voltage for buck converter DCD2 (datasheet page 3). The datasheet (page 5) specifies an input voltage range of 2.5V to 5.5V. The datasheet (page 2) requires a 10µF input capacitor. The schematic shows VINDCD2 connected to SYS_5P0V, with C241 (10µF, 16V) and C253 (10µF, 16V) connected between SYS_5P0V and GND, providing adequate input decoupling shared with VINDCD1. The connection is correct.SW2 switching node correctly connected to inductor L9 (1.5µH) as required for DCD2 buck converter operation.
Pin 13 (SW2) is the switching node for DCD2 (datasheet page 3). The datasheet specifies this pin should be connected to one terminal of the inductor and recommends a 1.5µH inductor (page 2). It is connected to net N25830793, which connects to pin 1 of L9. L9 is specified as VLS252012ET-1R5N, which is a 1.5µH inductor with 2.0A typical rated current (inductor datasheet page 6), adequate for the 1.5A maximum load indicated by the schematic text '1.8V @ 1.5A max'. The connection is correct.GNDDCD2 ground pin correctly connected to system GND.
Pin 14 (GNDDCD2) is the power ground for DCD2 (datasheet page 3). It is connected to the GND net. Proper grounding is essential for the buck converter to function correctly and for current return paths. The connection to system ground is correct.SW1 switching node correctly connected to inductor L8 (1.5µH) as required for DCD1 buck converter operation.
Pin 16 (SW1) is the switching node for DCD1 (datasheet page 3). The datasheet specifies this pin should be connected to one terminal of the inductor and recommends a 1.5µH inductor (page 2). It is connected to net N22934179, which connects to pin 1 of L8. L8 is specified as VLS252012ET-1R5N, which is a 1.5µH inductor with 2.0A typical rated current (inductor datasheet page 6), adequate for the 1.5A maximum load indicated by the schematic text '1V @ 1.5A max'. The connection is correct.EPAD exposed pad correctly connected to system GND for thermal management.
Pin 17 (EPAD) is the exposed pad. The datasheet (page 3) specifies that the exposed pad should be connected to system ground. It is connected to the GND net. The datasheet (page 8) emphasizes that 'ISL9307 employs thermally enhanced TQFN package with exposed pad. Exposed pad should be properly soldered onto thermal pad of board to remove heat from IC. Thermal pad should be big enough for nine vias.' Connecting the exposed pad to ground provides both electrical grounding and thermal dissipation path, which is critical for the IC's thermal performance given the high currents involved in the buck converters. The connection is correct.L8 ✅
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Inductor input correctly connected to SW1 switching node of U29 for DCD1 buck converter.
Pin 1 of L8 is connected to net N22934179, which is the SW1 (pin 16) switching node of U29 (ISL9307). This is the correct connection for the inductor in a buck converter topology. The inductor is specified as VLS252012ET-1R5N with 1.5µH inductance and 2.0A typical rated current (datasheet page 6), which matches the ISL9307 datasheet recommendation (page 2) for a 1.5µH inductor. The 2.0A current rating is adequate for the 1.5A maximum load indicated by the schematic text '1V @ 1.5A max'. The connection is correct.Inductor output correctly connected to DCD1 output node with proper 10µF output capacitor and connection to 1P0V rail.
Pin 2 of L8 is connected to net N22939905, which is the output node of the DCD1 buck converter. This net connects to: C243 (10µF output capacitor to GND), C242 (0.047µF compensation capacitor), the feedback divider network (R2, R5, R279), and through R286 (0Ω) to the 1P0V rail. The ISL9307 datasheet (page 2) requires a 10µF output capacitor for DCD1, which is satisfied by C243. The inductor datasheet (page 6) shows DC resistance of 0.105Ω typical, 0.126Ω maximum, which will result in minimal voltage drop at 1.5A load (approximately 0.16V maximum). The connection is correct and follows the recommended buck converter topology.L9 ✅
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Inductor input correctly connected to SW2 switching node of U29 for DCD2 buck converter.
Pin 1 of L9 is connected to net N25830793, which is the SW2 (pin 13) switching node of U29 (ISL9307). This is the correct connection for the inductor in a buck converter topology. The inductor is specified as VLS252012ET-1R5N with 1.5µH inductance and 2.0A typical rated current (datasheet page 6), which matches the ISL9307 datasheet recommendation (page 2) for a 1.5µH inductor. The 2.0A current rating is adequate for the 1.5A maximum load indicated by the schematic text '1.8V @ 1.5A max'. The connection is correct.Inductor output correctly connected to DCD2 output node with proper 10µF output capacitor and connection to 1P8V rail.
Pin 2 of L9 is connected to net N25830712, which is the output node of the DCD2 buck converter. This net connects to: C245 (10µF output capacitor to GND), C244 (0.047µF compensation capacitor), the feedback divider network (R282, R281), and through R287 (0Ω) to the 1P8V rail. The ISL9307 datasheet (page 2) requires a 10µF output capacitor for DCD2, which is satisfied by C245. The inductor datasheet (page 6) shows DC resistance of 0.105Ω typical, 0.126Ω maximum, which will result in minimal voltage drop at 1.5A load (approximately 0.16V maximum). The connection is correct and follows the recommended buck converter topology. Note: While the inductor connection itself is correct, there is a critical issue with the feedback divider values (R282) connected to this output node, as documented in the U29 pin 11 analysis, which will prevent the output from reaching the intended 1.8V voltage.U30 - DC-TO-DC PWR SUPPLY ❌
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DCDPG is connected to an LED (CR8) through a pullup resistor, but the LED polarity is reversed, causing it to function opposite to the schematic notes which state 'Power Good = LED ON'.
VINDCD1 is correctly connected to SYS_5P0V, providing input power for DCD1 buck converter and internal circuits.
Pin 1 (VINDCD1) is connected to the SYS_5P0V net. According to the ISL9305H datasheet (page 2), this pin is the 'Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/analog circuits.' The datasheet (page 6) specifies the input voltage range as 2.5V to 5.5V. SYS_5P0V is the main system 5V rail, which falls within the acceptable range. The connection is properly decoupled with capacitors C241 and C253 (both 10µF) connected between SYS_5P0V and GND, meeting the datasheet requirement (page 3) for a 10µF input decoupling capacitor. This connection provides the necessary input power for the first buck converter and the IC's internal circuitry.FB1 is correctly connected to the DCD1 output (N22955654) for voltage feedback regulation.
Pin 2 (FB1) is connected to net N22955654, which is the output of the DCD1 buck converter after inductor L11. The ISL9305H datasheet (page 2) states: 'Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For fixed output versions, connect this pin directly to the DCD1 output.' This is a fixed output version, and FB1 is connected directly to the output through R330 (0 ohm resistor) to VDD_DSP. The output has proper decoupling with C248 (10µF) at the FB1 node and C218 (100µF) at the final VDD_DSP rail, exceeding the datasheet requirement (page 3) of 10µF + 1µF output capacitance. The datasheet (page 6) specifies the FB regulation voltage as 0.8V typical (0.785V min, 0.815V max). This connection enables proper voltage regulation for the DCD1 output.SCLK is correctly connected to I2C_SCL with appropriate pullup resistor for I2C communication.
Pin 3 (SCLK) is connected to the I2C_SCL net. According to the ISL9305H datasheet (page 2), this is the 'I2C interface clock pin.' The I2C_SCL net also connects to R284 (10K pullup resistor to SYS_5P0V), which is required for proper I2C bus operation. The datasheet (page 6) specifies the I2C interface speed as 400kb/s. The pullup resistor value of 10K is appropriate for I2C communication at this speed and voltage level. This connection enables I2C-based programming and control of the ISL9305H's output voltages and operating modes.SDAT is correctly connected to I2C_SDA with appropriate pullup resistor for I2C communication.
Pin 4 (SDAT) is connected to the I2C_SDA net. According to the ISL9305H datasheet (page 2), this is the 'I2C interface data pin.' The I2C_SDA net also connects to R285 (10K pullup resistor to SYS_5P0V), which is required for proper I2C bus operation. The datasheet (page 6) specifies the I2C interface speed as 400kb/s. The pullup resistor value of 10K is appropriate for I2C communication at this speed. This connection enables I2C-based programming and control of the ISL9305H's output voltages and operating modes.VINLDO1 is correctly connected to SYS_5P0V, providing input power for LDO1.
Pin 5 (VINLDO1) is connected to the SYS_5P0V net. According to the ISL9305H datasheet (page 2), this is the 'Input voltage for LDO1.' The datasheet (page 6) specifies: 'VINLDO1, VINLDO2 Supply Voltage: 1.5V min, 5.5V max. No higher than VINDCD1.' Since SYS_5P0V is the same voltage as VINDCD1 (pin 1), this connection satisfies the requirement that VINLDO1 not exceed VINDCD1. The 5V input is within the specified range and appropriate for the LDO1 regulator. The connection is properly decoupled with capacitor C254 (1µF) connected between SYS_5P0V and GND, meeting the datasheet requirement (page 3) for a 1µF input decoupling capacitor.VOLDO1 is correctly connected to output net N23028604 with proper output capacitance.
Pin 6 (VOLDO1) is connected to net N23028604, which is the output of LDO1. According to the ISL9305H datasheet (page 2), this is the 'Output voltage of LDO1.' The datasheet (page 3) states that an 'Output capacitor 1µF required' for the LDO outputs. The output net connects to C255 (10µF capacitor to GND), which exceeds the minimum requirement. The output is routed through R332 (0 ohm resistor) to the VDD_ADJ rail. The datasheet (page 6) specifies that LDO1 can provide up to 300mA output current. This connection properly implements the LDO1 output with adequate decoupling capacitance.VOLDO2 is correctly connected to output net N23029208 with proper output capacitance.
Pin 7 (VOLDO2) is connected to net N23029208, which is the output of LDO2. According to the ISL9305H datasheet (page 2), this is the 'Output voltage of LDO2.' The datasheet (page 3) states that an 'Output capacitor 1µF required' for the LDO outputs. The output net connects to C256 (10µF capacitor to GND), which exceeds the minimum requirement. The output is routed through R333 (0 ohm resistor) to the VDD_GPIO rail. The datasheet (page 6) specifies that LDO2 can provide up to 300mA output current. This connection properly implements the LDO2 output with adequate decoupling capacitance.VINLDO2 is correctly connected to SYS_5P0V, providing input power for LDO2.
Pin 8 (VINLDO2) is connected to the SYS_5P0V net. According to the ISL9305H datasheet (page 2), this is the 'Input voltage for LDO2.' The datasheet (page 6) specifies: 'VINLDO1, VINLDO2 Supply Voltage: 1.5V min, 5.5V max. No higher than VINDCD1.' Since SYS_5P0V is the same voltage as VINDCD1 (pin 1), this connection satisfies the requirement that VINLDO2 not exceed VINDCD1. The 5V input is within the specified range and appropriate for the LDO2 regulator.GNDLDO is correctly connected to system ground.
Pin 9 (GNDLDO) is connected to the GND net. According to the ISL9305H datasheet (page 2), this is the 'Power ground for LDO1 and LDO2.' This connection provides the ground reference for both LDO regulators. Proper grounding is essential for stable LDO operation and accurate output voltage regulation.FB2 is correctly connected to the DCD2 output (N22955725) for voltage feedback regulation.
Pin 11 (FB2) is connected to net N22955725, which is the output of the DCD2 buck converter after inductor L10. The ISL9305H datasheet (page 2) states: 'Feedback pin for DCD2, connect external voltage divider resistors between DCD2 output, this pin and ground. For fixed output versions, connect this pin directly to the DCD2 output.' This is a fixed output version, and FB2 is connected directly to the output through R331 (0 ohm resistor) to 1P35V. The output has proper decoupling with C250 (10µF) to ground, meeting the datasheet requirement (page 3) of 10µF + 1µF output capacitance. The datasheet (page 6) specifies the FB regulation voltage as 0.8V typical (0.785V min, 0.815V max). This connection enables proper voltage regulation for the DCD2 output.VINDCD2 is correctly connected to SYS_5P0V, providing input power for DCD2 buck converter.
Pin 12 (VINDCD2) is connected to the SYS_5P0V net. According to the ISL9305H datasheet (page 2), this is the 'Input voltage for buck converter DCD2.' The datasheet (page 6) specifies: 'VINDCD2 Input Voltage Range: 2.5V to VINDCD1.' Since SYS_5P0V is the same voltage as VINDCD1 (pin 1), this connection satisfies the requirement. The 5V input is within the acceptable range and provides the necessary input power for the second buck converter. The connection shares the same decoupling capacitors (C241 and C253, both 10µF) on the SYS_5P0V rail.SW2 is correctly connected to inductor L10 for the DCD2 buck converter switching node.
Pin 13 (SW2) is connected to net N22955745, which connects to L10 pin 1. According to the ISL9305H datasheet (page 2), this is the 'Switching node for DCD2, connect to one terminal of the inductor.' The datasheet (page 3) recommends a '1.5µH External inductor required' for the switching node. L10 is specified as a 1.5µH inductor (VLS252012ET-1R5N), which matches the recommendation. The other terminal of L10 connects to the FB2 feedback pin and the output capacitors, completing the buck converter output filter. This is the standard configuration for a synchronous buck converter.GNDDCD2 is correctly connected to system ground.
Pin 14 (GNDDCD2) is connected to the GND net. According to the ISL9305H datasheet (page 2), this is the 'Power ground for DCD2.' This connection provides the ground reference for the second buck converter. Proper grounding is essential for stable buck converter operation and accurate output voltage regulation.GNDDCD1 is correctly connected to system ground.
Pin 15 (GNDDCD1) is connected to the GND net. According to the ISL9305H datasheet (page 2), this is the 'Power ground for DCD1.' This connection provides the ground reference for the first buck converter. Proper grounding is essential for stable buck converter operation and accurate output voltage regulation.SW1 is correctly connected to inductor L11 for the DCD1 buck converter switching node.
Pin 16 (SW1) is connected to net N22955797, which connects to L11 pin 1. According to the ISL9305H datasheet (page 2), this is the 'Switching node for DCD1, connect to one terminal of the inductor.' The datasheet (page 3) recommends a '1.5µH External inductor required' for the switching node. L11 is specified as a 1.5µH inductor (VLS252012ET-1R5N), which matches the recommendation. The other terminal of L11 connects to the FB1 feedback pin and the output capacitors, completing the buck converter output filter. This is the standard configuration for a synchronous buck converter.EPAD is correctly connected to system ground.
Pin 17 (EPAD) is the exposed pad and is connected to the GND net. According to the ISL9305H datasheet (page 2), the exposed pad should 'Connect to system ground.' This connection provides thermal dissipation and electrical grounding for the IC package. Proper connection of the exposed pad to ground is critical for thermal performance and EMI reduction in switch-mode power supplies. The datasheet (page 5) specifies the thermal resistance θJC as 5°C/W for the 16 Ld TQFN package, and proper grounding of the exposed pad is essential to achieve this performance.L10 ✅
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Inductor terminal connected to SW2 switching node of U30 DCD2 buck converter.
Pin 1 of L10 is connected to net N22955745, which is the SW2 (pin 13) switching node of U30. This is one terminal of the output filter inductor for the DCD2 buck converter. The ISL9305H datasheet (page 3) recommends a 1.5µH inductor for the switching node. L10 is specified as VLS252012ET-1R5N, which according to the inductor datasheet (page 6) has an inductance of 1.5µH ±30%, DC resistance max 0.126Ω (0.105Ω typical), and rated current of 1.80A max (based on inductance change) and 1.45A typical (based on temperature rise). The current rating is adequate for the DCD2 maximum output current of 1.5A specified in the ISL9305H datasheet (page 6). This connection is part of the standard buck converter output filter topology.Inductor terminal connected to DCD2 output and FB2 feedback pin.
Pin 2 of L10 is connected to net N22955725, which connects to the FB2 feedback pin (pin 11) of U30 and the output capacitor C250 (10µF). This is the output terminal of the DCD2 buck converter filter inductor. The net also connects through R331 (0 ohm) to the 1P35V power rail. This configuration forms the output filter of the buck converter, where the inductor and output capacitor smooth the switching waveform to produce a stable DC output voltage. The connection to FB2 provides voltage feedback for regulation. This is the correct topology for a synchronous buck converter output stage.L11 ✅
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Inductor terminal connected to SW1 switching node of U30 DCD1 buck converter.
Pin 1 of L11 is connected to net N22955797, which is the SW1 (pin 16) switching node of U30. This is one terminal of the output filter inductor for the DCD1 buck converter. The ISL9305H datasheet (page 3) recommends a 1.5µH inductor for the switching node. L11 is specified as VLS252012ET-1R5N, which according to the inductor datasheet (page 6) has an inductance of 1.5µH ±30%, DC resistance max 0.126Ω (0.105Ω typical), and rated current of 1.80A max (based on inductance change) and 1.45A typical (based on temperature rise). The current rating is adequate for the DCD1 maximum output current of 1.5A specified in the ISL9305H datasheet (page 6). This connection is part of the standard buck converter output filter topology.Inductor terminal connected to DCD1 output and FB1 feedback pin.
Pin 2 of L11 is connected to net N22955654, which connects to the FB1 feedback pin (pin 2) of U30 and the output capacitor C248 (10µF). This is the output terminal of the DCD1 buck converter filter inductor. The net also connects through R330 (0 ohm) to the VDD_DSP power rail. This configuration forms the output filter of the buck converter, where the inductor and output capacitor smooth the switching waveform to produce a stable DC output voltage. The connection to FB1 provides voltage feedback for regulation. This is the correct topology for a synchronous buck converter output stage.C218 ✅
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Capacitor positive terminal connected to VDD_DSP power rail for bulk decoupling.
Pin 1 of C218 is connected to the VDD_DSP net, which is the output of the DCD1 buck converter (through R330 from N22955654). C218 is specified as a 100µF, 6.3V, X5R, low ESR capacitor in 1210 package (GRM32ER60J107ME20L). The schematic text notes indicate this rail powers the 'DSP CHIP' and 'BANKS 502 DDR3'. The ISL9305H datasheet (page 3) recommends '10µF + 1µF' output capacitors for the buck converters. C248 (10µF) is present at the immediate converter output, while C218 provides additional bulk capacitance at the load. The 100µF value provides substantial energy storage for transient load currents from power-hungry digital loads. The low ESR characteristic is important for minimizing voltage ripple and providing good transient response. The 6.3V rating is adequate for the VDD_DSP voltage level derived from the 5V input. This is good design practice for high-current digital loads.Capacitor negative terminal connected to ground for bulk decoupling.
Pin 2 of C218 is connected to the GND net. This completes the decoupling capacitor connection between the VDD_DSP power rail and ground. The large 100µF capacitance provides bulk energy storage to support transient load currents from the DSP chip, while the low ESR specification helps minimize voltage droop during load transients. This is a standard power supply decoupling configuration for high-current digital loads.U36 - NC7SZ125 ❌
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OE (Output Enable) pin is tied to 5P0V (HIGH), permanently disabling the buffer output. This is a design error that renders the component non-functional.
Data input A is connected to N25176046, which is pulled down to GND through R327 (1K resistor). This connection is correct for a buffer input.
Pin 2 is the data input A according to the datasheet (page 2). It connects to net N25176046, which also connects to R327 pin 1. R327 (1K resistor, RES0402_1K) has its other end (pin 2) connected to GND, providing a pull-down for the input. This configuration ensures the input has a defined logic LOW level when not driven by another source. The datasheet (page 3) specifies input voltage ranges: VIL (LOW level input) should be ≤0.35VCC for VCC=1.65-1.95V or ≤0.30VCC for VCC=2.3-5.5V. With VCC at 3.3V (pin 5), the pull-down ensures the input stays at a valid LOW level. The datasheet (page 3) explicitly notes that 'Unused inputs must be held HIGH or LOW. They may not float,' which this pull-down resistor satisfies. The input connection is appropriate and follows best practices for buffer inputs. However, due to the OE pin being held HIGH (pin 1 issue), this input configuration is currently non-functional in the overall circuit.Ground pin is correctly connected to the GND net.
Pin 3 is the ground reference according to the datasheet (page 2). It is connected to the GND net, which is the circuit's common ground reference. This is the standard and required connection for the device ground pin, ensuring proper operation of the internal circuitry and providing the reference for logic levels. The connection is correct.Three-state output Y is connected to TURBO_MODE signal with a 1K pull-up resistor (R328) to VDD_GPIO. The connection is correct, though the output is non-functional due to the OE pin issue.
Pin 4 is the three-state output Y according to the datasheet (page 2). It connects to the TURBO_MODE net, which also connects to R328 pin 2. R328 (1K resistor) has its other end (pin 1) connected to VDD_GPIO, providing a pull-up for the output signal. This is a standard configuration for a three-state buffer output, ensuring the signal has a defined level when the output is in high-impedance state. The datasheet (page 4) specifies output voltage levels: VOH (HIGH level output) minimum 2.90V at VCC=3.00V with IOH=-100µA, and VOL (LOW level output) maximum 0.10V at VCC=1.65-4.50V with IOL=100µA. The pull-up resistor ensures TURBO_MODE has a defined HIGH state when the output is in high-impedance mode. The datasheet (page 4) shows the device can sink 24mA at 3V VCC, which is more than sufficient for the approximately 3.3mA that would flow through the 1K pull-up when the output drives LOW. The output connection itself is correct and appropriate for a three-state buffer. However, because OE (pin 1) is tied HIGH, the output is permanently in high-impedance state, and TURBO_MODE is simply pulled HIGH by R328 rather than being actively driven by the buffer. The fundamental issue is with pin 1, not this pin's connection.VCC supply pin is correctly connected to 3P3V (3.3V power rail).
Pin 5 is the supply voltage VCC according to the datasheet (page 2). It is connected to the 3P3V net (3.3V power supply). The datasheet (page 3) specifies the operating supply voltage range as 1.65V to 5.50V, and 3.3V falls well within this range. The datasheet (page 4) also provides electrical characteristics at VCC=3.30V, confirming this is a standard and recommended operating voltage for this device. There is a DNI (Do Not Install) capacitor C288 (0.1µF, CAP0402_0P1UF_X5R_35V) between 3P3V and GND near this component, which would serve as a standard decoupling capacitor if installed. The VCC connection is correct and appropriate.CR8 - LED_0603_5MA_GRN ❌
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LED anode and cathode connections are reversed. Pin 1 (Cathode) is connected to the positive side through R288 from SYS_5P0V, and Pin 2 (Anode) is connected to GND. This reverse bias prevents the LED from lighting.
LED anode and cathode connections are reversed. Pin 1 (Cathode) is connected to the positive side through R288 from SYS_5P0V, and Pin 2 (Anode) is connected to GND. This reverse bias prevents the LED from lighting.
U34 - STM6904TWEDS6F ✅
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MR (Manual Reset) input is correctly connected to pushbutton switch SW2 for active-low manual reset functionality.
Pin 1 (MR) is connected to net PB_RESET_L, which connects to pushbutton switch SW2 pin 2 (with SW2 pin 1 connected to GND). The datasheet (page 6) describes MR as an 'Active-low manual reset input with internal pull-up resistor' and explicitly recommends (page 7): 'Connect a normally open momentary switch from MR to VSS; external debounce circuitry is not required.' The schematic implements exactly this configuration. When the button is pressed, MR is pulled to ground, asserting an active-low reset. The internal 10kΩ pull-up resistor to VCC keeps MR high during normal operation. R95 (marked DNI) provides an optional bypass path to PS_POR_L if needed. This connection follows the datasheet recommendation precisely.VCC is correctly connected to the 3P3V supply rail with appropriate decoupling capacitors.
Pin 2 (VCC) is connected to the 3P3V supply net. The datasheet (page 12) specifies an operating voltage range of 0.8 to 5.5V, so 3.3V is well within the acceptable range. The VCC pin serves dual purposes: primary supply voltage and integrated fixed threshold under-voltage monitor (page 6). The datasheet typical application diagram (page 8) shows a 0.1µF decoupling capacitor on VCC. The schematic provides multiple 0.1µF decoupling capacitors on the 3P3V rail (C259, C291, C295), ensuring adequate decoupling for the voltage monitor IC. This implementation matches datasheet recommendations.V2IN is correctly connected to monitor the 1P8V rail with appropriate fixed threshold selection.
Pin 3 (V2IN) is connected to the 1P8V supply net for monitoring the 1.8V rail. The datasheet (page 6) describes V2IN as 'Second fixed threshold input monitor' with customer-selectable, factory-programmed thresholds. The part number STM6904TWEDS6F includes ordering code information where the 'W' variant corresponds to a V2IN reset threshold of approximately 1.683V typical (1.666V min, 1.700V max at 25°C per page 13). Since the monitored 1.8V rail is above this threshold during normal operation, the monitor will correctly detect undervoltage conditions when the rail drops below the threshold. Decoupling capacitor C290 (0.1µF) is present on the 1P8V rail. This connection is appropriate for monitoring the 1.8V supply.VSS is correctly connected to ground.
Pin 4 (VSS) is connected to the GND net. The datasheet (page 6, 7) identifies this pin as 'Ground' for the power supply. This is a standard and correct ground connection required for the device operation.V3IN is correctly configured with resistor divider R298/R301 to monitor the 1P35V rail with calculated trip point of 1.2V.
Pin 5 (V3IN) is connected to net N23613650, which is the center node of a voltage divider formed by R298 (10kΩ from 1P35V) and R301 (10kΩ to GND). The datasheet (page 6) describes V3IN as 'Adjustable third reset comparator input' where 'RST is driven low when the voltage (VTRIP) at the pin falls below 600 mV internal reference voltage.' The datasheet (page 9) provides the formula: VTRIP = 0.6V × (R1 + R2) / R2, where R2 is the resistor to ground. Applying this formula: VTRIP = 0.6V × (10kΩ + 10kΩ) / 10kΩ = 1.2V. This means the 1.35V rail will trigger a reset if it drops below 1.2V, providing approximately 11.1% undervoltage protection margin. During normal operation, the voltage at V3IN is 1.35V × (10kΩ / 20kΩ) = 0.675V, which is above the V3IN threshold of 600mV typical (589-611mV range per page 14). The resistor values and connections are correct per datasheet guidance (page 7, 8, 9).V4IN is correctly configured with resistor divider R300/R299 to monitor the 1P0V rail with calculated trip point of 0.885V.
Pin 6 (V4IN) is connected to net N23614416, which is the center node of a voltage divider formed by R300 (4.75kΩ from 1P0V) and R299 (10kΩ to GND). The datasheet (page 6) describes V4IN as 'Adjustable fourth reset comparator input' operating identically to V3IN with a 600mV internal reference. Using the formula from page 9: VTRIP = 0.6V × (R1 + R2) / R2 = 0.6V × (4.75kΩ + 10kΩ) / 10kΩ = 0.885V. This means the 1.0V rail will trigger a reset if it drops below 0.885V, providing approximately 11.5% undervoltage protection margin. During normal operation, the voltage at V4IN is 1.0V × (10kΩ / 14.75kΩ) = 0.678V, which is above the V4IN threshold of 600mV typical (589-611mV range per page 14). The resistor values are specifically chosen to provide similar protection margins for both adjustable inputs. This configuration follows datasheet recommendations (page 7, 8, 9).TRSEL is correctly tied to GND to select the 210ms reset timeout period.
Pin 7 (TRSEL) is connected to the GND net (VSS). The datasheet (page 6) states: 'Controls selectable tREC. Two tREC options available. If pin is tied high (VCC), tREC = 420 ms. If pin is tied low (VSS), tREC = 210 ms. Note: Pin must be tied to VCC or VSS (do not float).' By tying TRSEL to ground, the design selects the shorter 210ms reset timeout period (tREC). The datasheet (page 7) confirms this requirement: 'Pin must be tied to VSS (210 ms) or VCC (420 ms).' The 210ms timeout is appropriate for most applications and allows adequate time for the system to stabilize after power-up or reset conditions. This connection correctly meets the datasheet requirement that the pin must not be left floating.RST_L output is correctly connected through 0-ohm resistor R96 to PS_POR_L with required external 10kΩ pull-up resistor.
Pin 8 (RST_L) is connected to net N25161882, which connects through R96 (0-ohm resistor) to the PS_POR_L net. The datasheet (page 6) describes RST as 'Active-low open drain reset output (10 kΩ internal pull-up)' and (page 7) states: 'The reset output (RST) pin is driven low and stays low whenever VCC or V2IN, or V3IN, or V4IN falls below its factory-trimmed or adjustable reset threshold or when MR goes to logic low. Connect an external pull-up resistor to VCC. A 10 kΩ pull-up resistor should be sufficient for most applications.' Following the PS_POR_L net, R326 (10kΩ) connects between PS_POR_L and 3P3V, providing the required external pull-up resistor. The 0-ohm resistor R96 simply extends the net to allow the reset signal to propagate to the rest of the system. This implementation correctly follows the datasheet recommendation for an open-drain output with external pull-up (page 7, 8).R298 - RES0402_10K ✅
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Upper resistor of voltage divider for V3IN, correctly connected to 1P35V supply rail.
Pin 1 is connected to the 1P35V supply rail, and pin 2 is connected to net N23613650 (the V3IN divider node). This 10kΩ resistor forms the upper portion of the voltage divider that sets the trip point for monitoring the 1.35V rail. Per the STM6904 datasheet formula (page 9): VTRIP = 0.6V × (R1 + R2) / R2, where R1 is R298 (10kΩ) and R2 is R301 (10kΩ), resulting in a trip point of 1.2V. This provides approximately 11.1% undervoltage protection for the 1.35V rail. The resistor value and connections are appropriate for this voltage monitoring application.Midpoint of voltage divider, correctly connected to U34 pin 5 (V3IN).
Pin 2 is connected to net N23613650, which connects to U34 pin 5 (V3IN) and R301 pin 2. This forms the voltage divider midpoint that feeds the adjustable voltage monitor input. During normal operation, this node sits at approximately 0.675V (1.35V × 10kΩ / 20kΩ), which is above the 600mV threshold required by the STM6904. The connection is correct as part of the voltage monitoring circuit.R299 - RES0402_10K ✅
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Lower resistor of voltage divider for V4IN, correctly connected to ground.
Pin 1 is connected to GND, and pin 2 is connected to net N23614416 (the V4IN divider node). This 10kΩ resistor forms the lower portion of the voltage divider that sets the trip point for monitoring the 1.0V rail. Per the STM6904 datasheet formula (page 9): VTRIP = 0.6V × (R1 + R2) / R2, where R1 is R300 (4.75kΩ) and R2 is R299 (10kΩ), resulting in a trip point of 0.885V. This provides approximately 11.5% undervoltage protection for the 1.0V rail. The resistor value and connections are appropriate for this voltage monitoring application.Midpoint of voltage divider, correctly connected to U34 pin 6 (V4IN).
Pin 2 is connected to net N23614416, which connects to U34 pin 6 (V4IN) and R300 pin 1. This forms the voltage divider midpoint that feeds the adjustable voltage monitor input. During normal operation, this node sits at approximately 0.678V (1.0V × 10kΩ / 14.75kΩ), which is above the 600mV threshold required by the STM6904. The connection is correct as part of the voltage monitoring circuit.R300 - RES0402_4K75 ✅
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Midpoint of voltage divider, correctly connected to U34 pin 6 (V4IN).
Pin 1 is connected to net N23614416, which connects to U34 pin 6 (V4IN) and R299 pin 2. This forms the voltage divider midpoint that feeds the adjustable voltage monitor input. The connection is correct as part of the voltage monitoring circuit for the 1.0V rail.Upper resistor of voltage divider for V4IN, correctly connected to 1P0V supply rail.
Pin 2 is connected to the 1P0V supply rail, and pin 1 is connected to net N23614416 (the V4IN divider node). This 4.75kΩ resistor forms the upper portion of the voltage divider that sets the trip point for monitoring the 1.0V rail. Per the STM6904 datasheet formula (page 9): VTRIP = 0.6V × (R1 + R2) / R2, where R1 is R300 (4.75kΩ) and R2 is R299 (10kΩ), resulting in a trip point of 0.885V. The 4.75kΩ value is specifically chosen to provide approximately 11.5% undervoltage protection for the 1.0V rail, which is similar to the protection margin provided for the 1.35V rail. This resistor value and connection are appropriate for this voltage monitoring application.R301 - RES0402_10K ✅
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Lower resistor of voltage divider for V3IN, correctly connected to ground.
Pin 1 is connected to GND, and pin 2 is connected to net N23613650 (the V3IN divider node). This 10kΩ resistor forms the lower portion of the voltage divider that sets the trip point for monitoring the 1.35V rail. Per the STM6904 datasheet formula (page 9): VTRIP = 0.6V × (R1 + R2) / R2, where R1 is R298 (10kΩ) and R2 is R301 (10kΩ), resulting in a trip point of 1.2V. The resistor value and connections are appropriate for this voltage monitoring application.Midpoint of voltage divider, correctly connected to U34 pin 5 (V3IN).
Pin 2 is connected to net N23613650, which connects to U34 pin 5 (V3IN) and R298 pin 2. This forms the voltage divider midpoint that feeds the adjustable voltage monitor input. The connection is correct as part of the voltage monitoring circuit for the 1.35V rail.U33 - NC7SZ125 ✅
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Output Enable (active low) connected to PS_POR_L from voltage monitor U34, controlling when the buffer drives BOARD_RESET_L.
Pin 1 is the OE (Output Enable) input, active low per datasheet page 2. It connects to PS_POR_L, which is driven by voltage monitor U34 (pin 8, RST_L) through R96. R326 provides a 10K pull-up to 3P3V. The circuit implements power-supply-controlled reset generation: When PS_POR_L is LOW (power supplies bad), OE is LOW and the buffer is enabled, driving output Y to match input A (which is pulled LOW by R294), thus asserting BOARD_RESET_L LOW. When PS_POR_L is HIGH (power supplies good), OE is HIGH and the buffer output enters high-impedance state, allowing R295 to pull BOARD_RESET_L HIGH to 1P8V. Input voltage levels are compatible with datasheet specifications (page 4): when HIGH, PS_POR_L is at 3.3V (above VIH = 0.70VCC = 2.31V); when LOW, it's below VIL = 0.30VCC = 0.99V. This connection correctly implements power-supply-dependent reset control with proper polarity preservation (both PS_POR_L and BOARD_RESET_L are active low).Data input A pulled LOW through R294 (1K to GND), intentionally configured to provide logic LOW input for reset generation.
Pin 2 is the data input A per datasheet page 2. It connects to net N23601474, which is pulled to GND through R294 (1K resistor). This intentionally holds the input at logic LOW. When the buffer is enabled (OE LOW), output Y drives LOW to assert the reset signal. When disabled (OE HIGH), the output is high-impedance. The 1K pull-down value is appropriate - the datasheet page 4 specifies input leakage current of ±10µA max, so the 1K resistor easily maintains a solid logic low level while not drawing excessive current. The input voltage range is 0 to 5.5V per datasheet page 3, so GND is well within specification. This configuration uses the buffer as a controlled pull-down switch: enabled state pulls BOARD_RESET_L LOW (asserting reset), disabled state allows BOARD_RESET_L to be pulled HIGH by R295 (de-asserting reset). The use of a resistor rather than direct GND connection provides flexibility for future modifications and limits current if the input were accidentally driven.Ground pin correctly connected to system GND.
Pin 3 is the ground reference per datasheet page 2. It is correctly connected to the GND net, providing the ground reference for the IC. This is a standard and correct connection.Three-state output Y drives BOARD_RESET_L with 1K pull-up to 1P8V through R295, implementing level translation from 3.3V to 1.8V logic.
Pin 4 is the three-state output Y per datasheet page 2. It drives BOARD_RESET_L, which connects to connector J13 pin 30 (RESET_N). R295 (1K) pulls this output to 1P8V when the buffer is in high-impedance state. When the buffer is enabled (OE LOW), it drives the output LOW (VOL < 0.10V per datasheet page 4), asserting the active-LOW reset signal. When disabled (OE HIGH), the output is high-Z and R295 pulls BOARD_RESET_L to 1.8V, de-asserting the reset. The datasheet page 4 confirms 'Output tolerates voltages above VCC when in 3-STATE', so the 1P8V pull-up is safe even though VCC is 3P3V. The 1K pull-up value is appropriate for a reset signal - it can source up to 1.8mA, sufficient for typical logic inputs, while the buffer can sink at least 16mA while maintaining VOL < 0.40V (datasheet page 4). This configuration correctly provides: (1) active-LOW reset assertion when power supplies are bad, (2) reset de-assertion at 1.8V logic level when power supplies are good, and (3) compatibility with 1.8V logic devices connected to BOARD_RESET_L.VCC power supply connected to 3P3V with proper decoupling.
Pin 5 is the VCC supply voltage pin per datasheet page 2. It is connected to the 3P3V rail (3.3V), which is within the specified operating range of 1.65V to 5.5V per datasheet page 3. Decoupling capacitor C259 (0.1µF) is provided between 3P3V and GND, which is appropriate for high-frequency noise filtering in this high-speed CMOS device. The datasheet page 3 shows recommended operating conditions include proper bypassing. This is a correct power supply connection following best practices.R294 - RES0402_1K ✅
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1K pull-down resistor connecting buffer input A (U33 pin 2) to GND, intentionally holding the input at logic LOW.
R294 is a 1K resistor configured as a pull-down. Pin 1 connects to net N23601474 (U33 pin 2, input A), and pin 2 connects to GND. This intentionally holds the buffer input at logic LOW, ensuring that when the buffer is enabled, it drives the output LOW to assert the reset signal. The 1K value is appropriate for a CMOS input pull-down - it provides a defined LOW state (the NC7SZ125 datasheet page 4 shows input leakage of ±10µA max, so voltage drop would be negligible) while not drawing excessive current. This resistor is part of the reset generation circuit where the buffer is used as a controlled switch to condition the reset signal. The use of a resistor rather than direct connection allows for potential future modifications if the input needs to be driven by an external signal. This is a correct implementation for the intended reset generation function.1K pull-down resistor connecting buffer input A (U33 pin 2) to GND, intentionally holding the input at logic LOW.
R294 is a 1K resistor configured as a pull-down. Pin 1 connects to net N23601474 (U33 pin 2, input A), and pin 2 connects to GND. This intentionally holds the buffer input at logic LOW, ensuring that when the buffer is enabled, it drives the output LOW to assert the reset signal. The 1K value is appropriate for a CMOS input pull-down - it provides a defined LOW state (the NC7SZ125 datasheet page 4 shows input leakage of ±10µA max, so voltage drop would be negligible) while not drawing excessive current. This resistor is part of the reset generation circuit where the buffer is used as a controlled switch to condition the reset signal. The use of a resistor rather than direct connection allows for potential future modifications if the input needs to be driven by an external signal. This is a correct implementation for the intended reset generation function.R295 - RES0402_1K ✅
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1K pull-up resistor connecting buffer output Y (U33 pin 4) to 1P8V rail, providing level translation for BOARD_RESET_L.
R295 is a 1K resistor configured as a pull-up. Pin 1 connects to 1P8V (1.8V supply), and pin 2 connects to BOARD_RESET_L (U33 pin 4, output Y). This provides level translation from 3.3V logic to 1.8V logic. When the buffer output is in high-impedance state (power supplies good, reset de-asserted), R295 pulls BOARD_RESET_L to 1.8V, providing a valid HIGH level for 1.8V logic devices. When the buffer actively drives LOW (power supplies bad, reset asserted), the buffer overrides the pull-up and drives the output to near 0V. The 1K value can source up to 1.8mA, which is sufficient for typical logic inputs, while providing adequate pull-up strength without causing excessive current draw when the buffer drives low. The NC7SZ125 datasheet page 4 confirms the output can tolerate voltages above VCC when in 3-STATE mode, so pulling to 1P8V while VCC is 3P3V is safe. This is a correct implementation for level translation and reset signal generation compatible with 1.8V logic domains.1K pull-up resistor connecting buffer output Y (U33 pin 4) to 1P8V rail, providing level translation for BOARD_RESET_L.
R295 is a 1K resistor configured as a pull-up. Pin 1 connects to 1P8V (1.8V supply), and pin 2 connects to BOARD_RESET_L (U33 pin 4, output Y). This provides level translation from 3.3V logic to 1.8V logic. When the buffer output is in high-impedance state (power supplies good, reset de-asserted), R295 pulls BOARD_RESET_L to 1.8V, providing a valid HIGH level for 1.8V logic devices. When the buffer actively drives LOW (power supplies bad, reset asserted), the buffer overrides the pull-up and drives the output to near 0V. The 1K value can source up to 1.8mA, which is sufficient for typical logic inputs, while providing adequate pull-up strength without causing excessive current draw when the buffer drives low. The NC7SZ125 datasheet page 4 confirms the output can tolerate voltages above VCC when in 3-STATE mode, so pulling to 1P8V while VCC is 3P3V is safe. This is a correct implementation for level translation and reset signal generation compatible with 1.8V logic domains.R95 - RES0402_0 ✅
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0-ohm resistor (DNI) that provides an option to bypass the voltage monitor circuit by directly connecting the pushbutton reset to the system reset signal.
Pin 1 connects to PB_RESET_L, which is connected to SW2 pin 2 (pushbutton) and U34 pin 1 (MR - Manual Reset input). Pin 2 connects to PS_POR_L, which is the main system reset signal that drives U33 pin 1 (output enable) and is routed to RESET_N through R98. This resistor is marked DNI (Do Not Install) in the attributes. The schematic includes a note stating 'populate R95 & remove R96 to bypass RESET circuit', which confirms this is an alternative configuration option. In normal operation, R96 is installed and connects the voltage monitor output (U34 pin 8) to PS_POR_L. When R95 is populated and R96 is removed, the pushbutton directly controls the system reset, bypassing the voltage monitoring function. This provides flexibility for different use cases or debugging scenarios. The 0-ohm value is appropriate for this jumper function, and R326 (10K pull-up to 3P3V) ensures PS_POR_L is in a defined high state when the pushbutton is not pressed.0-ohm resistor (DNI) that provides an option to bypass the voltage monitor circuit by directly connecting the pushbutton reset to the system reset signal.
Pin 1 connects to PB_RESET_L, which is connected to SW2 pin 2 (pushbutton) and U34 pin 1 (MR - Manual Reset input). Pin 2 connects to PS_POR_L, which is the main system reset signal that drives U33 pin 1 (output enable) and is routed to RESET_N through R98. This resistor is marked DNI (Do Not Install) in the attributes. The schematic includes a note stating 'populate R95 & remove R96 to bypass RESET circuit', which confirms this is an alternative configuration option. In normal operation, R96 is installed and connects the voltage monitor output (U34 pin 8) to PS_POR_L. When R95 is populated and R96 is removed, the pushbutton directly controls the system reset, bypassing the voltage monitoring function. This provides flexibility for different use cases or debugging scenarios. The 0-ohm value is appropriate for this jumper function, and R326 (10K pull-up to 3P3V) ensures PS_POR_L is in a defined high state when the pushbutton is not pressed.R96 - RES0402_0 ✅
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0-ohm resistor that connects the voltage monitor reset output to the system reset signal in normal operation.
Pin 1 connects to N25161882, which is the output of U34 pin 8 (RST_L - Reset output, active low). Pin 2 connects to PS_POR_L, the main system reset signal. This resistor is installed by default (no DNI marking) and provides the normal reset path from the voltage monitor to the system. U34 (STM6904TWEDS6F) is a 4-input voltage monitor that monitors 3P3V (VCC on pin 2), 1P8V (V2IN on pin 3), 1P35V (through resistor divider on V3IN pin 5), and 1P0V (through resistor divider on V4IN pin 6). When any monitored voltage falls out of specification or the manual reset button is pressed, U34 asserts its reset output low, which propagates through R96 to PS_POR_L. The schematic note indicates that R96 should be removed if R95 is populated to bypass the reset circuit. The 0-ohm value is appropriate for this series connection. This is the primary reset path in the default configuration, ensuring proper system reset based on power supply monitoring.0-ohm resistor that connects the voltage monitor reset output to the system reset signal in normal operation.
Pin 1 connects to N25161882, which is the output of U34 pin 8 (RST_L - Reset output, active low). Pin 2 connects to PS_POR_L, the main system reset signal. This resistor is installed by default (no DNI marking) and provides the normal reset path from the voltage monitor to the system. U34 (STM6904TWEDS6F) is a 4-input voltage monitor that monitors 3P3V (VCC on pin 2), 1P8V (V2IN on pin 3), 1P35V (through resistor divider on V3IN pin 5), and 1P0V (through resistor divider on V4IN pin 6). When any monitored voltage falls out of specification or the manual reset button is pressed, U34 asserts its reset output low, which propagates through R96 to PS_POR_L. The schematic note indicates that R96 should be removed if R95 is populated to bypass the reset circuit. The 0-ohm value is appropriate for this series connection. This is the primary reset path in the default configuration, ensuring proper system reset based on power supply monitoring.R98 - RES0402_0 ✅
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0-ohm resistor that routes the system reset signal to the external connector.
Pin 1 connects to PS_POR_L, which is the main system reset signal (pulled up to 3P3V through R326 and driven by the voltage monitor through R96 or by the pushbutton through R95 in bypass mode). Pin 2 connects to RESET_N, which is routed to J13 pin 30 on the external connector. This resistor provides a direct connection from the internal reset signal to the external interface, allowing external systems to monitor or use the board's reset status. The 0-ohm value is appropriate for this direct connection while providing the option to add series resistance if needed for signal integrity in future revisions. The signal name RESET_N suggests an active-low reset, which is consistent with PS_POR_L (Power-On Reset, active Low). This connection allows the reset signal to be shared with external systems through the connector, enabling coordinated reset behavior across multiple boards or systems.0-ohm resistor that routes the system reset signal to the external connector.
Pin 1 connects to PS_POR_L, which is the main system reset signal (pulled up to 3P3V through R326 and driven by the voltage monitor through R96 or by the pushbutton through R95 in bypass mode). Pin 2 connects to RESET_N, which is routed to J13 pin 30 on the external connector. This resistor provides a direct connection from the internal reset signal to the external interface, allowing external systems to monitor or use the board's reset status. The 0-ohm value is appropriate for this direct connection while providing the option to add series resistance if needed for signal integrity in future revisions. The signal name RESET_N suggests an active-low reset, which is consistent with PS_POR_L (Power-On Reset, active Low). This connection allows the reset signal to be shared with external systems through the connector, enabling coordinated reset behavior across multiple boards or systems.R326 - RES0402_10K ✅
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10K pull-up resistor that pulls the system reset signal to 3.3V when not actively driven low.
Pin 1 connects to PS_POR_L, the main system reset signal. Pin 2 connects to 3P3V, the 3.3V power supply rail. This resistor provides a pull-up for the PS_POR_L signal, ensuring it defaults to a high (inactive) state when not being actively driven low by the voltage monitor (through R96) or pushbutton (through R95 in bypass mode). PS_POR_L drives U33 pin 1 (O\E, output enable, active low), so when PS_POR_L is high (pulled up), the buffer is disabled. When PS_POR_L is pulled low by a reset condition, the buffer is enabled and drives BOARD_RESET_L low. The 10K value is appropriate for a reset signal pull-up, providing sufficient pull-up strength while limiting current draw when the signal is driven low. Using 3P3V is correct because U33 (NC7SZ125 buffer) is powered from 3P3V (pin 5), and U34 voltage monitor is also powered from 3P3V (pin 2), ensuring compatible logic levels throughout the reset circuit. This is a standard configuration for active-low reset signals with open-drain or tri-state drivers.10K pull-up resistor that pulls the system reset signal to 3.3V when not actively driven low.
Pin 1 connects to PS_POR_L, the main system reset signal. Pin 2 connects to 3P3V, the 3.3V power supply rail. This resistor provides a pull-up for the PS_POR_L signal, ensuring it defaults to a high (inactive) state when not being actively driven low by the voltage monitor (through R96) or pushbutton (through R95 in bypass mode). PS_POR_L drives U33 pin 1 (O\E, output enable, active low), so when PS_POR_L is high (pulled up), the buffer is disabled. When PS_POR_L is pulled low by a reset condition, the buffer is enabled and drives BOARD_RESET_L low. The 10K value is appropriate for a reset signal pull-up, providing sufficient pull-up strength while limiting current draw when the signal is driven low. Using 3P3V is correct because U33 (NC7SZ125 buffer) is powered from 3P3V (pin 5), and U34 voltage monitor is also powered from 3P3V (pin 2), ensuring compatible logic levels throughout the reset circuit. This is a standard configuration for active-low reset signals with open-drain or tri-state drivers.J13 - BSH-030-01-F-D-A ✅
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System 5V power supply pins connected in parallel to SYS_5P0V net.
Pins 1 and 2 are both connected to the SYS_5P0V net, providing 5V system power through the expansion connector. The parallel connection of these pins is standard design practice to increase current carrying capacity and reduce voltage drop, which is particularly important for power distribution. The datasheet (page 1) describes this as a double row socket assembly with 0.5mm pitch and phosphor bronze contacts with selective gold plating, suitable for power distribution applications. The use of two adjacent pins in the double-row configuration for the same power rail is appropriate for distributing current and maintaining power integrity.System 5V power supply pins connected in parallel to SYS_5P0V net.
Pins 1 and 2 are both connected to the SYS_5P0V net, providing 5V system power through the expansion connector. The parallel connection of these pins is standard design practice to increase current carrying capacity and reduce voltage drop, which is particularly important for power distribution. The datasheet (page 1) describes this as a double row socket assembly with 0.5mm pitch and phosphor bronze contacts with selective gold plating, suitable for power distribution applications. The use of two adjacent pins in the double-row configuration for the same power rail is appropriate for distributing current and maintaining power integrity.I2C clock signal (I2C_SCL) for serial communication interface.
Pin 3 is connected to the I2C_SCL net, which is the clock line for the I2C communication bus. This is a standard bidirectional interface signal for inter-chip communication, as indicated by the electrical_type 'Io' in the schematic. The placement adjacent to pin 4 (I2C_SDA) is good design practice for paired signals to minimize crosstalk and maintain signal integrity. The connector's 0.5mm pitch allows for close coupling of the I2C signal pair.I2C data signal (I2C_SDA) for serial communication interface.
Pin 4 is connected to the I2C_SDA net, which is the data line for the I2C communication bus. This pin is adjacent to pin 3 (I2C_SCL), completing the I2C interface. The adjacent placement of I2C signals is appropriate for signal integrity, routing efficiency, and maintaining proper timing relationships between clock and data lines.Regulator enable control signal 1 (REG_EN1).
Pin 5 is connected to REG_EN1, which is a control signal for enabling a voltage regulator. This is part of a set of four regulator enable signals (REG_EN1 through REG_EN4) distributed across the connector, providing independent power management control for external modules.Regulator enable control signal 2 (REG_EN2).
Pin 6 is connected to REG_EN2, the second regulator enable signal. This pin is on the opposite row from pin 5 (REG_EN1), following the double-row configuration of the connector. The distribution of regulator enable signals across the connector allows for flexible power management of external modules.Regulator enable control signal 3 (REG_EN3).
Pin 7 is connected to REG_EN3, the third regulator enable signal. This continues the pattern of regulator control signals being distributed across the connector for comprehensive power management control.Regulator enable control signal 4 (REG_EN4).
Pin 8 is connected to REG_EN4, the fourth and final regulator enable signal. This completes the set of regulator control signals, providing full power management capability through the expansion connector.Programming I/O signal (PROG_IO) for device programming interface.
Pin 9 is connected to PROG_IO, which is used for device programming operations. This is a standard control signal for programming or configuration purposes, allowing external programming tools or modules to interface with the system for firmware updates or configuration.Unconnected pin, intentionally left as no-connect (NC).
Pin 10 has no net connection (empty net field in the XML). The schematic includes explicit text notation 'NC_PORT' which indicates this is an intentional no-connect pin. In expansion connector designs, it's common practice to leave certain pins unconnected for future use, board identification, or to provide mechanical keying. The datasheet (page 1) describes this as a generic connector where pin assignments are application-specific, so having unused pins is acceptable. Given the explicit NC notation in the schematic, this is an intentional design decision.Ground pins providing return path and reference.
Pins 11 and 12 are both connected to GND. These are the first pair of ground pins in the connector, positioned after the initial control and communication signals. The parallel ground connections help reduce ground impedance and provide a solid reference plane. Multiple ground pins distributed throughout the connector are essential for maintaining signal integrity, reducing ground bounce, and providing low-impedance return paths for both signals and power supplies.Ground pins providing return path and reference.
Pins 11 and 12 are both connected to GND. These are the first pair of ground pins in the connector, positioned after the initial control and communication signals. The parallel ground connections help reduce ground impedance and provide a solid reference plane. Multiple ground pins distributed throughout the connector are essential for maintaining signal integrity, reducing ground bounce, and providing low-impedance return paths for both signals and power supplies.DSP X-axis identification bit 0 (DSP_XID0).
Pin 13 is connected to DSP_XID0, which is the least significant bit of the DSP X-axis identification interface. This is part of a coordinate-based identification system with X and Y axes, each having 4 bits (0-3), allowing for 8-bit 2D identification of external DSP modules. The systematic organization of ID signals facilitates board identification and configuration.DSP Y-axis identification bit 0 (DSP_YID0).
Pin 14 is connected to DSP_YID0, which is the least significant bit of the DSP Y-axis identification interface. This pin is adjacent to pin 13 (DSP_XID0), organizing the X and Y ID bits in pairs across the two rows of the connector. This pairing is good design practice for maintaining signal integrity and simplifying routing.DSP X-axis identification bit 1 (DSP_XID1).
Pin 15 is connected to DSP_XID1, the second bit of the DSP X-axis identification. This continues the pattern of X-axis ID bits on odd-numbered pins, maintaining the systematic organization of the identification interface.DSP Y-axis identification bit 1 (DSP_YID1).
Pin 16 is connected to DSP_YID1, the second bit of the DSP Y-axis identification. This maintains the pattern of Y-axis ID bits on even-numbered pins adjacent to their X-axis counterparts, which is optimal for signal integrity and routing.DSP X-axis identification bit 2 (DSP_XID2).
Pin 17 is connected to DSP_XID2, the third bit of the DSP X-axis identification. The consistent organization of ID signals continues through the connector.DSP Y-axis identification bit 2 (DSP_YID2).
Pin 18 is connected to DSP_YID2, the third bit of the DSP Y-axis identification. The adjacent pairing with DSP_XID2 maintains the established pattern.DSP X-axis identification bit 3 (DSP_XID3).
Pin 19 is connected to DSP_XID3, the most significant bit of the DSP X-axis identification. This completes the 4-bit X-axis identification interface.DSP Y-axis identification bit 3 (DSP_YID3).
Pin 20 is connected to DSP_YID3, the most significant bit of the DSP Y-axis identification. This completes the 4-bit Y-axis identification interface and the full 8-bit coordinate-based identification system.Ground pins providing return path and reference.
Pins 21 and 22 are both connected to GND. These ground pins are strategically placed after the DSP ID signal group, providing a ground reference between signal groups to minimize crosstalk and improve signal integrity. The distribution of ground pins throughout the connector is essential for maintaining signal quality.Ground pins providing return path and reference.
Pins 21 and 22 are both connected to GND. These ground pins are strategically placed after the DSP ID signal group, providing a ground reference between signal groups to minimize crosstalk and improve signal integrity. The distribution of ground pins throughout the connector is essential for maintaining signal quality.DSP flag signal (DSP_FLAG) for status indication.
Pin 23 is connected to DSP_FLAG, which is a status or control flag signal for the DSP interface. This provides additional control or status information for DSP operations beyond the identification signals.UART receive signal (UART_RX) for serial communication.
Pin 24 is connected to UART_RX, which is the receive line for UART serial communication. This pin is positioned near pin 26 (UART_TX), grouping the UART interface signals together for logical organization and routing efficiency.Turbo mode control signal (TURBO_MODE).
Pin 25 is connected to TURBO_MODE, which is a control signal for enabling a turbo or high-performance operating mode. This allows external control of system performance settings.UART transmit signal (UART_TX) for serial communication.
Pin 26 is connected to UART_TX, which is the transmit line for UART serial communication. This completes the UART interface pair with pin 24 (UART_RX), providing full bidirectional serial communication capability.S/PDIF digital audio signal (SPDIF).
Pin 27 is connected to SPDIF, which is a Sony/Philips Digital Interface Format signal for digital audio transmission. This provides digital audio connectivity through the connector, allowing external audio modules or devices to interface with the system.User LED control signal (USER_LED).
Pin 28 is connected to USER_LED, which drives LED CR10 (green LED, part number LTST-C193KGKT-5A) through current limiting resistor R30 (240 ohm). The schematic shows CR10 is a green LED with a 2V forward voltage and 5mA current rating. The LED circuit has the anode connected to USER_LED and the cathode connected through R30 to GND, which is the correct polarity for LED operation. The 240 ohm resistor provides appropriate current limiting for the 5mA LED.JTAG boot enable signal (JTAG_BOOT_EN).
Pin 29 is connected to JTAG_BOOT_EN, which is a control signal to enable JTAG boot mode. This is part of the JTAG interface group that includes pins 37-40, providing debug and programming capabilities. The signal allows external control of the boot configuration.Active-low reset signal (RESET_N) connected to power-on-reset circuit.
Pin 30 is connected to RESET_N, which is the system reset signal (active low). Tracing the connection, RESET_N connects through R98 (0 ohm resistor) to PS_POR_L, which is the power-on-reset output from voltage monitor U34 (STM6904TWEDS6F). The voltage monitor U34 generates PS_POR_L on pin 8 (RST_L) after monitoring multiple voltage rails (3P3V, 1P8V, 1P35V via divider, and 1P0V via divider). The schematic note states 'populate R95 & remove R96 to bypass RESET circuit', indicating this is an intentional design with configuration options. R98 is the normal configuration path, and the 0 ohm resistor allows for easy reconfiguration if needed. This connection allows external modules to receive the system reset signal and synchronize their reset timing with the main system.Ground pins providing return path and reference.
Pins 31 and 32 are both connected to GND. These ground pins are positioned after the communication and control signal group and before the analog signals, providing ground reference between signal groups and helping to isolate different types of signals.Ground pins providing return path and reference.
Pins 31 and 32 are both connected to GND. These ground pins are positioned after the communication and control signal group and before the analog signals, providing ground reference between signal groups and helping to isolate different types of signals.ADC negative input (VADC_N) for differential analog measurement.
Pin 33 is connected to VADC_N, which is the negative input of a differential ADC interface. This pin is paired with pin 34 (VADC_P) to form a differential analog input pair. The adjacent placement of differential pairs is critical for maintaining signal integrity, minimizing skew, and ensuring proper common-mode noise rejection. The connector's 0.5mm pitch (datasheet page 1) allows for close coupling of the differential pair.ADC positive input (VADC_P) for differential analog measurement.
Pin 34 is connected to VADC_P, which is the positive input of a differential ADC interface. This completes the differential pair with pin 33 (VADC_N). The adjacent placement is optimal for differential signaling, maintaining signal integrity and common-mode noise rejection.Ground pins providing return path and reference for analog signals.
Pins 35 and 36 are both connected to GND. These ground pins are strategically placed immediately after the analog input pins (VADC_N/P), providing a clean ground reference for the analog signals and helping to isolate them from digital signals. This placement is excellent design practice for mixed-signal applications, as ground pins surrounding sensitive analog signals help reduce noise coupling.Ground pins providing return path and reference for analog signals.
Pins 35 and 36 are both connected to GND. These ground pins are strategically placed immediately after the analog input pins (VADC_N/P), providing a clean ground reference for the analog signals and helping to isolate them from digital signals. This placement is excellent design practice for mixed-signal applications, as ground pins surrounding sensitive analog signals help reduce noise coupling.JTAG Test Mode Select signal (JTAG_TMS).
Pin 37 is connected to JTAG_TMS, which is the Test Mode Select signal of the JTAG interface. This is part of the standard 4-wire JTAG interface (TMS, TDI, TCK, TDO) used for debugging and programming. The grouping of JTAG signals together (pins 37-40) is appropriate for maintaining signal integrity and simplifying routing.JTAG Test Data In signal (JTAG_TDI).
Pin 38 is connected to JTAG_TDI, which is the Test Data In signal of the JTAG interface. This pin receives data from the JTAG controller and is part of the standard JTAG debug and programming interface.JTAG Test Clock signal (JTAG_TCK).
Pin 39 is connected to JTAG_TCK, which is the Test Clock signal of the JTAG interface. This provides the clock for JTAG operations and is a critical timing signal for the JTAG protocol.JTAG Test Data Out signal (JTAG_TDO).
Pin 40 is connected to JTAG_TDO, which is the Test Data Out signal of the JTAG interface. This pin transmits data from the target device to the JTAG controller. This completes the standard JTAG interface (TMS, TDI, TCK, TDO) for debugging and programming operations.Ground pins providing return path and reference.
Pins 41 and 42 are both connected to GND. These ground pins are positioned after the JTAG signal group and before the power supply section, providing ground reference between signal groups and helping to separate different functional areas of the connector.Ground pins providing return path and reference.
Pins 41 and 42 are both connected to GND. These ground pins are positioned after the JTAG signal group and before the power supply section, providing ground reference between signal groups and helping to separate different functional areas of the connector.1.0V power supply pins connected in parallel to 1P0V net.
Pins 43 and 44 are both connected to the 1P0V net, providing 1.0V power supply. The parallel connection increases current carrying capacity, which is important for processor core power. This voltage is monitored by U34 (voltage monitor) through a resistor divider network (R300 4.75K and R299 10K) on net N23614416, which scales the 1.0V to an appropriate level for the monitor input. The monitoring ensures proper power sequencing and system protection.1.0V power supply pins connected in parallel to 1P0V net.
Pins 43 and 44 are both connected to the 1P0V net, providing 1.0V power supply. The parallel connection increases current carrying capacity, which is important for processor core power. This voltage is monitored by U34 (voltage monitor) through a resistor divider network (R300 4.75K and R299 10K) on net N23614416, which scales the 1.0V to an appropriate level for the monitor input. The monitoring ensures proper power sequencing and system protection.DSP core voltage supply pins connected in parallel to VDD_DSP net.
Pins 45 and 46 are both connected to the VDD_DSP net, providing power to the DSP core. The parallel connection increases current carrying capacity, which is particularly important for high-current DSP applications. DSP cores typically require significant current, making the parallel connection essential for adequate power delivery.DSP core voltage supply pins connected in parallel to VDD_DSP net.
Pins 45 and 46 are both connected to the VDD_DSP net, providing power to the DSP core. The parallel connection increases current carrying capacity, which is particularly important for high-current DSP applications. DSP cores typically require significant current, making the parallel connection essential for adequate power delivery.1.35V power supply pins connected in parallel to 1P35V net.
Pins 47 and 48 are both connected to the 1P35V net, providing 1.35V power supply. This voltage level is commonly used for DDR3L memory interfaces. The parallel connection increases current carrying capacity. This voltage is monitored by U34 (voltage monitor) through a resistor divider network (R298 10K and R301 10K) on net N23613650, ensuring proper voltage levels for system operation.1.35V power supply pins connected in parallel to 1P35V net.
Pins 47 and 48 are both connected to the 1P35V net, providing 1.35V power supply. This voltage level is commonly used for DDR3L memory interfaces. The parallel connection increases current carrying capacity. This voltage is monitored by U34 (voltage monitor) through a resistor divider network (R298 10K and R301 10K) on net N23613650, ensuring proper voltage levels for system operation.1.8V power supply pins connected in parallel to 1P8V net.
Pins 49 and 50 are both connected to the 1P8V net, providing 1.8V power supply. The parallel connection increases current carrying capacity. This voltage is directly monitored by U34 (voltage monitor) on pin 3 (V2IN), indicating its importance to system operation. The 1P8V rail also powers U33 (NC7SZ125 buffer) on pin 5 and has decoupling capacitors C290 and C278 (both 0.1uF) for local filtering.1.8V power supply pins connected in parallel to 1P8V net.
Pins 49 and 50 are both connected to the 1P8V net, providing 1.8V power supply. The parallel connection increases current carrying capacity. This voltage is directly monitored by U34 (voltage monitor) on pin 3 (V2IN), indicating its importance to system operation. The 1P8V rail also powers U33 (NC7SZ125 buffer) on pin 5 and has decoupling capacitors C290 and C278 (both 0.1uF) for local filtering.Ground pins providing return path and reference.
Pins 51 and 52 are both connected to GND. These ground pins are positioned in the middle of the power supply pin group, providing a ground reference between different voltage rails to minimize noise coupling and improve power integrity. Multiple ground pins in the power section are essential for reducing ground bounce and maintaining clean power delivery.Ground pins providing return path and reference.
Pins 51 and 52 are both connected to GND. These ground pins are positioned in the middle of the power supply pin group, providing a ground reference between different voltage rails to minimize noise coupling and improve power integrity. Multiple ground pins in the power section are essential for reducing ground bounce and maintaining clean power delivery.Adjustable voltage supply pins connected in parallel to VDD_ADJ net.
Pins 53 and 54 are both connected to the VDD_ADJ net, providing an adjustable voltage supply. The parallel connection increases current carrying capacity. The adjustable nature suggests this rail may be configurable for different applications or components, providing flexibility in the system design.Adjustable voltage supply pins connected in parallel to VDD_ADJ net.
Pins 53 and 54 are both connected to the VDD_ADJ net, providing an adjustable voltage supply. The parallel connection increases current carrying capacity. The adjustable nature suggests this rail may be configurable for different applications or components, providing flexibility in the system design.GPIO voltage supply pins connected in parallel to VDD_GPIO net.
Pins 55 and 56 are both connected to the VDD_GPIO net, providing power for GPIO (General Purpose Input/Output) circuits. The parallel connection increases current carrying capacity, which is important for driving multiple GPIO pins. This is a common practice for I/O voltage supplies.GPIO voltage supply pins connected in parallel to VDD_GPIO net.
Pins 55 and 56 are both connected to the VDD_GPIO net, providing power for GPIO (General Purpose Input/Output) circuits. The parallel connection increases current carrying capacity, which is important for driving multiple GPIO pins. This is a common practice for I/O voltage supplies.2.5V power supply pins connected in parallel to 2P5V net.
Pins 57 and 58 are both connected to the 2P5V net, providing 2.5V power supply. This is an intermediate voltage level that may be used for certain I/O standards or analog circuits. The parallel connection provides adequate current capability.2.5V power supply pins connected in parallel to 2P5V net.
Pins 57 and 58 are both connected to the 2P5V net, providing 2.5V power supply. This is an intermediate voltage level that may be used for certain I/O standards or analog circuits. The parallel connection provides adequate current capability.3.3V power supply pins connected in parallel to 3P3V net.
Pins 59 and 60 are both connected to the 3P3V net, providing 3.3V power supply. This is one of the most common I/O voltage levels used throughout the system. The 3P3V rail powers multiple components including U33 (NC7SZ125 buffer) on pin 5 (VCC) and U34 (STM6904TWEDS6F voltage monitor) on pin 2 (VCC). It also has pull-up resistor R326 (10K) for PS_POR_L signal and multiple decoupling capacitors (C259, C291, C295, all 0.1uF). The parallel connection on the connector ensures adequate current delivery to external modules. The 3.3V supply is critical as it powers the voltage monitoring circuit that generates the system reset signal.3.3V power supply pins connected in parallel to 3P3V net.
Pins 59 and 60 are both connected to the 3P3V net, providing 3.3V power supply. This is one of the most common I/O voltage levels used throughout the system. The 3P3V rail powers multiple components including U33 (NC7SZ125 buffer) on pin 5 (VCC) and U34 (STM6904TWEDS6F voltage monitor) on pin 2 (VCC). It also has pull-up resistor R326 (10K) for PS_POR_L signal and multiple decoupling capacitors (C259, C291, C295, all 0.1uF). The parallel connection on the connector ensures adequate current delivery to external modules. The 3.3V supply is critical as it powers the voltage monitoring circuit that generates the system reset signal.SW2 - B3U-1000P ✅
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Switch contact A connected to GND, providing ground reference for the reset button.
Pin 1 (contact A) is connected to GND. According to the B3U-1000P datasheet (pages 2-3), this is an SPST-NO (Single Pole Single Throw - Normally Open) switch with two contact terminals. When the button is pressed, pins 1 and 2 are electrically connected. By connecting pin 1 to ground, pressing the button pulls the signal on pin 2 (PB_RESET_L) to ground, creating an active-low reset function. The datasheet (page 1) specifies a contact resistance of 100mΩ max and a rating of 1-50mA at 3-12VDC, which is appropriate for this digital signal application. This is a standard and correct configuration for a manual reset pushbutton.Switch contact B connected to PB_RESET_L reset signal, which is pulled low when the button is pressed.
Pin 2 (contact B) is connected to net PB_RESET_L. This signal connects to U34 pin 1 (MR - Manual Reset input) and to R95 pin 1. When the pushbutton SW2 is not pressed, the switch is open (SPST-NO configuration per datasheet page 1), and PB_RESET_L is held at its default state by the voltage monitor's circuitry. When the button is pressed, pin 2 is connected to pin 1 (GND), pulling PB_RESET_L low to activate the manual reset function. The switch has a durability rating of 200,000 operations minimum (datasheet page 1), which is suitable for a manual reset button application. This is the correct configuration for an active-low reset button.CR10 - LTST-C193KGKT-5A ✅
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📄 DRCY referred to this Datasheet for this component.
LED cathode correctly connected through current limiting resistor R30 (240Ω) to ground.
Pin 1 is the cathode of the LED, as confirmed by the LTST-C193KGKT-5A datasheet (page 2, which specifies cathode terminal with polarity marking on package). It connects to net N25352411, which connects to R30 pin 1. R30 pin 2 connects to GND, providing a current limiting path to ground. The polarity is correct - the cathode should connect to ground through a current limiting resistor. With R30 = 240Ω and assuming USER_LED is driven to 3.3V with a typical LED forward voltage of ~2V (datasheet page 4 specifies VF = 1.7 to 2.3V at IF=5mA), the current would be approximately (3.3V - 2V) / 240Ω ≈ 5.4mA. This is well within the safe operating range (datasheet page 3 specifies maximum DC Forward Current IF = 20mA) and matches the typical operating current of 5mA specified in the datasheet (page 4). The connection is correct.LED anode correctly connected to USER_LED signal from connector J13.
Pin 2 is the anode of the LED, as confirmed by the LTST-C193KGKT-5A datasheet (page 2, which specifies anode terminal with polarity marking on package). It connects to net USER_LED, which connects to J13 pin 28. The polarity is correct - the anode should receive the positive drive signal. When USER_LED is driven high (likely 3.3V based on the circuit context), current flows from the anode through the LED to the cathode, through current limiting resistor R30 to ground, illuminating the LED. The datasheet (page 4) specifies luminous intensity of 4.5 to 28 mcd at IF=5mA, and the circuit provides approximately 5.4mA as calculated, which is appropriate for visible indication. The green LED with peak emission wavelength of 574nm (datasheet page 4) serves as a user indicator. The connection is correct.R30 - RES0402_240 ✅
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240Ω current limiting resistor for LED CR10. Pin 1 connects to LED cathode, pin 2 connects to GND.
R30 is a 240Ω resistor (0402 package) serving as a current limiting resistor for LED CR10. Pin 1 connects to net N25352411 (LED cathode), and pin 2 connects to GND. The resistor value is appropriately sized for the LED application. With USER_LED driven to approximately 3.3V and a typical green LED forward voltage of ~2V (CR10 datasheet page 4 specifies 1.7-2.3V at IF=5mA), the current through the LED would be approximately (3.3V - 2V) / 240Ω ≈ 5.4mA. This is well within the LED's maximum DC forward current of 20mA (CR10 datasheet page 3) and close to the typical operating current of 5mA specified in the LED datasheet (page 4). The resistor value provides adequate current limiting while ensuring sufficient brightness for a user indicator LED. This is a correct and standard configuration for LED current limiting.240Ω current limiting resistor for LED CR10. Pin 1 connects to LED cathode, pin 2 connects to GND.
R30 is a 240Ω resistor (0402 package) serving as a current limiting resistor for LED CR10. Pin 1 connects to net N25352411 (LED cathode), and pin 2 connects to GND. The resistor value is appropriately sized for the LED application. With USER_LED driven to approximately 3.3V and a typical green LED forward voltage of ~2V (CR10 datasheet page 4 specifies 1.7-2.3V at IF=5mA), the current through the LED would be approximately (3.3V - 2V) / 240Ω ≈ 5.4mA. This is well within the LED's maximum DC forward current of 20mA (CR10 datasheet page 3) and close to the typical operating current of 5mA specified in the LED datasheet (page 4). The resistor value provides adequate current limiting while ensuring sufficient brightness for a user indicator LED. This is a correct and standard configuration for LED current limiting.📤 Upload Missing Datasheets
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Component
R242, pins1, 2: 10K pull-up resistor on RXI_NO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.R242 connects pin 1 to 1P8V and pin 2 to RXI_NO_FRAME_N, functioning as a pull-up resistor on the negative signal of the RXI_NO_FRAME differential pair. This signal connects to U23 pin B7 (EPIPHANY E16G301 microprocessor). R243 provides the complementary pull-down on RXI_NO_FRAME_P (U23 pin B8) to GND. This configuration creates a default idle state where the negative signal is higher than the positive signal (N > P), which is inverted from the standard LVDS convention where P > N. The schematic annotation indicates these are '100 Ohm Differential LVDS Signals', and standard LVDS practice is to have P > N in the idle state. This inverted polarity is inconsistent with the TXI_NO_RD_WAIT pair (R240/R241) which uses standard polarity. However, this same inverted polarity pattern is consistently applied to all three frame signal pairs (RXI_NO_FRAME, TXO_SO_FRAME, and RXI_SO_FRAME), which suggests it might be intentional based on the processor's requirements for frame signals versus wait signals. While LVDS receivers can typically work with either polarity, the inconsistency between signal types is unusual. The 10K value and common-mode voltage (0.9V) are appropriate for LVDS biasing. Without the EPIPHANY E16G301 processor datasheet, it cannot be definitively determined if this inverted polarity is required by the processor or represents a design error. Recommendation: Verify the required idle state polarities for all LVDS signal pairs against the processor datasheet. If standard polarity is required for frame signals, swap the connections of R242 and R243 so that R242 connects RXI_NO_FRAME_P to 1P8V and R243 connects RXI_NO_FRAME_N to GND.
All affected pins
Component
R242, pins `1, 2`: 10K pull-up resistor on RXI_NO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.R242 connects pin 1 to 1P8V and pin 2 to RXI_NO_FRAME_N, functioning as a pull-up resistor on the negative signal of the RXI_NO_FRAME differential pair. This signal connects to U23 pin B7 (EPIPHANY E16G301 microprocessor). R243 provides the complementary pull-down on RXI_NO_FRAME_P (U23 pin B8) to GND. This configuration creates a default idle state where the negative signal is higher than the positive signal (N > P), which is inverted from the standard LVDS convention where P > N. The schematic annotation indicates these are '100 Ohm Differential LVDS Signals', and standard LVDS practice is to have P > N in the idle state. This inverted polarity is inconsistent with the TXI_NO_RD_WAIT pair (R240/R241) which uses standard polarity. However, this same inverted polarity pattern is consistently applied to all three frame signal pairs (RXI_NO_FRAME, TXO_SO_FRAME, and RXI_SO_FRAME), which suggests it might be intentional based on the processor's requirements for frame signals versus wait signals. While LVDS receivers can typically work with either polarity, the inconsistency between signal types is unusual. The 10K value and common-mode voltage (0.9V) are appropriate for LVDS biasing. Without the EPIPHANY E16G301 processor datasheet, it cannot be definitively determined if this inverted polarity is required by the processor or represents a design error. Recommendation: Verify the required idle state polarities for all LVDS signal pairs against the processor datasheet. If standard polarity is required for frame signals, swap the connections of R242 and R243 so that R242 connects RXI_NO_FRAME_P to 1P8V and R243 connects RXI_NO_FRAME_N to GND.
Component
R243, pins `1, 2`: 10K pull-down resistor on RXI_NO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.R243 connects pin 1 to GND and pin 2 to RXI_NO_FRAME_P, functioning as a pull-down resistor on the positive signal of the RXI_NO_FRAME differential pair. This signal connects to U23 pin B8 (EPIPHANY E16G301 microprocessor). R242 provides the complementary pull-up on RXI_NO_FRAME_N (U23 pin B7) to 1P8V. This configuration creates a default idle state where the negative signal is higher than the positive signal (N > P), which is inverted from the standard LVDS convention where P > N. The schematic annotation indicates these are '100 Ohm Differential LVDS Signals', and standard LVDS practice is to have P > N in the idle state. This inverted polarity is inconsistent with the TXI_NO_RD_WAIT pair (R240/R241) which uses standard polarity. However, this same inverted polarity pattern is consistently applied to all three frame signal pairs (RXI_NO_FRAME, TXO_SO_FRAME, and RXI_SO_FRAME), which suggests it might be intentional based on the processor's requirements. The 10K value and common-mode voltage (0.9V) are appropriate for LVDS biasing. Without the EPIPHANY E16G301 processor datasheet, it cannot be definitively determined if this inverted polarity is required by the processor or represents a design error. Recommendation: Verify the required idle state polarities for all LVDS signal pairs against the processor datasheet. If standard polarity is required, swap the connections of R242 and R243.
Component
R244, pins `1, 2`: 10K pull-up resistor on TXO_SO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.R244 connects pin 1 to TXO_SO_FRAME_N and pin 2 to 1P8V, functioning as a pull-up resistor on the negative signal of the TXO_SO_FRAME differential pair. This signal connects to U23 pin R10 (EPIPHANY E16G301 microprocessor). R245 provides the complementary pull-down on TXO_SO_FRAME_P (U23 pin R9) to GND. This configuration creates a default idle state where the negative signal is higher than the positive signal (N > P), which is inverted from the standard LVDS convention where P > N. The schematic annotation indicates these are '100 Ohm Differential LVDS Signals', and standard LVDS practice is to have P > N in the idle state. This inverted polarity is inconsistent with the TXI_NO_RD_WAIT pair (R240/R241) which uses standard polarity. However, this same inverted polarity pattern is consistently applied to all three frame signal pairs (RXI_NO_FRAME, TXO_SO_FRAME, and RXI_SO_FRAME), which suggests it might be intentional based on the processor's requirements. TXO_SO_FRAME is an output signal from U23, but this should not affect the polarity convention. The 10K value and common-mode voltage (0.9V) are appropriate for LVDS biasing. Without the EPIPHANY E16G301 processor datasheet, it cannot be definitively determined if this inverted polarity is required by the processor or represents a design error. Recommendation: Verify the required idle state polarities for all LVDS signal pairs against the processor datasheet. If standard polarity is required, swap the connections of R244 and R245 so that R244 connects TXO_SO_FRAME_P to 1P8V and R245 connects TXO_SO_FRAME_N to GND.
Component
R245, pins `1, 2`: 10K pull-down resistor on TXO_SO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.R245 connects pin 1 to TXO_SO_FRAME_P and pin 2 to GND, functioning as a pull-down resistor on the positive signal of the TXO_SO_FRAME differential pair. This signal connects to U23 pin R9 (EPIPHANY E16G301 microprocessor). R244 provides the complementary pull-up on TXO_SO_FRAME_N (U23 pin R10) to 1P8V. This configuration creates a default idle state where the negative signal is higher than the positive signal (N > P), which is inverted from the standard LVDS convention where P > N. The schematic annotation indicates these are '100 Ohm Differential LVDS Signals', and standard LVDS practice is to have P > N in the idle state. This inverted polarity is inconsistent with the TXI_NO_RD_WAIT pair (R240/R241) which uses standard polarity. However, this same inverted polarity pattern is consistently applied to all three frame signal pairs (RXI_NO_FRAME, TXO_SO_FRAME, and RXI_SO_FRAME), which suggests it might be intentional based on the processor's requirements. The 10K value and common-mode voltage (0.9V) are appropriate for LVDS biasing. Without the EPIPHANY E16G301 processor datasheet, it cannot be definitively determined if this inverted polarity is required by the processor or represents a design error. Recommendation: Verify the required idle state polarities for all LVDS signal pairs against the processor datasheet. If standard polarity is required, swap the connections of R244 and R245.
Component
R246, pins `1, 2`: 10K pull-down resistor on RXI_SO_FRAME_P signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.R246 connects pin 1 to GND and pin 2 to RXI_SO_FRAME_P, functioning as a pull-down resistor on the positive signal of the RXI_SO_FRAME differential pair. This signal connects to U23 pin U7 (EPIPHANY E16G301 microprocessor). R247 provides the complementary pull-up on RXI_SO_FRAME_N (U23 pin U8) to 1P8V. This configuration creates a default idle state where the negative signal is higher than the positive signal (N > P), which is inverted from the standard LVDS convention where P > N. The schematic annotation indicates these are '100 Ohm Differential LVDS Signals', and standard LVDS practice is to have P > N in the idle state. This inverted polarity is inconsistent with the TXI_NO_RD_WAIT pair (R240/R241) which uses standard polarity. However, this same inverted polarity pattern is consistently applied to all three frame signal pairs (RXI_NO_FRAME, TXO_SO_FRAME, and RXI_SO_FRAME), which suggests it might be intentional based on the processor's requirements. The 10K value and common-mode voltage (0.9V) are appropriate for LVDS biasing. Without the EPIPHANY E16G301 processor datasheet, it cannot be definitively determined if this inverted polarity is required by the processor or represents a design error. Recommendation: Verify the required idle state polarities for all LVDS signal pairs against the processor datasheet. If standard polarity is required, swap the connections of R246 and R247 so that R246 connects RXI_SO_FRAME_N to GND and R247 connects RXI_SO_FRAME_P to 1P8V.
Component
R247, pins `1, 2`: 10K pull-up resistor on RXI_SO_FRAME_N signal. Configuration has inverted LVDS polarity (N > P) compared to standard convention and inconsistent with TXI_NO_RD_WAIT pair.R247 connects pin 1 to 1P8V and pin 2 to RXI_SO_FRAME_N, functioning as a pull-up resistor on the negative signal of the RXI_SO_FRAME differential pair. This signal connects to U23 pin U8 (EPIPHANY E16G301 microprocessor). R246 provides the complementary pull-down on RXI_SO_FRAME_P (U23 pin U7) to GND. This configuration creates a default idle state where the negative signal is higher than the positive signal (N > P), which is inverted from the standard LVDS convention where P > N. The schematic annotation indicates these are '100 Ohm Differential LVDS Signals', and standard LVDS practice is to have P > N in the idle state. This inverted polarity is inconsistent with the TXI_NO_RD_WAIT pair (R240/R241) which uses standard polarity. However, this same inverted polarity pattern is consistently applied to all three frame signal pairs (RXI_NO_FRAME, TXO_SO_FRAME, and RXI_SO_FRAME), which suggests it might be intentional based on the processor's requirements. The 10K value and common-mode voltage (0.9V) are appropriate for LVDS biasing. Without the EPIPHANY E16G301 processor datasheet, it cannot be definitively determined if this inverted polarity is required by the processor or represents a design error. Recommendation: Verify the required idle state polarities for all LVDS signal pairs against the processor datasheet. If standard polarity is required, swap the connections of R246 and R247.
Datasheets: 📄 R242
Component
U26, pins33, 34: DDCSCL and DDCSDA pins have pull-up resistors that significantly exceed the datasheet-required range, which may cause DDC communication issues and HDMI compliance problems.Pins 33 (DDCSCL) and 34 (DDCSDA) are the DDC I2C interface to the HDMI sink according to the datasheet (page 16-18). These pins serve as master to the DDC bus and are tolerant of 5V CMOS logic levels. The datasheet (page 43) explicitly states: 'Pull-up resistor of 1.5kΩ to 2kΩ (+/-10%) to HDMI +5V required for each signal'. The word 'required' is used, not 'recommended', indicating this is a mandatory specification. The specified range with tolerance is 1.35kΩ-2.2kΩ. The schematic shows R19 (4.75K) on DDC_SCL and R21 (4.75K) on DDC_SDA, both pulling up to HDMI_5V. These 4.75K values are significantly higher than the specified range—more than 2× the maximum allowed value. Higher pull-up values can cause: (1) slower rise times on the DDC bus that may violate I2C timing specifications, (2) potential communication failures with some HDMI sinks, (3) non-compliance with HDMI specification requirements. The DDC interface is critical for EDID reading and HDCP negotiation. While the circuit may function in some cases with more tolerant sinks, it does not meet the datasheet requirement and could cause interoperability issues with various HDMI displays. The pull-up resistors should be changed to values within the 1.5k-2.2k range (e.g., 1.8k or 2k ohms) to ensure proper DDC operation and HDMI compliance.
Component
U37, pins2, 3, 8, 9: I2C level shifter pins are incorrectly connected - the TPD12S016's I2C interface should bridge the HDMI transmitter's DDC interface to the HDMI connector, not the control I2C interface.The TPD12S016's I2C level shifters are fundamentally misconnected. According to the datasheet (page 4), SCL_A/SDA_A (pins 2/3) are 'HDMI controller side SCL/SDA signal pins referenced to VCCA. Connect to HDMI controller' and SCL_B/SDA_B (pins 8/9) are 'HDMI connector side SCL/SDA signal pins referenced to 5V_OUT supply. Connect to HDMI connector SCL/SDA pins.' The typical applications (pages 18-20) clearly show these pins should provide ESD protection and level shifting for the DDC (Display Data Channel) interface between the HDMI transmitter and connector. However, the current design has: (1) SCL_A/SDA_A (pins 2/3) connected to PS_I2C_SCL/SDA - the processor's control interface for configuring the ADV7513, (2) SCL_B/SDA_B (pins 8/9) connected to I2C_SCL/SDA which connects to U26 pins 35/36 (SCL/SDA) - the ADV7513's control interface, and (3) The actual DDC lines (DDC_SCL/DDC_SDA) connecting directly from U26 pins 33/34 (DDCSCL/DDCSDA) to J10 pins 17/18 (connector DDC), completely bypassing the TPD12S016. This means the DDC lines lack the IEC 61000-4-2 Level 4 ESD protection (±8kV contact discharge per datasheet page 1) that the TPD12S016 is designed to provide, and the control I2C interface is unnecessarily routed through the ESD protection device. The correct connections should be: U37 pins 2/3 (SCL_A/SDA_A) to U26 pins 33/34 (DDCSCL/DDCSDA), U37 pins 8/9 (SCL_B/SDA_B) to J10 pins 17/18 (DDC_SCL/DDC_SDA), and PS_I2C_SCL/SDA should connect directly to U26 pins 35/36 (SCL/SDA) without going through U37. The datasheet specifies that SCL_A/SDA_A have internal 10kΩ pullups to VCCA (page 7) and SCL_B/SDA_B have internal 1.75kΩ pullups to the 5V rail (page 7), with the ability to drive up to 750pF capacitive loads exceeding HDMI 1.4 specifications.
Component
D1, pins1, 2: Diode is incorrectly placed in series with pull-up resistor R225, creating an inappropriate topology that reduces the pull-up voltage and serves no clear purpose for the CEC application. Both D1 and R225 are marked DNI.D1 is configured with pin 2 (ANODE) connected to net N22414199, which connects to 3P3V through R225 (27.4K), and pin 1 (CATHODE) connected to HDMI_CEC. According to the datasheet (page 1), pin 1 is correctly identified as CATHODE and pin 2 as ANODE. This creates a circuit path: 3P3V → R225 → D1 (anode to cathode) → HDMI_CEC. While the individual pin connections match the schematic as drawn, the circuit topology is inappropriate for the application. The BAS16XV2T1G has a forward voltage drop of 0.715-1.25V depending on current (datasheet page 2). In this configuration, when HDMI_CEC is pulled low, the diode will conduct and pull the line up to approximately 2.3-2.6V (3.3V minus Vf) rather than the full 3.3V. This voltage reduction is detrimental to proper CEC operation, which typically requires pull-up to the full supply voltage for reliable logic high levels. Standard CEC circuits use direct resistor pull-ups without series diodes. The series diode in this configuration provides no clear benefit: it's not providing ESD protection (wrong orientation and location for that purpose), not providing meaningful reverse polarity protection (CEC is a bidirectional open-drain signal), and not serving any switching function. The HDMI_CEC net connects to U26 pin 30 (ADV7513 HDMI transmitter CEC pin) and U37 pin 1 (TPD12S016 level shifter CEC_A pin). Both D1 and R225 are marked 'DNI' (Do Not Install), which suggests the designer recognized this circuit was problematic or unnecessary during design review. Recommendation: Remove D1 entirely and connect R225 directly between 3P3V and HDMI_CEC for a standard pull-up configuration. Alternatively, if pull-up is provided elsewhere in the circuit (such as within U37 or at the connector), both components can remain unpopulated as indicated by the DNI status.
Component
U29, pin11: FB2 feedback pin has incorrect voltage divider values - R282 should be approximately 70K instead of 10K, resulting in 0.94V output instead of the intended 1.8V.Pin 11 (FB2) is the feedback pin for DCD2 (datasheet page 3). It is connected to net N25830704 as part of a voltage divider network for DCD2 output regulation. The datasheet specifies a feedback regulation voltage of 0.8V typical (page 5: 0.785V min, 0.8V typ, 0.815V max). The voltage divider consists of R282 (10K) from output N25830712 to FB2 (N25830704), and R281 (56.2K) from FB2 to GND. C244 (0.047µF) provides compensation. Using the voltage divider equation: VOUT = VFB × (1 + R282/R281) = 0.8V × (1 + 10K/56.2K) = 0.8V × 1.178 = 0.942V. However, the schematic text indicates '1.8V @ 1.5A max' and R287 (0Ω) connects the output to the 1P8V rail, clearly indicating the intended output is 1.8V. For a 1.8V output with 0.8V feedback: 1.8V = 0.8V × (1 + R282/R281), solving gives R282 = 1.25 × R281 = 1.25 × 56.2K = 70.25K. The current value of R282 = 10K is incorrect and will result in an output voltage of approximately 0.94V instead of 1.8V, a critical 48% error. Recommendation: Replace R282 with a 70K or 71.5K resistor (standard E96 value) to achieve the correct 1.8V output voltage.
@allspice-carah take a look
Component
U29, pin15: GNDDCD1 ground pin is not connected to any net - this is a critical error that will prevent DCD1 from functioning.Pin 15 (GNDDCD1) has no net connection in the schematic XML (no element present in the pin definition). The datasheet (page 3) specifies this is the power ground for DCD1, which is essential for the buck converter operation. Without a ground connection, DCD1 cannot function - there is no return path for the switching currents, and the internal circuits cannot operate properly. The datasheet (page 8) emphasizes proper grounding for good EMI performance and states that 'Ground of input and output capacitors should be connected as close as possible as well. Solid ground plane helpful for good EMI performance.' This is a critical error that must be corrected immediately. Recommendation: Connect pin 15 (GNDDCD1) to the system GND net, preferably with a low-impedance connection close to the IC to minimize ground bounce and ensure proper operation of DCD1.
Component
CR8, pins1, 2: LED anode and cathode connections are reversed. Pin 1 (Cathode) is connected to the positive side through R288 from SYS_5P0V, and Pin 2 (Anode) is connected to GND. This reverse bias prevents the LED from lighting.CR8 is a green LED (LTST-C193KGKT-5A) intended to indicate power good status, as noted in the schematic annotations: 'Power Good = LED ON' and 'Power Bad = LED OFF', with an additional note that 'CR8 could be removed for production'. Pin 1 is labeled 'C' (Cathode) in the component attributes and connects to net N23098459. Pin 2 is labeled 'A' (Anode) and connects to GND. Net N23098459 connects to U30 pin 10 (DCDPG - DC/DC Power Good signal) and to R288 pin 1 (620Ω current-limiting resistor, RES0402_620). R288 pin 2 connects to SYS_5P0V. This creates a circuit path: SYS_5P0V → R288 (620Ω) → N23098459 → LED Cathode (pin 1), with LED Anode (pin 2) → GND. For proper LED operation, current must flow from anode to cathode, requiring the anode to be at a higher potential than the cathode. The datasheet (page 4) specifies forward voltage VF of 1.7V to 2.3V at IF=5mA, and the datasheet (page 3) specifies maximum DC forward current of 20mA and maximum reverse voltage VR=5V. In the current configuration, the cathode is at approximately 5V (when DCDPG is HIGH indicating power good) and the anode is at 0V (GND), which places the LED in reverse bias. While the LED won't be damaged (reverse voltage is within the 5V maximum), it will not conduct current or emit light. With R288=620Ω and SYS_5P0V=5V, if properly connected, the forward current would be approximately (5V-2V)/620Ω ≈ 4.8mA, which is appropriate for this LED rated at 5mA nominal current. The correct connection should be: Pin 2 (Anode) to N23098459 (positive side through R288), and Pin 1 (Cathode) to GND (lower potential). Recommendation: Swap the net connections so that pin 1 (Cathode) connects to GND and pin 2 (Anode) connects to N23098459, or verify and correct the pin labeling in the schematic symbol if it doesn't match the physical device.
All affected pins
Component
U30, pin `10`: DCDPG is connected to an LED (CR8) through a pullup resistor, but the LED polarity is reversed, causing it to function opposite to the schematic notes which state 'Power Good = LED ON'.Pin 10 (DCDPG) is connected to net N23098459, which connects to CR8 pin 1 (LED cathode) and R288 (620 ohm pullup to SYS_5P0V). CR8 pin 2 (LED anode) is connected to GND. According to the ISL9305H datasheet (page 2), 'The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1 and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter voltages are within the power good range. The pin will be pulled low if either DCD is outside their range.' The datasheet (page 3) confirms that an external pull-up resistor is required, which is provided by R288. However, the LED connection is incorrect. When DCDPG is HIGH (power good condition), the LED cathode is at ~5V and the anode is at GND (0V), which reverse biases the LED, turning it OFF. When DCDPG is LOW (power bad condition), both the cathode and anode are at ~0V, so no current flows and the LED remains OFF. For an LED to conduct in the forward direction, current must flow from anode to cathode, requiring the anode to be at a higher potential than the cathode. The schematic notes state 'Power Good = LED ON' and 'Power Bad = LED OFF', but the current configuration will result in the LED being always OFF or reverse biased. For correct operation, CR8 pins should be swapped: the anode (pin 2) should connect to N23098459 and the cathode (pin 1) should connect to GND. This would allow current to flow through the LED when DCDPG is HIGH (power good), turning the LED ON, and no current when DCDPG is LOW (power bad), turning the LED OFF.
Component
CR8, pins `1, 2`: LED anode and cathode connections are reversed. Pin 1 (Cathode) is connected to the positive side through R288 from SYS_5P0V, and Pin 2 (Anode) is connected to GND. This reverse bias prevents the LED from lighting.CR8 is a green LED (LTST-C193KGKT-5A) intended to indicate power good status, as noted in the schematic annotations: 'Power Good = LED ON' and 'Power Bad = LED OFF', with an additional note that 'CR8 could be removed for production'. Pin 1 is labeled 'C' (Cathode) in the component attributes and connects to net N23098459. Pin 2 is labeled 'A' (Anode) and connects to GND. Net N23098459 connects to U30 pin 10 (DCDPG - DC/DC Power Good signal) and to R288 pin 1 (620Ω current-limiting resistor, RES0402_620). R288 pin 2 connects to SYS_5P0V. This creates a circuit path: SYS_5P0V → R288 (620Ω) → N23098459 → LED Cathode (pin 1), with LED Anode (pin 2) → GND. For proper LED operation, current must flow from anode to cathode, requiring the anode to be at a higher potential than the cathode. The datasheet (page 4) specifies forward voltage VF of 1.7V to 2.3V at IF=5mA, and the datasheet (page 3) specifies maximum DC forward current of 20mA and maximum reverse voltage VR=5V. In the current configuration, the cathode is at approximately 5V (when DCDPG is HIGH indicating power good) and the anode is at 0V (GND), which places the LED in reverse bias. While the LED won't be damaged (reverse voltage is within the 5V maximum), it will not conduct current or emit light. With R288=620Ω and SYS_5P0V=5V, if properly connected, the forward current would be approximately (5V-2V)/620Ω ≈ 4.8mA, which is appropriate for this LED rated at 5mA nominal current. The correct connection should be: Pin 2 (Anode) to N23098459 (positive side through R288), and Pin 1 (Cathode) to GND (lower potential). Recommendation: Swap the net connections so that pin 1 (Cathode) connects to GND and pin 2 (Anode) connects to N23098459, or verify and correct the pin labeling in the schematic symbol if it doesn't match the physical device.
Datasheets: 📄 CR8 📄 U30
Component
U36, pin1: OE (Output Enable) pin is tied to 5P0V (HIGH), permanently disabling the buffer output. This is a design error that renders the component non-functional.Pin 1 is the OE (Output Enable) input, which is active-low according to the datasheet (page 2). The datasheet function table clearly states: 'When OE is LOW, output Y follows input A. When OE is HIGH, output Y is in high-impedance state (Z) regardless of input A state.' This pin is connected to the 5P0V power rail, keeping OE permanently HIGH. With OE held HIGH, the output Y (pin 4) remains in high-impedance state regardless of the input A state, completely disabling the buffer's functionality. The input A (pin 2) is pulled to GND through R327 (1K), and the output Y (pin 4) connects to TURBO_MODE which is pulled up to VDD_GPIO through R328 (1K). In the current configuration, TURBO_MODE would simply be pulled HIGH by R328 since the buffer output is always in high-Z state. For proper buffer operation, OE should be connected to GND (to permanently enable the buffer) or to a control signal that can be driven LOW when buffer operation is required. There is no indication in the schematic of any design intent to have a permanently disabled buffer. The presence of DNI capacitor C288 suggests this may be an optional circuit, but even so, the buffer should be functional when installed. Recommendation: Connect pin 1 to GND to enable the buffer, or to an appropriate control signal if conditional operation is desired.
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