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Bug Fixes and component re-positioning #8

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allspice-hermes commented 2024-07-25 13:40:10 +00:00
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Resolved Issues

Closes #4
Closes #5
...

Description

This DR fixes some of the bugs reported and also updates the position of some components within the board for a better distribution and placement for manufacture. After approval, we should release a new stable version for the board.

@AllSpiceUser @RevaReviewa could you guys take a look at this and confirm the board release afterwards?
...

Because the revision of KiCad increased, the file format changed how schematic symbol attributes are stored. All schematics have changed and have attribute changes.

Design Review Checklist

Process

  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained

System

  • Power
    • Sufficient power supplied from upstream source
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • I/Os are specified
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review

Components

  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power

Schematics

  • Document
    • Dot on each connection
    • No four-point connections
    • Title block completed for each sheet
    • All components have reference designators and values
    • Multi-part components don't have unplaced symbols
    • Page title present and consistent on all pages if not in title block
    • Symbols identify open collector/drain pins and internal pulled up/down pins
    • Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
    • Components follow preferred reference designator pattern

PCB

  • Manufacturing
    • PCB manufacturing requirements noted on fab layer
      • Plating specified
        • Plating material
        • Plating thickness
      • Layer stack-up specified
      • Minimum trace/space specified
      • Minimum hole size specified
      • PCB color specified
      • Silkscreen color specified
      • Controlled impedance specified
      • Blind or buried vias specified
      • Panelization specified
        • External routing specified (ex. v-groove vs route)
      • Drill table generated
      • All specifications exceed manufacturing tolerance
## Resolved Issues Closes #4 Closes #5 ... ## Description This DR fixes some of the bugs reported and also updates the position of some components within the board for a better distribution and placement for manufacture. After approval, we should release a new stable version for the board. @AllSpiceUser @RevaReviewa could you guys take a look at this and confirm the board release afterwards? ... Because the revision of KiCad increased, the file format changed how schematic symbol attributes are stored. All schematics have changed and have attribute changes. ## Design Review Checklist ### Process - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained ### System - [ ] Power - [ ] Sufficient power supplied from upstream source - [ ] Supply rated for necessary country specifications - [ ] Estimated total worst-case power supply draw - [ ] Connectors - [ ] I/Os are specified - [ ] Sufficient Current and Voltage rating - [ ] Mating connectors have matching pinout - [ ] Same contact material specified for mating connectors - [ ] Testing - [ ] Test procedure written - [ ] Environmental - [ ] Specified min/max operating temperature - [ ] Specified min/max storage temperature - [ ] Specified min/max humidity - [ ] ROHS compliance requirement review ### Components - [ ] Unpopulated components are denoted DNI - [ ] Components meet environmental specifications - [ ] All components have quantity, reference designator and description - [ ] Suggested and alternate manufacturers listed - [ ] Price and stock checked for each component - [ ] Component derating - [ ] Voltage - [ ] Current - [ ] Power at worst-case operating temperature - [ ] Temperature at worst-case power ### Schematics - [ ] Document - [ ] Dot on each connection - [ ] No four-point connections - [ ] Title block completed for each sheet - [ ] All components have reference designators and values - [ ] Multi-part components don't have unplaced symbols - [ ] Page title present and consistent on all pages if not in title block - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins - [ ] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [ ] Components follow preferred reference designator pattern <!-- Link to spec --> ### PCB - [ ] Manufacturing - [ ] PCB manufacturing requirements noted on `fab` layer - [ ] Plating specified - [ ] Plating material - [ ] Plating thickness - [ ] Layer stack-up specified - [ ] Minimum trace/space specified - [ ] Minimum hole size specified - [ ] PCB color specified - [ ] Silkscreen color specified - [ ] Controlled impedance specified - [ ] Blind or buried vias specified - [ ] Panelization specified - [ ] External routing specified (ex. v-groove vs route) - [ ] Drill table generated - [ ] All specifications exceed manufacturing tolerance <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
Screenshot 2024-10-16 at 9.40.33 PM.png
50 KiB
Screenshot 2024-10-16 at 9.40.33 PM.png
allspice-hermes added the
priority/4 - high
layout
 labels 2024-07-25 13:40:10 +00:00
AllSpiceAlice was assigned by allspice-hermes 2024-07-25 13:40:10 +00:00
RevaReviewa was assigned by allspice-hermes 2024-07-25 13:40:10 +00:00
allspice-hermes added 1 commit 2024-07-25 13:40:10 +00:00
brendan reviewed 2024-09-18 17:29:31 +00:00
SingleBoardComputer.kicad_pcb Outdated
brendan commented 2024-09-18 17:29:31 +00:00
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@gautam Please review

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" layers="1" diff-visibility="full" variant="default" view-coords="75.0,29.9,86.1,45.4" aspect-ratio="0.994" } @gautam Please review
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brendan marked this conversation as resolved
allspice-hermes requested review from AllSpiceAlice 2024-10-01 18:30:39 +00:00
allspice-hermes removed review request for AllSpiceAlice 2024-10-01 18:30:47 +00:00
allspice-hermes requested review from AngelaGlobalPCBA 2024-10-01 18:30:47 +00:00
allspice-hermes requested review from RevaReviewa 2024-10-01 18:31:03 +00:00
allspice-hermes removed review request for RevaReviewa 2024-10-01 18:42:38 +00:00
AllSpiceAlice reviewed 2024-10-17 01:44:28 +00:00
SingleBoardComputer.kicad_pcb Outdated
AllSpiceAlice commented 2024-10-17 01:44:28 +00:00
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Please check the vias underneath U100 @daniel

Please check the vias underneath U100 @daniel !thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="42.8,42.4,57.1,56.2" aspect-ratio="0.994" }
MikaChanical reviewed 2024-10-17 01:50:41 +00:00
SingleBoardComputer.kicad_pcb Outdated
MikaChanical commented 2024-10-17 01:50:41 +00:00
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@AllSpiceAlice , can you update the silkscreen on this footprint. It's unclear where to place it.

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="31.7,21.8,82.2,28.9" aspect-ratio="0.994" } @AllSpiceAlice , can you update the silkscreen on this footprint. It's unclear where to place it.
AllSpiceAlice commented 2024-10-17 03:15:45 +00:00
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@MikaChanical , how does J3 look? If you like it, I'll fix the other connector.

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...1ad1cc6d8062201c0f3e9d2e8271c5c6b78b37fe" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="32.9,22.3,61.2,27.1" aspect-ratio="0.994" } @MikaChanical , how does J3 look? If you like it, I'll fix the other connector.
MikaChanical commented 2024-10-17 03:18:20 +00:00
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@AllSpiceAlice, would you make both the Pin-1 triangle and circle markers bigger. There are models with polarized retention features, so we need this to be big enough for fab.

@AllSpiceAlice, would you make both the Pin-1 triangle and circle markers bigger. There are models with polarized retention features, so we need this to be big enough for fab.
AllSpiceAlice commented 2024-10-17 03:23:15 +00:00
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@MikaChanical , how do these look? I removed the triangle to cut down on visual clutter.

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...a3c822e27c2b431d95cff1fd8b9d166fa3007c5e" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="28.8,21.6,85.1,30.1" aspect-ratio="0.994" } @MikaChanical , how do these look? I removed the triangle to cut down on visual clutter.
AllSpiceAlice added 1 commit 2024-10-17 02:10:19 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:12:49 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:21:39 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:34:58 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:39:14 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:48:03 +00:00
PavelInPurchasing reviewed 2024-10-17 02:58:03 +00:00
Bootloader-ATMEGA16U.kicad_sch
PavelInPurchasing commented 2024-10-17 02:58:03 +00:00
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@daniel , can you remove this connector? It's EOL, and the team agreed they didn't need it anyways.

!thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...5fd194e5655270f77442cdb95cbbe5606af50380" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="65.4,27.2,73.8,39.0" aspect-ratio="1.405" } @daniel , can you remove this connector? It's EOL, and the team agreed they didn't need it anyways.
daniel commented 2024-10-17 03:01:10 +00:00
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@PavelInPurchasing, it's been removed

@PavelInPurchasing, it's been removed !thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...4d8a762fe08925f5f8fa254d91605e36e96f5fe3" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="48.8,29.9,67.2,39.4" aspect-ratio="1.405" }
RevaReviewa reviewed 2024-10-17 03:05:34 +00:00
Bootloader-ATMEGA16U.kicad_sch
RevaReviewa commented 2024-10-17 03:05:34 +00:00
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@AllSpiceAlice, can you add another reset switch to GND for RESET2?

!thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...5fd194e5655270f77442cdb95cbbe5606af50380" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="31.7,23.7,43.2,29.5" aspect-ratio="1.405" } @AllSpiceAlice, can you add another reset switch to GND for RESET2?
AllSpiceAlice commented 2024-10-17 03:07:21 +00:00
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@RevaReviewa , here you go! That should help the manufacturing team figure out the programming sequence without worrying about bricking the microcontrollers or the bootloader.

!thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...4d8a762fe08925f5f8fa254d91605e36e96f5fe3" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="15.7,14.2,43.2,34.8" aspect-ratio="1.405" } @RevaReviewa , here you go! That should help the manufacturing team figure out the programming sequence without worrying about bricking the microcontrollers or the bootloader.
AllSpiceAlice added 1 commit 2024-10-17 03:11:30 +00:00
AllSpiceAlice added 1 commit 2024-10-17 03:14:27 +00:00
AllSpiceAlice added 1 commit 2024-10-17 03:22:26 +00:00
RevaReviewa reviewed 2024-10-17 03:28:06 +00:00
VREG_5V_3.3V.kicad_sch
RevaReviewa commented 2024-10-17 03:28:06 +00:00
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@AllSpiceAlice, can we disconnect SCK from this buffer? We're getting interference.

!thumbnail[](VREG_5V_3.3V.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" doc-id="3c86f159e194b13ca2d9" diff-visibility="full" variant="default" view-coords="5.4,45.6,33.0,67.0" aspect-ratio="1.405" } @AllSpiceAlice, can we disconnect SCK from this buffer? We're getting interference.
AllSpiceAlice commented 2024-10-17 03:29:08 +00:00
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@RevaReviewa , Removed

!thumbnail[](VREG_5V_3.3V.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...a3c822e27c2b431d95cff1fd8b9d166fa3007c5e" pr="8" doc-id="3c86f159e194b13ca2d9" diff-visibility="full" variant="default" view-coords="5.2,43.3,34.5,65.2" aspect-ratio="1.405" } @RevaReviewa , Removed
RevaReviewa commented 2024-10-17 03:30:15 +00:00
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@AllSpiceAlice did you park the comparator? You need to check the datasheet to see if you need to pull up/down the inputs/outputs when not in use?

@AllSpiceAlice did you park the comparator? You need to check the datasheet to see if you need to pull up/down the inputs/outputs when not in use?
AllSpiceAlice commented 2024-10-17 03:30:43 +00:00
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@RevaReviewa I did not! Thank you for spotting that!

@RevaReviewa I did not! Thank you for spotting that!
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Reference: AllSpice-Demos/KiCAD-Demo#8
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