AllSpice-Demos/KiCAD-Demo
AllSpice-Demos/KiCAD-Demo
11
Fork 2
Files Issues 5 Design Reviews 1 Actions Releases 1 Activity

Bug Fixes and component re-positioning #8

Open
allspice-hermes wants to merge 10 commits from develop into main
pull from: develop
merge into: AllSpice-Demos:main
Upload Latest Revision
Conversation 6 Commits 10 Changes 5 +54194 -32632
allspice-hermes commented 2024-07-25 13:40:10 +00:00
Owner
Copy Link

Resolved Issues

  • Closes #5 Remove debug header to prevent misconnection

  • Closes #4 Replace LED with Part from Approved Parts List

  • Closes #3 Fix 5V Power Trace width

  • Add protection to endstops

  • Add LEDs to Fans

Description

V3 adds more protection to external cables/sensors and improves data transmission.
Resolves manufacturing and customer issues from V2.

EndStops.SchDoc
  • Add protection diode to endstops
  • Remove e-stop Endstop channel
Connectors.SchDoc
  • Move mounting holes and fiducials from Connectors to Power
Fans.SchDoc
  • Add LEDs to Fans
  • Fix Fan input protection
Microcontroller.SchDoc
  • Add protection diodes to MicroSD
  • Update bypass caps
  • Add inline resistors to SERCOM
  • Add yellow LED to PC1
Motor.SchDoc
  • Fix MOSI/MISO swap
  • Add protection circuitry to Motor
Power.SchDoc
  • Add fuses to VBED, VPWR_IN
  • Update +5V DCDC Regulator compensation and enable
Thermistors.SchDoc
  • Add 3rd thermistor channel
Thermocouples.SchDoc
  • Fix MOSI/MISO Swap
  • Remove _DRDY and _FAULT
USB.SchDoc
  • Add more filters to USB
  • Fix oscillator caps
  • Change isoisolator bias

Design Review Checklist

Process
  • Commits in correct branch @gautam at 3/19/25 @ 14:00
  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained
System
  • Power
    • Sufficient power supplied from upstream source
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • I/Os are specified
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review
Components
  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power
Schematics
  • Document
    • Dot on each connection
    • No four-point connections
    • Title block completed for each sheet
    • All components have reference designators and values
    • Multi-part components don't have unplaced symbols
    • Page title present and consistent on all pages if not in title block
    • Symbols identify open collector/drain pins and internal pulled up/down pins
    • Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
    • Components follow preferred reference designator pattern
  • External I/O
    • Filtered for EMI
    • Protected against electrostatic discharge (ESD)
    • Unused inputs terminated
  • Microcontrollers / ICs
    • Predictable or controlled power-up state
      • Reset filtered
    • Sufficient bypass capacitance
    • Oscillators checked for reliable startup
    • Pullups on open-collector pins
    • Logic-low and logic-high voltage levels checked
    • No-connect pins labeled NC
    • Clock lines with series/parallel termination
    • Check for latchup & off-voltage
    • Check datasheet errata/apnotes
  • Busses
    • UART/USART TX->RX and RX<-TX
    • I2C pullups per capacitance
    • Bus timing checked
  • Analog
    • Adequate power rails
    • Amplifier stability
    • Rate-of-rise/fall checked
  • General
    • Bulk capacitance
    • Polarized components
    • Reverse voltage on electrolytics
    • Cap derating for MTBF
    • LDO capacitance
    • Comparator slew/timing
    • Opamp common mode input range
    • Custom part pin verification
    • BJT base-emitter reverse current
    • Consistent power net names
    • Debug features included
PCB

  • Manufacturing

    • Requirements on fab layer
      • Plating: material + thickness
      • Stack-up, trace/space, hole size
      • PCB/silkscreen color
      • Impedance, blind/buried vias
      • Panelization, routing, drill table
      • Specs > tolerance
    • Power plane spacing minimized
    • Proper solder paste & fiducials

  • Footprints

    • Pin 1 marked
    • Polarity marked (diodes, LEDs, caps)
    • Dimensions vs datasheet
    • Thermal pads present

  • Placement

    • Accessible jumpers, debug
    • Correct resistor placement
    • SMPS loop minimized
    • Cap & driver proximity
    • SMT top / THT bottom

  • Clearance

    • Keep-outs honored
    • Clearance per voltage rating
    • Avoid edge components

  • Mechanical

    • CAD uploaded
    • Connector + harness clearance
    • Isolated mounting holes
    • Defined outline/enclosure
    • Rounded internal corners

  • Electrical

    • All nets routed
    • Analog/digital common joined once
    • ERC passes
    • Isolation barriers OK

  • Signal Integrity

    • Ground plane gaps minimized
    • No gaps under high-speed signals
    • No stubs, impedance matched pairs
    • Terminated lines
    • Short crystal paths
    • Guard ring
    • Avoid under/noisy components
    • RF via fencing < 1/20 λ
    • Shield can option

  • Copper Pour

    • All planes poured
    • No high-impedance paths
    • No pour between IC pins

  • Traces

    • Oblique trace angles
    • Correct width/via size
    • No pin-to-pin shortcuts
    • Smooth bends for impedance

  • Thermal

    • Separate heat sources
    • Thermal vias in pads

  • Testing

    • Critical test points added
    • Ground near analog test points

  • Silk screen

    • Rev, date, serial space
    • No silk on pads/vias
    • 2-direction readable text
    • Legible font
    • Connector pinouts
    • Fuse specs
    • Functional groups
    • Test points, LEDs, buttons, jumpers labeled
## Resolved Issues - Closes #5 Remove debug header to prevent misconnection - Closes #4 Replace LED with Part from Approved Parts List - Closes #3 Fix 5V Power Trace width - Add protection to endstops - Add LEDs to Fans ## Description V3 adds more protection to external cables/sensors and improves data transmission. Resolves manufacturing and customer issues from V2. <details> <summary>EndStops.SchDoc</summary> - Add protection diode to endstops - Remove e-stop Endstop channel </details> <details> <summary>Connectors.SchDoc</summary> - Move mounting holes and fiducials from Connectors to Power </details> <details> <summary>Fans.SchDoc</summary> - Add LEDs to Fans - Fix Fan input protection </details> <details> <summary>Microcontroller.SchDoc</summary> - Add protection diodes to MicroSD - Update bypass caps - Add inline resistors to SERCOM - Add yellow LED to PC1 </details> <details> <summary>Motor.SchDoc</summary> - Fix MOSI/MISO swap - Add protection circuitry to Motor </details> <details> <summary>Power.SchDoc</summary> - Add fuses to VBED, VPWR_IN - Update +5V DCDC Regulator compensation and enable </details> <details> <summary>Thermistors.SchDoc</summary> - Add 3rd thermistor channel </details> <details> <summary>Thermocouples.SchDoc</summary> - Fix MOSI/MISO Swap - Remove _DRDY and _FAULT </details> <details> <summary>USB.SchDoc</summary> - Add more filters to USB - Fix oscillator caps - Change isoisolator bias </details> --- ## Design Review Checklist <details> <summary>Process</summary> - [x] Commits in correct branch @gautam at 3/19/25 @ 14:00 - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [x] Power - [x] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [ ] Voltage - [ ] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [x] Components follow preferred reference designator pattern - [x] External I/O - [x] Filtered for EMI - [x] Protected against electrostatic discharge (ESD) - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Predictable or controlled power-up state - [x] Reset filtered - [x] Sufficient bypass capacitance - [x] Oscillators checked for reliable startup - [x] Pullups on open-collector pins - [x] Logic-low and logic-high voltage levels checked - [x] No-connect pins labeled NC - [x] Clock lines with series/parallel termination - [x] Check for latchup & off-voltage - [x] Check datasheet errata/apnotes - [ ] Busses - [ ] UART/USART TX->RX and RX<-TX - [ ] I2C pullups [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Bus timing checked - [x] Analog - [x] Adequate power rails - [x] Amplifier stability - [x] Rate-of-rise/fall checked - [ ] General - [ ] Bulk capacitance - [ ] Polarized components - [ ] Reverse voltage on electrolytics - [ ] Cap derating for MTBF - [x] LDO capacitance - [ ] Comparator slew/timing - [ ] Opamp common mode input range - [ ] Custom part pin verification - [ ] BJT base-emitter reverse current - [ ] Consistent power net names - [ ] Debug features included </details> <details> <summary>PCB</summary> - [x] Manufacturing - [x] Requirements on `fab` layer - [x] Plating: material + thickness - [x] Stack-up, trace/space, hole size - [x] PCB/silkscreen color - [x] Impedance, blind/buried vias - [x] Panelization, routing, drill table - [x] Specs > tolerance - [x] Power plane spacing minimized - [x] Proper solder paste & fiducials - [x] Footprints - [x] Pin 1 marked - [x] Polarity marked (diodes, LEDs, caps) - [x] Dimensions vs datasheet - [x] Thermal pads present - [x] Placement - [x] Accessible jumpers, debug - [x] Correct resistor placement - [x] SMPS loop minimized - [x] Cap & driver proximity - [x] SMT top / THT bottom - [x] Clearance - [x] Keep-outs honored - [x] Clearance per voltage rating - [x] Avoid edge components - [x] Mechanical - [x] CAD uploaded - [x] Connector + harness clearance - [x] Isolated mounting holes - [x] Defined outline/enclosure - [x] Rounded internal corners - [x] Electrical - [x] All nets routed - [x] Analog/digital common joined once - [x] ERC passes - [x] Isolation barriers OK - [x] Signal Integrity - [x] Ground plane gaps minimized - [x] No gaps under high-speed signals - [x] No stubs, impedance matched pairs - [x] Terminated lines - [x] Short crystal paths - [x] Guard ring - [x] Avoid under/noisy components - [x] RF via fencing < 1/20 λ - [x] Shield can option - [x] Copper Pour - [x] All planes poured - [x] No high-impedance paths - [x] No pour between IC pins - [x] Traces - [x] Oblique trace angles - [x] Correct width/via size - [x] No pin-to-pin shortcuts - [x] Smooth bends for impedance - [x] Thermal - [x] Separate heat sources - [x] Thermal vias in pads - [x] Testing - [x] Critical test points added - [x] Ground near analog test points - [ ] Silk screen - [x] Rev, date, serial space - [x] No silk on pads/vias - [ ] 2-direction readable text - [ ] Legible font - [ ] Connector pinouts - [ ] Fuse specs - [ ] Functional groups - [ ] Test points, LEDs, buttons, jumpers labeled </details> <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
Screenshot 2024-10-16 at 9.40.33 PM.png
50 KiB
Screenshot 2024-10-16 at 9.40.33 PM.png
allspice-hermes added the
priority/4 - high
layout
 labels 2024-07-25 13:40:10 +00:00
AllSpiceAlice was assigned by allspice-hermes 2024-07-25 13:40:10 +00:00
RevaReviewa was assigned by allspice-hermes 2024-07-25 13:40:10 +00:00
allspice-hermes added 1 commit 2024-07-25 13:40:10 +00:00
brendan reviewed 2024-09-18 17:29:31 +00:00
SingleBoardComputer.kicad_pcb Outdated
brendan commented 2024-09-18 17:29:31 +00:00
Owner
Copy Link

@gautam Please review

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" layers="1" diff-visibility="full" variant="default" view-coords="75.0,29.9,86.1,45.4" aspect-ratio="0.994" } @gautam Please review
👍 1
brendan marked this conversation as resolved
allspice-hermes requested review from AllSpiceAlice 2024-10-01 18:30:39 +00:00
allspice-hermes removed review request for AllSpiceAlice 2024-10-01 18:30:47 +00:00
allspice-hermes requested review from AngelaGlobalPCBA 2024-10-01 18:30:47 +00:00
allspice-hermes requested review from RevaReviewa 2024-10-01 18:31:03 +00:00
allspice-hermes removed review request for RevaReviewa 2024-10-01 18:42:38 +00:00
AllSpiceAlice reviewed 2024-10-17 01:44:28 +00:00
SingleBoardComputer.kicad_pcb Outdated
AllSpiceAlice commented 2024-10-17 01:44:28 +00:00
Owner
Copy Link

Please check the vias underneath U100 @daniel

Please check the vias underneath U100 @daniel !thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="42.8,42.4,57.1,56.2" aspect-ratio="0.994" }
MikaChanical reviewed 2024-10-17 01:50:41 +00:00
SingleBoardComputer.kicad_pcb Outdated
MikaChanical commented 2024-10-17 01:50:41 +00:00
Member
Copy Link

@AllSpiceAlice , can you update the silkscreen on this footprint. It's unclear where to place it.

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="31.7,21.8,82.2,28.9" aspect-ratio="0.994" } @AllSpiceAlice , can you update the silkscreen on this footprint. It's unclear where to place it.
AllSpiceAlice commented 2024-10-17 03:15:45 +00:00
Owner
Copy Link

@MikaChanical , how does J3 look? If you like it, I'll fix the other connector.

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...1ad1cc6d8062201c0f3e9d2e8271c5c6b78b37fe" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="32.9,22.3,61.2,27.1" aspect-ratio="0.994" } @MikaChanical , how does J3 look? If you like it, I'll fix the other connector.
MikaChanical commented 2024-10-17 03:18:20 +00:00
Member
Copy Link

@AllSpiceAlice, would you make both the Pin-1 triangle and circle markers bigger. There are models with polarized retention features, so we need this to be big enough for fab.

@AllSpiceAlice, would you make both the Pin-1 triangle and circle markers bigger. There are models with polarized retention features, so we need this to be big enough for fab.
AllSpiceAlice commented 2024-10-17 03:23:15 +00:00
Owner
Copy Link

@MikaChanical , how do these look? I removed the triangle to cut down on visual clutter.

!thumbnail[](SingleBoardComputer.kicad_pcb){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...a3c822e27c2b431d95cff1fd8b9d166fa3007c5e" pr="8" layers="82,81,63,61,60,59,58,57,33,35,37,1,32,38,34" diff-visibility="full" variant="default" view-coords="28.8,21.6,85.1,30.1" aspect-ratio="0.994" } @MikaChanical , how do these look? I removed the triangle to cut down on visual clutter.
AllSpiceAlice added 1 commit 2024-10-17 02:10:19 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:12:49 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:21:39 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:34:58 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:39:14 +00:00
AllSpiceAlice added 1 commit 2024-10-17 02:48:03 +00:00
PavelInPurchasing reviewed 2024-10-17 02:58:03 +00:00
Bootloader-ATMEGA16U.kicad_sch
PavelInPurchasing commented 2024-10-17 02:58:03 +00:00
Member
Copy Link

@daniel , can you remove this connector? It's EOL, and the team agreed they didn't need it anyways.

!thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...5fd194e5655270f77442cdb95cbbe5606af50380" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="65.4,27.2,73.8,39.0" aspect-ratio="1.405" } @daniel , can you remove this connector? It's EOL, and the team agreed they didn't need it anyways.
daniel-allspice commented 2024-10-17 03:01:10 +00:00
Member
Copy Link

@PavelInPurchasing, it's been removed

@PavelInPurchasing, it's been removed !thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...4d8a762fe08925f5f8fa254d91605e36e96f5fe3" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="48.8,29.9,67.2,39.4" aspect-ratio="1.405" }
RevaReviewa reviewed 2024-10-17 03:05:34 +00:00
Bootloader-ATMEGA16U.kicad_sch
RevaReviewa commented 2024-10-17 03:05:34 +00:00
Member
Copy Link

@AllSpiceAlice, can you add another reset switch to GND for RESET2?

!thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...5fd194e5655270f77442cdb95cbbe5606af50380" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="31.7,23.7,43.2,29.5" aspect-ratio="1.405" } @AllSpiceAlice, can you add another reset switch to GND for RESET2?
AllSpiceAlice commented 2024-10-17 03:07:21 +00:00
Owner
Copy Link

@RevaReviewa , here you go! That should help the manufacturing team figure out the programming sequence without worrying about bricking the microcontrollers or the bootloader.

!thumbnail[](Bootloader-ATMEGA16U.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...4d8a762fe08925f5f8fa254d91605e36e96f5fe3" pr="8" doc-id="2318a9d9d4f9a5612643" diff-visibility="full" variant="default" view-coords="15.7,14.2,43.2,34.8" aspect-ratio="1.405" } @RevaReviewa , here you go! That should help the manufacturing team figure out the programming sequence without worrying about bricking the microcontrollers or the bootloader.
AllSpiceAlice added 1 commit 2024-10-17 03:11:30 +00:00
AllSpiceAlice added 1 commit 2024-10-17 03:14:27 +00:00
AllSpiceAlice added 1 commit 2024-10-17 03:22:26 +00:00
RevaReviewa reviewed 2024-10-17 03:28:06 +00:00
VREG_5V_3.3V.kicad_sch
RevaReviewa commented 2024-10-17 03:28:06 +00:00
Member
Copy Link

@AllSpiceAlice, can we disconnect SCK from this buffer? We're getting interference.

!thumbnail[](VREG_5V_3.3V.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...f0c6d1baba28db424093a9ac75be40fd55c2c518" pr="8" doc-id="3c86f159e194b13ca2d9" diff-visibility="full" variant="default" view-coords="5.4,45.6,33.0,67.0" aspect-ratio="1.405" } @AllSpiceAlice, can we disconnect SCK from this buffer? We're getting interference.
AllSpiceAlice commented 2024-10-17 03:29:08 +00:00
Owner
Copy Link

@RevaReviewa , Removed

!thumbnail[](VREG_5V_3.3V.kicad_sch){ diff="AllSpice-Demos/KiCAD-Demo:8a26e4d6dbeb69a5cd3cbba54807ba080ccb3192...a3c822e27c2b431d95cff1fd8b9d166fa3007c5e" pr="8" doc-id="3c86f159e194b13ca2d9" diff-visibility="full" variant="default" view-coords="5.2,43.3,34.5,65.2" aspect-ratio="1.405" } @RevaReviewa , Removed
RevaReviewa commented 2024-10-17 03:30:15 +00:00
Member
Copy Link

@AllSpiceAlice did you park the comparator? You need to check the datasheet to see if you need to pull up/down the inputs/outputs when not in use?

@AllSpiceAlice did you park the comparator? You need to check the datasheet to see if you need to pull up/down the inputs/outputs when not in use?
AllSpiceAlice commented 2024-10-17 03:30:43 +00:00
Owner
Copy Link

@RevaReviewa I did not! Thank you for spotting that!

@RevaReviewa I did not! Thank you for spotting that!
This design review can be merged automatically.
This branch is out-of-date with the base branch
You are not authorized to merge this design review.
View command line instructions.

Checkout

From your project repository, check out a new branch and test the changes.
git fetch -u origin develop:develop
git checkout develop
Sign in to join this conversation.
Reviewers
No Reviewers
brendan
AngelaGlobalPCBA
AllSpiceAlice
MikaChanical
PavelInPurchasing
RevaReviewa
Labels
Clear labels
bug
Something doesn't work
dfm
Design for manufacturing consideration
documentation
Improvements to supporting documentation
eol
End of life component
feature
New feature or request
firmware
Requires FW attention
layout
Requires PCB layout attention
mechanical
Requires ME attention
priority/1 - idea
Nice to have or idea to capture
priority/2 - low
Should be resolved eventually
priority/3 - medium
Should be resolved before product launch
priority/4 - high
Should be resolved before next release
priority/5 - critical
Must be fixed immediately - blocking item
bug
Something doesn't work
dfm
Design for manufacturing consideration
documentation
Improvements to supporting documentation
eol
End of life component
feature
New feature or request
firmware
Requires FW attention
layout
Requires PCB layout attention
mechanical
Requires ME attention
priority/1 - idea
Nice to have or idea to capture
priority/2 - low
Should be resolved eventually
priority/3 - medium
Should be resolved before product launch
priority/4 - high
Should be resolved before next release
priority/5 - critical
Must be fixed immediately - blocking item
No Label
layout
priority/4 - high
Milestone
No items
No Milestone
Assignees
Clear assignees
allspice-admin-daniel AllSpiceAlice allspice-carah allspice-eli allspice-hermes allspice-ian allspice-kyle allspice-thomas brendan coleblaeser daniel-allspice emmy john-allspice MikaChanical nick NickHerbert PavelInPurchasing RevaReviewa rowan sam sherry Tayawiggins valentina
No Assignees AllSpiceAlice RevaReviewa
7 Participants
Notifications
Due Date
No due date set.
Dependencies

No dependencies set.

Reference: AllSpice-Demos/KiCAD-Demo#8
No description provided.
Delete Branch "develop"

Deleting a branch is permanent. Although the deleted branch may continue to exist for a short time before it actually gets removed, it CANNOT be undone in most cases. Continue?