AllSpice-Demos/OrCAD-Demo

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Fix schematic and PCB Errors #2

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AllSpiceAlice wants to merge 10 commits from develop into main

AllSpiceAlice commented

2025-05-21 01:01:42 +00:00

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Resolved Issues

V0.4 Fixes

Fix USB_DM, USB_DP swap, resolves #3
Fix GPIO24 bias resistors R10, R1, swapped
Remove C19, C20, excessive bypass caps
Add protection diode D1 between VBUS and VSYS
Remove jumper R16 from 3V3 to U1
Adjust USB data transmission resistors R12, R13 from 24 Ω to 27 Ω
Add Bootselect switch
Swap QSPI_SD2, QSPI_SD3
Remove Debug2 connector J3
Add protection to endstops
Add LEDs to Fans

Description

Overview

V0.4 Fixes design errors from V0.3

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes match design usage
- Reference designators follow standard
External I/O
- EMI filtered
- ESD protection
- Unused inputs terminated
Microcontrollers / ICs
- Controlled power-up state
  - Reset filtered
- Bypass caps
- Oscillator startup
- Pullups on OC pins
- Logic levels verified
- No-connect pins labeled
- Termination for clock lines
- Input voltage risks & latchup
- Datasheet errata reviewed
Busses
- UART TX->RX and RX<-TX
- I2C pullups per capacitance
- Timing reviewed
Analog
- Rail availability
- Amp stability
- Rise/fall timing
General
- Bulk capacitance
- Polarized components
- Reverse voltage checked
- Derating for MTBF
- LDOs have sufficient caps
- Comparator timing
- Opamp input range
- Custom pin numbers verified
- BJT reverse current
- Net naming consistent
- Debug resources added

PCB

Manufacturing
- fab layer info present
  - Plating
  - Stack-up
  - Trace/space
  - Hole size
  - PCB/silkscreen color
  - Impedance
  - Blind/buried vias
  - Panelization and routing
  - Drill table
  - Tolerance margins
- Power planes spaced
- Solder paste OK
- Fiducials placed
Footprints
- Pin 1 marked
- Polarity marked
- Matches datasheet
- Thermal pads OK
Placement
- Jumpers & debug accessible
- Filtering close to source
- Termination near targets
- SMPS loops minimized
- Caps & drivers close
- SMT top, THT bottom
Clearance
- Keep-outs respected
- Clearance by voltage
- No components at edge
Mechanical
- CAD file uploaded
- Clearance for connectors
- Harness radius OK
- Isolated mounting holes
- Board outline + enclosure defined
- Milled corners
Electrical
- All traces routed
- Analog/digital join once
- ERC passes
- Isolation barriers
Signal Integrity
- Ground gaps minimized
- No gaps under HS signals
- No stubs
- Differential pairs matched
- Terminated lines
- Short crystal lines
- Crystal guard ring
- No traces under sensitive or noisy parts
- RF via fencing OK
- Shielding can considered
Copper Pour
- Poured planes
- No high-Z paths
- No pour between IC pins
Traces
- Angled trace-pad
- Widths for current & heating
- No IC pin shorts
- Large vias for internal power
- Mitered bends or curves
Thermal
- Hot/cold components spaced
- Thermal vias in pads
Testing
- Test points added
- Analog test ground nearby
Silk screen
- Revision, date, serial space
- No silk over pads
- Text readable from 2 sides
- Font legibility
- Connector pinouts
- Fuse specs
- Group labels
- Functionality labels: test pts, LEDs, buttons, connectors

## Resolved Issues <details> <summary>V0.4 Fixes</summary> - Fix USB_DM, USB_DP swap, resolves #3 - Fix GPIO24 bias resistors R10, R1, swapped - Remove C19, C20, excessive bypass caps - Add protection diode D1 between VBUS and VSYS - Remove jumper R16 from 3V3 to U1 - Adjust USB data transmission resistors R12, R13 from 24 Ω to 27 Ω - Add Bootselect switch - Swap QSPI_SD2, QSPI_SD3 - Remove Debug2 connector J3 - Add protection to endstops - Add LEDs to Fans </details> ## Description <details> <summary>Overview</summary> V0.4 Fixes design errors from V0.3 </details> --- ## Design Review Checklist <details> <summary>Process</summary> - [ ] Commits in correct branch - [ ] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [x] Power - [x] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes match design usage - [x] Reference designators follow standard - [x] External I/O - [x] EMI filtered - [x] ESD protection - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Controlled power-up state - [x] Reset filtered - [x] Bypass caps - [x] Oscillator startup - [x] Pullups on OC pins - [x] Logic levels verified - [x] No-connect pins labeled - [x] Termination for clock lines - [x] Input voltage risks & latchup - [x] Datasheet errata reviewed - [ ] Busses - [ ] UART TX->RX and RX<-TX - [ ] I2C pullups [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Timing reviewed - [x] Analog - [x] Rail availability - [x] Amp stability - [x] Rise/fall timing - [ ] General - [ ] Bulk capacitance - [ ] Polarized components - [ ] Reverse voltage checked - [ ] Derating for MTBF - [x] LDOs have sufficient caps - [ ] Comparator timing - [ ] Opamp input range - [ ] Custom pin numbers verified - [ ] BJT reverse current - [ ] Net naming consistent - [ ] Debug resources added </details> <details> <summary>PCB</summary> - [x] Manufacturing - [x] `fab` layer info present - [x] Plating - [x] Stack-up - [x] Trace/space - [x] Hole size - [x] PCB/silkscreen color - [x] Impedance - [x] Blind/buried vias - [x] Panelization and routing - [x] Drill table - [x] Tolerance margins - [x] Power planes spaced - [x] Solder paste OK - [x] Fiducials placed - [x] Footprints - [x] Pin 1 marked - [x] Polarity marked - [x] Matches datasheet - [x] Thermal pads OK - [x] Placement - [x] Jumpers & debug accessible - [x] Filtering close to source - [x] Termination near targets - [x] SMPS loops minimized - [x] Caps & drivers close - [x] SMT top, THT bottom - [x] Clearance - [x] Keep-outs respected - [x] Clearance by voltage - [x] No components at edge - [x] Mechanical - [x] CAD file uploaded - [x] Clearance for connectors - [x] Harness radius OK - [x] Isolated mounting holes - [x] Board outline + enclosure defined - [x] Milled corners - [x] Electrical - [x] All traces routed - [x] Analog/digital join once - [x] ERC passes - [x] Isolation barriers - [x] Signal Integrity - [x] Ground gaps minimized - [x] No gaps under HS signals - [x] No stubs - [x] Differential pairs matched - [x] Terminated lines - [x] Short crystal lines - [x] Crystal guard ring - [x] No traces under sensitive or noisy parts - [x] RF via fencing OK - [x] Shielding can considered - [x] Copper Pour - [x] Poured planes - [x] No high-Z paths - [x] No pour between IC pins - [x] Traces - [x] Angled trace-pad - [x] Widths for current & heating - [x] No IC pin shorts - [x] Large vias for internal power - [x] Mitered bends or curves - [x] Thermal - [x] Hot/cold components spaced - [x] Thermal vias in pads - [x] Testing - [x] Test points added - [x] Analog test ground nearby - [ ] Silk screen - [x] Revision, date, serial space - [x] No silk over pads - [ ] Text readable from 2 sides - [ ] Font legibility - [ ] Connector pinouts - [ ] Fuse specs - [ ] Group labels - [ ] Functionality labels: test pts, LEDs, buttons, connectors </details>

AllSpiceAlice added 1 commit 2025-05-21 01:01:42 +00:00

Add V1 Changes

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339fec9bb1

AllSpiceAlice changed title from ~~Add V1 Changes~~ to Fix schematic and PCB Errors

2025-05-21 01:03:26 +00:00

AllSpiceAlice requested review from RevaReviewa 2025-05-21 01:03:33 +00:00

AllSpiceAlice requested review from daniel-allspice 2025-05-21 01:03:42 +00:00

AllSpiceAlice requested review from MikaChanical 2025-05-21 01:03:55 +00:00

AllSpiceAlice requested review from PavelInPurchasing 2025-05-21 01:04:02 +00:00

AllSpiceAlice added the

priority/5 - critical

layout

firmware

dfm

labels 2025-05-21 01:04:23 +00:00

daniel-allspice was assigned by AllSpiceAlice

2025-05-21 01:05:22 +00:00

RevaReviewa reviewed 2025-05-21 01:16:43 +00:00

RPI-PICO-R3-PUBLIC.DSN

RevaReviewa commented

2025-05-21 01:16:43 +00:00

Member

@daniel-allspice, can you check QSPI_D2 and QSPI_D3? They look swapped.

!thumbnail[](RPI-PICO-R3-PUBLIC.DSN){ diff="AllSpice-Demos/OrCAD-Demo:2a50172cd61cff4bdc27f4ca4151cba26cc7b715...339fec9bb188f677e9dd59211eb105780a340a6f" pr="2" doc-id="67612bb56aa7d3a48b11" diff-visibility="full" variant="default" view-coords="3.3,50.9,28.1,67.9" aspect-ratio="1.404" } @daniel-allspice, can you check QSPI_D2 and QSPI_D3? They look swapped.

AllSpiceAlice commented

2025-05-21 01:18:22 +00:00

Author

Owner

@RevaReviewa , this has been fixed in V0.4

> @RevaReviewa , this has been fixed in V0.4

brendan marked this conversation as resolved

PavelInPurchasing reviewed 2025-05-21 01:21:29 +00:00

RPI-PICO-R3-PUBLIC.DSN

PavelInPurchasing commented

2025-05-21 01:21:29 +00:00

Member

Please update MFG and MPN info for [U1, J2, R4, R15, J0]. USE THE APL!

!thumbnail[](RPI-PICO-R3-PUBLIC.DSN){ diff="AllSpice-Demos/OrCAD-Demo:2a50172cd61cff4bdc27f4ca4151cba26cc7b715...339fec9bb188f677e9dd59211eb105780a340a6f" pr="2" doc-id="67612bb56aa7d3a48b11" diff-visibility="full" variant="default" view-coords="39.7,50.2,58.8,78.9" aspect-ratio="1.404" } Please update MFG and MPN info for [U1, J2, R4, R15, J0]. USE THE APL!

Screenshot 2025-05-20 at 8.19.00 PM.png

24 KiB

AllSpiceAlice marked this conversation as resolved

MikaChanical reviewed 2025-05-21 01:26:57 +00:00

RPI-PICO-R3a-PUBLIC.brd

MikaChanical commented

2025-05-21 01:26:57 +00:00

Member

@AllSpiceAlice, mechanical review complete. No change to board outline, or mounting features. All new components (and old components) are below the height limit. It think it's ready! Thermal review looks good. It still needs to pass RF review. Too magic for me.

!thumbnail[](RPI-PICO-R3a-PUBLIC.brd){ diff="AllSpice-Demos/OrCAD-Demo:2a50172cd61cff4bdc27f4ca4151cba26cc7b715...339fec9bb188f677e9dd59211eb105780a340a6f" pr="2" layers="81,82,1,32,67,66,42,41,65,64,40,37,38,35,36,33,34,57" diff-visibility="full" variant="default" view-coords="7.2,5.9,94.2,93.1" aspect-ratio="0.510" } @AllSpiceAlice, mechanical review complete. No change to board outline, or mounting features. All new components (and old components) are below the height limit. It think it's ready! Thermal review looks good. It still needs to pass RF review. Too magic for me.

MikaChanical referenced this design review

2025-05-21 01:30:07 +00:00

Mechanical Review [Done] -> RF Review [WIP] #4

RevaReviewa reviewed 2025-05-21 01:44:14 +00:00

RPI-PICO-R3a-PUBLIC.brd

RevaReviewa commented

2025-05-21 01:44:14 +00:00

Member

@AllSpiceAlice , can we fix this pinch point in the polygon region?

!thumbnail[](RPI-PICO-R3a-PUBLIC.brd){ diff="AllSpice-Demos/OrCAD-Demo:2a50172cd61cff4bdc27f4ca4151cba26cc7b715...339fec9bb188f677e9dd59211eb105780a340a6f" pr="2" layers="1" diff-visibility="removed" variant="default" view-coords="26.3,18.4,52.5,26.9" aspect-ratio="0.510" } @AllSpiceAlice , can we fix this pinch point in the polygon region?

RevaReviewa commented

2025-05-21 01:45:30 +00:00

Member

![image](/attachments/969ca598-da25-41da-9df6-3cdbb67935d7)

image.png

22 KiB

RevaReviewa reviewed 2025-05-21 01:46:52 +00:00

RPI-PICO-R3-PUBLIC.DSN

RevaReviewa commented

2025-05-21 01:46:52 +00:00

Member

@AllSpiceAlice, great addition. Now let's replace it with a part from the APL. 🥰

!thumbnail[](RPI-PICO-R3-PUBLIC.DSN){ diff="AllSpice-Demos/OrCAD-Demo:2a50172cd61cff4bdc27f4ca4151cba26cc7b715...339fec9bb188f677e9dd59211eb105780a340a6f" pr="2" doc-id="67612bb56aa7d3a48b11" diff-visibility="full" variant="default" view-coords="7.7,26.9,32.4,52.7" aspect-ratio="1.404" } @AllSpiceAlice, great addition. Now let's replace it with a part from the APL. 🥰

MikaChanical reviewed 2025-05-21 01:48:40 +00:00

RPI-PICO-R3a-PUBLIC.brd

MikaChanical commented

2025-05-21 01:48:10 +00:00

Member

@AllSpiceAlice , the spec for the mounting holes is 2.1mm (± 0.05mm). We're getting reports that the prototypes aren't hitting this spec. Can you check the actual file?

!thumbnail[](RPI-PICO-R3a-PUBLIC.brd){ diff="AllSpice-Demos/OrCAD-Demo:2a50172cd61cff4bdc27f4ca4151cba26cc7b715...339fec9bb188f677e9dd59211eb105780a340a6f" pr="2" layers="81,82,1,32,67,66,42,41,65,64,40,37,38,35,36,33,34,57" diff-visibility="full" variant="default" view-coords="25.6,7.2,76.6,18.3" aspect-ratio="0.510" } @AllSpiceAlice , the spec for the mounting holes is 2.1mm (± 0.05mm). We're getting reports that the prototypes aren't hitting this spec. Can you check the actual file?

MikaChanical referenced this design review

2025-05-21 01:49:48 +00:00

Check USB mounting hole size against spec. Check field reports for quality yields. #7

AllSpiceAlice added this to the V1 Critical Design Review milestone 2025-05-21 01:54:59 +00:00

AllSpiceAlice reviewed 2025-05-28 16:36:45 +00:00

brendan referenced this design review

2025-05-30 00:02:26 +00:00

Test #9

AllSpiceAlice added 1 commit 2025-06-02 00:39:34 +00:00

Update BOM view

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AllSpiceAlice added 1 commit 2025-06-02 00:40:32 +00:00

Fix typo in display_bom.py

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AllSpiceAlice added 1 commit 2025-06-02 00:42:51 +00:00

s/Python/Python3

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AllSpiceAlice added 1 commit 2025-06-02 00:48:27 +00:00

Change clone method

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AllSpiceAlice added 1 commit 2025-06-02 00:49:26 +00:00

Fix path to script

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allspice-thomas removed review request for RevaReviewa 2025-06-04 17:12:22 +00:00

allspice-thomas requested review from RevaReviewa 2025-06-04 17:12:54 +00:00

allspice-thomas requested review from allspice-thomas 2025-06-04 22:38:36 +00:00

allspice-thomas approved these changes 2025-06-04 22:41:53 +00:00

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allspice-thomas left a comment

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looks good.

allspice-thomas dismissed allspice-thomas’s review 2025-06-04 22:42:31 +00:00

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yes

allspice-thomas requested review from allspice-thomas 2025-06-05 18:46:20 +00:00

AllSpiceAlice reviewed 2025-06-12 18:25:36 +00:00

RPI-PICO-R3-PUBLIC.DSN

AllSpiceAlice commented

2025-06-12 18:25:36 +00:00

Author

Owner

check ground @AllSpiceAlice

!thumbnail[](RPI-PICO-R3-PUBLIC.DSN){ diff="AllSpice-Demos/OrCAD-Demo:2a50172cd61cff4bdc27f4ca4151cba26cc7b715...37fe8547d0ca9f70f681a91bebdddc83efe527c0" pr="2" doc-id="67612bb56aa7d3a48b11" diff-visibility="full" variant="default" view-coords="79.9,47.6,96.9,59.3" aspect-ratio="1.405" } check ground @AllSpiceAlice

allspice-thomas added 1 commit 2025-06-25 17:31:55 +00:00