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Schematic design for V3 release #13
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Reference: AllSpice-Demos/SystemCap-Demo-Project#13
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Design Review Checklist
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Parts Check Report
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Validation Rules
Each part must have:
Issues
U11
Problems
U14
Problems
U5
Problems
J8
Problems
J9
Problems
J11
Problems
PTH1
Problems
PTH2
Problems
PTH3
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PTH4
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U36
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U33
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J13
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@allspice-andy that was just a debug header so no issue removing it 👍
DRCY has reviewed this Design Review, and there should be a review posted below.
DRCY Connections Checker Review
DRCY reviewed the 5 pages that changed in this design review. It selected 169 components to review and found 36 potential issues in 87 components. DRCY posted a comment on the schematic for each issue. Component Details below lists every component DRCY reviewed.
Component Details
DRCY reviewed all connections of the following components:
DRCY uses AI. Please verify the outputs.
[🚨 Error] Component
U2, pinsN19, R15, T18, V14, W17, Y20: Bank 34 VCCO is on VD_GPIO, which has no source anywhere; rename it to VDD_GPIO.Observed: All six bank 34 VCCO balls (VCCO_34_1..6) connect to net VD_GPIO. Across the whole design, VD_GPIO reaches only those six balls, the decoupling capacitors on this page (C126–C134) and one port symbol. No regulator, connector or other source drives it. The I/O rail that does exist is VDD_GPIO. It supplies bank 13 VCCO, the TPD12S016 VCCA and the bank 34 pull-ups R18/R20 on this same page. The VD_GPIO name looks like a typo for VDD_GPIO.
Requirement: Each PL I/O bank needs its VCCO supplied at the chosen I/O voltage (1.2–3.3 V for HR banks), because VCCO powers the bank's output drivers and some of its input buffers.
Consequence: Bank 34 has no supply, so GPIO0–11 on J11, the HDMI transmitter data/sync/clock lines, HDMI_INT, PS_I2C_SCL, PROG_IO and TURBO_MODE cannot work. Signals pulled to or driven at VDD_GPIO (R20, R18, R22, U36/R328) would also back-feed the unpowered bank through its I/O clamp paths.
Evidence:
Suggested repair: Rename the VD_GPIO port/net on this page to VDD_GPIO, so bank 34 VCCO and C126–C134 join the rail its pull-ups and the level shifter already use. Alternatively, connect VD_GPIO to its intended regulator.
3 affected locations (one shared root cause)
C134, pin `1`; ComponentC126, pin `1`; ComponentC127, pin `1`; ComponentC128, pin `1`; ComponentC129, pin `1`; ComponentC130, pin `1`; ComponentC131, pin `1`; ComponentC132, pin `1`; ComponentC133, pin `1`; ComponentU2, pins `N19, R15, T18, V14, W17, Y20` (G002-F001)R41, pin `1`; ComponentR42, pin `1`; ComponentR44, pin `1`; ComponentR94, pin `1`; ComponentR82, pin `1`; ComponentU2, pins `N19, R15, T18, V14, W17, Y20` (G004-F001)U2, pins `N19, R15, T18, V14, W17, Y20` (G001-F001)Component
C134, pin `1`; ComponentC126, pin `1`; ComponentC127, pin `1`; ComponentC128, pin `1`; ComponentC129, pin `1`; ComponentC130, pin `1`; ComponentC131, pin `1`; ComponentC132, pin `1`; ComponentC133, pin `1`; ComponentU2, pins `N19, R15, T18, V14, W17, Y20`: Bank 34 VCCO and its decoupling are on an unsourced VD_GPIO net; rename it to VDD_GPIO. (G002-F001)Observed: The bank 34 VCCO pins (U2 N19, R15, T18, V14, W17, Y20) and all nine bank 34 decoupling capacitors (C126–C134 pin 1) are on a net called VD_GPIO. In the whole design, VD_GPIO contains only these pins and one port on this page. No regulator, connector or other page connects to it, and no other component or attribute anywhere uses the name VD_GPIO. The same page has two VDD_GPIO ports (used by pull-ups R18 and R20). Off-page, VDD_GPIO is driven by U30 VOLDO2 through R333 and also powers bank 13 VCCO.
Requirement: Each HR bank's common VCCO supply must be connected to a powered 1.2 V–3.3 V rail for the bank's I/O to work, and the bank decoupling has to sit on that powered rail.
Consequence: With VD_GPIO unconnected, bank 34 VCCO has no supply. The GPIO, HDMI and I2C SCL I/Os on bank 34 cannot drive or receive signals correctly. The pull-ups to VDD_GPIO (R18, R20, and R22 on HDMI_INT off-page) would also feed current into the unpowered bank through its I/O pins. The decoupling capacitors C126–C134 have no rail to decouple.
Evidence:
Suggested repair: Rename the VD_GPIO port and net to VDD_GPIO, the rail that powers bank 13 and the bank 34 pull-ups, or tie the bank to whichever rail is intended. Then confirm that the rail's voltage matches the I/O standards used on bank 34.
Component
R41, pin `1`; ComponentR42, pin `1`; ComponentR44, pin `1`; ComponentR94, pin `1`; ComponentR82, pin `1`; ComponentU2, pins `N19, R15, T18, V14, W17, Y20`: Bank 34 VCCO net VD_GPIO, which drives R41/R42/R44/R94/R82, has no supply; rename it to VDD_GPIO. (G004-F001)Observed: R41, R42, R44, R94 and R82 are driven by U2 bank 34 pins R17, V17, T17, Y17 and Y16. All six bank 34 VCCO balls (N19, R15, T18, V14, W17, Y20) sit on net VD_GPIO. In the whole design, VD_GPIO connects only to this page's port, the decoupling capacitors C126–C134 and those six VCCO balls. Nothing supplies it. On this same page, the bank 34 pull-ups R18 (N9/N17) and R20 (PS_I2C_SCL/N18) go to VDD_GPIO, a different net. VDD_GPIO is a real rail that powers bank 13 VCCO, the HDMI page and J13. So VD_GPIO looks like a misspelling of VDD_GPIO.
Requirement: Each HR bank has one common VCCO supply, which powers its output drivers and certain input buffers, at 1.2 V to 3.3 V. Without VCCO the bank cannot drive any outputs.
Consequence: Bank 34 has no output supply. HDMI_CLK, HDMI_DE, HDMI_HSYNC, HDMI_VSYNC, SPDIF and the HDMI_D8–D23 data lines into U26 (ADV7513) cannot be driven, so the HDMI path does not work. Bank 34 pins that are pulled up to the powered VDD_GPIO rail (N17, N18) would also back-feed an unpowered bank. That makes it impossible to check the 22.1 Ω series values against the bank 34 drive.
Evidence:
Suggested repair: Rename the VD_GPIO power port and net to VDD_GPIO, or tie it to the rail that is meant to supply bank 34, so that bank 34 VCCO shares the VDD_GPIO supply used by its pull-ups and by U26's interface.
Datasheets: U2, C126, C131, C134, R41
Replace a datasheet: C126, C127, C128, C129, C130, C131, C132, C133, C134, R41, R42, R44, R82, R94, U2
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[⚠️ Warning] Component
C135, pins1, 2; ComponentC136, pins1, 2; ComponentC137, pins1, 2; ComponentC138, pins1, 2; ComponentC139, pins1, 2: C135–C139 part number C1005X5R1C474K is not listed in the TDK range table; confirm it can be ordered.Observed: C135 through C139 carry MFG_PART_NO C1005X5R1C474K (0.47 µF, 16 V, X5R, 0402, ±10 %). The resolved TDK catalog's X5R capacitance-range table has no catalog number listed for 470 nF, C1005, 16 V. Every value for this part was decoded from the part-number construction rules, not read from a listed part.
Requirement: Each BOM entry must map to a part the manufacturer lists as orderable at the stated value, voltage and size.
Consequence: The 0.47 µF bank-35 decoupling parts may not be orderable as specified, which risks sourcing delay or uncontrolled substitution (for example a different voltage rating or thickness).
Evidence:
Suggested repair: Confirm with TDK or a distributor that C1005X5R1C474K (with full suffix) is orderable. If not, pick a listed 0.47 µF X5R 0402 part rated ≥6.3 V and update the BOM.
Datasheet: C135
Replace a datasheet: C135, C136, C137, C138, C139
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[⚠️ Warning] Component
C140, pins1, 2; ComponentC141, pins1, 2; ComponentC142, pins1, 2: The C140–C142 part number C1005X5R0J475K is incomplete and its K tolerance conflicts with the catalog.Observed: C140, C141 and C142 carry MFG_PART_NO/VENDOR_PN C1005X5R0J475K. That is a truncated TDK catalog number with tolerance code K (±10 %) and no thickness, packaging or special codes. Looking it up resolves to the soft-termination variant C1005X5R0J475K050BE, and that catalog's X5R capacitance-range table lists only ±20 % for the 4.7 µF 1005 row.
Requirement: The BOM part number must name one orderable part whose tolerance and termination match what the catalog offers for that value and size.
Consequence: Procurement or assembly may fail to source the part as written, or may substitute a different termination or tolerance variant. Decoupling still works with ±20 % parts, so this is a BOM and sourcing risk, not a functional failure.
Evidence:
Suggested repair: Replace the truncated number with a complete orderable TDK part number (for example a general-termination or soft-termination 4.7 µF 6.3 V X5R 0402 at a tolerance TDK offers), or list approved alternates.
Datasheet: C140
Replace a datasheet: C140, C141, C142
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[🚨 Error] Component
U2, pinN17; ComponentR18, pins1, 2: PS_I2C_SDA never reaches U2; R18/N17 on orphan net N9 should be labeled PS_I2C_SDA.Observed: U2 N17 (IO_L23P_T3_34) and the R18 4.75K pull-up to VDD_GPIO sit on page-local net N9, with nothing else connected. The TPD12S016 SDA_A pin (U37 pin 3) is on net PS_I2C_SDA. Design-wide, that net has only U37 and a port: no Zynq pin and no pull-up. The matching SCL line (PS_I2C_SCL) connects U2 N18, R20 and U37 SCL_A correctly. The PS_I2C_SDA label appears to be missing from N17/R18.
Requirement: An I2C/DDC bus needs both SCL and SDA wired from the controller to the level shifter, each with a pull-up on the controller-side rail.
Consequence: The I2C SDA line through U37 never reaches the Zynq and has no pull-up on the A side. I2C/DDC transactions behind U37 (HDMI DDC/EDID and any other I2C_SDA devices) fail, and R18 is a pull-up on an unused pin.
Evidence:
Suggested repair: Label net N9 (U2 N17 / R18 pin 2) PS_I2C_SDA so it joins U37 SDA_A.
Datasheets: U2, R18
Replace a datasheet: R18, U2
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[⚠️ Warning] Component
U2, pinU13; ComponentR223, pin2: PUDC_B strap R223 shares GPIO8_P with J11, so the strap and the user I/O can interfere.Observed: U2 U13 (IO_L3P_T0_DQS_PUDC_B_34) is the configuration-time PUDC_B strap. It is held low by R223 (1K to GND) and is also exported as GPIO8_P to expansion connector J11 pin 25, as the P leg of the GPIO8_P/GPIO8_N pair. GPIO8_N has no matching resistor.
Requirement: PUDC_B has to stay at a defined level during configuration, and that level should not depend on what is plugged into J11. Once configured, GPIO8_P is a user I/O and should not carry a resistive load that the rest of the bank's pairs do not have.
Consequence: An expansion board that drives or pulls GPIO8_P high during configuration can change the PUDC_B strap and with it the I/O pull-up state while configuration runs. In use, a 1K load to ground draws several mA from a high output and unbalances the GPIO8 pair when it is used differentially.
Evidence:
Suggested repair: Document that GPIO8_P is a configuration strap carrying a 1K pull-down on the expansion connector. Alternatively, strap PUDC_B on a ball that is not brought out to J11.
Datasheets: U2, R223
Replace a datasheet: R223, U2
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[💡 Recommendation] Component
U2, pinJ15: U2 J15 is mislabeled IO_25_34 in the bank 35 section; rename it to IO_25_35.Observed: In the bank 35 symbol section (SEC 7), ball J15 is named IO_25_34. All other pins in that section, and the bank's VCCO_35 balls, are bank 35, and the bank 34 section already has its own IO_25_34 on T19.
Requirement: Symbol pin names need to identify the correct bank, so I/O standard and VCCO checks and constraint generation use the right bank.
Consequence: Mislabeling the bank can mislead pin planning or automated bank/VCCO checks for RXO_EA_RD_WAIT, which actually runs at the bank 35 2P5V level. Connectivity itself is not affected.
Evidence:
Suggested repair: Rename the U2 J15 symbol pin to IO_25_35 in the library.
Datasheet: U2
Replace a datasheet: U2
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[🚨 Error] Component
U23, pinsB5, B6: U23 RXI_NO_DATA5 pair (B5/B6) has no 100 Ω termination; add the missing R199.Observed: U23 has no 100 Ω differential termination on its north eLink receiver input pair RXI_NO_DATA_N5/P5 (B5/B6). In the whole design, the nets RXI_NO_DATA5_N and RXI_NO_DATA5_P reach only U23 and the PEC_NORTH connector J8 (pins 14 and 16), with no part between them. Every other RXI pair on this page has a 100 Ω resistor across it at the U23 pins: DATA0–4 use R194–R198, DATA6–7 use R200–R201, plus FRAME (R202) and LCLK (R203). The designator R199, which would fall in that sequence, does not exist in the design.
Requirement: The page notes mark these pairs as '100 Ohm Differential LVDS Signals'. The same receiver bank terminates every other incoming pair with 100 Ω at the receiver. A current-mode LVDS receiver input needs a differential termination matched to the line to set its voltage swing and absorb reflections.
Consequence: Without a termination, an LVDS driver on an expansion card sees an open line on bit 5. The swing is undefined and the edge reflects, so the receiver can corrupt north eLink data bit 5 and with it every north-link transaction.
Evidence:
Suggested repair: Add a 100 Ω 0402 resistor (the R199 slot, matching R194–R201) across RXI_NO_DATA5_P/N, placed at U23 B6/B5.
2 affected locations (one shared root cause)
U23, pins `B5, B6`; ComponentR198, pins `1, 2`; ComponentR200, pins `1, 2` (G002-F001)U23, pins `B5, B6` (G001-F001)Component
U23, pins `B5, B6`; ComponentR198, pins `1, 2`; ComponentR200, pins `1, 2`: North eLink RXI_NO_DATA5 pair at U23 B5/B6 has no 100 Ω termination; add R199 like the other lanes. (G002-F001)Observed: Of the eight north eLink receive data pairs at U23, RXI_NO_DATA5_P (U23.B6) and RXI_NO_DATA5_N (U23.B5) are the only ones with no 100 Ω resistor across them. Across the whole design, each of these two nets reaches only the off-page port, PEC_NORTH connector J8 (pins 16 and 14), and the U23 ball. The resistor numbering skips straight from R198 (DATA4) to R200 (DATA6), and R199 does not exist anywhere in the design. Every other north receive pair on this page has its own 100 Ω resistor between P and N: DATA0–4 and DATA6–7 (R194–R198, R200, R201), FRAME (R202) and LCLK (R203). The south DATA0–7 pairs (R207–R214) all have one too.
Requirement: The page marks these lanes as '100 Ohm Differential LVDS Signals', and DS01 for U23 describes the eLink as a source-synchronous LVDS DDR bus. The design applies an external 100 Ω differential termination at the U23 receiver on every other RXI data, frame and clock pair. That makes this termination a requirement for each lane of the byte-wide receive bus, so DATA5 needs it as well.
Consequence: When anything drives the PEC_NORTH eLink, the DATA5 lane reaches U23 without the 100 Ω load its LVDS driver expects. The swing will not be the intended one, and reflections on this high-speed DDR lane will be stronger than on the other seven. The result can be bit errors on that lane, which corrupt whole eLink transfers on the north port, since every transaction uses all eight data lanes.
Evidence:
Suggested repair: Add a 100 Ω 0402 resistor (designator R199, CRCW0402100RFKED like its neighbours) between RXI_NO_DATA5_P and RXI_NO_DATA5_N, placed at the U23 B5/B6 balls.
Datasheets: U23, R198
Replace a datasheet: R198, R200, U23
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[⚠️ Warning] Component
U23, pinsB7, B8, U7, U8, B11, B12; ComponentR242, pin2; ComponentR243, pin2; ComponentR246, pin2; ComponentR247, pin2; ComponentR240, pin1; ComponentR241, pin1: U23 eLink idle-bias networks (10 kΩ legs across 100 Ω) give only about 9 mV differential, below LVDS threshold.Observed: The idle-bias networks on the LVDS inputs RXI_NO_FRAME (B7/B8), RXI_SO_FRAME (U7/U8) and TXI_NO_RD_WAIT (B11/B12) each use 10 kΩ to 1P8V and 10 kΩ to GND, with the 100 Ω termination (R202, R215, R204) between the two legs. The resulting divider is 10 kΩ + 100 Ω + 10 kΩ across 1.8 V. That gives only about 1.8 V × 100/20100 ≈ 9 mV of differential bias at U23 when nothing drives the pair.
Requirement: A failsafe bias must hold the undriven differential input clearly beyond the receiver's switching threshold. A typical LVDS receiver threshold is ±100 mV, so 9 mV is about an order of magnitude too small.
Consequence: With no expansion card fitted, these inputs effectively float at about 9 mV differential. The receiver can toggle on noise, producing spurious FRAME on the north or south receivers, or chattering RD_WAIT on the north transmitter. The intended defined idle state is not guaranteed.
Evidence:
Suggested repair: Lower the bias resistors (for example, about 1 kΩ per leg gives about 85 mV, which is still marginal), or confirm that the E16G301 receiver has internal failsafe and drop the networks.
2 affected locations (one shared root cause)
R241, pins `1, 2`; ComponentR240, pins `1, 2`; ComponentR204, pins `1, 2` (G004-F002)U23, pins `B7, B8, U7, U8, B11, B12`; ComponentR242, pin `2`; ComponentR243, pin `2`; ComponentR246, pin `2`; ComponentR247, pin `2`; ComponentR240, pin `1`; ComponentR241, pin `1` (G001-F003)Component
R241, pins `1, 2`; ComponentR240, pins `1, 2`; ComponentR204, pins `1, 2`: R240/R241 10K bias gives only about 9 mV across R204, which is likely below the LVDS threshold; use smaller bias resistors. (G004-F002)Observed: The bias chain runs from 1P8V through R241 (10K) to TXI_NO_RD_WAIT_P, through R204 (100 Ω) to TXI_NO_RD_WAIT_N, and through R240 (10K) to GND. The series total is 20.1 kΩ. That gives about 89.6 µA at 1.8 V and only about 9 mV differential across R204, with the common mode near 0.9 V.
Requirement: A failsafe bias works only if the undriven differential voltage is above the receiver's input threshold. Standard LVDS (TIA/EIA-644) receivers guarantee a defined state only at |VID| ≥ 100 mV. No E16G301 receiver threshold is available here to show that a lower value is enough.
Consequence: With PEC_NORTH unmated, U23's north RD_WAIT receiver sees only about 9 mV of offset. That is within the threshold uncertainty of a typical LVDS receiver, so the intended idle state (wait asserted) is not guaranteed and the input can still float or chatter. The same bias topology on the FRAME pairs probably has the same margin problem.
Evidence:
Suggested repair: Lower the bias resistors (for example about 680 Ω–1 kΩ each with the 100 Ω termination gives roughly 80–120 mV), or confirm from the E16G301 datasheet that its receiver threshold or internal failsafe is enough at 9 mV.
Datasheets: U23, R241
Replace a datasheet: R204, R240, R241, R242, R243, R246, R247, U23
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[⚠️ Warning] Component
R205, pins1, 2; ComponentU23, pinsC10, C11: TXI_NO_WR_WAIT (R205) has no failsafe bias, so it floats when PEC_NORTH is empty; add 10K bias resistors.Observed: TXI_NO_WR_WAIT_P/N (U23 C11/C10) has only R205, a 100 Ω resistor across the pair. Nothing biases it to 1P8V or GND. Across the whole design the only other connection on each net is the PEC_NORTH connector, J8 pins 36 and 34. When no expansion card is fitted to J8, nothing drives these receiver inputs, and R205 holds them at about 0 V differential with a floating common mode. On the same page, the designer did bias the matching TXI_NO_RD_WAIT pair (R241 to 1P8V, R240 to GND) and the RXI_NO_FRAME and RXI_SO_FRAME pairs (R242/R243, R246/R247).
Requirement: An LVDS receiver input that can be left undriven needs a failsafe bias that sets a defined logic state. Otherwise the receiver output is undefined and can chatter. The page applies exactly this kind of 10K bias to the RD_WAIT and FRAME inputs that can also be left undriven.
Consequence: With no card on PEC_NORTH, the Epiphany north-link write-wait input sits at an undefined, noise-driven state. Write-wait can toggle at random, so traffic routed to the north link may stall or misbehave, and the receiver may chatter and draw extra current. North RD_WAIT is biased but WR_WAIT is not, so the two wait inputs of the same link idle in different, inconsistent states.
Evidence:
Suggested repair: Add a 10K bias on TXI_NO_WR_WAIT like the one on TXI_NO_RD_WAIT (P to 1P8V, N to GND, or the reverse if write-wait should idle deasserted), and size it to give a valid differential across R205 (see the bias-margin finding).
Datasheets: U23, R205
Replace a datasheet: R205, U23
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[⚠️ Warning] Component
U23, pinsR9, R10; ComponentR236, pins1, 2; ComponentR244, pin1; ComponentR245, pin1: U23 TXO_SO_FRAME output carries an installed 100 Ω source termination and bias (R236/R244/R245), unlike every other TXO pair.Observed: U23's south transmitter output pair TXO_SO_FRAME_P/N (R9/R10) has an installed 100 Ω resistor (R236) across it, plus a 10 kΩ pull-up to 1P8V on N (R244) and a 10 kΩ pull-down to GND on P (R245). The pair then runs to J9 pin 35. All other TXO pairs leave the source unterminated: TXO_NO data uses DNI R226–R233, TXO_NO_LCLK uses DNI R206, and TXO_NO_FRAME, TXO_SO data and TXO_SO_LCLK have no resistor. The matching north output TXO_NO_FRAME has neither termination nor bias.
Requirement: On a point-to-point LVDS link the single 100 Ω termination belongs at the receiver. This design follows that rule everywhere else: its outputs are unterminated or the termination is DNI, and its inputs carry 100 Ω. A transmitter output does not need failsafe bias.
Consequence: If the south expansion card terminates FRAME with 100 Ω at its receiver, as LVDS requires, U23's driver sees about 50 Ω. That roughly halves the FRAME swing, and the near-end resistor adds a reflection mismatch. FRAME is the only south output with reduced margin. The asymmetry with the north link suggests the RXI-style termination and bias was copied onto an output by mistake.
Evidence:
Suggested repair: Mark R236 DNI to match the other TXO pairs. Also remove R244/R245, unless an idle-state reason for biasing this output is documented.
2 affected locations (one shared root cause)
U23, pins `R9, R10`; ComponentR236, pins `1, 2`; ComponentR244, pin `1`; ComponentR245, pin `1` (G001-F002)R236, pins `1, 2`; ComponentU23, pins `R9, R10` (G008-F001)Component
R236, pins `1, 2`; ComponentU23, pins `R9, R10`: R236 adds an installed 100 Ω source-end termination on TXO_SO_FRAME; make it DNI like the other TXO pairs. (G008-F001)Observed: R236 is an installed 100 Ω resistor across TXO_SO_FRAME_P/N, right at the U23 transmitter outputs (R9/R10). The pair then runs out to J9 pins 35/33 (PEC_SOUTH). No other U23 transmitter output on this page has an installed termination. TXO_SO_DATA0-7 and TXO_SO_LCLK have none, and TXO_NO_FRAME has none. The north TXO_NO_DATA and TXO_NO_LCLK terminations (R226-R233, R206) are all marked DNI. This board puts its 100 Ω terminations at the receiving pins (RXI_* and TXI_*), for example R194-R216, R217 and R218.
Requirement: eLink is a source-synchronous LVDS link built to connect directly to other Epiphany chips or FPGAs. The board's own convention is a single 100 Ω termination at the receiver. FRAME is a timing-critical signal sent alongside DATA and LCLK, so it should be loaded the same way they are: no installed termination at the source.
Consequence: An expansion card that terminates its receiver with 100 Ω, as this board does for its own eLink inputs, would leave the U23 FRAME driver looking into about 50 Ω. That roughly halves the FRAME differential swing and changes its edge rate compared with the unterminated DATA and LCLK pairs, cutting receiver noise margin and adding FRAME-to-clock skew on the south eLink.
Evidence:
Suggested repair: Mark R236 as DNI to match the north TXO terminations (R206, R226-R233). Alternatively, document why a source-end termination is needed on FRAME only.
Datasheets: U23, R236
Replace a datasheet: R236, R244, R245, U23
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[💡 Recommendation] Component
C230, pin1; ComponentC231, pin1; ComponentU26, pins1, 11, 31, 51: Two of U26's four DVDD pins have only 10 nF local bypass; use 0.1 µF at each pin.Observed: HDMI_DVDD feeds four U26 DVDD pins: 1, 11, 31 and 51. None of these pins sit next to each other. The rail has only two 0.1 µF bypass capacitors (C58, C67) and two 10 nF capacitors (C230, C231), plus the 10 µF bulk capacitor C232. If each capacitor serves one pin, two of the pins get only 10 nF instead of 0.1 µF.
Requirement: The ADV7513 hardware guide says to place a 0.1 µF bypass capacitor to the ground plane as close as possible to each supply pin. Only adjacent power pins may share one.
Consequence: Two DVDD pins get one tenth of the recommended local capacitance. That leaves less high-frequency decoupling margin against the 64 mV RMS DVDD noise limit, and leans more heavily on the FB14 filter and the shared 1P8V rail.
Evidence:
Suggested repair: Change C230 and C231 to 0.1 µF, or add a 0.1 µF capacitor at each DVDD pin. Keep the 10 nF parts as extra high-frequency decoupling if wanted.
2 affected locations (one repeated pattern)
C144, pin `1`; ComponentC145, pin `1`; ComponentU26, pins `15, 19, 25` (G003-F002)C230, pin `1`; ComponentC231, pin `1`; ComponentU26, pins `1, 11, 31, 51` (G004-F001)Component
C144, pin `1`; ComponentC145, pin `1`; ComponentU26, pins `15, 19, 25`: HDMI_AVDD has two 0.1 µF bypasses for three non-adjacent AVDD pins; add one more. (G003-F002)Observed: HDMI_AVDD has three supply pins on U26: AVDD1 (pin 15), AVDD2 (pin 19) and AVDD3 (pin 25). None of them are adjacent: pins 16–18 sit between 15 and 19, and pins 20–24 sit between 19 and 25. The net has only two 0.1 µF capacitors (C144, C145), plus two 10 nF (C233, C234) and one 10 µF (C235).
Requirement: The guide asks for a 0.1 µF bypass capacitor to the ground plane as close as possible to each supply pin. Only adjacent power pins may share one.
Consequence: One AVDD pin has no 0.1 µF bypass of its own and depends on a 10 nF part or a capacitor at a neighbouring pin. This gives less mid-frequency decoupling for the TMDS output stage than the guide intends.
Evidence:
Suggested repair: Add a third 0.1 µF 0402 capacitor on HDMI_AVDD, so that pins 15, 19 and 25 each have one placed at the pin.
Datasheets: U26, C144, C230
Replace a datasheet: C144, C145, C230, C231, U26
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[💡 Recommendation] Component
C233, pins1, 2; ComponentC234, pins1, 2: C233/C234 10 nF part number is incomplete and its TDK catalog match is NRND; update to an active part.Observed: C233 and C234 list MFG_PART_NO C1005X7R1C103K with no packaging/thickness suffix and no DEVICE attribute. The matching TDK catalog entry, C1005X7R1C103K050BA, is marked Not Recommended for New Designs.
Requirement: BOM parts should resolve to one active, orderable part number.
Consequence: The part number is incomplete and the matching catalog item is NRND. This creates sourcing ambiguity and lifecycle risk for these 10 nF AVDD decoupling capacitors.
Evidence:
Suggested repair: Give the full TDK part number, or replace it with an active-status 0402 10 nF X7R part of 16 V or higher.
3 affected locations (one repeated pattern)
C233, pins `1, 2`; ComponentC234, pins `1, 2` (G003-F003)C265, pins `1, 2` (G005-F001)C266, pins `1, 2` (G006-F002)Component
C265, pins `1, 2`: C265 part number is truncated and maps to an NRND TDK part; specify a complete, active part. (G005-F001)Observed: C265 (10nF HDMI_PVDD bypass) has MFG_PART_NO and VENDOR_PN set to 'C1005X7R1C103K'. That number stops after the tolerance code and leaves out the thickness and packaging suffix. The TDK catalog entry that matches it, C1005X7R1C103K050BA, is marked Not Recommended for New Designs.
Requirement: The BOM part number must identify one orderable part that is still recommended for new production.
Consequence: The truncated number leaves the ordered variant ambiguous, and the variant that matches is NRND. This creates sourcing risk for the PLL-domain bypass capacitor (and for the other 10nF caps that use the same part number).
Evidence:
Suggested repair: Change the part number to a complete, active 0402 10nF X7R 16V (or higher) MLCC part number, including the thickness and packaging suffix.
Component
C266, pins `1, 2`: C266 part number is truncated and its matching TDK variant is NRND; specify an active full part number. (G006-F002)Observed: C266 is listed as TDK C1005X7R1C103K with no packaging or thickness suffix. The catalog entry that matches it, C1005X7R1C103K050BA, is printed in gray, meaning Not Recommended for New Designs.
Requirement: BOM part numbers should identify an orderable, active part.
Consequence: The truncated part number leaves the exact orderable variant ambiguous, and the matching catalog variant is NRND. This is a supply-continuity risk for the HDMI_BGVDD decoupling capacitor.
Evidence:
Suggested repair: Specify the full, active TDK part number (or an equivalent 0402 10 nF X7R ≥16 V capacitor) in the C266 metadata.
Datasheet: C233
Replace a datasheet: C233, C234, C265, C266
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[⚠️ Warning] Component
FB15, pins1, 2; ComponentC235, pin1; ComponentU26, pins15, 19, 25: FB15 ferrite bead stands in for the 10 µH AVDD filter inductor the ADV7513 guide calls for.Observed: HDMI_AVDD is fed from the 1P8V rail through one part, FB15 (Murata BLM15AG121SN1D, a 0402 ferrite bead rated 120 Ω at 100 MHz), into C235 (10 µF). The 10 µH inductor that the ADV7513 guide calls for is not there. The 1P8V rail is not a dedicated LDO output: it also reaches 11 other schematic pages.
Requirement: The ADV7513 hardware guide says to give the device its own 1.8 V LDO and to give each of the DVDD, AVDD and PVDD/BGVDD domains a 10 µH + 10 µF LC filter placed close to the chip. This removes noise above about 20 kHz. The AVDD noise limit in the specification table gives no number and refers back to this filtering section.
Consequence: With a bead in place of the 10 µH inductor, the corner frequency of the LC filter is much higher than the ~20 kHz the guide relies on. Noise from the shared 1P8V rail, from tens of kHz up to a few MHz, can pass into the TMDS output supply and add jitter or margin loss on the HDMI link. How bad this is depends on the noise on 1P8V, which this page does not show.
Evidence:
Suggested repair: Fit a 10 µH inductor rated for the AVDD current in FB15's position, as the guide recommends, or feed HDMI_AVDD from a dedicated low-noise 1.8 V LDO. Otherwise, confirm by measurement that the AVDD noise stays within the Section 7.1 limits.
2 affected locations (one repeated pattern)
FB15, pins `1, 2`; ComponentC235, pin `1`; ComponentU26, pins `15, 19, 25` (G003-F001)FB17, pins `1, 2`; ComponentC267, pin `1` (G006-F001)Component
FB17, pins `1, 2`; ComponentC267, pin `1`: FB17 bead filter on HDMI_BGVDD differs from the ADV7513 10 µH LC recommendation; check bandgap supply noise. (G006-F001)Observed: HDMI_BGVDD (U26 pin 13) is fed from the shared 1P8V rail through FB17, a Murata BLM15AG121SN1D ferrite bead rated 120 Ω at 100 MHz. C267 (10 µF), C266 (10 nF) and C263 (0.1 µF) filter the node. The page has no 10 µH inductor and no dedicated 1.8 V LDO. The 1P8V net also reaches 11 other schematic pages.
Requirement: The ADV7513 hardware guide says to power the device from its own 1.8 V LDO. Each supply domain, including PVDD/BGVDD, should get an LC filter of a 10 µH inductor and a 10 µF capacitor placed close to the chip, which suppresses noise above about 20 kHz. The noise limit on BGVdd is 64 mV RMS.
Consequence: A bead filter only works at high frequency, so it does not give the low-frequency (about 20 kHz and up) attenuation the guide's 10 µH LC network provides. Noise from loads elsewhere on the shared 1P8V rail can reach the bandgap reference and degrade TMDS output jitter or amplitude. The page does not show whether the 64 mV RMS BGVdd limit is met.
Evidence:
Suggested repair: Either put a 10 µH inductor (or a bead with equivalent low-frequency impedance) in the FB17 position, or confirm by measurement that HDMI_BGVDD noise stays well under 64 mV RMS with the shared 1P8V rail under load.
Datasheets: U26, FB15, C235
Replace a datasheet: C235, C267, FB15, FB17, U26
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[⚠️ Warning] Component
J10, pinsGND1, GND2, GND3, GND4: J10's metadata says SMT but 46765-1001 is the through-hole-shell variant; align the footprint and MPN.Observed: J10's CAD metadata calls the part surface-mount: DESCRIPTION 'CONN, HDMI, RCPT, MICRO D, RA, SMT', DEVICE/PART_NAME 'HDMI_MICRO_D_RA_SMT'. The ordered part number is 46765-1001.
Requirement: The Molex drawing lists 46765-1001 as the 'THRU HOLE TYPE+KAPTON TAPE' variant. Its four shell tails mount in plated slotted holes (1.50 x 2.55 mm), which an SMT-only land pattern would not provide.
Consequence: If the footprint follows the 'SMT' symbol, the through-hole shell legs of the ordered 46765-1001 have no plated slots. The part may not seat, or the shell may not be soldered to GND, which weakens mechanical retention and the shell ground path that the ESD scheme relies on. If the footprint was drawn for an SMT variant, the BOM part number is wrong.
Evidence:
Suggested repair: Confirm which variant is intended. Either keep 46765-1001 and make sure the footprint has the four plated shell slots and the keep-out, or change the MPN to the SMT-shell variant that matches the footprint.
Datasheet: J10
Replace a datasheet: J10
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[⚠️ Warning] Component
J10, pins17, 18; ComponentU37, pins8, 9: J10 DDC SCL/SDA have no ESD protection because U37's DDC channels serve the system I2C; add DDC clamps.Observed: J10 SCL (pin 17) and SDA (pin 18) connect directly to U26 DDCSCL/DDCSDA with no clamp of any kind. The TPD12S016 (U37) DDC-side ESD/level-shift pins SCL_B/SDA_B (pins 8/9) are wired to the system I2C_SCL/I2C_SDA bus instead. That bus also reaches U26's register port, connector J13 and U30 off-page. Of the connector's signal lines, only the DDC pair has no ESD clamp.
Requirement: The TPD12S016 datasheet assigns SCL_B and SDA_B to the HDMI connector's SCL and SDA pins, which are the B-side pins with IEC 61000-4-2 ±8 kV clamps. The ADV7513 example schematic places ESD protection between the device and the HDMI connector.
Consequence: ESD from a user-accessible Micro-HDMI receptacle on pins 17/18 goes straight into U26's DDC pins. That risks latent or hard damage to the ADV7513's EDID/HDCP master, while the rest of the connector is protected.
Evidence:
Suggested repair: Add low-capacitance ESD diodes on DDC_SCL/DDC_SDA next to J10, keeping the bus under the 50 pF DDC loading limit. Alternatively, move the DDC lines through a TPD12S016 B/A channel pair and give the system I2C bus its own translator.
3 affected locations (one shared root cause)
U26, pins `33, 34`; ComponentJ10, pins `17, 18`; ComponentU37, pins `8, 9` (G001-F004)U37, pins `8, 9`; ComponentJ10, pins `17, 18` (G007-F003)J10, pins `17, 18`; ComponentU37, pins `8, 9` (G008-F002)Component
U26, pins `33, 34`; ComponentJ10, pins `17, 18`; ComponentU37, pins `8, 9`: The U26 DDC lines reach J10 with no ESD protection; add clamps at the connector. (G001-F004)Observed: U26 DDCSCL/DDCSDA go straight to HDMI connector J10 SCL/SDA with no ESD clamp. U37 does have connector-side DDC channels (SCL_B/SDA_B, IEC 61000-4-2 rated), but they are on the internal 5 V I2C_SCL/I2C_SDA bus instead of the connector DDC pins.
Requirement: The TPD12S016 SCL_B/SDA_B pins are meant to connect to the HDMI connector SCL/SDA pins. The ADV7513 example schematic puts ESD protection between the device and the HDMI connector.
Consequence: Cable-side ESD on the DDC pins reaches the ADV7513 DDC pins directly, so a field ESD event could damage the transmitter.
Evidence:
Suggested repair: Add low-capacitance ESD clamps on DDC_SCL/DDC_SDA at J10, or reassign U37's B-side DDC channels to the connector.
Component
U37, pins `8, 9`; ComponentJ10, pins `17, 18`: HDMI DDC lines bypass U37; J10 SCL/SDA reach the ADV7513 with no ESD protection. (G007-F003)Observed: U37 SCL_B and SDA_B (pins 8 and 9) connect to the system I2C bus (I2C_SCL/I2C_SDA: U26 SCL/SDA, U30, J13), not to the HDMI connector. The connector DDC pins J10.17/J10.18 (DDC_SCL/DDC_SDA) connect directly to U26 DDCSCL/DDCSDA and the R19/R21 pull-ups. No ESD clamp sits on either DDC line.
Requirement: The TPD12S016 B-side DDC pins are meant to connect to the HDMI connector SCL/SDA pins, where they provide the IEC 61000-4-2 ±8 kV clamps. The ADV7513 example schematic places ESD protection between the device and the HDMI connector.
Consequence: Cable-side ESD on HDMI pins 17 and 18 goes straight into the ADV7513 DDC pins with no clamp, which risks field damage to U26. The TPD12S016 B-side clamps protect only the internal I2C bus.
Evidence:
Suggested repair: Either route DDC through a protection or level-shift device at the connector, or add low-capacitance ESD clamps on DDC_SCL/DDC_SDA at J10.
Datasheets: U26, J10, U37
Replace a datasheet: J10, U26, U37
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[🚨 Error] Component
J11, pins3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 17, 18, 19, 20, 23, 24, 25, 26, 27, 28, 29, 30: Bank 34 VCCO for J11 GPIO0–GPIO11 is on unsourced net VD_GPIO; tie it to VDD_GPIO.Observed: J11 brings out GPIO0_P/N through GPIO11_P/N, and all of them come from Zynq U2 bank 34. U2's bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) sit on a net named VD_GPIO, not VDD_GPIO. In the whole design, VD_GPIO holds only one port, the decoupling capacitors C126–C134 and those six VCCO pins. No regulator or other source drives it. VDD_GPIO, the rail on J11 pins 1 and 2, is fed by U30 VOLDO2 through R333 and only reaches bank 13's VCCO pins.
Requirement: An FPGA I/O bank only works when its VCCO pins are tied to a powered rail. The I/O voltage reference on J11 (VDD_GPIO) should also be the same rail that powers every bank brought out on J11.
Consequence: As drawn, bank 34 has no power. GPIO0–GPIO11 on J11 cannot drive or receive, and the HDMI data, sync and interrupt signals on the same bank also fail. If an expansion board drives these pins while VCCO is unpowered, current can flow back into the unpowered bank.
Evidence:
Suggested repair: Rename the VD_GPIO net or port to VDD_GPIO, or connect it to that rail, so that bank 34 VCCO shares the supply that J11 pins 1 and 2 provide.
3 affected locations (one shared root cause)
J11, pins `3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 17, 18, 19, 20, 23, 24, 25, 26, 27, 28, 29, 30` (G009-F001)U26, pins `53, 63, 2, 64, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 28`; ComponentR22, pins `1, 2` (G001-F001)U37, pins `2, 24` (G007-F002)Component
U26, pins `53, 63, 2, 64, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 52, 54, 28`; ComponentR22, pins `1, 2`: U26 video inputs and INT come from Zynq bank 34, whose VCCO net VD_GPIO has no supply. (G001-F001)Observed: Every video input of U26 (HDMI_CLK through R41, HDMI_DE through R94, HDMI_D8–D23, HSYNC, VSYNC) and its INT output (HDMI_INT, pulled up by R22 to VDD_GPIO) connect to Zynq U2 bank 34 I/O pins. The bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) sit on a net named VD_GPIO. That net carries only those VCCO pins and decoupling capacitors C126–C134, and no regulator output drives it. The design's GPIO rail is called VDD_GPIO and is fed from U30 LDO2 through R333.
Requirement: U26's video inputs need a CMOS driver at 1.8 V to 3.3 V (VIH min 1.35 V). Its open-drain INT must be pulled up to the host microcontroller's logic level and read by a powered input. An FPGA I/O bank can only drive or receive signals when its VCCO is supplied.
Consequence: With bank 34 unpowered, U26 gets no pixel clock, DE, sync, or data, so there is no HDMI video. R22 would also back-feed the unpowered bank through the P20 input clamp from VDD_GPIO.
Evidence:
Suggested repair: Join the bank 34 VCCO net to the intended rail, for example by renaming VD_GPIO to VDD_GPIO. Make sure that rail is within U26's 1.8–3.3 V input range and matches R22's pull-up rail.
Component
U37, pins `2, 24`: U37 SCL_A is driven from Zynq bank 34, whose VCCO net VD_GPIO has no supply source. (G007-F002)Observed: U37 references its A side to VCCA = VDD_GPIO (pin 24). SCL_A (pin 2) is driven by Zynq U2 pin N18 in bank 34. Bank 34's VCCO pins are on net VD_GPIO, not VDD_GPIO. VD_GPIO has only decoupling capacitors and a port, with no regulator or other source anywhere in the design. VDD_GPIO comes from U30 LDO2 through R333 and powers bank 13.
Requirement: U37's A-side signals are referenced to VCCA, which should be the same supply as the controller's I/O. The controller pin driving SCL_A needs a powered I/O bank at the VCCA level.
Consequence: The Zynq pin driving U37 SCL_A has no I/O supply, so it cannot drive the I2C clock. R20 and U37's internal 10k pull-up to VDD_GPIO back-feed the unpowered bank through its input structures. Together with the SDA break, the I2C path from the Zynq to the ADV7513 is unusable.
Evidence:
Suggested repair: Connect the Zynq bank 34 VCCO net to VDD_GPIO (VD_GPIO looks like a misspelling of VDD_GPIO), or move the controller I2C pins to a bank powered from VCCA.
Datasheets: U26, J11, U37, R22
Replace a datasheet: J11, R22, U26, U37
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[⚠️ Warning] Component
J11, pin25: J11 pin 25 (GPIO8_P) is the Zynq PUDC_B strap with a 1 kΩ pull-down; isolate or document it.Observed: J11 pin 25 (GPIO8_P) goes to U2 pin U13, which is the dual-purpose IO_L3P_T0_DQS_PUDC_B_34 pin. The same net has a permanent 1 kΩ pull-down (R223) to GND, so this expansion-connector pin is both the configuration pull-up control strap and a user I/O. It also has a 1 kΩ load that its pair partner GPIO8_N (J11 pin 23) does not have.
Requirement: PUDC_B sets the I/O pull-up behaviour during configuration, so it needs a defined level that nothing external overrides. A connector GPIO offered to users as a differential pair should not carry a strong, one-sided load.
Consequence: An expansion board that drives or pulls J11 pin 25 high during power-up can change the configuration pull-up state of U2's I/O. After configuration, the 1 kΩ to ground draws a few mA whenever the pin is high and makes the GPIO8 pair unbalanced, so it is a poor choice for differential use.
Evidence:
Suggested repair: Document J11 pin 25 as a strap-sensitive pin with a 1 kΩ pull-down. Alternatively, move PUDC_B off the expansion connector, or fit a series-isolated strap so the external connector cannot override it.
Datasheet: J11
Replace a datasheet: J11
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[⚠️ Warning] Component
R19, pins1, 2; ComponentR21, pins1, 2: DDC pull-ups R19/R21 are 4.75 kΩ, outside the ADV7513's required 1.5–2 kΩ; change them to about 2 kΩ.Observed: R19 (DDC_SCL to HDMI_5V) and R21 (DDC_SDA to HDMI_5V) are 4.75 kΩ 1% resistors (CRCW04024K75FKED). They are the only pull-ups on the page-local DDC_SCL and DDC_SDA nets, which run straight from U26 DDCSCL/DDCSDA (pins 33/34) to J10 SCL/SDA (pins 17/18). U37's 1.75 kΩ B-side pull-ups are not on these nets: its SCL_B/SDA_B pins go to I2C_SCL/I2C_SDA.
Requirement: The ADV7513 hardware guide says each DDC line needs a 1.5 kΩ to 2 kΩ (±10%) pull-up to HDMI +5 V. Its example schematic shows 2 kΩ pull-ups to +5 V on DDC_SDA and DDC_SCL.
Consequence: The source-side pull-up is about 2.4 times the recommended maximum, so the rising-edge RC time on the DDC bus is about 2.4 times longer. Once a cable and sink are attached, this reduces rise-time margin for EDID/HDCP reads and risks failing HDMI source DDC compliance.
Evidence:
Suggested repair: Change R19 and R21 to a value in the 1.5–2 kΩ range, for example 1.8 kΩ or 2.0 kΩ 1%, still tied to HDMI_5V.
2 affected locations (one shared root cause)
R19, pins `1, 2`; ComponentR21, pins `1, 2` (G008-F001)U26, pins `33, 34`; ComponentR19, pins `1, 2`; ComponentR21, pins `1, 2` (G001-F003)Component
U26, pins `33, 34`; ComponentR19, pins `1, 2`; ComponentR21, pins `1, 2`: The U26 DDC pull-ups R19/R21 are 4.75 kΩ; use 1.5–2 kΩ as the ADV7513 requires. (G001-F003)Observed: DDC_SCL and DDC_SDA run straight from U26 pins 33/34 to J10 pins 17/18. Their only pull-ups are R19 and R21, each 4.75 kΩ to HDMI_5V.
Requirement: Each DDC line needs a 1.5 kΩ to 2 kΩ (±10%) pull-up to HDMI +5 V.
Consequence: The pull-up is about 2.4 to 3.2 times weaker than specified, which slows DDC rise times with cable and sink capacitance. EDID/HDCP reads may fail or the port may fail HDMI source compliance on long or heavily loaded cables.
Evidence:
Suggested repair: Change R19 and R21 to a value between 1.5 kΩ and 2 kΩ, for example 1.8 kΩ.
Datasheets: U26, R19
Replace a datasheet: R19, R21, U26
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[⚠️ Warning] Component
U26, pins55, 56, 57, 58, 59, 60, 61, 62: Unused U26 inputs D0–D7 float under NC markers; tie them to GND as the datasheet requires.Observed: U26 video inputs D0–D7 (pins 55–62) have no net and carry no-connect markers, so these CMOS inputs float.
Requirement: Connect any unused input data signals to ground.
Consequence: Floating CMOS inputs can sit at mid-rail. That raises supply current, and nearby switching can couple noise into the input buffers.
Evidence:
Suggested repair: Tie D0–D7 to GND, individually or through a shared ground connection.
Datasheet: U26
Replace a datasheet: U26
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[🚨 Error] Component
U37, pin3: U37 SDA_A sits on PS_I2C_SDA, which has no controller; connect it to the Zynq SDA pin (net N9).Observed: U37 pin 3 (SDA_A) connects only to the PS_I2C_SDA port. No other page in the design uses PS_I2C_SDA, so SDA_A has no controller. SCL_A (pin 2) on PS_I2C_SCL does reach Zynq U2 pin N18, which has R20 (4.75k) pulling it up to VDD_GPIO. The matching Zynq pin U2 N17 sits on an unnamed net N9 that has only R18 (4.75k) pulling it up to VDD_GPIO, so it looks like the intended SDA line that never got the PS_I2C_SDA name.
Requirement: The TPD12S016 SDA_A pin is the HDMI-controller-side SDA pin and must connect to the I2C controller.
Consequence: The Zynq has no SDA path through U37 to the I2C_SDA bus. It therefore cannot configure the ADV7513 (U26) or talk to the ISL9305 PMIC (U30), and HDMI output cannot be brought up. SDA_A only idles high through its internal 10k pull-up.
Evidence:
Suggested repair: Join the Zynq SDA pin (U2 N17, net N9) to PS_I2C_SDA, for example by putting the PS_I2C_SDA port or net name on that net on the Zynq page.
2 affected locations (one shared root cause)
U26, pin `36`; ComponentU37, pins `3, 9` (G001-F002)U37, pin `3` (G007-F001)Component
U26, pin `36`; ComponentU37, pins `3, 9`: U26 SDA has no route to the processor because PS_I2C_SDA at U37 SDA_A is unconnected off-page. (G001-F002)Observed: U26 SDA (pin 36) is on I2C_SDA. That net goes to U37 SDA_B, U30 SDAT, R285 (10K to SYS_5P0V) and expansion connector J13 pin 4, with no Zynq pin on it. The level-shifted processor side, PS_I2C_SDA on U37 SDA_A, has no connection beyond U37 on any page. The matching PS_I2C_SCL does reach Zynq U2 N18.
Requirement: U26 has to be programmed over SDA/SCL by an I2C master (main map at 0x72 or 0x7A) before it outputs video.
Consequence: The on-board processor has no SDA path to U26 (or to the U30 PMIC on the same bus). It cannot configure the HDMI transmitter, so HDMI output does not work unless an external master is connected at J13.
Evidence:
Suggested repair: Connect PS_I2C_SDA to the intended Zynq I/O pin next to the PS_I2C_SCL pin on the Zynq page, or fix the net-name mismatch there.
Datasheets: U26, U37
Replace a datasheet: U26, U37
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[⚠️ Warning] Component
U37, pin1; ComponentU26, pin30: ADV7513 CEC VOL (0.6 V max) exceeds U37 CEC_A low threshold (about 0.19 V); CEC may not translate.Observed: U37 CEC_A (pin 1) shares HDMI_CEC with ADV7513 CEC (U26 pin 30). VCCA is VDD_GPIO, which is 2.9 V by default from U30 LDO2. For U37 to see a low, CEC_A must be pulled below VILC = 0.065×VCCA (about 0.19 V) or VIL = 0.082×VCCA (about 0.24 V). The ADV7513 only guarantees a CEC output low of 0.6 V maximum.
Requirement: A port-A driver must pull CEC_A below VILC/VIL (0.065/0.082 × VCCA). TI states that port A needs a low-impedance driver.
Consequence: If the ADV7513 CEC low lands anywhere in its guaranteed range above about 0.19–0.24 V, U37 may not pass it to CEC_B. CEC transmit from the ADV7513 to the HDMI bus could then fail or be intermittent.
Evidence:
Suggested repair: Confirm the ADV7513 CEC VOL at about 0.3 mA (10k pull-up to 2.9 V). If it cannot be guaranteed below 0.065×VCCA, drive CEC through a buffer that meets port-A levels, or use the ADV7513's recommended 27k/diode CEC network instead of the U37 CEC channel.
Datasheets: U26, U37
Replace a datasheet: U26, U37
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[⚠️ Warning] Component
C241, pin1; ComponentC253, pin1; ComponentC254, pin1; ComponentU29, pins1, 12, 5; ComponentU30, pins1, 12, 5, 8: SYS_5P0V has only three input capacitors shared by U29 and U30; give each converter its own input capacitors.Observed: SYS_5P0V feeds seven regulator input pins: U29 VINDCD1/VINDCD2/VINLDO and U30 VINDCD1/VINDCD2/VINLDO1/VINLDO2. Two 3 MHz, 1.5 A bucks and two 300 mA LDOs share that rail. Its only input capacitors are C241 (10 µF), C253 (10 µF) and C254 (1 µF), about 21 µF nominal in total. No other page puts bulk capacitance on SYS_5P0V. The only extra parts are 0.1 µF and 0.47 µF local decoupling capacitors (C52, C59, C258, C274, C279) on other pages. Those serve other ICs.
Requirement: For U29, the ISL9307 datasheet calls for a 10 µF input capacitor on VINDCD1 placed as close to the pin as possible, 10 µF on VINDCD2 in the block diagram (the part list says 1 µF) and 1 µF on VINLDO. For U30, the ISL9305H datasheet calls for 10 µF on each of VINDCD1 and VINDCD2 and 1 µF on each of VINLDO1 and VINLDO2. Across both converters that is about 6 to 7 dedicated, pin-local capacitors and roughly 33 to 43 µF.
Consequence: With three capacitors spread over seven input pins on two separate ICs, at least one converter's buck input pins have no dedicated low-impedance capacitor nearby. That makes the high-di/dt input loop larger and can raise input ripple at 3 MHz, along with switching noise, EMI and the risk of UVLO or PG glitches during load transients. The 16 V X5R 10 µF parts also lose some capacitance at 5 V DC bias, which cuts the margin further.
Evidence:
Suggested repair: Give each converter its own input capacitors next to its pins. At minimum, add a 10 µF capacitor at each VINDCD1/VINDCD2 pair and 1 µF at each LDO input, so that U29 and U30 each have their own set.
2 affected locations (one shared root cause)
C241, pin `1`; ComponentC253, pin `1`; ComponentC254, pin `1`; ComponentU29, pins `1, 12, 5`; ComponentU30, pins `1, 12, 5, 8` (G005-F001)U30, pins `1, 12`; ComponentC241, pin `1`; ComponentC253, pin `1` (G006-F003)Component
U30, pins `1, 12`; ComponentC241, pin `1`; ComponentC253, pin `1`: U30 VINDCD1/VINDCD2 have no dedicated 10 µF input capacitors; add one per buck input. (G006-F003)Observed: Across the whole design, SYS_5P0V has only two 10 µF bulk capacitors, C241 and C253, plus one 1 µF (C254), all on this page. The other SYS_5P0V capacitors are 0.47 µF and 0.1 µF parts on other pages. Those two 10 µF parts are shared by four 3 MHz buck inputs: U29 VINDCD1/VINDCD2 and U30 VINDCD1/VINDCD2. Neither of U30's buck inputs has its own 10 µF capacitor.
Requirement: The ISL9305 recommended external components call for a 10 µF input capacitor on each of VINDCD1 and VINDCD2, and 1 µF on each LDO input.
Consequence: With only two 10 µF capacitors shared across four high-frequency buck inputs, U30's input ripple and switching-current loops may not be bypassed as the datasheet intends. The capacitors are also 0805 X5R parts biased at 5 V, which lowers their effective capacitance. This risks input ripple, noise coupling, and degraded regulation on U30's DCD outputs. How much depends on placement, which the schematic does not show.
Evidence:
Suggested repair: Add a dedicated 10 µF capacitor at U30 VINDCD1 and another at VINDCD2, plus 1 µF at VINLDO1/VINLDO2, each placed at its pin.
Datasheets: C241, U30, U29, C254
Replace a datasheet: C241, C253, C254, U29, U30
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[⚠️ Warning] Component
C242, pins1, 2: C242 is labelled 0.047 µF but its MPN is a 0.1 µF part; align the BOM fields.Observed: C242's VALUE, DESCRIPTION, DEVICE and PART_NAME all say 0.047 µF X5R 25V. Its MFG_PART_NO and VENDOR_PN are C1005X7R1H104K050BB, which is a 100 nF X7R 50 V part. C244, the matching feed-forward capacitor on DCD2, carries a 47 nF part number (C1005X5R1E473M).
Requirement: The part number used to buy the part must match the value the design specifies, especially for a feed-forward capacitor across the feedback divider, where its value sets a compensation zero and pole.
Consequence: Which part gets built is ambiguous. If assembled from the MPN, the feed-forward capacitance across R2+R5 (24.75 kΩ) roughly doubles. That moves the zero from about 137 Hz to about 64 Hz, so DCD1's loop response would differ from DCD2's and from what was intended.
Evidence:
Suggested repair: Change C242's MPN to a 47 nF 0402 part, such as the C1005X5R1E473M used for C244, or change the value fields if 100 nF was intended.
Datasheet: C242
Replace a datasheet: C242
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[💡 Recommendation] Component
C244, pins1, 2: C244's part number is truncated and resolves to an NRND TDK part; specify a complete, active MPN.Observed: C244's MFG_PART_NO and VENDOR_PN are 'C1005X5R1E473M', which leaves off the thickness and packaging suffix. The resolved catalog part, C1005X5R1E473M050BA, is shown as Not Recommended for New Designs.
Requirement: BOM part numbers should identify one orderable, active part.
Consequence: Procurement may be ambiguous because the suffix that sets thickness and packaging is missing, and supply of an NRND part may be limited in production.
Evidence:
Suggested repair: Specify a complete, active TDK part number (or an equivalent 47 nF 0402 X5R/X7R rated ≥25 V).
Datasheet: C244
Replace a datasheet: C244
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[🚨 Error] Component
CR8, pins1, 2; ComponentU30, pin10; ComponentR288, pin1: CR8 is reverse-biased (anode on GND), so the power-good LED can never light; swap its orientation.Observed: CR8's anode (pin 2, A) goes to GND. Its cathode (pin 1, C) goes to N23098459, which also connects to U30 DCDPG (pin 10) and R288, a 620 Ω pull-up to SYS_5P0V. When DCDPG releases high (power good), the cathode sits about 5 V above the anode, so the LED is reverse-biased. When DCDPG pulls low, both LED terminals are near 0 V. CR8 can never be forward-biased.
Requirement: The page note says 'Power Good = LED ON / Power Bad = LED OFF'. To get that with an open-drain PG output and a pull-up, the LED anode must go on the pulled-up DCDPG node and the cathode on GND. The LED datasheet says to put the cathode on the lower-potential side.
Consequence: The power-good indicator never lights, so it cannot show U30's DCD status. While power is good, CR8 also has about 5 V of reverse bias across it. The datasheet provided gives no reverse-voltage rating to check that against.
Evidence:
Suggested repair: Swap CR8's connections so the anode goes to N23098459 and the cathode to GND. Also check that the symbol pin numbers match the footprint polarity. With the LED corrected, power good drives about (5 − 1.9)/620 ≈ 5 mA through CR8, which matches its 5 mA rating.
Datasheets: CR8, U30, R288
Replace a datasheet: CR8, R288, U30
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[⚠️ Warning] Component
F1, pins1, 2: F1 4 A fuse may run above its 70 % derating at the noted SYS_5P0V load budget.Observed: F1 (ERB-RE4R00V, 4 A rated) is the only fuse between J12/5P0V_IN and 5P0V. With J14 jumpered 1-2, 5P0V feeds SYS_5P0V. On this page, SYS_5P0V supplies U29 and U30: four bucks noted at 1.5 A max each (1 V, 1.8 V, 0.9–1.1 V and 1.35–1.5 V) and four LDOs noted at 300 mA max each. Off this page, SYS_5P0V also feeds U13 (USB PWR DIST IN), J13 pins 1/2 (BSH-030 connector), U37 and U12. Assuming about 85 % buck efficiency, the noted page maxima alone draw roughly 1.9 A for the bucks plus 1.2 A for the LDOs, about 3.1 A from 5 V. That is before any USB-host or J13 load.
Requirement: The ERB-RE4R00V datasheet says normal operating current should be 70 % or less of rated current. For this 4 A part that is 2.8 A.
Consequence: If the noted rail maxima and the USB/expansion loads occur together, F1 runs above its recommended 70 % derating. Under heat or inrush it can age or nuisance-open, which removes board power.
Evidence:
Suggested repair: Confirm the worst-case SYS_5P0V current from the barrel input. If it can exceed about 2.8 A, change F1 to a higher-rated fuse (for example 5–6 A, 32 V) or budget-limit the downstream loads.
Datasheet: F1
Replace a datasheet: F1
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[⚠️ Warning] Component
J14, pin2: J14 pin 2 carries the whole SYS_5P0V load through one 3 A header contact.Observed: J14 pin 2 is the only path into SYS_5P0V from either source (pin 1 = 5P0V, pin 3 = USB_VBUS). So the whole SYS_5P0V load passes through one header contact and its jumper shunt. The page note says '3A PER PIN'. The noted regulator maxima alone come to about 3.1 A at 5 V, before the U13 USB-host and J13 expansion loads on other pages.
Requirement: The PBC36SAAN datasheet rates each contact at 3 A, which matches the '3A PER PIN' note on this page.
Consequence: At the noted worst-case budget, J14 pin 2 and its shunt run at or above their 3 A rating. This risks contact heating, voltage drop on SYS_5P0V and long-term contact degradation.
Evidence:
Suggested repair: Confirm the worst-case SYS_5P0V current. If it can reach 3 A, use a higher-current selection method (for example parallel pin pairs, a higher-rated jumper or a solder/0 Ω link) or reduce the load budget.
Datasheet: J14
Replace a datasheet: J14
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[⚠️ Warning] Component
L8, pins1, 2: L8 thermal rating of 1.45 A is below the 1.5 A load stated for 1P0V; use a higher-current inductor.Observed: L8 is a TDK VLS252012ET-1R5N carrying a symbol attribute CURRENT=2A. It is the DCD1 inductor for a rail the page labels '1V @ 1.5A max'. At 5 V in, 1.0 V out, 1.5 µH and 3 MHz, the computed ripple is about 0.18 A p-p, so the peak current is about 1.59 A.
Requirement: For this part the rated current is the smaller of Idc1 (1.80 A max, 2.00 A typ) and Idc2 (1.45 A typ, set by a 40 °C self-heating rise). The ISL9307 reference design uses a 1.80 A rated 1.5 µH inductor for a 1500 mA output. Its P-MOSFET peak current limit is 2.1 to 2.75 A.
Consequence: At the stated 1.5 A full load, the RMS current is above the 1.45 A thermal rating, so the inductor heats more than 40 °C. Overload up to the converter's 2.1 to 2.75 A current limit goes beyond Idc1, and inductance drops by more than 30%. The 2A attribute overstates the part's rating.
Evidence:
Suggested repair: Use a 1.5 µH inductor rated at least 2 A for thermal rise and about 2.75 A for saturation, or confirm the real ZYNQ VCCINT load stays well below 1.45 A. Correct the CURRENT attribute either way.
4 affected locations (one repeated pattern)
L8, pins `1, 2` (G003-F002)L9, pins `1, 2` (G004-F002)L10, pins `1, 2` (G007-F002)L11, pins `1, 2` (G007-F001)Component
L9, pins `1, 2`: L9 is rated 1.45 A, not the 2 A in its attributes, which is below the 1.5 A rail maximum; use a higher-current inductor. (G004-F002)Observed: L9 is a TDK VLS252012ET-1R5N carrying the DCD2 output. Its attributes give CURRENT: 2A and DESCRIPTION 'IND, 1.5uH, 2A', and the page note specifies the rail as '1.8V @ 1.5A max'. With 5 V in, 1.8 V out, 3 MHz and 1.5 µH, ripple is about 0.26 A p-p, so the inductor sees about 1.5 A DC and about 1.63 A peak at full load. U29's P-MOSFET current limit is 2.1–2.75 A.
Requirement: The inductor rated current is the smaller of Idc1 and Idc2. For VLS252012ET-1R5N, Idc1 (30% inductance drop) is 1.80 A max and Idc2 (40 °C self-heating rise) is 1.45 A typ. Peak current must stay within the rated current.
Consequence: At the stated 1.5 A maximum load, L9 runs above its 1.45 A thermal rating and close to its saturation rating. During overload or start-up the IC's current limit (≥2.1 A) is above Idc1, so the inductor can saturate before the limit trips. The 2A schematic attribute overstates the part's rating and hides this lack of margin.
Evidence:
Suggested repair: Use a 1.5 µH inductor rated for at least about 2.75 A saturation and about 1.6 A thermal, or confirm that the real 1P8V load is well below 1.45 A. Correct the CURRENT/DESCRIPTION attributes to match the chosen part.
Component
L10, pins `1, 2`: L10 rated current of 1.45 A is below the 1.5 A 1P35V load plus ripple; upsize the inductor. (G007-F002)Observed: L10 (TDK VLS252012ET-1R5N, 1.5 µH) is the DCD2 inductor between U30 SW2 (N22955745) and the 1P35V output node N22955725. The page note gives this rail as '1.5V to 1.35V @ 1.5A max'. The attributes say CURRENT=2A, but the datasheet rated current is 1.45 A typ (Idc2), with Idc1 at 1.80 A max. Ripple at 5 V in, 3 MHz is about 0.22 A at 1.35 V out and 0.23 A at 1.5 V out, so the peak is about 1.6 A at full load.
Requirement: Per the VLS252012E datasheet, rated current is the smaller of Idc1 and Idc2, and peak current must stay within it. U30 DCD2 is specified for 1.5 A, with a current limit of 2.1 A minimum.
Consequence: At the stated DDR3 load, L10 runs above its 1.45 A thermal rating, with inductance roll-off as the current approaches 1.8 A. The likely results are overheating and degraded regulation on the DDR3/Zynq bank 502 supply.
Evidence:
Suggested repair: Use a 1.5 µH inductor rated for at least the 2.1 A converter current limit, or confirm that the DDR3 rail load stays well below 1.45 A. Correct the CURRENT attribute.
Component
L11, pins `1, 2`: L11 rated current of 1.45 A is below the 1.5 A VDD_DSP load plus ripple; upsize the inductor. (G007-F001)Observed: L11 (TDK VLS252012ET-1R5N, 1.5 µH) is the DCD1 inductor between U30 SW1 (N22955797) and the VDD_DSP output node N22955654. The page note gives this rail as '0.9V TO 1.1V @ 1.5A max'. The part's CURRENT attribute and description say 2A. The datasheet rated current for this part number is 1.45 A typ (Idc2, the 40 °C self-heating limit), and Idc1 is 1.80 A max. At about 5 V in, 1.1 V out and 3 MHz, ripple is about 0.19 A peak-to-peak, so the inductor peak is about 1.6 A at full load.
Requirement: Per the VLS252012E datasheet, rated current is the smaller of Idc1 and Idc2, and peak current must stay within it. U30 DCD1 is specified to deliver 1.5 A, and its P-MOSFET current limit is 2.1 A minimum.
Consequence: At the stated 1.5 A load, L11 runs above its 1.45 A thermal rating and close to its 1.8 A saturation point. Expect excess self-heating (more than 40 °C rise), loss of inductance, higher ripple and reduced efficiency on the DSP core rail. The 2A attribute overstates the part's capability.
Evidence:
Suggested repair: Use an inductor with Isat and Irms of at least 2.1 A, at or above U30's current limit, in a compatible footprint. Otherwise, document and enforce a VDD_DSP load limit well below 1.45 A. Correct the CURRENT attribute either way.
Datasheet: L8
Replace a datasheet: L10, L11, L8, L9
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[🚨 Error] Component
U29, pin15: U29 GNDDCD1 (pin 15) is unconnected; tie it to GND.Observed: U29 pin 15 (GNDDCD1) has no net on this page, and the design lookup also shows it as '(unconnected)'. The other grounds are connected: GNDDCD2 (14), GNDLDO (9) and EPAD (17) are all on GND.
Requirement: The ISL9307 datasheet calls pin 15 the power ground for DCD1. The typical application connects GNDDCD1, GNDDCD2 and GNDLDO all to ground. The layout guidance treats SW, inductor, output capacitor and PGND as the DCD1 power loop.
Consequence: The DCD1 low-side switch and its return current have no designed path to ground. DCD1 makes the 1P0V (ZYNQ) rail, rated 1.5 A on the page. As drawn, its return current would have to flow through internal substrate or EPAD paths, which the datasheet does not specify. The likely results are improper regulation, high stress on the device, or a failed 1P0V rail.
Evidence:
Suggested repair: Connect U29 pin 15 to GND with a short, wide connection to the DCD1 output and input capacitor grounds.
2 affected locations (one shared root cause)
U29, pin `15`; ComponentL8, pin `1` (G003-F001)U29, pin `15` (G002-F001)Component
U29, pin `15`; ComponentL8, pin `1`: U29 GNDDCD1 (pin 15) is unconnected, so the 1P0V buck has no power ground; tie it to GND. (G003-F001)Observed: U29 pin 15 (GNDDCD1), the power ground for buck DCD1, has no net. The design lookup shows it as unconnected. DCD1 is the converter that drives SW1 into L8.1 to make the 1P0V rail. U30's equivalent pin 15 is tied to GND.
Requirement: The ISL9307 datasheet calls GNDDCD1 the power ground for DCD1 and shows GNDDCD1, GNDDCD2 and GNDLDO all going to ground. Its layout guidance has the SW/PGND power loop kept small and direct.
Consequence: DCD1's low-side switch current has no designed return path. If the netlist is used as drawn, the 1P0V buck that feeds ZYNQ may not regulate, or may only work through an unspecified internal path, at up to 1.5 A.
Evidence:
Suggested repair: Connect U29 pin 15 (GNDDCD1) to GND, keeping the return close to the C243 and input-capacitor grounds.
Datasheets: L8, U29
Replace a datasheet: L8, U29
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[🚨 Error] Component
R282, pins1, 2; ComponentR281, pins1, 2: The R282/R281 feedback divider sets U29 DCD2 to about 0.94 V instead of 1.8 V; change R282 to about 71.5K.Observed: R282 (10K, CRCW040210K0FKED) runs from the DCD2 output node N25830712 (L9.2, C245.1, R287.1) to FB2 net N25830704. R281 (56.2K) runs from FB2 to GND. U29 pin 11 (FB2) is on N25830704. With VFB = 0.8 V, the setpoint is 0.8 × (1 + 10/56.2) ≈ 0.94 V, not the 1.8 V shown by the page note '1.8V @ 1.5A max' and the 1P8V net name. For comparison, the DCD1 divider (R2 20K + R5 4.75K over R279 100K) gives about 1.0 V, which matches its 1P0V label, so the same formula holds on this page.
Requirement: For the adjustable ISL9307IRTAANFZ-T, Vout = VFB × (1 + Rtop/Rbottom), with VFB 0.785/0.8/0.815 V min/typ/max. A 1.8 V output needs Rtop/Rbottom ≈ 1.25.
Consequence: The 1P8V rail regulates to about 0.92–0.96 V. The Zynq VCCAUX/VCCPAUX and every other 1.8 V load on the 11 external pages would be badly undervolted, so the board would not boot or work.
Evidence:
Suggested repair: Change the divider ratio to about 1.25. For example, keep R281 at 56.2K and change R282 to 71.5K 1%, which gives about 1.82 V nominal, then recheck the C244 feed-forward value against the new top resistor.
2 affected locations (one shared root cause)
R282, pins `1, 2`; ComponentR281, pins `1, 2` (G004-F001)U29, pin `11`; ComponentR282, pins `1, 2`; ComponentR281, pins `1, 2` (G002-F002)Component
U29, pin `11`; ComponentR282, pins `1, 2`; ComponentR281, pins `1, 2`: The U29 DCD2 divider (R282 10K over R281 56.2K) sets about 0.94 V, not 1.8 V; increase R282. (G002-F002)Observed: The DCD2 feedback divider has R282 = 10K from the output (N25830712) to FB2 and R281 = 56.2K from FB2 to GND. That sets VOUT = 0.8 V × (1 + 10/56.2) ≈ 0.94 V. Through R287 (0 Ω) this output drives the 1P8V net, and the page note reads '1.8V @ 1.5A max'.
Requirement: On this adjustable variant (ISL9307IRTAANFZ-T), the buck output is set by an external divider around VFB = 0.8 V typ (0.785–0.815 V). A 1.8 V output needs Rtop/Rbottom = 1.25, i.e. about 70.3K over 56.2K.
Consequence: The 1P8V rail regulates at about 0.92–0.96 V instead of 1.8 V. Every 1.8 V load across the design would be badly under-powered and would not work.
Evidence:
Suggested repair: Change R282 to about 71.5K 1% (with R281 = 56.2K this gives about 1.82 V), or re-scale the divider for 1.8 V. Recheck the feed-forward capacitor C244 after the change.
Datasheets: U29, R282
Replace a datasheet: R281, R282, U29
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[⚠️ Warning] Component
R286, pins1, 2: R286 0402 jumper carries the 1.5 A 1P0V load at its 1.5 A limit; upsize it or bypass it.Observed: R286 is a 0402 0 Ω jumper (CRCW04020000Z0ED) that carries the whole 1P0V load from the DCD1 output node to the 1P0V port. The page labels that load '1V @ 1.5A max'. Feedback is sensed on N22939905, upstream of R286.
Requirement: The CRCW0402 jumper is rated 1.5 A maximum current and up to 20 mΩ resistance.
Consequence: At the stated maximum load the jumper runs at its absolute current limit with no margin. It also adds up to 30 mV of unregulated drop after the feedback sense point, which is 3% of the 1.0 V rail.
Evidence:
Suggested repair: Use a larger jumper (0603 is rated 2 A) or parallel jumpers, or move the feedback sense point to the 1P0V side of R286.
4 affected locations (one repeated pattern)
R286, pins `1, 2` (G003-F004)R287, pins `1, 2` (G004-F003)R330, pins `1, 2` (G007-F003)R331, pins `1, 2` (G007-F004)Component
R287, pins `1, 2`: R287, a 0402 jumper rated 1.5 A, carries the full 1.5 A 1P8V rail with no margin; upsize it. (G004-F003)Observed: R287 is a CRCW04020000Z0ED 0402 zero-ohm jumper and the only series link from the DCD2 output node N25830712 to the 1P8V rail. The page note specifies the rail at '1.8V @ 1.5A max'.
Requirement: The CRCW0402 jumper maximum current (Imax) is 1.5 A, listed as an absolute maximum.
Consequence: At the rail's stated full load, the jumper runs at its absolute-maximum current with no margin, which risks overheating or drift in the jumper and its joints if the load reaches or briefly exceeds 1.5 A.
Evidence:
Suggested repair: Use a larger jumper (0603/0805, with a higher Imax) or two 0402 jumpers in parallel, or confirm that the real 1P8V load stays well below 1.5 A.
Component
R330, pins `1, 2`: R330 0402 jumper is rated 1.5 A max, equal to the VDD_DSP full load; use a larger jumper. (G007-F003)Observed: R330 is a CRCW04020000Z0ED 0402 zero-ohm jumper that carries the entire DCD1 output from N22955654 to VDD_DSP. The page note gives VDD_DSP a 1.5 A maximum. U30 FB1 senses on N22955654, upstream of R330.
Requirement: The CRCW0402 jumper has an absolute-maximum current of 1.5 A and a resistance of up to 20 mΩ.
Consequence: At the stated full load, R330 runs at its absolute-maximum current with no margin. Its drop of up to 30 mV at 1.5 A is also outside the FB1 regulation loop, which is about 3% of a 0.9–1.1 V core rail.
Evidence:
Suggested repair: Use a larger jumper (0603 or bigger, with a higher Imax) or parallel jumpers. Alternatively, move the FB1 sense point downstream of the jumper.
Component
R331, pins `1, 2`: R331 0402 jumper is rated 1.5 A max, equal to the 1P35V full load; use a larger jumper. (G007-F004)Observed: R331 is a CRCW04020000Z0ED 0402 zero-ohm jumper that carries the entire DCD2 output from N22955725 to 1P35V. The page note gives 1P35V a 1.5 A maximum. U30 FB2 senses upstream of R331.
Requirement: The CRCW0402 jumper has an absolute-maximum current of 1.5 A and a resistance of up to 20 mΩ.
Consequence: At the stated full DDR3 load, R331 operates at its absolute-maximum current with zero margin. Its drop of up to 30 mV is not corrected by the regulator.
Evidence:
Suggested repair: Use a higher-current jumper (larger case size) or parallel jumpers, or sense FB2 after the jumper.
Datasheet: R286
Replace a datasheet: R286, R287, R330, R331
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[⚠️ Warning] Component
R293, pin1; ComponentR329, pin1; ComponentU29, pins5, 6, 7: U29 LDOs drop 5V to 3.3V and 2.5V at up to 300mA each, about 1.26W in one package.Observed: Both U29 LDOs run straight from SYS_5P0V (VINLDO pin 5). LDO1 (VOLDO1, then R293 to 3P3V) is labelled 3.3V @ 300mA max. LDO2 (VOLDO2, then R329 to 2P5V) is labelled 2.5V @ 300mA max. At those currents the LDOs dissipate about (5 − 3.3) × 0.3 = 0.51 W plus (5 − 2.5) × 0.3 = 0.75 W, about 1.26 W in total. That is on top of the losses from the two 1.5 A buck converters in the same package.
Requirement: U29 θJA is 40.2 °C/W typical, and that figure assumes a high-conductivity test board. The recommended junction temperature limit is 125 °C, and thermal shutdown is at 155 °C typical.
Consequence: The LDOs alone raise the junction about 51 °C above ambient, even on the datasheet's best-case board. Add the buck losses and high ambient, and the junction can pass the 125 °C recommended limit or trip thermal shutdown. A shutdown would drop the 3P3V and 2P5V rails as well as the 1V and 1.8V rails.
Evidence:
Suggested repair: Feed VINLDO from a lower rail, such as one of the buck outputs when the headroom allows. Otherwise, confirm that the real 3P3V and 2P5V load currents and the board's thermal design keep TJ under 125 °C.
Datasheets: U29, R293
Replace a datasheet: R293, R329, U29
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[⚠️ Warning] Component
U30, pins16, 2: U30 DCD1 powers up at 1.2 V on VDD_DSP, above the 0.9–1.1 V range noted on the page.Observed: U30 is the fixed-output ISL9305IRTHWBNLZ-T. FB1 is tied directly to the DCD1 output (N22955654), which feeds VDD_DSP through 0 Ω R330. The page labels that rail '0.9V TO 1.1V @ 1.5A max'. DCD1's factory fuse default is 1.2 V, and only an I2C write can change it.
Requirement: From power-up, before any I2C reprogramming, the DCD1 output should stay within the annotated VDD_DSP range of 0.9–1.1 V.
Consequence: From power-up until host firmware reprograms U30 over I2C, VDD_DSP sits at about 1.2 V (up to about 1.24 V at +3%). That is above the 0.9–1.1 V range annotated for the DSP rail. If the DSP's limits match the note, it is overstressed at every boot and whenever firmware does not configure U30.
Evidence:
Suggested repair: Check the DSP's maximum core voltage. If 1.2 V is not allowed, choose an ISL9305 variant whose DCD1 default is in range, or hold VDD_DSP off until it is programmed.
Datasheet: U30
Replace a datasheet: U30
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[🚨 Error] Component
J13, pins9, 25: Bank 34 VCCO is on VD_GPIO, which has no supply, so J13 PROG_IO and TURBO_MODE are dead; rename it to VDD_GPIO.Observed: J13 pin 9 (PROG_IO) goes to U2 N20 (IO_L14P_T2_SRCC_34) and J13 pin 25 (TURBO_MODE) goes to U2 R16 (IO_L19P_T3_34). Both are bank 34 I/Os. All six bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) sit on a net called VD_GPIO. Across the whole design, that net has only those six pins, nine decoupling capacitors (C126–C134) and one port. It has no regulator, connector or other supply. The connector rail on J13 pins 55/56 and the bank 13 VCCO pins use a differently spelled net, VDD_GPIO. The TURBO_MODE pull-up R328 also goes to VDD_GPIO.
Requirement: An FPGA I/O bank's VCCO pins have to be tied to a powered supply rail, or the bank's I/Os cannot drive or receive signals. The I/Os that J13 routes to that bank depend on the bank being powered.
Consequence: As the netlist stands, bank 34 has no power. PROG_IO and TURBO_MODE on J13, plus the other bank 34 signals (HDMI data, GPIO pairs), will not work. A TURBO_MODE signal pulled up to VDD_GPIO would also back-feed into an unpowered bank through its I/O clamp structures.
Evidence:
Suggested repair: Rename the VD_GPIO port and net on the bank 34 page to VDD_GPIO, or wire it to whatever rail is intended for bank 34.
Datasheet: J13
Replace a datasheet: J13
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[🚨 Error] Component
R96, pins1, 2: R96 is drawn as 0 Ω but its MPN is a 10 kΩ part; change the MPN to the 0 Ω jumper.Observed: R96 sits in series between U34 RST_L (N25161882) and PS_POR_L. Its VALUE (0), DEVICE (RES0402_0) and DESCRIPTION ("RES, 0402, 0 OHM, 1%") all say it is a 0 Ω jumper. Its MFG_PART_NO and VENDOR_PN are both CRCW040210K0FKED, a 10 kΩ resistor. The other 0 Ω jumpers on this page (R95, R98) carry CRCW04020000Z0ED.
Requirement: A part's ordering part number has to match its schematic value. Here PS_POR_L must reach a valid logic low when U34 asserts RST. U33 /OE is on PS_POR_L, and its VIL max at VCC = 3.3 V is 0.3·VCC (0.99 V).
Consequence: If parts are bought by MPN, a 10 kΩ resistor goes into the R96 position. When U34 pulls RST low, PS_POR_L then becomes a divider: 10 kΩ (R96) to ground against 10 kΩ (R326) to 3P3V, about 1.65 V. That is above U33's 0.99 V VIL, so BOARD_RESET_L would not reliably assert. The same marginal level also drives the Zynq PS_POR_B, so power-on, undervoltage and push-button resets could fail.
Evidence:
Suggested repair: Change R96's MFG_PART_NO and VENDOR_PN to the 0 Ω jumper CRCW04020000Z0ED, matching R95 and R98.
3 affected locations (one shared root cause)
R96, pins `1, 2` (G002-F001)U34, pin `8`; ComponentR96, pins `1, 2`; ComponentR326, pin `1` (G001-F001)U33, pin `1`; ComponentR96, pins `1, 2` (G003-F001)Component
U34, pin `8`; ComponentR96, pins `1, 2`; ComponentR326, pin `1`: R96 on U34 RST output is labeled 0 Ω but its part number is a 10 kΩ resistor; fix the part number. (G001-F001)Observed: U34 RST_L (pin 8, net N25161882) reaches PS_POR_L only through R96. R96 is labeled VALUE=0 and DESCRIPTION 'RES, 0402, 0 OHM, 1%', but its MFG_PART_NO and VENDOR_PN are CRCW040210K0FKED. The design's resolved part data maps that part number to a 10 kΩ resistor. PS_POR_L is pulled up to 3P3V by R326 (10 kΩ) and goes to the Zynq U2 PS_POR_B (pin C7) and the U33 OE̅ input. If a 10 kΩ part is fitted at R96, U34 pulling RST low divides through R96 against R326, so PS_POR_L only falls to about 3.3 V × 10k/(10k+10k) ≈ 1.65 V.
Requirement: U34 RST is an active-low open-drain reset output that has to pull the downstream reset node to a valid logic low. The series element between RST and PS_POR_L must be the 0 Ω jumper shown by R96's VALUE and DESCRIPTION, with a jumper resistance of 20 mΩ or less. A 10 kΩ resistor does not meet that.
Consequence: If parts are bought by the listed part number, R96 is a 10 kΩ resistor. Supply-monitor and push-button resets would then only pull PS_POR_L to about mid-rail (~1.65 V), not a solid low. Zynq PS_POR_B and the U33 enable would not reliably see reset, so power-on and brownout reset of the processor would fail or become unpredictable.
Evidence:
Suggested repair: Change R96's MFG_PART_NO and VENDOR_PN to the 0 Ω jumper part used elsewhere on this page (CRCW04020000Z0ED, as on R95 and R98), so the BOM matches VALUE and DESCRIPTION.
Component
U33, pin `1`; ComponentR96, pins `1, 2`: R96 lists a 10K part number on a 0 Ω jumper, which could stop U33 O̅E̅ from asserting reset; fix the MPN. (G003-F001)Observed: R96 is the only installed series link from U34 RST_L (net N25161882) to PS_POR_L, and PS_POR_L drives U33 pin 1 (O̅E̅). R96's attributes disagree with each other. VALUE=0, DEVICE=RES0402_0 and DESCRIPTION='RES, 0402, 0 OHM' all say a jumper, but MFG_PART_NO and VENDOR_PN are CRCW040210K0FKED, which is a 10 kΩ resistor. R326 (10K) pulls PS_POR_L up to 3P3V. If R96 is bought by its part number, a 10 kΩ part goes in. U34 pulling low through 10 kΩ against the 10 kΩ pull-up then only brings PS_POR_L down to about 3.3 V × 10k/(10k+10k) ≈ 1.65 V.
Requirement: With U33 at VCC = 3.3 V, the O̅E̅ input needs VIL ≤ 0.30 × VCC ≈ 0.99 V to enable the output. U33 then drives BOARD_RESET_L low, because A is held low by R294.
Consequence: If the 10 kΩ part from the part-number field is fitted, a reset from U34 or SW2 leaves PS_POR_L at about 1.65 V, which is not a valid low. U33 stays tri-stated and BOARD_RESET_L is never asserted to the USB transceivers and the Ethernet PHY. The Zynq PS_POR_B input gets the same marginal level.
Evidence:
Suggested repair: Change R96's MFG_PART_NO and VENDOR_PN to the 0 Ω jumper CRCW04020000Z0ED, so they match VALUE and DESCRIPTION.
Datasheets: U33, U34, R96
Replace a datasheet: R326, R96, U33, U34
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[⚠️ Warning] Component
SW2, pins1, 2: SW2 switches only about 0.5 mA at 3.3 V, below the B3U-1000P's 1 mA/5 V rated minimum load.Observed: SW2 (B3U-1000P) connects PB_RESET_L directly to GND. The only pull-up on PB_RESET_L is U34's internal 10 kΩ MR pull-up to VCC (3P3V). The open contact therefore sees about 3.3 V, and the closed contact carries roughly 0.33–0.8 mA. U34's datasheet gives MR input current at VIN = VSS as 500 µA typ and 800 µA max.
Requirement: The B3U-1000P is rated for 1–50 mA at 5–12 VDC into a resistive load.
Consequence: The switch runs below its rated minimum voltage and current. Omron's datasheet does not guarantee contact performance in this range, so manual-reset closures may be unreliable over the switch's life.
Evidence:
Suggested repair: Add an external pull-up from PB_RESET_L to 3P3V that brings the closed-contact current to 1 mA or more (for example about 3.3 kΩ or less in parallel with the internal 10 kΩ). Alternatively, confirm with Omron that low-level loads are acceptable. The 5 V minimum voltage would still not be met on a 3.3 V rail.
Datasheet: SW2
Replace a datasheet: SW2
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