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Schematic feature/fix: update power and dsp schematic pages #8

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allspice-carah wants to merge 6 commits from develop into main
pull from: develop
merge into: AllSpice-Demos:main
Conversation 4 Commits 6 Changes 21 +1043
allspice-carah commented 2026-06-15 22:10:45 +00:00
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Design Review Checklist

Process
  • Commits in correct branch
  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained
System
  • Power
    • Sufficient power supplied from upstream source
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • I/Os are specified
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review
Components
  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power
Schematics
  • Document
    • Dot on each connection
    • No four-point connections
    • Title block completed for each sheet
    • All components have reference designators and values
    • Multi-part components don't have unplaced symbols
    • Page title present and consistent on all pages if not in title block
    • Symbols identify open collector/drain pins and internal pulled up/down pins
    • Pin names and attributes on symbols with multi-function pins match usage
    • Components follow preferred reference designator pattern
  • External I/O
    • Filtered for EMI
    • Protected against ESD
    • Unused inputs terminated
  • Microcontrollers / ICs
    • Predictable or controlled power-up state
      • Reset filtered
    • Sufficient bypass capacitance
    • Oscillators checked for reliable startup
    • Pullups on open-collector pins
    • Logic-low and logic-high voltage levels checked
    • No-connect pins labeled NC
    • Clock lines terminated
    • Check for power-off voltage & CMOS latchup
    • Review datasheet errata/apnotes
  • Busses
    • UART TX/RX pairs correct
    • I2C SDA/SCL pullups per TI guideline
    • Setup/hold/access times considered
  • Analog
    • Sufficient power rails
    • Amplifier stability
    • Rise/fall rate considerations
  • General
    • Bulk capacitance calculated
    • Polarized components checked
    • No reverse voltage on electrolytic/tantalum
    • Derating checked
    • Capacitance on LDOs
    • Comparator delays/slew rates
    • Opamp common-mode range
    • Custom part pin numbers verified
    • Transistor reverse current/voltage
    • Consistent power net naming
    • Debug features included
## Design Review Checklist <details> <summary>Process</summary> - [ ] Commits in correct branch - [ ] Schematic and PCB file names follow standard - [ ] Export necessary review files (3D model, BOM, etc.) - [ ] Update relevant system architecture documents - [ ] Update project README page - [ ] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [ ] Power - [ ] Sufficient power supplied from upstream source - [ ] Supply rated for necessary country specifications - [ ] Estimated total worst-case power supply draw - [ ] Connectors - [ ] I/Os are specified - [ ] Sufficient Current and Voltage rating - [ ] Mating connectors have matching pinout - [ ] Same contact material specified for mating connectors - [ ] Testing - [ ] Test procedure written - [ ] Environmental - [ ] Specified min/max operating temperature - [ ] Specified min/max storage temperature - [ ] Specified min/max humidity - [ ] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [ ] Unpopulated components are denoted DNI - [ ] Components meet environmental specifications - [ ] All components have quantity, reference designator and description - [ ] Suggested and alternate manufacturers listed - [ ] Price and stock checked for each component - [ ] Component derating - [ ] Voltage - [ ] Current - [ ] Power at worst-case operating temperature - [ ] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [ ] Document - [ ] Dot on each connection - [ ] No four-point connections - [ ] Title block completed for each sheet - [ ] All components have reference designators and values - [ ] Multi-part components don't have unplaced symbols - [ ] Page title present and consistent on all pages if not in title block - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins - [ ] Pin names and attributes on symbols with multi-function pins match usage - [ ] Components follow preferred reference designator pattern - [ ] External I/O - [ ] Filtered for EMI - [ ] Protected against ESD - [ ] Unused inputs terminated - [ ] Microcontrollers / ICs - [ ] Predictable or controlled power-up state - [ ] Reset filtered - [ ] Sufficient bypass capacitance - [ ] Oscillators checked for reliable startup - [ ] Pullups on open-collector pins - [ ] Logic-low and logic-high voltage levels checked - [ ] No-connect pins labeled NC - [ ] Clock lines terminated - [ ] Check for power-off voltage & CMOS latchup - [ ] Review datasheet errata/apnotes - [ ] Busses - [ ] UART TX/RX pairs correct - [ ] I2C SDA/SCL pullups per [TI guideline](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Setup/hold/access times considered - [ ] Analog - [ ] Sufficient power rails - [ ] Amplifier stability - [ ] Rise/fall rate considerations - [ ] General - [ ] Bulk capacitance calculated - [ ] Polarized components checked - [ ] No reverse voltage on electrolytic/tantalum - [ ] Derating checked - [ ] Capacitance on LDOs - [ ] Comparator delays/slew rates - [ ] Opamp common-mode range - [ ] Custom part pin numbers verified - [ ] Transistor reverse current/voltage - [ ] Consistent power net naming - [ ] Debug features included </details> <details>
allspice-carah added 1 commit 2026-06-15 22:10:45 +00:00
updated power management
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allspice-carah changed title from Feature/fix: update power and dsp schematic pages to Schematic feature/fix: update power and dsp schematic pages 2026-06-15 22:13:22 +00:00
allspice-carah reviewed 2026-06-15 22:15:38 +00:00
parallella.sdax
allspice-carah commented 2026-06-15 22:15:38 +00:00
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@allspice-wayne can you create a quick slide for Monday's team meeting on annotation best practices. With all due respect, I think some of the newer team members could use some tutorial on good documentation. 1. This needs to be captured as an issue, this needs to be added to the requirements table, otherwise we can't add it. This is the equivalent of a TBD. Thank you 🍨

!thumbnail[](parallella.sdax){ view-coords="27.4,1.2,57.0,20.2" variant="default" aspect-ratio="1.321" doc-id="899dffe5006059bf8b9b" diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...d86f880abf4c72a7a39d3337390ac1a0a22b177c" pr="8" diff-visibility="full" } @allspice-wayne can you create a quick slide for Monday's team meeting on annotation best practices. With all due respect, I think some of the newer team members could use some tutorial on good documentation. 1. This needs to be captured as an issue, this needs to be added to the requirements table, otherwise we can't add it. This is the equivalent of a TBD. </rant> Thank you 🍨
allspice-carah reviewed 2026-06-15 22:17:38 +00:00
parallella.sdax
allspice-carah commented 2026-06-15 22:17:38 +00:00
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@nick , can you update the firmware team about this new Power fault flag? The checks can't check if the signals aren't added. 🥫 💯

!thumbnail[](parallella.sdax){ view-coords="45.0,18.8,80.5,34.3" variant="default" aspect-ratio="1.321" doc-id="868a51b63acf98f4ff33" diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...d86f880abf4c72a7a39d3337390ac1a0a22b177c" pr="8" diff-visibility="full" } @nick , can you update the firmware team about this new Power fault flag? The checks can't check if the signals aren't added. 🥫 💯
allspice-carah added the
bug
feature
priority/4 - high
 labels 2026-06-15 22:18:16 +00:00
allspice-carah added this to the V3 Project Update milestone 2026-06-15 22:18:32 +00:00
allspice-carah pinned this 2026-06-15 22:18:40 +00:00
allspice-carah requested review from DRCY 2026-06-15 22:18:47 +00:00
allspice-carah added 5 commits 2026-06-15 22:30:51 +00:00
add procurement checks before manufacturing
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add push of report to Jira
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7b6969bcb0
fixed typo and trigger only on DR
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050777c045
updated ticket properties and push to Jira
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d195b44a0e
Merge pull request 'add procurement checks before manufacturing' (#2) from hc/auto-validations into develop
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Reviewed-on: AllSpice-Demos/Parallella-AI-Demo#2
actions-botbot commented 2026-06-15 22:31:16 +00:00
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Parts Check Report

Summary

  • Parts checked: 550
  • Parts with issues: 13

Validation Rules

Each part must have:

  • Vendor PN
  • Description
Issues

U11

  • Vendor PN: NC7WZ16P6X
  • Description: —

Problems

  • ❌ Missing Description

U14

  • Vendor PN: NC7WZ16P6X
  • Description: —

Problems

  • ❌ Missing Description

U5

  • Vendor PN: NC7WZ16P6X
  • Description: —

Problems

  • ❌ Missing Description

J8

  • Vendor PN: BSH-030-01-F-D-A
  • Description: —

Problems

  • ❌ Missing Description

J9

  • Vendor PN: BSH-030-01-F-D-A
  • Description: —

Problems

  • ❌ Missing Description

J11

  • Vendor PN: BSH-030-01-F-D-A
  • Description: —

Problems

  • ❌ Missing Description

PTH1

  • Vendor PN: —
  • Description: —

Problems

  • ❌ Missing Vendor PN
  • ❌ Missing Description

PTH2

  • Vendor PN: —
  • Description: —

Problems

  • ❌ Missing Vendor PN
  • ❌ Missing Description

PTH3

  • Vendor PN: —
  • Description: —

Problems

  • ❌ Missing Vendor PN
  • ❌ Missing Description

PTH4

  • Vendor PN: —
  • Description: —

Problems

  • ❌ Missing Vendor PN
  • ❌ Missing Description

U36

  • Vendor PN: NC7SZ125M5X
  • Description: —

Problems

  • ❌ Missing Description

U33

  • Vendor PN: NC7SZ125M5X
  • Description: —

Problems

  • ❌ Missing Description

J13

  • Vendor PN: BSH-030-01-F-D-A
  • Description: —

Problems

  • ❌ Missing Description
# Parts Check Report ## Summary - **Parts checked:** 550 - **Parts with issues:** 13 ### Validation Rules Each part must have: - **Vendor PN** - **Description** --- <details> <summary>Issues</summary> ### U11 - **Vendor PN:** NC7WZ16P6X - **Description:** — **Problems** - ❌ Missing Description --- ### U14 - **Vendor PN:** NC7WZ16P6X - **Description:** — **Problems** - ❌ Missing Description --- ### U5 - **Vendor PN:** NC7WZ16P6X - **Description:** — **Problems** - ❌ Missing Description --- ### J8 - **Vendor PN:** BSH-030-01-F-D-A - **Description:** — **Problems** - ❌ Missing Description --- ### J9 - **Vendor PN:** BSH-030-01-F-D-A - **Description:** — **Problems** - ❌ Missing Description --- ### J11 - **Vendor PN:** BSH-030-01-F-D-A - **Description:** — **Problems** - ❌ Missing Description --- ### PTH1 - **Vendor PN:** — - **Description:** — **Problems** - ❌ Missing Vendor PN - ❌ Missing Description --- ### PTH2 - **Vendor PN:** — - **Description:** — **Problems** - ❌ Missing Vendor PN - ❌ Missing Description --- ### PTH3 - **Vendor PN:** — - **Description:** — **Problems** - ❌ Missing Vendor PN - ❌ Missing Description --- ### PTH4 - **Vendor PN:** — - **Description:** — **Problems** - ❌ Missing Vendor PN - ❌ Missing Description --- ### U36 - **Vendor PN:** NC7SZ125M5X - **Description:** — **Problems** - ❌ Missing Description --- ### U33 - **Vendor PN:** NC7SZ125M5X - **Description:** — **Problems** - ❌ Missing Description --- ### J13 - **Vendor PN:** BSH-030-01-F-D-A - **Description:** — **Problems** - ❌ Missing Description --- </details>
DRCYAI reviewed 2026-06-15 23:07:56 +00:00
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DRCY Connections Checker Review

DRCY reviewed the connections in the 5 page(s) that changed in this DR. From these pages, DRCY selected 78 component(s) to review, and found 6 potential issue(s) in 7 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

U2 - 7Z020-CLG400 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: XC7Z020-1CLG400C (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
B19 IO_L2P_T0_AD8P_35 RXI_EA_DATA0_P ✅ Differential pair RXI_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
A20 IO_L2N_T0_AD8N_35 RXI_EA_DATA0_N ✅ Differential pair RXI_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
C19 VCCO_35_1 2P5V ✅ Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143).
F18 VCCO_35_2 2P5V ✅ Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143).
H14 VCCO_35_3 2P5V ✅ Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143).
J17 VCCO_35_4 2P5V ✅ Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143).
K20 VCCO_35_5 2P5V ✅ Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143).
M16 VCCO_35_6 2P5V ✅ Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143).
C20 IO_L1P_T0_AD0P_35 RXI_EA_DATA1_P ✅ Differential pair RXI_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
B20 IO_L1N_T0_AD0N_35 RXI_EA_DATA1_N ✅ Differential pair RXI_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
D19 IO_L4P_T0_35 RXI_EA_DATA2_P ✅ Differential pair RXI_EA_DATA2_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
D20 IO_L4N_T0_35 RXI_EA_DATA2_N ✅ Differential pair RXI_EA_DATA2_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
E17 IO_L3P_T0_DQS_AD1P_35 RXI_EA_DATA4_P ✅ Differential pair RXI_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface.
D18 IO_L3N_T0_DQS_AD1N_35 RXI_EA_DATA4_N ✅ Differential pair RXI_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface.
E18 IO_L5P_T0_AD9P_35 RXI_EA_DATA3_P ✅ Differential pair RXI_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
E19 IO_L5N_T0_AD9N_35 RXI_EA_DATA3_N ✅ Differential pair RXI_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
F16 IO_L6P_T0_35 RXI_EA_LCLK_P ✅ Differential pair RXI_EA_LCLK_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive clock.
F17 IO_L6N_T0_VREF_35 RXI_EA_LCLK_N ✅ Differential pair RXI_EA_LCLK_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive clock.
F19 IO_L15P_T2_DQS_AD12P_35 RXI_EA_DATA5_P ✅ Differential pair RXI_EA_DATA5_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface.
F20 IO_L15N_T2_DQS_AD12N_35 RXI_EA_DATA5_N ✅ Differential pair RXI_EA_DATA5_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface.
G14 IO_0_35 DSP_RESET_L ✅ DSP_RESET_L connected to Bank 35 additional I/O pin with 1K pull-down resistor.
G17 IO_L16P_T2_35 RXI_EA_DATA6_P ✅ Differential pair RXI_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
G18 IO_L16N_T2_35 RXI_EA_DATA6_N ✅ Differential pair RXI_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
G19 IO_L18P_T2_AD13P_35 RXI_EA_DATA7_P ✅ Differential pair RXI_EA_DATA7_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
G20 IO_L18N_T2_AD13N_35 RXI_EA_DATA7_N ✅ Differential pair RXI_EA_DATA7_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface.
H15 IO_L19P_T3_35 RXI_EA_FRAME_P ✅ Differential pair RXI_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive frame.
G15 IO_L19N_T3_VREF_35 RXI_EA_FRAME_N ✅ Differential pair RXI_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive frame.
H16 IO_L13P_T2_MRCC_35 RXI_CCLK_P ✅ Differential pair RXI_CCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface receive control clock.
H17 IO_L13N_T2_MRCC_35 RXI_CCLK_N ✅ Differential pair RXI_CCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface receive control clock.
J15 IO_25_34 RXO_EA_RD_WAIT ✅ RXO_EA_RD_WAIT connected to Bank 35 additional I/O pin. Pin name shows IO_25_34 but should be IO_25_35 based on bank assignment.
J18 IO_L14P_T2_AD4P_SRCC_35 RXO_EA_WR_WAIT_P ✅ Differential pair RXO_EA_WR_WAIT_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface write wait output.
H18 IO_L14N_T2_AD4N_SRCC_35 RXO_EA_WR_WAIT_N ✅ Differential pair RXO_EA_WR_WAIT_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface write wait output.
J20 IO_L17P_T2_AD5P_35 TXO_EA_FRAME_P ✅ Differential pair TXO_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit frame.
H20 IO_L17N_T2_AD5N_35 TXO_EA_FRAME_N ✅ Differential pair TXO_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit frame.
K14 IO_L20P_T3_AD6P_35 TXI_EA_RD_WAIT_P ✅ Differential pair TXI_EA_RD_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface read wait input.
J14 IO_L20N_T3_AD6N_35 TXI_EA_RD_WAIT_N ✅ Differential pair TXI_EA_RD_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface read wait input.
K16 IO_L24P_T3_AD15P_35 TXI_EA_WR_WAIT_P ✅ Differential pair TXI_EA_WR_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface write wait input.
J16 IO_L24N_T3_AD15N_35 TXI_EA_WR_WAIT_N ✅ Differential pair TXI_EA_WR_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface write wait input.
K17 IO_L12P_T1_MRCC_35 TXO_EA_LCLK_P ✅ Differential pair TXO_EA_LCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface transmit clock.
K18 IO_L12N_T1_MRCC_35 TXO_EA_LCLK_N ✅ Differential pair TXO_EA_LCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface transmit clock.
K19 IO_L10P_T1_AD11P_35 TXO_EA_DATA0_P ✅ Differential pair TXO_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
J19 IO_L10N_T1_AD11N_35 TXO_EA_DATA0_N ✅ Differential pair TXO_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
L14 IO_L22P_T3_AD7P_35 TXO_EA_DATA1_P ✅ Differential pair TXO_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
L15 IO_L22N_T3_AD7N_35 TXO_EA_DATA1_N ✅ Differential pair TXO_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
L16 IO_L11P_T1_SRCC_35 TXO_EA_DATA2_P ✅ Differential pair TXO_EA_DATA2_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface transmit data.
L17 IO_L11N_T1_SRCC_35 TXO_EA_DATA2_N ✅ Differential pair TXO_EA_DATA2_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface transmit data.
L19 IO_L9P_T1_DQS_AD3P_35 TXO_EA_DATA4_P ✅ Differential pair TXO_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data.
L20 IO_L9N_T1_DQS_AD3N_35 TXO_EA_DATA4_N ✅ Differential pair TXO_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data.
M14 IO_L23P_T3_35 TXO_EA_DATA3_P ✅ Differential pair TXO_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
M15 IO_L23N_T3_35 TXO_EA_DATA3_N ✅ Differential pair TXO_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
M17 IO_L8P_T1_AD10P_35 TXO_EA_DATA6_P ✅ Differential pair TXO_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
M18 IO_L8N_T1_AD10N_35 TXO_EA_DATA6_N ✅ Differential pair TXO_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
M19 IO_L7P_T1_AD2P_35 TXO_EA_DATA5_P ✅ Differential pair TXO_EA_DATA5_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
M20 IO_L7N_T1_AD2N_35 TXO_EA_DATA5_N ✅ Differential pair TXO_EA_DATA5_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data.
N15 IO_L21P_T3_DQS_AD14P_35 TXO_EA_DATA7_P ✅ Differential pair TXO_EA_DATA7_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data.
N16 IO_L21N_T3_DQS_AD14N_35 TXO_EA_DATA7_N ✅ Differential pair TXO_EA_DATA7_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data.
N17 IO_L23P_T3_34 N9 ✅ Net N9 and HDMI_D13 connected to differential pair pins, with N9 having 4.75K pull-up resistor.
P18 IO_L23N_T3_34 HDMI_D13 ✅ Net N9 and HDMI_D13 connected to differential pair pins, with N9 having 4.75K pull-up resistor.
N18 IO_L13P_T2_MRCC_34 PS_I2C_SCL ✅ PS_I2C_SCL and HDMI_D19 connected to differential pair pins, with 4.75K pull-up on PS_I2C_SCL.
P19 IO_L13N_T2_MRCC_34 HDMI_D19 ✅ PS_I2C_SCL and HDMI_D19 connected to differential pair pins, with 4.75K pull-up on PS_I2C_SCL.
N19 VCCO_34_1 VD_GPIO ✅ Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134).
R15 VCCO_34_2 VD_GPIO ✅ Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134).
T18 VCCO_34_3 VD_GPIO ✅ Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134).
V14 VCCO_34_4 VD_GPIO ✅ Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134).
W17 VCCO_34_5 VD_GPIO ✅ Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134).
Y20 VCCO_34_6 VD_GPIO ✅ Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134).
N20 IO_L14P_T2_SRCC_34 PROG_IO ✅ PROG_IO and HDMI_INT connected to differential pair pins on Bank 34 SRCC-capable I/O.
P20 IO_L14N_T2_SRCC_34 HDMI_INT ✅ PROG_IO and HDMI_INT connected to differential pair pins on Bank 34 SRCC-capable I/O.
P14 IO_L6P_T0_34 GPIO4_P ✅ Differential pair GPIO4_P/N correctly connected to Bank 34 I/O pins.
R14 IO_L6N_T0_VREF_34 GPIO4_N ✅ Differential pair GPIO4_P/N correctly connected to Bank 34 I/O pins.
P15 IO_L24P_T3_34 GPIO2_P ✅ Differential pair GPIO2_P/N correctly connected to Bank 34 I/O pins.
P16 IO_L24N_T3_34 GPIO2_N ✅ Differential pair GPIO2_P/N correctly connected to Bank 34 I/O pins.
R16 IO_L19P_T3_34 TURBO_MODE ✅ TURBO_MODE and HDMI_CLK connected to differential pair pins, with HDMI_CLK having 22.1Ω series termination.
R17 IO_L19N_T3_VREF_34 N23973428 ✅ TURBO_MODE and HDMI_CLK connected to differential pair pins, with HDMI_CLK having 22.1Ω series termination.
R19 IO_0_34 HDMI_D18 ✅ HDMI_D18 connected to Bank 34 additional I/O pin.
T11 IO_L1P_T0_34 GPIO11_P ✅ Differential pair GPIO11_P/N correctly connected to Bank 34 I/O pins.
T10 IO_L1N_T0_34 GPIO11_N ✅ Differential pair GPIO11_P/N correctly connected to Bank 34 I/O pins.
T12 IO_L2P_T0_34 GPIO10_P ✅ Differential pair GPIO10_P/N correctly connected to Bank 34 I/O pins.
U12 IO_L2N_T0_34 GPIO10_N ✅ Differential pair GPIO10_P/N correctly connected to Bank 34 I/O pins.
T14 IO_L5P_T0_34 GPIO5_P ✅ Differential pair GPIO5_P/N correctly connected to Bank 34 I/O pins.
T15 IO_L5N_T0_34 GPIO5_N ✅ Differential pair GPIO5_P/N correctly connected to Bank 34 I/O pins.
T16 IO_L9P_T1_DQS_34 GPIO0_P ✅ Differential pair GPIO0_P/N correctly connected to Bank 34 DQS-capable I/O pins.
U17 IO_L9N_T1_DQS_34 GPIO0_N ✅ Differential pair GPIO0_P/N correctly connected to Bank 34 DQS-capable I/O pins.
T17 IO_L20P_T3_34 N23971584 ✅ HDMI_HSYNC and HDMI_D12 connected to differential pair pins, with HDMI_HSYNC having 22.1Ω series termination.
R18 IO_L20N_T3_34 HDMI_D12 ✅ HDMI_HSYNC and HDMI_D12 connected to differential pair pins, with HDMI_HSYNC having 22.1Ω series termination.
T19 IO_25_34 HDMI_D17 ✅ HDMI_D17 connected to Bank 34 additional I/O pin.
T20 IO_L15P_T2_DQS_34 HDMI_D23 ✅ HDMI data signals D23 and D22 connected to differential pair DQS-capable pins.
U20 IO_L15N_T2_DQS_34 HDMI_D22 ✅ HDMI data signals D23 and D22 connected to differential pair DQS-capable pins.
U13 IO_L3P_T0_DQS_PUDC_B_34 GPIO8_P ✅ Differential pair GPIO8_P/N connected to Bank 34 I/O pins with 1K pull-down resistor on GPIO8_P.
V13 IO_L3N_T0_DQS_34 GPIO8_N ✅ Differential pair GPIO8_P/N connected to Bank 34 I/O pins with 1K pull-down resistor on GPIO8_P.
U14 IO_L11P_T1_SRCC_34 GPIO6_P ✅ Differential pair GPIO6_P/N correctly connected to Bank 34 SRCC-capable I/O pins.
U15 IO_L11N_T1_SRCC_34 GPIO6_N ✅ Differential pair GPIO6_P/N correctly connected to Bank 34 SRCC-capable I/O pins.
U18 IO_L12P_T1_MRCC_34 GPIO3_P ✅ Differential pair GPIO3_P/N correctly connected to Bank 34 MRCC-capable I/O pins.
U19 IO_L12N_T1_MRCC_34 GPIO3_N ✅ Differential pair GPIO3_P/N correctly connected to Bank 34 MRCC-capable I/O pins.
V12 IO_L4P_T0_34 GPIO9_P ✅ Differential pair GPIO9_P/N correctly connected to Bank 34 I/O pins.
W13 IO_L4N_T0_34 GPIO9_N ✅ Differential pair GPIO9_P/N correctly connected to Bank 34 I/O pins.
V15 IO_L10P_T1_34 HDMI_D11 ✅ HDMI data signals D11 and D16 connected to differential pair pins.
W15 IO_L10N_T1_34 HDMI_D16 ✅ HDMI data signals D11 and D16 connected to differential pair pins.
V16 IO_L18P_T2_34 GPIO1_P ✅ Differential pair GPIO1_P/N correctly connected to Bank 34 I/O pins.
W16 IO_L18N_T2_34 GPIO1_N ✅ Differential pair GPIO1_P/N correctly connected to Bank 34 I/O pins.
V17 IO_L21P_T3_DQS_34 N23969750 ✅ HDMI_VSYNC and HDMI_D10 connected to differential pair DQS-capable pins, with HDMI_VSYNC having 22.1Ω series termination.
V18 IO_L21N_T3_DQS_34 HDMI_D10 ✅ HDMI_VSYNC and HDMI_D10 connected to differential pair DQS-capable pins, with HDMI_VSYNC having 22.1Ω series termination.
V20 IO_L16P_T2_34 HDMI_D21 ✅ HDMI data signals D21 and D20 connected to differential pair pins.
W20 IO_L16N_T2_34 HDMI_D20 ✅ HDMI data signals D21 and D20 connected to differential pair pins.
W14 IO_L8P_T1_34 GPIO7_P ✅ Differential pair GPIO7_P/N correctly connected to Bank 34 I/O pins.
Y14 IO_L8N_T1_34 GPIO7_N ✅ Differential pair GPIO7_P/N correctly connected to Bank 34 I/O pins.
W18 IO_L22P_T3_34 HDMI_D9 ✅ HDMI data signals D9 and D15 connected to differential pair pins.
W19 IO_L22N_T3_34 HDMI_D15 ✅ HDMI data signals D9 and D15 connected to differential pair pins.
Y16 IO_L7P_T1_34 N23961346 ✅ Differential pair connected through series resistors R82 (to SPDIF) and R94 (to HDMI_DE) for source termination.
Y17 IO_L7N_T1_34 N23963188 ✅ Differential pair connected through series resistors R82 (to SPDIF) and R94 (to HDMI_DE) for source termination.
Y18 IO_L17P_T2_34 HDMI_D8 ✅ HDMI data signals D8 and D14 connected to differential pair pins.
Y19 IO_L17N_T2_34 HDMI_D14 ✅ HDMI data signals D8 and D14 connected to differential pair pins.
R44 - RES0402_22R1 ✅

DRCY found no issues in this component 🎉

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Part Number: CRCW040222R1FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N23971584 ✅ 22.1Ω series termination resistor between FPGA pin T17 (IO_L20P_T3_34) and HDMI_HSYNC output. Pin 1 connects to internal net N23971584 from U2 pin T17, pin 2 connects to HDMI_HSYNC.
2 2 HDMI_HSYNC ✅ 22.1Ω series termination resistor between FPGA pin T17 (IO_L20P_T3_34) and HDMI_HSYNC output. Pin 1 connects to internal net N23971584 from U2 pin T17, pin 2 connects to HDMI_HSYNC.
R41 - RES0402_22R1 ✅

DRCY found no issues in this component 🎉

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Part Number: CRCW040222R1FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N23973428 ✅ 22.1Ω series termination resistor between FPGA pin R17 (IO_L19N_T3_VREF_34) and HDMI_CLK output. Pin 1 connects to internal net N23973428 from U2 pin R17, pin 2 connects to HDMI_CLK.
2 2 HDMI_CLK ✅ 22.1Ω series termination resistor between FPGA pin R17 (IO_L19N_T3_VREF_34) and HDMI_CLK output. Pin 1 connects to internal net N23973428 from U2 pin R17, pin 2 connects to HDMI_CLK.
R82 - RES0402_22R1 ✅

DRCY found no issues in this component 🎉

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Part Number: CRCW040222R1FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N23961346 ✅ 22.1Ω series termination resistor between FPGA pin Y16 (IO_L7P_T1_34) and SPDIF output. Pin 1 connects to internal net N23961346 from U2 pin Y16, pin 2 connects to SPDIF.
2 2 SPDIF ✅ 22.1Ω series termination resistor between FPGA pin Y16 (IO_L7P_T1_34) and SPDIF output. Pin 1 connects to internal net N23961346 from U2 pin Y16, pin 2 connects to SPDIF.
R94 - RES0402_22R1 ✅

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Part Number: CRCW040222R1FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N23963188 ✅ 22.1Ω series termination resistor between FPGA pin Y17 (IO_L7N_T1_34) and HDMI_DE output. Pin 1 connects to internal net N23963188 from U2 pin Y17, pin 2 connects to HDMI_DE.
2 2 HDMI_DE ✅ 22.1Ω series termination resistor between FPGA pin Y17 (IO_L7N_T1_34) and HDMI_DE output. Pin 1 connects to internal net N23963188 from U2 pin Y17, pin 2 connects to HDMI_DE.
R42 - RES0402_22R1 ✅

DRCY found no issues in this component 🎉

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Part Number: CRCW040222R1FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N23969750 ✅ 22.1Ω series termination resistor between FPGA pin V17 (IO_L21P_T3_DQS_34) and HDMI_VSYNC output. Pin 1 connects to internal net N23969750 from U2 pin V17, pin 2 connects to HDMI_VSYNC.
2 2 HDMI_VSYNC ✅ 22.1Ω series termination resistor between FPGA pin V17 (IO_L21P_T3_DQS_34) and HDMI_VSYNC output. Pin 1 connects to internal net N23969750 from U2 pin V17, pin 2 connects to HDMI_VSYNC.
R18 ❌

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Part Number: CRCW04024K75FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 VDD_GPIO ❌
Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34.
  • Pin 1 is connected to net VDD_GPIO (from schematic)
  • R18 is a 4.75kΩ resistor functioning as a pull-up resistor (reasoning)
  • The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO (from schematic)
  • All decoupling capacitors for Bank 34 (C126-C134) are connected to VD_GPIO (from schematic)
  • Pull-up resistors for I/O pins should be connected to the same voltage rail as the bank's VCCO supply to ensure proper voltage levels (reasoning)
  • No other components on this schematic page are connected to VDD_GPIO, suggesting it may be a net naming error (from schematic)
  • R18 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage (reasoning)
2 2 N9 ✅ Pin 2 is correctly connected to net N9, which connects to Zynq pin N17 (IO_L23P_T3_34), forming a pull-up resistor configuration.
R20 ❌

DRCY flagged 1 potential issues in this component.

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Part Number: CRCW04024K75FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 VDD_GPIO ❌
Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34 and ensure proper I2C operation.
  • Pin 1 is connected to net VDD_GPIO (from schematic)
  • R20 is a 4.75kΩ resistor functioning as an I2C SCL pull-up resistor (reasoning)
  • The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO (from schematic)
  • I2C pull-up resistors should be connected to the same voltage rail as the I/O pins to ensure proper logic levels (reasoning)
  • The I2C SCL signal connects to U2 pin N18 (IO_L13P_T2_MRCC_34) which is in Bank 34 (from schematic)
  • R20 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage (reasoning)
2 2 PS_I2C_SCL ✅ Pin 2 is correctly connected to PS_I2C_SCL, which connects to Zynq pin N18 (IO_L13P_T2_MRCC_34), forming a proper I2C pull-up configuration.
R223 ✅

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Part Number: CRCW04021K00FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND, forming one terminal of a pull-down resistor for GPIO8_P signal.
2 2 GPIO8_P ✅ Connected to GPIO8_P signal (U2 pin U13), forming a pull-down resistor. This configuration is unusual for a differential pair signal but may be intentional for pre-configuration state control.
R178 ✅

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Part Number: CRCW04021K00FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Connected to GND, forming one terminal of a pull-down resistor for DSP_RESET_L signal.
2 2 DSP_RESET_L ✅ Connected to DSP_RESET_L signal (U2 pin G14), forming a pull-down resistor to hold the reset signal low when not actively driven.
U23 - 16-CORE MICROPROCESSOR ❌

DRCY flagged 1 potential issues in this component.

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Part Number: E16G301 (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
B5 RXI_NO_DATA_N5 RXI_NO_DATA5_N ❌
RXI_NO_DATA5 differential pair appears to be missing series resistors. All other data pairs have 100-ohm series resistors (R194-R198, R200-R201), but R199 is absent from the component list.
  • Pin B5 (RXI_NO_DATA_N5) is connected to net RXI_NO_DATA5_N (from schematic)
  • Pin B6 (RXI_NO_DATA_P5) is connected to net RXI_NO_DATA5_P (from schematic)
  • All other RXI_NO_DATA pairs (0-4, 6-7) have 100-ohm series resistors (from schematic)
  • There is a gap in resistor numbering from R198 to R200, where R199 would be expected for DATA5 (from schematic)
  • The nets RXI_NO_DATA5_N and RXI_NO_DATA5_P are labeled on the schematic, suggesting they should be connected (from schematic)
  • No components on this page are connected to the RXI_NO_DATA5 nets (from schematic)
  • The missing series resistors are likely an error unless DATA5 is intentionally unused in this design (reasoning)
  • If DATA5 is used, 100-ohm series resistors should be added consistent with the other data pairs (reasoning)
B6 RXI_NO_DATA_P5 RXI_NO_DATA5_P ❌
RXI_NO_DATA5 differential pair appears to be missing series resistors. All other data pairs have 100-ohm series resistors (R194-R198, R200-R201), but R199 is absent from the component list.
  • Pin B5 (RXI_NO_DATA_N5) is connected to net RXI_NO_DATA5_N (from schematic)
  • Pin B6 (RXI_NO_DATA_P5) is connected to net RXI_NO_DATA5_P (from schematic)
  • All other RXI_NO_DATA pairs (0-4, 6-7) have 100-ohm series resistors (from schematic)
  • There is a gap in resistor numbering from R198 to R200, where R199 would be expected for DATA5 (from schematic)
  • The nets RXI_NO_DATA5_N and RXI_NO_DATA5_P are labeled on the schematic, suggesting they should be connected (from schematic)
  • No components on this page are connected to the RXI_NO_DATA5 nets (from schematic)
  • The missing series resistors are likely an error unless DATA5 is intentionally unused in this design (reasoning)
  • If DATA5 is used, 100-ohm series resistors should be added consistent with the other data pairs (reasoning)
A2 RXI_NO_DATA_N0 RXI_NO_DATA0_N ✅ RXI_NO_DATA0 differential pair correctly connected through 100-ohm series resistor R194 for LVDS signal integrity.
A3 RXI_NO_DATA_P0 RXI_NO_DATA0_P ✅ RXI_NO_DATA0 differential pair correctly connected through 100-ohm series resistor R194 for LVDS signal integrity.
A4 RXI_NO_DATA_N4 RXI_NO_DATA4_N ✅ RXI_NO_DATA4 differential pair correctly connected through 100-ohm series resistor R198 for LVDS signal integrity.
A5 RXI_NO_DATA_P4 RXI_NO_DATA4_P ✅ RXI_NO_DATA4 differential pair correctly connected through 100-ohm series resistor R198 for LVDS signal integrity.
A6 RXI_NO_LCLK_N RXI_NO_LCLK_N ✅ RXI_NO_LCLK differential pair correctly connected through 100-ohm series resistor R203 for LVDS clock signal integrity.
A7 RXI_NO_LCLK_P RXI_NO_LCLK_P ✅ RXI_NO_LCLK differential pair correctly connected through 100-ohm series resistor R203 for LVDS clock signal integrity.
A9 RXI_NO_CCLK_N N23150336 ✅ RXI_NO_CCLK differential clock input pair tied to static DC levels (P to GND via R289, N to 1P8V via R290). This configuration appears to intentionally disable the clock input, likely because this interface is not used or an alternative clock source is employed.
A10 RXI_NO_CCLK_P N23150334 ✅ RXI_NO_CCLK differential clock input pair tied to static DC levels (P to GND via R289, N to 1P8V via R290). This configuration appears to intentionally disable the clock input, likely because this interface is not used or an alternative clock source is employed.
A12 TXO_NO_LCLK_N TXO_NO_LCLK_N ✅ TXO_NO_LCLK differential pair connected to output nets. DNI resistor R206 would provide series termination if installed.
A13 TXO_NO_LCLK_P TXO_NO_LCLK_P ✅ TXO_NO_LCLK differential pair connected to output nets. DNI resistor R206 would provide series termination if installed.
A14 TXO_NO_DATA_N3 TXO_NO_DATA3_N ✅ TXO_NO_DATA3 differential pair connected to output nets. DNI resistor R230 would provide series termination if installed.
A15 TXO_NO_DATA_P3 TXO_NO_DATA3_P ✅ TXO_NO_DATA3 differential pair connected to output nets. DNI resistor R230 would provide series termination if installed.
A16 TXO_NO_DATA_N7 TXO_NO_DATA7_N ✅ TXO_NO_DATA7 differential pair connected to output nets. DNI resistor R226 would provide series termination if installed.
A17 TXO_NO_DATA_P7 TXO_NO_DATA7_P ✅ TXO_NO_DATA7 differential pair connected to output nets. DNI resistor R226 would provide series termination if installed.
B3 RXI_NO_DATA_N1 RXI_NO_DATA1_N ✅ RXI_NO_DATA1 differential pair correctly connected through 100-ohm series resistor R195 for LVDS signal integrity.
B4 RXI_NO_DATA_P1 RXI_NO_DATA1_P ✅ RXI_NO_DATA1 differential pair correctly connected through 100-ohm series resistor R195 for LVDS signal integrity.
B7 RXI_NO_FRAME_N RXI_NO_FRAME_N ✅ RXI_NO_FRAME differential pair correctly connected through 100-ohm series resistor R202 with appropriate pull resistors (R242 to 1P8V on N, R243 to GND on P) for idle state.
B8 RXI_NO_FRAME_P RXI_NO_FRAME_P ✅ RXI_NO_FRAME differential pair correctly connected through 100-ohm series resistor R202 with appropriate pull resistors (R242 to 1P8V on N, R243 to GND on P) for idle state.
B9 RXO_NO_RD_WAIT_N RXO_NO_RD_WAIT_N ✅ RXO_NO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed.
B10 RXO_NO_RD_WAIT_P RXO_NO_RD_WAIT_P ✅ RXO_NO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed.
B11 TXI_NO_RD_WAIT_N TXI_NO_RD_WAIT_N ✅ TXI_NO_RD_WAIT differential input correctly connected through 100-ohm series resistor R204 with appropriate pull resistors (R241 to 1P8V on P, R240 to GND on N) for idle state.
B12 TXI_NO_RD_WAIT_P TXI_NO_RD_WAIT_P ✅ TXI_NO_RD_WAIT differential input correctly connected through 100-ohm series resistor R204 with appropriate pull resistors (R241 to 1P8V on P, R240 to GND on N) for idle state.
B13 TXO_NO_DATA_N2 TXO_NO_DATA2_N ✅ TXO_NO_DATA2 differential pair connected to output nets. DNI resistor R231 would provide series termination if installed.
B14 TXO_NO_DATA_P2 TXO_NO_DATA2_P ✅ TXO_NO_DATA2 differential pair connected to output nets. DNI resistor R231 would provide series termination if installed.
B15 TXO_NO_DATA_N6 TXO_NO_DATA6_N ✅ TXO_NO_DATA6 differential pair connected to output nets. DNI resistor R227 would provide series termination if installed.
B16 TXO_NO_DATA_P6 TXO_NO_DATA6_P ✅ TXO_NO_DATA6 differential pair connected to output nets. DNI resistor R227 would provide series termination if installed.
C4 RXI_NO_DATA_N2 RXI_NO_DATA2_N ✅ RXI_NO_DATA2 differential pair correctly connected through 100-ohm series resistor R196 for LVDS signal integrity.
C5 RXI_NO_DATA_P2 RXI_NO_DATA2_P ✅ RXI_NO_DATA2 differential pair correctly connected through 100-ohm series resistor R196 for LVDS signal integrity.
C6 RXI_NO_DATA_N6 RXI_NO_DATA6_N ✅ RXI_NO_DATA6 differential pair correctly connected through 100-ohm series resistor R200 for LVDS signal integrity.
C7 RXI_NO_DATA_P6 RXI_NO_DATA6_P ✅ RXI_NO_DATA6 differential pair correctly connected through 100-ohm series resistor R200 for LVDS signal integrity.
C8 RXO_NO_WR_WAIT_N RXO_NO_WR_WAIT_N ✅ RXO_NO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed.
C9 RXO_NO_WR_WAIT_P RXO_NO_WR_WAIT_P ✅ RXO_NO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed.
C10 TXI_NO_WR_WAIT_N TXI_NO_WR_WAIT_N ✅ TXI_NO_WR_WAIT differential input correctly connected through 100-ohm series resistor R205 for LVDS signal integrity.
C11 TXI_NO_WR_WAIT_P TXI_NO_WR_WAIT_P ✅ TXI_NO_WR_WAIT differential input correctly connected through 100-ohm series resistor R205 for LVDS signal integrity.
C12 TXO_NO_DATA_N1 TXO_NO_DATA1_N ✅ TXO_NO_DATA1 differential pair connected to output nets. DNI resistor R232 would provide series termination if installed.
C13 TXO_NO_DATA_P1 TXO_NO_DATA1_P ✅ TXO_NO_DATA1 differential pair connected to output nets. DNI resistor R232 would provide series termination if installed.
C14 TXO_NO_DATA_N5 TXO_NO_DATA5_N ✅ TXO_NO_DATA5 differential pair connected to output nets. DNI resistor R228 would provide series termination if installed.
C15 TXO_NO_DATA_P5 TXO_NO_DATA5_P ✅ TXO_NO_DATA5 differential pair connected to output nets. DNI resistor R228 would provide series termination if installed.
D5 RXI_NO_DATA_N3 RXI_NO_DATA3_N ✅ RXI_NO_DATA3 differential pair correctly connected through 100-ohm series resistor R197 for LVDS signal integrity.
D6 RXI_NO_DATA_P3 RXI_NO_DATA3_P ✅ RXI_NO_DATA3 differential pair correctly connected through 100-ohm series resistor R197 for LVDS signal integrity.
D7 RXI_NO_DATA_N7 RXI_NO_DATA7_N ✅ RXI_NO_DATA7 differential pair correctly connected through 100-ohm series resistor R201 for LVDS signal integrity.
D8 RXI_NO_DATA_P7 RXI_NO_DATA7_P ✅ RXI_NO_DATA7 differential pair correctly connected through 100-ohm series resistor R201 for LVDS signal integrity.
D9 TXO_NO_FRAME_N TXO_NO_FRAME_N ✅ TXO_NO_FRAME differential output pair connected to output nets.
D10 TXO_NO_FRAME_P TXO_NO_FRAME_P ✅ TXO_NO_FRAME differential output pair connected to output nets.
D11 TXO_NO_DATA_N0 TXO_NO_DATA0_N ✅ TXO_NO_DATA0 differential pair connected to output nets. DNI resistor R233 would provide series termination if installed.
D12 TXO_NO_DATA_P0 TXO_NO_DATA0_P ✅ TXO_NO_DATA0 differential pair connected to output nets. DNI resistor R233 would provide series termination if installed.
D13 TXO_NO_DATA_N4 TXO_NO_DATA4_N ✅ TXO_NO_DATA4 differential pair connected to output nets. DNI resistor R229 would provide series termination if installed.
D14 TXO_NO_DATA_P4 TXO_NO_DATA4_P ✅ TXO_NO_DATA4 differential pair connected to output nets. DNI resistor R229 would provide series termination if installed.
R5 RXI_SO_DATA_P3 RXI_SO_DATA3_P ✅ RXI_SO_DATA3 differential pair correctly connected through 100-ohm series resistor R210 for LVDS signal integrity.
R6 RXI_SO_DATA_N3 RXI_SO_DATA3_N ✅ RXI_SO_DATA3 differential pair correctly connected through 100-ohm series resistor R210 for LVDS signal integrity.
R7 RXI_SO_DATA_P7 RXI_SO_DATA7_P ✅ RXI_SO_DATA7 differential pair correctly connected through 100-ohm series resistor R214 for LVDS signal integrity.
R8 RXI_SO_DATA_N7 RXI_SO_DATA7_N ✅ RXI_SO_DATA7 differential pair correctly connected through 100-ohm series resistor R214 for LVDS signal integrity.
R9 TXO_SO_FRAME_P TXO_SO_FRAME_P ✅ TXO_SO_FRAME differential output correctly connected through 100-ohm series resistor R236 with appropriate pull resistors (R244 to 1P8V on N, R245 to GND on P) for idle state.
R10 TXO_SO_FRAME_N TXO_SO_FRAME_N ✅ TXO_SO_FRAME differential output correctly connected through 100-ohm series resistor R236 with appropriate pull resistors (R244 to 1P8V on N, R245 to GND on P) for idle state.
R11 TXO_SO_DATA_P0 TXO_SO_DATA0_P ✅ TXO_SO_DATA0 differential output pair connected to output nets.
R12 TXO_SO_DATA_N0 TXO_SO_DATA0_N ✅ TXO_SO_DATA0 differential output pair connected to output nets.
R13 TXO_SO_DATA_P4 TXO_SO_DATA4_P ✅ TXO_SO_DATA4 differential output pair connected to output nets.
R14 TXO_SO_DATA_N4 TXO_SO_DATA4_N ✅ TXO_SO_DATA4 differential output pair connected to output nets.
T4 RXI_SO_DATA_P2 RXI_SO_DATA2_P ✅ RXI_SO_DATA2 differential pair correctly connected through 100-ohm series resistor R209 for LVDS signal integrity.
T5 RXI_SO_DATA_N2 RXI_SO_DATA2_N ✅ RXI_SO_DATA2 differential pair correctly connected through 100-ohm series resistor R209 for LVDS signal integrity.
T6 RXI_SO_DATA_P6 RXI_SO_DATA6_P ✅ RXI_SO_DATA6 differential pair correctly connected through 100-ohm series resistor R213 for LVDS signal integrity.
T7 RXI_SO_DATA_N6 RXI_SO_DATA6_N ✅ RXI_SO_DATA6 differential pair correctly connected through 100-ohm series resistor R213 for LVDS signal integrity.
T8 RXO_SO_WR_WAIT_P RXO_SO_WR_WAIT_P ✅ RXO_SO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed.
T9 RXO_SO_WR_WAIT_N RXO_SO_WR_WAIT_N ✅ RXO_SO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed.
T10 TXI_SO_WR_WAIT_P TXI_SO_WR_WAIT_P ✅ TXI_SO_WR_WAIT differential input correctly connected through 100-ohm series resistor R218 for LVDS signal integrity.
T11 TXI_SO_WR_WAIT_N TXI_SO_WR_WAIT_N ✅ TXI_SO_WR_WAIT differential input correctly connected through 100-ohm series resistor R218 for LVDS signal integrity.
T12 TXO_SO_DATA_P1 TXO_SO_DATA1_P ✅ TXO_SO_DATA1 differential output pair connected to output nets.
T13 TXO_SO_DATA_N1 TXO_SO_DATA1_N ✅ TXO_SO_DATA1 differential output pair connected to output nets.
T14 TXO_SO_DATA_P5 TXO_SO_DATA5_P ✅ TXO_SO_DATA5 differential output pair connected to output nets.
T15 TXO_SO_DATA_N5 TXO_SO_DATA5_N ✅ TXO_SO_DATA5 differential output pair connected to output nets.
U3 RXI_SO_DATA_P1 RXI_SO_DATA1_P ✅ RXI_SO_DATA1 differential pair correctly connected through 100-ohm series resistor R208 for LVDS signal integrity.
U4 RXI_SO_DATA_N1 RXI_SO_DATA1_N ✅ RXI_SO_DATA1 differential pair correctly connected through 100-ohm series resistor R208 for LVDS signal integrity.
U5 RXI_SO_DATA_P5 RXI_SO_DATA5_P ✅ RXI_SO_DATA5 differential pair correctly connected through 100-ohm series resistor R212 for LVDS signal integrity.
U6 RXI_SO_DATA_N5 RXI_SO_DATA5_N ✅ RXI_SO_DATA5 differential pair correctly connected through 100-ohm series resistor R212 for LVDS signal integrity.
U7 RXI_SO_FRAME_P RXI_SO_FRAME_P ✅ RXI_SO_FRAME differential pair correctly connected through 100-ohm series resistor R215 with appropriate pull resistors (R247 to 1P8V on N, R246 to GND on P) for idle state.
U8 RXI_SO_FRAME_N RXI_SO_FRAME_N ✅ RXI_SO_FRAME differential pair correctly connected through 100-ohm series resistor R215 with appropriate pull resistors (R247 to 1P8V on N, R246 to GND on P) for idle state.
U9 RXO_SO_RD_WAIT_P RXO_SO_RD_WAIT_P ✅ RXO_SO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed.
U10 RXO_SO_RD_WAIT_N RXO_SO_RD_WAIT_N ✅ RXO_SO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed.
U11 TXI_SO_RD_WAIT_P TXI_SO_RD_WAIT_P ✅ TXI_SO_RD_WAIT differential input correctly connected through 100-ohm series resistor R217 for LVDS signal integrity.
U12 TXI_SO_RD_WAIT_N TXI_SO_RD_WAIT_N ✅ TXI_SO_RD_WAIT differential input correctly connected through 100-ohm series resistor R217 for LVDS signal integrity.
U13 TXO_SO_DATA_P2 TXO_SO_DATA2_P ✅ TXO_SO_DATA2 differential output pair connected to output nets.
U14 TXO_SO_DATA_N2 TXO_SO_DATA2_N ✅ TXO_SO_DATA2 differential output pair connected to output nets.
U15 TXO_SO_DATA_P6 TXO_SO_DATA6_P ✅ TXO_SO_DATA6 differential output pair connected to output nets.
U16 TXO_SO_DATA_N6 TXO_SO_DATA6_N ✅ TXO_SO_DATA6 differential output pair connected to output nets.
V2 RXI_SO_DATA_P0 RXI_SO_DATA0_P ✅ RXI_SO_DATA0 differential pair correctly connected through 100-ohm series resistor R207 for LVDS signal integrity.
V3 RXI_SO_DATA_N0 RXI_SO_DATA0_N ✅ RXI_SO_DATA0 differential pair correctly connected through 100-ohm series resistor R207 for LVDS signal integrity.
V4 RXI_SO_DATA_P4 RXI_SO_DATA4_P ✅ RXI_SO_DATA4 differential pair correctly connected through 100-ohm series resistor R211 for LVDS signal integrity.
V5 RXI_SO_DATA_N4 RXI_SO_DATA4_N ✅ RXI_SO_DATA4 differential pair correctly connected through 100-ohm series resistor R211 for LVDS signal integrity.
V6 RXI_SO_LCLK_P RXI_SO_LCLK_P ✅ RXI_SO_LCLK differential pair correctly connected through 100-ohm series resistor R216 for LVDS clock signal integrity.
V7 RXI_SO_LCLK_N RXI_SO_LCLK_N ✅ RXI_SO_LCLK differential pair correctly connected through 100-ohm series resistor R216 for LVDS clock signal integrity.
V9 RXI_SO_CCLK_P N23155371 ✅ RXI_SO_CCLK differential clock input pair tied to static DC levels (P to GND via R291, N to 1P8V via R292). This configuration appears to intentionally disable the clock input, matching the treatment of the North interface CCLK pins.
V10 RXI_SO_CCLK_N N23155373 ✅ RXI_SO_CCLK differential clock input pair tied to static DC levels (P to GND via R291, N to 1P8V via R292). This configuration appears to intentionally disable the clock input, matching the treatment of the North interface CCLK pins.
V12 TXO_SO_LCLK_P TXO_SO_LCLK_P ✅ TXO_SO_LCLK differential output pair connected to output nets.
V13 TXO_SO_LCLK_N TXO_SO_LCLK_N ✅ TXO_SO_LCLK differential output pair connected to output nets.
V14 TXO_SO_DATA_P3 TXO_SO_DATA3_P ✅ TXO_SO_DATA3 differential output pair connected to output nets.
V15 TXO_SO_DATA_N3 TXO_SO_DATA3_N ✅ TXO_SO_DATA3 differential output pair connected to output nets.
V16 TXO_SO_DATA_P7 TXO_SO_DATA7_P ✅ TXO_SO_DATA7 differential output pair connected to output nets.
V17 TXO_SO_DATA_N7 TXO_SO_DATA7_N ✅ TXO_SO_DATA7 differential output pair connected to output nets.
R194 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_DATA0_P ✅ 100Ω differential termination resistor for RXI_NO_DATA0 LVDS pair. Connects between RXI_NO_DATA0_P (pin 1) and RXI_NO_DATA0_N (pin 2).
2 2 RXI_NO_DATA0_N ✅ 100Ω differential termination resistor for RXI_NO_DATA0 LVDS pair. Connects between RXI_NO_DATA0_P (pin 1) and RXI_NO_DATA0_N (pin 2).
R195 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_DATA1_P ✅ 100Ω differential termination resistor for RXI_NO_DATA1 LVDS pair. Connects between RXI_NO_DATA1_P (pin 1) and RXI_NO_DATA1_N (pin 2).
2 2 RXI_NO_DATA1_N ✅ 100Ω differential termination resistor for RXI_NO_DATA1 LVDS pair. Connects between RXI_NO_DATA1_P (pin 1) and RXI_NO_DATA1_N (pin 2).
R196 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_DATA2_P ✅ 100Ω differential termination resistor for RXI_NO_DATA2 LVDS pair. Connects between RXI_NO_DATA2_P (pin 1) and RXI_NO_DATA2_N (pin 2).
2 2 RXI_NO_DATA2_N ✅ 100Ω differential termination resistor for RXI_NO_DATA2 LVDS pair. Connects between RXI_NO_DATA2_P (pin 1) and RXI_NO_DATA2_N (pin 2).
R197 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_DATA3_P ✅ 100Ω differential termination resistor for RXI_NO_DATA3 LVDS pair. Connects between RXI_NO_DATA3_P (pin 1) and RXI_NO_DATA3_N (pin 2).
2 2 RXI_NO_DATA3_N ✅ 100Ω differential termination resistor for RXI_NO_DATA3 LVDS pair. Connects between RXI_NO_DATA3_P (pin 1) and RXI_NO_DATA3_N (pin 2).
R198 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_DATA4_P ✅ 100Ω differential termination resistor for RXI_NO_DATA4 LVDS pair. Connects between RXI_NO_DATA4_P (pin 1) and RXI_NO_DATA4_N (pin 2).
2 2 RXI_NO_DATA4_N ✅ 100Ω differential termination resistor for RXI_NO_DATA4 LVDS pair. Connects between RXI_NO_DATA4_P (pin 1) and RXI_NO_DATA4_N (pin 2).
R200 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_DATA6_P ✅ 100Ω differential termination resistor for RXI_NO_DATA6 LVDS pair. Connects between RXI_NO_DATA6_P (pin 1) and RXI_NO_DATA6_N (pin 2).
2 2 RXI_NO_DATA6_N ✅ 100Ω differential termination resistor for RXI_NO_DATA6 LVDS pair. Connects between RXI_NO_DATA6_P (pin 1) and RXI_NO_DATA6_N (pin 2).
R201 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_DATA7_P ✅ 100Ω differential termination resistor for RXI_NO_DATA7 LVDS pair. Connects between RXI_NO_DATA7_P (pin 1) and RXI_NO_DATA7_N (pin 2).
2 2 RXI_NO_DATA7_N ✅ 100Ω differential termination resistor for RXI_NO_DATA7 LVDS pair. Connects between RXI_NO_DATA7_P (pin 1) and RXI_NO_DATA7_N (pin 2).
R203 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_LCLK_P ✅ 100Ω differential termination resistor for RXI_NO_LCLK LVDS pair. Connects between RXI_NO_LCLK_P (pin 1) and RXI_NO_LCLK_N (pin 2).
2 2 RXI_NO_LCLK_N ✅ 100Ω differential termination resistor for RXI_NO_LCLK LVDS pair. Connects between RXI_NO_LCLK_P (pin 1) and RXI_NO_LCLK_N (pin 2).
R202 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 RXI_NO_FRAME_P ✅ 100Ω differential termination resistor for RXI_NO_FRAME LVDS pair. Connects between RXI_NO_FRAME_P (pin 1) and RXI_NO_FRAME_N (pin 2).
2 2 RXI_NO_FRAME_N ✅ 100Ω differential termination resistor for RXI_NO_FRAME LVDS pair. Connects between RXI_NO_FRAME_P (pin 1) and RXI_NO_FRAME_N (pin 2).
R204 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXI_NO_RD_WAIT_P ✅ 100Ω differential termination resistor for LVDS TXI_NO_RD_WAIT signal pair. Correctly placed between P and N signals with appropriate DC bias resistors.
2 2 TXI_NO_RD_WAIT_N ✅ 100Ω differential termination resistor for LVDS TXI_NO_RD_WAIT signal pair. Correctly placed between P and N signals with appropriate DC bias resistors.
R205 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXI_NO_WR_WAIT_P ✅ 100Ω differential termination resistor for LVDS TXI_NO_WR_WAIT signal pair. Unlike the similar TXI_NO_RD_WAIT signal (R204), this pair lacks DC bias resistors, which may be intentional based on signal characteristics.
2 2 TXI_NO_WR_WAIT_N ✅ 100Ω differential termination resistor for LVDS TXI_NO_WR_WAIT signal pair. Unlike the similar TXI_NO_RD_WAIT signal (R204), this pair lacks DC bias resistors, which may be intentional based on signal characteristics.
R217 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXI_SO_RD_WAIT_P ✅ 100 ohm differential termination resistor for TXI_SO_RD_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair.
2 2 TXI_SO_RD_WAIT_N ✅ 100 ohm differential termination resistor for TXI_SO_RD_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair.
R218 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXI_SO_WR_WAIT_P ✅ 100 ohm differential termination resistor for TXI_SO_WR_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair.
2 2 TXI_SO_WR_WAIT_N ✅ 100 ohm differential termination resistor for TXI_SO_WR_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair.
R236 - RES0402_100 ✅

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Part Number: CRCW0402100RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXO_SO_FRAME_P ✅ 100 ohm differential termination resistor for TXO_SO_FRAME LVDS pair. Unusually placed at the transmitter (U23) rather than receiver, but appears intentional given this is a frame signal with special bias resistors and R236 is not marked DNI unlike other TXO termination resistors.
2 2 TXO_SO_FRAME_N ✅ 100 ohm differential termination resistor for TXO_SO_FRAME LVDS pair. Unusually placed at the transmitter (U23) rather than receiver, but appears intentional given this is a frame signal with special bias resistors and R236 is not marked DNI unlike other TXO termination resistors.
R289 - RES0402_0 ✅

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Part Number: CRCW04020000Z0ED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ 0-ohm resistor connecting U23 pin A10 (RXI_NO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input.
2 2 N23150334 ✅ 0-ohm resistor connecting U23 pin A10 (RXI_NO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input.
R290 - RES0402_0 ✅

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Part Number: CRCW04020000Z0ED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ 0-ohm resistor connecting U23 pin A9 (RXI_NO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input.
2 2 N23150336 ✅ 0-ohm resistor connecting U23 pin A9 (RXI_NO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input.
R291 - RES0402_0 ✅

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Part Number: CRCW04020000Z0ED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ 0-ohm resistor connecting U23 pin V9 (RXI_SO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input.
2 2 N23155371 ✅ 0-ohm resistor connecting U23 pin V9 (RXI_SO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input.
R292 - RES0402_0 ✅

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Part Number: CRCW04020000Z0ED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ 0-ohm resistor connecting U23 pin V10 (RXI_SO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input.
2 2 N23155373 ✅ 0-ohm resistor connecting U23 pin V10 (RXI_SO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input.
R240 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXI_NO_RD_WAIT_N ✅ Pull-down resistor terminal connected to TXI_NO_RD_WAIT_N signal. This resistor, along with R241, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state.
2 2 GND ✅ Pull-down resistor terminal connected to GND. This resistor, along with R241, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state.
R241 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXI_NO_RD_WAIT_P ✅ Pull-up resistor terminal connected to TXI_NO_RD_WAIT_P signal. This resistor, along with R240, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state.
2 2 1P8V ✅ Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R240, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state.
R242 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R243, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
2 2 RXI_NO_FRAME_N ✅ Pull-up resistor terminal connected to RXI_NO_FRAME_N signal. This resistor, along with R243, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
R243 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pull-down resistor terminal connected to GND. This resistor, along with R242, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
2 2 RXI_NO_FRAME_P ✅ Pull-down resistor terminal connected to RXI_NO_FRAME_P signal. This resistor, along with R242, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
R244 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXO_SO_FRAME_N ✅ Pull-up resistor terminal connected to TXO_SO_FRAME_N signal. This resistor, along with R245, provides biasing for the differential FRAME signal output from U23. Note that bias resistors on LVDS outputs are unusual but may provide a default state when the driver is tri-stated or powered down.
2 2 1P8V ✅ Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R245, provides biasing for the differential FRAME signal output from U23.
R245 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 TXO_SO_FRAME_P ✅ Pull-down resistor terminal connected to TXO_SO_FRAME_P signal. This resistor, along with R244, provides biasing for the differential FRAME signal output from U23. Note that bias resistors on LVDS outputs are unusual but may provide a default state when the driver is tri-stated or powered down.
2 2 GND ✅ Pull-down resistor terminal connected to GND. This resistor, along with R244, provides biasing for the differential FRAME signal output from U23.
R246 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ Pull-down resistor terminal connected to GND. This resistor, along with R247, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
2 2 RXI_SO_FRAME_P ✅ Pull-down resistor terminal connected to RXI_SO_FRAME_P signal. This resistor, along with R247, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
R247 ✅

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Part Number: CRCW040210K0FKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R246, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
2 2 RXI_SO_FRAME_N ✅ Pull-up resistor terminal connected to RXI_SO_FRAME_N signal. This resistor, along with R246, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state.
FB14 ✅

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Part Number: BLM15AG121SN1D (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ Input terminal correctly connected to 1P8V supply rail.
2 2 HDMI_DVDD ✅ Output terminal correctly connected to HDMI_DVDD power domain.
R237 ✅

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Warning

DRCY couldn't determine a part number for this component. Add a part-number
attribute to this component — either the attribute configured as the
repository's preferred part-number attribute, or a recognizable one such as
MPN/IPN — to enable datasheet lookup.

Pin Designator Pin Name Net Correct? Analysis
1 1 N25262962 ✅ Resistor terminal correctly connected to U26 PD/AD pin.
2 2 GND ✅ Resistor terminal correctly connected to ground.
U26 - HDMI_DVI_XCVR_ADV7513 ✅

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Part Number: ADV7513BSWZ (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 DVDD1 HDMI_DVDD ✅ DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling.
11 DVDD2 HDMI_DVDD ✅ DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling.
31 DVDD3 HDMI_DVDD ✅ DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling.
51 DVDD4 HDMI_DVDD ✅ DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling.
2 VSYNC HDMI_VSYNC ✅ VSYNC pin correctly connected to video sync input signal.
3 SPDIF SPDIF ✅ SPDIF pin correctly connected to S/PDIF audio input signal.
4 MCLK GND ✅ Audio input pins correctly grounded since I2S audio is not used in this design.
5 I2S0 GND ✅ Audio input pins correctly grounded since I2S audio is not used in this design.
6 I2S1 GND ✅ Audio input pins correctly grounded since I2S audio is not used in this design.
7 I2S2 GND ✅ Audio input pins correctly grounded since I2S audio is not used in this design.
8 I2S3 GND ✅ Audio input pins correctly grounded since I2S audio is not used in this design.
9 SCLK GND ✅ Audio input pins correctly grounded since I2S audio is not used in this design.
10 LRCLK GND ✅ Audio input pins correctly grounded since I2S audio is not used in this design.
12 PVDD HDMI_PVDD ✅ PVDD pin correctly connected to 1.8V PLL supply through ferrite bead with proper decoupling.
13 BGVDD HDMI_BGVDD ✅ BGVDD pin correctly connected to 1.8V bandgap supply through ferrite bead with proper decoupling.
14 R_EXT N23881678 ✅ R_EXT pin correctly connected to 887Ω reference resistor to ground as specified.
15 AVDD1 HDMI_AVDD ✅ AVDD pins correctly connected to 1.8V analog supply through ferrite bead with proper decoupling.
19 AVDD2 HDMI_AVDD ✅ AVDD pins correctly connected to 1.8V analog supply through ferrite bead with proper decoupling.
25 AVDD3 HDMI_AVDD ✅ AVDD pins correctly connected to 1.8V analog supply through ferrite bead with proper decoupling.
16 HPD HDMI_HPD ✅ HPD pin correctly connected to hot plug detect signal through U37 level shifter.
17 TXC- HDMI_TXC_N ✅ TXC+/TXC- pins correctly connected to TMDS clock outputs through U37 ESD protection to HDMI connector.
18 TXC+ HDMI_TXC_P ✅ TXC+/TXC- pins correctly connected to TMDS clock outputs through U37 ESD protection to HDMI connector.
20 TX0- HDMI_TX0_N ✅ TX0+/TX0- pins correctly connected to TMDS data channel 0 outputs through U37 ESD protection to HDMI connector.
21 TX0+ HDMI_TX0_P ✅ TX0+/TX0- pins correctly connected to TMDS data channel 0 outputs through U37 ESD protection to HDMI connector.
22 PD N25262962 ✅ PD/AD pin correctly connected to ground through 1kΩ resistor to set I2C address to 0x72 and active-high power-down.
23 TX1- HDMI_TX1_N ✅ TX1+/TX1- pins correctly connected to TMDS data channel 1 outputs through U37 ESD protection to HDMI connector.
24 TX1+ HDMI_TX1_P ✅ TX1+/TX1- pins correctly connected to TMDS data channel 1 outputs through U37 ESD protection to HDMI connector.
26 TX2- HDMI_TX2_N ✅ TX2+/TX2- pins correctly connected to TMDS data channel 2 outputs through U37 ESD protection to HDMI connector.
27 TX2+ HDMI_TX2_P ✅ TX2+/TX2- pins correctly connected to TMDS data channel 2 outputs through U37 ESD protection to HDMI connector.
28 INT HDMI_INT ✅ INT pin correctly connected to interrupt output with pullup resistor, though resistor value is higher than recommended.
29 DVDD_3V N23924961 ✅ DVDD_3V pin correctly connected to 3.3V supply through ferrite bead with proper decoupling.
30 CEC HDMI_CEC ✅ CEC pin correctly connected to CEC signal through U37 level shifter for proper voltage translation.
32 CEC_CLK HDMI_24M_CES_CLK ✅ CEC_CLK pin correctly connected to CEC clock input signal.
33 DDCSCL DDC_SCL ✅ DDCSCL/DDCSDA pins correctly connected to HDMI connector DDC interface with pullups, though pullup values are outside recommended range.
34 DDCSDA DDC_SDA ✅ DDCSCL/DDCSDA pins correctly connected to HDMI connector DDC interface with pullups, though pullup values are outside recommended range.
35 SCL I2C_SCL ✅ I2C slave interface (SCL/SDA) correctly connected through level shifter U37 from processor. Connection is functional due to 5V tolerance of ADV7513 I2C pins.
36 SDA I2C_SDA ✅ I2C slave interface (SCL/SDA) correctly connected through level shifter U37 from processor. Connection is functional due to 5V tolerance of ADV7513 I2C pins.
37 D23 HDMI_D23 ✅ Video data input pins D23-D8 correctly connected to video data signals.
38 D22 HDMI_D22 ✅ Video data input pins D23-D8 correctly connected to video data signals.
39 D21 HDMI_D21 ✅ Video data input pins D23-D8 correctly connected to video data signals.
40 D20 HDMI_D20 ✅ Video data input pins D23-D8 correctly connected to video data signals.
41 D19 HDMI_D19 ✅ Video data input pins D23-D8 correctly connected to video data signals.
42 D18 HDMI_D18 ✅ Video data input pins D23-D8 correctly connected to video data signals.
43 D17 HDMI_D17 ✅ Video data input pins D23-D8 correctly connected to video data signals.
44 D16 HDMI_D16 ✅ Video data input pins D23-D8 correctly connected to video data signals.
45 D15 HDMI_D15 ✅ Video data input pins D23-D8 correctly connected to video data signals.
46 D14 HDMI_D14 ✅ Video data input pins D23-D8 correctly connected to video data signals.
47 D13 HDMI_D13 ✅ Video data input pins D23-D8 correctly connected to video data signals.
48 D12 HDMI_D12 ✅ Video data input pins D23-D8 correctly connected to video data signals.
49 D11 HDMI_D11 ✅ Video data input pins D23-D8 correctly connected to video data signals.
50 D10 HDMI_D10 ✅ Video data input pins D23-D8 correctly connected to video data signals.
52 D9 HDMI_D9 ✅ Video data input pins D23-D8 correctly connected to video data signals.
54 D8 HDMI_D8 ✅ Video data input pins D23-D8 correctly connected to video data signals.
53 CLK HDMI_CLK ✅ CLK pin correctly connected to video clock input signal.
55 D7 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
56 D6 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
57 D5 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
58 D4 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
59 D3 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
60 D2 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
61 D1 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
62 D0 ✅ Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs.
63 DE HDMI_DE ✅ DE pin correctly connected to data enable signal input.
64 HSYNC HDMI_HSYNC ✅ HSYNC pin correctly connected to horizontal sync input signal.
65 EPAD GND ✅ EPAD pin correctly connected to ground plane.
FB16 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: BLM15AG121SN1D (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N23924961 ✅ Input terminal correctly connected to filtered 3.3V power domain.
2 2 3P3V ✅ Output terminal correctly connected to 3P3V supply rail.
FB17 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: BLM15AG121SN1D (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ Input terminal correctly connected to 1P8V supply rail.
2 2 HDMI_BGVDD ✅ Output terminal correctly connected to HDMI_BGVDD band gap power domain.
FB15 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: BLM15AG121SN1D (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ Input terminal correctly connected to 1P8V supply rail.
2 2 HDMI_AVDD ✅ Output terminal correctly connected to HDMI_AVDD analog power domain.
FB18 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: BLM15AG121SN1D (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ Input terminal correctly connected to 1P8V supply rail.
2 2 HDMI_PVDD ✅ Output terminal correctly connected to HDMI_PVDD PLL power domain.
R224 ✅

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Warning

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Pin Designator Pin Name Net Correct? Analysis
1 1 N23881678 ✅ Resistor terminal correctly connected to U26 R_EXT pin.
2 2 GND ✅ Resistor terminal correctly connected to ground.
U37 - TPD12S016 ✅

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📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: TPD12S016PWR (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 CEC_A HDMI_CEC ✅ CEC_A pin correctly connected to ADV7513 CEC output for level shifting to HDMI connector.
2 SCL_A PS_I2C_SCL ✅ SCL_A and SDA_A controller-side I2C signals correctly connected to processor I2C interface for ADV7513 configuration.
3 SDA_A PS_I2C_SDA ✅ SCL_A and SDA_A controller-side I2C signals correctly connected to processor I2C interface for ADV7513 configuration.
4 HPD_A HDMI_HPD ✅ HPD_A pin correctly connected to ADV7513 HPD input, buffering hot plug detect from connector.
5 LS_OE VDD_GPIO ✅ LS_OE pin correctly tied high to VDD_GPIO to enable level shifters.
6 GND1 GND ✅ Ground pins correctly connected to system ground plane.
14 GND2 GND ✅ Ground pins correctly connected to system ground plane.
19 GND3 GND ✅ Ground pins correctly connected to system ground plane.
7 CEC_B HDMI_CEC_B ✅ CEC_B pin correctly connected to HDMI connector CEC pin with internal pullup.
8 SCL_B I2C_SCL ✅ SCL_B and SDA_B connector-side I2C signals connected to ADV7513 I2C slave interface. This is an unconventional but functional design that uses U37 to level-shift configuration I2C rather than DDC interface.
9 SDA_B I2C_SDA ✅ SCL_B and SDA_B connector-side I2C signals connected to ADV7513 I2C slave interface. This is an unconventional but functional design that uses U37 to level-shift configuration I2C rather than DDC interface.
10 HPD_B HDMI_HPD_B ✅ HPD_B pin correctly connected to HDMI connector HPD pin with pulldown resistor.
11 VCC_5V SYS_5P0V ✅ VCC5V pin correctly connected to 5V supply with decoupling capacitor.
12 CT_HPD VDD_GPIO ✅ CT_HPD pin correctly tied high to VDD_GPIO to enable load switch and HPD.
13 5V_OUT HDMI_5V ✅ 5V_OUT pin correctly connected to HDMI connector 5V pin with decoupling and pullup resistors.
15 CLK- HDMI_TXC_N ✅ CLK+/CLK- pins correctly connected for TMDS clock ESD protection between ADV7513 and HDMI connector.
16 CLK+ HDMI_TXC_P ✅ CLK+/CLK- pins correctly connected for TMDS clock ESD protection between ADV7513 and HDMI connector.
17 D0- HDMI_TX0_N ✅ D0+/D0- pins correctly connected for TMDS data channel 0 ESD protection between ADV7513 and HDMI connector.
18 D0+ HDMI_TX0_P ✅ D0+/D0- pins correctly connected for TMDS data channel 0 ESD protection between ADV7513 and HDMI connector.
20 D1- HDMI_TX1_N ✅ D1+/D1- pins correctly connected for TMDS data channel 1 ESD protection between ADV7513 and HDMI connector.
21 D1+ HDMI_TX1_P ✅ D1+/D1- pins correctly connected for TMDS data channel 1 ESD protection between ADV7513 and HDMI connector.
22 D2- HDMI_TX2_N ✅ D2+/D2- pins correctly connected for TMDS data channel 2 ESD protection between ADV7513 and HDMI connector.
23 D2+ HDMI_TX2_P ✅ D2+/D2- pins correctly connected for TMDS data channel 2 ESD protection between ADV7513 and HDMI connector.
24 VCCA VDD_GPIO ✅ VCCA pin correctly connected to VDD_GPIO supply with decoupling capacitor.
C239 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Warning

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 VDD_GPIO ✅ Decoupling capacitor positive terminal correctly connects to VCCA supply.
2 2 GND ✅ Decoupling capacitor ground terminal correctly connects to ground.
C258 ✅

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Warning

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 SYS_5P0V ✅ Decoupling capacitor positive terminal correctly connects to VCC5V supply.
2 2 GND ✅ Decoupling capacitor ground terminal correctly connects to ground.
C289 - CAP0402_0P1UF_X5R_35V ✅

DRCY found no issues in this component 🎉

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Warning

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_5V ✅ 0.1uF decoupling capacitor correctly connected between HDMI_5V and GND to provide local bypassing for the 5V supply to the HDMI connector.
2 2 GND ✅ 0.1uF decoupling capacitor correctly connected between HDMI_5V and GND to provide local bypassing for the 5V supply to the HDMI connector.
R24 - RES0402_4K75 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Warning

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_HPD_B ✅ 4.75K pulldown resistor correctly connected between HDMI_HPD_B and GND to pull Hot Plug Detect signal low when no device is connected.
2 2 GND ✅ 4.75K pulldown resistor correctly connected between HDMI_HPD_B and GND to pull Hot Plug Detect signal low when no device is connected.
R21 - RES0402_4K75 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Warning

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 DDC_SDA ✅ 4.75K pullup resistor correctly connected between DDC_SDA and HDMI_5V to provide required I2C pullup for DDC data line.
2 2 HDMI_5V ✅ 4.75K pullup resistor correctly connected between DDC_SDA and HDMI_5V to provide required I2C pullup for DDC data line.
R19 - RES0402_4K75 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Warning

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attribute to this component — either the attribute configured as the
repository's preferred part-number attribute, or a recognizable one such as
MPN/IPN — to enable datasheet lookup.

Pin Designator Pin Name Net Correct? Analysis
1 1 DDC_SCL ✅ 4.75K pullup resistor correctly connected between DDC_SCL and HDMI_5V to provide required I2C pullup for DDC clock line.
2 2 HDMI_5V ✅ 4.75K pullup resistor correctly connected between DDC_SCL and HDMI_5V to provide required I2C pullup for DDC clock line.
J10 - HDMI_MICRO_D_RA ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: 46765-1001 (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 HPD HDMI_HPD_B ✅ HPD pin correctly connected to hot plug detect signal through U37 with pulldown resistor.
2 RES ✅ RES pin correctly left unconnected as it is a reserved/utility pin.
3 D2+ HDMI_TX2_P ✅ D2+ and D2- pins correctly connected to TMDS data channel 2 through U37 ESD protection.
5 D2- HDMI_TX2_N ✅ D2+ and D2- pins correctly connected to TMDS data channel 2 through U37 ESD protection.
4 D2S GND ✅ D2S shield pin correctly connected to ground.
6 D1+ HDMI_TX1_P ✅ D1+ and D1- pins correctly connected to TMDS data channel 1 through U37 ESD protection.
8 D1- HDMI_TX1_N ✅ D1+ and D1- pins correctly connected to TMDS data channel 1 through U37 ESD protection.
7 D1S GND ✅ D1S shield pin correctly connected to ground.
9 D0+ HDMI_TX0_P ✅ D0+ and D0- pins correctly connected to TMDS data channel 0 through U37 ESD protection.
11 D0- HDMI_TX0_N ✅ D0+ and D0- pins correctly connected to TMDS data channel 0 through U37 ESD protection.
10 D0S GND ✅ D0S shield pin correctly connected to ground.
12 CLK+ HDMI_TXC_P ✅ CLK+ and CLK- pins correctly connected to TMDS clock through U37 ESD protection.
14 CLK- HDMI_TXC_N ✅ CLK+ and CLK- pins correctly connected to TMDS clock through U37 ESD protection.
13 CLKS GND ✅ CLKS shield pin correctly connected to ground.
15 CEC HDMI_CEC_B ✅ CEC pin correctly connected to CEC signal through U37 level shifter.
16 DDC GND ✅ DDC ground pin correctly connected to system ground.
17 SCL DDC_SCL ✅ SCL and SDA pins correctly connected to DDC interface with pullup resistors, though pullup values are outside recommended range.
18 SDA DDC_SDA ✅ SCL and SDA pins correctly connected to DDC interface with pullup resistors, though pullup values are outside recommended range.
19 5V0 HDMI_5V ✅ 5V power pin correctly connected to current-limited 5V output from U37.
GND1 SHLD1 GND ✅ Shield pins correctly connected to system ground for EMI protection.
GND2 SHLD2 GND ✅ Shield pins correctly connected to system ground for EMI protection.
GND3 SHLD3 GND ✅ Shield pins correctly connected to system ground for EMI protection.
GND4 SHLD4 GND ✅ Shield pins correctly connected to system ground for EMI protection.
J11 - BSH-030-01-F-D-A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: BSH-030-01-F-D-A (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 01 VDD_GPIO ✅ Power supply pins connected to VDD_GPIO. Both pins provide redundant power connections to the GPIO expansion connector.
2 02 VDD_GPIO ✅ Power supply pins connected to VDD_GPIO. Both pins provide redundant power connections to the GPIO expansion connector.
3 03 GPIO0_N ✅ GPIO0 differential pair (GPIO0_N and GPIO0_P) on Row 1 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity.
5 05 GPIO0_P ✅ GPIO0 differential pair (GPIO0_N and GPIO0_P) on Row 1 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity.
4 04 GPIO1_N ✅ GPIO1 differential pair (GPIO1_N and GPIO1_P) on Row 2 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity.
6 06 GPIO1_P ✅ GPIO1 differential pair (GPIO1_N and GPIO1_P) on Row 2 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity.
7 07 GPIO2_N ✅ GPIO2 differential pair (GPIO2_N and GPIO2_P) on Row 1 of the connector.
9 09 GPIO2_P ✅ GPIO2 differential pair (GPIO2_N and GPIO2_P) on Row 1 of the connector.
8 08 GPIO3_N ✅ GPIO3 differential pair (GPIO3_N and GPIO3_P) on Row 2 of the connector.
10 10 GPIO3_P ✅ GPIO3 differential pair (GPIO3_N and GPIO3_P) on Row 2 of the connector.
11 11 GND ✅ Ground pins providing return paths for GPIO0-GPIO3 differential pairs. Ground pins are strategically placed every 10 pins for good signal integrity.
12 12 GND ✅ Ground pins providing return paths for GPIO0-GPIO3 differential pairs. Ground pins are strategically placed every 10 pins for good signal integrity.
13 13 GPIO4_N ✅ GPIO4 differential pair (GPIO4_N and GPIO4_P) on Row 1 of the connector.
15 15 GPIO4_P ✅ GPIO4 differential pair (GPIO4_N and GPIO4_P) on Row 1 of the connector.
14 14 GPIO5_N ✅ GPIO5 differential pair (GPIO5_N and GPIO5_P) on Row 2 of the connector.
16 16 GPIO5_P ✅ GPIO5 differential pair (GPIO5_N and GPIO5_P) on Row 2 of the connector.
17 17 GPIO6_N ✅ GPIO6 differential pair (GPIO6_N and GPIO6_P) on Row 1 of the connector.
19 19 GPIO6_P ✅ GPIO6 differential pair (GPIO6_N and GPIO6_P) on Row 1 of the connector.
18 18 GPIO7_N ✅ GPIO7 differential pair (GPIO7_N and GPIO7_P) on Row 2 of the connector.
20 20 GPIO7_P ✅ GPIO7 differential pair (GPIO7_N and GPIO7_P) on Row 2 of the connector.
21 21 GND ✅ Ground pins providing return paths for GPIO4-GPIO7 differential pairs.
22 22 GND ✅ Ground pins providing return paths for GPIO4-GPIO7 differential pairs.
23 23 GPIO8_N ✅ GPIO8 differential pair (GPIO8_N and GPIO8_P) on Row 1 of the connector.
25 25 GPIO8_P ✅ GPIO8 differential pair (GPIO8_N and GPIO8_P) on Row 1 of the connector.
24 24 GPIO9_N ✅ GPIO9 differential pair (GPIO9_N and GPIO9_P) on Row 2 of the connector.
26 26 GPIO9_P ✅ GPIO9 differential pair (GPIO9_N and GPIO9_P) on Row 2 of the connector.
27 27 GPIO10_N ✅ GPIO10 differential pair (GPIO10_N and GPIO10_P) on Row 1 of the connector.
29 29 GPIO10_P ✅ GPIO10 differential pair (GPIO10_N and GPIO10_P) on Row 1 of the connector.
28 28 GPIO11_N ✅ GPIO11 differential pair (GPIO11_N and GPIO11_P) on Row 2 of the connector.
30 30 GPIO11_P ✅ GPIO11 differential pair (GPIO11_N and GPIO11_P) on Row 2 of the connector.
31 31 GND ✅ Ground pins providing return paths for GPIO8-GPIO11 differential pairs.
32 32 GND ✅ Ground pins providing return paths for GPIO8-GPIO11 differential pairs.
33 33 GPIO12_N ✅ GPIO12 differential pair (GPIO12_N and GPIO12_P) on Row 1 of the connector.
35 35 GPIO12_P ✅ GPIO12 differential pair (GPIO12_N and GPIO12_P) on Row 1 of the connector.
34 34 GPIO13_N ✅ GPIO13 differential pair (GPIO13_N and GPIO13_P) on Row 2 of the connector.
36 36 GPIO13_P ✅ GPIO13 differential pair (GPIO13_N and GPIO13_P) on Row 2 of the connector.
37 37 GPIO14_N ✅ GPIO14 differential pair (GPIO14_N and GPIO14_P) on Row 1 of the connector.
39 39 GPIO14_P ✅ GPIO14 differential pair (GPIO14_N and GPIO14_P) on Row 1 of the connector.
38 38 GPIO15_N ✅ GPIO15 differential pair (GPIO15_N and GPIO15_P) on Row 2 of the connector.
40 40 GPIO15_P ✅ GPIO15 differential pair (GPIO15_N and GPIO15_P) on Row 2 of the connector.
41 41 GND ✅ Ground pins providing return paths for GPIO12-GPIO15 differential pairs.
42 42 GND ✅ Ground pins providing return paths for GPIO12-GPIO15 differential pairs.
43 43 GPIO16_N ✅ GPIO16 differential pair (GPIO16_N and GPIO16_P) on Row 1 of the connector.
45 45 GPIO16_P ✅ GPIO16 differential pair (GPIO16_N and GPIO16_P) on Row 1 of the connector.
44 44 GPIO17_N ✅ GPIO17 differential pair (GPIO17_N and GPIO17_P) on Row 2 of the connector.
46 46 GPIO17_P ✅ GPIO17 differential pair (GPIO17_N and GPIO17_P) on Row 2 of the connector.
47 47 GPIO18_N ✅ GPIO18 differential pair (GPIO18_N and GPIO18_P) on Row 1 of the connector.
49 49 GPIO18_P ✅ GPIO18 differential pair (GPIO18_N and GPIO18_P) on Row 1 of the connector.
48 48 GPIO19_N ✅ GPIO19 differential pair (GPIO19_N and GPIO19_P) on Row 2 of the connector.
50 50 GPIO19_P ✅ GPIO19 differential pair (GPIO19_N and GPIO19_P) on Row 2 of the connector.
51 51 GND ✅ Ground pins providing return paths for GPIO16-GPIO19 differential pairs.
52 52 GND ✅ Ground pins providing return paths for GPIO16-GPIO19 differential pairs.
53 53 GPIO20_N ✅ GPIO20 differential pair (GPIO20_N and GPIO20_P) on Row 1 of the connector.
55 55 GPIO20_P ✅ GPIO20 differential pair (GPIO20_N and GPIO20_P) on Row 1 of the connector.
54 54 GPIO21_N ✅ GPIO21 differential pair (GPIO21_N and GPIO21_P) on Row 2 of the connector.
56 56 GPIO21_P ✅ GPIO21 differential pair (GPIO21_N and GPIO21_P) on Row 2 of the connector.
57 57 GPIO22_N ✅ GPIO22 differential pair (GPIO22_N and GPIO22_P) on Row 1 of the connector.
59 59 GPIO22_P ✅ GPIO22 differential pair (GPIO22_N and GPIO22_P) on Row 1 of the connector.
58 58 GPIO23_N ✅ GPIO23 differential pair (GPIO23_N and GPIO23_P) on Row 2 of the connector.
60 60 GPIO23_P ✅ GPIO23 differential pair (GPIO23_N and GPIO23_P) on Row 2 of the connector.
R22 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Warning

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attribute to this component — either the attribute configured as the
repository's preferred part-number attribute, or a recognizable one such as
MPN/IPN — to enable datasheet lookup.

Pin Designator Pin Name Net Correct? Analysis
1 1 HDMI_INT ✅ Pin 1 correctly connected to HDMI_INT net from ADV7513 interrupt output.
2 2 VDD_GPIO ✅ Pin 2 correctly connected to VDD_GPIO supply, providing pull-up for open-drain interrupt output.
D1 - DIODE_BAS16XV2T1G ✅

DRCY found no issues in this component 🎉

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Warning

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 CATHODE HDMI_CEC ✅ Component is DNI (Do Not Install) and electrically absent from the circuit.
2 ANODE N22414199 ✅ Component is DNI (Do Not Install) and electrically absent from the circuit.
R225 - RES0402_27K4 ✅

DRCY found no issues in this component 🎉

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Warning

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 3P3V ✅ Component is DNI (Do Not Install) and electrically absent from the circuit.
2 2 N22414199 ✅ Component is DNI (Do Not Install) and electrically absent from the circuit.
L8 ✅

DRCY found no issues in this component 🎉

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Part Number: VLS252012ET-1R5N (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N22934179 ✅ L8 is correctly connected between the SW1 switching node (pin 16 of U29) and the DCD1 output, forming the output filter for the 1V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A).
2 2 N22939905 ✅ L8 is correctly connected between the SW1 switching node (pin 16 of U29) and the DCD1 output, forming the output filter for the 1V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A).
1 1 N22934179 ✅ Inductor terminal 1 is correctly connected to the SW1 switching node (N22934179) of U29 DCD1 converter, forming one end of the buck converter output filter.
2 2 N22939905 ✅ Inductor terminal 2 is correctly connected to the DCD1 output node (N22939905), which feeds the 1P0V rail through R286 (0Ω). Output capacitors C242 (0.047µF) and C243 (10µF) are connected to this node. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A.
L9 ✅

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Part Number: VLS252012ET-1R5N (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N25830793 ✅ L9 is correctly connected between the SW2 switching node (pin 13 of U29) and the DCD2 output, forming the output filter for the 1.8V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A).
2 2 N25830712 ✅ L9 is correctly connected between the SW2 switching node (pin 13 of U29) and the DCD2 output, forming the output filter for the 1.8V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A).
1 1 N25830793 ✅ Inductor terminal 1 is correctly connected to the SW2 switching node (N25830793) of U29 DCD2 converter, forming one end of the buck converter output filter.
2 2 N25830712 ✅ Inductor terminal 2 is correctly connected to the DCD2 output node (N25830712), which feeds the 1P8V rail through R287 (0Ω). Output capacitors C244 (0.047µF) and C245 (10µF) are connected to this node. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A.
U29 - DC-TO-DC PWR SUPPLY ❌

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Part Number: ISL9307IRTAANFZ-T (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
11 FB2 N25830704 ❌
FB2 is connected to a voltage divider network (R282, R281) that produces approximately 0.94V output, but the design specification indicates 1.8V is required. The resistor values are incorrect for the intended 1.8V output.
  • Pin 11 (FB2) is connected to net N25830704 (from schematic)
  • FB2 connects to a voltage divider consisting of R282 (10K) from the output to FB2, and R281 (56.2K) from FB2 to ground (from schematic)
  • FB2 regulation voltage is 0.8V typical (from datasheet ISL9307IRTAANFZ-T, page 5)
  • The output voltage is calculated as Vout = 0.8V × (1 + R282/R281) = 0.8V × (1 + 10K/56.2K) = 0.942V (reasoning)
  • The text note indicates the output should be 1.8V @ 1.5A max (from schematic)
  • The DCD2 output connects through R287 (0 ohm) to the 1P8V net, confirming the intended output is 1.8V (from schematic)
  • For 1.8V output, the resistor ratio should be R_TOP/R_BOT = (1.8V/0.8V) - 1 = 1.25 (reasoning)
  • The actual ratio is R282/R281 = 10K/56.2K = 0.178, which does not match the required 1.25 ratio (reasoning)
  • To achieve 1.8V output, either R282 should be changed to approximately 70K (keeping R281 = 56.2K), or R281 should be changed to approximately 8K (keeping R282 = 10K) (reasoning)
  • The feedback resistor values are incorrect and will produce 0.94V instead of the intended 1.8V (reasoning)
15 GNDDCD1 ❌
GNDDCD1 is not connected to any net. This is a critical error that will prevent DCD1 from functioning properly.
  • Pin 15 (GNDDCD1) has no net connection in the schematic (from schematic)
  • GNDDCD1 is the power ground for DCD1 and must be connected to ground (from datasheet ISL9307IRTAANFZ-T, page 3)
  • All other ground pins (GNDLDO, GNDDCD2, EPAD) are correctly connected to GND (from schematic)
  • Without a ground connection, DCD1 will not have a return path for its power ground and cannot function (reasoning)
  • Pin 15 must be connected to GND to match the other ground pins and enable proper operation of DCD1 (reasoning)
1 VINDCD1 SYS_5P0V ✅ VINDCD1 and VINDCD2 are correctly connected to SYS_5P0V, providing input power for both DC-DC converters.
12 VINDCD2 SYS_5P0V ✅ VINDCD1 and VINDCD2 are correctly connected to SYS_5P0V, providing input power for both DC-DC converters.
2 FB1 N22934548 ✅ FB1 is correctly connected to a voltage divider network (R2, R5, R279) that sets the DCD1 output to 1.0V.
3 ENDCD1 REG_EN1 ✅ ENDCD1 and ENDCD2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both DC-DC converters when SYS_5P0V is present.
10 ENDCD2 REG_EN2 ✅ ENDCD1 and ENDCD2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both DC-DC converters when SYS_5P0V is present.
4 ENLDO1 REG_EN3 ✅ ENLDO1 and ENLDO2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both LDOs when SYS_5P0V is present.
8 ENLDO2 REG_EN4 ✅ ENLDO1 and ENLDO2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both LDOs when SYS_5P0V is present.
5 VINLDO SYS_5P0V ✅ VINLDO is correctly connected to SYS_5P0V, providing input power for both LDO regulators.
6 VOLDO1 N22979034 ✅ VOLDO1 and VOLDO2 are correctly connected to output capacitors and provide fixed 3.3V and 2.5V outputs respectively, matching the part number specification.
7 VOLDO2 N22979674 ✅ VOLDO1 and VOLDO2 are correctly connected to output capacitors and provide fixed 3.3V and 2.5V outputs respectively, matching the part number specification.
9 GNDLDO GND ✅ GNDLDO, GNDDCD2, and EPAD are correctly connected to GND.
14 GNDDCD2 GND ✅ GNDLDO, GNDDCD2, and EPAD are correctly connected to GND.
17 EPAD GND ✅ GNDLDO, GNDDCD2, and EPAD are correctly connected to GND.
13 SW2 N25830793 ✅ SW1 and SW2 are correctly connected to inductors L8 and L9 respectively, forming the output filters for the DC-DC converters.
16 SW1 N22934179 ✅ SW1 and SW2 are correctly connected to inductors L8 and L9 respectively, forming the output filters for the DC-DC converters.
U30 - DC-TO-DC PWR SUPPLY ❌

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Part Number: ISL9305IRTHWBNLZ-T (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
10 DCDPG N23098459 ❌
DCDPG is connected to LED CR8 for power-good indication, but the LED polarity is reversed. The LED anode is connected to GND and cathode to DCDPG, which will prevent the LED from lighting up when power is good.
  • Pin 10 (DCDPG) is connected to net N23098459 (from schematic)
  • N23098459 connects to CR8 pin 1 (cathode) and R288 pin 1 (620 ohm resistor) (from schematic)
  • CR8 pin 2 (anode) is connected to GND (from schematic)
  • R288 pin 2 is connected to SYS_5P0V, providing pull-up for the open-drain DCDPG output (from schematic)
  • DCDPG is an open-drain output that is released (high-Z, pulled high) when power is good and pulled low when power is bad (from datasheet ISL9305IRTHWBNLZ-T, page 2)
  • When power is good, DCDPG is high-Z and pulled to ~5V by R288, placing ~5V at the LED cathode and 0V at the LED anode, reverse-biasing the LED (reasoning)
  • When power is bad, DCDPG pulls N23098459 to GND, placing 0V at both LED terminals with no current flow (reasoning)
  • The LED will not light up in either state with the current polarity (reasoning)
  • The LED connections should be swapped: CR8 pin 1 should connect to GND and CR8 pin 2 should connect to N23098459 (reasoning)
1 VINDCD1 SYS_5P0V ✅ VINDCD1 is correctly connected to SYS_5P0V as the input voltage for DCD1 and internal circuits.
2 FB1 N22955654 ✅ FB1 is correctly connected to the DCD1 output through inductor L11 for fixed output configuration.
3 SCLK I2C_SCL ✅ SCLK is correctly connected to I2C_SCL with appropriate 10K pull-up resistor to SYS_5P0V.
4 SDAT I2C_SDA ✅ SDAT is correctly connected to I2C_SDA with appropriate 10K pull-up resistor to SYS_5P0V.
5 VINLDO1 SYS_5P0V ✅ VINLDO1 is correctly connected to SYS_5P0V as the input voltage for LDO1.
6 VOLDO1 N23028604 ✅ VOLDO1 is correctly connected to output net N23028604 with appropriate 10uF output capacitor.
7 VOLDO2 N23029208 ✅ VOLDO2 is correctly connected to output net N23029208 with appropriate 10uF output capacitor.
8 VINLDO2 SYS_5P0V ✅ VINLDO2 is correctly connected to SYS_5P0V as the input voltage for LDO2.
9 GNDLDO GND ✅ GNDLDO is correctly connected to GND as the power ground for LDO1 and LDO2.
11 FB2 N22955725 ✅ FB2 is correctly connected to the DCD2 output through inductor L10 for fixed output configuration.
12 VINDCD2 SYS_5P0V ✅ VINDCD2 is correctly connected to SYS_5P0V as the input voltage for DCD2.
13 SW2 N22955745 ✅ SW2 is correctly connected to inductor L10 pin 1 as the switching node for DCD2.
14 GNDDCD2 GND ✅ GNDDCD2 is correctly connected to GND as the power ground for DCD2.
15 GNDDCD1 GND ✅ GNDDCD1 is correctly connected to GND as the power ground for DCD1.
16 SW1 N22955797 ✅ SW1 is correctly connected to inductor L11 pin 1 as the switching node for DCD1.
17 EPAD GND ✅ EPAD is correctly connected to GND as required for the exposed pad.
L10 ✅

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Part Number: VLS252012ET-1R5N (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N22955745 ✅ Pin 1 is correctly connected to the SW2 switching node of U30 for the DCD2 buck converter.
2 2 N22955725 ✅ Pin 2 is correctly connected to the DCD2 output with appropriate output capacitor C250.
L11 ✅

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Part Number: VLS252012ET-1R5N (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N22955797 ✅ Pin 1 is correctly connected to the SW1 switching node of U30 for the DCD1 buck converter.
2 2 N22955654 ✅ Pin 2 is correctly connected to the DCD1 output with appropriate output capacitor C248.
F1 - ERB-RE4R00V ✅

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Part Number: ERB-RE4R00V (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 5P0V_IN ✅ Fuse terminals correctly connected between power jack input (5P0V_IN) and system power rail (5P0V), but the 4A fuse rating is too high to properly protect the 2.5A-rated power jack J12, creating a protection coordination issue.
2 2 5P0V ✅ Fuse terminals correctly connected between power jack input (5P0V_IN) and system power rail (5P0V), but the 4A fuse rating is too high to properly protect the 2.5A-rated power jack J12, creating a protection coordination issue.
J12 - PJ-002A ✅

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Part Number: PJ-002A (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 CENTER 5P0V_IN ✅ CENTER pin correctly connected to 5P0V_IN net, serving as the positive power input from the barrel jack center pin.
2 SLEEVE GND ✅ SLEEVE pin correctly connected to GND, providing the ground return path for the power input.
3 SHUNT GND ✅ SHUNT pin connected to GND. This is the switching contact that is normally closed to pin 2 but opens when a plug is inserted; tying it to ground is acceptable when the switching function is not needed.
R288 - CRCW0402620RFKED ✅

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Part Number: CRCW0402620RFKED (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 N23098459 ✅ Connected to net N23098459, which connects to CR8 pin 1 (cathode) and U30 pin 10 (DCDPG). This resistor serves as a current limiting resistor for LED CR8.
2 2 SYS_5P0V ✅ Connected to SYS_5P0V supply rail. The 620Ω value is appropriate for limiting LED current to approximately 5mA.
CR8 - LTST-C193KGKT-5A ❌

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Part Number: LTST-C193KGKT-5A (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 C N23098459 ❌
LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.
  • Pin 1 is labeled 'C' (cathode) in the schematic and is connected to net N23098459 (from schematic)
  • Pin 2 is labeled 'A' (anode) in the schematic and is connected to net GND (from schematic)
  • Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) (from schematic)
  • Pin 1 is the cathode (negative terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • Pin 2 is the anode (positive terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode (reasoning)
  • With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on (reasoning)
  • A text note near the LED states 'Power Good = LED ON', indicating the LED should illuminate when power is good (from schematic)
  • The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 (reasoning)
  • With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior (reasoning)
  • To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 (reasoning)
  • With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on (reasoning)
2 A GND ❌
LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.
  • Pin 1 is labeled 'C' (cathode) in the schematic and is connected to net N23098459 (from schematic)
  • Pin 2 is labeled 'A' (anode) in the schematic and is connected to net GND (from schematic)
  • Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) (from schematic)
  • Pin 1 is the cathode (negative terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • Pin 2 is the anode (positive terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode (reasoning)
  • With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on (reasoning)
  • A text note near the LED states 'Power Good = LED ON', indicating the LED should illuminate when power is good (from schematic)
  • The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 (reasoning)
  • With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior (reasoning)
  • To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 (reasoning)
  • With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on (reasoning)
U36 - NC7SZ125 ❌

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Part Number: NC7SZ125M5X (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 O\E\ 5P0V ❌
Output enable pin (O̅E̅) is connected to 5P0V (HIGH), which permanently disables the buffer and puts the output in high-impedance state. This appears to be a design error as the buffer serves no function in this configuration.
  • Pin 1 (O̅E̅) is connected to net 5P0V (from schematic)
  • Pin 1 is the output enable input (O̅E̅), which is active LOW (from datasheet NC7SZ125M5X, page 2)
  • When O̅E̅ is LOW, the buffer is enabled and output follows input; when O̅E̅ is HIGH, output is in high-impedance state (from datasheet NC7SZ125M5X, page 2)
  • The 5P0V net is a power rail at approximately 5V, which is a logic HIGH level (reasoning)
  • With O̅E̅ tied HIGH, the buffer is permanently disabled and the output (pin 4) will always be in high-impedance state (reasoning)
  • The buffer serves no function in this configuration since it is always disabled (reasoning)
  • Pin 1 should be connected to GND to enable the buffer, or the buffer should be removed if not needed (reasoning)
2 A N25176046 ✅ Input pin A is connected to net N25176046, which is pulled down to GND through R327 (1K). Since the buffer is disabled, this input has no effect on the output.
3 GND GND ✅ Ground pin is correctly connected to the GND net.
4 Y TURBO_MODE ✅ Output pin Y is connected to TURBO_MODE net, which is pulled up to VDD_GPIO through R328 (1K). Since the buffer is disabled, the output is in high-impedance state and TURBO_MODE is determined solely by the pull-up resistor.
5 VCC 3P3V ✅ VCC pin is connected to 3P3V rail, which is within the 1.65V to 5.5V operating range. The local decoupling capacitor C288 is marked DNI, which is not ideal but may be acceptable if sufficient decoupling exists elsewhere on the 3P3V rail.
J14 - HDR_1X3_TH_VER ✅

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Part Number: PBC36SAAN (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 1 5P0V ✅ Connected to 5P0V, the fused 5V input from the barrel jack connector. This pin provides access to the main 5V input power after the 4A fuse F1.
2 2 SYS_5P0V ✅ Connected to SYS_5P0V, the system 5V power rail that supplies the DC-DC converters U29 and U30. This pin serves as the distribution point for system power.
3 3 USB_VBUS ✅ Connected to USB_VBUS, intended as an alternative USB power input. Currently only connected to a DNI capacitor C287, indicating this is a placeholder for future functionality.
U34 - VOLTMON_4IN_3P3 ✅

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Part Number: STM6904TWEDS6F (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 MR PB_RESET_L ✅ MR (manual reset) input is correctly connected to pushbutton SW2 via PB_RESET_L net. When the button is pressed, this active-low input is pulled to ground, asserting a manual reset.
2 VCC 3P3V ✅ VCC is correctly connected to 3P3V supply with 0.1µF decoupling capacitor C291. The 3.3V supply is monitored with factory-programmed threshold of 3.078V typical.
3 V2IN 1P8V ✅ V2IN is correctly connected to 1P8V supply with 0.1µF decoupling capacitor C290. The 1.8V supply is monitored with factory-programmed threshold of 1.683V typical.
4 VSS GND ✅ VSS is correctly connected to ground.
5 V3IN N23613650 ✅ V3IN is correctly connected to adjustable voltage divider monitoring 1P35V supply. Resistors R298 (10K) and R301 (10K) form a 2:1 divider setting trip threshold at 1.2V (88.9% of nominal 1.35V).
6 V4IN N23614416 ✅ V4IN is correctly connected to adjustable voltage divider monitoring 1P0V supply. Resistors R300 (4.75K) and R299 (10K) form a divider setting trip threshold at 0.885V (88.5% of nominal 1.0V).
7 TRSEL GND ✅ TRSEL is correctly connected to GND, selecting the 210ms reset timeout period.
8 RST_L N25161882 ✅ RST_L output is correctly connected through R96 (0Ω) to PS_POR_L net, which has 10kΩ pull-up resistor R326 to 3P3V. This matches the datasheet recommendation for open-drain output configuration.
SW2 - SW_PB_VERT ✅

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Part Number: B3U-1000P (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 A GND ✅ Terminal A is correctly connected to GND for the normally-open pushbutton switch.
2 B PB_RESET_L ✅ Terminal B is correctly connected to PB_RESET_L, which connects to U34 pin 1 (MR). When the button is pressed, this pulls the manual reset input low.
R294 ✅

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 N23601474 ✅ 1K resistor pulls the input of U33 (pin 2) to GND, ensuring the input is held at logic LOW.
2 2 GND ✅ 1K resistor pulls the input of U33 (pin 2) to GND, ensuring the input is held at logic LOW.
C259 ✅

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attribute to this component — either the attribute configured as the
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Pin Designator Pin Name Net Correct? Analysis
1 1 GND ✅ 0.1µF decoupling capacitor between 3P3V and GND for U33 power supply.
2 2 3P3V ✅ 0.1µF decoupling capacitor between 3P3V and GND for U33 power supply.
U33 - NC7SZ125 ✅

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Part Number: NC7SZ125M5X (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 O\E\ PS_POR_L ✅ Output enable pin (O̅E̅) is connected to PS_POR_L, which controls when the buffer is enabled. When PS_POR_L is LOW (during reset), the buffer is enabled and drives the output LOW.
2 A N23601474 ✅ Input pin (A) is tied LOW through R294 (1K resistor to GND). This ensures the output is LOW when the buffer is enabled.
3 GND GND ✅ Ground pin is correctly connected to the GND net.
4 Y BOARD_RESET_L ✅ Output pin (Y) drives BOARD_RESET_L, which is pulled up to 1P8V through R295 (1K). When enabled, output drives LOW; when disabled (high-Z), R295 pulls the signal to 1P8V.
5 VCC 3P3V ✅ Power supply pin (VCC) is correctly connected to 3P3V with decoupling capacitor C259 (0.1µF).
R295 ✅

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attribute to this component — either the attribute configured as the
repository's preferred part-number attribute, or a recognizable one such as
MPN/IPN — to enable datasheet lookup.

Pin Designator Pin Name Net Correct? Analysis
1 1 1P8V ✅ 1K resistor pulls BOARD_RESET_L up to 1P8V when U33 output is in high-Z state.
2 2 BOARD_RESET_L ✅ 1K resistor pulls BOARD_RESET_L up to 1P8V when U33 output is in high-Z state.
J13 - BSH-030-01-F-D-A ✅

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Part Number: BSH-030-01-F-D-A (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 01 SYS_5P0V ✅ System 5V power supply pins, both connected to SYS_5P0V net. Paired pins provide redundancy and increased current carrying capacity.
2 02 SYS_5P0V ✅ System 5V power supply pins, both connected to SYS_5P0V net. Paired pins provide redundancy and increased current carrying capacity.
3 03 I2C_SCL ✅ I2C clock signal (I2C_SCL) for serial communication interface.
4 04 I2C_SDA ✅ I2C data signal (I2C_SDA) for serial communication interface.
5 05 REG_EN1 ✅ Regulator enable control signal 1 (REG_EN1).
6 06 REG_EN2 ✅ Regulator enable control signal 2 (REG_EN2).
7 07 REG_EN3 ✅ Regulator enable control signal 3 (REG_EN3).
8 08 REG_EN4 ✅ Regulator enable control signal 4 (REG_EN4).
9 09 PROG_IO ✅ Programming I/O signal (PROG_IO) for device programming interface.
10 10 ✅ No connection (NC). This pin is intentionally left unconnected.
11 11 GND ✅ Ground pins providing return path for signals and power.
12 12 GND ✅ Ground pins providing return path for signals and power.
13 13 DSP_XID0 ✅ DSP X-axis ID bit 0 (DSP_XID0) for device identification.
14 14 DSP_YID0 ✅ DSP Y-axis ID bit 0 (DSP_YID0) for device identification.
15 15 DSP_XID1 ✅ DSP X-axis ID bit 1 (DSP_XID1) for device identification.
16 16 DSP_YID1 ✅ DSP Y-axis ID bit 1 (DSP_YID1) for device identification.
17 17 DSP_XID2 ✅ DSP X-axis ID bit 2 (DSP_XID2) for device identification.
18 18 DSP_YID2 ✅ DSP Y-axis ID bit 2 (DSP_YID2) for device identification.
19 19 DSP_XID3 ✅ DSP X-axis ID bit 3 (DSP_XID3) for device identification.
20 20 DSP_YID3 ✅ DSP Y-axis ID bit 3 (DSP_YID3) for device identification.
21 21 GND ✅ Ground pins providing return path for signals and power.
22 22 GND ✅ Ground pins providing return path for signals and power.
23 23 DSP_FLAG ✅ DSP flag signal (DSP_FLAG) for status indication.
24 24 UART_RX ✅ UART receive signal (UART_RX) for serial communication.
25 25 TURBO_MODE ✅ Turbo mode control signal (TURBO_MODE) for performance control.
26 26 UART_TX ✅ UART transmit signal (UART_TX) for serial communication.
27 27 SPDIF ✅ SPDIF digital audio signal for audio interface.
28 28 USER_LED ✅ User LED control signal (USER_LED) for status indication.
29 29 JTAG_BOOT_EN ✅ JTAG boot enable signal (JTAG_BOOT_EN) for debug/programming control.
30 30 RESET_N ✅ System reset signal (RESET_N) for board reset control.
31 31 GND ✅ Ground pins providing return path for signals and power.
32 32 GND ✅ Ground pins providing return path for signals and power.
33 33 VADC_N ✅ Analog voltage negative input (VADC_N) for differential analog signal.
34 34 VADC_P ✅ Analog voltage positive input (VADC_P) for differential analog signal.
35 35 GND ✅ Ground pins providing return path for signals and power, particularly important for adjacent analog signals.
36 36 GND ✅ Ground pins providing return path for signals and power, particularly important for adjacent analog signals.
37 37 JTAG_TMS ✅ JTAG test mode select signal (JTAG_TMS) for debug interface.
38 38 JTAG_TDI ✅ JTAG test data input signal (JTAG_TDI) for debug interface.
39 39 JTAG_TCK ✅ JTAG test clock signal (JTAG_TCK) for debug interface.
40 40 JTAG_TDO ✅ JTAG test data output signal (JTAG_TDO) for debug interface.
41 41 GND ✅ Ground pins providing return path for signals and power.
42 42 GND ✅ Ground pins providing return path for signals and power.
43 43 1P0V ✅ 1.0V power supply pins, both connected to 1P0V net. Paired pins provide redundancy and increased current carrying capacity.
44 44 1P0V ✅ 1.0V power supply pins, both connected to 1P0V net. Paired pins provide redundancy and increased current carrying capacity.
45 45 VDD_DSP ✅ DSP core voltage supply pins, both connected to VDD_DSP net. Paired pins provide redundancy and increased current carrying capacity.
46 46 VDD_DSP ✅ DSP core voltage supply pins, both connected to VDD_DSP net. Paired pins provide redundancy and increased current carrying capacity.
47 47 1P35V ✅ 1.35V power supply pins, both connected to 1P35V net. Paired pins provide redundancy and increased current carrying capacity.
48 48 1P35V ✅ 1.35V power supply pins, both connected to 1P35V net. Paired pins provide redundancy and increased current carrying capacity.
49 49 1P8V ✅ 1.8V power supply pins, both connected to 1P8V net. Paired pins provide redundancy and increased current carrying capacity.
50 50 1P8V ✅ 1.8V power supply pins, both connected to 1P8V net. Paired pins provide redundancy and increased current carrying capacity.
51 51 GND ✅ Ground pins providing return path for signals and power, particularly important in the power supply section.
52 52 GND ✅ Ground pins providing return path for signals and power, particularly important in the power supply section.
53 53 VDD_ADJ ✅ Adjustable voltage supply pins, both connected to VDD_ADJ net. Paired pins provide redundancy and increased current carrying capacity.
54 54 VDD_ADJ ✅ Adjustable voltage supply pins, both connected to VDD_ADJ net. Paired pins provide redundancy and increased current carrying capacity.
55 55 VDD_GPIO ✅ GPIO voltage supply pins, both connected to VDD_GPIO net. Paired pins provide redundancy and increased current carrying capacity.
56 56 VDD_GPIO ✅ GPIO voltage supply pins, both connected to VDD_GPIO net. Paired pins provide redundancy and increased current carrying capacity.
57 57 2P5V ✅ 2.5V power supply pins, both connected to 2P5V net. Paired pins provide redundancy and increased current carrying capacity.
58 58 2P5V ✅ 2.5V power supply pins, both connected to 2P5V net. Paired pins provide redundancy and increased current carrying capacity.
59 59 3P3V ✅ 3.3V power supply pins, both connected to 3P3V net. Paired pins provide redundancy and increased current carrying capacity.
60 60 3P3V ✅ 3.3V power supply pins, both connected to 3P3V net. Paired pins provide redundancy and increased current carrying capacity.
CR10 - LED_0603_5MA_GRN ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Part Number: LTST-C193KGKT-5A (MPN) — inferred by DRCY

Pin Designator Pin Name Net Correct? Analysis
1 C N25352411 ✅ LED cathode correctly connected through current limiting resistor R30 (240Ω) to ground.
2 A USER_LED ✅ LED anode correctly connected to USER_LED signal from connector J13 pin 28.
R30 - RES0402_240 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Warning

DRCY couldn't determine a part number for this component. Add a part-number
attribute to this component — either the attribute configured as the
repository's preferred part-number attribute, or a recognizable one such as
MPN/IPN — to enable datasheet lookup.

Pin Designator Pin Name Net Correct? Analysis
1 1 N25352411 ✅ Current limiting resistor for LED CR10, connected between LED cathode and ground.
2 2 GND ✅ Current limiting resistor ground connection, completing the LED current path.

Note: DRCY uses AI. Please verify the outputs.

# DRCY Connections Checker Review DRCY reviewed the connections in the 5 page(s) that changed in this DR. From these pages, DRCY selected 78 component(s) to review, and found 6 potential issue(s) in 7 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary><b>Component Details</b></summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary><b>U2</b> - 7Z020-CLG400 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/XC7Z020-1CLG400C/ds190-Zynq-7000-Overview.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/XC7Z020-1CLG400C) Part Number: `XC7Z020-1CLG400C` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B19 | IO_L2P_T0_AD8P_35 | RXI_EA_DATA0_P | ✅ | Differential pair RXI_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | A20 | IO_L2N_T0_AD8N_35 | RXI_EA_DATA0_N | ✅ | Differential pair RXI_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | C19 | VCCO_35_1 | 2P5V | ✅ | Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143). | | F18 | VCCO_35_2 | 2P5V | ✅ | Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143). | | H14 | VCCO_35_3 | 2P5V | ✅ | Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143). | | J17 | VCCO_35_4 | 2P5V | ✅ | Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143). | | K20 | VCCO_35_5 | 2P5V | ✅ | Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143). | | M16 | VCCO_35_6 | 2P5V | ✅ | Bank 35 power supply pins (VCCO_35) correctly connected to 2P5V with adequate decoupling capacitors (C135-C143). | | C20 | IO_L1P_T0_AD0P_35 | RXI_EA_DATA1_P | ✅ | Differential pair RXI_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | B20 | IO_L1N_T0_AD0N_35 | RXI_EA_DATA1_N | ✅ | Differential pair RXI_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | D19 | IO_L4P_T0_35 | RXI_EA_DATA2_P | ✅ | Differential pair RXI_EA_DATA2_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | D20 | IO_L4N_T0_35 | RXI_EA_DATA2_N | ✅ | Differential pair RXI_EA_DATA2_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | E17 | IO_L3P_T0_DQS_AD1P_35 | RXI_EA_DATA4_P | ✅ | Differential pair RXI_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface. | | D18 | IO_L3N_T0_DQS_AD1N_35 | RXI_EA_DATA4_N | ✅ | Differential pair RXI_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface. | | E18 | IO_L5P_T0_AD9P_35 | RXI_EA_DATA3_P | ✅ | Differential pair RXI_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | E19 | IO_L5N_T0_AD9N_35 | RXI_EA_DATA3_N | ✅ | Differential pair RXI_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | F16 | IO_L6P_T0_35 | RXI_EA_LCLK_P | ✅ | Differential pair RXI_EA_LCLK_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive clock. | | F17 | IO_L6N_T0_VREF_35 | RXI_EA_LCLK_N | ✅ | Differential pair RXI_EA_LCLK_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive clock. | | F19 | IO_L15P_T2_DQS_AD12P_35 | RXI_EA_DATA5_P | ✅ | Differential pair RXI_EA_DATA5_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface. | | F20 | IO_L15N_T2_DQS_AD12N_35 | RXI_EA_DATA5_N | ✅ | Differential pair RXI_EA_DATA5_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface. | | G14 | IO_0_35 | DSP_RESET_L | ✅ | DSP_RESET_L connected to Bank 35 additional I/O pin with 1K pull-down resistor. | | G17 | IO_L16P_T2_35 | RXI_EA_DATA6_P | ✅ | Differential pair RXI_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | G18 | IO_L16N_T2_35 | RXI_EA_DATA6_N | ✅ | Differential pair RXI_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | G19 | IO_L18P_T2_AD13P_35 | RXI_EA_DATA7_P | ✅ | Differential pair RXI_EA_DATA7_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | G20 | IO_L18N_T2_AD13N_35 | RXI_EA_DATA7_N | ✅ | Differential pair RXI_EA_DATA7_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface. | | H15 | IO_L19P_T3_35 | RXI_EA_FRAME_P | ✅ | Differential pair RXI_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive frame. | | G15 | IO_L19N_T3_VREF_35 | RXI_EA_FRAME_N | ✅ | Differential pair RXI_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface receive frame. | | H16 | IO_L13P_T2_MRCC_35 | RXI_CCLK_P | ✅ | Differential pair RXI_CCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface receive control clock. | | H17 | IO_L13N_T2_MRCC_35 | RXI_CCLK_N | ✅ | Differential pair RXI_CCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface receive control clock. | | J15 | IO_25_34 | RXO_EA_RD_WAIT | ✅ | RXO_EA_RD_WAIT connected to Bank 35 additional I/O pin. Pin name shows IO_25_34 but should be IO_25_35 based on bank assignment. | | J18 | IO_L14P_T2_AD4P_SRCC_35 | RXO_EA_WR_WAIT_P | ✅ | Differential pair RXO_EA_WR_WAIT_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface write wait output. | | H18 | IO_L14N_T2_AD4N_SRCC_35 | RXO_EA_WR_WAIT_N | ✅ | Differential pair RXO_EA_WR_WAIT_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface write wait output. | | J20 | IO_L17P_T2_AD5P_35 | TXO_EA_FRAME_P | ✅ | Differential pair TXO_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit frame. | | H20 | IO_L17N_T2_AD5N_35 | TXO_EA_FRAME_N | ✅ | Differential pair TXO_EA_FRAME_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit frame. | | K14 | IO_L20P_T3_AD6P_35 | TXI_EA_RD_WAIT_P | ✅ | Differential pair TXI_EA_RD_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface read wait input. | | J14 | IO_L20N_T3_AD6N_35 | TXI_EA_RD_WAIT_N | ✅ | Differential pair TXI_EA_RD_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface read wait input. | | K16 | IO_L24P_T3_AD15P_35 | TXI_EA_WR_WAIT_P | ✅ | Differential pair TXI_EA_WR_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface write wait input. | | J16 | IO_L24N_T3_AD15N_35 | TXI_EA_WR_WAIT_N | ✅ | Differential pair TXI_EA_WR_WAIT_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface write wait input. | | K17 | IO_L12P_T1_MRCC_35 | TXO_EA_LCLK_P | ✅ | Differential pair TXO_EA_LCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface transmit clock. | | K18 | IO_L12N_T1_MRCC_35 | TXO_EA_LCLK_N | ✅ | Differential pair TXO_EA_LCLK_P/N correctly connected to Bank 35 MRCC-capable I/O pins for external asynchronous interface transmit clock. | | K19 | IO_L10P_T1_AD11P_35 | TXO_EA_DATA0_P | ✅ | Differential pair TXO_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | J19 | IO_L10N_T1_AD11N_35 | TXO_EA_DATA0_N | ✅ | Differential pair TXO_EA_DATA0_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | L14 | IO_L22P_T3_AD7P_35 | TXO_EA_DATA1_P | ✅ | Differential pair TXO_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | L15 | IO_L22N_T3_AD7N_35 | TXO_EA_DATA1_N | ✅ | Differential pair TXO_EA_DATA1_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | L16 | IO_L11P_T1_SRCC_35 | TXO_EA_DATA2_P | ✅ | Differential pair TXO_EA_DATA2_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface transmit data. | | L17 | IO_L11N_T1_SRCC_35 | TXO_EA_DATA2_N | ✅ | Differential pair TXO_EA_DATA2_P/N correctly connected to Bank 35 SRCC-capable I/O pins for external asynchronous interface transmit data. | | L19 | IO_L9P_T1_DQS_AD3P_35 | TXO_EA_DATA4_P | ✅ | Differential pair TXO_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data. | | L20 | IO_L9N_T1_DQS_AD3N_35 | TXO_EA_DATA4_N | ✅ | Differential pair TXO_EA_DATA4_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data. | | M14 | IO_L23P_T3_35 | TXO_EA_DATA3_P | ✅ | Differential pair TXO_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | M15 | IO_L23N_T3_35 | TXO_EA_DATA3_N | ✅ | Differential pair TXO_EA_DATA3_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | M17 | IO_L8P_T1_AD10P_35 | TXO_EA_DATA6_P | ✅ | Differential pair TXO_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | M18 | IO_L8N_T1_AD10N_35 | TXO_EA_DATA6_N | ✅ | Differential pair TXO_EA_DATA6_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | M19 | IO_L7P_T1_AD2P_35 | TXO_EA_DATA5_P | ✅ | Differential pair TXO_EA_DATA5_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | M20 | IO_L7N_T1_AD2N_35 | TXO_EA_DATA5_N | ✅ | Differential pair TXO_EA_DATA5_P/N correctly connected to Bank 35 I/O pins for external asynchronous interface transmit data. | | N15 | IO_L21P_T3_DQS_AD14P_35 | TXO_EA_DATA7_P | ✅ | Differential pair TXO_EA_DATA7_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data. | | N16 | IO_L21N_T3_DQS_AD14N_35 | TXO_EA_DATA7_N | ✅ | Differential pair TXO_EA_DATA7_P/N correctly connected to Bank 35 DQS-capable I/O pins for external asynchronous interface transmit data. | | N17 | IO_L23P_T3_34 | N9 | ✅ | Net N9 and HDMI_D13 connected to differential pair pins, with N9 having 4.75K pull-up resistor. | | P18 | IO_L23N_T3_34 | HDMI_D13 | ✅ | Net N9 and HDMI_D13 connected to differential pair pins, with N9 having 4.75K pull-up resistor. | | N18 | IO_L13P_T2_MRCC_34 | PS_I2C_SCL | ✅ | PS_I2C_SCL and HDMI_D19 connected to differential pair pins, with 4.75K pull-up on PS_I2C_SCL. | | P19 | IO_L13N_T2_MRCC_34 | HDMI_D19 | ✅ | PS_I2C_SCL and HDMI_D19 connected to differential pair pins, with 4.75K pull-up on PS_I2C_SCL. | | N19 | VCCO_34_1 | VD_GPIO | ✅ | Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134). | | R15 | VCCO_34_2 | VD_GPIO | ✅ | Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134). | | T18 | VCCO_34_3 | VD_GPIO | ✅ | Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134). | | V14 | VCCO_34_4 | VD_GPIO | ✅ | Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134). | | W17 | VCCO_34_5 | VD_GPIO | ✅ | Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134). | | Y20 | VCCO_34_6 | VD_GPIO | ✅ | Bank 34 power supply pins (VCCO_34) correctly connected to VD_GPIO with adequate decoupling capacitors (C126-C134). | | N20 | IO_L14P_T2_SRCC_34 | PROG_IO | ✅ | PROG_IO and HDMI_INT connected to differential pair pins on Bank 34 SRCC-capable I/O. | | P20 | IO_L14N_T2_SRCC_34 | HDMI_INT | ✅ | PROG_IO and HDMI_INT connected to differential pair pins on Bank 34 SRCC-capable I/O. | | P14 | IO_L6P_T0_34 | GPIO4_P | ✅ | Differential pair GPIO4_P/N correctly connected to Bank 34 I/O pins. | | R14 | IO_L6N_T0_VREF_34 | GPIO4_N | ✅ | Differential pair GPIO4_P/N correctly connected to Bank 34 I/O pins. | | P15 | IO_L24P_T3_34 | GPIO2_P | ✅ | Differential pair GPIO2_P/N correctly connected to Bank 34 I/O pins. | | P16 | IO_L24N_T3_34 | GPIO2_N | ✅ | Differential pair GPIO2_P/N correctly connected to Bank 34 I/O pins. | | R16 | IO_L19P_T3_34 | TURBO_MODE | ✅ | TURBO_MODE and HDMI_CLK connected to differential pair pins, with HDMI_CLK having 22.1Ω series termination. | | R17 | IO_L19N_T3_VREF_34 | N23973428 | ✅ | TURBO_MODE and HDMI_CLK connected to differential pair pins, with HDMI_CLK having 22.1Ω series termination. | | R19 | IO_0_34 | HDMI_D18 | ✅ | HDMI_D18 connected to Bank 34 additional I/O pin. | | T11 | IO_L1P_T0_34 | GPIO11_P | ✅ | Differential pair GPIO11_P/N correctly connected to Bank 34 I/O pins. | | T10 | IO_L1N_T0_34 | GPIO11_N | ✅ | Differential pair GPIO11_P/N correctly connected to Bank 34 I/O pins. | | T12 | IO_L2P_T0_34 | GPIO10_P | ✅ | Differential pair GPIO10_P/N correctly connected to Bank 34 I/O pins. | | U12 | IO_L2N_T0_34 | GPIO10_N | ✅ | Differential pair GPIO10_P/N correctly connected to Bank 34 I/O pins. | | T14 | IO_L5P_T0_34 | GPIO5_P | ✅ | Differential pair GPIO5_P/N correctly connected to Bank 34 I/O pins. | | T15 | IO_L5N_T0_34 | GPIO5_N | ✅ | Differential pair GPIO5_P/N correctly connected to Bank 34 I/O pins. | | T16 | IO_L9P_T1_DQS_34 | GPIO0_P | ✅ | Differential pair GPIO0_P/N correctly connected to Bank 34 DQS-capable I/O pins. | | U17 | IO_L9N_T1_DQS_34 | GPIO0_N | ✅ | Differential pair GPIO0_P/N correctly connected to Bank 34 DQS-capable I/O pins. | | T17 | IO_L20P_T3_34 | N23971584 | ✅ | HDMI_HSYNC and HDMI_D12 connected to differential pair pins, with HDMI_HSYNC having 22.1Ω series termination. | | R18 | IO_L20N_T3_34 | HDMI_D12 | ✅ | HDMI_HSYNC and HDMI_D12 connected to differential pair pins, with HDMI_HSYNC having 22.1Ω series termination. | | T19 | IO_25_34 | HDMI_D17 | ✅ | HDMI_D17 connected to Bank 34 additional I/O pin. | | T20 | IO_L15P_T2_DQS_34 | HDMI_D23 | ✅ | HDMI data signals D23 and D22 connected to differential pair DQS-capable pins. | | U20 | IO_L15N_T2_DQS_34 | HDMI_D22 | ✅ | HDMI data signals D23 and D22 connected to differential pair DQS-capable pins. | | U13 | IO_L3P_T0_DQS_PUDC_B_34 | GPIO8_P | ✅ | Differential pair GPIO8_P/N connected to Bank 34 I/O pins with 1K pull-down resistor on GPIO8_P. | | V13 | IO_L3N_T0_DQS_34 | GPIO8_N | ✅ | Differential pair GPIO8_P/N connected to Bank 34 I/O pins with 1K pull-down resistor on GPIO8_P. | | U14 | IO_L11P_T1_SRCC_34 | GPIO6_P | ✅ | Differential pair GPIO6_P/N correctly connected to Bank 34 SRCC-capable I/O pins. | | U15 | IO_L11N_T1_SRCC_34 | GPIO6_N | ✅ | Differential pair GPIO6_P/N correctly connected to Bank 34 SRCC-capable I/O pins. | | U18 | IO_L12P_T1_MRCC_34 | GPIO3_P | ✅ | Differential pair GPIO3_P/N correctly connected to Bank 34 MRCC-capable I/O pins. | | U19 | IO_L12N_T1_MRCC_34 | GPIO3_N | ✅ | Differential pair GPIO3_P/N correctly connected to Bank 34 MRCC-capable I/O pins. | | V12 | IO_L4P_T0_34 | GPIO9_P | ✅ | Differential pair GPIO9_P/N correctly connected to Bank 34 I/O pins. | | W13 | IO_L4N_T0_34 | GPIO9_N | ✅ | Differential pair GPIO9_P/N correctly connected to Bank 34 I/O pins. | | V15 | IO_L10P_T1_34 | HDMI_D11 | ✅ | HDMI data signals D11 and D16 connected to differential pair pins. | | W15 | IO_L10N_T1_34 | HDMI_D16 | ✅ | HDMI data signals D11 and D16 connected to differential pair pins. | | V16 | IO_L18P_T2_34 | GPIO1_P | ✅ | Differential pair GPIO1_P/N correctly connected to Bank 34 I/O pins. | | W16 | IO_L18N_T2_34 | GPIO1_N | ✅ | Differential pair GPIO1_P/N correctly connected to Bank 34 I/O pins. | | V17 | IO_L21P_T3_DQS_34 | N23969750 | ✅ | HDMI_VSYNC and HDMI_D10 connected to differential pair DQS-capable pins, with HDMI_VSYNC having 22.1Ω series termination. | | V18 | IO_L21N_T3_DQS_34 | HDMI_D10 | ✅ | HDMI_VSYNC and HDMI_D10 connected to differential pair DQS-capable pins, with HDMI_VSYNC having 22.1Ω series termination. | | V20 | IO_L16P_T2_34 | HDMI_D21 | ✅ | HDMI data signals D21 and D20 connected to differential pair pins. | | W20 | IO_L16N_T2_34 | HDMI_D20 | ✅ | HDMI data signals D21 and D20 connected to differential pair pins. | | W14 | IO_L8P_T1_34 | GPIO7_P | ✅ | Differential pair GPIO7_P/N correctly connected to Bank 34 I/O pins. | | Y14 | IO_L8N_T1_34 | GPIO7_N | ✅ | Differential pair GPIO7_P/N correctly connected to Bank 34 I/O pins. | | W18 | IO_L22P_T3_34 | HDMI_D9 | ✅ | HDMI data signals D9 and D15 connected to differential pair pins. | | W19 | IO_L22N_T3_34 | HDMI_D15 | ✅ | HDMI data signals D9 and D15 connected to differential pair pins. | | Y16 | IO_L7P_T1_34 | N23961346 | ✅ | Differential pair connected through series resistors R82 (to SPDIF) and R94 (to HDMI_DE) for source termination. | | Y17 | IO_L7N_T1_34 | N23963188 | ✅ | Differential pair connected through series resistors R82 (to SPDIF) and R94 (to HDMI_DE) for source termination. | | Y18 | IO_L17P_T2_34 | HDMI_D8 | ✅ | HDMI data signals D8 and D14 connected to differential pair pins. | | Y19 | IO_L17N_T2_34 | HDMI_D14 | ✅ | HDMI data signals D8 and D14 connected to differential pair pins. | </details> <details> <summary><b>R44</b> - RES0402_22R1 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040222R1FKED) Part Number: `CRCW040222R1FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23971584 | ✅ | 22.1Ω series termination resistor between FPGA pin T17 (IO_L20P_T3_34) and HDMI_HSYNC output. Pin 1 connects to internal net N23971584 from U2 pin T17, pin 2 connects to HDMI_HSYNC. | | 2 | 2 | HDMI_HSYNC | ✅ | 22.1Ω series termination resistor between FPGA pin T17 (IO_L20P_T3_34) and HDMI_HSYNC output. Pin 1 connects to internal net N23971584 from U2 pin T17, pin 2 connects to HDMI_HSYNC. | </details> <details> <summary><b>R41</b> - RES0402_22R1 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040222R1FKED) Part Number: `CRCW040222R1FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23973428 | ✅ | 22.1Ω series termination resistor between FPGA pin R17 (IO_L19N_T3_VREF_34) and HDMI_CLK output. Pin 1 connects to internal net N23973428 from U2 pin R17, pin 2 connects to HDMI_CLK. | | 2 | 2 | HDMI_CLK | ✅ | 22.1Ω series termination resistor between FPGA pin R17 (IO_L19N_T3_VREF_34) and HDMI_CLK output. Pin 1 connects to internal net N23973428 from U2 pin R17, pin 2 connects to HDMI_CLK. | </details> <details> <summary><b>R82</b> - RES0402_22R1 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040222R1FKED) Part Number: `CRCW040222R1FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23961346 | ✅ | 22.1Ω series termination resistor between FPGA pin Y16 (IO_L7P_T1_34) and SPDIF output. Pin 1 connects to internal net N23961346 from U2 pin Y16, pin 2 connects to SPDIF. | | 2 | 2 | SPDIF | ✅ | 22.1Ω series termination resistor between FPGA pin Y16 (IO_L7P_T1_34) and SPDIF output. Pin 1 connects to internal net N23961346 from U2 pin Y16, pin 2 connects to SPDIF. | </details> <details> <summary><b>R94</b> - RES0402_22R1 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040222R1FKED) Part Number: `CRCW040222R1FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23963188 | ✅ | 22.1Ω series termination resistor between FPGA pin Y17 (IO_L7N_T1_34) and HDMI_DE output. Pin 1 connects to internal net N23963188 from U2 pin Y17, pin 2 connects to HDMI_DE. | | 2 | 2 | HDMI_DE | ✅ | 22.1Ω series termination resistor between FPGA pin Y17 (IO_L7N_T1_34) and HDMI_DE output. Pin 1 connects to internal net N23963188 from U2 pin Y17, pin 2 connects to HDMI_DE. | </details> <details> <summary><b>R42</b> - RES0402_22R1 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040222R1FKED) Part Number: `CRCW040222R1FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23969750 | ✅ | 22.1Ω series termination resistor between FPGA pin V17 (IO_L21P_T3_DQS_34) and HDMI_VSYNC output. Pin 1 connects to internal net N23969750 from U2 pin V17, pin 2 connects to HDMI_VSYNC. | | 2 | 2 | HDMI_VSYNC | ✅ | 22.1Ω series termination resistor between FPGA pin V17 (IO_L21P_T3_DQS_34) and HDMI_VSYNC output. Pin 1 connects to internal net N23969750 from U2 pin V17, pin 2 connects to HDMI_VSYNC. | </details> <details> <summary><b>R18</b> ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04024K75FKED) Part Number: `CRCW04024K75FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDD_GPIO | ❌ | <details><summary>Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="da9371496a49e0f28b40" diff-visibility="full" variant="default" view-coords="46.25,41.65,53.75,49.15" aspect-ratio="1.33" } <ul><li>Pin 1 is connected to net VDD_GPIO <em>(from schematic)</em></li><li>R18 is a 4.75kΩ resistor functioning as a pull-up resistor <em>(reasoning)</em></li><li>The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO <em>(from schematic)</em></li><li>All decoupling capacitors for Bank 34 (C126-C134) are connected to VD_GPIO <em>(from schematic)</em></li><li>Pull-up resistors for I/O pins should be connected to the same voltage rail as the bank&#x27;s VCCO supply to ensure proper voltage levels <em>(reasoning)</em></li><li>No other components on this schematic page are connected to VDD_GPIO, suggesting it may be a net naming error <em>(from schematic)</em></li><li>R18 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage <em>(reasoning)</em></li></ul></details> | | 2 | 2 | N9 | ✅ | Pin 2 is correctly connected to net N9, which connects to Zynq pin N17 (IO_L23P_T3_34), forming a pull-up resistor configuration. | </details> <details> <summary><b>R20</b> ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04024K75FKED) Part Number: `CRCW04024K75FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDD_GPIO | ❌ | <details><summary>Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34 and ensure proper I2C operation.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="da9371496a49e0f28b40" diff-visibility="full" variant="default" view-coords="46.25,13.37,53.75,20.87" aspect-ratio="1.33" } <ul><li>Pin 1 is connected to net VDD_GPIO <em>(from schematic)</em></li><li>R20 is a 4.75kΩ resistor functioning as an I2C SCL pull-up resistor <em>(reasoning)</em></li><li>The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO <em>(from schematic)</em></li><li>I2C pull-up resistors should be connected to the same voltage rail as the I/O pins to ensure proper logic levels <em>(reasoning)</em></li><li>The I2C SCL signal connects to U2 pin N18 (IO_L13P_T2_MRCC_34) which is in Bank 34 <em>(from schematic)</em></li><li>R20 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage <em>(reasoning)</em></li></ul></details> | | 2 | 2 | PS_I2C_SCL | ✅ | Pin 2 is correctly connected to PS_I2C_SCL, which connects to Zynq pin N18 (IO_L13P_T2_MRCC_34), forming a proper I2C pull-up configuration. | </details> <details> <summary><b>R223</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04021K00FKED) Part Number: `CRCW04021K00FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming one terminal of a pull-down resistor for GPIO8_P signal. | | 2 | 2 | GPIO8_P | ✅ | Connected to GPIO8_P signal (U2 pin U13), forming a pull-down resistor. This configuration is unusual for a differential pair signal but may be intentional for pre-configuration state control. | </details> <details> <summary><b>R178</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04021K00FKED) Part Number: `CRCW04021K00FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming one terminal of a pull-down resistor for DSP_RESET_L signal. | | 2 | 2 | DSP_RESET_L | ✅ | Connected to DSP_RESET_L signal (U2 pin G14), forming a pull-down resistor to hold the reset signal low when not actively driven. | </details> <details> <summary><b>U23</b> - 16-CORE MICROPROCESSOR ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.parallella.org/docs/parallella_manual.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/E16G301) Part Number: `E16G301` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B5 | RXI_NO_DATA_N5 | RXI_NO_DATA5_N | ❌ | <details><summary>RXI_NO_DATA5 differential pair appears to be missing series resistors. All other data pairs have 100-ohm series resistors (R194-R198, R200-R201), but R199 is absent from the component list.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="cec4189011063486798f" diff-visibility="full" variant="default" view-coords="38.33,21.26,45.83,28.76" aspect-ratio="1.33" } <ul><li>Pin B5 (RXI_NO_DATA_N5) is connected to net RXI_NO_DATA5_N <em>(from schematic)</em></li><li>Pin B6 (RXI_NO_DATA_P5) is connected to net RXI_NO_DATA5_P <em>(from schematic)</em></li><li>All other RXI_NO_DATA pairs (0-4, 6-7) have 100-ohm series resistors <em>(from schematic)</em></li><li>There is a gap in resistor numbering from R198 to R200, where R199 would be expected for DATA5 <em>(from schematic)</em></li><li>The nets RXI_NO_DATA5_N and RXI_NO_DATA5_P are labeled on the schematic, suggesting they should be connected <em>(from schematic)</em></li><li>No components on this page are connected to the RXI_NO_DATA5 nets <em>(from schematic)</em></li><li>The missing series resistors are likely an error unless DATA5 is intentionally unused in this design <em>(reasoning)</em></li><li>If DATA5 is used, 100-ohm series resistors should be added consistent with the other data pairs <em>(reasoning)</em></li></ul></details> | | B6 | RXI_NO_DATA_P5 | RXI_NO_DATA5_P | ❌ | <details><summary>RXI_NO_DATA5 differential pair appears to be missing series resistors. All other data pairs have 100-ohm series resistors (R194-R198, R200-R201), but R199 is absent from the component list.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="cec4189011063486798f" diff-visibility="full" variant="default" view-coords="38.33,20.60,45.83,28.10" aspect-ratio="1.33" } <ul><li>Pin B5 (RXI_NO_DATA_N5) is connected to net RXI_NO_DATA5_N <em>(from schematic)</em></li><li>Pin B6 (RXI_NO_DATA_P5) is connected to net RXI_NO_DATA5_P <em>(from schematic)</em></li><li>All other RXI_NO_DATA pairs (0-4, 6-7) have 100-ohm series resistors <em>(from schematic)</em></li><li>There is a gap in resistor numbering from R198 to R200, where R199 would be expected for DATA5 <em>(from schematic)</em></li><li>The nets RXI_NO_DATA5_N and RXI_NO_DATA5_P are labeled on the schematic, suggesting they should be connected <em>(from schematic)</em></li><li>No components on this page are connected to the RXI_NO_DATA5 nets <em>(from schematic)</em></li><li>The missing series resistors are likely an error unless DATA5 is intentionally unused in this design <em>(reasoning)</em></li><li>If DATA5 is used, 100-ohm series resistors should be added consistent with the other data pairs <em>(reasoning)</em></li></ul></details> | | A2 | RXI_NO_DATA_N0 | RXI_NO_DATA0_N | ✅ | RXI_NO_DATA0 differential pair correctly connected through 100-ohm series resistor R194 for LVDS signal integrity. | | A3 | RXI_NO_DATA_P0 | RXI_NO_DATA0_P | ✅ | RXI_NO_DATA0 differential pair correctly connected through 100-ohm series resistor R194 for LVDS signal integrity. | | A4 | RXI_NO_DATA_N4 | RXI_NO_DATA4_N | ✅ | RXI_NO_DATA4 differential pair correctly connected through 100-ohm series resistor R198 for LVDS signal integrity. | | A5 | RXI_NO_DATA_P4 | RXI_NO_DATA4_P | ✅ | RXI_NO_DATA4 differential pair correctly connected through 100-ohm series resistor R198 for LVDS signal integrity. | | A6 | RXI_NO_LCLK_N | RXI_NO_LCLK_N | ✅ | RXI_NO_LCLK differential pair correctly connected through 100-ohm series resistor R203 for LVDS clock signal integrity. | | A7 | RXI_NO_LCLK_P | RXI_NO_LCLK_P | ✅ | RXI_NO_LCLK differential pair correctly connected through 100-ohm series resistor R203 for LVDS clock signal integrity. | | A9 | RXI_NO_CCLK_N | N23150336 | ✅ | RXI_NO_CCLK differential clock input pair tied to static DC levels (P to GND via R289, N to 1P8V via R290). This configuration appears to intentionally disable the clock input, likely because this interface is not used or an alternative clock source is employed. | | A10 | RXI_NO_CCLK_P | N23150334 | ✅ | RXI_NO_CCLK differential clock input pair tied to static DC levels (P to GND via R289, N to 1P8V via R290). This configuration appears to intentionally disable the clock input, likely because this interface is not used or an alternative clock source is employed. | | A12 | TXO_NO_LCLK_N | TXO_NO_LCLK_N | ✅ | TXO_NO_LCLK differential pair connected to output nets. DNI resistor R206 would provide series termination if installed. | | A13 | TXO_NO_LCLK_P | TXO_NO_LCLK_P | ✅ | TXO_NO_LCLK differential pair connected to output nets. DNI resistor R206 would provide series termination if installed. | | A14 | TXO_NO_DATA_N3 | TXO_NO_DATA3_N | ✅ | TXO_NO_DATA3 differential pair connected to output nets. DNI resistor R230 would provide series termination if installed. | | A15 | TXO_NO_DATA_P3 | TXO_NO_DATA3_P | ✅ | TXO_NO_DATA3 differential pair connected to output nets. DNI resistor R230 would provide series termination if installed. | | A16 | TXO_NO_DATA_N7 | TXO_NO_DATA7_N | ✅ | TXO_NO_DATA7 differential pair connected to output nets. DNI resistor R226 would provide series termination if installed. | | A17 | TXO_NO_DATA_P7 | TXO_NO_DATA7_P | ✅ | TXO_NO_DATA7 differential pair connected to output nets. DNI resistor R226 would provide series termination if installed. | | B3 | RXI_NO_DATA_N1 | RXI_NO_DATA1_N | ✅ | RXI_NO_DATA1 differential pair correctly connected through 100-ohm series resistor R195 for LVDS signal integrity. | | B4 | RXI_NO_DATA_P1 | RXI_NO_DATA1_P | ✅ | RXI_NO_DATA1 differential pair correctly connected through 100-ohm series resistor R195 for LVDS signal integrity. | | B7 | RXI_NO_FRAME_N | RXI_NO_FRAME_N | ✅ | RXI_NO_FRAME differential pair correctly connected through 100-ohm series resistor R202 with appropriate pull resistors (R242 to 1P8V on N, R243 to GND on P) for idle state. | | B8 | RXI_NO_FRAME_P | RXI_NO_FRAME_P | ✅ | RXI_NO_FRAME differential pair correctly connected through 100-ohm series resistor R202 with appropriate pull resistors (R242 to 1P8V on N, R243 to GND on P) for idle state. | | B9 | RXO_NO_RD_WAIT_N | RXO_NO_RD_WAIT_N | ✅ | RXO_NO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed. | | B10 | RXO_NO_RD_WAIT_P | RXO_NO_RD_WAIT_P | ✅ | RXO_NO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed. | | B11 | TXI_NO_RD_WAIT_N | TXI_NO_RD_WAIT_N | ✅ | TXI_NO_RD_WAIT differential input correctly connected through 100-ohm series resistor R204 with appropriate pull resistors (R241 to 1P8V on P, R240 to GND on N) for idle state. | | B12 | TXI_NO_RD_WAIT_P | TXI_NO_RD_WAIT_P | ✅ | TXI_NO_RD_WAIT differential input correctly connected through 100-ohm series resistor R204 with appropriate pull resistors (R241 to 1P8V on P, R240 to GND on N) for idle state. | | B13 | TXO_NO_DATA_N2 | TXO_NO_DATA2_N | ✅ | TXO_NO_DATA2 differential pair connected to output nets. DNI resistor R231 would provide series termination if installed. | | B14 | TXO_NO_DATA_P2 | TXO_NO_DATA2_P | ✅ | TXO_NO_DATA2 differential pair connected to output nets. DNI resistor R231 would provide series termination if installed. | | B15 | TXO_NO_DATA_N6 | TXO_NO_DATA6_N | ✅ | TXO_NO_DATA6 differential pair connected to output nets. DNI resistor R227 would provide series termination if installed. | | B16 | TXO_NO_DATA_P6 | TXO_NO_DATA6_P | ✅ | TXO_NO_DATA6 differential pair connected to output nets. DNI resistor R227 would provide series termination if installed. | | C4 | RXI_NO_DATA_N2 | RXI_NO_DATA2_N | ✅ | RXI_NO_DATA2 differential pair correctly connected through 100-ohm series resistor R196 for LVDS signal integrity. | | C5 | RXI_NO_DATA_P2 | RXI_NO_DATA2_P | ✅ | RXI_NO_DATA2 differential pair correctly connected through 100-ohm series resistor R196 for LVDS signal integrity. | | C6 | RXI_NO_DATA_N6 | RXI_NO_DATA6_N | ✅ | RXI_NO_DATA6 differential pair correctly connected through 100-ohm series resistor R200 for LVDS signal integrity. | | C7 | RXI_NO_DATA_P6 | RXI_NO_DATA6_P | ✅ | RXI_NO_DATA6 differential pair correctly connected through 100-ohm series resistor R200 for LVDS signal integrity. | | C8 | RXO_NO_WR_WAIT_N | RXO_NO_WR_WAIT_N | ✅ | RXO_NO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed. | | C9 | RXO_NO_WR_WAIT_P | RXO_NO_WR_WAIT_P | ✅ | RXO_NO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed. | | C10 | TXI_NO_WR_WAIT_N | TXI_NO_WR_WAIT_N | ✅ | TXI_NO_WR_WAIT differential input correctly connected through 100-ohm series resistor R205 for LVDS signal integrity. | | C11 | TXI_NO_WR_WAIT_P | TXI_NO_WR_WAIT_P | ✅ | TXI_NO_WR_WAIT differential input correctly connected through 100-ohm series resistor R205 for LVDS signal integrity. | | C12 | TXO_NO_DATA_N1 | TXO_NO_DATA1_N | ✅ | TXO_NO_DATA1 differential pair connected to output nets. DNI resistor R232 would provide series termination if installed. | | C13 | TXO_NO_DATA_P1 | TXO_NO_DATA1_P | ✅ | TXO_NO_DATA1 differential pair connected to output nets. DNI resistor R232 would provide series termination if installed. | | C14 | TXO_NO_DATA_N5 | TXO_NO_DATA5_N | ✅ | TXO_NO_DATA5 differential pair connected to output nets. DNI resistor R228 would provide series termination if installed. | | C15 | TXO_NO_DATA_P5 | TXO_NO_DATA5_P | ✅ | TXO_NO_DATA5 differential pair connected to output nets. DNI resistor R228 would provide series termination if installed. | | D5 | RXI_NO_DATA_N3 | RXI_NO_DATA3_N | ✅ | RXI_NO_DATA3 differential pair correctly connected through 100-ohm series resistor R197 for LVDS signal integrity. | | D6 | RXI_NO_DATA_P3 | RXI_NO_DATA3_P | ✅ | RXI_NO_DATA3 differential pair correctly connected through 100-ohm series resistor R197 for LVDS signal integrity. | | D7 | RXI_NO_DATA_N7 | RXI_NO_DATA7_N | ✅ | RXI_NO_DATA7 differential pair correctly connected through 100-ohm series resistor R201 for LVDS signal integrity. | | D8 | RXI_NO_DATA_P7 | RXI_NO_DATA7_P | ✅ | RXI_NO_DATA7 differential pair correctly connected through 100-ohm series resistor R201 for LVDS signal integrity. | | D9 | TXO_NO_FRAME_N | TXO_NO_FRAME_N | ✅ | TXO_NO_FRAME differential output pair connected to output nets. | | D10 | TXO_NO_FRAME_P | TXO_NO_FRAME_P | ✅ | TXO_NO_FRAME differential output pair connected to output nets. | | D11 | TXO_NO_DATA_N0 | TXO_NO_DATA0_N | ✅ | TXO_NO_DATA0 differential pair connected to output nets. DNI resistor R233 would provide series termination if installed. | | D12 | TXO_NO_DATA_P0 | TXO_NO_DATA0_P | ✅ | TXO_NO_DATA0 differential pair connected to output nets. DNI resistor R233 would provide series termination if installed. | | D13 | TXO_NO_DATA_N4 | TXO_NO_DATA4_N | ✅ | TXO_NO_DATA4 differential pair connected to output nets. DNI resistor R229 would provide series termination if installed. | | D14 | TXO_NO_DATA_P4 | TXO_NO_DATA4_P | ✅ | TXO_NO_DATA4 differential pair connected to output nets. DNI resistor R229 would provide series termination if installed. | | R5 | RXI_SO_DATA_P3 | RXI_SO_DATA3_P | ✅ | RXI_SO_DATA3 differential pair correctly connected through 100-ohm series resistor R210 for LVDS signal integrity. | | R6 | RXI_SO_DATA_N3 | RXI_SO_DATA3_N | ✅ | RXI_SO_DATA3 differential pair correctly connected through 100-ohm series resistor R210 for LVDS signal integrity. | | R7 | RXI_SO_DATA_P7 | RXI_SO_DATA7_P | ✅ | RXI_SO_DATA7 differential pair correctly connected through 100-ohm series resistor R214 for LVDS signal integrity. | | R8 | RXI_SO_DATA_N7 | RXI_SO_DATA7_N | ✅ | RXI_SO_DATA7 differential pair correctly connected through 100-ohm series resistor R214 for LVDS signal integrity. | | R9 | TXO_SO_FRAME_P | TXO_SO_FRAME_P | ✅ | TXO_SO_FRAME differential output correctly connected through 100-ohm series resistor R236 with appropriate pull resistors (R244 to 1P8V on N, R245 to GND on P) for idle state. | | R10 | TXO_SO_FRAME_N | TXO_SO_FRAME_N | ✅ | TXO_SO_FRAME differential output correctly connected through 100-ohm series resistor R236 with appropriate pull resistors (R244 to 1P8V on N, R245 to GND on P) for idle state. | | R11 | TXO_SO_DATA_P0 | TXO_SO_DATA0_P | ✅ | TXO_SO_DATA0 differential output pair connected to output nets. | | R12 | TXO_SO_DATA_N0 | TXO_SO_DATA0_N | ✅ | TXO_SO_DATA0 differential output pair connected to output nets. | | R13 | TXO_SO_DATA_P4 | TXO_SO_DATA4_P | ✅ | TXO_SO_DATA4 differential output pair connected to output nets. | | R14 | TXO_SO_DATA_N4 | TXO_SO_DATA4_N | ✅ | TXO_SO_DATA4 differential output pair connected to output nets. | | T4 | RXI_SO_DATA_P2 | RXI_SO_DATA2_P | ✅ | RXI_SO_DATA2 differential pair correctly connected through 100-ohm series resistor R209 for LVDS signal integrity. | | T5 | RXI_SO_DATA_N2 | RXI_SO_DATA2_N | ✅ | RXI_SO_DATA2 differential pair correctly connected through 100-ohm series resistor R209 for LVDS signal integrity. | | T6 | RXI_SO_DATA_P6 | RXI_SO_DATA6_P | ✅ | RXI_SO_DATA6 differential pair correctly connected through 100-ohm series resistor R213 for LVDS signal integrity. | | T7 | RXI_SO_DATA_N6 | RXI_SO_DATA6_N | ✅ | RXI_SO_DATA6 differential pair correctly connected through 100-ohm series resistor R213 for LVDS signal integrity. | | T8 | RXO_SO_WR_WAIT_P | RXO_SO_WR_WAIT_P | ✅ | RXO_SO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed. | | T9 | RXO_SO_WR_WAIT_N | RXO_SO_WR_WAIT_N | ✅ | RXO_SO_WR_WAIT differential output pair. DNI resistor R235 would provide series termination if installed. | | T10 | TXI_SO_WR_WAIT_P | TXI_SO_WR_WAIT_P | ✅ | TXI_SO_WR_WAIT differential input correctly connected through 100-ohm series resistor R218 for LVDS signal integrity. | | T11 | TXI_SO_WR_WAIT_N | TXI_SO_WR_WAIT_N | ✅ | TXI_SO_WR_WAIT differential input correctly connected through 100-ohm series resistor R218 for LVDS signal integrity. | | T12 | TXO_SO_DATA_P1 | TXO_SO_DATA1_P | ✅ | TXO_SO_DATA1 differential output pair connected to output nets. | | T13 | TXO_SO_DATA_N1 | TXO_SO_DATA1_N | ✅ | TXO_SO_DATA1 differential output pair connected to output nets. | | T14 | TXO_SO_DATA_P5 | TXO_SO_DATA5_P | ✅ | TXO_SO_DATA5 differential output pair connected to output nets. | | T15 | TXO_SO_DATA_N5 | TXO_SO_DATA5_N | ✅ | TXO_SO_DATA5 differential output pair connected to output nets. | | U3 | RXI_SO_DATA_P1 | RXI_SO_DATA1_P | ✅ | RXI_SO_DATA1 differential pair correctly connected through 100-ohm series resistor R208 for LVDS signal integrity. | | U4 | RXI_SO_DATA_N1 | RXI_SO_DATA1_N | ✅ | RXI_SO_DATA1 differential pair correctly connected through 100-ohm series resistor R208 for LVDS signal integrity. | | U5 | RXI_SO_DATA_P5 | RXI_SO_DATA5_P | ✅ | RXI_SO_DATA5 differential pair correctly connected through 100-ohm series resistor R212 for LVDS signal integrity. | | U6 | RXI_SO_DATA_N5 | RXI_SO_DATA5_N | ✅ | RXI_SO_DATA5 differential pair correctly connected through 100-ohm series resistor R212 for LVDS signal integrity. | | U7 | RXI_SO_FRAME_P | RXI_SO_FRAME_P | ✅ | RXI_SO_FRAME differential pair correctly connected through 100-ohm series resistor R215 with appropriate pull resistors (R247 to 1P8V on N, R246 to GND on P) for idle state. | | U8 | RXI_SO_FRAME_N | RXI_SO_FRAME_N | ✅ | RXI_SO_FRAME differential pair correctly connected through 100-ohm series resistor R215 with appropriate pull resistors (R247 to 1P8V on N, R246 to GND on P) for idle state. | | U9 | RXO_SO_RD_WAIT_P | RXO_SO_RD_WAIT_P | ✅ | RXO_SO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed. | | U10 | RXO_SO_RD_WAIT_N | RXO_SO_RD_WAIT_N | ✅ | RXO_SO_RD_WAIT differential output pair. DNI resistor R234 would provide series termination if installed. | | U11 | TXI_SO_RD_WAIT_P | TXI_SO_RD_WAIT_P | ✅ | TXI_SO_RD_WAIT differential input correctly connected through 100-ohm series resistor R217 for LVDS signal integrity. | | U12 | TXI_SO_RD_WAIT_N | TXI_SO_RD_WAIT_N | ✅ | TXI_SO_RD_WAIT differential input correctly connected through 100-ohm series resistor R217 for LVDS signal integrity. | | U13 | TXO_SO_DATA_P2 | TXO_SO_DATA2_P | ✅ | TXO_SO_DATA2 differential output pair connected to output nets. | | U14 | TXO_SO_DATA_N2 | TXO_SO_DATA2_N | ✅ | TXO_SO_DATA2 differential output pair connected to output nets. | | U15 | TXO_SO_DATA_P6 | TXO_SO_DATA6_P | ✅ | TXO_SO_DATA6 differential output pair connected to output nets. | | U16 | TXO_SO_DATA_N6 | TXO_SO_DATA6_N | ✅ | TXO_SO_DATA6 differential output pair connected to output nets. | | V2 | RXI_SO_DATA_P0 | RXI_SO_DATA0_P | ✅ | RXI_SO_DATA0 differential pair correctly connected through 100-ohm series resistor R207 for LVDS signal integrity. | | V3 | RXI_SO_DATA_N0 | RXI_SO_DATA0_N | ✅ | RXI_SO_DATA0 differential pair correctly connected through 100-ohm series resistor R207 for LVDS signal integrity. | | V4 | RXI_SO_DATA_P4 | RXI_SO_DATA4_P | ✅ | RXI_SO_DATA4 differential pair correctly connected through 100-ohm series resistor R211 for LVDS signal integrity. | | V5 | RXI_SO_DATA_N4 | RXI_SO_DATA4_N | ✅ | RXI_SO_DATA4 differential pair correctly connected through 100-ohm series resistor R211 for LVDS signal integrity. | | V6 | RXI_SO_LCLK_P | RXI_SO_LCLK_P | ✅ | RXI_SO_LCLK differential pair correctly connected through 100-ohm series resistor R216 for LVDS clock signal integrity. | | V7 | RXI_SO_LCLK_N | RXI_SO_LCLK_N | ✅ | RXI_SO_LCLK differential pair correctly connected through 100-ohm series resistor R216 for LVDS clock signal integrity. | | V9 | RXI_SO_CCLK_P | N23155371 | ✅ | RXI_SO_CCLK differential clock input pair tied to static DC levels (P to GND via R291, N to 1P8V via R292). This configuration appears to intentionally disable the clock input, matching the treatment of the North interface CCLK pins. | | V10 | RXI_SO_CCLK_N | N23155373 | ✅ | RXI_SO_CCLK differential clock input pair tied to static DC levels (P to GND via R291, N to 1P8V via R292). This configuration appears to intentionally disable the clock input, matching the treatment of the North interface CCLK pins. | | V12 | TXO_SO_LCLK_P | TXO_SO_LCLK_P | ✅ | TXO_SO_LCLK differential output pair connected to output nets. | | V13 | TXO_SO_LCLK_N | TXO_SO_LCLK_N | ✅ | TXO_SO_LCLK differential output pair connected to output nets. | | V14 | TXO_SO_DATA_P3 | TXO_SO_DATA3_P | ✅ | TXO_SO_DATA3 differential output pair connected to output nets. | | V15 | TXO_SO_DATA_N3 | TXO_SO_DATA3_N | ✅ | TXO_SO_DATA3 differential output pair connected to output nets. | | V16 | TXO_SO_DATA_P7 | TXO_SO_DATA7_P | ✅ | TXO_SO_DATA7 differential output pair connected to output nets. | | V17 | TXO_SO_DATA_N7 | TXO_SO_DATA7_N | ✅ | TXO_SO_DATA7 differential output pair connected to output nets. | </details> <details> <summary><b>R194</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_DATA0_P | ✅ | 100Ω differential termination resistor for RXI_NO_DATA0 LVDS pair. Connects between RXI_NO_DATA0_P (pin 1) and RXI_NO_DATA0_N (pin 2). | | 2 | 2 | RXI_NO_DATA0_N | ✅ | 100Ω differential termination resistor for RXI_NO_DATA0 LVDS pair. Connects between RXI_NO_DATA0_P (pin 1) and RXI_NO_DATA0_N (pin 2). | </details> <details> <summary><b>R195</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_DATA1_P | ✅ | 100Ω differential termination resistor for RXI_NO_DATA1 LVDS pair. Connects between RXI_NO_DATA1_P (pin 1) and RXI_NO_DATA1_N (pin 2). | | 2 | 2 | RXI_NO_DATA1_N | ✅ | 100Ω differential termination resistor for RXI_NO_DATA1 LVDS pair. Connects between RXI_NO_DATA1_P (pin 1) and RXI_NO_DATA1_N (pin 2). | </details> <details> <summary><b>R196</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_DATA2_P | ✅ | 100Ω differential termination resistor for RXI_NO_DATA2 LVDS pair. Connects between RXI_NO_DATA2_P (pin 1) and RXI_NO_DATA2_N (pin 2). | | 2 | 2 | RXI_NO_DATA2_N | ✅ | 100Ω differential termination resistor for RXI_NO_DATA2 LVDS pair. Connects between RXI_NO_DATA2_P (pin 1) and RXI_NO_DATA2_N (pin 2). | </details> <details> <summary><b>R197</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_DATA3_P | ✅ | 100Ω differential termination resistor for RXI_NO_DATA3 LVDS pair. Connects between RXI_NO_DATA3_P (pin 1) and RXI_NO_DATA3_N (pin 2). | | 2 | 2 | RXI_NO_DATA3_N | ✅ | 100Ω differential termination resistor for RXI_NO_DATA3 LVDS pair. Connects between RXI_NO_DATA3_P (pin 1) and RXI_NO_DATA3_N (pin 2). | </details> <details> <summary><b>R198</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_DATA4_P | ✅ | 100Ω differential termination resistor for RXI_NO_DATA4 LVDS pair. Connects between RXI_NO_DATA4_P (pin 1) and RXI_NO_DATA4_N (pin 2). | | 2 | 2 | RXI_NO_DATA4_N | ✅ | 100Ω differential termination resistor for RXI_NO_DATA4 LVDS pair. Connects between RXI_NO_DATA4_P (pin 1) and RXI_NO_DATA4_N (pin 2). | </details> <details> <summary><b>R200</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_DATA6_P | ✅ | 100Ω differential termination resistor for RXI_NO_DATA6 LVDS pair. Connects between RXI_NO_DATA6_P (pin 1) and RXI_NO_DATA6_N (pin 2). | | 2 | 2 | RXI_NO_DATA6_N | ✅ | 100Ω differential termination resistor for RXI_NO_DATA6 LVDS pair. Connects between RXI_NO_DATA6_P (pin 1) and RXI_NO_DATA6_N (pin 2). | </details> <details> <summary><b>R201</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_DATA7_P | ✅ | 100Ω differential termination resistor for RXI_NO_DATA7 LVDS pair. Connects between RXI_NO_DATA7_P (pin 1) and RXI_NO_DATA7_N (pin 2). | | 2 | 2 | RXI_NO_DATA7_N | ✅ | 100Ω differential termination resistor for RXI_NO_DATA7 LVDS pair. Connects between RXI_NO_DATA7_P (pin 1) and RXI_NO_DATA7_N (pin 2). | </details> <details> <summary><b>R203</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_LCLK_P | ✅ | 100Ω differential termination resistor for RXI_NO_LCLK LVDS pair. Connects between RXI_NO_LCLK_P (pin 1) and RXI_NO_LCLK_N (pin 2). | | 2 | 2 | RXI_NO_LCLK_N | ✅ | 100Ω differential termination resistor for RXI_NO_LCLK LVDS pair. Connects between RXI_NO_LCLK_P (pin 1) and RXI_NO_LCLK_N (pin 2). | </details> <details> <summary><b>R202</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RXI_NO_FRAME_P | ✅ | 100Ω differential termination resistor for RXI_NO_FRAME LVDS pair. Connects between RXI_NO_FRAME_P (pin 1) and RXI_NO_FRAME_N (pin 2). | | 2 | 2 | RXI_NO_FRAME_N | ✅ | 100Ω differential termination resistor for RXI_NO_FRAME LVDS pair. Connects between RXI_NO_FRAME_P (pin 1) and RXI_NO_FRAME_N (pin 2). | </details> <details> <summary><b>R204</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXI_NO_RD_WAIT_P | ✅ | 100Ω differential termination resistor for LVDS TXI_NO_RD_WAIT signal pair. Correctly placed between P and N signals with appropriate DC bias resistors. | | 2 | 2 | TXI_NO_RD_WAIT_N | ✅ | 100Ω differential termination resistor for LVDS TXI_NO_RD_WAIT signal pair. Correctly placed between P and N signals with appropriate DC bias resistors. | </details> <details> <summary><b>R205</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXI_NO_WR_WAIT_P | ✅ | 100Ω differential termination resistor for LVDS TXI_NO_WR_WAIT signal pair. Unlike the similar TXI_NO_RD_WAIT signal (R204), this pair lacks DC bias resistors, which may be intentional based on signal characteristics. | | 2 | 2 | TXI_NO_WR_WAIT_N | ✅ | 100Ω differential termination resistor for LVDS TXI_NO_WR_WAIT signal pair. Unlike the similar TXI_NO_RD_WAIT signal (R204), this pair lacks DC bias resistors, which may be intentional based on signal characteristics. | </details> <details> <summary><b>R217</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXI_SO_RD_WAIT_P | ✅ | 100 ohm differential termination resistor for TXI_SO_RD_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair. | | 2 | 2 | TXI_SO_RD_WAIT_N | ✅ | 100 ohm differential termination resistor for TXI_SO_RD_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair. | </details> <details> <summary><b>R218</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXI_SO_WR_WAIT_P | ✅ | 100 ohm differential termination resistor for TXI_SO_WR_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair. | | 2 | 2 | TXI_SO_WR_WAIT_N | ✅ | 100 ohm differential termination resistor for TXI_SO_WR_WAIT LVDS pair. Correctly placed at the receiver (U23) end of the differential pair. | </details> <details> <summary><b>R236</b> - RES0402_100 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402100RFKED) Part Number: `CRCW0402100RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXO_SO_FRAME_P | ✅ | 100 ohm differential termination resistor for TXO_SO_FRAME LVDS pair. Unusually placed at the transmitter (U23) rather than receiver, but appears intentional given this is a frame signal with special bias resistors and R236 is not marked DNI unlike other TXO termination resistors. | | 2 | 2 | TXO_SO_FRAME_N | ✅ | 100 ohm differential termination resistor for TXO_SO_FRAME LVDS pair. Unusually placed at the transmitter (U23) rather than receiver, but appears intentional given this is a frame signal with special bias resistors and R236 is not marked DNI unlike other TXO termination resistors. | </details> <details> <summary><b>R289</b> - RES0402_0 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04020000Z0ED) Part Number: `CRCW04020000Z0ED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0-ohm resistor connecting U23 pin A10 (RXI_NO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input. | | 2 | 2 | N23150334 | ✅ | 0-ohm resistor connecting U23 pin A10 (RXI_NO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input. | </details> <details> <summary><b>R290</b> - RES0402_0 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04020000Z0ED) Part Number: `CRCW04020000Z0ED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | 0-ohm resistor connecting U23 pin A9 (RXI_NO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input. | | 2 | 2 | N23150336 | ✅ | 0-ohm resistor connecting U23 pin A9 (RXI_NO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input. | </details> <details> <summary><b>R291</b> - RES0402_0 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04020000Z0ED) Part Number: `CRCW04020000Z0ED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0-ohm resistor connecting U23 pin V9 (RXI_SO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input. | | 2 | 2 | N23155371 | ✅ | 0-ohm resistor connecting U23 pin V9 (RXI_SO_CCLK_P) to GND. This ties the positive clock input to ground, creating a static DC level that effectively disables this clock input. | </details> <details> <summary><b>R292</b> - RES0402_0 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04020000Z0ED) Part Number: `CRCW04020000Z0ED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | 0-ohm resistor connecting U23 pin V10 (RXI_SO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input. | | 2 | 2 | N23155373 | ✅ | 0-ohm resistor connecting U23 pin V10 (RXI_SO_CCLK_N) to 1P8V. This ties the negative clock input to the positive supply, creating a static DC level that effectively disables this clock input. | </details> <details> <summary><b>R240</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXI_NO_RD_WAIT_N | ✅ | Pull-down resistor terminal connected to TXI_NO_RD_WAIT_N signal. This resistor, along with R241, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state. | | 2 | 2 | GND | ✅ | Pull-down resistor terminal connected to GND. This resistor, along with R241, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state. | </details> <details> <summary><b>R241</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXI_NO_RD_WAIT_P | ✅ | Pull-up resistor terminal connected to TXI_NO_RD_WAIT_P signal. This resistor, along with R240, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state. | | 2 | 2 | 1P8V | ✅ | Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R240, provides biasing for the differential WAIT signal input to U23, establishing a default 'ready' state. | </details> <details> <summary><b>R242</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R243, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | | 2 | 2 | RXI_NO_FRAME_N | ✅ | Pull-up resistor terminal connected to RXI_NO_FRAME_N signal. This resistor, along with R243, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | </details> <details> <summary><b>R243</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pull-down resistor terminal connected to GND. This resistor, along with R242, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | | 2 | 2 | RXI_NO_FRAME_P | ✅ | Pull-down resistor terminal connected to RXI_NO_FRAME_P signal. This resistor, along with R242, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | </details> <details> <summary><b>R244</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXO_SO_FRAME_N | ✅ | Pull-up resistor terminal connected to TXO_SO_FRAME_N signal. This resistor, along with R245, provides biasing for the differential FRAME signal output from U23. Note that bias resistors on LVDS outputs are unusual but may provide a default state when the driver is tri-stated or powered down. | | 2 | 2 | 1P8V | ✅ | Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R245, provides biasing for the differential FRAME signal output from U23. | </details> <details> <summary><b>R245</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TXO_SO_FRAME_P | ✅ | Pull-down resistor terminal connected to TXO_SO_FRAME_P signal. This resistor, along with R244, provides biasing for the differential FRAME signal output from U23. Note that bias resistors on LVDS outputs are unusual but may provide a default state when the driver is tri-stated or powered down. | | 2 | 2 | GND | ✅ | Pull-down resistor terminal connected to GND. This resistor, along with R244, provides biasing for the differential FRAME signal output from U23. | </details> <details> <summary><b>R246</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pull-down resistor terminal connected to GND. This resistor, along with R247, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | | 2 | 2 | RXI_SO_FRAME_P | ✅ | Pull-down resistor terminal connected to RXI_SO_FRAME_P signal. This resistor, along with R247, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | </details> <details> <summary><b>R247</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW040210K0FKED) Part Number: `CRCW040210K0FKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | Pull-up resistor terminal connected to 1P8V power rail. This resistor, along with R246, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | | 2 | 2 | RXI_SO_FRAME_N | ✅ | Pull-up resistor terminal connected to RXI_SO_FRAME_N signal. This resistor, along with R246, provides biasing for the differential FRAME signal input to U23, establishing a default 'no frame' state. | </details> <details> <summary><b>FB14</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/BLM15AG121SN1D/ENFA0018%2520%25281%2529.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/BLM15AG121SN1D) Part Number: `BLM15AG121SN1D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | Input terminal correctly connected to 1P8V supply rail. | | 2 | 2 | HDMI_DVDD | ✅ | Output terminal correctly connected to HDMI_DVDD power domain. | </details> <details> <summary><b>R237</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N25262962 | ✅ | Resistor terminal correctly connected to U26 PD/AD pin. | | 2 | 2 | GND | ✅ | Resistor terminal correctly connected to ground. | </details> <details> <summary><b>U26</b> - HDMI_DVI_XCVR_ADV7513 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/ADV7513BSWZ/adv7513_hardware_user_guide.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ADV7513BSWZ) Part Number: `ADV7513BSWZ` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DVDD1 | HDMI_DVDD | ✅ | DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling. | | 11 | DVDD2 | HDMI_DVDD | ✅ | DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling. | | 31 | DVDD3 | HDMI_DVDD | ✅ | DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling. | | 51 | DVDD4 | HDMI_DVDD | ✅ | DVDD pins correctly connected to 1.8V digital supply through ferrite bead with proper decoupling. | | 2 | VSYNC | HDMI_VSYNC | ✅ | VSYNC pin correctly connected to video sync input signal. | | 3 | SPDIF | SPDIF | ✅ | SPDIF pin correctly connected to S/PDIF audio input signal. | | 4 | MCLK | GND | ✅ | Audio input pins correctly grounded since I2S audio is not used in this design. | | 5 | I2S0 | GND | ✅ | Audio input pins correctly grounded since I2S audio is not used in this design. | | 6 | I2S1 | GND | ✅ | Audio input pins correctly grounded since I2S audio is not used in this design. | | 7 | I2S2 | GND | ✅ | Audio input pins correctly grounded since I2S audio is not used in this design. | | 8 | I2S3 | GND | ✅ | Audio input pins correctly grounded since I2S audio is not used in this design. | | 9 | SCLK | GND | ✅ | Audio input pins correctly grounded since I2S audio is not used in this design. | | 10 | LRCLK | GND | ✅ | Audio input pins correctly grounded since I2S audio is not used in this design. | | 12 | PVDD | HDMI_PVDD | ✅ | PVDD pin correctly connected to 1.8V PLL supply through ferrite bead with proper decoupling. | | 13 | BGVDD | HDMI_BGVDD | ✅ | BGVDD pin correctly connected to 1.8V bandgap supply through ferrite bead with proper decoupling. | | 14 | R_EXT | N23881678 | ✅ | R_EXT pin correctly connected to 887Ω reference resistor to ground as specified. | | 15 | AVDD1 | HDMI_AVDD | ✅ | AVDD pins correctly connected to 1.8V analog supply through ferrite bead with proper decoupling. | | 19 | AVDD2 | HDMI_AVDD | ✅ | AVDD pins correctly connected to 1.8V analog supply through ferrite bead with proper decoupling. | | 25 | AVDD3 | HDMI_AVDD | ✅ | AVDD pins correctly connected to 1.8V analog supply through ferrite bead with proper decoupling. | | 16 | HPD | HDMI_HPD | ✅ | HPD pin correctly connected to hot plug detect signal through U37 level shifter. | | 17 | TXC- | HDMI_TXC_N | ✅ | TXC+/TXC- pins correctly connected to TMDS clock outputs through U37 ESD protection to HDMI connector. | | 18 | TXC+ | HDMI_TXC_P | ✅ | TXC+/TXC- pins correctly connected to TMDS clock outputs through U37 ESD protection to HDMI connector. | | 20 | TX0- | HDMI_TX0_N | ✅ | TX0+/TX0- pins correctly connected to TMDS data channel 0 outputs through U37 ESD protection to HDMI connector. | | 21 | TX0+ | HDMI_TX0_P | ✅ | TX0+/TX0- pins correctly connected to TMDS data channel 0 outputs through U37 ESD protection to HDMI connector. | | 22 | PD | N25262962 | ✅ | PD/AD pin correctly connected to ground through 1kΩ resistor to set I2C address to 0x72 and active-high power-down. | | 23 | TX1- | HDMI_TX1_N | ✅ | TX1+/TX1- pins correctly connected to TMDS data channel 1 outputs through U37 ESD protection to HDMI connector. | | 24 | TX1+ | HDMI_TX1_P | ✅ | TX1+/TX1- pins correctly connected to TMDS data channel 1 outputs through U37 ESD protection to HDMI connector. | | 26 | TX2- | HDMI_TX2_N | ✅ | TX2+/TX2- pins correctly connected to TMDS data channel 2 outputs through U37 ESD protection to HDMI connector. | | 27 | TX2+ | HDMI_TX2_P | ✅ | TX2+/TX2- pins correctly connected to TMDS data channel 2 outputs through U37 ESD protection to HDMI connector. | | 28 | INT | HDMI_INT | ✅ | INT pin correctly connected to interrupt output with pullup resistor, though resistor value is higher than recommended. | | 29 | DVDD_3V | N23924961 | ✅ | DVDD_3V pin correctly connected to 3.3V supply through ferrite bead with proper decoupling. | | 30 | CEC | HDMI_CEC | ✅ | CEC pin correctly connected to CEC signal through U37 level shifter for proper voltage translation. | | 32 | CEC_CLK | HDMI_24M_CES_CLK | ✅ | CEC_CLK pin correctly connected to CEC clock input signal. | | 33 | DDCSCL | DDC_SCL | ✅ | DDCSCL/DDCSDA pins correctly connected to HDMI connector DDC interface with pullups, though pullup values are outside recommended range. | | 34 | DDCSDA | DDC_SDA | ✅ | DDCSCL/DDCSDA pins correctly connected to HDMI connector DDC interface with pullups, though pullup values are outside recommended range. | | 35 | SCL | I2C_SCL | ✅ | I2C slave interface (SCL/SDA) correctly connected through level shifter U37 from processor. Connection is functional due to 5V tolerance of ADV7513 I2C pins. | | 36 | SDA | I2C_SDA | ✅ | I2C slave interface (SCL/SDA) correctly connected through level shifter U37 from processor. Connection is functional due to 5V tolerance of ADV7513 I2C pins. | | 37 | D23 | HDMI_D23 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 38 | D22 | HDMI_D22 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 39 | D21 | HDMI_D21 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 40 | D20 | HDMI_D20 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 41 | D19 | HDMI_D19 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 42 | D18 | HDMI_D18 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 43 | D17 | HDMI_D17 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 44 | D16 | HDMI_D16 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 45 | D15 | HDMI_D15 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 46 | D14 | HDMI_D14 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 47 | D13 | HDMI_D13 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 48 | D12 | HDMI_D12 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 49 | D11 | HDMI_D11 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 50 | D10 | HDMI_D10 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 52 | D9 | HDMI_D9 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 54 | D8 | HDMI_D8 | ✅ | Video data input pins D23-D8 correctly connected to video data signals. | | 53 | CLK | HDMI_CLK | ✅ | CLK pin correctly connected to video clock input signal. | | 55 | D7 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 56 | D6 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 57 | D5 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 58 | D4 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 59 | D3 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 60 | D2 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 61 | D1 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 62 | D0 | | ✅ | Video data input pins D7-D0 are not connected. Datasheet recommends grounding unused video inputs. | | 63 | DE | HDMI_DE | ✅ | DE pin correctly connected to data enable signal input. | | 64 | HSYNC | HDMI_HSYNC | ✅ | HSYNC pin correctly connected to horizontal sync input signal. | | 65 | EPAD | GND | ✅ | EPAD pin correctly connected to ground plane. | </details> <details> <summary><b>FB16</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/BLM15AG121SN1D/ENFA0018%2520%25281%2529.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/BLM15AG121SN1D) Part Number: `BLM15AG121SN1D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23924961 | ✅ | Input terminal correctly connected to filtered 3.3V power domain. | | 2 | 2 | 3P3V | ✅ | Output terminal correctly connected to 3P3V supply rail. | </details> <details> <summary><b>FB17</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/BLM15AG121SN1D/ENFA0018%2520%25281%2529.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/BLM15AG121SN1D) Part Number: `BLM15AG121SN1D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | Input terminal correctly connected to 1P8V supply rail. | | 2 | 2 | HDMI_BGVDD | ✅ | Output terminal correctly connected to HDMI_BGVDD band gap power domain. | </details> <details> <summary><b>FB15</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/BLM15AG121SN1D/ENFA0018%2520%25281%2529.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/BLM15AG121SN1D) Part Number: `BLM15AG121SN1D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | Input terminal correctly connected to 1P8V supply rail. | | 2 | 2 | HDMI_AVDD | ✅ | Output terminal correctly connected to HDMI_AVDD analog power domain. | </details> <details> <summary><b>FB18</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/BLM15AG121SN1D/ENFA0018%2520%25281%2529.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/BLM15AG121SN1D) Part Number: `BLM15AG121SN1D` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | Input terminal correctly connected to 1P8V supply rail. | | 2 | 2 | HDMI_PVDD | ✅ | Output terminal correctly connected to HDMI_PVDD PLL power domain. | </details> <details> <summary><b>R224</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23881678 | ✅ | Resistor terminal correctly connected to U26 R_EXT pin. | | 2 | 2 | GND | ✅ | Resistor terminal correctly connected to ground. | </details> <details> <summary><b>U37</b> - TPD12S016 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/TPD12S016PWR) Part Number: `TPD12S016PWR` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CEC_A | HDMI_CEC | ✅ | CEC_A pin correctly connected to ADV7513 CEC output for level shifting to HDMI connector. | | 2 | SCL_A | PS_I2C_SCL | ✅ | SCL_A and SDA_A controller-side I2C signals correctly connected to processor I2C interface for ADV7513 configuration. | | 3 | SDA_A | PS_I2C_SDA | ✅ | SCL_A and SDA_A controller-side I2C signals correctly connected to processor I2C interface for ADV7513 configuration. | | 4 | HPD_A | HDMI_HPD | ✅ | HPD_A pin correctly connected to ADV7513 HPD input, buffering hot plug detect from connector. | | 5 | LS_OE | VDD_GPIO | ✅ | LS_OE pin correctly tied high to VDD_GPIO to enable level shifters. | | 6 | GND1 | GND | ✅ | Ground pins correctly connected to system ground plane. | | 14 | GND2 | GND | ✅ | Ground pins correctly connected to system ground plane. | | 19 | GND3 | GND | ✅ | Ground pins correctly connected to system ground plane. | | 7 | CEC_B | HDMI_CEC_B | ✅ | CEC_B pin correctly connected to HDMI connector CEC pin with internal pullup. | | 8 | SCL_B | I2C_SCL | ✅ | SCL_B and SDA_B connector-side I2C signals connected to ADV7513 I2C slave interface. This is an unconventional but functional design that uses U37 to level-shift configuration I2C rather than DDC interface. | | 9 | SDA_B | I2C_SDA | ✅ | SCL_B and SDA_B connector-side I2C signals connected to ADV7513 I2C slave interface. This is an unconventional but functional design that uses U37 to level-shift configuration I2C rather than DDC interface. | | 10 | HPD_B | HDMI_HPD_B | ✅ | HPD_B pin correctly connected to HDMI connector HPD pin with pulldown resistor. | | 11 | VCC_5V | SYS_5P0V | ✅ | VCC5V pin correctly connected to 5V supply with decoupling capacitor. | | 12 | CT_HPD | VDD_GPIO | ✅ | CT_HPD pin correctly tied high to VDD_GPIO to enable load switch and HPD. | | 13 | 5V_OUT | HDMI_5V | ✅ | 5V_OUT pin correctly connected to HDMI connector 5V pin with decoupling and pullup resistors. | | 15 | CLK- | HDMI_TXC_N | ✅ | CLK+/CLK- pins correctly connected for TMDS clock ESD protection between ADV7513 and HDMI connector. | | 16 | CLK+ | HDMI_TXC_P | ✅ | CLK+/CLK- pins correctly connected for TMDS clock ESD protection between ADV7513 and HDMI connector. | | 17 | D0- | HDMI_TX0_N | ✅ | D0+/D0- pins correctly connected for TMDS data channel 0 ESD protection between ADV7513 and HDMI connector. | | 18 | D0+ | HDMI_TX0_P | ✅ | D0+/D0- pins correctly connected for TMDS data channel 0 ESD protection between ADV7513 and HDMI connector. | | 20 | D1- | HDMI_TX1_N | ✅ | D1+/D1- pins correctly connected for TMDS data channel 1 ESD protection between ADV7513 and HDMI connector. | | 21 | D1+ | HDMI_TX1_P | ✅ | D1+/D1- pins correctly connected for TMDS data channel 1 ESD protection between ADV7513 and HDMI connector. | | 22 | D2- | HDMI_TX2_N | ✅ | D2+/D2- pins correctly connected for TMDS data channel 2 ESD protection between ADV7513 and HDMI connector. | | 23 | D2+ | HDMI_TX2_P | ✅ | D2+/D2- pins correctly connected for TMDS data channel 2 ESD protection between ADV7513 and HDMI connector. | | 24 | VCCA | VDD_GPIO | ✅ | VCCA pin correctly connected to VDD_GPIO supply with decoupling capacitor. | </details> <details> <summary><b>C239</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VDD_GPIO | ✅ | Decoupling capacitor positive terminal correctly connects to VCCA supply. | | 2 | 2 | GND | ✅ | Decoupling capacitor ground terminal correctly connects to ground. | </details> <details> <summary><b>C258</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SYS_5P0V | ✅ | Decoupling capacitor positive terminal correctly connects to VCC5V supply. | | 2 | 2 | GND | ✅ | Decoupling capacitor ground terminal correctly connects to ground. | </details> <details> <summary><b>C289</b> - CAP0402_0P1UF_X5R_35V ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_5V | ✅ | 0.1uF decoupling capacitor correctly connected between HDMI_5V and GND to provide local bypassing for the 5V supply to the HDMI connector. | | 2 | 2 | GND | ✅ | 0.1uF decoupling capacitor correctly connected between HDMI_5V and GND to provide local bypassing for the 5V supply to the HDMI connector. | </details> <details> <summary><b>R24</b> - RES0402_4K75 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_HPD_B | ✅ | 4.75K pulldown resistor correctly connected between HDMI_HPD_B and GND to pull Hot Plug Detect signal low when no device is connected. | | 2 | 2 | GND | ✅ | 4.75K pulldown resistor correctly connected between HDMI_HPD_B and GND to pull Hot Plug Detect signal low when no device is connected. | </details> <details> <summary><b>R21</b> - RES0402_4K75 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDC_SDA | ✅ | 4.75K pullup resistor correctly connected between DDC_SDA and HDMI_5V to provide required I2C pullup for DDC data line. | | 2 | 2 | HDMI_5V | ✅ | 4.75K pullup resistor correctly connected between DDC_SDA and HDMI_5V to provide required I2C pullup for DDC data line. | </details> <details> <summary><b>R19</b> - RES0402_4K75 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDC_SCL | ✅ | 4.75K pullup resistor correctly connected between DDC_SCL and HDMI_5V to provide required I2C pullup for DDC clock line. | | 2 | 2 | HDMI_5V | ✅ | 4.75K pullup resistor correctly connected between DDC_SCL and HDMI_5V to provide required I2C pullup for DDC clock line. | </details> <details> <summary><b>J10</b> - HDMI_MICRO_D_RA ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/en-us/products/part-detail/467651001?display=pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/46765-1001) Part Number: `46765-1001` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | HPD | HDMI_HPD_B | ✅ | HPD pin correctly connected to hot plug detect signal through U37 with pulldown resistor. | | 2 | RES | | ✅ | RES pin correctly left unconnected as it is a reserved/utility pin. | | 3 | D2+ | HDMI_TX2_P | ✅ | D2+ and D2- pins correctly connected to TMDS data channel 2 through U37 ESD protection. | | 5 | D2- | HDMI_TX2_N | ✅ | D2+ and D2- pins correctly connected to TMDS data channel 2 through U37 ESD protection. | | 4 | D2S | GND | ✅ | D2S shield pin correctly connected to ground. | | 6 | D1+ | HDMI_TX1_P | ✅ | D1+ and D1- pins correctly connected to TMDS data channel 1 through U37 ESD protection. | | 8 | D1- | HDMI_TX1_N | ✅ | D1+ and D1- pins correctly connected to TMDS data channel 1 through U37 ESD protection. | | 7 | D1S | GND | ✅ | D1S shield pin correctly connected to ground. | | 9 | D0+ | HDMI_TX0_P | ✅ | D0+ and D0- pins correctly connected to TMDS data channel 0 through U37 ESD protection. | | 11 | D0- | HDMI_TX0_N | ✅ | D0+ and D0- pins correctly connected to TMDS data channel 0 through U37 ESD protection. | | 10 | D0S | GND | ✅ | D0S shield pin correctly connected to ground. | | 12 | CLK+ | HDMI_TXC_P | ✅ | CLK+ and CLK- pins correctly connected to TMDS clock through U37 ESD protection. | | 14 | CLK- | HDMI_TXC_N | ✅ | CLK+ and CLK- pins correctly connected to TMDS clock through U37 ESD protection. | | 13 | CLKS | GND | ✅ | CLKS shield pin correctly connected to ground. | | 15 | CEC | HDMI_CEC_B | ✅ | CEC pin correctly connected to CEC signal through U37 level shifter. | | 16 | DDC | GND | ✅ | DDC ground pin correctly connected to system ground. | | 17 | SCL | DDC_SCL | ✅ | SCL and SDA pins correctly connected to DDC interface with pullup resistors, though pullup values are outside recommended range. | | 18 | SDA | DDC_SDA | ✅ | SCL and SDA pins correctly connected to DDC interface with pullup resistors, though pullup values are outside recommended range. | | 19 | 5V0 | HDMI_5V | ✅ | 5V power pin correctly connected to current-limited 5V output from U37. | | GND1 | SHLD1 | GND | ✅ | Shield pins correctly connected to system ground for EMI protection. | | GND2 | SHLD2 | GND | ✅ | Shield pins correctly connected to system ground for EMI protection. | | GND3 | SHLD3 | GND | ✅ | Shield pins correctly connected to system ground for EMI protection. | | GND4 | SHLD4 | GND | ✅ | Shield pins correctly connected to system ground for EMI protection. | </details> <details> <summary><b>J11</b> - BSH-030-01-F-D-A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6209/bsh-xxx-01-x-d-xx-xx-mkt.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/BSH-030-01-F-D-A) Part Number: `BSH-030-01-F-D-A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 01 | VDD_GPIO | ✅ | Power supply pins connected to VDD_GPIO. Both pins provide redundant power connections to the GPIO expansion connector. | | 2 | 02 | VDD_GPIO | ✅ | Power supply pins connected to VDD_GPIO. Both pins provide redundant power connections to the GPIO expansion connector. | | 3 | 03 | GPIO0_N | ✅ | GPIO0 differential pair (GPIO0_N and GPIO0_P) on Row 1 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity. | | 5 | 05 | GPIO0_P | ✅ | GPIO0 differential pair (GPIO0_N and GPIO0_P) on Row 1 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity. | | 4 | 04 | GPIO1_N | ✅ | GPIO1 differential pair (GPIO1_N and GPIO1_P) on Row 2 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity. | | 6 | 06 | GPIO1_P | ✅ | GPIO1 differential pair (GPIO1_N and GPIO1_P) on Row 2 of the connector. Keeping both signals of the differential pair on the same row minimizes skew and maintains signal integrity. | | 7 | 07 | GPIO2_N | ✅ | GPIO2 differential pair (GPIO2_N and GPIO2_P) on Row 1 of the connector. | | 9 | 09 | GPIO2_P | ✅ | GPIO2 differential pair (GPIO2_N and GPIO2_P) on Row 1 of the connector. | | 8 | 08 | GPIO3_N | ✅ | GPIO3 differential pair (GPIO3_N and GPIO3_P) on Row 2 of the connector. | | 10 | 10 | GPIO3_P | ✅ | GPIO3 differential pair (GPIO3_N and GPIO3_P) on Row 2 of the connector. | | 11 | 11 | GND | ✅ | Ground pins providing return paths for GPIO0-GPIO3 differential pairs. Ground pins are strategically placed every 10 pins for good signal integrity. | | 12 | 12 | GND | ✅ | Ground pins providing return paths for GPIO0-GPIO3 differential pairs. Ground pins are strategically placed every 10 pins for good signal integrity. | | 13 | 13 | GPIO4_N | ✅ | GPIO4 differential pair (GPIO4_N and GPIO4_P) on Row 1 of the connector. | | 15 | 15 | GPIO4_P | ✅ | GPIO4 differential pair (GPIO4_N and GPIO4_P) on Row 1 of the connector. | | 14 | 14 | GPIO5_N | ✅ | GPIO5 differential pair (GPIO5_N and GPIO5_P) on Row 2 of the connector. | | 16 | 16 | GPIO5_P | ✅ | GPIO5 differential pair (GPIO5_N and GPIO5_P) on Row 2 of the connector. | | 17 | 17 | GPIO6_N | ✅ | GPIO6 differential pair (GPIO6_N and GPIO6_P) on Row 1 of the connector. | | 19 | 19 | GPIO6_P | ✅ | GPIO6 differential pair (GPIO6_N and GPIO6_P) on Row 1 of the connector. | | 18 | 18 | GPIO7_N | ✅ | GPIO7 differential pair (GPIO7_N and GPIO7_P) on Row 2 of the connector. | | 20 | 20 | GPIO7_P | ✅ | GPIO7 differential pair (GPIO7_N and GPIO7_P) on Row 2 of the connector. | | 21 | 21 | GND | ✅ | Ground pins providing return paths for GPIO4-GPIO7 differential pairs. | | 22 | 22 | GND | ✅ | Ground pins providing return paths for GPIO4-GPIO7 differential pairs. | | 23 | 23 | GPIO8_N | ✅ | GPIO8 differential pair (GPIO8_N and GPIO8_P) on Row 1 of the connector. | | 25 | 25 | GPIO8_P | ✅ | GPIO8 differential pair (GPIO8_N and GPIO8_P) on Row 1 of the connector. | | 24 | 24 | GPIO9_N | ✅ | GPIO9 differential pair (GPIO9_N and GPIO9_P) on Row 2 of the connector. | | 26 | 26 | GPIO9_P | ✅ | GPIO9 differential pair (GPIO9_N and GPIO9_P) on Row 2 of the connector. | | 27 | 27 | GPIO10_N | ✅ | GPIO10 differential pair (GPIO10_N and GPIO10_P) on Row 1 of the connector. | | 29 | 29 | GPIO10_P | ✅ | GPIO10 differential pair (GPIO10_N and GPIO10_P) on Row 1 of the connector. | | 28 | 28 | GPIO11_N | ✅ | GPIO11 differential pair (GPIO11_N and GPIO11_P) on Row 2 of the connector. | | 30 | 30 | GPIO11_P | ✅ | GPIO11 differential pair (GPIO11_N and GPIO11_P) on Row 2 of the connector. | | 31 | 31 | GND | ✅ | Ground pins providing return paths for GPIO8-GPIO11 differential pairs. | | 32 | 32 | GND | ✅ | Ground pins providing return paths for GPIO8-GPIO11 differential pairs. | | 33 | 33 | GPIO12_N | ✅ | GPIO12 differential pair (GPIO12_N and GPIO12_P) on Row 1 of the connector. | | 35 | 35 | GPIO12_P | ✅ | GPIO12 differential pair (GPIO12_N and GPIO12_P) on Row 1 of the connector. | | 34 | 34 | GPIO13_N | ✅ | GPIO13 differential pair (GPIO13_N and GPIO13_P) on Row 2 of the connector. | | 36 | 36 | GPIO13_P | ✅ | GPIO13 differential pair (GPIO13_N and GPIO13_P) on Row 2 of the connector. | | 37 | 37 | GPIO14_N | ✅ | GPIO14 differential pair (GPIO14_N and GPIO14_P) on Row 1 of the connector. | | 39 | 39 | GPIO14_P | ✅ | GPIO14 differential pair (GPIO14_N and GPIO14_P) on Row 1 of the connector. | | 38 | 38 | GPIO15_N | ✅ | GPIO15 differential pair (GPIO15_N and GPIO15_P) on Row 2 of the connector. | | 40 | 40 | GPIO15_P | ✅ | GPIO15 differential pair (GPIO15_N and GPIO15_P) on Row 2 of the connector. | | 41 | 41 | GND | ✅ | Ground pins providing return paths for GPIO12-GPIO15 differential pairs. | | 42 | 42 | GND | ✅ | Ground pins providing return paths for GPIO12-GPIO15 differential pairs. | | 43 | 43 | GPIO16_N | ✅ | GPIO16 differential pair (GPIO16_N and GPIO16_P) on Row 1 of the connector. | | 45 | 45 | GPIO16_P | ✅ | GPIO16 differential pair (GPIO16_N and GPIO16_P) on Row 1 of the connector. | | 44 | 44 | GPIO17_N | ✅ | GPIO17 differential pair (GPIO17_N and GPIO17_P) on Row 2 of the connector. | | 46 | 46 | GPIO17_P | ✅ | GPIO17 differential pair (GPIO17_N and GPIO17_P) on Row 2 of the connector. | | 47 | 47 | GPIO18_N | ✅ | GPIO18 differential pair (GPIO18_N and GPIO18_P) on Row 1 of the connector. | | 49 | 49 | GPIO18_P | ✅ | GPIO18 differential pair (GPIO18_N and GPIO18_P) on Row 1 of the connector. | | 48 | 48 | GPIO19_N | ✅ | GPIO19 differential pair (GPIO19_N and GPIO19_P) on Row 2 of the connector. | | 50 | 50 | GPIO19_P | ✅ | GPIO19 differential pair (GPIO19_N and GPIO19_P) on Row 2 of the connector. | | 51 | 51 | GND | ✅ | Ground pins providing return paths for GPIO16-GPIO19 differential pairs. | | 52 | 52 | GND | ✅ | Ground pins providing return paths for GPIO16-GPIO19 differential pairs. | | 53 | 53 | GPIO20_N | ✅ | GPIO20 differential pair (GPIO20_N and GPIO20_P) on Row 1 of the connector. | | 55 | 55 | GPIO20_P | ✅ | GPIO20 differential pair (GPIO20_N and GPIO20_P) on Row 1 of the connector. | | 54 | 54 | GPIO21_N | ✅ | GPIO21 differential pair (GPIO21_N and GPIO21_P) on Row 2 of the connector. | | 56 | 56 | GPIO21_P | ✅ | GPIO21 differential pair (GPIO21_N and GPIO21_P) on Row 2 of the connector. | | 57 | 57 | GPIO22_N | ✅ | GPIO22 differential pair (GPIO22_N and GPIO22_P) on Row 1 of the connector. | | 59 | 59 | GPIO22_P | ✅ | GPIO22 differential pair (GPIO22_N and GPIO22_P) on Row 1 of the connector. | | 58 | 58 | GPIO23_N | ✅ | GPIO23 differential pair (GPIO23_N and GPIO23_P) on Row 2 of the connector. | | 60 | 60 | GPIO23_P | ✅ | GPIO23 differential pair (GPIO23_N and GPIO23_P) on Row 2 of the connector. | </details> <details> <summary><b>R22</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_INT | ✅ | Pin 1 correctly connected to HDMI_INT net from ADV7513 interrupt output. | | 2 | 2 | VDD_GPIO | ✅ | Pin 2 correctly connected to VDD_GPIO supply, providing pull-up for open-drain interrupt output. | </details> <details> <summary><b>D1</b> - DIODE_BAS16XV2T1G ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CATHODE | HDMI_CEC | ✅ | Component is DNI (Do Not Install) and electrically absent from the circuit. | | 2 | ANODE | N22414199 | ✅ | Component is DNI (Do Not Install) and electrically absent from the circuit. | </details> <details> <summary><b>R225</b> - RES0402_27K4 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 3P3V | ✅ | Component is DNI (Do Not Install) and electrically absent from the circuit. | | 2 | 2 | N22414199 | ✅ | Component is DNI (Do Not Install) and electrically absent from the circuit. | </details> <details> <summary><b>L8</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/2237/VLS252012E_Series.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/VLS252012ET-1R5N) Part Number: `VLS252012ET-1R5N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N22934179 | ✅ | L8 is correctly connected between the SW1 switching node (pin 16 of U29) and the DCD1 output, forming the output filter for the 1V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A). | | 2 | 2 | N22939905 | ✅ | L8 is correctly connected between the SW1 switching node (pin 16 of U29) and the DCD1 output, forming the output filter for the 1V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A). | | 1 | 1 | N22934179 | ✅ | Inductor terminal 1 is correctly connected to the SW1 switching node (N22934179) of U29 DCD1 converter, forming one end of the buck converter output filter. | | 2 | 2 | N22939905 | ✅ | Inductor terminal 2 is correctly connected to the DCD1 output node (N22939905), which feeds the 1P0V rail through R286 (0Ω). Output capacitors C242 (0.047µF) and C243 (10µF) are connected to this node. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A. | </details> <details> <summary><b>L9</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/2237/VLS252012E_Series.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/VLS252012ET-1R5N) Part Number: `VLS252012ET-1R5N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N25830793 | ✅ | L9 is correctly connected between the SW2 switching node (pin 13 of U29) and the DCD2 output, forming the output filter for the 1.8V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A). | | 2 | 2 | N25830712 | ✅ | L9 is correctly connected between the SW2 switching node (pin 13 of U29) and the DCD2 output, forming the output filter for the 1.8V buck converter. The 1.5µH inductance matches the ISL9307 datasheet recommendation. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A, which may result in temperature rise exceeding 40°C at full load, but the inductor will not saturate (Idc1 rating is 1.80A). | | 1 | 1 | N25830793 | ✅ | Inductor terminal 1 is correctly connected to the SW2 switching node (N25830793) of U29 DCD2 converter, forming one end of the buck converter output filter. | | 2 | 2 | N25830712 | ✅ | Inductor terminal 2 is correctly connected to the DCD2 output node (N25830712), which feeds the 1P8V rail through R287 (0Ω). Output capacitors C244 (0.047µF) and C245 (10µF) are connected to this node. The inductor's thermal current rating (Idc2) of 1.45A is slightly below the specified maximum output current of 1.5A. | </details> <details> <summary><b>U29</b> - DC-TO-DC PWR SUPPLY ❌</summary> DRCY flagged 2 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/isl9307-datasheet) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ISL9307IRTAANFZ-T) Part Number: `ISL9307IRTAANFZ-T` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 11 | FB2 | N25830704 | ❌ | <details><summary>FB2 is connected to a voltage divider network (R282, R281) that produces approximately 0.94V output, but the design specification indicates 1.8V is required. The resistor values are incorrect for the intended 1.8V output.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="63.08,37.70,70.58,45.20" aspect-ratio="1.33" } <ul><li>Pin 11 (FB2) is connected to net N25830704 <em>(from schematic)</em></li><li>FB2 connects to a voltage divider consisting of R282 (10K) from the output to FB2, and R281 (56.2K) from FB2 to ground <em>(from schematic)</em></li><li>FB2 regulation voltage is 0.8V typical <em>(from datasheet <a href="https://www.renesas.com/us/en/document/dst/isl9307-datasheet#page=5">ISL9307IRTAANFZ-T</a>, page 5)</em></li><li>The output voltage is calculated as Vout = 0.8V × (1 + R282/R281) = 0.8V × (1 + 10K/56.2K) = 0.942V <em>(reasoning)</em></li><li>The text note indicates the output should be 1.8V @ 1.5A max <em>(from schematic)</em></li><li>The DCD2 output connects through R287 (0 ohm) to the 1P8V net, confirming the intended output is 1.8V <em>(from schematic)</em></li><li>For 1.8V output, the resistor ratio should be R_TOP/R_BOT = (1.8V/0.8V) - 1 = 1.25 <em>(reasoning)</em></li><li>The actual ratio is R282/R281 = 10K/56.2K = 0.178, which does not match the required 1.25 ratio <em>(reasoning)</em></li><li>To achieve 1.8V output, either R282 should be changed to approximately 70K (keeping R281 = 56.2K), or R281 should be changed to approximately 8K (keeping R282 = 10K) <em>(reasoning)</em></li><li>The feedback resistor values are incorrect and will produce 0.94V instead of the intended 1.8V <em>(reasoning)</em></li></ul></details> | | 15 | GNDDCD1 | | ❌ | <details><summary>GNDDCD1 is not connected to any net. This is a critical error that will prevent DCD1 from functioning properly.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="63.08,33.10,70.58,40.60" aspect-ratio="1.33" } <ul><li>Pin 15 (GNDDCD1) has no net connection in the schematic <em>(from schematic)</em></li><li>GNDDCD1 is the power ground for DCD1 and must be connected to ground <em>(from datasheet <a href="https://www.renesas.com/us/en/document/dst/isl9307-datasheet#page=3">ISL9307IRTAANFZ-T</a>, page 3)</em></li><li>All other ground pins (GNDLDO, GNDDCD2, EPAD) are correctly connected to GND <em>(from schematic)</em></li><li>Without a ground connection, DCD1 will not have a return path for its power ground and cannot function <em>(reasoning)</em></li><li>Pin 15 must be connected to GND to match the other ground pins and enable proper operation of DCD1 <em>(reasoning)</em></li></ul></details> | | 1 | VINDCD1 | SYS_5P0V | ✅ | VINDCD1 and VINDCD2 are correctly connected to SYS_5P0V, providing input power for both DC-DC converters. | | 12 | VINDCD2 | SYS_5P0V | ✅ | VINDCD1 and VINDCD2 are correctly connected to SYS_5P0V, providing input power for both DC-DC converters. | | 2 | FB1 | N22934548 | ✅ | FB1 is correctly connected to a voltage divider network (R2, R5, R279) that sets the DCD1 output to 1.0V. | | 3 | ENDCD1 | REG_EN1 | ✅ | ENDCD1 and ENDCD2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both DC-DC converters when SYS_5P0V is present. | | 10 | ENDCD2 | REG_EN2 | ✅ | ENDCD1 and ENDCD2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both DC-DC converters when SYS_5P0V is present. | | 4 | ENLDO1 | REG_EN3 | ✅ | ENLDO1 and ENLDO2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both LDOs when SYS_5P0V is present. | | 8 | ENLDO2 | REG_EN4 | ✅ | ENLDO1 and ENLDO2 are correctly pulled up to SYS_5P0V through 10K resistors, enabling both LDOs when SYS_5P0V is present. | | 5 | VINLDO | SYS_5P0V | ✅ | VINLDO is correctly connected to SYS_5P0V, providing input power for both LDO regulators. | | 6 | VOLDO1 | N22979034 | ✅ | VOLDO1 and VOLDO2 are correctly connected to output capacitors and provide fixed 3.3V and 2.5V outputs respectively, matching the part number specification. | | 7 | VOLDO2 | N22979674 | ✅ | VOLDO1 and VOLDO2 are correctly connected to output capacitors and provide fixed 3.3V and 2.5V outputs respectively, matching the part number specification. | | 9 | GNDLDO | GND | ✅ | GNDLDO, GNDDCD2, and EPAD are correctly connected to GND. | | 14 | GNDDCD2 | GND | ✅ | GNDLDO, GNDDCD2, and EPAD are correctly connected to GND. | | 17 | EPAD | GND | ✅ | GNDLDO, GNDDCD2, and EPAD are correctly connected to GND. | | 13 | SW2 | N25830793 | ✅ | SW1 and SW2 are correctly connected to inductors L8 and L9 respectively, forming the output filters for the DC-DC converters. | | 16 | SW1 | N22934179 | ✅ | SW1 and SW2 are correctly connected to inductors L8 and L9 respectively, forming the output filters for the DC-DC converters. | </details> <details> <summary><b>U30</b> - DC-TO-DC PWR SUPPLY ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/isl9305h-datasheet) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ISL9305IRTHWBNLZ-T) Part Number: `ISL9305IRTHWBNLZ-T` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | DCDPG | N23098459 | ❌ | <details><summary>DCDPG is connected to LED CR8 for power-good indication, but the LED polarity is reversed. The LED anode is connected to GND and cathode to DCDPG, which will prevent the LED from lighting up when power is good.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="62.58,77.82,70.08,85.32" aspect-ratio="1.33" } <ul><li>Pin 10 (DCDPG) is connected to net N23098459 <em>(from schematic)</em></li><li>N23098459 connects to CR8 pin 1 (cathode) and R288 pin 1 (620 ohm resistor) <em>(from schematic)</em></li><li>CR8 pin 2 (anode) is connected to GND <em>(from schematic)</em></li><li>R288 pin 2 is connected to SYS_5P0V, providing pull-up for the open-drain DCDPG output <em>(from schematic)</em></li><li>DCDPG is an open-drain output that is released (high-Z, pulled high) when power is good and pulled low when power is bad <em>(from datasheet <a href="https://www.renesas.com/us/en/document/dst/isl9305h-datasheet#page=2">ISL9305IRTHWBNLZ-T</a>, page 2)</em></li><li>When power is good, DCDPG is high-Z and pulled to ~5V by R288, placing ~5V at the LED cathode and 0V at the LED anode, reverse-biasing the LED <em>(reasoning)</em></li><li>When power is bad, DCDPG pulls N23098459 to GND, placing 0V at both LED terminals with no current flow <em>(reasoning)</em></li><li>The LED will not light up in either state with the current polarity <em>(reasoning)</em></li><li>The LED connections should be swapped: CR8 pin 1 should connect to GND and CR8 pin 2 should connect to N23098459 <em>(reasoning)</em></li></ul></details> | | 1 | VINDCD1 | SYS_5P0V | ✅ | VINDCD1 is correctly connected to SYS_5P0V as the input voltage for DCD1 and internal circuits. | | 2 | FB1 | N22955654 | ✅ | FB1 is correctly connected to the DCD1 output through inductor L11 for fixed output configuration. | | 3 | SCLK | I2C_SCL | ✅ | SCLK is correctly connected to I2C_SCL with appropriate 10K pull-up resistor to SYS_5P0V. | | 4 | SDAT | I2C_SDA | ✅ | SDAT is correctly connected to I2C_SDA with appropriate 10K pull-up resistor to SYS_5P0V. | | 5 | VINLDO1 | SYS_5P0V | ✅ | VINLDO1 is correctly connected to SYS_5P0V as the input voltage for LDO1. | | 6 | VOLDO1 | N23028604 | ✅ | VOLDO1 is correctly connected to output net N23028604 with appropriate 10uF output capacitor. | | 7 | VOLDO2 | N23029208 | ✅ | VOLDO2 is correctly connected to output net N23029208 with appropriate 10uF output capacitor. | | 8 | VINLDO2 | SYS_5P0V | ✅ | VINLDO2 is correctly connected to SYS_5P0V as the input voltage for LDO2. | | 9 | GNDLDO | GND | ✅ | GNDLDO is correctly connected to GND as the power ground for LDO1 and LDO2. | | 11 | FB2 | N22955725 | ✅ | FB2 is correctly connected to the DCD2 output through inductor L10 for fixed output configuration. | | 12 | VINDCD2 | SYS_5P0V | ✅ | VINDCD2 is correctly connected to SYS_5P0V as the input voltage for DCD2. | | 13 | SW2 | N22955745 | ✅ | SW2 is correctly connected to inductor L10 pin 1 as the switching node for DCD2. | | 14 | GNDDCD2 | GND | ✅ | GNDDCD2 is correctly connected to GND as the power ground for DCD2. | | 15 | GNDDCD1 | GND | ✅ | GNDDCD1 is correctly connected to GND as the power ground for DCD1. | | 16 | SW1 | N22955797 | ✅ | SW1 is correctly connected to inductor L11 pin 1 as the switching node for DCD1. | | 17 | EPAD | GND | ✅ | EPAD is correctly connected to GND as required for the exposed pad. | </details> <details> <summary><b>L10</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/2237/VLS252012E_Series.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/VLS252012ET-1R5N) Part Number: `VLS252012ET-1R5N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N22955745 | ✅ | Pin 1 is correctly connected to the SW2 switching node of U30 for the DCD2 buck converter. | | 2 | 2 | N22955725 | ✅ | Pin 2 is correctly connected to the DCD2 output with appropriate output capacitor C250. | </details> <details> <summary><b>L11</b> ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/2237/VLS252012E_Series.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/VLS252012ET-1R5N) Part Number: `VLS252012ET-1R5N` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N22955797 | ✅ | Pin 1 is correctly connected to the SW1 switching node of U30 for the DCD1 buck converter. | | 2 | 2 | N22955654 | ✅ | Pin 2 is correctly connected to the DCD1 output with appropriate output capacitor C248. | </details> <details> <summary><b>F1</b> - ERB-RE4R00V ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/ERB-RE4R00V/AFA0000C7.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ERB-RE4R00V) Part Number: `ERB-RE4R00V` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 5P0V_IN | ✅ | Fuse terminals correctly connected between power jack input (5P0V_IN) and system power rail (5P0V), but the 4A fuse rating is too high to properly protect the 2.5A-rated power jack J12, creating a protection coordination issue. | | 2 | 2 | 5P0V | ✅ | Fuse terminals correctly connected between power jack input (5P0V_IN) and system power rail (5P0V), but the 4A fuse rating is too high to properly protect the 2.5A-rated power jack J12, creating a protection coordination issue. | </details> <details> <summary><b>J12</b> - PJ-002A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.sameskydevices.com/product/resource/pj-002a.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/PJ-002A) Part Number: `PJ-002A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CENTER | 5P0V_IN | ✅ | CENTER pin correctly connected to 5P0V_IN net, serving as the positive power input from the barrel jack center pin. | | 2 | SLEEVE | GND | ✅ | SLEEVE pin correctly connected to GND, providing the ground return path for the power input. | | 3 | SHUNT | GND | ✅ | SHUNT pin connected to GND. This is the switching contact that is normally closed to pin 2 but opens when a plug is inserted; tying it to ground is acceptable when the switching function is not needed. | </details> <details> <summary><b>R288</b> - CRCW0402620RFKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW0402620RFKED) Part Number: `CRCW0402620RFKED` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23098459 | ✅ | Connected to net N23098459, which connects to CR8 pin 1 (cathode) and U30 pin 10 (DCDPG). This resistor serves as a current limiting resistor for LED CR8. | | 2 | 2 | SYS_5P0V | ✅ | Connected to SYS_5P0V supply rail. The 620Ω value is appropriate for limiting LED current to approximately 5mA. | </details> <details> <summary><b>CR8</b> - LTST-C193KGKT-5A ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/LTST-C193KGKT-5A) Part Number: `LTST-C193KGKT-5A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | C | N23098459 | ❌ | <details><summary>LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="70.01,79.79,77.51,87.29" aspect-ratio="1.33" } <ul><li>Pin 1 is labeled &#x27;C&#x27; (cathode) in the schematic and is connected to net N23098459 <em>(from schematic)</em></li><li>Pin 2 is labeled &#x27;A&#x27; (anode) in the schematic and is connected to net GND <em>(from schematic)</em></li><li>Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) <em>(from schematic)</em></li><li>Pin 1 is the cathode (negative terminal) according to the datasheet <em>(from datasheet <a href="https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2">LTST-C193KGKT-5A</a>, page 2)</em></li><li>Pin 2 is the anode (positive terminal) according to the datasheet <em>(from datasheet <a href="https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2">LTST-C193KGKT-5A</a>, page 2)</em></li><li>For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode <em>(reasoning)</em></li><li>With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on <em>(reasoning)</em></li><li>A text note near the LED states &#x27;Power Good = LED ON&#x27;, indicating the LED should illuminate when power is good <em>(from schematic)</em></li><li>The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 <em>(reasoning)</em></li><li>With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior <em>(reasoning)</em></li><li>To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 <em>(reasoning)</em></li><li>With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on <em>(reasoning)</em></li></ul></details> | | 2 | A | GND | ❌ | <details><summary>LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="70.01,82.42,77.51,89.92" aspect-ratio="1.33" } <ul><li>Pin 1 is labeled &#x27;C&#x27; (cathode) in the schematic and is connected to net N23098459 <em>(from schematic)</em></li><li>Pin 2 is labeled &#x27;A&#x27; (anode) in the schematic and is connected to net GND <em>(from schematic)</em></li><li>Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) <em>(from schematic)</em></li><li>Pin 1 is the cathode (negative terminal) according to the datasheet <em>(from datasheet <a href="https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2">LTST-C193KGKT-5A</a>, page 2)</em></li><li>Pin 2 is the anode (positive terminal) according to the datasheet <em>(from datasheet <a href="https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2">LTST-C193KGKT-5A</a>, page 2)</em></li><li>For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode <em>(reasoning)</em></li><li>With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on <em>(reasoning)</em></li><li>A text note near the LED states &#x27;Power Good = LED ON&#x27;, indicating the LED should illuminate when power is good <em>(from schematic)</em></li><li>The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 <em>(reasoning)</em></li><li>With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior <em>(reasoning)</em></li><li>To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 <em>(reasoning)</em></li><li>With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on <em>(reasoning)</em></li></ul></details> | </details> <details> <summary><b>U36</b> - NC7SZ125 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/NC7SZ125M5X/NC7SZ125-D.PDF) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/NC7SZ125M5X) Part Number: `NC7SZ125M5X` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | O\E\ | 5P0V | ❌ | <details><summary>Output enable pin (O̅E̅) is connected to 5P0V (HIGH), which permanently disables the buffer and puts the output in high-impedance state. This appears to be a design error as the buffer serves no function in this configuration.</summary>!thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="18.54,25.21,26.04,32.71" aspect-ratio="1.33" } <ul><li>Pin 1 (O̅E̅) is connected to net 5P0V <em>(from schematic)</em></li><li>Pin 1 is the output enable input (O̅E̅), which is active LOW <em>(from datasheet <a href="https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/NC7SZ125M5X/NC7SZ125-D.PDF#page=2">NC7SZ125M5X</a>, page 2)</em></li><li>When O̅E̅ is LOW, the buffer is enabled and output follows input; when O̅E̅ is HIGH, output is in high-impedance state <em>(from datasheet <a href="https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/NC7SZ125M5X/NC7SZ125-D.PDF#page=2">NC7SZ125M5X</a>, page 2)</em></li><li>The 5P0V net is a power rail at approximately 5V, which is a logic HIGH level <em>(reasoning)</em></li><li>With O̅E̅ tied HIGH, the buffer is permanently disabled and the output (pin 4) will always be in high-impedance state <em>(reasoning)</em></li><li>The buffer serves no function in this configuration since it is always disabled <em>(reasoning)</em></li><li>Pin 1 should be connected to GND to enable the buffer, or the buffer should be removed if not needed <em>(reasoning)</em></li></ul></details> | | 2 | A | N25176046 | ✅ | Input pin A is connected to net N25176046, which is pulled down to GND through R327 (1K). Since the buffer is disabled, this input has no effect on the output. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | TURBO_MODE | ✅ | Output pin Y is connected to TURBO_MODE net, which is pulled up to VDD_GPIO through R328 (1K). Since the buffer is disabled, the output is in high-impedance state and TURBO_MODE is determined solely by the pull-up resistor. | | 5 | VCC | 3P3V | ✅ | VCC pin is connected to 3P3V rail, which is within the 1.65V to 5.5V operating range. The local decoupling capacitor C288 is marked DNI, which is not ideal but may be acceptable if sufficient decoupling exists elsewhere on the 3P3V rail. | </details> <details> <summary><b>J14</b> - HDR_1X3_TH_VER ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3.amazonaws.com/catalogspreads-pdf/PAGE112-113%2520.100%2520MALE%2520HDR.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/PBC36SAAN) Part Number: `PBC36SAAN` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 5P0V | ✅ | Connected to 5P0V, the fused 5V input from the barrel jack connector. This pin provides access to the main 5V input power after the 4A fuse F1. | | 2 | 2 | SYS_5P0V | ✅ | Connected to SYS_5P0V, the system 5V power rail that supplies the DC-DC converters U29 and U30. This pin serves as the distribution point for system power. | | 3 | 3 | USB_VBUS | ✅ | Connected to USB_VBUS, intended as an alternative USB power input. Currently only connected to a DNI capacitor C287, indicating this is a placeholder for future functionality. | </details> <details> <summary><b>U34</b> - VOLTMON_4IN_3P3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.st.com/content/ccc/resource/technical/document/datasheet/cc/6f/0c/27/59/40/4e/e5/CD00180457.pdf/files/CD00180457.pdf/jcr:content/translations/en.CD00180457.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/STM6904TWEDS6F) Part Number: `STM6904TWEDS6F` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | MR | PB_RESET_L | ✅ | MR (manual reset) input is correctly connected to pushbutton SW2 via PB_RESET_L net. When the button is pressed, this active-low input is pulled to ground, asserting a manual reset. | | 2 | VCC | 3P3V | ✅ | VCC is correctly connected to 3P3V supply with 0.1µF decoupling capacitor C291. The 3.3V supply is monitored with factory-programmed threshold of 3.078V typical. | | 3 | V2IN | 1P8V | ✅ | V2IN is correctly connected to 1P8V supply with 0.1µF decoupling capacitor C290. The 1.8V supply is monitored with factory-programmed threshold of 1.683V typical. | | 4 | VSS | GND | ✅ | VSS is correctly connected to ground. | | 5 | V3IN | N23613650 | ✅ | V3IN is correctly connected to adjustable voltage divider monitoring 1P35V supply. Resistors R298 (10K) and R301 (10K) form a 2:1 divider setting trip threshold at 1.2V (88.9% of nominal 1.35V). | | 6 | V4IN | N23614416 | ✅ | V4IN is correctly connected to adjustable voltage divider monitoring 1P0V supply. Resistors R300 (4.75K) and R299 (10K) form a divider setting trip threshold at 0.885V (88.5% of nominal 1.0V). | | 7 | TRSEL | GND | ✅ | TRSEL is correctly connected to GND, selecting the 210ms reset timeout period. | | 8 | RST_L | N25161882 | ✅ | RST_L output is correctly connected through R96 (0Ω) to PS_POR_L net, which has 10kΩ pull-up resistor R326 to 3P3V. This matches the datasheet recommendation for open-drain output configuration. | </details> <details> <summary><b>SW2</b> - SW_PB_VERT ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://omronfs.omron.com/en_US/ecb/products/pdf/en-b3u.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/B3U-1000P) Part Number: `B3U-1000P` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A | GND | ✅ | Terminal A is correctly connected to GND for the normally-open pushbutton switch. | | 2 | B | PB_RESET_L | ✅ | Terminal B is correctly connected to PB_RESET_L, which connects to U34 pin 1 (MR). When the button is pressed, this pulls the manual reset input low. | </details> <details> <summary><b>R294</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N23601474 | ✅ | 1K resistor pulls the input of U33 (pin 2) to GND, ensuring the input is held at logic LOW. | | 2 | 2 | GND | ✅ | 1K resistor pulls the input of U33 (pin 2) to GND, ensuring the input is held at logic LOW. | </details> <details> <summary><b>C259</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0.1µF decoupling capacitor between 3P3V and GND for U33 power supply. | | 2 | 2 | 3P3V | ✅ | 0.1µF decoupling capacitor between 3P3V and GND for U33 power supply. | </details> <details> <summary><b>U33</b> - NC7SZ125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/NC7SZ125M5X/NC7SZ125-D.PDF) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/NC7SZ125M5X) Part Number: `NC7SZ125M5X` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | O\E\ | PS_POR_L | ✅ | Output enable pin (O̅E̅) is connected to PS_POR_L, which controls when the buffer is enabled. When PS_POR_L is LOW (during reset), the buffer is enabled and drives the output LOW. | | 2 | A | N23601474 | ✅ | Input pin (A) is tied LOW through R294 (1K resistor to GND). This ensures the output is LOW when the buffer is enabled. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | BOARD_RESET_L | ✅ | Output pin (Y) drives BOARD_RESET_L, which is pulled up to 1P8V through R295 (1K). When enabled, output drives LOW; when disabled (high-Z), R295 pulls the signal to 1P8V. | | 5 | VCC | 3P3V | ✅ | Power supply pin (VCC) is correctly connected to 3P3V with decoupling capacitor C259 (0.1µF). | </details> <details> <summary><b>R295</b> ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V | ✅ | 1K resistor pulls BOARD_RESET_L up to 1P8V when U33 output is in high-Z state. | | 2 | 2 | BOARD_RESET_L | ✅ | 1K resistor pulls BOARD_RESET_L up to 1P8V when U33 output is in high-Z state. | </details> <details> <summary><b>J13</b> - BSH-030-01-F-D-A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6209/bsh-xxx-01-x-d-xx-xx-mkt.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/BSH-030-01-F-D-A) Part Number: `BSH-030-01-F-D-A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 01 | SYS_5P0V | ✅ | System 5V power supply pins, both connected to SYS_5P0V net. Paired pins provide redundancy and increased current carrying capacity. | | 2 | 02 | SYS_5P0V | ✅ | System 5V power supply pins, both connected to SYS_5P0V net. Paired pins provide redundancy and increased current carrying capacity. | | 3 | 03 | I2C_SCL | ✅ | I2C clock signal (I2C_SCL) for serial communication interface. | | 4 | 04 | I2C_SDA | ✅ | I2C data signal (I2C_SDA) for serial communication interface. | | 5 | 05 | REG_EN1 | ✅ | Regulator enable control signal 1 (REG_EN1). | | 6 | 06 | REG_EN2 | ✅ | Regulator enable control signal 2 (REG_EN2). | | 7 | 07 | REG_EN3 | ✅ | Regulator enable control signal 3 (REG_EN3). | | 8 | 08 | REG_EN4 | ✅ | Regulator enable control signal 4 (REG_EN4). | | 9 | 09 | PROG_IO | ✅ | Programming I/O signal (PROG_IO) for device programming interface. | | 10 | 10 | | ✅ | No connection (NC). This pin is intentionally left unconnected. | | 11 | 11 | GND | ✅ | Ground pins providing return path for signals and power. | | 12 | 12 | GND | ✅ | Ground pins providing return path for signals and power. | | 13 | 13 | DSP_XID0 | ✅ | DSP X-axis ID bit 0 (DSP_XID0) for device identification. | | 14 | 14 | DSP_YID0 | ✅ | DSP Y-axis ID bit 0 (DSP_YID0) for device identification. | | 15 | 15 | DSP_XID1 | ✅ | DSP X-axis ID bit 1 (DSP_XID1) for device identification. | | 16 | 16 | DSP_YID1 | ✅ | DSP Y-axis ID bit 1 (DSP_YID1) for device identification. | | 17 | 17 | DSP_XID2 | ✅ | DSP X-axis ID bit 2 (DSP_XID2) for device identification. | | 18 | 18 | DSP_YID2 | ✅ | DSP Y-axis ID bit 2 (DSP_YID2) for device identification. | | 19 | 19 | DSP_XID3 | ✅ | DSP X-axis ID bit 3 (DSP_XID3) for device identification. | | 20 | 20 | DSP_YID3 | ✅ | DSP Y-axis ID bit 3 (DSP_YID3) for device identification. | | 21 | 21 | GND | ✅ | Ground pins providing return path for signals and power. | | 22 | 22 | GND | ✅ | Ground pins providing return path for signals and power. | | 23 | 23 | DSP_FLAG | ✅ | DSP flag signal (DSP_FLAG) for status indication. | | 24 | 24 | UART_RX | ✅ | UART receive signal (UART_RX) for serial communication. | | 25 | 25 | TURBO_MODE | ✅ | Turbo mode control signal (TURBO_MODE) for performance control. | | 26 | 26 | UART_TX | ✅ | UART transmit signal (UART_TX) for serial communication. | | 27 | 27 | SPDIF | ✅ | SPDIF digital audio signal for audio interface. | | 28 | 28 | USER_LED | ✅ | User LED control signal (USER_LED) for status indication. | | 29 | 29 | JTAG_BOOT_EN | ✅ | JTAG boot enable signal (JTAG_BOOT_EN) for debug/programming control. | | 30 | 30 | RESET_N | ✅ | System reset signal (RESET_N) for board reset control. | | 31 | 31 | GND | ✅ | Ground pins providing return path for signals and power. | | 32 | 32 | GND | ✅ | Ground pins providing return path for signals and power. | | 33 | 33 | VADC_N | ✅ | Analog voltage negative input (VADC_N) for differential analog signal. | | 34 | 34 | VADC_P | ✅ | Analog voltage positive input (VADC_P) for differential analog signal. | | 35 | 35 | GND | ✅ | Ground pins providing return path for signals and power, particularly important for adjacent analog signals. | | 36 | 36 | GND | ✅ | Ground pins providing return path for signals and power, particularly important for adjacent analog signals. | | 37 | 37 | JTAG_TMS | ✅ | JTAG test mode select signal (JTAG_TMS) for debug interface. | | 38 | 38 | JTAG_TDI | ✅ | JTAG test data input signal (JTAG_TDI) for debug interface. | | 39 | 39 | JTAG_TCK | ✅ | JTAG test clock signal (JTAG_TCK) for debug interface. | | 40 | 40 | JTAG_TDO | ✅ | JTAG test data output signal (JTAG_TDO) for debug interface. | | 41 | 41 | GND | ✅ | Ground pins providing return path for signals and power. | | 42 | 42 | GND | ✅ | Ground pins providing return path for signals and power. | | 43 | 43 | 1P0V | ✅ | 1.0V power supply pins, both connected to 1P0V net. Paired pins provide redundancy and increased current carrying capacity. | | 44 | 44 | 1P0V | ✅ | 1.0V power supply pins, both connected to 1P0V net. Paired pins provide redundancy and increased current carrying capacity. | | 45 | 45 | VDD_DSP | ✅ | DSP core voltage supply pins, both connected to VDD_DSP net. Paired pins provide redundancy and increased current carrying capacity. | | 46 | 46 | VDD_DSP | ✅ | DSP core voltage supply pins, both connected to VDD_DSP net. Paired pins provide redundancy and increased current carrying capacity. | | 47 | 47 | 1P35V | ✅ | 1.35V power supply pins, both connected to 1P35V net. Paired pins provide redundancy and increased current carrying capacity. | | 48 | 48 | 1P35V | ✅ | 1.35V power supply pins, both connected to 1P35V net. Paired pins provide redundancy and increased current carrying capacity. | | 49 | 49 | 1P8V | ✅ | 1.8V power supply pins, both connected to 1P8V net. Paired pins provide redundancy and increased current carrying capacity. | | 50 | 50 | 1P8V | ✅ | 1.8V power supply pins, both connected to 1P8V net. Paired pins provide redundancy and increased current carrying capacity. | | 51 | 51 | GND | ✅ | Ground pins providing return path for signals and power, particularly important in the power supply section. | | 52 | 52 | GND | ✅ | Ground pins providing return path for signals and power, particularly important in the power supply section. | | 53 | 53 | VDD_ADJ | ✅ | Adjustable voltage supply pins, both connected to VDD_ADJ net. Paired pins provide redundancy and increased current carrying capacity. | | 54 | 54 | VDD_ADJ | ✅ | Adjustable voltage supply pins, both connected to VDD_ADJ net. Paired pins provide redundancy and increased current carrying capacity. | | 55 | 55 | VDD_GPIO | ✅ | GPIO voltage supply pins, both connected to VDD_GPIO net. Paired pins provide redundancy and increased current carrying capacity. | | 56 | 56 | VDD_GPIO | ✅ | GPIO voltage supply pins, both connected to VDD_GPIO net. Paired pins provide redundancy and increased current carrying capacity. | | 57 | 57 | 2P5V | ✅ | 2.5V power supply pins, both connected to 2P5V net. Paired pins provide redundancy and increased current carrying capacity. | | 58 | 58 | 2P5V | ✅ | 2.5V power supply pins, both connected to 2P5V net. Paired pins provide redundancy and increased current carrying capacity. | | 59 | 59 | 3P3V | ✅ | 3.3V power supply pins, both connected to 3P3V net. Paired pins provide redundancy and increased current carrying capacity. | | 60 | 60 | 3P3V | ✅ | 3.3V power supply pins, both connected to 3P3V net. Paired pins provide redundancy and increased current carrying capacity. | </details> <details> <summary><b>CR10</b> - LED_0603_5MA_GRN ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/LTST-C193KGKT-5A) Part Number: `LTST-C193KGKT-5A` (MPN) — inferred by DRCY | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | C | N25352411 | ✅ | LED cathode correctly connected through current limiting resistor R30 (240Ω) to ground. | | 2 | A | USER_LED | ✅ | LED anode correctly connected to USER_LED signal from connector J13 pin 28. | </details> <details> <summary><b>R30</b> - RES0402_240 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. > [!WARNING] > DRCY couldn't determine a part number for this component. Add a part-number > attribute to this component — either the attribute configured as the > repository's preferred part-number attribute, or a recognizable one such as > `MPN`/`IPN` — to enable datasheet lookup. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | N25352411 | ✅ | Current limiting resistor for LED CR10, connected between LED cathode and ground. | | 2 | 2 | GND | ✅ | Current limiting resistor ground connection, completing the LED current path. | </details> </details> <sub><sup>Note: DRCY uses AI. Please verify the outputs.</sup></sub>
parallella.sdax
DRCYAI commented 2026-06-15 23:07:56 +00:00
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[🚨 Error] Component R18, pin 1: Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34.

  • Pin 1 is connected to net VDD_GPIO (from schematic)
  • R18 is a 4.75kΩ resistor functioning as a pull-up resistor (reasoning)
  • The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO (from schematic)
  • All decoupling capacitors for Bank 34 (C126-C134) are connected to VD_GPIO (from schematic)
  • Pull-up resistors for I/O pins should be connected to the same voltage rail as the bank's VCCO supply to ensure proper voltage levels (reasoning)
  • No other components on this schematic page are connected to VDD_GPIO, suggesting it may be a net naming error (from schematic)
  • R18 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage (reasoning)
All affected pins
Component R18, pin `1`: Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34.
  • Pin 1 is connected to net VDD_GPIO (from schematic)
  • R18 is a 4.75kΩ resistor functioning as a pull-up resistor (reasoning)
  • The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO (from schematic)
  • All decoupling capacitors for Bank 34 (C126-C134) are connected to VD_GPIO (from schematic)
  • Pull-up resistors for I/O pins should be connected to the same voltage rail as the bank's VCCO supply to ensure proper voltage levels (reasoning)
  • No other components on this schematic page are connected to VDD_GPIO, suggesting it may be a net naming error (from schematic)
  • R18 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage (reasoning)
Component R20, pin `1`: Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34 and ensure proper I2C operation.
  • Pin 1 is connected to net VDD_GPIO (from schematic)
  • R20 is a 4.75kΩ resistor functioning as an I2C SCL pull-up resistor (reasoning)
  • The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO (from schematic)
  • I2C pull-up resistors should be connected to the same voltage rail as the I/O pins to ensure proper logic levels (reasoning)
  • The I2C SCL signal connects to U2 pin N18 (IO_L13P_T2_MRCC_34) which is in Bank 34 (from schematic)
  • R20 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage (reasoning)

Datasheets: 📄 R18

Replace a datasheet: 📤 R18 📤 R20

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[🚨 Error] **Component `R18`, pin `1`: Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34.** !thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="da9371496a49e0f28b40" diff-visibility="full" variant="default" view-coords="46.25,41.65,53.75,49.15" aspect-ratio="1.33" } - Pin 1 is connected to net VDD_GPIO *(from schematic)* - R18 is a 4.75kΩ resistor functioning as a pull-up resistor *(reasoning)* - The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO *(from schematic)* - All decoupling capacitors for Bank 34 (C126-C134) are connected to VD_GPIO *(from schematic)* - Pull-up resistors for I/O pins should be connected to the same voltage rail as the bank&#x27;s VCCO supply to ensure proper voltage levels *(reasoning)* - No other components on this schematic page are connected to VDD_GPIO, suggesting it may be a net naming error *(from schematic)* - R18 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>R18</code>, pin `1`: Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34.</summary> - Pin 1 is connected to net VDD_GPIO *(from schematic)* - R18 is a 4.75kΩ resistor functioning as a pull-up resistor *(reasoning)* - The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO *(from schematic)* - All decoupling capacitors for Bank 34 (C126-C134) are connected to VD_GPIO *(from schematic)* - Pull-up resistors for I/O pins should be connected to the same voltage rail as the bank&#x27;s VCCO supply to ensure proper voltage levels *(reasoning)* - No other components on this schematic page are connected to VDD_GPIO, suggesting it may be a net naming error *(from schematic)* - R18 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage *(reasoning)* </details> <details> <summary>Component <code>R20</code>, pin `1`: Pin 1 is connected to VDD_GPIO, but should be connected to VD_GPIO to match the VCCO supply for Zynq Bank 34 and ensure proper I2C operation.</summary> - Pin 1 is connected to net VDD_GPIO *(from schematic)* - R20 is a 4.75kΩ resistor functioning as an I2C SCL pull-up resistor *(reasoning)* - The Zynq U2 Bank 34 VCCO pins (N19, R15, T18, V14, W17, Y20) are all connected to net VD_GPIO *(from schematic)* - I2C pull-up resistors should be connected to the same voltage rail as the I/O pins to ensure proper logic levels *(reasoning)* - The I2C SCL signal connects to U2 pin N18 (IO_L13P_T2_MRCC_34) which is in Bank 34 *(from schematic)* - R20 pin 1 should be connected to VD_GPIO instead of VDD_GPIO to match the Bank 34 supply voltage *(reasoning)* </details> </details> Datasheets: [📄 R18](https://www.vishay.com/docs/20035/dcrcwe3.pdf) <sub>Replace a datasheet: [📤 R18](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04024K75FKED) [📤 R20](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/CRCW04024K75FKED)</sub> <sub><sup>💬 Reply to this comment and mention <b>@DRCY</b> to give feedback that DRCY will incorporate on the next run.</sup></sub>
parallella.sdax
DRCYAI commented 2026-06-15 23:07:56 +00:00
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[🚨 Error] Component U23, pins B5, B6: RXI_NO_DATA5 differential pair appears to be missing series resistors. All other data pairs have 100-ohm series resistors (R194-R198, R200-R201), but R199 is absent from the component list.

  • Pin B5 (RXI_NO_DATA_N5) is connected to net RXI_NO_DATA5_N (from schematic)
  • Pin B6 (RXI_NO_DATA_P5) is connected to net RXI_NO_DATA5_P (from schematic)
  • All other RXI_NO_DATA pairs (0-4, 6-7) have 100-ohm series resistors (from schematic)
  • There is a gap in resistor numbering from R198 to R200, where R199 would be expected for DATA5 (from schematic)
  • The nets RXI_NO_DATA5_N and RXI_NO_DATA5_P are labeled on the schematic, suggesting they should be connected (from schematic)
  • No components on this page are connected to the RXI_NO_DATA5 nets (from schematic)
  • The missing series resistors are likely an error unless DATA5 is intentionally unused in this design (reasoning)
  • If DATA5 is used, 100-ohm series resistors should be added consistent with the other data pairs (reasoning)

Replace a datasheet: 📤 U23

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[🚨 Error] **Component `U23`, pins `B5, B6`: RXI_NO_DATA5 differential pair appears to be missing series resistors. All other data pairs have 100-ohm series resistors (R194-R198, R200-R201), but R199 is absent from the component list.** !thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="cec4189011063486798f" diff-visibility="full" variant="default" view-coords="38.33,20.60,45.83,28.76" aspect-ratio="1.33" } - Pin B5 (RXI_NO_DATA_N5) is connected to net RXI_NO_DATA5_N *(from schematic)* - Pin B6 (RXI_NO_DATA_P5) is connected to net RXI_NO_DATA5_P *(from schematic)* - All other RXI_NO_DATA pairs (0-4, 6-7) have 100-ohm series resistors *(from schematic)* - There is a gap in resistor numbering from R198 to R200, where R199 would be expected for DATA5 *(from schematic)* - The nets RXI_NO_DATA5_N and RXI_NO_DATA5_P are labeled on the schematic, suggesting they should be connected *(from schematic)* - No components on this page are connected to the RXI_NO_DATA5 nets *(from schematic)* - The missing series resistors are likely an error unless DATA5 is intentionally unused in this design *(reasoning)* - If DATA5 is used, 100-ohm series resistors should be added consistent with the other data pairs *(reasoning)* <sub>Replace a datasheet: [📤 U23](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/E16G301)</sub> <sub><sup>💬 Reply to this comment and mention <b>@DRCY</b> to give feedback that DRCY will incorporate on the next run.</sup></sub>
parallella.sdax
DRCYAI commented 2026-06-15 23:07:56 +00:00
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[🚨 Error] Component U29, pin 11: FB2 is connected to a voltage divider network (R282, R281) that produces approximately 0.94V output, but the design specification indicates 1.8V is required. The resistor values are incorrect for the intended 1.8V output.

  • Pin 11 (FB2) is connected to net N25830704 (from schematic)
  • FB2 connects to a voltage divider consisting of R282 (10K) from the output to FB2, and R281 (56.2K) from FB2 to ground (from schematic)
  • FB2 regulation voltage is 0.8V typical (from datasheet ISL9307IRTAANFZ-T, page 5)
  • The output voltage is calculated as Vout = 0.8V × (1 + R282/R281) = 0.8V × (1 + 10K/56.2K) = 0.942V (reasoning)
  • The text note indicates the output should be 1.8V @ 1.5A max (from schematic)
  • The DCD2 output connects through R287 (0 ohm) to the 1P8V net, confirming the intended output is 1.8V (from schematic)
  • For 1.8V output, the resistor ratio should be R_TOP/R_BOT = (1.8V/0.8V) - 1 = 1.25 (reasoning)
  • The actual ratio is R282/R281 = 10K/56.2K = 0.178, which does not match the required 1.25 ratio (reasoning)
  • To achieve 1.8V output, either R282 should be changed to approximately 70K (keeping R281 = 56.2K), or R281 should be changed to approximately 8K (keeping R282 = 10K) (reasoning)
  • The feedback resistor values are incorrect and will produce 0.94V instead of the intended 1.8V (reasoning)

Replace a datasheet: 📤 U29

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[🚨 Error] **Component `U29`, pin `11`: FB2 is connected to a voltage divider network (R282, R281) that produces approximately 0.94V output, but the design specification indicates 1.8V is required. The resistor values are incorrect for the intended 1.8V output.** !thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="63.08,37.70,70.58,45.20" aspect-ratio="1.33" } - Pin 11 (FB2) is connected to net N25830704 *(from schematic)* - FB2 connects to a voltage divider consisting of R282 (10K) from the output to FB2, and R281 (56.2K) from FB2 to ground *(from schematic)* - FB2 regulation voltage is 0.8V typical *(from datasheet [ISL9307IRTAANFZ-T](<https://www.renesas.com/us/en/document/dst/isl9307-datasheet#page=5>), page 5)* - The output voltage is calculated as Vout = 0.8V × (1 + R282/R281) = 0.8V × (1 + 10K/56.2K) = 0.942V *(reasoning)* - The text note indicates the output should be 1.8V @ 1.5A max *(from schematic)* - The DCD2 output connects through R287 (0 ohm) to the 1P8V net, confirming the intended output is 1.8V *(from schematic)* - For 1.8V output, the resistor ratio should be R_TOP/R_BOT = (1.8V/0.8V) - 1 = 1.25 *(reasoning)* - The actual ratio is R282/R281 = 10K/56.2K = 0.178, which does not match the required 1.25 ratio *(reasoning)* - To achieve 1.8V output, either R282 should be changed to approximately 70K (keeping R281 = 56.2K), or R281 should be changed to approximately 8K (keeping R282 = 10K) *(reasoning)* - The feedback resistor values are incorrect and will produce 0.94V instead of the intended 1.8V *(reasoning)* <sub>Replace a datasheet: [📤 U29](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ISL9307IRTAANFZ-T)</sub> <sub><sup>💬 Reply to this comment and mention <b>@DRCY</b> to give feedback that DRCY will incorporate on the next run.</sup></sub>
parallella.sdax
DRCYAI commented 2026-06-15 23:07:56 +00:00
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[🚨 Error] Component U29, pin 15: GNDDCD1 is not connected to any net. This is a critical error that will prevent DCD1 from functioning properly.

  • Pin 15 (GNDDCD1) has no net connection in the schematic (from schematic)
  • GNDDCD1 is the power ground for DCD1 and must be connected to ground (from datasheet ISL9307IRTAANFZ-T, page 3)
  • All other ground pins (GNDLDO, GNDDCD2, EPAD) are correctly connected to GND (from schematic)
  • Without a ground connection, DCD1 will not have a return path for its power ground and cannot function (reasoning)
  • Pin 15 must be connected to GND to match the other ground pins and enable proper operation of DCD1 (reasoning)

Replace a datasheet: 📤 U29

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[🚨 Error] **Component `U29`, pin `15`: GNDDCD1 is not connected to any net. This is a critical error that will prevent DCD1 from functioning properly.** !thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="63.08,33.10,70.58,40.60" aspect-ratio="1.33" } - Pin 15 (GNDDCD1) has no net connection in the schematic *(from schematic)* - GNDDCD1 is the power ground for DCD1 and must be connected to ground *(from datasheet [ISL9307IRTAANFZ-T](<https://www.renesas.com/us/en/document/dst/isl9307-datasheet#page=3>), page 3)* - All other ground pins (GNDLDO, GNDDCD2, EPAD) are correctly connected to GND *(from schematic)* - Without a ground connection, DCD1 will not have a return path for its power ground and cannot function *(reasoning)* - Pin 15 must be connected to GND to match the other ground pins and enable proper operation of DCD1 *(reasoning)* <sub>Replace a datasheet: [📤 U29](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ISL9307IRTAANFZ-T)</sub> <sub><sup>💬 Reply to this comment and mention <b>@DRCY</b> to give feedback that DRCY will incorporate on the next run.</sup></sub>
parallella.sdax
DRCYAI commented 2026-06-15 23:07:56 +00:00
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[🚨 Error] Component CR8, pins 1, 2: LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.

  • Pin 1 is labeled 'C' (cathode) in the schematic and is connected to net N23098459 (from schematic)
  • Pin 2 is labeled 'A' (anode) in the schematic and is connected to net GND (from schematic)
  • Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) (from schematic)
  • Pin 1 is the cathode (negative terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • Pin 2 is the anode (positive terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode (reasoning)
  • With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on (reasoning)
  • A text note near the LED states 'Power Good = LED ON', indicating the LED should illuminate when power is good (from schematic)
  • The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 (reasoning)
  • With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior (reasoning)
  • To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 (reasoning)
  • With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on (reasoning)
All affected pins
Component U30, pin `10`: DCDPG is connected to LED CR8 for power-good indication, but the LED polarity is reversed. The LED anode is connected to GND and cathode to DCDPG, which will prevent the LED from lighting up when power is good.
  • Pin 10 (DCDPG) is connected to net N23098459 (from schematic)
  • N23098459 connects to CR8 pin 1 (cathode) and R288 pin 1 (620 ohm resistor) (from schematic)
  • CR8 pin 2 (anode) is connected to GND (from schematic)
  • R288 pin 2 is connected to SYS_5P0V, providing pull-up for the open-drain DCDPG output (from schematic)
  • DCDPG is an open-drain output that is released (high-Z, pulled high) when power is good and pulled low when power is bad (from datasheet ISL9305IRTHWBNLZ-T, page 2)
  • When power is good, DCDPG is high-Z and pulled to ~5V by R288, placing ~5V at the LED cathode and 0V at the LED anode, reverse-biasing the LED (reasoning)
  • When power is bad, DCDPG pulls N23098459 to GND, placing 0V at both LED terminals with no current flow (reasoning)
  • The LED will not light up in either state with the current polarity (reasoning)
  • The LED connections should be swapped: CR8 pin 1 should connect to GND and CR8 pin 2 should connect to N23098459 (reasoning)
Component CR8, pins `1, 2`: LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.
  • Pin 1 is labeled 'C' (cathode) in the schematic and is connected to net N23098459 (from schematic)
  • Pin 2 is labeled 'A' (anode) in the schematic and is connected to net GND (from schematic)
  • Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) (from schematic)
  • Pin 1 is the cathode (negative terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • Pin 2 is the anode (positive terminal) according to the datasheet (from datasheet LTST-C193KGKT-5A, page 2)
  • For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode (reasoning)
  • With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on (reasoning)
  • A text note near the LED states 'Power Good = LED ON', indicating the LED should illuminate when power is good (from schematic)
  • The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 (reasoning)
  • With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior (reasoning)
  • To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 (reasoning)
  • With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on (reasoning)

Datasheets: 📄 CR8 📄 U30

Replace a datasheet: 📤 CR8 📤 U30

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[🚨 Error] **Component `CR8`, pins `1, 2`: LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.** !thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="70.01,79.79,77.51,89.92" aspect-ratio="1.33" } - Pin 1 is labeled &#x27;C&#x27; (cathode) in the schematic and is connected to net N23098459 *(from schematic)* - Pin 2 is labeled &#x27;A&#x27; (anode) in the schematic and is connected to net GND *(from schematic)* - Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) *(from schematic)* - Pin 1 is the cathode (negative terminal) according to the datasheet *(from datasheet [LTST-C193KGKT-5A](<https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2>), page 2)* - Pin 2 is the anode (positive terminal) according to the datasheet *(from datasheet [LTST-C193KGKT-5A](<https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2>), page 2)* - For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode *(reasoning)* - With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on *(reasoning)* - A text note near the LED states &#x27;Power Good = LED ON&#x27;, indicating the LED should illuminate when power is good *(from schematic)* - The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 *(reasoning)* - With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior *(reasoning)* - To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 *(reasoning)* - With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U30</code>, pin `10`: DCDPG is connected to LED CR8 for power-good indication, but the LED polarity is reversed. The LED anode is connected to GND and cathode to DCDPG, which will prevent the LED from lighting up when power is good.</summary> - Pin 10 (DCDPG) is connected to net N23098459 *(from schematic)* - N23098459 connects to CR8 pin 1 (cathode) and R288 pin 1 (620 ohm resistor) *(from schematic)* - CR8 pin 2 (anode) is connected to GND *(from schematic)* - R288 pin 2 is connected to SYS_5P0V, providing pull-up for the open-drain DCDPG output *(from schematic)* - DCDPG is an open-drain output that is released (high-Z, pulled high) when power is good and pulled low when power is bad *(from datasheet [ISL9305IRTHWBNLZ-T](<https://www.renesas.com/us/en/document/dst/isl9305h-datasheet#page=2>), page 2)* - When power is good, DCDPG is high-Z and pulled to ~5V by R288, placing ~5V at the LED cathode and 0V at the LED anode, reverse-biasing the LED *(reasoning)* - When power is bad, DCDPG pulls N23098459 to GND, placing 0V at both LED terminals with no current flow *(reasoning)* - The LED will not light up in either state with the current polarity *(reasoning)* - The LED connections should be swapped: CR8 pin 1 should connect to GND and CR8 pin 2 should connect to N23098459 *(reasoning)* </details> <details> <summary>Component <code>CR8</code>, pins `1, 2`: LED pins are connected with reversed polarity. Pin 1 (cathode) is connected to the positive side through R288, and pin 2 (anode) is connected to GND, which prevents the LED from ever turning on.</summary> - Pin 1 is labeled &#x27;C&#x27; (cathode) in the schematic and is connected to net N23098459 *(from schematic)* - Pin 2 is labeled &#x27;A&#x27; (anode) in the schematic and is connected to net GND *(from schematic)* - Net N23098459 connects to R288 pin 1, which connects through R288 (620Ω) to SYS_5P0V, and also connects to U30 pin 10 (DCDPG) *(from schematic)* - Pin 1 is the cathode (negative terminal) according to the datasheet *(from datasheet [LTST-C193KGKT-5A](<https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2>), page 2)* - Pin 2 is the anode (positive terminal) according to the datasheet *(from datasheet [LTST-C193KGKT-5A](<https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF#page=2>), page 2)* - For an LED to conduct, the anode must be at a higher potential than the cathode, with current flowing from anode to cathode *(reasoning)* - With the anode at GND (0V) and cathode at approximately 5V (when DCDPG is high-impedance), the LED is reverse biased and will not turn on *(reasoning)* - A text note near the LED states &#x27;Power Good = LED ON&#x27;, indicating the LED should illuminate when power is good *(from schematic)* - The DCDPG signal from U30 is typically high-impedance or high when power is good, which would pull N23098459 toward SYS_5P0V through R288 *(reasoning)* - With the current connections, the LED cannot turn on regardless of the DCDPG state, contradicting the intended behavior *(reasoning)* - To achieve the intended functionality, pin 1 (cathode) should be connected to GND and pin 2 (anode) should be connected to N23098459 *(reasoning)* - With corrected connections, when DCDPG is high-impedance (power good), the anode would be at approximately 5V and cathode at GND, forward biasing the LED and turning it on *(reasoning)* </details> </details> Datasheets: [📄 CR8](https://optoelectronics.liteon.com/upload/download/DS22-2007-0094/LTST-C193KGKT-5A.PDF) [📄 U30](https://www.renesas.com/us/en/document/dst/isl9305h-datasheet) <sub>Replace a datasheet: [📤 CR8](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/LTST-C193KGKT-5A) [📤 U30](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/ISL9305IRTHWBNLZ-T)</sub> <sub><sup>💬 Reply to this comment and mention <b>@DRCY</b> to give feedback that DRCY will incorporate on the next run.</sup></sub>
parallella.sdax
DRCYAI commented 2026-06-15 23:07:56 +00:00
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[🚨 Error] Component U36, pin 1: Output enable pin (O̅E̅) is connected to 5P0V (HIGH), which permanently disables the buffer and puts the output in high-impedance state. This appears to be a design error as the buffer serves no function in this configuration.

  • Pin 1 (O̅E̅) is connected to net 5P0V (from schematic)
  • Pin 1 is the output enable input (O̅E̅), which is active LOW (from datasheet NC7SZ125M5X, page 2)
  • When O̅E̅ is LOW, the buffer is enabled and output follows input; when O̅E̅ is HIGH, output is in high-impedance state (from datasheet NC7SZ125M5X, page 2)
  • The 5P0V net is a power rail at approximately 5V, which is a logic HIGH level (reasoning)
  • With O̅E̅ tied HIGH, the buffer is permanently disabled and the output (pin 4) will always be in high-impedance state (reasoning)
  • The buffer serves no function in this configuration since it is always disabled (reasoning)
  • Pin 1 should be connected to GND to enable the buffer, or the buffer should be removed if not needed (reasoning)

Replace a datasheet: 📤 U36

💬 Reply to this comment and mention @DRCY to give feedback that DRCY will incorporate on the next run.

[🚨 Error] **Component `U36`, pin `1`: Output enable pin (O̅E̅) is connected to 5P0V (HIGH), which permanently disables the buffer and puts the output in high-impedance state. This appears to be a design error as the buffer serves no function in this configuration.** !thumbnail[](parallella.sdax){ diff="AllSpice-Demos/Parallella-AI-Demo:e3bd227a2e06a51e009f1a792a46dc8301aad123...c43f795f4858df4442aa64dee09c27eb5a1d49f0" pr="8" doc-id="899dffe5006059bf8b9b" diff-visibility="full" variant="default" view-coords="18.54,25.21,26.04,32.71" aspect-ratio="1.33" } - Pin 1 (O̅E̅) is connected to net 5P0V *(from schematic)* - Pin 1 is the output enable input (O̅E̅), which is active LOW *(from datasheet [NC7SZ125M5X](<https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/NC7SZ125M5X/NC7SZ125-D.PDF#page=2>), page 2)* - When O̅E̅ is LOW, the buffer is enabled and output follows input; when O̅E̅ is HIGH, output is in high-impedance state *(from datasheet [NC7SZ125M5X](<https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/raw/commit/d86f880abf4c72a7a39d3337390ac1a0a22b177c/.allspice/datasheets/NC7SZ125M5X/NC7SZ125-D.PDF#page=2>), page 2)* - The 5P0V net is a power rail at approximately 5V, which is a logic HIGH level *(reasoning)* - With O̅E̅ tied HIGH, the buffer is permanently disabled and the output (pin 4) will always be in high-impedance state *(reasoning)* - The buffer serves no function in this configuration since it is always disabled *(reasoning)* - Pin 1 should be connected to GND to enable the buffer, or the buffer should be removed if not needed *(reasoning)* <sub>Replace a datasheet: [📤 U36](https://hub.allspice.io/AllSpice-Demos/Parallella-AI-Demo/_upload/develop/.allspice/datasheets/NC7SZ125M5X)</sub> <sub><sup>💬 Reply to this comment and mention <b>@DRCY</b> to give feedback that DRCY will incorporate on the next run.</sup></sub>
allspice-carah requested review from allspice-thomas 2026-06-17 15:45:13 +00:00
allspice-carah requested review from nick 2026-06-17 15:45:19 +00:00
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