AllSpice-Resources/Altium-component-library-demo
20
Fork 0
Files Issues 3 Design Reviews 2 Actions Activity

Change pin order on symbol ADUM4160 #22

Open
AllSpiceAlice wants to merge 2 commits from AU/update_component into main
pull from: AU/update_component
merge into: AllSpice-Resources:main
Conversation 2 Commits 2 Changes 1
AllSpiceAlice commented 2023-08-29 13:38:22 +00:00
Owner
Copy Link

Resolved Issues

Closes 21: Update pins on symbol ADUM4160

Description

Changed pins to match datasheet, differential pins were unclear.

Design Review Checklist

Process

  • Commits in correct branch
  • File names follow standard
  • Update project README page

System

  • Power
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review

Components

  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power

Schematics

  • Microcontrollers / ICs
    • Check the data sheet errata and apnotes for weird IC behaviors
  • Busses
  • Analog
    • Sufficient power rails for analog circuits
    • Amplifiers checked for stability
    • Consider signal rate-of-rise and fall for noise radiation
  • General
    • Sufficient bulk capacitance calculated
    • Polarized components checked
    • Electrolytic/tantalum capacitors checked for no reverse voltage
    • Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
    • Check pin numbers of all custom-generated parts
    • Check reverse base-emitter current/voltage on bipolar transistors
    • Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
    • Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default

PCB

  • Manufacturing
    • PCB manufacturing requirements noted on fab layer
      • Plating specified
        • Plating material
        • Plating thickness
      • Layer stack-up specified
      • Minimum trace/space specified
      • Minimum hole size specified
      • Controlled impedance specified
      • Blind or buried vias specified
  • Footprints
    • Pin 1 marked in a consistent manner
    • Component polarity marked
      • Diodes, LEDs
      • Electrolytic, tantalum capacitors
      • Keyed components like connectors
    • Footprint dimensions cross-checked with datasheet recommendation
    • Sufficient thermal pads on high-power components or nets
  • Clearance
    • Keep-out areas honored
      • Around mounting holes
      • For programming tools
      • For assembly tools (wrenches, screwdrivers etc.)
      • For connectors
    • Trace-to-trace clearance based upon voltage rating
    • Component size based upon voltage rating
  • Mechanical
    • CAD file uploaded
    • Clearance above connectors
    • Clearance below through-hole components
    • Mounting holes electrically isolated if necessary
      • Mounting holes have via stitching
    • Hole diameters leave margin for plating
  • Electrical
    • ERC passes
    • Isolation barriers are large enough
  • Signal integrity
    • Gaps in ground planes checked and minimized
    • High-speed signals avoid gaps in ground planes
    • Stubs minimized for high-speed signals
    • Differential pair spacing based upon impedance matching
    • Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
    • Option for a shielding can over sensitive circuitry e.g. RF?
  • Copper pour
    • All planes have been poured
    • Planes and pours checked for high-impedance paths
    • No pour between adjacent pins on ICs
  • Traces
    • Trace-pad connections sufficiently obtuse (angle 90 deg or more)
    • Trace widths sufficient for the current draw and max heating
    • No connections between adjacent pins on ICs
    • Vias for internal power traces sufficiently large
    • Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
  • Thermal
    • Temperature sensitive components placed away from hot components
    • Thermal vias in thermal pads
  • Silk screen
    • Notes and documentation
      • Updated revision number
      • Updated date
    • No silk screen over pads / vias
    • Text is readable from at most two directions
    • Silk screen size / font will legible after printing
    • Connector pin-outs labeled
    • Fuse size and type marked on PCB
    • Functional groups marked
    • Functionality labeled
      • Test points
      • LEDs
      • Buttons
      • Connectors/terminals
      • Jumpers/fuses
## Resolved Issues Closes 21: Update pins on symbol ADUM4160 ## Description Changed pins to match datasheet, differential pins were unclear. ## Design Review Checklist ### Process - [ ] Commits in correct branch - [ ] File names follow standard - [ ] Update project README page ### System - [x] Power - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review ### Components - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power ### Schematics - [x] Microcontrollers / ICs - [x] Check the data sheet errata and apnotes for weird IC behaviors - [x] Busses - [x] UART/USART TX->RX and RX<-TX - [x] I2C SDA and SCL pins correct(https://www.ti.com/lit/an/slva689/slva689.pdf) - [x] Analog - [x] Sufficient power rails for analog circuits - [x] Amplifiers checked for stability - [x] Consider signal rate-of-rise and fall for noise radiation - [ ] General - [x] Sufficient bulk capacitance calculated - [ ] Polarized components checked - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage - [x] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF - [x] Check pin numbers of all custom-generated parts - [ ] Check reverse base-emitter current/voltage on bipolar transistors - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default ### PCB - [x] Manufacturing - [x] PCB manufacturing requirements noted on `fab` layer - [x] Plating specified - [x] Plating material - [x] Plating thickness - [x] Layer stack-up specified - [x] Minimum trace/space specified - [x] Minimum hole size specified - [x] Controlled impedance specified - [x] Blind or buried vias specified - [ ] Footprints - [ ] Pin 1 marked in a consistent manner - [ ] Component polarity marked - [ ] Diodes, LEDs - [ ] Electrolytic, tantalum capacitors - [ ] Keyed components like connectors - [ ] Footprint dimensions cross-checked with datasheet recommendation - [ ] Sufficient thermal pads on high-power components or nets - [ ] Clearance - [ ] Keep-out areas honored - [ ] Around mounting holes - [ ] For programming tools - [ ] For assembly tools (wrenches, screwdrivers etc.) - [ ] For connectors - [ ] Trace-to-trace clearance based upon voltage rating - [ ] Component size based upon voltage rating - [ ] Mechanical - [ ] CAD file uploaded - [ ] Clearance above connectors - [ ] Clearance below through-hole components - [ ] Mounting holes electrically isolated if necessary - [ ] Mounting holes have via stitching - [ ] Hole diameters leave margin for plating - [ ] Electrical - [ ] ERC passes - [ ] Isolation barriers are large enough - [ ] Signal integrity - [ ] Gaps in ground planes checked and minimized - [ ] High-speed signals avoid gaps in ground planes - [ ] Stubs minimized for high-speed signals - [ ] Differential pair spacing based upon impedance matching - [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda) - [ ] Option for a shielding can over sensitive circuitry e.g. RF? - [ ] Copper pour - [ ] All planes have been poured - [ ] Planes and pours checked for high-impedance paths - [ ] No pour between adjacent pins on ICs - [ ] Traces - [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more) - [ ] Trace widths sufficient for the current draw and max heating - [ ] No connections between adjacent pins on ICs - [ ] Vias for internal power traces sufficiently large - [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces - [ ] Thermal - [ ] Temperature sensitive components placed away from hot components - [ ] Thermal vias in thermal pads - [ ] Silk screen - [ ] Notes and documentation - [ ] Updated revision number - [ ] Updated date - [ ] No silk screen over pads / vias - [ ] Text is readable from at most two directions - [ ] Silk screen size / font will legible after printing - [ ] Connector pin-outs labeled - [ ] Fuse size and type marked on PCB - [ ] Functional groups marked - [ ] Functionality labeled - [ ] Test points - [ ] LEDs - [ ] Buttons - [ ] Connectors/terminals - [ ] Jumpers/fuses <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
AllSpiceAlice added the
3 - medium
documentation
 labels 2023-08-29 13:38:22 +00:00
AllSpiceAlice added 1 commit 2023-08-29 13:38:23 +00:00
AllSpiceAlice requested review from RevaReviewa 2023-08-29 14:05:05 +00:00
RevaReviewa commented 2023-08-29 14:10:20 +00:00
First-time contributor
Copy Link

@AllSpiceUser can you add a title to the component "USB Isolator"?

@AllSpiceUser can you add a title to the component "USB Isolator"?
Screenshot 2023-08-29 at 9.07.34 AM.png
72 KiB
Screenshot 2023-08-29 at 9.07.34 AM.png
AllSpiceAlice added 1 commit 2023-08-29 14:11:16 +00:00
AllSpiceAlice commented 2023-08-29 14:12:30 +00:00
Author
Owner
Copy Link

@AllSpiceUser can you add a title to the component "USB Isolator"?

@RevaReviewa I've added the title.

> @AllSpiceUser can you add a title to the component "USB Isolator"? @RevaReviewa I've added the title.
Screenshot 2023-08-29 at 9.11.45 AM.png
43 KiB
Screenshot 2023-08-29 at 9.11.45 AM.png
This design review can be merged automatically.
You are not authorized to merge this design review.
View command line instructions.

Checkout

From your project repository, check out a new branch and test the changes.
git fetch -u origin AU/update_component:AU/update_component
git checkout AU/update_component
Sign in to join this conversation.
Reviewers
No Reviewers
RevaReviewa
Labels
Clear labels
1 - idea
Nice to have or idea to capture
2 - low
Should be resolved eventually
3 - medium
Should be resolved before product launch
4 - high
Should be resolved before next release
5 - critical
Must be fixed immediately - blocking item
bug
Something doesn't work
dfm
Design for manufacturing consideration
documentation
Improvements to supporting documentation
eol
End of life component
feature
New feature or request
firmware
Requires FW attention
layout
Requires PCB layout attention
mechanical
Requires ME attention
No Label
3 - medium
documentation
Milestone
No items
No Milestone
Assignees
Clear assignees
AllSpiceAlice allspice-carah allspice-eli allspice-hermes allspice-kyle allspice-thomas McRaeAlex rowan sam sherry Tayawiggins
No Assignees
2 Participants
Notifications
Due Date
No due date set.
Dependencies

No dependencies set.

Reference: AllSpice-Resources/Altium-component-library-demo#22
No description provided.
Delete Branch "AU/update_component"

Deleting a branch is permanent. Although the deleted branch may continue to exist for a short time before it actually gets removed, it CANNOT be undone in most cases. Continue?