AllSpice/ArchimajorDemo

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bugfix_general #21

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AllSpiceAlice wants to merge 3 commits from bugfix_general into develop

AllSpiceAlice commented

2023-04-17 00:51:43 +00:00

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This short description prepends any pull request. It is fully markdown compatible. See markdown guide for examples of what you can do!

Resolved Issues

...

Description

...

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
- Components follow preferred reference designator pattern
External I/O
- Filtered for EMI
- Protected against electrostatic discharge (ESD)
- Unused inputs terminated
Microcontrollers / ICs
- Predictable or controlled power-up state
  - Reset filtered
- Sufficient bypass capacitance
- Oscillators checked for reliable startup
- Pullups on open-collector pins
- Logic-low and logic-high voltage levels checked
- No-connect pins labeled NC
- Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
- Check for input voltages applied with power off and CMOS latchup possibilities
- Check the data sheet errata and apnotes for weird IC behaviors
Busses
- UART/USART TX->RX and RX<-TX
- I2C SDA and SCL pullup with appropriate value per capacitance
- Setup, hold, access times for data and address busses
Analog
- Sufficient power rails for analog circuits
- Amplifiers checked for stability
- Consider signal rate-of-rise and fall for noise radiation
General
- Sufficient bulk capacitance calculated
- Polarized components checked
- Electrolytic/tantalum capacitors checked for no reverse voltage
- Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
- Sufficient capacitance on low dropout voltage regulators
- Sufficient time delays and slew rates for comparators
- Sufficient common mode input voltage rating on opamps
- Check pin numbers of all custom-generated parts
- Check reverse base-emitter current/voltage on bipolar transistors
- Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
- Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default

PCB

Manufacturing
- PCB manufacturing requirements noted on fab layer
  - Plating specified
    - Plating material
    - Plating thickness
  - Layer stack-up specified
  - Minimum trace/space specified
  - Minimum hole size specified
  - PCB color specified
  - Silkscreen color specified
  - Controlled impedance specified
  - Blind or buried vias specified
  - Panelization specified
    - External routing specified (ex. v-groove vs route)
  - Drill table generated
  - All specifications exceed manufacturing tolerance
- Space between power planes minimized
- Solder paste openings proper size
- Fiducials placed if necessary
Footprints
- Pin 1 marked in a consistent manner
- Component polarity marked
  - Diodes, LEDs
  - Electrolytic, tantalum capacitors
  - Keyed components like connectors
- Footprint dimensions cross-checked with datasheet recommendation
- Sufficient thermal pads on high-power components or nets
Placement
- Jumpers accessible
- Debug connectors accessible
- Filter resistors closer to source
- Termination resistors close to target
- Small loop path on switch-mode power supplies
- Bypass capacitors close to ICs
- Bypass capacitors close to connectors
- Drivers / receivers close to connectors
- SMT components on top side, through-hole components on bottom side if possible
Clearance
- Keep-out areas honored
  - Around mounting holes
  - For programming tools
  - For assembly tools (wrenches, screwdrivers etc.)
  - For connectors
- Trace-to-trace clearance based upon voltage rating
- Component size based upon voltage rating
- Keep components away from board edge
Mechanical
- CAD file uploaded
- Clearance above connectors
- Clearance below through-hole components
- Enough space for the minimum bending radius of the wire harness
- Mounting holes electrically isolated if necessary
  - Mounting holes have via stitching
- Hole diameters leave margin for plating
- Board outline defined
- Mechanical enclosure defined
- Internal corners are rounded and can be milled
Electrical
- All traces are routed
- Analog and digital commons joined at only one point
- ERC passes
- Isolation barriers are large enough
Signal integrity
- Gaps in ground planes checked and minimized
- High-speed signals avoid gaps in ground planes
- Stubs minimized for high-speed signals
- Differential pair spacing based upon impedance matching
- Transmission lines terminated with an appropriate impedance
- Crystal connections kept short
- Guard ring around crystals
- Traces avoided under sensitive components
- Traces avoided under noisy components
- Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
- Option for a shielding can over sensitive circuitry e.g. RF?
Copper pour
- All planes have been poured
- Planes and pours checked for high-impedance paths
- No pour between adjacent pins on ICs
Traces
- Trace-pad connections sufficiently obtuse (angle 90 deg or more)
- Trace widths sufficient for the current draw and max heating
- No connections between adjacent pins on ICs
- Vias for internal power traces sufficiently large
- Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
Thermal
- Temperature sensitive components placed away from hot components
- Thermal vias in thermal pads
Testing
- Test points on PCBs for critical circuits, hard to reach nets
- Ground connection points close to analog test points
Silk screen
- Notes and documentation
  - Updated revision number
  - Updated date
  - Blank space designated for a serial / assembly number
- No silk screen over pads / vias
- Text is readable from at most two directions
- Silk screen size / font will legible after printing
- Connector pin-outs labeled
- Fuse size and type marked on PCB
- Functional groups marked
- Functionality labeled
  - Test points
  - LEDs
  - Buttons
  - Connectors/terminals
  - Jumpers/fuses

*This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!* ## Resolved Issues  ... ## Description  ... ## Design Review Checklist ### Process - [ ] Commits in correct branch - [ ] Schematic and PCB file names follow standard - [ ] Export necessary review files (3D model, BOM, etc.) - [ ] Update relevant system architecture documents - [ ] Update project README page - [ ] Simulations uploaded and outputs explained ### System - [ ] Power - [ ] Sufficient power supplied from upstream source - [ ] Supply rated for necessary country specifications - [ ] Estimated total worst-case power supply draw - [ ] Connectors - [ ] I/Os are specified - [ ] Sufficient Current and Voltage rating - [ ] Mating connectors have matching pinout - [ ] Same contact material specified for mating connectors - [ ] Testing - [ ] Test procedure written - [ ] Environmental - [ ] Specified min/max operating temperature - [ ] Specified min/max storage temperature - [ ] Specified min/max humidity - [ ] ROHS compliance requirement review ### Components - [ ] Unpopulated components are denoted DNI - [ ] Components meet environmental specifications - [ ] All components have quantity, reference designator and description - [ ] Suggested and alternate manufacturers listed - [ ] Price and stock checked for each component - [ ] Component derating - [ ] Voltage - [ ] Current - [ ] Power at worst-case operating temperature - [ ] Temperature at worst-case power ### Schematics - [ ] Document - [ ] Dot on each connection - [ ] No four-point connections - [ ] Title block completed for each sheet - [ ] All components have reference designators and values - [ ] Multi-part components don't have unplaced symbols - [ ] Page title present and consistent on all pages if not in title block - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins - [ ] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [ ] Components follow preferred reference designator pattern  - [ ] External I/O - [ ] Filtered for EMI - [ ] Protected against electrostatic discharge (ESD) - [ ] Unused inputs terminated - [ ] Microcontrollers / ICs - [ ] Predictable or controlled power-up state - [ ] Reset filtered - [ ] Sufficient bypass capacitance - [ ] Oscillators checked for reliable startup - [ ] Pullups on open-collector pins - [ ] Logic-low and logic-high voltage levels checked - [ ] No-connect pins labeled NC - [ ] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination - [ ] Check for input voltages applied with power off and CMOS latchup possibilities - [ ] Check the data sheet errata and apnotes for weird IC behaviors - [ ] Busses - [ ] UART/USART TX->RX and RX<-TX - [ ] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Setup, hold, access times for data and address busses - [ ] Analog - [ ] Sufficient power rails for analog circuits - [ ] Amplifiers checked for stability - [ ] Consider signal rate-of-rise and fall for noise radiation - [ ] General - [ ] Sufficient bulk capacitance calculated - [ ] Polarized components checked - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF - [ ] Sufficient capacitance on low dropout voltage regulators - [ ] Sufficient time delays and slew rates for comparators - [ ] Sufficient common mode input voltage rating on opamps - [ ] Check pin numbers of all custom-generated parts - [ ] Check reverse base-emitter current/voltage on bipolar transistors - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default ### PCB - [ ] Manufacturing - [ ] PCB manufacturing requirements noted on `fab` layer - [ ] Plating specified - [ ] Plating material - [ ] Plating thickness - [ ] Layer stack-up specified - [ ] Minimum trace/space specified - [ ] Minimum hole size specified - [ ] PCB color specified - [ ] Silkscreen color specified - [ ] Controlled impedance specified - [ ] Blind or buried vias specified - [ ] Panelization specified - [ ] External routing specified (ex. v-groove vs route) - [ ] Drill table generated - [ ] All specifications exceed manufacturing tolerance - [ ] Space between power planes minimized - [ ] Solder paste openings proper size - [ ] Fiducials placed if necessary - [ ] Footprints - [ ] Pin 1 marked in a consistent manner - [ ] Component polarity marked - [ ] Diodes, LEDs - [ ] Electrolytic, tantalum capacitors - [ ] Keyed components like connectors - [ ] Footprint dimensions cross-checked with datasheet recommendation - [ ] Sufficient thermal pads on high-power components or nets - [ ] Placement - [ ] Jumpers accessible - [ ] Debug connectors accessible - [ ] Filter resistors closer to source - [ ] Termination resistors close to target - [ ] Small loop path on switch-mode power supplies - [ ] Bypass capacitors close to ICs - [ ] Bypass capacitors close to connectors - [ ] Drivers / receivers close to connectors - [ ] SMT components on top side, through-hole components on bottom side if possible - [ ] Clearance - [ ] Keep-out areas honored - [ ] Around mounting holes - [ ] For programming tools - [ ] For assembly tools (wrenches, screwdrivers etc.) - [ ] For connectors - [ ] Trace-to-trace clearance based upon voltage rating - [ ] Component size based upon voltage rating - [ ] Keep components away from board edge - [ ] Mechanical - [ ] CAD file uploaded - [ ] Clearance above connectors - [ ] Clearance below through-hole components - [ ] Enough space for the minimum bending radius of the wire harness - [ ] Mounting holes electrically isolated if necessary - [ ] Mounting holes have via stitching - [ ] Hole diameters leave margin for plating - [ ] Board outline defined - [ ] Mechanical enclosure defined - [ ] Internal corners are rounded and can be milled - [ ] Electrical - [ ] All traces are routed - [ ] Analog and digital commons joined at only one point - [ ] ERC passes - [ ] Isolation barriers are large enough - [ ] Signal integrity - [ ] Gaps in ground planes checked and minimized - [ ] High-speed signals avoid gaps in ground planes - [ ] Stubs minimized for high-speed signals - [ ] Differential pair spacing based upon impedance matching - [ ] Transmission lines terminated with an appropriate impedance - [ ] Crystal connections kept short - [ ] Guard ring around crystals - [ ] Traces avoided under sensitive components - [ ] Traces avoided under noisy components - [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda) - [ ] Option for a shielding can over sensitive circuitry e.g. RF? - [ ] Copper pour - [ ] All planes have been poured - [ ] Planes and pours checked for high-impedance paths - [ ] No pour between adjacent pins on ICs - [ ] Traces - [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more) - [ ] Trace widths sufficient for the current draw and max heating - [ ] No connections between adjacent pins on ICs - [ ] Vias for internal power traces sufficiently large - [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces - [ ] Thermal - [ ] Temperature sensitive components placed away from hot components - [ ] Thermal vias in thermal pads - [ ] Testing - [ ] Test points on PCBs for critical circuits, hard to reach nets - [ ] Ground connection points close to analog test points - [ ] Silk screen - [ ] Notes and documentation - [ ] Updated revision number - [ ] Updated date - [ ] Blank space designated for a serial / assembly number - [ ] No silk screen over pads / vias - [ ] Text is readable from at most two directions - [ ] Silk screen size / font will legible after printing - [ ] Connector pin-outs labeled - [ ] Fuse size and type marked on PCB - [ ] Functional groups marked - [ ] Functionality labeled - [ ] Test points - [ ] LEDs - [ ] Buttons - [ ] Connectors/terminals - [ ] Jumpers/fuses

AllSpiceAlice added 42 commits 2023-04-17 00:51:44 +00:00

Merge pull request 'Update files for current repo' (#1 ) from develop into main 746c436ce0

Reviewed-on: AllSpiceUser/ArchimajorDemo#1

Merge pull request 'Update EOL 3pF capacitors' (#3 ) from develop into main dafe88f1dc

Reviewed-on: AllSpiceUser/ArchimajorDemo#3

Merge pull request 'Create PCBA variant to test' (#5 ) from develop into main f1da2ba1ab

Reviewed-on: AllSpiceUser/ArchimajorDemo#5

Merge pull request 'Update PCB layout to reflect previous design review sch changes' (#6 ) from develop into main e09ca167a5

Reviewed-on: AllSpiceUser/ArchimajorDemo#6

Merge pull request 'Add ESD protection to endstop inputs' (#8 ) from develop into main 06bb9de59d

Reviewed-on: AllSpiceUser/ArchimajorDemo#8

Add ESD protection to endstops 8a4da0811e

Foo

Merge pull request 'Update documentation and remove extra channels' (#16 ) from develop into main d9bcca8143

Reviewed-on: AllSpiceUser/ArchimajorDemo#16

Add extra mosfet channel c231abe9d7

Remove ch from mosfets.schdoc 36f514b0f5

Add extra channel, changed 10K res to 5K 6336a173c8

Remove mosfet ch, change R30 to 10K f18e0a468a

Merge branch 'main' into Demo eb71420b18

Merge pull request 'Add mosfet ch' (#18 ) from Demo into main 57812780d5

Reviewed-on: AllSpiceUser/ArchimajorDemo#18

refresh 63e7d86860

refresh 67067636c5

refresh e880dc02e7

Fix corrupted png 23a263c3b1

Fix typo in image synax ddad961c89

Removed unnecessary steps add79697da

Update part number suffix to match package 0497be8603

Added description to sch sheet c124294c5b

Clean up readability 981a133cf8

Redownload of license 5e41187435

Add documentation b636133181

Erase extra end-channel 8bc1aafa46

Increase fan current 02a0fd85cf

Update microcontroller package e96f547463

Improve bias current 841d243a0a

Add current limit 65553e2828

Add power equations to document f7531eb27d

Update signal conditioning 76b7131614

Add layout notes to USB signals 1bce7f32da

Add temp curve to document 8f0a3f8b79

Add documentation 26c5c0c2fe

Merge branch 'refresh' of https://hub.allspice.io/ProductDevelopmentFirm/ArchimajorDemo into refresh 48eff61aa7

Update linguist-generated b352ff976d

Remove obsolete filter 895602c82a

Fix submodule reference 4f366e9b1e

Merge pull request 'Refresh file list' (#13 ) from refresh_all into main 1a5c8de63e

Reviewed-on: ProductDevelopmentFirm/ArchimajorDemo#13

Merge pull request 'Update documentation' (#14 ) from refresh into main a383e008f5

Reviewed-on: ProductDevelopmentFirm/ArchimajorDemo#14

add new mosfet channel d6a5512d7f

Delete diode, change R29 Val b1cf79a38a

AllSpiceAlice added 1 commit 2023-04-17 00:55:20 +00:00

Delete channel, test out adding cap affbdb1597

AllSpiceAlice closed this pull request

2023-04-17 00:58:42 +00:00

AllSpiceAlice reviewed 2023-06-28 18:25:43 +00:00

Mosfets.SchDoc

AllSpiceAlice commented

2023-06-28 18:25:43 +00:00

Author

Contributor

Remove extra channel

!thumbnail[](Mosfets.SchDoc){ diff="ProductDevelopmentFirm/ArchimajorDemo:2da01551312e13d387fec5fee1df3a3bb1d370c9...affbdb15972ce6f128a52f0978a714425536e46a" pr="21" diff-visibility="full" variant="default" view-coords="3.0,72.7,88.9,90.1" aspect-ratio="1.284" } Remove extra channel

AllSpiceAlice added a new dependency 2023-06-28 18:26:43 +00:00

#20 Add topics to repo for demo

AllSpiceAlice removed a dependency 2023-06-28 18:26:52 +00:00

#20 Add topics to repo for demo

AllSpiceAlice added a new dependency 2023-06-28 18:26:59 +00:00

#28 Remove extra channel

daniel-allspice reviewed 2023-11-30 16:56:10 +00:00

Archimajor.PcbDoc

daniel-allspice commented

2023-11-30 16:56:10 +00:00

Member

@daniel , can you rotate this component and see if the new circuit fits to the right?

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice/ArchimajorDemo:a383e008f58436565307e755b6a3a8db2d561eff...affbdb15972ce6f128a52f0978a714425536e46a" pr="21" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="51.5,3.8,65.6,21.9" aspect-ratio="1.346" } @daniel , can you rotate this component and see if the new circuit fits to the right?

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