Create R&D deviation DEV-A #32

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AllSpiceAlice wants to merge 5 commits from develop into main

AllSpiceAlice commented

2023-08-28 23:59:59 +00:00

Contributor

This short description prepends any pull request. It is fully markdown compatible. See markdown guide for examples of what you can do!

Resolved Issues

...

Description

...

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
- Components follow preferred reference designator pattern
External I/O
- Filtered for EMI
- Protected against electrostatic discharge (ESD)
- Unused inputs terminated
Microcontrollers / ICs
- Predictable or controlled power-up state
  - Reset filtered
- Sufficient bypass capacitance
- Oscillators checked for reliable startup
- Pullups on open-collector pins
- Logic-low and logic-high voltage levels checked
- No-connect pins labeled NC
- Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
- Check for input voltages applied with power off and CMOS latchup possibilities
- Check the data sheet errata and apnotes for weird IC behaviors
Busses
- UART/USART TX->RX and RX<-TX
- I2C SDA and SCL pullup with appropriate value per capacitance
- Setup, hold, access times for data and address busses
Analog
- Sufficient power rails for analog circuits
- Amplifiers checked for stability
- Consider signal rate-of-rise and fall for noise radiation
General
- Sufficient bulk capacitance calculated
- Polarized components checked
- Electrolytic/tantalum capacitors checked for no reverse voltage
- Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
- Sufficient capacitance on low dropout voltage regulators
- Sufficient time delays and slew rates for comparators
- Sufficient common mode input voltage rating on opamps
- Check pin numbers of all custom-generated parts
- Check reverse base-emitter current/voltage on bipolar transistors
- Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
- Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default

PCB

Manufacturing
- PCB manufacturing requirements noted on fab layer
  - Plating specified
    - Plating material
    - Plating thickness
  - Layer stack-up specified
  - Minimum trace/space specified
  - Minimum hole size specified
  - PCB color specified
  - Silkscreen color specified
  - Controlled impedance specified
  - Blind or buried vias specified
  - Panelization specified
    - External routing specified (ex. v-groove vs route)
  - Drill table generated
  - All specifications exceed manufacturing tolerance
- Space between power planes minimized
- Solder paste openings proper size
- Fiducials placed if necessary
Footprints
- Pin 1 marked in a consistent manner
- Component polarity marked
  - Diodes, LEDs
  - Electrolytic, tantalum capacitors
  - Keyed components like connectors
- Footprint dimensions cross-checked with datasheet recommendation
- Sufficient thermal pads on high-power components or nets
Placement
- Jumpers accessible
- Debug connectors accessible
- Filter resistors closer to source
- Termination resistors close to target
- Small loop path on switch-mode power supplies
- Bypass capacitors close to ICs
- Bypass capacitors close to connectors
- Drivers / receivers close to connectors
- SMT components on top side, through-hole components on bottom side if possible
Clearance
- Keep-out areas honored
  - Around mounting holes
  - For programming tools
  - For assembly tools (wrenches, screwdrivers etc.)
  - For connectors
- Trace-to-trace clearance based upon voltage rating
- Component size based upon voltage rating
- Keep components away from board edge
Mechanical
- CAD file uploaded
- Clearance above connectors
- Clearance below through-hole components
- Enough space for the minimum bending radius of the wire harness
- Mounting holes electrically isolated if necessary
  - Mounting holes have via stitching
- Hole diameters leave margin for plating
- Board outline defined
- Mechanical enclosure defined
- Internal corners are rounded and can be milled
Electrical
- All traces are routed
- Analog and digital commons joined at only one point
- ERC passes
- Isolation barriers are large enough
Signal integrity
- Gaps in ground planes checked and minimized
- High-speed signals avoid gaps in ground planes
- Stubs minimized for high-speed signals
- Differential pair spacing based upon impedance matching
- Transmission lines terminated with an appropriate impedance
- Crystal connections kept short
- Guard ring around crystals
- Traces avoided under sensitive components
- Traces avoided under noisy components
- Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
- Option for a shielding can over sensitive circuitry e.g. RF?
Copper pour
- All planes have been poured
- Planes and pours checked for high-impedance paths
- No pour between adjacent pins on ICs
Traces
- Trace-pad connections sufficiently obtuse (angle 90 deg or more)
- Trace widths sufficient for the current draw and max heating
- No connections between adjacent pins on ICs
- Vias for internal power traces sufficiently large
- Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
Thermal
- Temperature sensitive components placed away from hot components
- Thermal vias in thermal pads
Testing
- Test points on PCBs for critical circuits, hard to reach nets
- Ground connection points close to analog test points
Silk screen
- Notes and documentation
  - Updated revision number
  - Updated date
  - Blank space designated for a serial / assembly number
- No silk screen over pads / vias
- Text is readable from at most two directions
- Silk screen size / font will legible after printing
- Connector pin-outs labeled
- Fuse size and type marked on PCB
- Functional groups marked
- Functionality labeled
  - Test points
  - LEDs
  - Buttons
  - Connectors/terminals
  - Jumpers/fuses

*This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!* ## Resolved Issues  ... ## Description  ... ## Design Review Checklist ### Process - [x] Commits in correct branch - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [ ] Update project README page - [ ] Simulations uploaded and outputs explained ### System - [ ] Power - [ ] Sufficient power supplied from upstream source - [ ] Supply rated for necessary country specifications - [ ] Estimated total worst-case power supply draw - [ ] Connectors - [ ] I/Os are specified - [ ] Sufficient Current and Voltage rating - [ ] Mating connectors have matching pinout - [ ] Same contact material specified for mating connectors - [ ] Testing - [ ] Test procedure written - [ ] Environmental - [ ] Specified min/max operating temperature - [ ] Specified min/max storage temperature - [ ] Specified min/max humidity - [ ] ROHS compliance requirement review ### Components - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [ ] Suggested and alternate manufacturers listed - [ ] Price and stock checked for each component - [ ] Component derating - [ ] Voltage - [ ] Current - [ ] Power at worst-case operating temperature - [ ] Temperature at worst-case power ### Schematics - [ ] Document - [ ] Dot on each connection - [ ] No four-point connections - [ ] Title block completed for each sheet - [ ] All components have reference designators and values - [ ] Multi-part components don't have unplaced symbols - [ ] Page title present and consistent on all pages if not in title block - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins - [ ] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [ ] Components follow preferred reference designator pattern  - [ ] External I/O - [ ] Filtered for EMI - [ ] Protected against electrostatic discharge (ESD) - [ ] Unused inputs terminated - [ ] Microcontrollers / ICs - [ ] Predictable or controlled power-up state - [ ] Reset filtered - [ ] Sufficient bypass capacitance - [ ] Oscillators checked for reliable startup - [ ] Pullups on open-collector pins - [ ] Logic-low and logic-high voltage levels checked - [ ] No-connect pins labeled NC - [ ] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination - [ ] Check for input voltages applied with power off and CMOS latchup possibilities - [ ] Check the data sheet errata and apnotes for weird IC behaviors - [ ] Busses - [ ] UART/USART TX->RX and RX<-TX - [ ] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Setup, hold, access times for data and address busses - [ ] Analog - [ ] Sufficient power rails for analog circuits - [ ] Amplifiers checked for stability - [ ] Consider signal rate-of-rise and fall for noise radiation - [ ] General - [ ] Sufficient bulk capacitance calculated - [ ] Polarized components checked - [ ] Electrolytic/tantalum capacitors checked for no reverse voltage - [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF - [ ] Sufficient capacitance on low dropout voltage regulators - [ ] Sufficient time delays and slew rates for comparators - [ ] Sufficient common mode input voltage rating on opamps - [ ] Check pin numbers of all custom-generated parts - [ ] Check reverse base-emitter current/voltage on bipolar transistors - [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) - [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default ### PCB - [ ] Manufacturing - [ ] PCB manufacturing requirements noted on `fab` layer - [ ] Plating specified - [ ] Plating material - [ ] Plating thickness - [ ] Layer stack-up specified - [ ] Minimum trace/space specified - [ ] Minimum hole size specified - [ ] PCB color specified - [ ] Silkscreen color specified - [ ] Controlled impedance specified - [ ] Blind or buried vias specified - [ ] Panelization specified - [ ] External routing specified (ex. v-groove vs route) - [ ] Drill table generated - [ ] All specifications exceed manufacturing tolerance - [ ] Space between power planes minimized - [ ] Solder paste openings proper size - [ ] Fiducials placed if necessary - [ ] Footprints - [ ] Pin 1 marked in a consistent manner - [ ] Component polarity marked - [ ] Diodes, LEDs - [ ] Electrolytic, tantalum capacitors - [ ] Keyed components like connectors - [ ] Footprint dimensions cross-checked with datasheet recommendation - [ ] Sufficient thermal pads on high-power components or nets - [ ] Placement - [ ] Jumpers accessible - [ ] Debug connectors accessible - [ ] Filter resistors closer to source - [ ] Termination resistors close to target - [ ] Small loop path on switch-mode power supplies - [ ] Bypass capacitors close to ICs - [ ] Bypass capacitors close to connectors - [ ] Drivers / receivers close to connectors - [ ] SMT components on top side, through-hole components on bottom side if possible - [ ] Clearance - [ ] Keep-out areas honored - [ ] Around mounting holes - [ ] For programming tools - [ ] For assembly tools (wrenches, screwdrivers etc.) - [ ] For connectors - [ ] Trace-to-trace clearance based upon voltage rating - [ ] Component size based upon voltage rating - [ ] Keep components away from board edge - [ ] Mechanical - [ ] CAD file uploaded - [ ] Clearance above connectors - [ ] Clearance below through-hole components - [ ] Enough space for the minimum bending radius of the wire harness - [ ] Mounting holes electrically isolated if necessary - [ ] Mounting holes have via stitching - [ ] Hole diameters leave margin for plating - [ ] Board outline defined - [ ] Mechanical enclosure defined - [ ] Internal corners are rounded and can be milled - [ ] Electrical - [ ] All traces are routed - [ ] Analog and digital commons joined at only one point - [ ] ERC passes - [ ] Isolation barriers are large enough - [ ] Signal integrity - [ ] Gaps in ground planes checked and minimized - [ ] High-speed signals avoid gaps in ground planes - [ ] Stubs minimized for high-speed signals - [ ] Differential pair spacing based upon impedance matching - [ ] Transmission lines terminated with an appropriate impedance - [ ] Crystal connections kept short - [ ] Guard ring around crystals - [ ] Traces avoided under sensitive components - [ ] Traces avoided under noisy components - [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda) - [ ] Option for a shielding can over sensitive circuitry e.g. RF? - [ ] Copper pour - [ ] All planes have been poured - [ ] Planes and pours checked for high-impedance paths - [ ] No pour between adjacent pins on ICs - [ ] Traces - [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more) - [ ] Trace widths sufficient for the current draw and max heating - [ ] No connections between adjacent pins on ICs - [ ] Vias for internal power traces sufficiently large - [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces - [ ] Thermal - [ ] Temperature sensitive components placed away from hot components - [ ] Thermal vias in thermal pads - [ ] Testing - [ ] Test points on PCBs for critical circuits, hard to reach nets - [ ] Ground connection points close to analog test points - [ ] Silk screen - [ ] Notes and documentation - [ ] Updated revision number - [ ] Updated date - [ ] Blank space designated for a serial / assembly number - [ ] No silk screen over pads / vias - [ ] Text is readable from at most two directions - [ ] Silk screen size / font will legible after printing - [ ] Connector pin-outs labeled - [ ] Fuse size and type marked on PCB - [ ] Functional groups marked - [ ] Functionality labeled - [ ] Test points - [ ] LEDs - [ ] Buttons - [ ] Connectors/terminals - [ ] Jumpers/fuses

AllSpiceAlice added the

5 - critical

feature

labels 2023-08-28 23:59:59 +00:00

AllSpiceAlice added 1 commit 2023-08-29 00:00:02 +00:00

f559b90889 remove thermocouple, change trace, add devA note

AllSpiceAlice requested review from RevaReviewa 2023-08-29 00:05:49 +00:00

AllSpiceAlice requested review from PavelInPurchasing 2023-08-29 00:05:49 +00:00

AllSpiceAlice requested review from Allie 2023-08-29 00:05:49 +00:00

AllSpiceAlice requested review from AngelaGlobalPCBA 2023-08-29 00:05:50 +00:00

RevaReviewa requested changes 2023-08-29 00:09:16 +00:00

RevaReviewa left a comment

Member

@AllSpiceUser, can you adjust the bias of this resistor on all the channels?

!snippet[](EndStops.SchDoc){ commit="95719adde8107958bf40467ee092c45b6ddaba00" variant="default" view-coords="5.1,4.4,47.6,24.1" aspect-ratio="1.286" thumbnail="float-left" } @AllSpiceUser, can you adjust the bias of this resistor on all the channels?

👍 1

AllSpiceAlice added 1 commit 2023-08-29 00:11:23 +00:00

17643aa033 Add extra power connector

AllSpiceAlice added 1 commit 2023-08-29 00:11:45 +00:00

dcabb0d680 Change bias to endstop, as requested

AllSpiceAlice reviewed 2023-08-29 00:13:48 +00:00

EndStops.SchDoc

AllSpiceAlice commented

2023-08-29 00:13:41 +00:00

Author

Contributor

@RevaReviewa , how does this look?

!thumbnail[](EndStops.SchDoc){ diff="ProductDevelopmentFirm/ArchimajorDemo:214ac365308d2e3747b0ddafa75d31db2d4aba7a...dcabb0d68047916739c05782923dc9dbdaba63ae" pr="32" diff-visibility="full" variant="default" view-coords="4.0,3.6,48.5,23.0" aspect-ratio="1.284" } @RevaReviewa , how does this look?

👍 1

RevaReviewa commented

2023-08-29 00:15:06 +00:00

Member

@AllSpiceUser, looks great, thank you! 🔥🔥

👍 1

AllSpiceAlice added 1 commit 2023-08-29 00:19:08 +00:00

6702ffa0a4 Delete extra channel, add test ckt, adjust bias

AllSpiceAlice added this to the Release V2 milestone 2023-09-13 18:34:07 +00:00

AllSpiceAlice added 1 commit 2023-09-14 17:19:44 +00:00

fbe99e8edd clean up readme formatting

Allie added a new dependency 2023-09-14 19:47:30 +00:00

#33 Add new test points

Allie removed a dependency 2023-09-14 19:47:47 +00:00

#33 Add new test points

Allie approved these changes 2023-09-14 19:51:39 +00:00

Archimajor.PcbDoc

Allie commented

2023-09-14 19:50:30 +00:00

First-time contributor

@AllSpiceUser @marcus @brendan have you reviewed this yet???????

!thumbnail[](Archimajor.PcbDoc){ diff="ProductDevelopmentFirm/ArchimajorDemo:214ac365308d2e3747b0ddafa75d31db2d4aba7a...fbe99e8edd672ff4bb7cb04a7422846df15ba3f0" pr="32" layers="82,81,74,72,71,69,68,66,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="53.3,13.9,63.3,22.9" aspect-ratio="1.342" } @AllSpiceUser @marcus @brendan have you reviewed this yet???????

AllSpiceAlice commented

2023-09-15 21:10:44 +00:00

Author

Contributor

@Allie thank you for the reminder. I'll do it by EOB Friday

Allie reviewed 2023-09-14 19:52:20 +00:00

Archimajor.PcbDoc

Allie commented

2023-09-14 19:52:20 +00:00

First-time contributor

👍 1

AllSpiceAlice commented

2023-09-15 21:12:45 +00:00

Author

Contributor

I'll adjust the trace width of this net. Thank you!

👍 1

AllSpiceAlice reviewed 2023-09-15 21:07:06 +00:00

USB.SchDoc

AllSpiceAlice commented

2023-09-15 21:07:06 +00:00

Author

Contributor

Add a third connector in case we need the extra current.

!thumbnail[](USB.SchDoc){ diff="ProductDevelopmentFirm/ArchimajorDemo:214ac365308d2e3747b0ddafa75d31db2d4aba7a...fbe99e8edd672ff4bb7cb04a7422846df15ba3f0" pr="32" diff-visibility="full" variant="default" view-coords="74.8,39.0,95.4,57.6" aspect-ratio="1.284" } Add a third connector in case we need the extra current.

👍 1