Added termination control to gpio_io_o_0[15:12] #247
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@ -23004,7 +23004,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Mar 07 02:50:09 UTC 2023</spirit:value>
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<spirit:value>Sun May 07 20:53:22 UTC 2023</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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@ -79,6 +79,7 @@ module dso_top
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reg[63:0] adc_data;
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wire serdes_ready;
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assign term = gpio_io_o_0[15:12];
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assign atten = gpio_io_o_0[19:16];
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assign dc_cpl = gpio_io_o_0[23:20];
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@ -73,8 +73,11 @@
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
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<Proxy FileSetName="design_1_xdma_0_0"/>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
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<Proxy FileSetName="design_1_util_ds_buf_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
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<Proxy FileSetName="design_1_axi_crossbar_0_1"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
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<Proxy FileSetName="design_1_clk_wiz_0_0"/>
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@ -82,33 +85,30 @@
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_clock_converter_0_0/design_1_axi_clock_converter_0_0.xci">
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<Proxy FileSetName="design_1_axi_clock_converter_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
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<Proxy FileSetName="design_1_axi_crossbar_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci">
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<Proxy FileSetName="design_1_axi_gpio_0_1"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci">
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<Proxy FileSetName="design_1_axi_fifo_mm_s_0_0"/>
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</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dwidth_converter_0_0/design_1_axi_dwidth_converter_0_0.xci">
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<Proxy FileSetName="design_1_axi_dwidth_converter_0_0"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
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<Proxy FileSetName="design_1_axi_crossbar_0_1"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_datamover_0_0/design_1_axi_datamover_0_0.xci">
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<Proxy FileSetName="design_1_axi_datamover_0_0"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci">
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||||
<Proxy FileSetName="design_1_mig_7series_0_0"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
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<Proxy FileSetName="design_1_util_ds_buf_0_0"/>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
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||||
<Proxy FileSetName="design_1_axi_crossbar_0_0"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_datamover_0_0/design_1_axi_datamover_0_0.xci">
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||||
<Proxy FileSetName="design_1_axi_datamover_0_0"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dwidth_converter_0_0/design_1_axi_dwidth_converter_0_0.xci">
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||||
<Proxy FileSetName="design_1_axi_dwidth_converter_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci">
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||||
<Proxy FileSetName="design_1_axi_fifo_mm_s_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci">
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||||
<Proxy FileSetName="design_1_util_vector_logic_0_0"/>
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||||
</CompFileExtendedInfo>
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||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
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||||
<Proxy FileSetName="design_1_xdma_0_0"/>
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||||
</CompFileExtendedInfo>
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||||
</File>
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||||
<File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v">
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<FileInfo>
|
||||
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