Added termination control to gpio_io_o_0[15:12] #247

Merged
AleksaBjelogrlic merged 1 commits from FW/Aleksa/TE0712_Rev3_Baseboard into master 2023-05-07 21:07:03 +00:00
4 changed files with 21 additions and 20 deletions

View File

@ -23004,7 +23004,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Mar 07 02:50:09 UTC 2023</spirit:value>
<spirit:value>Sun May 07 20:53:22 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>

View File

@ -79,6 +79,7 @@ module dso_top
reg[63:0] adc_data;
wire serdes_ready;
assign term = gpio_io_o_0[15:12];
assign atten = gpio_io_o_0[19:16];
assign dc_cpl = gpio_io_o_0[23:20];

View File

@ -73,8 +73,11 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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<Proxy FileSetName="design_1_xdma_0_0"/>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
<Proxy FileSetName="design_1_util_ds_buf_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_1"/>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
<Proxy FileSetName="design_1_clk_wiz_0_0"/>
@ -82,33 +85,30 @@
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<Proxy FileSetName="design_1_axi_gpio_0_1"/>
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</File>
<File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v">
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