AllSpice
/
ThunderScope
19
Fork 0
Files Issues 7 Design Reviews Releases Activity

Added termination control to gpio_io_o_0[15:12] #247

Merged
AleksaBjelogrlic merged 1 commits from FW/Aleksa/TE0712_Rev3_Baseboard into master 2023-05-07 21:07:03 +00:00
Conversation 0 Commits 1 Files Changed 4 +21 -20
4 changed files with 21 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xml
View File

@ -23004,7 +23004,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Mar 07 02:50:09 UTC 2023</spirit:value> <spirit:value>Sun May 07 20:53:22 UTC 2023</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>

1
Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/imports/hdl/dso_top.v
View File

@ -79,6 +79,7 @@ module dso_top
reg[63:0] adc_data; reg[63:0] adc_data;
wire serdes_ready; wire serdes_ready;
assign term = gpio_io_o_0[15:12];
assign atten = gpio_io_o_0[19:16]; assign atten = gpio_io_o_0[19:16];
assign dc_cpl = gpio_io_o_0[23:20]; assign dc_cpl = gpio_io_o_0[23:20];

38
Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.xpr
View File

@ -73,8 +73,11 @@
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci"> <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
<Proxy FileSetName="design_1_xdma_0_0"/> <Proxy FileSetName="design_1_util_ds_buf_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_1"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci"> <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
<Proxy FileSetName="design_1_clk_wiz_0_0"/> <Proxy FileSetName="design_1_clk_wiz_0_0"/>
@ -82,33 +85,30 @@
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_clock_converter_0_0/design_1_axi_clock_converter_0_0.xci"> <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_clock_converter_0_0/design_1_axi_clock_converter_0_0.xci">
<Proxy FileSetName="design_1_axi_clock_converter_0_0"/> <Proxy FileSetName="design_1_axi_clock_converter_0_0"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci"> <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci">
<Proxy FileSetName="design_1_axi_gpio_0_1"/> <Proxy FileSetName="design_1_axi_gpio_0_1"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci">
<Proxy FileSetName="design_1_axi_fifo_mm_s_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dwidth_converter_0_0/design_1_axi_dwidth_converter_0_0.xci">
<Proxy FileSetName="design_1_axi_dwidth_converter_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
<Proxy FileSetName="design_1_axi_crossbar_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_datamover_0_0/design_1_axi_datamover_0_0.xci">
<Proxy FileSetName="design_1_axi_datamover_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci"> <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci">
<Proxy FileSetName="design_1_mig_7series_0_0"/> <Proxy FileSetName="design_1_mig_7series_0_0"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci"> <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
<Proxy FileSetName="design_1_util_ds_buf_0_0"/> <Proxy FileSetName="design_1_axi_crossbar_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_datamover_0_0/design_1_axi_datamover_0_0.xci">
<Proxy FileSetName="design_1_axi_datamover_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dwidth_converter_0_0/design_1_axi_dwidth_converter_0_0.xci">
<Proxy FileSetName="design_1_axi_dwidth_converter_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci">
<Proxy FileSetName="design_1_axi_fifo_mm_s_0_0"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci"> <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci">
<Proxy FileSetName="design_1_util_vector_logic_0_0"/> <Proxy FileSetName="design_1_util_vector_logic_0_0"/>
</CompFileExtendedInfo> </CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
<Proxy FileSetName="design_1_xdma_0_0"/>
</CompFileExtendedInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v"> <File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v">
<FileInfo> <FileInfo>

BIN
Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top_TE0712_Rev3_Baseboard.bin
View File

Binary file not shown.