AllSpiceAlice/Altium-Demo-2024-Q2

Fork 1

V2: Add input protection and improve data integrity #6

Merged

daniel-allspice merged 2 commits from develop into main

2024-01-02 03:25:17 +00:00

daniel-allspice commented

2024-01-02 02:58:40 +00:00

Collaborator

Resolved Issues

Closes #2, Fix flakey endstop detection
Closes #3, Fix static damage to fan tachometer detection
Closes #4, Add magnetics to USB data to clean up signal
Closes #5, Add inline resistors to Sercom signals

Description

These changes fix communication and static damage issues on V1

Duplicate Motor 1 -> Motor 2 driver nets
Change Endstop input cap value
Add input protection to Fan tachometer
Add Fan test connector
Add debug header to microcontroller
Add inline drive resistors to SERCOM (Can/UART/SPI)
Add isolated VUSB detection to VBUS_UC
Add filter magnetics to USB D+/-

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
- Components follow preferred reference designator pattern
External I/O
- Filtered for EMI
- Protected against electrostatic discharge (ESD)
- Unused inputs terminated
Microcontrollers / ICs
- Predictable or controlled power-up state
  - Reset filtered
- Sufficient bypass capacitance
- Oscillators checked for reliable startup
- Pullups on open-collector pins
- Logic-low and logic-high voltage levels checked
- No-connect pins labeled NC
- Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
- Check for input voltages applied with power off and CMOS latchup possibilities
- Check the data sheet errata and apnotes for weird IC behaviors
Busses
- UART/USART TX->RX and RX<-TX
- I2C SDA and SCL pullup with appropriate value per capacitance
- Setup, hold, access times for data and address busses
Analog
- Sufficient power rails for analog circuits
- Amplifiers checked for stability
- Consider signal rate-of-rise and fall for noise radiation
General
- Sufficient bulk capacitance calculated
- Polarized components checked
- Electrolytic/tantalum capacitors checked for no reverse voltage
- Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
- Sufficient capacitance on low dropout voltage regulators
- Sufficient time delays and slew rates for comparators
- Sufficient common mode input voltage rating on opamps
- Check pin numbers of all custom-generated parts
- Check reverse base-emitter current/voltage on bipolar transistors
- Power nets use preferred and consistent naming (ex. no 3.3V vs +3.3V)
- Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default

PCB

Manufacturing
- PCB manufacturing requirements noted on fab layer
  - Plating specified
    - Plating material
    - Plating thickness
  - Layer stack-up specified
  - Minimum trace/space specified
  - Minimum hole size specified
  - PCB color specified
  - Silkscreen color specified
  - Controlled impedance specified
  - Blind or buried vias specified
  - Panelization specified
    - External routing specified (ex. v-groove vs route)
  - Drill table generated
  - All specifications exceed manufacturing tolerance
- Space between power planes minimized
- Solder paste openings proper size
- Fiducials placed if necessary
Footprints
- Pin 1 marked in a consistent manner
- Component polarity marked
  - Diodes, LEDs
  - Electrolytic, tantalum capacitors
  - Keyed components like connectors
- Footprint dimensions cross-checked with datasheet recommendation
- Sufficient thermal pads on high-power components or nets
Placement
- Jumpers accessible
- Debug connectors accessible
- Filter resistors closer to source
- Termination resistors close to target
- Small loop path on switch-mode power supplies
- Bypass capacitors close to ICs
- Bypass capacitors close to connectors
- Drivers / receivers close to connectors
- SMT components on top side, through-hole components on bottom side if possible
Clearance
- Keep-out areas honored
  - Around mounting holes
  - For programming tools
  - For assembly tools (wrenches, screwdrivers etc.)
  - For connectors
- Trace-to-trace clearance based upon voltage rating
- Component size based upon voltage rating
- Keep components away from board edge
Mechanical
- CAD file uploaded
- Clearance above connectors
- Clearance below through-hole components
- Enough space for the minimum bending radius of the wire harness
- Mounting holes electrically isolated if necessary
  - Mounting holes have via stitching
- Hole diameters leave margin for plating
- Board outline defined
- Mechanical enclosure defined
- Internal corners are rounded and can be milled
Electrical
- All traces are routed
- Analog and digital commons joined at only one point
- ERC passes
- Isolation barriers are large enough
Signal integrity
- Gaps in ground planes checked and minimized
- High-speed signals avoid gaps in ground planes
- Stubs minimized for high-speed signals
- Differential pair spacing based upon impedance matching
- Transmission lines terminated with an appropriate impedance
- Crystal connections kept short
- Guard ring around crystals
- Traces avoided under sensitive components
- Traces avoided under noisy components
- Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
- Option for a shielding can over sensitive circuitry e.g. RF?
Copper pour
- All planes have been poured
- Planes and pours checked for high-impedance paths
- No pour between adjacent pins on ICs
Traces
- Trace-pad connections sufficiently obtuse (angle 90 deg or more)
- Trace widths sufficient for the current draw and max heating
- No connections between adjacent pins on ICs
- Vias for internal power traces sufficiently large
- Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
Thermal
- Temperature sensitive components placed away from hot components
- Thermal vias in thermal pads
Testing
- Test points on PCBs for critical circuits, hard to reach nets
- Ground connection points close to analog test points
Silk screen
- Notes and documentation
  - Updated revision number
  - Updated date
  - Blank space designated for a serial / assembly number
- No silk screen over pads / vias
- Text is readable from at most two directions
- Silk screen size / font will legible after printing
- Connector pin-outs labeled
- Fuse size and type marked on PCB
- Functional groups marked
- Functionality labeled
  - Test points
  - LEDs
  - Buttons
  - Connectors/terminals
  - Jumpers/fuses

## Resolved Issues - Closes #2, Fix flakey endstop detection - Closes #3, Fix static damage to fan tachometer detection - Closes #4, Add magnetics to USB data to clean up signal - Closes #5, Add inline resistors to Sercom signals ## Description These changes fix communication and static damage issues on V1 - Duplicate Motor 1 -> Motor 2 driver nets - Change Endstop input cap value - Add input protection to Fan tachometer - Add Fan test connector - Add debug header to microcontroller - Add inline drive resistors to SERCOM (Can/UART/SPI) - Add isolated VUSB detection to VBUS_UC - Add filter magnetics to USB D+/- ## Design Review Checklist ### Process - [x] Commits in correct branch - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained ### System - [x] Power - [x] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review ### Components - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power ### Schematics - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name) - [x] Components follow preferred reference designator pattern  - [x] External I/O - [x] Filtered for EMI - [x] Protected against electrostatic discharge (ESD) - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Predictable or controlled power-up state - [x] Reset filtered - [x] Sufficient bypass capacitance - [x] Oscillators checked for reliable startup - [x] Pullups on open-collector pins - [x] Logic-low and logic-high voltage levels checked - [x] No-connect pins labeled NC - [x] Clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination - [x] Check for input voltages applied with power off and CMOS latchup possibilities - [x] Check the data sheet errata and apnotes for weird IC behaviors - [x] Busses - [x] UART/USART TX->RX and RX<-TX - [x] I2C SDA and SCL pullup with appropriate value [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [x] Setup, hold, access times for data and address busses - [x] Analog - [x] Sufficient power rails for analog circuits - [x] Amplifiers checked for stability - [x] Consider signal rate-of-rise and fall for noise radiation - [x] General - [x] Sufficient bulk capacitance calculated - [x] Polarized components checked - [x] Electrolytic/tantalum capacitors checked for no reverse voltage - [x] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF - [x] Sufficient capacitance on low dropout voltage regulators - [x] Sufficient time delays and slew rates for comparators - [x] Sufficient common mode input voltage rating on opamps - [x] Check pin numbers of all custom-generated parts - [x] Check reverse base-emitter current/voltage on bipolar transistors - [x] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`) - [x] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default ### PCB - [x] Manufacturing - [x] PCB manufacturing requirements noted on `fab` layer - [x] Plating specified - [x] Plating material - [x] Plating thickness - [x] Layer stack-up specified - [x] Minimum trace/space specified - [x] Minimum hole size specified - [x] PCB color specified - [x] Silkscreen color specified - [x] Controlled impedance specified - [x] Blind or buried vias specified - [x] Panelization specified - [x] External routing specified (ex. v-groove vs route) - [x] Drill table generated - [x] All specifications exceed manufacturing tolerance - [x] Space between power planes minimized - [x] Solder paste openings proper size - [x] Fiducials placed if necessary - [x] Footprints - [x] Pin 1 marked in a consistent manner - [x] Component polarity marked - [x] Diodes, LEDs - [x] Electrolytic, tantalum capacitors - [x] Keyed components like connectors - [x] Footprint dimensions cross-checked with datasheet recommendation - [x] Sufficient thermal pads on high-power components or nets - [x] Placement - [x] Jumpers accessible - [x] Debug connectors accessible - [x] Filter resistors closer to source - [x] Termination resistors close to target - [x] Small loop path on switch-mode power supplies - [x] Bypass capacitors close to ICs - [x] Bypass capacitors close to connectors - [x] Drivers / receivers close to connectors - [x] SMT components on top side, through-hole components on bottom side if possible - [x] Clearance - [x] Keep-out areas honored - [x] Around mounting holes - [x] For programming tools - [x] For assembly tools (wrenches, screwdrivers etc.) - [x] For connectors - [x] Trace-to-trace clearance based upon voltage rating - [x] Component size based upon voltage rating - [x] Keep components away from board edge - [x] Mechanical - [x] CAD file uploaded - [x] Clearance above connectors - [x] Clearance below through-hole components - [x] Enough space for the minimum bending radius of the wire harness - [x] Mounting holes electrically isolated if necessary - [x] Mounting holes have via stitching - [x] Hole diameters leave margin for plating - [x] Board outline defined - [x] Mechanical enclosure defined - [x] Internal corners are rounded and can be milled - [x] Electrical - [x] All traces are routed - [x] Analog and digital commons joined at only one point - [x] ERC passes - [x] Isolation barriers are large enough - [x] Signal integrity - [x] Gaps in ground planes checked and minimized - [x] High-speed signals avoid gaps in ground planes - [x] Stubs minimized for high-speed signals - [x] Differential pair spacing based upon impedance matching - [x] Transmission lines terminated with an appropriate impedance - [x] Crystal connections kept short - [x] Guard ring around crystals - [x] Traces avoided under sensitive components - [x] Traces avoided under noisy components - [x] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda) - [x] Option for a shielding can over sensitive circuitry e.g. RF? - [x] Copper pour - [x] All planes have been poured - [x] Planes and pours checked for high-impedance paths - [x] No pour between adjacent pins on ICs - [x] Traces - [x] Trace-pad connections sufficiently obtuse (angle 90 deg or more) - [x] Trace widths sufficient for the current draw and max heating - [x] No connections between adjacent pins on ICs - [x] Vias for internal power traces sufficiently large - [x] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces - [x] Thermal - [x] Temperature sensitive components placed away from hot components - [x] Thermal vias in thermal pads - [x] Testing - [x] Test points on PCBs for critical circuits, hard to reach nets - [x] Ground connection points close to analog test points - [x] Silk screen - [x] Notes and documentation - [x] Updated revision number - [x] Updated date - [x] Blank space designated for a serial / assembly number - [x] No silk screen over pads / vias - [x] Text is readable from at most two directions - [x] Silk screen size / font will legible after printing - [x] Connector pin-outs labeled - [x] Fuse size and type marked on PCB - [x] Functional groups marked - [x] Functionality labeled - [x] Test points - [x] LEDs - [x] Buttons - [x] Connectors/terminals - [x] Jumpers/fuses

daniel-allspice added the

priority/5 - critical

labels 2024-01-02 02:58:40 +00:00

allspice-admin-daniel added 2 commits 2024-01-02 03:01:32 +00:00

Add input ESD protection, fix USB data 2f2ec90f14

Merge branch 'develop' of https://hub.allspice.io/AllSpice/Archimajor-Demo-WIP into develop c7343af20d

daniel-allspice requested review from RevaReviewa 2024-01-02 03:05:44 +00:00

daniel-allspice requested review from PavelInPurchasing 2024-01-02 03:05:44 +00:00

daniel-allspice requested review from MikaChanical 2024-01-02 03:05:53 +00:00

RevaReviewa reviewed 2024-01-02 03:08:51 +00:00

EndStops.SchDoc

RevaReviewa commented

2024-01-02 03:08:51 +00:00

First-time contributor

@daniel, have you simulated these values or prototyped them?

!thumbnail[](EndStops.SchDoc){ diff="AllSpice/Archimajor-Demo-WIP:e7f977b503c10880a45159a4b70a55bb8e5251bc...c7343af20dbcd167653d125d9f3866dbd7220aaa" pr="6" diff-visibility="full" variant="default" view-coords="6.1,5.2,47.6,24.0" aspect-ratio="1.286" } @daniel, have you simulated these values or prototyped them?

daniel-allspice commented

2024-01-02 03:10:04 +00:00

Author

Collaborator

@RevaReviewa, I have simulated. I've included the data in our simulations folder.

The prototype circuit catches 100% of the endstop signals. Much better than 80%

@RevaReviewa, I have simulated. I've included the data in our simulations folder. The prototype circuit catches 100% of the endstop signals. Much better than 80%

RevaReviewa reviewed 2024-01-02 03:11:51 +00:00

Microcontroller.SchDoc

RevaReviewa commented

2024-01-02 03:11:51 +00:00

First-time contributor

@daniel , can you add inline resistors to these signals? The external cables could be of any length or quality.

!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice/Archimajor-Demo-WIP:7dc6e2faf89ca88afc56f6180a62534f62cd4c20...e7f977b503c10880a45159a4b70a55bb8e5251bc" pr="1" is-added=true diff-visibility="full" variant="default" view-coords="72.9,55.5,98.4,68.1" aspect-ratio="1.533" } @daniel , can you add inline resistors to these signals? The external cables could be of any length or quality.

daniel-allspice reviewed 2024-01-02 03:15:24 +00:00

Microcontroller.SchDoc

daniel-allspice commented

2024-01-02 03:15:24 +00:00

Author

Collaborator

@RevaReviewa , how do these inline resistors look?

!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice/Archimajor-Demo-WIP:e7f977b503c10880a45159a4b70a55bb8e5251bc...c7343af20dbcd167653d125d9f3866dbd7220aaa" pr="6" diff-visibility="full" variant="default" view-coords="72.1,54.6,98.0,69.7" aspect-ratio="1.533" } @RevaReviewa , how do these inline resistors look?

RevaReviewa commented

2024-01-02 03:16:07 +00:00

First-time contributor

Those are perfect, thank you!

daniel-allspice commented

2024-01-02 03:17:19 +00:00

Author

Collaborator

@PavelInPurchasing, can you check to see if any of these components change our COGs by more than 2%?

MikaChanical reviewed 2024-01-02 03:19:52 +00:00

Archimajor.PcbDoc

MikaChanical commented

2024-01-02 03:19:52 +00:00

First-time contributor

@daniel, can you use a different inductor than L1? It's interfering with the enclosure. Cuts it off by 2 mm.

!thumbnail[](Archimajor.PcbDoc){ diff="AllSpice/Archimajor-Demo-WIP:e7f977b503c10880a45159a4b70a55bb8e5251bc...c7343af20dbcd167653d125d9f3866dbd7220aaa" pr="6" layers="82,81,74,72,71,69,68,65,64,63,62,60,59,58,57,33,35,37,1,41,40,2,39,32,38,34" diff-visibility="full" variant="default" view-coords="66.2,3.6,84.9,22.0" aspect-ratio="1.347" } @daniel, can you use a different inductor than L1? It's interfering with the enclosure. Cuts it off by 2 mm.

daniel-allspice commented

2024-01-02 03:20:58 +00:00

Author

Collaborator

@MikaChanical, We can, but we would have to do another round of EVT. Are these low-volume enclosures or high-volume?

MikaChanical commented

2024-01-02 03:22:02 +00:00

First-time contributor

We're still using low volume production. I can update the enclosure and make sure these changes get into the injection mold design. Let me know if there's ever another window for EVT so we can shrink the enclosure in the long run.

MikaChanical approved these changes 2024-01-02 03:22:41 +00:00

MikaChanical left a comment

First-time contributor

Thank you for the changes. They look great!

RevaReviewa approved these changes 2024-01-02 03:23:29 +00:00

RevaReviewa left a comment

First-time contributor

The protection circuitry looks good. Let's prototype! 😸

PavelInPurchasing approved these changes 2024-01-02 03:25:02 +00:00

PavelInPurchasing left a comment

First-time contributor

@daniel, I checked the cost difference. We actually saved money on this build. Keep up the good work.

daniel-allspice merged commit d76eaf7269 into main

2024-01-02 03:25:17 +00:00

daniel-allspice referenced this issue from a commit

2024-01-02 03:25:19 +00:00

Merge pull request 'V2: Add input protection and improve data integrity' (#6) from develop into main

PavelInPurchasing reviewed 2024-01-02 04:44:33 +00:00

daniel-allspice added this to the V2 milestone 2024-01-02 04:58:35 +00:00

AllSpiceAlice reviewed 2024-01-23 21:42:30 +00:00

EndStops.SchDoc

AllSpiceAlice commented

2024-01-23 21:42:30 +00:00

Owner

@daniel please look at this

!thumbnail[](EndStops.SchDoc){ diff="AllSpice-demos/Altium-archimajor-3d-printer-driver-demo:e7f977b503c10880a45159a4b70a55bb8e5251bc...c7343af20dbcd167653d125d9f3866dbd7220aaa" pr="6" diff-visibility="full" variant="default" view-coords="6.3,5.0,48.8,25.1" aspect-ratio="1.286" } @daniel please look at this

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MikaChanical

RevaReviewa

PavelInPurchasing

6 Participants

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Reference: AllSpiceAlice/Altium-Demo-2024-Q2#6

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