mirror of
https://github.com/EEVengers/ThunderScope.git
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Merge pull request #244 from offbyfour/master
Adding the KiCad Design for the FPGA Module Board
This commit is contained in:
commit
2528351757
Hardware
Altium
DSO.PcbLibDSO.SchLib
FPGA_Module
.gitignoreConnectors.SchDocCopy of FPGA_Module.PcbDocDDR3L.SchDocFPGA_Bank_IO.SchDocFPGA_Banks_DDR3.SchDocFPGA_CFG.SchDocFPGA_MGT.SchDocFPGA_Module.PcbDocFPGA_Module.PrjPcbFPGA_Module.PrjPcbStructureFPGA_Module.pdfFPGA_Module.stepFPGA_PWR.SchDocJob1.OutJobPWR.SchDoc
Project Outputs for FPGA_Module
Design Rule Check - FPGA_Module.drcDesign Rule Check - FPGA_Module.htmlFPGA_Module.G1FPGA_Module.G2FPGA_Module.G3FPGA_Module.G4FPGA_Module.GBLFPGA_Module.GBOFPGA_Module.GBPFPGA_Module.GBSFPGA_Module.GKOFPGA_Module.GTLFPGA_Module.GTOFPGA_Module.GTPFPGA_Module.GTSFPGA_Module.XLNFPGA_Module.zip
Gerber
FPGA_Module-macro.APR_LIBFPGA_Module.EXTREPFPGA_Module.G1FPGA_Module.G2FPGA_Module.G3FPGA_Module.G4FPGA_Module.GBLFPGA_Module.GBOFPGA_Module.GBPFPGA_Module.GBSFPGA_Module.GM1FPGA_Module.GTLFPGA_Module.GTOFPGA_Module.GTPFPGA_Module.GTSFPGA_Module.REPFPGA_Module.RULFPGA_Module.apr
NC Drill
Status Report.TxtFPGA_Module_Rev2
.gitignoreConnectors.SchDocDDR3L.SchDocFPGA_Bank_IO.SchDocFPGA_Banks_DDR3.SchDocFPGA_CFG.SchDocFPGA_MGT.SchDocFPGA_Module.PcbDocFPGA_Module.PrjPcbFPGA_Module.PrjPcbStructureFPGA_Module.layersetFPGA_Module.pdfFPGA_Module.stackupFPGA_Module_Panel.PcbDocFPGA_PWR.SchDocJob1.OutJobPWR.SchDoc
README.mdProject Outputs for FPGA_Module
Assembly Drawing.PDF
BOM
Design Rule Check - FPGA_Module.drcDesign Rule Check - FPGA_Module.htmlFab Release
FPGA_Module_Panel.G1FPGA_Module_Panel.G2FPGA_Module_Panel.G3FPGA_Module_Panel.G4FPGA_Module_Panel.GBLFPGA_Module_Panel.GTLFPGA_Module_Panel.XLNFPGA_Module_Panel_10112022.zipFPGA_Module_Panel_Board Outline.gbrFPGA_Module_Panel_Drill_Drawing.gbrFPGA_Module_Panel_Drillguide.gbrFPGA_Module_Panel_Fab_Notes.gbrFPGA_Module_Panel_Legend_Bot.gbrFPGA_Module_Panel_Legend_Top.gbrFPGA_Module_Panel_Paste_Bot.gbrFPGA_Module_Panel_Paste_Top.gbrFPGA_Module_Panel_Soldermask_Bot.gbrFPGA_Module_Panel_Soldermask_Top.gbr
Gerber
FPGA_Module_Panel-macro.APR_LIBFPGA_Module_Panel.EXTREPFPGA_Module_Panel.G1FPGA_Module_Panel.G2FPGA_Module_Panel.G3FPGA_Module_Panel.G4FPGA_Module_Panel.GBLFPGA_Module_Panel.GTLFPGA_Module_Panel.REPFPGA_Module_Panel.RULFPGA_Module_Panel.aprFPGA_Module_Panel_Board Outline.gbrFPGA_Module_Panel_Drill_Drawing.gbrFPGA_Module_Panel_Drillguide.gbrFPGA_Module_Panel_Fab_Notes.gbrFPGA_Module_Panel_Legend_Bot.gbrFPGA_Module_Panel_Legend_Top.gbrFPGA_Module_Panel_Paste_Bot.gbrFPGA_Module_Panel_Paste_Top.gbrFPGA_Module_Panel_Soldermask_Bot.gbrFPGA_Module_Panel_Soldermask_Top.gbrTranscode Report.txt
NC Drill
Pick Place
Status Report.TxtThunderscope_E
ADC.SchDocBuffer.SchDocFE.SchDocFE_Channel.SchDocFPGA.HarnessFPGA.SchDocFPGA.pdfInput.SchDocJob1.OutJobLEDs.SchDocMain.SchDocPvLib1.PvLib
Managed/Sheets/FC1D1A13-1D8D-4C53-8666-9A4B6D32A5EC
OSHPark-4-layer-rules.RULOSHPark-4-layer-stackup.stackupPGA.SchDocPLL.SchDocProject Logs for Thunderscope-E
ADC SCH ECO 2021-01-12 1-50-26 PM.LOGADC SCH ECO 2021-01-12 1-52-21 PM.LOGADC SCH ECO 2021-01-12 2-20-35 PM.LOGADC SCH ECO 2021-01-14 1-49-38 PM.LOGADC SCH ECO 2021-01-14 1-49-59 PM.LOGADC SCH ECO 2021-01-14 4-15-55 PM.LOGADC SCH ECO 2021-01-14 4-16-46 PM.LOGADC SCH ECO 2021-01-24 12-27-09 PM.LOGBuffer SCH ECO 2021-01-03 3-51-16 PM.LOGBuffer SCH ECO 2021-01-12 1-50-26 PM.LOGBuffer SCH ECO 2021-01-12 1-52-21 PM.LOGBuffer SCH ECO 2021-01-12 2-20-35 PM.LOGBuffer SCH ECO 2021-01-14 1-49-38 PM.LOGBuffer SCH ECO 2021-01-14 1-49-59 PM.LOGBuffer SCH ECO 2021-01-14 4-15-55 PM.LOGBuffer SCH ECO 2021-01-14 4-16-46 PM.LOGBuffer SCH ECO 2021-01-24 12-27-09 PM.LOGCON_PCI_Express_X4_64PIN SCH ECO 2021-01-03 3-51-16 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-12 1-50-26 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-12 1-52-21 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-12 2-20-35 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-14 1-49-38 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-14 1-49-59 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-14 4-15-55 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-14 4-16-46 PM.LOGCON_PCIe_X4 SCH ECO 2021-01-24 12-27-09 PM.LOGFE SCH ECO 2021-01-12 1-50-26 PM.LOGFE SCH ECO 2021-01-12 1-52-21 PM.LOGFE SCH ECO 2021-01-12 2-20-35 PM.LOGFE SCH ECO 2021-01-14 1-49-38 PM.LOGFE SCH ECO 2021-01-14 1-49-59 PM.LOGFE SCH ECO 2021-01-14 4-15-55 PM.LOGFE SCH ECO 2021-01-14 4-16-46 PM.LOGFE SCH ECO 2021-01-18 10-09-14 AM.LOGFE SCH ECO 2021-01-24 12-27-09 PM.LOGFE_Channel SCH ECO 2021-01-12 1-50-26 PM.LOGFE_Channel SCH ECO 2021-01-12 1-52-21 PM.LOGFE_Channel SCH ECO 2021-01-12 2-20-35 PM.LOGFE_Channel SCH ECO 2021-01-14 1-49-38 PM.LOGFE_Channel SCH ECO 2021-01-14 1-49-59 PM.LOGFE_Channel SCH ECO 2021-01-14 4-15-55 PM.LOGFE_Channel SCH ECO 2021-01-14 4-16-46 PM.LOGFE_Channel SCH ECO 2021-01-24 12-27-09 PM.LOGFPGA SCH ECO 2021-01-12 1-50-26 PM.LOGFPGA SCH ECO 2021-01-12 1-52-21 PM.LOGFPGA SCH ECO 2021-01-12 2-20-35 PM.LOGFPGA SCH ECO 2021-01-14 1-49-38 PM.LOGFPGA SCH ECO 2021-01-14 1-49-59 PM.LOGFPGA SCH ECO 2021-01-14 4-15-55 PM.LOGFPGA SCH ECO 2021-01-14 4-16-46 PM.LOGFPGA SCH ECO 2021-01-24 12-27-09 PM.LOGInput SCH ECO 2021-01-03 3-51-16 PM.LOGInput SCH ECO 2021-01-12 1-50-26 PM.LOGInput SCH ECO 2021-01-12 1-52-21 PM.LOGInput SCH ECO 2021-01-12 2-20-35 PM.LOGInput SCH ECO 2021-01-14 1-49-38 PM.LOGInput SCH ECO 2021-01-14 1-49-59 PM.LOGInput SCH ECO 2021-01-14 4-15-55 PM.LOGInput SCH ECO 2021-01-14 4-16-46 PM.LOGInput SCH ECO 2021-01-24 12-13-46 PM.LOGInput SCH ECO 2021-01-24 12-27-09 PM.LOGLEDs SCH ECO 2021-01-23 6-17-16 PM.LOGLEDs SCH ECO 2021-01-24 12-27-09 PM.LOGMain SCH ECO 2021-01-12 1-50-26 PM.LOGMain SCH ECO 2021-01-12 1-52-21 PM.LOGMain SCH ECO 2021-01-12 2-20-35 PM.LOGMain SCH ECO 2021-01-14 1-49-38 PM.LOGMain SCH ECO 2021-01-14 1-49-59 PM.LOGMain SCH ECO 2021-01-14 4-15-55 PM.LOGMain SCH ECO 2021-01-14 4-16-46 PM.LOGMain SCH ECO 2021-01-17 1-47-29 PM.LOGMain SCH ECO 2021-01-17 7-31-27 PM.LOGMain SCH ECO 2021-01-20 2-52-17 PM.LOGMain SCH ECO 2021-01-24 12-13-13 PM.LOGMain SCH ECO 2021-01-24 12-27-09 PM.LOGPGA SCH ECO 2021-01-03 3-51-16 PM.LOGPGA SCH ECO 2021-01-12 1-50-26 PM.LOGPGA SCH ECO 2021-01-12 1-52-21 PM.LOGPGA SCH ECO 2021-01-12 2-20-35 PM.LOGPGA SCH ECO 2021-01-14 1-49-38 PM.LOGPGA SCH ECO 2021-01-14 1-49-59 PM.LOGPGA SCH ECO 2021-01-14 4-15-55 PM.LOGPGA SCH ECO 2021-01-14 4-16-46 PM.LOGPGA SCH ECO 2021-01-24 12-27-09 PM.LOGPLL SCH ECO 2021-01-03 3-51-16 PM.LOGPLL SCH ECO 2021-01-12 1-50-26 PM.LOGPLL SCH ECO 2021-01-12 1-52-21 PM.LOGPLL SCH ECO 2021-01-12 2-20-35 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-19-14 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-22-26 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-26-31 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-28-06 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-28-32 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-30-11 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-57-50 PM.LOGThunderscope-E PCB ECO 2021-01-14 4-59-24 PM.LOGThunderscope-E PCB ECO 2021-01-15 10-17-49 PM.LOGThunderscope-E PCB ECO 2021-01-15 10-18-46 PM.LOGThunderscope-E PCB ECO 2021-01-15 12-03-23 PM.LOGThunderscope-E PCB ECO 2021-01-15 12-28-02 PM.LOGThunderscope-E PCB ECO 2021-01-15 12-34-13 PM.LOGThunderscope-E PCB ECO 2021-01-15 4-44-02 PM.LOGThunderscope-E PCB ECO 2021-01-16 2-06-38 PM.LOGThunderscope-E PCB ECO 2021-01-16 2-37-34 PM.LOGThunderscope-E PCB ECO 2021-01-16 2-54-30 PM.LOGThunderscope-E PCB ECO 2021-01-16 4-48-28 PM.LOGThunderscope-E PCB ECO 2021-01-16 4-55-24 PM.LOGThunderscope-E PCB ECO 2021-01-16 6-12-35 PM.LOGThunderscope-E PCB ECO 2021-01-17 1-48-12 PM.LOGThunderscope-E PCB ECO 2021-01-17 4-26-20 PM.LOGThunderscope-E PCB ECO 2021-01-17 7-31-41 PM.LOGThunderscope-E PCB ECO 2021-01-17 7-32-31 PM.LOGThunderscope-E PCB ECO 2021-01-18 1-03-23 PM.LOGThunderscope-E PCB ECO 2021-01-18 1-18-02 PM.LOGThunderscope-E PCB ECO 2021-01-18 1-31-37 PM.LOGThunderscope-E PCB ECO 2021-01-18 1-47-57 PM.LOGThunderscope-E PCB ECO 2021-01-18 10-20-33 AM.LOGThunderscope-E PCB ECO 2021-01-18 11-03-42 AM.LOGThunderscope-E PCB ECO 2021-01-18 3-24-18 PM.LOGThunderscope-E PCB ECO 2021-01-19 12-08-35 PM.LOGThunderscope-E PCB ECO 2021-01-19 2-12-45 PM.LOGThunderscope-E PCB ECO 2021-01-19 2-20-02 PM.LOGThunderscope-E PCB ECO 2021-01-19 2-27-31 PM.LOGThunderscope-E PCB ECO 2021-01-19 9-56-50 AM.LOGThunderscope-E PCB ECO 2021-01-20 2-57-49 PM.LOGThunderscope-E PCB ECO 2021-01-20 3-20-39 PM.LOGThunderscope-E PCB ECO 2021-01-20 3-26-06 PM.LOGThunderscope-E PCB ECO 2021-01-20 3-31-46 PM.LOGThunderscope-E PCB ECO 2021-01-20 3-34-31 PM.LOGThunderscope-E PCB ECO 2021-01-20 7-30-51 PM.LOGThunderscope-E PCB ECO 2021-01-20 7-42-52 PM.LOGThunderscope-E PCB ECO 2021-01-20 7-45-46 PM.LOGThunderscope-E PCB ECO 2021-01-20 7-49-16 PM.LOGThunderscope-E PCB ECO 2021-01-22 11-14-27 AM.LOGThunderscope-E PCB ECO 2021-01-22 2-56-55 PM.LOGThunderscope-E PCB ECO 2021-01-22 3-00-47 PM.LOGThunderscope-E PCB ECO 2021-01-23 6-17-56 PM.LOGThunderscope-E PCB ECO 2021-01-23 6-28-21 PM.LOGThunderscope-E PCB ECO 2021-01-23 6-35-25 PM.LOG
Project Outputs for Thunderscope-E
BOM
Gerber
Thunderscope-E-macro.APR_LIBThunderscope-E.EXTREPThunderscope-E.G1Thunderscope-E.G2Thunderscope-E.GBLThunderscope-E.GBOThunderscope-E.GBPThunderscope-E.GBSThunderscope-E.GM1Thunderscope-E.GTLThunderscope-E.GTOThunderscope-E.GTPThunderscope-E.GTSThunderscope-E.REPThunderscope-E.apr
NC Drill
Thunderscope-E.G1Thunderscope-E.G2Thunderscope-E.GBLThunderscope-E.GBOThunderscope-E.GBSThunderscope-E.GM1Thunderscope-E.GTLThunderscope-E.GTOThunderscope-E.GTSThunderscope-E.TXTThunderscope-E.zipSchematics
ADC.jpgADC.pdfBuffer.jpgBuffer.pdfFE.jpgFE.pdfFE_Channel.jpgFE_Channel.pdfFPGA.jpgFPGA.pdfInput.jpgInput.pdfLEDs.jpgLEDs.pdfMain.jpgMain.pdfPGA.jpgPGA.pdf
Thunderscope-E.PCBDOCThunderscope-E.PrjPCBThunderscope-E.PrjPCBStructureThunderscope-E.pdf__Previews
Thunderscope_Rev2
ADC.SchDocBuffer.SchDocFE.SchDocFE_Channel.SchDocFPGA.HarnessFPGA.SchDocInput.SchDocJob1.OutJobM2_KEY_M.HarnessM2_KEY_M.SchDocMain.SchDoc
Managed/Sheets/FC1D1A13-1D8D-4C53-8666-9A4B6D32A5EC
PGA.SchDocPLL.SchDocProject Outputs for Thunderscope_Rev2
PvLib1.PvLibThunderscope_Rev2.PCBDOCThunderscope_Rev2.PrjPCBThunderscope_Rev2.PrjPCBStructureThunderscope_Rev2.pdf__Previews
Thunderscope_Rev3
ADC.SchDocFE.SchDocFE_Channel.SchDocFPGA.HarnessFPGA.SchDocJob1.OutJobM2_KEY_M.HarnessM2_KEY_M.SchDocMain.SchDoc
Managed/Sheets/FC1D1A13-1D8D-4C53-8666-9A4B6D32A5EC
PLL.SchDocProject Outputs for Thunderscope_Rev3
Design Rule Check - Thunderscope_Rev3.drcDesign Rule Check - Thunderscope_Rev3.html
PvLib1.PvLibThunderscope_Rev3.PCBDOCThunderscope_Rev3.PrjPCBThunderscope_Rev3.PrjPCBStructureThunderscope_Rev3.pdfGerber
Thunderscope_Rev3-macro.APR_LIBThunderscope_Rev3.EXTREPThunderscope_Rev3.G1Thunderscope_Rev3.G2Thunderscope_Rev3.G3Thunderscope_Rev3.G4Thunderscope_Rev3.GBLThunderscope_Rev3.GBOThunderscope_Rev3.GBPThunderscope_Rev3.GBSThunderscope_Rev3.GKOThunderscope_Rev3.GTLThunderscope_Rev3.GTOThunderscope_Rev3.GTPThunderscope_Rev3.GTSThunderscope_Rev3.REPThunderscope_Rev3.apr
NC Drill
Thunderscope_Rev3-RoundHoles.TXTThunderscope_Rev3-SlotHoles.TXTThunderscope_Rev3.DRRThunderscope_Rev3.LDP
Status Report.TxtThunderscope_Rev3.zipKiCad/FPGA_Module_Rev2
Board_PWR.kicad_schCustom_Power_Symbols.kicad_symDSO.PcbLibFPGA_Bank_34_IO.kicad_schFPGA_Banks_14_15_DDR3.kicad_schFPGA_CFG.kicad_schFPGA_MGT.kicad_schFPGA_PWR.kicad_schREADME.mdTS_FPGA_Module_Rev2.kicad_pcbTS_FPGA_Module_Rev2.kicad_prlTS_FPGA_Module_Rev2.kicad_proTS_FPGA_Module_Rev2.kicad_schTS_FPGA_Module_Rev2.kicad_sch-bakThunderscope-altium-import.kicad_symempty.kicad_wksfp-info-cachefp-lib-tablesym-lib-table
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