AllSpiceMirrors/ThunderScope
7
Fork 0
mirror of https://github.com/EEVengers/ThunderScope.git synced 2025-04-04 21:36:55 +00:00
Files Issues Releases Activity

overtemp shutdown and MCS decode

Browse Source
This commit is contained in:
Andrew E Wilson 2024-02-05 16:14:43 -07:00
parent c99683304b
commit 3fc00220a2
17 changed files with 188 additions and 280 deletions

1
.gitignore vendored
View File

@ -24,6 +24,7 @@ Software/xdma_driver_win_src_2018_2/*
# Vivado Projects
Firmware/XDMA/*_prj*/
/**/.Xil/
/**/__pycache__/
Firmware/XDMA/output/*.bin
Firmware/XDMA/output/*.bit
Firmware/XDMA/output/*.mcs

48
Firmware/XDMA/bd/top_bd.tcl
View File

@ -49,7 +49,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7a100tfgg484-2
create_project project_1 myproj -part xc7a200tfbg484-2
}
@ -139,6 +139,7 @@ xilinx.com:ip:axi_datamover:5.1\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:axi_fifo_mm_s:4.3\
xilinx.com:ip:axi_quad_spi:3.2\
xilinx.com:ip:xadc_wiz:3.3\
xilinx.com:ip:util_ds_buf:2.2\
xilinx.com:ip:axi_dwidth_converter:2.1\
xilinx.com:ip:xdma:4.1\
@ -185,9 +186,9 @@ proc write_mig_file_design_1_mig_7series_0_0 { str_mig_prj_filepath } {
puts $mig_prj_file { <dci_inputs>1</dci_inputs>}
puts $mig_prj_file { <Debug_En>OFF</Debug_En>}
puts $mig_prj_file { <DataDepth_En>1024</DataDepth_En>}
puts $mig_prj_file { <LowPower_En>OFF</LowPower_En>}
puts $mig_prj_file { <XADC_En>Enabled</XADC_En>}
puts $mig_prj_file { <TargetFPGA>xc7a100t-fgg484/-2</TargetFPGA>}
puts $mig_prj_file { <LowPower_En>ON</LowPower_En>}
puts $mig_prj_file { <XADC_En>Disabled</XADC_En>}
puts $mig_prj_file { <TargetFPGA>xc7a200t-fbg484/-2</TargetFPGA>}
puts $mig_prj_file { <Version>4.2</Version>}
puts $mig_prj_file { <SystemClock>No Buffer</SystemClock>}
puts $mig_prj_file { <ReferenceClock>Use System Clock</ReferenceClock>}
@ -213,8 +214,8 @@ proc write_mig_file_design_1_mig_7series_0_0 { str_mig_prj_filepath } {
puts $mig_prj_file { <DeepMemory>1</DeepMemory>}
puts $mig_prj_file { <DataMask>1</DataMask>}
puts $mig_prj_file { <ECC>Disabled</ECC>}
puts $mig_prj_file { <Ordering>Normal</Ordering>}
puts $mig_prj_file { <BankMachineCnt>8</BankMachineCnt>}
puts $mig_prj_file { <Ordering>Strict</Ordering>}
puts $mig_prj_file { <BankMachineCnt>3</BankMachineCnt>}
puts $mig_prj_file { <CustomPart>FALSE</CustomPart>}
puts $mig_prj_file { <NewPartName/>}
puts $mig_prj_file { <RowAddress>15</RowAddress>}
@ -504,6 +505,8 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI_0_0
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn_0
# Create pins
create_bd_pin -dir I -from 31 -to 0 gpio2_io_i
@ -511,6 +514,7 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
create_bd_pin -dir I -type rst axi_resetn
create_bd_pin -dir O -from 31 -to 0 gpio_io_o_0
create_bd_pin -dir O -from 0 -to 0 ss_o_0
create_bd_pin -dir O -from 11 -to 0 temp_out_0
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
@ -578,8 +582,6 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A00_ADDR_WIDTH {0} \
CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
@ -595,8 +597,6 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_READ_ISSUING {1} \
CONFIG.M03_WRITE_ISSUING {1} \
CONFIG.M04_A00_ADDR_WIDTH {0} \
CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
@ -825,7 +825,7 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_READ_ISSUING {1} \
CONFIG.M15_WRITE_ISSUING {1} \
CONFIG.NUM_MI {3} \
CONFIG.NUM_MI {4} \
CONFIG.S01_READ_ACCEPTANCE {1} \
CONFIG.S01_WRITE_ACCEPTANCE {1} \
CONFIG.S02_READ_ACCEPTANCE {1} \
@ -869,20 +869,31 @@ proc create_hier_cell_AXI_LITE_IO { parentCell nameHier } {
] $axi_quad_spi_0
# Create instance: xadc_wiz_0, and set properties
set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ]
set_property -dict [list \
CONFIG.ENABLE_TEMP_BUS {true} \
CONFIG.TEMPERATURE_ALARM_OT_TRIGGER {80} \
] $xadc_wiz_0
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins AXI_STR_TXD_0] [get_bd_intf_pins axi_fifo_mm_s_0/AXI_STR_TXD]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_quad_spi_0/SPI_0] [get_bd_intf_pins SPI_0_0]
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins xadc_wiz_0/Vp_Vn] [get_bd_intf_pins Vp_Vn_0]
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins S00_AXI] [get_bd_intf_pins axi_crossbar_0/S00_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_fifo_mm_s_0/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M01_AXI [get_bd_intf_pins axi_crossbar_0/M01_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M02_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins axi_crossbar_0/M02_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M03_AXI [get_bd_intf_pins axi_crossbar_0/M03_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
# Create port connections
connect_bd_net -net axi_aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_fifo_mm_s_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins axi_quad_spi_0/s_axi_aclk]
connect_bd_net -net axi_aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_fifo_mm_s_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins xadc_wiz_0/s_axi_aclk]
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins gpio_io_o_0]
connect_bd_net -net axi_quad_spi_0_ss_o [get_bd_pins axi_quad_spi_0/ss_o] [get_bd_pins ss_o_0]
connect_bd_net -net axi_resetn_1 [get_bd_pins axi_resetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_fifo_mm_s_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn]
connect_bd_net -net axi_resetn_1 [get_bd_pins axi_resetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_fifo_mm_s_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
connect_bd_net -net gpio2_io_i_1 [get_bd_pins gpio2_io_i] [get_bd_pins axi_gpio_0/gpio2_io_i]
connect_bd_net -net xadc_wiz_0_temp_out [get_bd_pins xadc_wiz_0/temp_out] [get_bd_pins temp_out_0]
# Restore current instance
current_bd_instance $oldCurInst
@ -1015,13 +1026,14 @@ proc create_hier_cell_Memory { parentCell nameHier } {
# Create pins
create_bd_pin -dir I -type clk ACLK
create_bd_pin -dir I -type rst S00_ARESETN
create_bd_pin -dir I -from 11 -to 0 device_temp_i
# Create instance: mig_7series_0, and set properties
set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0 ]
# Generate the PRJ File for MIG
set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ]
set str_mig_file_name mig_a.prj
set str_mig_file_name mig_b.prj
set str_mig_file_path ${str_mig_folder}/${str_mig_file_name}
write_mig_file_design_1_mig_7series_0_0 $str_mig_file_path
@ -1029,7 +1041,7 @@ proc create_hier_cell_Memory { parentCell nameHier } {
CONFIG.BOARD_MIG_PARAM {Custom} \
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.XML_INPUT_FILE {mig_a.prj} \
CONFIG.XML_INPUT_FILE {mig_b.prj} \
] $mig_7series_0
@ -1371,6 +1383,7 @@ proc create_hier_cell_Memory { parentCell nameHier } {
# Create port connections
connect_bd_net -net S00_ARESETN_1 [get_bd_pins S00_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_crossbar_0/aresetn]
connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mig_7series_0/sys_clk_i]
connect_bd_net -net device_temp_i_1 [get_bd_pins device_temp_i] [get_bd_pins mig_7series_0/device_temp_i]
connect_bd_net -net mig_7series_0_ui_clk [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins axi_clock_converter_0/m_axi_aclk]
connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins util_vector_logic_0/Op1]
connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins axi_clock_converter_0/m_axi_aresetn]
@ -1457,6 +1470,8 @@ proc create_root_design { parentCell } {
set SPI_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI_0_0 ]
set Vp_Vn_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn_0 ]
# Create ports
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
@ -1490,6 +1505,7 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net PCIe_M_AXI_LITE [get_bd_intf_pins PCIe/M_AXI_LITE] [get_bd_intf_pins AXI_LITE_IO/S00_AXI]
connect_bd_intf_net -intf_net S_AXIS_S2MM_0_1 [get_bd_intf_ports S_AXIS_S2MM] [get_bd_intf_pins Datamover/S_AXIS_S2MM]
connect_bd_intf_net -intf_net S_AXIS_S2MM_CMD_0_1 [get_bd_intf_ports S_AXIS_S2MM_CMD] [get_bd_intf_pins Datamover/S_AXIS_S2MM_CMD]
connect_bd_intf_net -intf_net Vp_Vn_0_1 [get_bd_intf_ports Vp_Vn_0] [get_bd_intf_pins AXI_LITE_IO/Vp_Vn_0]
connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins Memory/DDR3]
connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins PCIe/M_AXI] [get_bd_intf_pins Memory/S00_AXI]
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pcie_mgt] [get_bd_intf_pins PCIe/pcie_mgt]
@ -1497,6 +1513,7 @@ proc create_root_design { parentCell } {
# Create port connections
connect_bd_net -net AXI_LITE_IO_gpio_io_o_0 [get_bd_pins AXI_LITE_IO/gpio_io_o_0] [get_bd_ports gpio_io_o_0]
connect_bd_net -net AXI_LITE_IO_ss_o_0 [get_bd_pins AXI_LITE_IO/ss_o_0] [get_bd_ports ss_o_0]
connect_bd_net -net AXI_LITE_IO_temp_out_0 [get_bd_pins AXI_LITE_IO/temp_out_0] [get_bd_pins Memory/device_temp_i]
connect_bd_net -net Datamover_s2mm_err_0 [get_bd_pins Datamover/s2mm_err] [get_bd_ports s2mm_err]
connect_bd_net -net Datamover_s2mm_wr_xfer_cmplt_0 [get_bd_pins Datamover/s2mm_wr_xfer_cmplt] [get_bd_ports s2mm_wr_xfer_cmplt]
connect_bd_net -net PCIe_axi_aresetn [get_bd_pins PCIe/axi_aresetn] [get_bd_pins Memory/S00_ARESETN] [get_bd_ports axi_aresetn] [get_bd_pins AXI_LITE_IO/axi_resetn]
@ -1512,6 +1529,7 @@ proc create_root_design { parentCell } {
assign_bd_address -offset 0x40020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI_LITE] [get_bd_addr_segs AXI_LITE_IO/axi_fifo_mm_s_0/S_AXI/Mem0] -force
assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI_LITE] [get_bd_addr_segs AXI_LITE_IO/axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x40040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI_LITE] [get_bd_addr_segs AXI_LITE_IO/axi_quad_spi_0/AXI_LITE/Reg] -force
assign_bd_address -offset 0x40010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces PCIe/xdma_0/M_AXI_LITE] [get_bd_addr_segs AXI_LITE_IO/xadc_wiz_0/s_axi_lite/Reg] -force
# Restore current instance

4
Firmware/XDMA/hdl/100t_200t/dso_top.v
View File

@ -44,6 +44,8 @@ module dso_top
input adc_fclk_n,
input[7:0] adc_data_p,
input[7:0] adc_data_n,
input Vp_Vn_0_v_n,
input Vp_Vn_0_v_p,
inout qspi_d0,
inout qspi_d1,
inout qspi_d2,
@ -289,6 +291,8 @@ module dso_top
.s2mm_err(s2mm_err),
.s2mm_halt(s2mm_halt),
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
.Vp_Vn_0_v_n(Vp_Vn_0_v_n),
.Vp_Vn_0_v_p(Vp_Vn_0_v_p),
.SPI_0_0_io0_i(spi_rtl_0_io0_i),
.SPI_0_0_io0_o(spi_rtl_0_io0_o),
.SPI_0_0_io0_t(spi_rtl_0_io0_t),

4
Firmware/XDMA/hdl/35t_50t/dso_top.v
View File

@ -44,6 +44,8 @@ module dso_top
input adc_fclk_n,
input[7:0] adc_data_p,
input[7:0] adc_data_n,
input Vp_Vn_0_v_n,
input Vp_Vn_0_v_p,
inout qspi_d0,
inout qspi_d1,
inout qspi_d2,
@ -289,6 +291,8 @@ module dso_top
.s2mm_err(s2mm_err),
.s2mm_halt(s2mm_halt),
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
.Vp_Vn_0_v_n(Vp_Vn_0_v_n),
.Vp_Vn_0_v_p(Vp_Vn_0_v_p),
.SPI_0_0_io0_i(spi_rtl_0_io0_i),
.SPI_0_0_io0_o(spi_rtl_0_io0_o),
.SPI_0_0_io0_t(spi_rtl_0_io0_t),

36
Firmware/XDMA/utils/pcie_mem_util.py
View File

@ -3,26 +3,40 @@ import mmap
import numpy as np
class pcie_mem:
def __init__(self,offset,size=0x10000):
total_writes = 0
total_reads = 0
def __init__(self,offset,size=0x10000,sim=False):
self.offset = offset
self.size = size
self.size = size
mmap_file = os.open('/dev/mem', os.O_RDWR | os.O_SYNC)
mem = mmap.mmap(mmap_file, self.size,
mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE,
offset=self.offset)
os.close(mmap_file)
self.array = np.frombuffer(mem, np.uint32, self.size >> 2)
if (not sim):
print("hello")
mmap_file = os.open('/dev/mem', os.O_RDWR | os.O_SYNC)
mem = mmap.mmap(mmap_file, self.size,
mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE,
offset=self.offset)
os.close(mmap_file)
self.array = np.frombuffer(mem, np.uint32, self.size >> 2)
else:
self.array = np.zeros(self.size >> 2, dtype=np.uint32)
def wread(self,address):
pcie_mem.total_reads += 1
idx = address >> 2
#print(hex(self.offset+address))
return_val = int(self.array[idx])
return return_val
def wwrite(self,address,data):
pcie_mem.total_writes += 1
idx = address >> 2
#print(hex(self.offset+address))
self.array[idx] = np.uint32(data)
self.array[idx] = np.uint32(data)
def get_stats(self):
return (pcie_mem.total_writes,pcie_mem.total_reads)
def clear_stats(self):
pcie_mem.total_writes = 0
pcie_mem.total_reads = 0

149
Firmware/XDMA/utils/qspi.py
View File

@ -36,84 +36,120 @@ class QSPI:
CMD_WRITE_ENABLE = 0x06
def __init__ (self,device_offset,base_offset):
def __init__ (self,device_offset,base_offset,sim=False):
self.device_offset = device_offset
self.base_offset = base_offset
self.sim = sim
self.reset()
#Dummy read
self.read_id()
self.flash_id = self.read_id()
self.falsh_info = self.device_info_read()
print(hex(self.flash_id))
n2ps = self.falsh_info[0x20]
if (n2ps == 0x8):
self.page_size = 0x100
else:
self.page_size = 0x200
n2ss = self.falsh_info[0x21]
if (n2ss == 0x8):
self.sector_size = 64*1024
else:
self.sector_size = 256*1024
print(hex(self.sector_size))
print(hex(self.random_read(0x0)[0x23]))
print(self.is_busy())
# self.falsh_info = self.device_info_read() #TODO: Not Supported on Micron Flash?
# print(hex(self.flash_id))
self.page_size = 0x100
self.sector_size = 64*1024
# print(hex(self.sector_size))
# print(hex(self.random_read(0x0)[0x23]))
print("FLASH ID : 0x%02X, Sector Size : 0x%08X" % (self.flash_id,self.sector_size))
# print(self.is_busy())
self.status_clear()
#if (self.load_mcs("page.mcs",verify_only=True)):
# self.load_mcs("page.mcs")
print(hex(self.random_read(0x0)[0x23]))
# print(hex(self.random_read(0x0)[0x23])) #TODO: Add check for version?
#read_arry = self.random_read(0x0)
#for i in range(len(read_arry)):
# print(hex(i),hex(read_arry[i]))
if(self.sim):
self.pcie_stats()
def pcie_stats(self):
mem = pcie_mem(self.device_offset+self.base_offset,sim=self.sim)
print("PCIe Writes : %6d, Reads : %6d" % mem.get_stats())
mem.clear_stats()
def reset(self):
mem = pcie_mem(self.device_offset+self.base_offset)
mem = pcie_mem(self.device_offset+self.base_offset,sim=self.sim)
mem.wwrite(self.REG_RST,self.REG_RST_MASK)
mem.wwrite(self.REG_SSR,self.REG_SSR_CEF)
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
def issue_cmd(self,cmd,readback = 0):
#get pcie memory
mem = pcie_mem(self.device_offset+self.base_offset)
mem = pcie_mem(self.device_offset+self.base_offset,sim=self.sim)
#write cmd section
#enable CE
mem.wwrite(self.REG_SSR,self.REG_SSR_CEN)
#write cmd sequence until full or end of sequence, issue and start again
cmd_idx = 0
while(cmd_idx<len(cmd)):
while(cmd_idx<len(cmd) and (mem.wread(self.REG_SR)&self.REG_SR_TXF)!=self.REG_SR_TXF):
if (not self.sim):
while(cmd_idx<len(cmd)):
while(cmd_idx<len(cmd) and (mem.wread(self.REG_SR)&self.REG_SR_TXF)!=self.REG_SR_TXF):
mem.wwrite(self.REG_DTR,cmd[cmd_idx])
#print(hex(cmd[cmd_idx]))
cmd_idx += 1
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
while((mem.wread(self.REG_SR)&self.REG_SR_TXE)!=self.REG_SR_TXE):
pass
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#empty RX (all garabge data during cmd issue
while((mem.wread(self.REG_SR)&self.REG_SR_RXE)!=self.REG_SR_RXE):
mem.wread(self.REG_DRR)
#read
read_idx = 0
return_val = []
while(read_idx<readback):
while(read_idx<readback and (mem.wread(self.REG_SR)&self.REG_SR_TXF)!=self.REG_SR_TXF):
mem.wwrite(self.REG_DTR,0x0)
read_idx += 1
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
while((mem.wread(self.REG_SR)&self.REG_SR_TXE)!=self.REG_SR_TXE):
pass
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#read RX
while((mem.wread(self.REG_SR)&self.REG_SR_RXE)!=self.REG_SR_RXE):
return_val.append(mem.wread(self.REG_DRR))
#print(hex(return_val[-1]))
else:
while(cmd_idx<len(cmd)):
mem.wread(self.REG_SR)
mem.wwrite(self.REG_DTR,cmd[cmd_idx])
#print(hex(cmd[cmd_idx]))
cmd_idx += 1
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
while((mem.wread(self.REG_SR)&self.REG_SR_TXE)!=self.REG_SR_TXE):
pass
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#empty RX (all garabge data during cmd issue
while((mem.wread(self.REG_SR)&self.REG_SR_RXE)!=self.REG_SR_RXE):
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
mem.wread(self.REG_SR)
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#empty RX (all garabge data during cmd issue
mem.wread(self.REG_SR)
mem.wread(self.REG_DRR)
#read
read_idx = 0
return_val = []
while(read_idx<readback):
while(read_idx<readback and (mem.wread(self.REG_SR)&self.REG_SR_TXF)!=self.REG_SR_TXF):
#read
read_idx = 0
return_val = []
while(read_idx<readback):
mem.wread(self.REG_SR)
mem.wwrite(self.REG_DTR,0x0)
read_idx += 1
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
while((mem.wread(self.REG_SR)&self.REG_SR_TXE)!=self.REG_SR_TXE):
pass
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#read RX
while((mem.wread(self.REG_SR)&self.REG_SR_RXE)!=self.REG_SR_RXE):
#start
mem.wwrite(self.REG_CR,self.REG_CR_ON)
#go until empty
mem.wread(self.REG_SR)
#stop
mem.wwrite(self.REG_CR,self.REG_CR_OFF)
#read RX
mem.wread(self.REG_SR)
return_val.append(mem.wread(self.REG_DRR))
#print(hex(return_val[-1]))
#turn off CE
mem.wwrite(self.REG_SSR,self.REG_SSR_CEF)
@ -138,7 +174,7 @@ class QSPI:
return_val = self.issue_cmd(cmd,length)
return return_val
def is_busy(self):
def is_busy(self):
cmd = [self.CMD_STATUSREG_READ]
if ((self.issue_cmd(cmd,1)[0]&self.SR_IS_READY_MASK)==self.SR_IS_READY_MASK):
return True
@ -154,6 +190,7 @@ class QSPI:
self.issue_cmd(cmd)
def erase_sector(self,addr):
# print("Erase Sector at 0x%08X" % (addr))
self.status_clear()
self.write_en()
#make sure nothing is happening
@ -186,7 +223,7 @@ class QSPI:
pass
self.status_clear()
def write_sector(self,addr,data):
def write_sector(self,addr,data):
self.erase_sector(addr)
stride = self.page_size
#print(data[0:0x80])
@ -196,6 +233,8 @@ class QSPI:
def verify_sector (self,addr,data):
read_data = self.random_read(addr,self.sector_size)
if (self.sim):
return 0
for rbyte,dbyte in zip(read_data,data):
if(rbyte != dbyte):
print (addr,rbyte,dbyte)
@ -205,9 +244,8 @@ class QSPI:
return 0
def write_flash(self,addr,data,verify_only=False):
print("Addr : 0x%08X, Len : 0x%08X" % (addr,len(data)))
for i in range(0,len(data),self.sector_size):
print((i*100.0)/len(data))
print(hex(addr+i))
if(i<len(data)):
if(not verify_only):
self.write_sector(addr+i,data[0+i:self.sector_size+i])
@ -223,7 +261,8 @@ class QSPI:
# NEEDS MORE Features to support full MCS files
def load_mcs(self,path,verify_only=False):
key = ":([0-9A-F]{2})([0-9A-F]{4})([0-9A-F]{2})([0-9A-F]+)?([0-9A-F]{2})"
base_addr = 0
pass_var = 0
file_b = bytearray()
count = 0
with open(path, 'r') as file_t:
@ -236,9 +275,15 @@ class QSPI:
mcs_type = int(m.group(3),16)
if mcs_type == 1:
break
if mcs_type == 4:
if mcs_type == 4: #Update Base Address? assume sector change?
if (len(file_b)!=0):
pass_var += self.write_flash(base_addr,file_b,verify_only)
file_b = bytearray()
base_addr = int(m.group(4),16) << 16
continue
data_b = int.to_bytes(int(m.group(4),16),num_bytes,'big')
file_b.extend(data_b)
print(file_b[0:100])
return self.write_flash(0,file_b,verify_only)
pass_var += self.write_flash(base_addr,file_b,verify_only)
if(self.sim):
self.pcie_stats()
return pass_var

8
Firmware/XDMA/utils/sim_mcs.py Normal file
View File

@ -0,0 +1,8 @@
from qspi import *
print("Sim for QSPI interface via PCIe")
sim_qspi = QSPI(0x0,0x0,sim=True)
print("Sim for Full Flash")
sim_qspi.load_mcs("../output/xdma_prj_100t_full.mcs")
print("Sim for Update Only")
sim_qspi.load_mcs("../output/xdma_prj_100t_update.mcs")

8
Firmware/XDMA/xci/100t/mig_a.prj
View File

@ -15,9 +15,9 @@
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>OFF</LowPower_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7a100t-fgg484/-2</TargetFPGA>
@ -54,8 +54,8 @@
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>8</BankMachineCnt>
<Ordering>Strict</Ordering>
<BankMachineCnt>3</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName/>
<RowAddress>15</RowAddress>

2
Firmware/XDMA/xci/200t/mig_a.prj
View File

@ -17,7 +17,7 @@
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7a200t-fbg484/-2</TargetFPGA>

2
Firmware/XDMA/xci/35t/mig_a.prj
View File

@ -17,7 +17,7 @@
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7a35t-csg325/-2</TargetFPGA>

2
Firmware/XDMA/xci/50t/mig_a.prj
View File

@ -17,7 +17,7 @@
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7a50t-csg325/-2</TargetFPGA>

184
Firmware/XDMA/xci/50t/mig_b.prj
View File

@ -1,184 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project NoOfControllers="1">
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<ModuleName>design_1_mig_7series_0_1</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7a35t-csg325/-2</TargetFPGA>
<Version>4.2</Version>
<SystemClock>No Buffer</SystemClock>
<ReferenceClock>Use System Clock</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<FPGADevice>
<selected>7a/xc7a50t-csg325</selected>
<selected>7a/xc7a15t-csg325</selected>
<selected>7a/xc7a25t-csg325</selected>
<selected>7a/xc7a12t-csg325</selected>
</FPGADevice>
<Controller number="0">
<MemoryDevice>DDR3_SDRAM/Components/MT41K64M16XX-107</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>32</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Strict</Ordering>
<BankMachineCnt>3</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName/>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.35V</MemoryVoltage>
<C0_MEM_SIZE>268435456</C0_MEM_SIZE>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin IN_TERM="" IOSTANDARD="" PADName="V14" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="M17" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="T18" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="V17" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="T17" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="V12" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="V16" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="V13" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="V11" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="T13" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="T15" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="T14" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="R18" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="N17" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="T12" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="N18" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="K18" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="L18" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="M15" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B12" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B10" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D18" SLEW="" VCCAUX_IO="" name="ddr3_dm[2]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="G16" SLEW="" VCCAUX_IO="" name="ddr3_dm[3]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D14" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D8" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D11" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C8" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C11" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D9" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B11" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B17" SLEW="" VCCAUX_IO="" name="ddr3_dq[16]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D16" SLEW="" VCCAUX_IO="" name="ddr3_dq[17]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="E16" SLEW="" VCCAUX_IO="" name="ddr3_dq[18]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="E17" SLEW="" VCCAUX_IO="" name="ddr3_dq[19]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="A12" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C16" SLEW="" VCCAUX_IO="" name="ddr3_dq[20]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C18" SLEW="" VCCAUX_IO="" name="ddr3_dq[21]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D15" SLEW="" VCCAUX_IO="" name="ddr3_dq[22]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C17" SLEW="" VCCAUX_IO="" name="ddr3_dq[23]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="G17" SLEW="" VCCAUX_IO="" name="ddr3_dq[24]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="F17" SLEW="" VCCAUX_IO="" name="ddr3_dq[25]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="H17" SLEW="" VCCAUX_IO="" name="ddr3_dq[26]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="E18" SLEW="" VCCAUX_IO="" name="ddr3_dq[27]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="H16" SLEW="" VCCAUX_IO="" name="ddr3_dq[28]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="F14" SLEW="" VCCAUX_IO="" name="ddr3_dq[29]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="A15" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="H18" SLEW="" VCCAUX_IO="" name="ddr3_dq[30]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="G14" SLEW="" VCCAUX_IO="" name="ddr3_dq[31]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C13" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="A14" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="A13" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="D13" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B14" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="A10" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C9" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B15" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="A9" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="A17" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[2]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="F15" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[3]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="C14" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B9" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="B16" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[2]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="G15" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[3]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="K17" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="K15" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="U11" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
<Pin IN_TERM="" IOSTANDARD="" PADName="M16" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
</PinSelection>
<System_Control>
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
</System_Control>
<TimingParameters>
<Parameters tcke="5" tfaw="35" tras="34" trcd="13.91" trefi="7.8" trfc="110" trp="13.91" trrd="6" trtp="7.5" twtr="7.5"/>
</TimingParameters>
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
<mrCasLatency name="CAS Latency">6</mrCasLatency>
<mrMode name="Mode">Normal</mrMode>
<mrDllReset name="DLL Reset">No</mrDllReset>
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)">0</emrPosted>
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
<emrDQS name="TDQS enable">Enabled</emrDQS>
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG_STARVE_LIMIT</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>

4
Firmware/XDMA/xdc/35t_50t/module_bitgen.xdc
View File

@ -10,5 +10,5 @@ set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]

4
Firmware/XDMA/xdc/35t_50t/module_io.xdc
View File

@ -1,5 +1,5 @@
set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports {led}]
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports {sync}]
set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports led]
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports sync]
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports spi_sdio]
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports spi_sclk]

5
Firmware/XDMA/xdc/module_bitgen.xdc
View File

@ -10,8 +10,5 @@ set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]

5
Firmware/XDMA/xdc/module_io.xdc
View File

@ -1,5 +1,5 @@
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports {led}]
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports {sync}]
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports led]
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports sync]
set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS33} [get_ports spi_sdio]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports spi_sclk]
@ -135,3 +135,4 @@ set_property PACKAGE_PIN E10 [get_ports {pcie_clk_n[0]}]
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports pcie_perstn]

2
Firmware/XDMA/xdc/timing.xdc
View File

@ -1,4 +1,4 @@
create_clock -period 10.000 -name {pcie_clk_p[0]} -waveform {0.000 5.000} [get_ports {pcie_clk_p[0]}]
#create_clock -period 2.000 -name {adc_lclk_p} -waveform {0.000 1.000} [get_ports {adc_lclk_p}]
set_clock_groups -asynchronous -group [get_clocks {userclk2}] -group [get_clocks {clk_out2_clk_wiz_0}]