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Merge pull request #229 from EEVengers/FW/Aleksa/dso_top_unsigned
Organizing Firmware Folder
This commit is contained in:
Aleksa Bjelogrlic
GitHub
commit
406c9b5daf
Firmware/Artix7_PCIe
dso_top
dso_top.cache
ip/2020.1
2d3583ce78ad6539
31cd39614dc46ff1
34509a0b69fcb1af
8abae3f1fc384d9a
de240defa7bad4ca
wt
dso_top.hw
dso_top.ip_user_files/sim_scripts
clk_wiz_0
design_1
activehdl
modelsim
questa
riviera
vcs
xcelium
xsim
fifo_generator_0
activehdl
modelsim
questa
riviera
vcs
xcelium
xsim
dso_top.runs
.jobs
clk_wiz_0_synth_1
.Xil
.vivado.begin.rstISEWrap.jsISEWrap.shclk_wiz_0.dcpclk_wiz_0.tclclk_wiz_0.vdsclk_wiz_0_utilization_synth.pbclk_wiz_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pbdesign_1_axi_clock_converter_0_0_synth_1
.Xil
.vivado.begin.rstISEWrap.jsISEWrap.shdesign_1_axi_clock_converter_0_0.tcldesign_1_axi_clock_converter_0_0.vdsdesign_1_axi_clock_converter_0_0_utilization_synth.pbdesign_1_axi_clock_converter_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pbdesign_1_axi_crossbar_0_0_synth_1
.vivado.begin.rstISEWrap.jsISEWrap.shdesign_1_axi_crossbar_0_0.tcldesign_1_axi_crossbar_0_0.vdsdesign_1_axi_crossbar_0_0_utilization_synth.pbdesign_1_axi_crossbar_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pb
design_1_axi_crossbar_0_1_synth_1
.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_axi_crossbar_0_1.tcldesign_1_axi_crossbar_0_1.vdsdesign_1_axi_crossbar_0_1_utilization_synth.pbdesign_1_axi_crossbar_0_1_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pb
design_1_axi_datamover_0_0_synth_1
.Vivado_Synthesis.queue.rst
.Xil
.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_axi_datamover_0_0.tcldesign_1_axi_datamover_0_0.vdsdesign_1_axi_datamover_0_0_utilization_synth.pbdesign_1_axi_datamover_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pbdesign_1_axi_dwidth_converter_0_0_synth_1
.Vivado_Synthesis.queue.rst.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_axi_dwidth_converter_0_0.tcldesign_1_axi_dwidth_converter_0_0.vdsdesign_1_axi_dwidth_converter_0_0_utilization_synth.pbdesign_1_axi_dwidth_converter_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pb
design_1_axi_fifo_mm_s_0_0_synth_1
.Vivado_Synthesis.queue.rst
.Xil
.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_axi_fifo_mm_s_0_0.tcldesign_1_axi_fifo_mm_s_0_0.vdsdesign_1_axi_fifo_mm_s_0_0_utilization_synth.pbdesign_1_axi_fifo_mm_s_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pbdesign_1_axi_gpio_0_1_synth_1
.Vivado_Synthesis.queue.rst.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_axi_gpio_0_1.tcldesign_1_axi_gpio_0_1.vdsdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pb
design_1_clk_wiz_0_0_synth_1
.Vivado_Synthesis.queue.rst.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_clk_wiz_0_0.tcldesign_1_clk_wiz_0_0.vdsdesign_1_clk_wiz_0_0_utilization_synth.pbdesign_1_clk_wiz_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pb
design_1_mig_7series_0_0_synth_1
.Vivado_Synthesis.queue.rst
.Xil
.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_mig_7series_0_0.tcldesign_1_mig_7series_0_0.vdsdesign_1_mig_7series_0_0_utilization_synth.pbdesign_1_mig_7series_0_0_utilization_synth.rptgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pbdesign_1_util_ds_buf_0_0_synth_1
.Vivado_Synthesis.queue.rst.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_util_ds_buf_0_0.tcldesign_1_util_ds_buf_0_0.vdsdesign_1_util_ds_buf_0_0_utilization_synth.pbdesign_1_util_ds_buf_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pb
design_1_util_vector_logic_0_0_synth_1
.Vivado_Synthesis.queue.rst.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_util_vector_logic_0_0.tcldesign_1_util_vector_logic_0_0.vdsdesign_1_util_vector_logic_0_0_utilization_synth.pbdesign_1_util_vector_logic_0_0_utilization_synth.rptgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pb
design_1_xdma_0_0_synth_1
.Vivado_Synthesis.queue.rst
.Xil
.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__design_1_xdma_0_0.tcldesign_1_xdma_0_0.vdsdesign_1_xdma_0_0_utilization_synth.pbdesign_1_xdma_0_0_utilization_synth.rptdont_touch.xdcgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pbfifo_generator_0_synth_1
.Vivado_Synthesis.queue.rst
.Xil
.vivado.begin.rst.vivado.end.rstISEWrap.jsISEWrap.sh__synthesis_is_complete__dont_touch.xdcfifo_generator_0.tclfifo_generator_0.vdsfifo_generator_0_utilization_synth.pbfifo_generator_0_utilization_synth.rptgen_run.xmlhtr.txtjob.id.logrundef.jsrunme.batrunme.logrunme.shvivado.jouvivado.pbimpl_1
.Vivado_Implementation.queue.rst.init_design.begin.rst.init_design.end.rst.opt_design.begin.rst.opt_design.end.rst.place_design.begin.rst.place_design.end.rst.route_design.begin.rst.route_design.end.rst.vivado.begin.rst.vivado.end.rst.write_bitstream.begin.rst.write_bitstream.end.rstISEWrap.jsISEWrap.shdso_top.bitdso_top.hwdefdso_top.tcldso_top.vdidso_top_bus_skew_routed.pbdso_top_bus_skew_routed.rptdso_top_bus_skew_routed.rpxdso_top_clock_utilization_routed.rptdso_top_control_sets_placed.rptdso_top_drc_opted.pbdso_top_drc_opted.rptdso_top_drc_opted.rpxdso_top_drc_routed.pbdso_top_drc_routed.rptdso_top_drc_routed.rpxdso_top_io_placed.rptdso_top_methodology_drc_routed.pbdso_top_methodology_drc_routed.rptdso_top_methodology_drc_routed.rpxdso_top_power_routed.rptdso_top_power_routed.rpxdso_top_power_summary_routed.pbdso_top_route_status.pbdso_top_route_status.rptdso_top_routed.dcpdso_top_timing_summary_routed.pbdso_top_timing_summary_routed.rptdso_top_timing_summary_routed.rpxdso_top_utilization_placed.pbdso_top_utilization_placed.rptgen_run.xmlhtr.txtinit_design.pbjob.id.logopt_design.pbplace_design.pbproject.wdfroute_design.pbrundef.jsrunme.batrunme.logrunme.shusage_statistics_webtalk.htmlusage_statistics_webtalk.xmlvivado.jouvivado.pbwrite_bitstream.pb
synth_1
dso_top.srcs/sources_1
bd/design_1/ip
design_1_axi_clock_converter_0_0
design_1_axi_crossbar_0_0
design_1_axi_crossbar_0_1
design_1_axi_datamover_0_0
design_1_axi_dwidth_converter_0_0
design_1_axi_fifo_mm_s_0_0
design_1_axi_gpio_0_1
design_1_clk_wiz_0_0
design_1_mig_7series_0_0
design_1_util_ds_buf_0_0
design_1_util_vector_logic_0_0
ip/fifo_generator_0
dso_top_TE0712
dso_top.bindso_top.xpr
dso_top.ip_user_files
README.txt
bd/design_1
ip
design_1_auto_cc_0/sim
design_1_auto_us_df_0/sim
design_1_auto_us_df_1/sim
design_1_axi_datamover_0_0/sim
design_1_axi_fifo_mm_s_0_0/sim
design_1_axi_gpio_0_1/sim
design_1_axi_gpio_1_0/sim
design_1_clk_wiz_0_0
design_1_m00_data_fifo_0/sim
design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/rtl
axi
mig_7series_v4_2_axi_ctrl_addr_decode.vmig_7series_v4_2_axi_ctrl_read.vmig_7series_v4_2_axi_ctrl_reg.vmig_7series_v4_2_axi_ctrl_reg_bank.vmig_7series_v4_2_axi_ctrl_top.vmig_7series_v4_2_axi_ctrl_write.vmig_7series_v4_2_axi_mc.vmig_7series_v4_2_axi_mc_ar_channel.vmig_7series_v4_2_axi_mc_aw_channel.vmig_7series_v4_2_axi_mc_b_channel.vmig_7series_v4_2_axi_mc_cmd_arbiter.vmig_7series_v4_2_axi_mc_cmd_fsm.vmig_7series_v4_2_axi_mc_cmd_translator.vmig_7series_v4_2_axi_mc_fifo.vmig_7series_v4_2_axi_mc_incr_cmd.vmig_7series_v4_2_axi_mc_r_channel.vmig_7series_v4_2_axi_mc_simple_fifo.vmig_7series_v4_2_axi_mc_w_channel.vmig_7series_v4_2_axi_mc_wr_cmd_fsm.vmig_7series_v4_2_axi_mc_wrap_cmd.vmig_7series_v4_2_ddr_a_upsizer.vmig_7series_v4_2_ddr_axi_register_slice.vmig_7series_v4_2_ddr_axi_upsizer.vmig_7series_v4_2_ddr_axic_register_slice.vmig_7series_v4_2_ddr_carry_and.vmig_7series_v4_2_ddr_carry_latch_and.vmig_7series_v4_2_ddr_carry_latch_or.vmig_7series_v4_2_ddr_carry_or.vmig_7series_v4_2_ddr_command_fifo.vmig_7series_v4_2_ddr_comparator.vmig_7series_v4_2_ddr_comparator_sel.vmig_7series_v4_2_ddr_comparator_sel_static.vmig_7series_v4_2_ddr_r_upsizer.vmig_7series_v4_2_ddr_w_upsizer.v
clocking
mig_7series_v4_2_clk_ibuf.vmig_7series_v4_2_infrastructure.vmig_7series_v4_2_iodelay_ctrl.vmig_7series_v4_2_tempmon.v
controller
mig_7series_v4_2_arb_mux.vmig_7series_v4_2_arb_row_col.vmig_7series_v4_2_arb_select.vmig_7series_v4_2_bank_cntrl.vmig_7series_v4_2_bank_common.vmig_7series_v4_2_bank_compare.vmig_7series_v4_2_bank_mach.vmig_7series_v4_2_bank_queue.vmig_7series_v4_2_bank_state.vmig_7series_v4_2_col_mach.vmig_7series_v4_2_mc.vmig_7series_v4_2_rank_cntrl.vmig_7series_v4_2_rank_common.vmig_7series_v4_2_rank_mach.vmig_7series_v4_2_round_robin_arb.v
design_1_mig_7series_0_0.vdesign_1_mig_7series_0_0_mig_sim.vecc
mig_7series_v4_2_ecc_buf.vmig_7series_v4_2_ecc_dec_fix.vmig_7series_v4_2_ecc_gen.vmig_7series_v4_2_ecc_merge_enc.vmig_7series_v4_2_fi_xor.v
ip_top
phy
mig_7series_v4_2_ddr_byte_group_io.vmig_7series_v4_2_ddr_byte_lane.vmig_7series_v4_2_ddr_calib_top.vmig_7series_v4_2_ddr_if_post_fifo.vmig_7series_v4_2_ddr_mc_phy.vmig_7series_v4_2_ddr_mc_phy_wrapper.vmig_7series_v4_2_ddr_of_pre_fifo.vmig_7series_v4_2_ddr_phy_4lanes.vmig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.vmig_7series_v4_2_ddr_phy_dqs_found_cal.vmig_7series_v4_2_ddr_phy_dqs_found_cal_hr.vmig_7series_v4_2_ddr_phy_init.vmig_7series_v4_2_ddr_phy_ocd_cntlr.vmig_7series_v4_2_ddr_phy_ocd_data.vmig_7series_v4_2_ddr_phy_ocd_edge.vmig_7series_v4_2_ddr_phy_ocd_lim.vmig_7series_v4_2_ddr_phy_ocd_mux.vmig_7series_v4_2_ddr_phy_ocd_po_cntlr.vmig_7series_v4_2_ddr_phy_ocd_samp.vmig_7series_v4_2_ddr_phy_oclkdelay_cal.vmig_7series_v4_2_ddr_phy_prbs_rdlvl.vmig_7series_v4_2_ddr_phy_rdlvl.vmig_7series_v4_2_ddr_phy_tempmon.vmig_7series_v4_2_ddr_phy_top.vmig_7series_v4_2_ddr_phy_wrcal.vmig_7series_v4_2_ddr_phy_wrlvl.vmig_7series_v4_2_ddr_phy_wrlvl_off_delay.vmig_7series_v4_2_ddr_prbs_gen.vmig_7series_v4_2_ddr_skip_calib_tap.vmig_7series_v4_2_poc_cc.vmig_7series_v4_2_poc_edge_store.vmig_7series_v4_2_poc_meta.vmig_7series_v4_2_poc_pd.vmig_7series_v4_2_poc_tap_base.vmig_7series_v4_2_poc_top.v
ui
design_1_smartconnect_0_0
bd_0
bd_48ac.bd
sc_xtlm_design_1_smartconnect_0_0.memip
ip_0/sim
ip_1/sim
ip_10/sim
ip_11/sim
ip_12/sim
ip_13/sim
ip_14/sim
ip_15/sim
ip_16/sim
ip_17/sim
ip_18/sim
ip_19/sim
ip_2/sim
ip_20/sim
ip_21/sim
ip_22/sim
ip_23/sim
ip_24/sim
ip_25/sim
ip_26/sim
ip_27/sim
ip_28/sim
ip_29/sim
ip_3/sim
ip_30/sim
ip_31/sim
ip_32/sim
ip_33/sim
ip_34/sim
ip_35/sim
ip_36/sim
ip_37/sim
ip_38/sim
ip_39/sim
ip_4/sim
ip_40/sim
ip_41/sim
ip_42/sim
ip_43/sim
ip_44/sim
ip_45/sim
ip_46/sim
ip_5/sim
ip_6/sim
ip_7/sim
ip_8/sim
ip_9/sim
sim
sim
design_1_util_ds_buf_0_0
design_1_util_vector_logic_0_0/sim
design_1_xbar_0/sim
design_1_xdma_0_0
ip_0
sim
source
design_1_xdma_0_0_pcie2_ip_axi_basic_rx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_top.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.vdesign_1_xdma_0_0_pcie2_ip_core_top.vdesign_1_xdma_0_0_pcie2_ip_gt_common.vdesign_1_xdma_0_0_pcie2_ip_gt_rx_valid_filter_7x.vdesign_1_xdma_0_0_pcie2_ip_gt_top.vdesign_1_xdma_0_0_pcie2_ip_gt_wrapper.vdesign_1_xdma_0_0_pcie2_ip_gtp_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_gtx_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_pcie2_top.vdesign_1_xdma_0_0_pcie2_ip_pcie_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_top_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_brams_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_lane.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_misc.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_pipeline.vdesign_1_xdma_0_0_pcie2_ip_pcie_top.vdesign_1_xdma_0_0_pcie2_ip_pipe_clock.vdesign_1_xdma_0_0_pcie2_ip_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_pipe_eq.vdesign_1_xdma_0_0_pcie2_ip_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_pipe_sync.vdesign_1_xdma_0_0_pcie2_ip_pipe_user.vdesign_1_xdma_0_0_pcie2_ip_pipe_wrapper.vdesign_1_xdma_0_0_pcie2_ip_qpll_drp.vdesign_1_xdma_0_0_pcie2_ip_qpll_reset.vdesign_1_xdma_0_0_pcie2_ip_qpll_wrapper.vdesign_1_xdma_0_0_pcie2_ip_rxeq_scan.v
ip_1/sim
ip_2/sim
ip_3/sim
ip_4/sim
sim
xdma_v4_1/hdl/verilog
design_1_xdma_0_0_axi_stream_intf.svdesign_1_xdma_0_0_cfg_sideband.svdesign_1_xdma_0_0_core_top.svdesign_1_xdma_0_0_dma_bram_wrap.svdesign_1_xdma_0_0_dma_bram_wrap_1024.svdesign_1_xdma_0_0_dma_bram_wrap_2048.svdesign_1_xdma_0_0_dma_cpl.svdesign_1_xdma_0_0_dma_req.svdesign_1_xdma_0_0_pcie2_to_pcie3_wrapper.svdesign_1_xdma_0_0_rx_demux.svdesign_1_xdma_0_0_rx_destraddler.svdesign_1_xdma_0_0_tgt_cpl.svdesign_1_xdma_0_0_tgt_req.svdesign_1_xdma_0_0_tx_mux.sv
design_1_xlconstant_0_0/sim
design_1_xlconstant_0_2/sim
design_1_xlconstant_0_3/sim
sim
ip
clk_wiz_0
clk_wiz_0.vclk_wiz_0.veoclk_wiz_0_clk_wiz.vclk_wiz_0_sim_netlist.vclk_wiz_0_sim_netlist.vhdlclk_wiz_0_stub.vclk_wiz_0_stub.vhdl
fifo_generator_0
ipstatic
hdl
mmcm_pll_drp_func_7s_mmcm.vhmmcm_pll_drp_func_7s_pll.vhmmcm_pll_drp_func_us_mmcm.vhmmcm_pll_drp_func_us_pll.vhmmcm_pll_drp_func_us_plus_mmcm.vhmmcm_pll_drp_func_us_plus_pll.vhsimulation
mem_init_files
axi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xbar_1.hdesign_1_xbar_1_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hmig_a.prjmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
sim_scripts
clk_wiz_0
design_1
README.txt
activehdl
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
ies
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_b.prjrun.fsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
modelsim
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
questa
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.helaborate.dofile_info.txtglbl.vmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
riviera
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcompile.dodesign_1.shdesign_1.udodesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtwave.doxlconstant_v1_1_7.h
vcs
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsimulate.dosmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
xcelium
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hfile_info.txtglbl.vmig_b.prjrun.fsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
xsim
README.txtaxi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hcmd.tcldesign_1.shdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.helab.optfile_info.txtglbl.vmig_b.prj
protoinst_files
sc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtvhdl.prjvlog.prjxlconstant_v1_1_7.hxsim.inififo_generator_0
README.txt
activehdl
ies
modelsim
questa
README.txtcompile.doelaborate.dofifo_generator_0.shfifo_generator_0.udofile_info.txtglbl.vsimulate.dowave.do
riviera
vcs
xcelium
xsim
dso_top.srcs
constrs_1
sources_1
bd/design_1
design_1.bddesign_1.bxmldesign_1_ooc.xdc
hdl
hw_handoff
ip
design_1_axi_clock_converter_0_0
design_1_axi_clock_converter_0_0.dcpdesign_1_axi_clock_converter_0_0.xcidesign_1_axi_clock_converter_0_0.xmldesign_1_axi_clock_converter_0_0_clocks.xdcdesign_1_axi_clock_converter_0_0_ooc.xdcdesign_1_axi_clock_converter_0_0_sim_netlist.vdesign_1_axi_clock_converter_0_0_sim_netlist.vhdldesign_1_axi_clock_converter_0_0_stub.vdesign_1_axi_clock_converter_0_0_stub.vhdl
sim
design_1_axi_clock_converter_0_0.cppdesign_1_axi_clock_converter_0_0.hdesign_1_axi_clock_converter_0_0.vdesign_1_axi_clock_converter_0_0_sc.cppdesign_1_axi_clock_converter_0_0_sc.hdesign_1_axi_clock_converter_0_0_stub.sv
synth
sysc
design_1_axi_crossbar_0_0
design_1_axi_crossbar_0_0.dcpdesign_1_axi_crossbar_0_0.xcidesign_1_axi_crossbar_0_0.xmldesign_1_axi_crossbar_0_0_ooc.xdcdesign_1_axi_crossbar_0_0_sim_netlist.vdesign_1_axi_crossbar_0_0_sim_netlist.vhdldesign_1_axi_crossbar_0_0_stub.vdesign_1_axi_crossbar_0_0_stub.vhdl
sim
design_1_axi_crossbar_0_0.cppdesign_1_axi_crossbar_0_0.hdesign_1_axi_crossbar_0_0.vdesign_1_axi_crossbar_0_0_sc.cppdesign_1_axi_crossbar_0_0_sc.hdesign_1_axi_crossbar_0_0_stub.sv
src
synth
design_1_axi_crossbar_0_1
design_1_axi_crossbar_0_1.dcpdesign_1_axi_crossbar_0_1.xcidesign_1_axi_crossbar_0_1.xmldesign_1_axi_crossbar_0_1_ooc.xdcdesign_1_axi_crossbar_0_1_sim_netlist.vdesign_1_axi_crossbar_0_1_sim_netlist.vhdldesign_1_axi_crossbar_0_1_stub.vdesign_1_axi_crossbar_0_1_stub.vhdl
sim
design_1_axi_crossbar_0_1.cppdesign_1_axi_crossbar_0_1.hdesign_1_axi_crossbar_0_1.vdesign_1_axi_crossbar_0_1_sc.cppdesign_1_axi_crossbar_0_1_sc.hdesign_1_axi_crossbar_0_1_stub.sv
src
synth
design_1_axi_datamover_0_0
design_1_axi_datamover_0_0.dcpdesign_1_axi_datamover_0_0.xcidesign_1_axi_datamover_0_0.xdcdesign_1_axi_datamover_0_0.xmldesign_1_axi_datamover_0_0_clocks.xdcdesign_1_axi_datamover_0_0_ooc.xdcdesign_1_axi_datamover_0_0_sim_netlist.vdesign_1_axi_datamover_0_0_sim_netlist.vhdldesign_1_axi_datamover_0_0_stub.vdesign_1_axi_datamover_0_0_stub.vhdl
sim
synth
design_1_axi_dwidth_converter_0_0
design_1_axi_dwidth_converter_0_0.dcpdesign_1_axi_dwidth_converter_0_0.xcidesign_1_axi_dwidth_converter_0_0.xmldesign_1_axi_dwidth_converter_0_0_clocks.xdcdesign_1_axi_dwidth_converter_0_0_ooc.xdcdesign_1_axi_dwidth_converter_0_0_sim_netlist.vdesign_1_axi_dwidth_converter_0_0_sim_netlist.vhdldesign_1_axi_dwidth_converter_0_0_stub.vdesign_1_axi_dwidth_converter_0_0_stub.vhdl
sim
design_1_axi_dwidth_converter_0_0.cppdesign_1_axi_dwidth_converter_0_0.hdesign_1_axi_dwidth_converter_0_0.vdesign_1_axi_dwidth_converter_0_0_sc.cppdesign_1_axi_dwidth_converter_0_0_sc.hdesign_1_axi_dwidth_converter_0_0_stub.sv
src
synth
design_1_axi_fifo_mm_s_0_0
design_1_axi_fifo_mm_s_0_0.dcpdesign_1_axi_fifo_mm_s_0_0.xcidesign_1_axi_fifo_mm_s_0_0.xmldesign_1_axi_fifo_mm_s_0_0_ooc.xdcdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vhdldesign_1_axi_fifo_mm_s_0_0_stub.vdesign_1_axi_fifo_mm_s_0_0_stub.vhdl
sim
synth
design_1_axi_gpio_0_1
design_1_axi_gpio_0_1.dcpdesign_1_axi_gpio_0_1.xcidesign_1_axi_gpio_0_1.xdcdesign_1_axi_gpio_0_1.xmldesign_1_axi_gpio_0_1_board.xdcdesign_1_axi_gpio_0_1_ooc.xdcdesign_1_axi_gpio_0_1_sim_netlist.vdesign_1_axi_gpio_0_1_sim_netlist.vhdldesign_1_axi_gpio_0_1_stub.vdesign_1_axi_gpio_0_1_stub.vhdl
sim
synth
design_1_clk_wiz_0_0
design_1_clk_wiz_0_0.dcpdesign_1_clk_wiz_0_0.vdesign_1_clk_wiz_0_0.xcidesign_1_clk_wiz_0_0.xdcdesign_1_clk_wiz_0_0.xmldesign_1_clk_wiz_0_0_board.xdcdesign_1_clk_wiz_0_0_clk_wiz.vdesign_1_clk_wiz_0_0_late.xdcdesign_1_clk_wiz_0_0_ooc.xdcdesign_1_clk_wiz_0_0_sim_netlist.vdesign_1_clk_wiz_0_0_sim_netlist.vhdldesign_1_clk_wiz_0_0_stub.vdesign_1_clk_wiz_0_0_stub.vhdl
design_1_mig_7series_0_0
design_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.veodesign_1_mig_7series_0_0.xcidesign_1_mig_7series_0_0.xml
design_1_mig_7series_0_0
datasheet.txt
design_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdldesign_1_mig_7series_0_0_xmdf.tclmig_a.prjmig_b.prjxil_txt.inxil_txt.outdocs
example_design
mig.prjuser_design
constraints
rtl
axi
mig_7series_v4_2_axi_ctrl_addr_decode.vmig_7series_v4_2_axi_ctrl_read.vmig_7series_v4_2_axi_ctrl_reg.vmig_7series_v4_2_axi_ctrl_reg_bank.vmig_7series_v4_2_axi_ctrl_top.vmig_7series_v4_2_axi_ctrl_write.vmig_7series_v4_2_axi_mc.vmig_7series_v4_2_axi_mc_ar_channel.vmig_7series_v4_2_axi_mc_aw_channel.vmig_7series_v4_2_axi_mc_b_channel.vmig_7series_v4_2_axi_mc_cmd_arbiter.vmig_7series_v4_2_axi_mc_cmd_fsm.vmig_7series_v4_2_axi_mc_cmd_translator.vmig_7series_v4_2_axi_mc_fifo.vmig_7series_v4_2_axi_mc_incr_cmd.vmig_7series_v4_2_axi_mc_r_channel.vmig_7series_v4_2_axi_mc_simple_fifo.vmig_7series_v4_2_axi_mc_w_channel.vmig_7series_v4_2_axi_mc_wr_cmd_fsm.vmig_7series_v4_2_axi_mc_wrap_cmd.vmig_7series_v4_2_ddr_a_upsizer.vmig_7series_v4_2_ddr_axi_register_slice.vmig_7series_v4_2_ddr_axi_upsizer.vmig_7series_v4_2_ddr_axic_register_slice.vmig_7series_v4_2_ddr_carry_and.vmig_7series_v4_2_ddr_carry_latch_and.vmig_7series_v4_2_ddr_carry_latch_or.vmig_7series_v4_2_ddr_carry_or.vmig_7series_v4_2_ddr_command_fifo.vmig_7series_v4_2_ddr_comparator.vmig_7series_v4_2_ddr_comparator_sel.vmig_7series_v4_2_ddr_comparator_sel_static.vmig_7series_v4_2_ddr_r_upsizer.vmig_7series_v4_2_ddr_w_upsizer.v
clocking
mig_7series_v4_2_clk_ibuf.vmig_7series_v4_2_infrastructure.vmig_7series_v4_2_iodelay_ctrl.vmig_7series_v4_2_tempmon.v
controller
mig_7series_v4_2_arb_mux.vmig_7series_v4_2_arb_row_col.vmig_7series_v4_2_arb_select.vmig_7series_v4_2_bank_cntrl.vmig_7series_v4_2_bank_common.vmig_7series_v4_2_bank_compare.vmig_7series_v4_2_bank_mach.vmig_7series_v4_2_bank_queue.vmig_7series_v4_2_bank_state.vmig_7series_v4_2_col_mach.vmig_7series_v4_2_mc.vmig_7series_v4_2_rank_cntrl.vmig_7series_v4_2_rank_common.vmig_7series_v4_2_rank_mach.vmig_7series_v4_2_round_robin_arb.v
design_1_mig_7series_0_0.vdesign_1_mig_7series_0_0_mig.vdesign_1_mig_7series_0_0_mig_sim.vecc
mig_7series_v4_2_ecc_buf.vmig_7series_v4_2_ecc_dec_fix.vmig_7series_v4_2_ecc_gen.vmig_7series_v4_2_ecc_merge_enc.vmig_7series_v4_2_fi_xor.v
ip_top
phy
mig_7series_v4_2_ddr_byte_group_io.vmig_7series_v4_2_ddr_byte_lane.vmig_7series_v4_2_ddr_calib_top.vmig_7series_v4_2_ddr_if_post_fifo.vmig_7series_v4_2_ddr_mc_phy.vmig_7series_v4_2_ddr_mc_phy_wrapper.vmig_7series_v4_2_ddr_of_pre_fifo.vmig_7series_v4_2_ddr_phy_4lanes.vmig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.vmig_7series_v4_2_ddr_phy_dqs_found_cal.vmig_7series_v4_2_ddr_phy_dqs_found_cal_hr.vmig_7series_v4_2_ddr_phy_init.vmig_7series_v4_2_ddr_phy_ocd_cntlr.vmig_7series_v4_2_ddr_phy_ocd_data.vmig_7series_v4_2_ddr_phy_ocd_edge.vmig_7series_v4_2_ddr_phy_ocd_lim.vmig_7series_v4_2_ddr_phy_ocd_mux.vmig_7series_v4_2_ddr_phy_ocd_po_cntlr.vmig_7series_v4_2_ddr_phy_ocd_samp.vmig_7series_v4_2_ddr_phy_oclkdelay_cal.vmig_7series_v4_2_ddr_phy_prbs_rdlvl.vmig_7series_v4_2_ddr_phy_rdlvl.vmig_7series_v4_2_ddr_phy_tempmon.vmig_7series_v4_2_ddr_phy_top.vmig_7series_v4_2_ddr_phy_wrcal.vmig_7series_v4_2_ddr_phy_wrlvl.vmig_7series_v4_2_ddr_phy_wrlvl_off_delay.vmig_7series_v4_2_ddr_prbs_gen.vmig_7series_v4_2_ddr_skip_calib_tap.vmig_7series_v4_2_poc_cc.vmig_7series_v4_2_poc_edge_store.vmig_7series_v4_2_poc_meta.vmig_7series_v4_2_poc_pd.vmig_7series_v4_2_poc_tap_base.vmig_7series_v4_2_poc_top.v
ui
design_1_util_ds_buf_0_0
design_1_util_ds_buf_0_0.dcpdesign_1_util_ds_buf_0_0.xcidesign_1_util_ds_buf_0_0.xmldesign_1_util_ds_buf_0_0_board.xdcdesign_1_util_ds_buf_0_0_ooc.xdcdesign_1_util_ds_buf_0_0_sim_netlist.vdesign_1_util_ds_buf_0_0_sim_netlist.vhdldesign_1_util_ds_buf_0_0_stub.vdesign_1_util_ds_buf_0_0_stub.vhdl
sim
synth
util_ds_buf.vhddesign_1_util_vector_logic_0_0
design_1_util_vector_logic_0_0.dcpdesign_1_util_vector_logic_0_0.xcidesign_1_util_vector_logic_0_0.xmldesign_1_util_vector_logic_0_0_sim_netlist.vdesign_1_util_vector_logic_0_0_sim_netlist.vhdldesign_1_util_vector_logic_0_0_stub.vdesign_1_util_vector_logic_0_0_stub.vhdl
sim
synth
design_1_xdma_0_0
design_1_xdma_0_0.dcpdesign_1_xdma_0_0.xcidesign_1_xdma_0_0.xmldesign_1_xdma_0_0_board.xdcdesign_1_xdma_0_0_sim_netlist.vdesign_1_xdma_0_0_sim_netlist.vhdldesign_1_xdma_0_0_stub.vdesign_1_xdma_0_0_stub.vhdl
ip_0
design_1_xdma_0_0_pcie2_ip.xcidesign_1_xdma_0_0_pcie2_ip.xml
sim
source
design_1_xdma_0_0_pcie2_ip-PCIE_X0Y0.xdcdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_top.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.vdesign_1_xdma_0_0_pcie2_ip_core_top.vdesign_1_xdma_0_0_pcie2_ip_gt_common.vdesign_1_xdma_0_0_pcie2_ip_gt_rx_valid_filter_7x.vdesign_1_xdma_0_0_pcie2_ip_gt_top.vdesign_1_xdma_0_0_pcie2_ip_gt_wrapper.vdesign_1_xdma_0_0_pcie2_ip_gtp_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_gtx_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_pcie2_top.vdesign_1_xdma_0_0_pcie2_ip_pcie_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_top_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_brams_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_lane.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_misc.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_pipeline.vdesign_1_xdma_0_0_pcie2_ip_pcie_top.vdesign_1_xdma_0_0_pcie2_ip_pipe_clock.vdesign_1_xdma_0_0_pcie2_ip_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_pipe_eq.vdesign_1_xdma_0_0_pcie2_ip_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_pipe_sync.vdesign_1_xdma_0_0_pcie2_ip_pipe_user.vdesign_1_xdma_0_0_pcie2_ip_pipe_wrapper.vdesign_1_xdma_0_0_pcie2_ip_qpll_drp.vdesign_1_xdma_0_0_pcie2_ip_qpll_reset.vdesign_1_xdma_0_0_pcie2_ip_qpll_wrapper.vdesign_1_xdma_0_0_pcie2_ip_rxeq_scan.v
synth
sys_clk_gen_ps_v.txtip_1
sim
synth
xdma_v4_1_6_blk_mem_64_reg_be.xcixdma_v4_1_6_blk_mem_64_reg_be.xmlxdma_v4_1_6_blk_mem_64_reg_be_ooc.xdcip_2
sim
synth
xdma_v4_1_6_blk_mem_64_noreg_be.xcixdma_v4_1_6_blk_mem_64_noreg_be.xmlxdma_v4_1_6_blk_mem_64_noreg_be_ooc.xdcip_3
pcie2_fifo_generator_dma_cpl.xcipcie2_fifo_generator_dma_cpl.xdcpcie2_fifo_generator_dma_cpl.xml
sim
synth
ip_4
pcie2_fifo_generator_tgt_brdg.xcipcie2_fifo_generator_tgt_brdg.xdcpcie2_fifo_generator_tgt_brdg.xml
sim
synth
sim
source
synth
xdma_v4_1/hdl/verilog
design_1_xdma_0_0_axi_stream_intf.svdesign_1_xdma_0_0_cfg_sideband.svdesign_1_xdma_0_0_core_top.svdesign_1_xdma_0_0_dma_bram_wrap.svdesign_1_xdma_0_0_dma_bram_wrap_1024.svdesign_1_xdma_0_0_dma_bram_wrap_2048.svdesign_1_xdma_0_0_dma_cpl.svdesign_1_xdma_0_0_dma_req.svdesign_1_xdma_0_0_pcie2_to_pcie3_wrapper.svdesign_1_xdma_0_0_rx_demux.svdesign_1_xdma_0_0_rx_destraddler.svdesign_1_xdma_0_0_tgt_cpl.svdesign_1_xdma_0_0_tgt_req.svdesign_1_xdma_0_0_tx_mux.sv
design_1_xlconstant_0_0
design_1_xlconstant_0_0.xcidesign_1_xlconstant_0_0.xml
sim
design_1_xlconstant_0_0.cppdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_0.vdesign_1_xlconstant_0_0_stub.svxlconstant_v1_1_7.h
synth
design_1_xlconstant_0_2
design_1_xlconstant_0_2.xcidesign_1_xlconstant_0_2.xml
sim
design_1_xlconstant_0_2.cppdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_2.vdesign_1_xlconstant_0_2_stub.svxlconstant_v1_1_7.h
synth
design_1_xlconstant_0_3
ipshared
0513/hdl
07be/hdl
2137/hdl
2751/hdl
276e
hdl
simulation
2985
2ef9/hdl
47c9/hdl
51ce/hdl
5bfc/hdl
66ea/hdl
7589/hdl
8b3d
mmcm_pll_drp_func_7s_mmcm.vhmmcm_pll_drp_func_7s_pll.vhmmcm_pll_drp_func_us_mmcm.vhmmcm_pll_drp_func_us_pll.vhmmcm_pll_drp_func_us_plus_mmcm.vhmmcm_pll_drp_func_us_plus_pll.vh
8dfa/hdl
a040/hdl
a5cb/hdl
af86/hdl
b68e/hdl
b752/hdl
b8f8/hdl
verilog
axi_infrastructure_header.vhaxidma_fifo.vhdma_defines.svhdma_defines.vhdma_pcie_axis_cc_if.svhdma_pcie_axis_cq_if.svhdma_pcie_axis_rc_if.svhdma_pcie_axis_rq_if.svhdma_pcie_c2h_crdt_if.svhdma_pcie_dsc_in_if.svhdma_pcie_dsc_out_if.svhdma_pcie_fabric_input_if.svhdma_pcie_fabric_output_if.svhdma_pcie_gic_if.svhdma_pcie_h2c_crdt_if.svhdma_pcie_mi_16Bx2048_4Bwe_ram_if.svhdma_pcie_mi_2Bx2048_ram_if.svhdma_pcie_mi_4Bx2048_4Bwe_ram_if.svhdma_pcie_mi_64Bx1024_32Bwe_ram_if.svhdma_pcie_mi_64Bx128_32Bwe_ram_if.svhdma_pcie_mi_64Bx2048_32Bwe_ram_if.svhdma_pcie_mi_64Bx256_32Bwe_ram_if.svhdma_pcie_mi_64Bx512_32Bwe_ram_if.svhdma_pcie_mi_8Bx2048_4Bwe_ram_if.svhdma_pcie_mi_dsc_cpld_if.svhdma_pcie_mi_dsc_cpli_if.svhdma_pcie_misc_input_if.svhdma_pcie_misc_output_if.svhdma_soft_defines.vhpcie_dma_attr_defines.svhpciedmacoredefines.vhxdma_axi4mm_axi_bridge.vh
xdma_v4_1_vl_rfs.svbb35/hdl
e6d5
hdl
simulation
ec67/hdl
ef1e/hdl
fcfc/hdl
sim
synth
ui
imports
ip
clk_wiz_0.xcix
fifo_generator_0
doc
fifo_generator_0.dcpfifo_generator_0.veofifo_generator_0.vhofifo_generator_0.xcififo_generator_0.xdcfifo_generator_0.xmlfifo_generator_0_clocks.xdcfifo_generator_0_ooc.xdcfifo_generator_0_sim_netlist.vfifo_generator_0_sim_netlist.vhdlfifo_generator_0_stub.vfifo_generator_0_stub.vhdlhdl
blk_mem_gen_v8_4_vhsyn_rfs.vhdfifo_generator_v13_2_rfs.vfifo_generator_v13_2_rfs.vhdfifo_generator_v13_2_vhsyn_rfs.vhd
sim
simulation
synth
new
dso_top_TE0712_unsigned
dso_top.bindso_top.xpr
dso_top.ip_user_files
README.txt
ip
clk_wiz_0
clk_wiz_0.vclk_wiz_0.veoclk_wiz_0_clk_wiz.vclk_wiz_0_sim_netlist.vclk_wiz_0_sim_netlist.vhdlclk_wiz_0_stub.vclk_wiz_0_stub.vhdl
fifo_generator_0
ipstatic
mem_init_files
axi_clock_converter.haxi_crossbar.haxi_data_fifo.haxi_dwidth_converter.hbd_48ac_one_0.hdesign_1_auto_cc_0.hdesign_1_auto_cc_0_sc.hdesign_1_auto_us_df_0.hdesign_1_auto_us_df_0_sc.hdesign_1_auto_us_df_1.hdesign_1_auto_us_df_1_sc.hdesign_1_axi_clock_converter_0_0.hdesign_1_axi_clock_converter_0_0_sc.hdesign_1_axi_crossbar_0_0.hdesign_1_axi_crossbar_0_0_sc.hdesign_1_axi_crossbar_0_1.hdesign_1_axi_crossbar_0_1_sc.hdesign_1_axi_dwidth_converter_0_0.hdesign_1_axi_dwidth_converter_0_0_sc.hdesign_1_m00_data_fifo_0.hdesign_1_m00_data_fifo_0_sc.hdesign_1_smartconnect_0_0.hdesign_1_smartconnect_0_0_sc.hdesign_1_xbar_0.hdesign_1_xbar_0_sc.hdesign_1_xbar_1.hdesign_1_xbar_1_sc.hdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_3.hmig_a.prjmig_b.prjsc_xtlm_design_1_smartconnect_0_0.memsmartconnect.cxxsmartconnect.hsmartconnect_xtlm.cxxsmartconnect_xtlm.hsmartconnect_xtlm_impl.hsys_clk_gen_ps_v.txtxlconstant_v1_1_7.h
sim_scripts
clk_wiz_0
design_1
README.txt
activehdl
README.txtcompile.dodesign_1.shdesign_1.udofile_info.txtglbl.vmig_a.prjsimulate.dosys_clk_gen_ps_v.txtwave.do
ies
modelsim
README.txtcompile.dodesign_1.shdesign_1.udofile_info.txtglbl.vmig_a.prjsimulate.dosys_clk_gen_ps_v.txtwave.do
questa
README.txtcompile.dodesign_1.shdesign_1.udoelaborate.dofile_info.txtglbl.vmig_a.prjsimulate.dosys_clk_gen_ps_v.txtwave.do
riviera
README.txtcompile.dodesign_1.shdesign_1.udofile_info.txtglbl.vmig_a.prjsimulate.dosys_clk_gen_ps_v.txtwave.do
vcs
xcelium
xsim
fifo_generator_0
README.txt
activehdl
ies
modelsim
questa
README.txtcompile.doelaborate.dofifo_generator_0.shfifo_generator_0.udofile_info.txtglbl.vsimulate.dowave.do
riviera
vcs
xcelium
xsim
dso_top.srcs
constrs_1
sources_1
bd/design_1
design_1.bddesign_1.bxmldesign_1_ooc.xdc
hdl
hw_handoff
ip
design_1_axi_clock_converter_0_0
design_1_axi_clock_converter_0_0.dcpdesign_1_axi_clock_converter_0_0.xcidesign_1_axi_clock_converter_0_0.xmldesign_1_axi_clock_converter_0_0_clocks.xdcdesign_1_axi_clock_converter_0_0_ooc.xdcdesign_1_axi_clock_converter_0_0_sim_netlist.vdesign_1_axi_clock_converter_0_0_sim_netlist.vhdldesign_1_axi_clock_converter_0_0_stub.vdesign_1_axi_clock_converter_0_0_stub.vhdl
sim
design_1_axi_clock_converter_0_0.cppdesign_1_axi_clock_converter_0_0.hdesign_1_axi_clock_converter_0_0.vdesign_1_axi_clock_converter_0_0_sc.cppdesign_1_axi_clock_converter_0_0_sc.hdesign_1_axi_clock_converter_0_0_stub.sv
synth
sysc
design_1_axi_crossbar_0_0
design_1_axi_crossbar_0_0.dcpdesign_1_axi_crossbar_0_0.xcidesign_1_axi_crossbar_0_0.xmldesign_1_axi_crossbar_0_0_ooc.xdcdesign_1_axi_crossbar_0_0_sim_netlist.vdesign_1_axi_crossbar_0_0_sim_netlist.vhdldesign_1_axi_crossbar_0_0_stub.vdesign_1_axi_crossbar_0_0_stub.vhdl
sim
design_1_axi_crossbar_0_0.cppdesign_1_axi_crossbar_0_0.hdesign_1_axi_crossbar_0_0.vdesign_1_axi_crossbar_0_0_sc.cppdesign_1_axi_crossbar_0_0_sc.hdesign_1_axi_crossbar_0_0_stub.sv
src
synth
design_1_axi_crossbar_0_1
design_1_axi_crossbar_0_1.dcpdesign_1_axi_crossbar_0_1.xcidesign_1_axi_crossbar_0_1.xmldesign_1_axi_crossbar_0_1_ooc.xdcdesign_1_axi_crossbar_0_1_sim_netlist.vdesign_1_axi_crossbar_0_1_sim_netlist.vhdldesign_1_axi_crossbar_0_1_stub.vdesign_1_axi_crossbar_0_1_stub.vhdl
sim
design_1_axi_crossbar_0_1.cppdesign_1_axi_crossbar_0_1.hdesign_1_axi_crossbar_0_1.vdesign_1_axi_crossbar_0_1_sc.cppdesign_1_axi_crossbar_0_1_sc.hdesign_1_axi_crossbar_0_1_stub.sv
src
synth
design_1_axi_datamover_0_0
design_1_axi_datamover_0_0.dcpdesign_1_axi_datamover_0_0.xcidesign_1_axi_datamover_0_0.xdcdesign_1_axi_datamover_0_0.xmldesign_1_axi_datamover_0_0_clocks.xdcdesign_1_axi_datamover_0_0_ooc.xdcdesign_1_axi_datamover_0_0_sim_netlist.vdesign_1_axi_datamover_0_0_sim_netlist.vhdldesign_1_axi_datamover_0_0_stub.vdesign_1_axi_datamover_0_0_stub.vhdl
sim
synth
design_1_axi_dwidth_converter_0_0
design_1_axi_dwidth_converter_0_0.dcpdesign_1_axi_dwidth_converter_0_0.xcidesign_1_axi_dwidth_converter_0_0.xmldesign_1_axi_dwidth_converter_0_0_clocks.xdcdesign_1_axi_dwidth_converter_0_0_ooc.xdcdesign_1_axi_dwidth_converter_0_0_sim_netlist.vdesign_1_axi_dwidth_converter_0_0_sim_netlist.vhdldesign_1_axi_dwidth_converter_0_0_stub.vdesign_1_axi_dwidth_converter_0_0_stub.vhdl
sim
design_1_axi_dwidth_converter_0_0.cppdesign_1_axi_dwidth_converter_0_0.hdesign_1_axi_dwidth_converter_0_0.vdesign_1_axi_dwidth_converter_0_0_sc.cppdesign_1_axi_dwidth_converter_0_0_sc.hdesign_1_axi_dwidth_converter_0_0_stub.sv
src
synth
design_1_axi_fifo_mm_s_0_0
design_1_axi_fifo_mm_s_0_0.dcpdesign_1_axi_fifo_mm_s_0_0.xcidesign_1_axi_fifo_mm_s_0_0.xmldesign_1_axi_fifo_mm_s_0_0_ooc.xdcdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vdesign_1_axi_fifo_mm_s_0_0_sim_netlist.vhdldesign_1_axi_fifo_mm_s_0_0_stub.vdesign_1_axi_fifo_mm_s_0_0_stub.vhdl
sim
synth
design_1_axi_gpio_0_1
design_1_axi_gpio_0_1.dcpdesign_1_axi_gpio_0_1.xcidesign_1_axi_gpio_0_1.xdcdesign_1_axi_gpio_0_1.xmldesign_1_axi_gpio_0_1_board.xdcdesign_1_axi_gpio_0_1_ooc.xdcdesign_1_axi_gpio_0_1_sim_netlist.vdesign_1_axi_gpio_0_1_sim_netlist.vhdldesign_1_axi_gpio_0_1_stub.vdesign_1_axi_gpio_0_1_stub.vhdl
sim
synth
design_1_clk_wiz_0_0
design_1_clk_wiz_0_0.dcpdesign_1_clk_wiz_0_0.vdesign_1_clk_wiz_0_0.xcidesign_1_clk_wiz_0_0.xdcdesign_1_clk_wiz_0_0.xmldesign_1_clk_wiz_0_0_board.xdcdesign_1_clk_wiz_0_0_clk_wiz.vdesign_1_clk_wiz_0_0_late.xdcdesign_1_clk_wiz_0_0_ooc.xdcdesign_1_clk_wiz_0_0_sim_netlist.vdesign_1_clk_wiz_0_0_sim_netlist.vhdldesign_1_clk_wiz_0_0_stub.vdesign_1_clk_wiz_0_0_stub.vhdl
design_1_mig_7series_0_0
design_1_mig_7series_0_0.dcpdesign_1_mig_7series_0_0.xcidesign_1_mig_7series_0_0.xmldesign_1_mig_7series_0_0_sim_netlist.vdesign_1_mig_7series_0_0_sim_netlist.vhdldesign_1_mig_7series_0_0_stub.vdesign_1_mig_7series_0_0_stub.vhdlmig_a.prjmig_b.prj
design_1_mig_7series_0_0/user_design
constraints
rtl
axi
mig_7series_v4_2_axi_ctrl_addr_decode.vmig_7series_v4_2_axi_ctrl_read.vmig_7series_v4_2_axi_ctrl_reg.vmig_7series_v4_2_axi_ctrl_reg_bank.vmig_7series_v4_2_axi_ctrl_top.vmig_7series_v4_2_axi_ctrl_write.vmig_7series_v4_2_axi_mc.vmig_7series_v4_2_axi_mc_ar_channel.vmig_7series_v4_2_axi_mc_aw_channel.vmig_7series_v4_2_axi_mc_b_channel.vmig_7series_v4_2_axi_mc_cmd_arbiter.vmig_7series_v4_2_axi_mc_cmd_fsm.vmig_7series_v4_2_axi_mc_cmd_translator.vmig_7series_v4_2_axi_mc_fifo.vmig_7series_v4_2_axi_mc_incr_cmd.vmig_7series_v4_2_axi_mc_r_channel.vmig_7series_v4_2_axi_mc_simple_fifo.vmig_7series_v4_2_axi_mc_w_channel.vmig_7series_v4_2_axi_mc_wr_cmd_fsm.vmig_7series_v4_2_axi_mc_wrap_cmd.vmig_7series_v4_2_ddr_a_upsizer.vmig_7series_v4_2_ddr_axi_register_slice.vmig_7series_v4_2_ddr_axi_upsizer.vmig_7series_v4_2_ddr_axic_register_slice.vmig_7series_v4_2_ddr_carry_and.vmig_7series_v4_2_ddr_carry_latch_and.vmig_7series_v4_2_ddr_carry_latch_or.vmig_7series_v4_2_ddr_carry_or.vmig_7series_v4_2_ddr_command_fifo.vmig_7series_v4_2_ddr_comparator.vmig_7series_v4_2_ddr_comparator_sel.vmig_7series_v4_2_ddr_comparator_sel_static.vmig_7series_v4_2_ddr_r_upsizer.vmig_7series_v4_2_ddr_w_upsizer.v
clocking
mig_7series_v4_2_clk_ibuf.vmig_7series_v4_2_infrastructure.vmig_7series_v4_2_iodelay_ctrl.vmig_7series_v4_2_tempmon.v
controller
mig_7series_v4_2_arb_mux.vmig_7series_v4_2_arb_row_col.vmig_7series_v4_2_arb_select.vmig_7series_v4_2_bank_cntrl.vmig_7series_v4_2_bank_common.vmig_7series_v4_2_bank_compare.vmig_7series_v4_2_bank_mach.vmig_7series_v4_2_bank_queue.vmig_7series_v4_2_bank_state.vmig_7series_v4_2_col_mach.vmig_7series_v4_2_mc.vmig_7series_v4_2_rank_cntrl.vmig_7series_v4_2_rank_common.vmig_7series_v4_2_rank_mach.vmig_7series_v4_2_round_robin_arb.v
design_1_mig_7series_0_0.vdesign_1_mig_7series_0_0_mig.vdesign_1_mig_7series_0_0_mig_sim.vecc
mig_7series_v4_2_ecc_buf.vmig_7series_v4_2_ecc_dec_fix.vmig_7series_v4_2_ecc_gen.vmig_7series_v4_2_ecc_merge_enc.vmig_7series_v4_2_fi_xor.v
ip_top
phy
mig_7series_v4_2_ddr_byte_group_io.vmig_7series_v4_2_ddr_byte_lane.vmig_7series_v4_2_ddr_calib_top.vmig_7series_v4_2_ddr_if_post_fifo.vmig_7series_v4_2_ddr_mc_phy.vmig_7series_v4_2_ddr_mc_phy_wrapper.vmig_7series_v4_2_ddr_of_pre_fifo.vmig_7series_v4_2_ddr_phy_4lanes.vmig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.vmig_7series_v4_2_ddr_phy_dqs_found_cal.vmig_7series_v4_2_ddr_phy_dqs_found_cal_hr.vmig_7series_v4_2_ddr_phy_init.vmig_7series_v4_2_ddr_phy_ocd_cntlr.vmig_7series_v4_2_ddr_phy_ocd_data.vmig_7series_v4_2_ddr_phy_ocd_edge.vmig_7series_v4_2_ddr_phy_ocd_lim.vmig_7series_v4_2_ddr_phy_ocd_mux.vmig_7series_v4_2_ddr_phy_ocd_po_cntlr.vmig_7series_v4_2_ddr_phy_ocd_samp.vmig_7series_v4_2_ddr_phy_oclkdelay_cal.vmig_7series_v4_2_ddr_phy_prbs_rdlvl.vmig_7series_v4_2_ddr_phy_rdlvl.vmig_7series_v4_2_ddr_phy_tempmon.vmig_7series_v4_2_ddr_phy_top.vmig_7series_v4_2_ddr_phy_wrcal.vmig_7series_v4_2_ddr_phy_wrlvl.vmig_7series_v4_2_ddr_phy_wrlvl_off_delay.vmig_7series_v4_2_ddr_prbs_gen.vmig_7series_v4_2_ddr_skip_calib_tap.vmig_7series_v4_2_poc_cc.vmig_7series_v4_2_poc_edge_store.vmig_7series_v4_2_poc_meta.vmig_7series_v4_2_poc_pd.vmig_7series_v4_2_poc_tap_base.vmig_7series_v4_2_poc_top.v
ui
design_1_util_ds_buf_0_0
design_1_util_ds_buf_0_0.dcpdesign_1_util_ds_buf_0_0.xcidesign_1_util_ds_buf_0_0.xmldesign_1_util_ds_buf_0_0_board.xdcdesign_1_util_ds_buf_0_0_ooc.xdcdesign_1_util_ds_buf_0_0_sim_netlist.vdesign_1_util_ds_buf_0_0_sim_netlist.vhdldesign_1_util_ds_buf_0_0_stub.vdesign_1_util_ds_buf_0_0_stub.vhdl
sim
synth
util_ds_buf.vhddesign_1_util_vector_logic_0_0
design_1_util_vector_logic_0_0.dcpdesign_1_util_vector_logic_0_0.xcidesign_1_util_vector_logic_0_0.xmldesign_1_util_vector_logic_0_0_sim_netlist.vdesign_1_util_vector_logic_0_0_sim_netlist.vhdldesign_1_util_vector_logic_0_0_stub.vdesign_1_util_vector_logic_0_0_stub.vhdl
sim
synth
design_1_xdma_0_0
design_1_xdma_0_0.dcpdesign_1_xdma_0_0.xcidesign_1_xdma_0_0.xmldesign_1_xdma_0_0_board.xdcdesign_1_xdma_0_0_sim_netlist.vdesign_1_xdma_0_0_sim_netlist.vhdldesign_1_xdma_0_0_stub.vdesign_1_xdma_0_0_stub.vhdl
ip_0
design_1_xdma_0_0_pcie2_ip.xcidesign_1_xdma_0_0_pcie2_ip.xml
sim
source
design_1_xdma_0_0_pcie2_ip-PCIE_X0Y0.xdcdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_top.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.vdesign_1_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.vdesign_1_xdma_0_0_pcie2_ip_core_top.vdesign_1_xdma_0_0_pcie2_ip_gt_common.vdesign_1_xdma_0_0_pcie2_ip_gt_rx_valid_filter_7x.vdesign_1_xdma_0_0_pcie2_ip_gt_top.vdesign_1_xdma_0_0_pcie2_ip_gt_wrapper.vdesign_1_xdma_0_0_pcie2_ip_gtp_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_gtp_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_gtx_cpllpd_ovrd.vdesign_1_xdma_0_0_pcie2_ip_pcie2_top.vdesign_1_xdma_0_0_pcie2_ip_pcie_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_bram_top_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_brams_7x.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_lane.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_misc.vdesign_1_xdma_0_0_pcie2_ip_pcie_pipe_pipeline.vdesign_1_xdma_0_0_pcie2_ip_pcie_top.vdesign_1_xdma_0_0_pcie2_ip_pipe_clock.vdesign_1_xdma_0_0_pcie2_ip_pipe_drp.vdesign_1_xdma_0_0_pcie2_ip_pipe_eq.vdesign_1_xdma_0_0_pcie2_ip_pipe_rate.vdesign_1_xdma_0_0_pcie2_ip_pipe_reset.vdesign_1_xdma_0_0_pcie2_ip_pipe_sync.vdesign_1_xdma_0_0_pcie2_ip_pipe_user.vdesign_1_xdma_0_0_pcie2_ip_pipe_wrapper.vdesign_1_xdma_0_0_pcie2_ip_qpll_drp.vdesign_1_xdma_0_0_pcie2_ip_qpll_reset.vdesign_1_xdma_0_0_pcie2_ip_qpll_wrapper.vdesign_1_xdma_0_0_pcie2_ip_rxeq_scan.v
synth
sys_clk_gen_ps_v.txtip_1
sim
synth
xdma_v4_1_6_blk_mem_64_reg_be.xcixdma_v4_1_6_blk_mem_64_reg_be.xmlxdma_v4_1_6_blk_mem_64_reg_be_ooc.xdcip_2
sim
synth
xdma_v4_1_6_blk_mem_64_noreg_be.xcixdma_v4_1_6_blk_mem_64_noreg_be.xmlxdma_v4_1_6_blk_mem_64_noreg_be_ooc.xdcip_3
pcie2_fifo_generator_dma_cpl.xcipcie2_fifo_generator_dma_cpl.xdcpcie2_fifo_generator_dma_cpl.xml
sim
synth
ip_4
pcie2_fifo_generator_tgt_brdg.xcipcie2_fifo_generator_tgt_brdg.xdcpcie2_fifo_generator_tgt_brdg.xml
sim
synth
sim
source
synth
xdma_v4_1/hdl/verilog
design_1_xdma_0_0_axi_stream_intf.svdesign_1_xdma_0_0_cfg_sideband.svdesign_1_xdma_0_0_core_top.svdesign_1_xdma_0_0_dma_bram_wrap.svdesign_1_xdma_0_0_dma_bram_wrap_1024.svdesign_1_xdma_0_0_dma_bram_wrap_2048.svdesign_1_xdma_0_0_dma_cpl.svdesign_1_xdma_0_0_dma_req.svdesign_1_xdma_0_0_pcie2_to_pcie3_wrapper.svdesign_1_xdma_0_0_rx_demux.svdesign_1_xdma_0_0_rx_destraddler.svdesign_1_xdma_0_0_tgt_cpl.svdesign_1_xdma_0_0_tgt_req.svdesign_1_xdma_0_0_tx_mux.sv
design_1_xlconstant_0_0
design_1_xlconstant_0_0.xcidesign_1_xlconstant_0_0.xml
sim
design_1_xlconstant_0_0.cppdesign_1_xlconstant_0_0.hdesign_1_xlconstant_0_0.vdesign_1_xlconstant_0_0_stub.svxlconstant_v1_1_7.h
synth
design_1_xlconstant_0_2
design_1_xlconstant_0_2.xcidesign_1_xlconstant_0_2.xml
sim
design_1_xlconstant_0_2.cppdesign_1_xlconstant_0_2.hdesign_1_xlconstant_0_2.vdesign_1_xlconstant_0_2_stub.svxlconstant_v1_1_7.h
synth
design_1_xlconstant_0_3
ipshared
0513/hdl
07be/hdl
2137/hdl
2751/hdl
276e
hdl
simulation
2985
2ef9/hdl
47c9/hdl
51ce/hdl
5bfc/hdl
66ea/hdl
7589/hdl
8b3d
mmcm_pll_drp_func_7s_mmcm.vhmmcm_pll_drp_func_7s_pll.vhmmcm_pll_drp_func_us_mmcm.vhmmcm_pll_drp_func_us_pll.vhmmcm_pll_drp_func_us_plus_mmcm.vhmmcm_pll_drp_func_us_plus_pll.vh
8dfa/hdl
a040/hdl
a5cb/hdl
af86/hdl
b68e/hdl
b752/hdl
b8f8/hdl
verilog
axi_infrastructure_header.vhaxidma_fifo.vhdma_defines.svhdma_defines.vhdma_pcie_axis_cc_if.svhdma_pcie_axis_cq_if.svhdma_pcie_axis_rc_if.svhdma_pcie_axis_rq_if.svhdma_pcie_c2h_crdt_if.svhdma_pcie_dsc_in_if.svhdma_pcie_dsc_out_if.svhdma_pcie_fabric_input_if.svhdma_pcie_fabric_output_if.svhdma_pcie_gic_if.svhdma_pcie_h2c_crdt_if.svhdma_pcie_mi_16Bx2048_4Bwe_ram_if.svhdma_pcie_mi_2Bx2048_ram_if.svhdma_pcie_mi_4Bx2048_4Bwe_ram_if.svhdma_pcie_mi_64Bx1024_32Bwe_ram_if.svhdma_pcie_mi_64Bx128_32Bwe_ram_if.svhdma_pcie_mi_64Bx2048_32Bwe_ram_if.svhdma_pcie_mi_64Bx256_32Bwe_ram_if.svhdma_pcie_mi_64Bx512_32Bwe_ram_if.svhdma_pcie_mi_8Bx2048_4Bwe_ram_if.svhdma_pcie_mi_dsc_cpld_if.svhdma_pcie_mi_dsc_cpli_if.svhdma_pcie_misc_input_if.svhdma_pcie_misc_output_if.svhdma_soft_defines.vhpcie_dma_attr_defines.svhpciedmacoredefines.vhxdma_axi4mm_axi_bridge.vh
xdma_v4_1_vl_rfs.svbb35/hdl
e6d5
hdl
simulation
ec67/hdl
ef1e/hdl
fcfc/hdl
sim
synth
ui
imports
ip
.Xil
clk_wiz_0.xcixfifo_generator_0
doc
fifo_generator_0.dcpfifo_generator_0.veofifo_generator_0.vhofifo_generator_0.xcififo_generator_0.xdcfifo_generator_0.xmlfifo_generator_0_clocks.xdcfifo_generator_0_ooc.xdcfifo_generator_0_sim_netlist.vfifo_generator_0_sim_netlist.vhdlfifo_generator_0_stub.vfifo_generator_0_stub.vhdlhdl
blk_mem_gen_v8_4_vhsyn_rfs.vhdfifo_generator_v13_2_rfs.vfifo_generator_v13_2_rfs.vhdfifo_generator_v13_2_vhsyn_rfs.vhd
sim
simulation
synth
new
@ -1,55 +0,0 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_clock_converter" spirit:version="2.1"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">2d3583ce78ad6539</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">e9eb3c28</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">41</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISOPTS">-directive areaoptimized_high -control_set_opt_threshold 1</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:componentInstances>
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</spirit:design>
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File diff suppressed because it is too large
Load Diff
@ -1,83 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>34509a0b69fcb1af</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>design_1_axi_datamover_0_0</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_datamover" spirit:version="5.1"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_S2MM_CMDSTS_AWCLK.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_S2MM_STS.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM_CMD.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_include_mm2s">Omit</spirit:configurableElementValue>
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|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">34509a0b69fcb1af</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">e68418ab</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">55</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">23</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISOPTS">-directive areaoptimized_high -control_set_opt_threshold 1</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@ -1,90 +0,0 @@
|
||||
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
// Date : Wed May 19 10:55:16 2021
|
||||
// Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_mig_7series_0_0_stub.v
|
||||
// Design : design_1_mig_7series_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tfgg484-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
|
||||
ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke,
|
||||
ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn,
|
||||
app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
|
||||
s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid,
|
||||
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen,
|
||||
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos,
|
||||
s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
|
||||
s_axi_rvalid, init_calib_complete, device_temp, sys_rst)
|
||||
/* synthesis syn_black_box black_box_pad_pin="ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst" */;
|
||||
inout [31:0]ddr3_dq;
|
||||
inout [3:0]ddr3_dqs_n;
|
||||
inout [3:0]ddr3_dqs_p;
|
||||
output [14:0]ddr3_addr;
|
||||
output [2:0]ddr3_ba;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_cas_n;
|
||||
output ddr3_we_n;
|
||||
output ddr3_reset_n;
|
||||
output [0:0]ddr3_ck_p;
|
||||
output [0:0]ddr3_ck_n;
|
||||
output [0:0]ddr3_cke;
|
||||
output [0:0]ddr3_cs_n;
|
||||
output [3:0]ddr3_dm;
|
||||
output [0:0]ddr3_odt;
|
||||
input sys_clk_i;
|
||||
output ui_clk;
|
||||
output ui_clk_sync_rst;
|
||||
output mmcm_locked;
|
||||
input aresetn;
|
||||
output app_sr_active;
|
||||
output app_ref_ack;
|
||||
output app_zq_ack;
|
||||
input [0:0]s_axi_awid;
|
||||
input [29:0]s_axi_awaddr;
|
||||
input [7:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [0:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [255:0]s_axi_wdata;
|
||||
input [31:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
input s_axi_bready;
|
||||
output [0:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input [0:0]s_axi_arid;
|
||||
input [29:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [0:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
input s_axi_rready;
|
||||
output [0:0]s_axi_rid;
|
||||
output [255:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
output init_calib_complete;
|
||||
output [11:0]device_temp;
|
||||
input sys_rst;
|
||||
endmodule
|
||||
@ -1,90 +0,0 @@
|
||||
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
-- Date : Wed May 19 10:55:16 2021
|
||||
-- Host : DESKTOP-J72MK93 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_mig_7series_0_0_stub.vhdl
|
||||
-- Design : design_1_mig_7series_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tfgg484-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
ddr3_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
ddr3_ras_n : out STD_LOGIC;
|
||||
ddr3_cas_n : out STD_LOGIC;
|
||||
ddr3_we_n : out STD_LOGIC;
|
||||
ddr3_reset_n : out STD_LOGIC;
|
||||
ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
ddr3_dm : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
sys_clk_i : in STD_LOGIC;
|
||||
ui_clk : out STD_LOGIC;
|
||||
ui_clk_sync_rst : out STD_LOGIC;
|
||||
mmcm_locked : out STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
app_sr_active : out STD_LOGIC;
|
||||
app_ref_ack : out STD_LOGIC;
|
||||
app_zq_ack : out STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
init_calib_complete : out STD_LOGIC;
|
||||
device_temp : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
sys_rst : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -1,80 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3538:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6366676d656d7061727463686f6f7365725f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3235:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:64657369676e74696d696e6773756d73656374696f6e70616e656c5f776f7273745f6e656761746976655f736c61636b:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e6d656e755f72657365745f616e645f67656e65726174655f6f75747075745f70726f6475637473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3932:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3732:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3537:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763746578746669656c645f76616c75655f6f665f7370656369666965645f706172616d65746572:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763746578746669656c645f76616c75655f6f665f7370656369666965645f706172616d657465725f6d616e75616c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636f6d6d616e64735f746f5f666f6c645f74657874:31:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f746f67676c655f626c6f636b5f636f6d6d656e7473:31:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3534:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d69676c6963656e7365706167655f616363657074:33:00:00
|
||||
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|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f696e666f726d6174696f6e5f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6176696761626c6574696d696e677265706f72747461625f74696d696e675f7265706f72745f6e617669676174696f6e5f74726565:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f636f6e6669675f6d656d6f7279:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f626f6f745f646576696365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f696d706c5f73657474696e6773:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f68617264776172655f6d616e61676572:36:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f70726f6772616d5f636f6e6669675f6d656d6f7279:3130:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f736176655f7273625f64657369676e:31:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f73797374656d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706174686d656e755f7365745f66616c73655f70617468:35:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706174686d656e755f7365745f6d756c74696379636c655f70617468:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d6366676d656d6469616c6f675f636f6e74656e74735f6f665f636f6e66696775726174696f6e5f66696c65:31:00:00
|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d6f7074696f6e7370616e656c696d706c5f7374726174656779:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:3135:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f70726f70657274696573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f72756e5f6761646765745f7461626265645f70616e65:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f7461626c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73656c6563746d656e755f686967686c69676874:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73656c6563746d656e755f6d61726b:33:00:00
|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c6465726d656e755f6164645f6970:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73797374656d6275696c646572766965775f6f7074696d697a655f726f7574696e67:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e676974656d666c61747461626c6570616e656c5f666c6f6f72706c616e6e696e67:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74696d696e676974656d666c61747461626c6570616e656c5f7461626c65:39:00:00
|
||||
eof:397969358
|
||||
@ -1,21 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646366676d656d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65727362626c6f636b:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d6366676d656d:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:726567656e65726174657273626c61796f7574:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3232:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766570726f6a6563746173:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766572736264657369676e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:76616c696461746572736264657369676e:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:3132:00:00
|
||||
eof:2166436748
|
||||
@ -1,4 +0,0 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:17
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:18
|
||||
eof:
|
||||
@ -1,40 +0,0 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761313030746667673438342d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:64736f5f746f70:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
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|
||||
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|
||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
|
||||
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|
||||
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|
||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
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|
||||
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|
||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
|
||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
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|
||||
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|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:34332e3030344d42:00:00
|
||||
eof:122310102
|
||||
@ -1,3 +0,0 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
|
||||
eof:2511430288
|
||||
@ -1,127 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Wed May 19 11:08:47 2021">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="22cd7da0d8814ac4ba10473639199647" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="22" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Flow_AreaOptimized_high" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Area_ExploreWithRemap" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddCfgMem" value="2" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="11" type="JavaHandler"/>
|
||||
<property name="CustomizeRSBBlock" value="31" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="6" type="JavaHandler"/>
|
||||
<property name="EditProperties" value="1" type="JavaHandler"/>
|
||||
<property name="FileExit" value="7" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="12" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="2" type="JavaHandler"/>
|
||||
<property name="ProgramCfgMem" value="12" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="2" type="JavaHandler"/>
|
||||
<property name="RegenerateRSBLayout" value="3" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="22" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="1" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="3" type="JavaHandler"/>
|
||||
<property name="SaveProjectAs" value="14" type="JavaHandler"/>
|
||||
<property name="SaveRSBDesign" value="2" type="JavaHandler"/>
|
||||
<property name="ToolsSettings" value="2" type="JavaHandler"/>
|
||||
<property name="ValidateRSBDesign" value="4" type="JavaHandler"/>
|
||||
<property name="ViewTaskProjectManager" value="12" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="58" type="GuiHandlerData"/>
|
||||
<property name="CfgMemPartChooser_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="25" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="DesignTimingSumSectionPanel_WORST_NEGATIVE_SLACK" value="2" type="GuiHandlerData"/>
|
||||
<property name="ExpRunMenu_RESET_AND_GENERATE_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="92" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="72" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="57" type="GuiHandlerData"/>
|
||||
<property name="HACGCTextField_VALUE_OF_SPECIFIED_PARAMETER" value="3" type="GuiHandlerData"/>
|
||||
<property name="HACGCTextField_VALUE_OF_SPECIFIED_PARAMETER_MANUAL" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="1" type="GuiHandlerData"/>
|
||||
<property name="HFolderChooserHelpers_UP_ONE_LEVEL" value="4" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_TOGGLE_BLOCK_COMMENTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="HJFileChooserRecentListPreview_RECENT_DIRECTORIES" value="1" type="GuiHandlerData"/>
|
||||
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="19" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_CHECKPOINT" value="7" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="54" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="23" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="40" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TEXT_EDITOR" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
|
||||
<property name="MigLicensePage_ACCEPT" value="3" type="GuiHandlerData"/>
|
||||
<property name="MigPinSelectionPage_VALIDATE" value="3" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_DISCARD_USER_CREATED_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="3" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="7" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CRITICAL_WARNINGS" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgView_INFORMATION_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_CONFIG_MEMORY" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_BOOT_DEVICE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_IMPL_SETTINGS" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="6" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_PROGRAM_CONFIG_MEMORY" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_REGENERATE_LAYOUT" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SAVE_PROJECT_AS" value="14" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SAVE_RSB_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_VALIDATE_RSB_DESIGN" value="4" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="20" type="GuiHandlerData"/>
|
||||
<property name="PAViews_SYSTEM" value="2" type="GuiHandlerData"/>
|
||||
<property name="PathMenu_SET_FALSE_PATH" value="5" type="GuiHandlerData"/>
|
||||
<property name="PathMenu_SET_MAXIMUM_DELAY" value="2" type="GuiHandlerData"/>
|
||||
<property name="PathMenu_SET_MULTICYCLE_PATH" value="5" type="GuiHandlerData"/>
|
||||
<property name="ProgramCfgMemDialog_CONTENTS_OF_CONFIGURATION_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgramDebugTab_OPEN_TARGET" value="12" type="GuiHandlerData"/>
|
||||
<property name="ProgramOptionsPanelImpl_STRATEGY" value="26" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_CANCEL" value="3" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="14" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="15" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="6" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_PROPERTIES" value="1" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_RUN_GADGET_TABBED_PANE" value="5" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="15" type="GuiHandlerData"/>
|
||||
<property name="SelectMenu_HIGHLIGHT" value="2" type="GuiHandlerData"/>
|
||||
<property name="SelectMenu_MARK" value="3" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/>
|
||||
<property name="SystemBuilderMenu_ADD_IP" value="2" type="GuiHandlerData"/>
|
||||
<property name="SystemBuilderView_OPTIMIZE_ROUTING" value="3" type="GuiHandlerData"/>
|
||||
<property name="TimingItemFlatTablePanel_FLOORPLANNING" value="2" type="GuiHandlerData"/>
|
||||
<property name="TimingItemFlatTablePanel_TABLE" value="9" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="70" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="62" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
@ -1,8 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2020.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0">
|
||||
<HWSession Dir="hw_1" File="hw.xml"/>
|
||||
</labtools>
|
||||
@ -1,696 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2020.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<hwsession version="1" minor="2">
|
||||
<device name="xc7a100t_0" gui_info="dashboard1=hw_ila_1[xc7a100t_0/hw_ila_1/Settings=ILA_SETTINGS_1;xc7a100t_0/hw_ila_1/Trigger Setup=ILA_TRIGGER_1;xc7a100t_0/hw_ila_1/Capture Setup=ILA_CAPTURE_1;xc7a100t_0/hw_ila_1/Status=ILA_STATUS_1;xc7a100t_0/hw_ila_1/Waveform=ILA_WAVE_1;]"/>
|
||||
<ObjectList object_type="hw_cfgmem" gui_info="">
|
||||
<Object name="" gui_info="">
|
||||
<Properties Property="PROGRAM.ADDRESS_RANGE" value="use_file"/>
|
||||
<Properties Property="PROGRAM.BLANK_CHECK" value="0"/>
|
||||
<Properties Property="PROGRAM.CFG_PROGRAM" value="1"/>
|
||||
<Properties Property="PROGRAM.CHECKSUM" value="0"/>
|
||||
<Properties Property="PROGRAM.ERASE" value="1"/>
|
||||
<Properties Property="PROGRAM.FILES" value="$_project_name_.runs/impl_1/$_project_name_.bin"/>
|
||||
<Properties Property="PROGRAM.PRM_FILE" value=""/>
|
||||
<Properties Property="PROGRAM.UNUSED_PIN_TERMINATION" value="pull-none"/>
|
||||
<Properties Property="PROGRAM.VERIFY" value="1"/>
|
||||
</Object>
|
||||
</ObjectList>
|
||||
<ObjectList object_type="hw_device" gui_info="">
|
||||
<Object name="xc7a100t_0" gui_info="">
|
||||
<Properties Property="FULL_PROBES.FILE" value=""/>
|
||||
<Properties Property="PROBES.FILE" value=""/>
|
||||
<Properties Property="PROGRAM.HW_BITSTREAM" value=""/>
|
||||
<Properties Property="PROGRAM.HW_CFGMEM_PART" value="s25fl256sxxxxxx0-spi-x1_x2_x4"/>
|
||||
<Properties Property="SLR.COUNT" value="1"/>
|
||||
</Object>
|
||||
</ObjectList>
|
||||
<ObjectList object_type="hw_ila" gui_info="">
|
||||
<Object name="" gui_info="">
|
||||
<Properties Property="CONTROL.TRIGGER_CONDITION" value="AND"/>
|
||||
<Properties Property="CORE_REFRESH_RATE_MS" value="500"/>
|
||||
</Object>
|
||||
<Object name="design_1_i/ila_0" gui_info="">
|
||||
<Properties Property="CONTROL.DATA_DEPTH" value="1024"/>
|
||||
<Properties Property="CONTROL.TRIGGER_CONDITION" value="AND"/>
|
||||
<Properties Property="CONTROL.TRIGGER_POSITION" value="0"/>
|
||||
<Properties Property="CONTROL.WINDOW_COUNT" value="1"/>
|
||||
<Properties Property="CORE_REFRESH_RATE_MS" value="500"/>
|
||||
</Object>
|
||||
</ObjectList>
|
||||
<ObjectList object_type="hw_probe" gui_info="">
|
||||
<Object name="design_1_i/S_AXIS_S2MM_0_1_TDATA[127:0]" gui_info=""/>
|
||||
<Object name="design_1_i/S_AXIS_S2MM_0_1_TLAST" gui_info=""/>
|
||||
<Object name="design_1_i/S_AXIS_S2MM_0_1_TREADY" gui_info="Trigger Setup=0"/>
|
||||
</ObjectList>
|
||||
<probeset name="hw project" active="false">
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe8[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const0>"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe5[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const0>_1"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe7[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const0>_2"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[15]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_1"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[9]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_10"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[10]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_11"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[11]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_12"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[12]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_13"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[13]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_14"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[14]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_15"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[1]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_2"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[2]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_3"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[3]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_4"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[4]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_5"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[5]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_6"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[6]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_7"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[7]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_8"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe2[8]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/<const1>_9"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq128'hXXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq128'hXXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe1[127:0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq128'hXXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX_XXXX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[127]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[126]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[125]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[124]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[123]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[122]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[121]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[120]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[119]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[118]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[117]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[116]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[115]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[114]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[113]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[112]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[111]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[110]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[109]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[108]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[107]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[106]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[105]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[104]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[103]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[102]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[101]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[100]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[99]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[98]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[97]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[96]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[95]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[94]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[93]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[92]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[91]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[90]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[89]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[88]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[87]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[86]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[85]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[84]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[83]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[82]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[81]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[80]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[79]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[78]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[77]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[76]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[75]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[74]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[73]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[72]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[71]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[70]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[69]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[68]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[67]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[66]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[65]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[64]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[63]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[62]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[61]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[60]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[59]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[58]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[57]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[56]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[55]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[54]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[53]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[52]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[51]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[50]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[49]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[48]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[47]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[46]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[45]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[44]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[43]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[42]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[41]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[40]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[39]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[38]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[37]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[36]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[35]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[34]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[33]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[32]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[31]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[30]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[29]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[28]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[27]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[26]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[25]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[24]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[23]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[22]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[21]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[20]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[19]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[18]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[17]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[16]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[15]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[14]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[13]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[12]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[11]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[10]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[9]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[8]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[7]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[6]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[5]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[4]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[3]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[2]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[1]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TDATA[0]"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq16'hXXXX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq16'hXXXX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe6[15:0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq16'hXXXX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[15]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[14]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[13]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[12]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[11]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[10]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[9]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[8]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[7]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[6]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[5]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[4]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[3]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[2]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[1]"/>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TKEEP[0]"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe4[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TLAST"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bR"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe0[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bR"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TREADY"/>
|
||||
</nets>
|
||||
</probe>
|
||||
<probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
|
||||
<probeOptions Id="DebugProbeParams">
|
||||
<Option Id="CAPTURE_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="COMPARE_VALUE.0" value="eq1'bX"/>
|
||||
<Option Id="DISPLAY_AS_ENUM" value="1"/>
|
||||
<Option Id="DISPLAY_HINT" value=""/>
|
||||
<Option Id="DISPLAY_RADIX" value="HEX"/>
|
||||
<Option Id="DISPLAY_VISIBILITY" value=""/>
|
||||
<Option Id="HW_ILA" value="hw_ila_1"/>
|
||||
<Option Id="LINK_TO_WAVEFORM" value="1"/>
|
||||
<Option Id="MAP" value="probe3[0]"/>
|
||||
<Option Id="NAME.CUSTOM" value=""/>
|
||||
<Option Id="NAME.SELECT" value="Long"/>
|
||||
<Option Id="SOURCE" value="netlist"/>
|
||||
<Option Id="TRIGGER_COMPARE_VALUE" value="eq1'bX"/>
|
||||
<Option Id="WAVEFORM_STYLE" value="Digital"/>
|
||||
</probeOptions>
|
||||
<nets>
|
||||
<net name="design_1_i/S_AXIS_S2MM_0_1_TVALID"/>
|
||||
</nets>
|
||||
</probe>
|
||||
</probeset>
|
||||
</hwsession>
|
||||
@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2020.1 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat May 15 20:18:01 -0400 2021
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./clk_wiz_0.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './clk_wiz_0.sh' script.
|
||||
|
||||
./clk_wiz_0.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./clk_wiz_0.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './clk_wiz_0.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2020.1 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat May 15 20:18:01 -0400 2021
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./clk_wiz_0.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './clk_wiz_0.sh' script.
|
||||
|
||||
./clk_wiz_0.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./clk_wiz_0.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './clk_wiz_0.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
@ -1,2 +0,0 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
@ -1,2 +0,0 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
@ -1,179 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project NoOfControllers="1">
|
||||
|
||||
|
||||
|
||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||
|
||||
<ModuleName>design_1_mig_7series_0_0</ModuleName>
|
||||
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
|
||||
<dci_inputs>1</dci_inputs>
|
||||
|
||||
<Debug_En>OFF</Debug_En>
|
||||
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
|
||||
<LowPower_En>OFF</LowPower_En>
|
||||
|
||||
<XADC_En>Enabled</XADC_En>
|
||||
|
||||
<TargetFPGA>xc7a100t-fgg484/-2</TargetFPGA>
|
||||
|
||||
<Version>4.2</Version>
|
||||
|
||||
<SystemClock>No Buffer</SystemClock>
|
||||
|
||||
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||
|
||||
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
|
||||
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
|
||||
<InternalVref>0</InternalVref>
|
||||
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
|
||||
<dci_cascade>0</dci_cascade>
|
||||
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
|
||||
<TimePeriod>2500</TimePeriod>
|
||||
<VccAuxIO>1.8V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>200</InputClkFreq>
|
||||
<UIExtraClocks>0</UIExtraClocks>
|
||||
<MMCM_VCO>800</MMCM_VCO>
|
||||
<MMCMClkOut0> 1.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>32</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Normal</Ordering>
|
||||
<BankMachineCnt>8</BankMachineCnt>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName/>
|
||||
<RowAddress>15</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||
<C0_MEM_SIZE>1073741824</C0_MEM_SIZE>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="J1" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K2" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M5" SLEW="" VCCAUX_IO="" name="ddr3_addr[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P6" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="N3" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="G1" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="J5" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="H5" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="H2" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="P1" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K1" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W2" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y7" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_dm[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_dm[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB7" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y9" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB6" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W9" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB5" SLEW="" VCCAUX_IO="" name="ddr3_dq[16]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AA5" SLEW="" VCCAUX_IO="" name="ddr3_dq[17]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB3" SLEW="" VCCAUX_IO="" name="ddr3_dq[18]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W4" SLEW="" VCCAUX_IO="" name="ddr3_dq[19]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="W1" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB2" SLEW="" VCCAUX_IO="" name="ddr3_dq[20]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y4" SLEW="" VCCAUX_IO="" name="ddr3_dq[21]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB1" SLEW="" VCCAUX_IO="" name="ddr3_dq[22]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AA1" SLEW="" VCCAUX_IO="" name="ddr3_dq[23]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_dq[24]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y6" SLEW="" VCCAUX_IO="" name="ddr3_dq[25]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_dq[26]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_dq[27]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_dq[28]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AA6" SLEW="" VCCAUX_IO="" name="ddr3_dq[29]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T4" SLEW="" VCCAUX_IO="" name="ddr3_dq[30]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U5" SLEW="" VCCAUX_IO="" name="ddr3_dq[31]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y2" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y1" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="Y8" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="V8" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="AA3" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="W5" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="Y3" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="W6" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS15" PADName="H3" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="J2" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
|
||||
</PinSelection>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters tcke="5" tfaw="40" tras="35" trcd="13.75" trefi="7.8" trfc="260" trp="13.75" trrd="7.5" trtp="7.5" twtr="7.5"/>
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">6</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/4</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG_STARVE_LIMIT</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
|
||||
</Project>
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user