Organizing Firmware Folder

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.1 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Sat Nov 27 13:18:12 -0500 2021
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./clk_wiz_0.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './clk_wiz_0.sh' script.
-
-./clk_wiz_0.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./clk_wiz_0.sh -noclean_files
-
-For more information on the script, please type './clk_wiz_0.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.1 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Sat Nov 27 13:18:12 -0500 2021
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./clk_wiz_0.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './clk_wiz_0.sh' script.
-
-./clk_wiz_0.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./clk_wiz_0.sh -noclean_files
-
-For more information on the script, please type './clk_wiz_0.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/activehdl/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/modelsim/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/questa/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/riviera/file_info.txt

@@ -1,17 +0,0 @@
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-glbl.v,Verilog,xil_defaultlib,glbl.v

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/riviera/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/vcs/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.1 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Sat Nov 27 13:14:40 -0500 2021
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./design_1.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './design_1.sh' script.
-
-./design_1.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./design_1.sh -noclean_files
-
-For more information on the script, please type './design_1.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/vcs/file_info.txt

@@ -1,17 +0,0 @@
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-glbl.v,Verilog,xil_defaultlib,glbl.v

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/xcelium/file_info.txt

@@ -1,17 +0,0 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
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-design_1_mig_7series_0_0_sim_netlist.v,verilog,xil_defaultlib,c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0_sim_netlist.v,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-design_1_clk_wiz_0_0_sim_netlist.v,verilog,xil_defaultlib,c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_sim_netlist.v,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
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-design_1_axi_gpio_0_1_sim_netlist.v,verilog,xil_defaultlib,c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1_sim_netlist.v,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-design_1_axi_fifo_mm_s_0_0_sim_netlist.v,verilog,xil_defaultlib,c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0_sim_netlist.v,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
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-design_1_axi_crossbar_0_0_sim_netlist.v,verilog,xil_defaultlib,c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0_sim_netlist.v,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-design_1_axi_crossbar_0_1_sim_netlist.v,verilog,xil_defaultlib,c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1_sim_netlist.v,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-design_1_axi_clock_converter_0_0_sim_netlist.v,verilog,xil_defaultlib,c:/Users/Aleksa/Documents/FPGA_Dev/Artix7_PCIe/DDR3_Optimization/dso_top/dso_top.srcs/sources_1/bd/design_1/ip/design_1_axi_clock_converter_0_0/design_1_axi_clock_converter_0_0_sim_netlist.v,incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/b8f8/hdl/verilog"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/8b3d"incdir="../../../../dso_top.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/design_1/xsim/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.1 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Sat Nov 27 13:14:40 -0500 2021
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./design_1.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './design_1.sh' script.
-
-./design_1.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./design_1.sh -noclean_files
-
-For more information on the script, please type './design_1.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/activehdl/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/modelsim/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/questa/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/riviera/file_info.txt

@@ -1,18 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_if.sv,
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/clk_vip_if.sv,
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/rst_vip_if.sv,
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_VCOMP.vhd,
-fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
-fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
-fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
-fifo_generator_0.v,verilog,xil_defaultlib,../../../../dso_top.srcs/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/riviera/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/vcs/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.1 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Sat Nov 27 13:18:47 -0500 2021
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./fifo_generator_0.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './fifo_generator_0.sh' script.
-
-./fifo_generator_0.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./fifo_generator_0.sh -noclean_files
-
-For more information on the script, please type './fifo_generator_0.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/vcs/file_info.txt

@@ -1,18 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_if.sv,
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/clk_vip_if.sv,
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/rst_vip_if.sv,
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_VCOMP.vhd,
-fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
-fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
-fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
-fifo_generator_0.v,verilog,xil_defaultlib,../../../../dso_top.srcs/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/xcelium/file_info.txt

@@ -1,18 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_if.sv,
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/clk_vip_if.sv,
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/rst_vip_if.sv,
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_fifo.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../Xilinx/Vivado/2020.1/data/ip/xpm/xpm_VCOMP.vhd,
-fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
-fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
-fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_5,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
-fifo_generator_0.v,verilog,xil_defaultlib,../../../../dso_top.srcs/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

Firmware/Artix7_PCIe/dso_top/dso_top.ip_user_files/sim_scripts/fifo_generator_0/xsim/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.1 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Sat Nov 27 13:18:47 -0500 2021
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./fifo_generator_0.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './fifo_generator_0.sh' script.
-
-./fifo_generator_0.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./fifo_generator_0.sh -noclean_files
-
-For more information on the script, please type './fifo_generator_0.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

Firmware/Artix7_PCIe/dso_top_TE0712/dso_top.ip_user_files/README.txt

@@ -1 +1 @@
-The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

Firmware/Artix7_PCIe/dso_top_TE0712/dso_top.ip_user_files/bd/design_1/ip/design_1_auto_cc_0/sim/design_1_auto_cc_0.v

@@ -0,0 +1,428 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
+// IP Revision: 20
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_auto_cc_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_aclk,
+  m_axi_aresetn,
+  m_axi_awid,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bid,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_arid,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rid,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [0 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [29 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [255 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [31 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [0 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [0 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [29 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [0 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [255 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
+HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
+input wire m_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
+input wire m_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
+output wire [0 : 0] m_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [29 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [255 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [31 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
+input wire [0 : 0] m_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
+output wire [0 : 0] m_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [29 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
+input wire [0 : 0] m_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [255 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 30, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0, CLK_DOMAIN design_1_mig_7series_0_0_ui_clk, NUM_READ_THREADS 1, NUM_WRITE_\
+THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_clock_converter_v2_1_20_axi_clock_converter #(
+    .C_FAMILY("artix7"),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(30),
+    .C_AXI_DATA_WIDTH(256),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(1),
+    .C_AXI_PROTOCOL(0),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(m_axi_aclk),
+    .m_axi_aresetn(m_axi_aresetn),
+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule

Firmware/Artix7_PCIe/dso_top_TE0712/dso_top.ip_user_files/bd/design_1/ip/design_1_auto_us_df_0/sim/design_1_auto_us_df_0.v

@@ -0,0 +1,391 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 21
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_auto_us_df_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [3 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [63 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [3 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [3 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [63 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [3 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 32, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE\
+_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [63 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [255 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [31 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [63 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [255 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 4, NUM_WRITE_OUTSTANDING 4, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
+HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_21_top #(
+    .C_FAMILY("artix7"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(4),
+    .C_SUPPORTS_ID(1),
+    .C_AXI_ADDR_WIDTH(64),
+    .C_S_AXI_DATA_WIDTH(128),
+    .C_M_AXI_DATA_WIDTH(256),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(1),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule

Firmware/Artix7_PCIe/dso_top_TE0712/dso_top.ip_user_files/bd/design_1/ip/design_1_auto_us_df_1/sim/design_1_auto_us_df_1.v

@@ -0,0 +1,289 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 21
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module design_1_auto_us_df_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [3 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [3 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
+HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [255 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [31 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_T\
+HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+
+  axi_dwidth_converter_v2_1_21_top #(
+    .C_FAMILY("artix7"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(4),
+    .C_SUPPORTS_ID(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(128),
+    .C_M_AXI_DATA_WIDTH(256),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(0),
+    .C_FIFO_MODE(1),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(4'H0),
+    .s_axi_araddr(32'H00000000),
+    .s_axi_arlen(8'H00),
+    .s_axi_arsize(3'H0),
+    .s_axi_arburst(2'H1),
+    .s_axi_arlock(1'H0),
+    .s_axi_arcache(4'H0),
+    .s_axi_arprot(3'H0),
+    .s_axi_arregion(4'H0),
+    .s_axi_arqos(4'H0),
+    .s_axi_arvalid(1'H0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'H0),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'H0),
+    .m_axi_rdata(256'H0000000000000000000000000000000000000000000000000000000000000000),
+    .m_axi_rresp(2'H0),
+    .m_axi_rlast(1'H1),
+    .m_axi_rvalid(1'H0),
+    .m_axi_rready()
+  );
+endmodule