AllSpiceMirrors/ThunderScope
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Beta 2 gateware release

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This commit is contained in:
Aleksa Bjelogrlic 2024-05-11 16:03:37 -04:00
parent 3fc00220a2
commit a384d5a43c
78 changed files with 805263 additions and 2858 deletions
Firmware/XDMA
.gitignore
bd
top_bd_100t.tcltop_bd_200t.tcltop_bd_50t.tcl
cfg
timer1_50t.bintimer2_50t.bin
hdl
100t_200t
dso_top.v
35t_50t
dso_top.v
adc_to_datamover.v
multiboot_address_table
multiboot_address_table.tclreadme.txt
output
README.md
xci
100t
clk_wiz_0.xcixfifo_generator_0.xci
fifo_generator_0
doc
fifo_generator_v13_2_changelog.txt
fifo_generator_0.dcpfifo_generator_0.veofifo_generator_0.vhofifo_generator_0.xcififo_generator_0.xdcfifo_generator_0.xmlfifo_generator_0_clocks.xdcfifo_generator_0_ooc.xdcfifo_generator_0_sim_netlist.vfifo_generator_0_sim_netlist.vhdlfifo_generator_0_stub.vfifo_generator_0_stub.vhdl
hdl
blk_mem_gen_v8_4_vhsyn_rfs.vhdfifo_generator_v13_2_rfs.vfifo_generator_v13_2_rfs.vhdfifo_generator_v13_2_vhsyn_rfs.vhd
sim
fifo_generator_0.v
simulation
fifo_generator_vlog_beh.v
synth
fifo_generator_0.vhd
mig_a.prj
200t
clk_wiz_0.xcixfifo_generator_0.xci
fifo_generator_0
fifo_generator_0.dcpfifo_generator_0.veofifo_generator_0.vhofifo_generator_0.xcififo_generator_0.xdcfifo_generator_0.xmlfifo_generator_0_clocks.xdcfifo_generator_0_ooc.xdcfifo_generator_0_sim_netlist.vfifo_generator_0_sim_netlist.vhdlfifo_generator_0_stub.vfifo_generator_0_stub.vhdl
hdl
blk_mem_gen_v8_4_vhsyn_rfs.vhdfifo_generator_v13_2_vhsyn_rfs.vhd
synth
fifo_generator_0.vhd
mig_a.prj
50t
clk_wiz_0.xcixfifo_generator_0.xci
fifo_generator_0
fifo_generator_0.dcpfifo_generator_0.veofifo_generator_0.vhofifo_generator_0.xcififo_generator_0.xdcfifo_generator_0.xmlfifo_generator_0_clocks.xdcfifo_generator_0_ooc.xdcfifo_generator_0_sim_netlist.vfifo_generator_0_sim_netlist.vhdlfifo_generator_0_stub.vfifo_generator_0_stub.vhdl
hdl
blk_mem_gen_v8_4_vhsyn_rfs.vhdfifo_generator_v13_2_vhsyn_rfs.vhd
synth
fifo_generator_0.vhd
mig_a.prj
xdc
35t_50t
module_bitgen.xdcmodule_io.xdctiming.xdc
module_bitgen.xdcmodule_io.xdctiming.xdc
xdma_gen.tcl

3
Firmware/XDMA/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
xdma_prj_50t/
xdma_prj_100t/
xdma_prj_200t/

1517
Firmware/XDMA/bd/top_bd_100t.tcl Normal file
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File diff suppressed because it is too large Load Diff

1967
Firmware/XDMA/bd/top_bd.tcl → Firmware/XDMA/bd/top_bd_200t.tcl
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File diff suppressed because it is too large Load Diff

1501
Firmware/XDMA/bd/top_bd_50t.tcl Normal file
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File diff suppressed because it is too large Load Diff

BIN
Firmware/XDMA/cfg/timer1_50t.bin Normal file
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Binary file not shown.

BIN
Firmware/XDMA/cfg/timer2_50t.bin Normal file
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Binary file not shown.

33
Firmware/XDMA/hdl/100t_200t/dso_top.v
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@ -50,7 +50,10 @@ module dso_top
inout qspi_d1,
inout qspi_d2,
inout qspi_d3,
output qspi_cs
output qspi_cs,
output eth_rst_n,
input ext_clk_p,
input ext_clk_n
);
wire [31:0]AXI_STR_TXD_0_tdata;
@ -102,12 +105,17 @@ module dso_top
wire spi_rtl_0_io3_io;
wire spi_rtl_0_io3_o;
wire spi_rtl_0_io3_t;
wire ss_o_0;
wire init_calib_complete_0;
assign eth_rst_n = 0;
assign term = gpio_io_o_0[15:12];
assign atten = gpio_io_o_0[19:16];
assign dc_cpl = gpio_io_o_0[23:20];
assign dc_cpl = ~gpio_io_o_0[23:20];
assign led = ~serdes_ready;
assign led = ~(serdes_ready & init_calib_complete_0);
//assign sync = S01_ARESETN;
assign acq_en = gpio_io_o_0[24];
@ -117,6 +125,8 @@ module dso_top
assign i2c_sda = (i2c_sda_buf) ? (1'bz) : (1'b0);
assign i2c_scl = (i2c_scl_buf) ? (1'bz) : (1'b0);
assign qspi_cs = (ss_o_0) ? (1'bz) : (1'b0);
reg[15:0] sync_counter;
reg sync_clk = 1'b0;
always @ (posedge divclk) begin
@ -197,6 +207,13 @@ module dso_top
always @(posedge divclk)
serdes_rst_cdc <= { serdes_rst_cdc[1:0], !S01_ARESETN };
assign serdes_rst = serdes_rst_cdc[2];
wire ddr_ready;
reg [2:0] ddr_ready_cdc = 3'b000;
always @(posedge divclk)
ddr_ready_cdc <= { ddr_ready_cdc[1:0], init_calib_complete_0};
assign ddr_ready = ddr_ready_cdc[2];
serdes serdes (
.rst (serdes_rst),
@ -230,7 +247,8 @@ module dso_top
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
.gpio_io_o_0(gpio_io_o_0),
.gpio2_io_i(gpio2_io_i),
.serdes_ready (serdes_ready)
.serdes_ready (serdes_ready),
.ddr_ready(ddr_ready)
);
serial_controller serial_controller(
@ -305,8 +323,11 @@ module dso_top
.SPI_0_0_io3_i(spi_rtl_0_io3_i),
.SPI_0_0_io3_o(spi_rtl_0_io3_o),
.SPI_0_0_io3_t(spi_rtl_0_io3_t),
.SPI_0_0_ss_t(1'b0),
.ss_o_0(qspi_cs)
.SPI_0_0_ss_t(),
.ss_o_0(ss_o_0),
.init_calib_complete_0(init_calib_complete_0),
.ext_clk_p(ext_clk_p),
.ext_clk_n(ext_clk_n)
);
IOBUF spi_rtl_0_io0_iobuf

27
Firmware/XDMA/hdl/35t_50t/dso_top.v
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@ -50,7 +50,8 @@ module dso_top
inout qspi_d1,
inout qspi_d2,
inout qspi_d3,
output qspi_cs
output qspi_cs,
input ext_clk
);
wire [31:0]AXI_STR_TXD_0_tdata;
@ -102,12 +103,15 @@ module dso_top
wire spi_rtl_0_io3_io;
wire spi_rtl_0_io3_o;
wire spi_rtl_0_io3_t;
wire ss_o_0;
wire init_calib_complete_0;
assign term = gpio_io_o_0[15:12];
assign atten = gpio_io_o_0[19:16];
assign dc_cpl = gpio_io_o_0[23:20];
assign dc_cpl = ~gpio_io_o_0[23:20];
assign led = ~serdes_ready;
assign led = serdes_ready & init_calib_complete_0;
//assign sync = S01_ARESETN;
assign acq_en = gpio_io_o_0[24];
@ -116,6 +120,8 @@ module dso_top
assign i2c_sda = (i2c_sda_buf) ? (1'bz) : (1'b0);
assign i2c_scl = (i2c_scl_buf) ? (1'bz) : (1'b0);
assign qspi_cs = (ss_o_0) ? (1'bz) : (1'b0);
reg[15:0] sync_counter;
reg sync_clk = 1'b0;
@ -198,6 +204,12 @@ module dso_top
serdes_rst_cdc <= { serdes_rst_cdc[1:0], !S01_ARESETN };
assign serdes_rst = serdes_rst_cdc[2];
wire ddr_ready;
reg [2:0] ddr_ready_cdc = 3'b000;
always @(posedge divclk)
ddr_ready_cdc <= { ddr_ready_cdc[1:0], init_calib_complete_0};
assign ddr_ready = ddr_ready_cdc[2];
serdes serdes (
.rst (serdes_rst),
.adc_lclk_p (adc_lclk_p),
@ -230,7 +242,8 @@ module dso_top
.s2mm_wr_xfer_cmplt(s2mm_wr_xfer_cmplt),
.gpio_io_o_0(gpio_io_o_0),
.gpio2_io_i(gpio2_io_i),
.serdes_ready (serdes_ready)
.serdes_ready (serdes_ready),
.ddr_ready(ddr_ready)
);
serial_controller serial_controller(
@ -305,8 +318,10 @@ module dso_top
.SPI_0_0_io3_i(spi_rtl_0_io3_i),
.SPI_0_0_io3_o(spi_rtl_0_io3_o),
.SPI_0_0_io3_t(spi_rtl_0_io3_t),
.SPI_0_0_ss_t(1'b0),
.ss_o_0(qspi_cs)
.SPI_0_0_ss_t(),
.ss_o_0(ss_o_0),
.init_calib_complete_0(init_calib_complete_0),
.ext_clk(ext_clk)
);
IOBUF spi_rtl_0_io0_iobuf

5
Firmware/XDMA/hdl/adc_to_datamover.v
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@ -18,7 +18,8 @@ module adc_to_datamover(
input s2mm_wr_xfer_cmplt,
input[31:0] gpio_io_o_0,
output[31:0] gpio2_io_i,
input serdes_ready
input serdes_ready,
input ddr_ready
);
wire fifo_full;
@ -115,7 +116,7 @@ module adc_to_datamover(
.wr_clk(adc_divclk),
.rd_clk(axi_aclk),
.din(adc_data),
.wr_en(serdes_ready), //add a state machine to deal with fifo full
.wr_en(serdes_ready & ddr_ready), //add a state machine to deal with fifo full
.rd_en(fifo_rd_en),
.dout(fifo_data),
.full(fifo_full),

603
Firmware/XDMA/multiboot_address_table/multiboot_address_table.tcl Normal file
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@ -0,0 +1,603 @@
#!/usr/bin/env tclsh
# Generate a Multiboot address table
#
# Inputs:
# - bitstream size
# - flash type
# - configuration data width
# - frequency (MHz)
# - flash density (Mbit)
#
# Assumptions:
# - The special configuration startup condition DCI_WAIT is assumed to be
# required and is included by default. This can be a significant factor
# in the spaceing between images, especially in smaller flash devices.
# This can be disable in the call to the NextBitstreamAddress procedure
# if you are confident that DCI_WAIT is not required in your design.
# If disabled, a small wait for PLL startup will be used instead.
# However, this cannot be disabled in the current design but the extra
# spacing required is small and likely not significant even in the
# smallest flash devices.
# - Using a sector size of 256 kB (smaller sectors will align)
# - timer image size = 1 kB
# - Only SPI and BPIx16 is supported (BPIx8 support not tested)
#
# TODO: Verify write_cfgmem settings and XDC contraints output
# Possible features:
# - Add a list of FPGA bitstream sizes
# - Automatically search for a bin file and get its size
# - Change verbose-ness so that it can be piped with other commands
# better (For example, it should be able to be output only the
# write_cfgmem command to stdout)
## Globals ##
set INSTRUCTIONS "
Usage: [info script]
This Tcl script calculates the multiboot address maps for using
timer barrier images for Multi-boot 7 series designs.
See XAPP1246 or XAPP1247 for more information
Usage:
Interactive mode:
[info script]
Interactive mode with given bitstream size in bytes:
[info script] <bitstream_size>
Batch mode (all arguments are required in the given order):
[info script] <flash_type> <data_width> <freq_mhz> <flash_size_mbit> <bitstream_size>
<flash_type> : Flash type: spi, bpi
<data_width> : Flash data width: 1, 2, 4, 8, 16
<freq_mhz> : Frequency of CCLK (enter highest frequency used)
<flash_size_mbit> : Size of flash device in Mbit (ex: 128, 256, 512, 1024)
<bitstream_size> : Size of bitstream in bytes. Get this from UG470 or
UG570. If compression is enabled and reading this
directly form the bitstream file itself, be aware that
subsequent builds can vary significantly in size and
this script will need to be re-run.
Interactive mode instructions:
- Select the parameters when prompted
- The first item listed is the default
- An empty answer will select the default
- Unless passed as the only command line argument, the
bitstream length defaults to 0.
"
## Option ranges and default values
# To change a default value, make it the first value in the list
set FLASH_TYPES [list spi bpi]
set FLASH_WIDTH [list 4 1 2 8 16]
set FREQ_MHZ_RANGE [list 100 3 150]
set FLASH_DENSITIES [list 256 32 64 128 512 1024 2048 4096 8192]
# Very rough ranges on valid bitstream sizes in bytes
set MIN_BIT_SIZE 131072 ; # 1 Mbit (in bytes)
set MAX_BIT_SIZE 536870912 ; # 4 Gbit (in bytes)
set BIT_SIZE_RANGE [list 0 $MIN_BIT_SIZE $MAX_BIT_SIZE]
# hexpr --
#
# Arguments:
# args: values to return formatted as hexidecimal
# All values are passed along to expr
#
# Results:
proc hexpr args {
uplevel "format \"0x%08X\" \"[expr $args] \""
}
# PromptForOption --
#
# Arguments:
# prompt: text to display to at prompt
# values: list of values to display and select from
# range: if this is true, treat values as a list of three integers:
# 0 - default
# 1 - minumum value
# 2 - maximum value
#
# Results: A valid response is returned from values
proc PromptForOption {prompt values {range 0}} {
while {1} {
puts -nonewline "${prompt} ( "
foreach i $values {
puts -nonewline "$i "
}
puts -nonewline ") : "
flush stdout;
if {[gets stdin line] < 0 && [eof stdin]} {
return -code error "end of file detected"
} elseif {[string length [string trim $line]] < 1} {
return [lindex $values 0]
} else {
if {$range} {
scan $line "%d" freq
if {$freq > [lindex $values 1] && $freq < [lindex $values 2]} {
return $freq
}
} else {
set value [string tolower [string trim $line]]
if {[lsearch $values $value] >= 0} {
return $value
}
}
}
puts "$line not recognized"
}
# shouldn't get here
error -code error "Failed to get a valid option"
}
# InteractiveMode --
#
# Arguments:
# bits: Optional size of bitstream (will be prompted otherwize)
#
# Results: A valid response is returned from values
proc InteractiveMode {{bits 0}} {
global INSTRUCTIONS
global FLASH_TYPES
global FLASH_WIDTH
global FREQ_MHZ_RANGE
global FLASH_DENSITIES
global BIT_SIZE_RANGE
set options {}
puts "$INSTRUCTIONS"
puts "Entering interactive mode\n"
set prompt "Enter flash type: "
lappend options [PromptForOption $prompt $FLASH_TYPES]
set prompt "Enter flash width (bits): "
lappend options [PromptForOption $prompt $FLASH_WIDTH]
set prompt "Enter CCLK frequency (MHz): "
lappend options [PromptForOption $prompt $FREQ_MHZ_RANGE 1]
set prompt "Enter Flash density in Mbit (2^20 bits):\n "
lappend options [PromptForOption $prompt $FLASH_DENSITIES]
if {$bits == 0} {
set prompt "Enter bitstream size in bytes:\n "
set size [PromptForOption $prompt $BIT_SIZE_RANGE 1]
while {$size == 0} {
puts "No default bitstream size available, please enter \
correct bitstream size"
set size [PromptForOption $prompt $BIT_SIZE_RANGE 1]
}
lappend options $size
} else {
lappend options $bits
}
return $options
}
# GetOptions --
#
# Arguments:
#
# Results: Interactive mode is run or command line arguments are processed for
# valid values
proc GetOptions {argc argv} {
global INSTRUCTIONS
global MIN_BIT_SIZE
global MAX_BIT_SIZE
if { $argc == 1 } {
if {![scan [lindex $argv 0] "%d" bit_size_bytes]} {
puts "Single argument must be an integer"
puts $INSTRUCTIONS
return -1
}
if { $bit_size_bytes < $MIN_BIT_SIZE || \
$bit_size_bytes > $MAX_BIT_SIZE } {
puts "\"[lindex $argv 0]\" is not a valid bitstream size"
puts "Expecting between $MIN_BIT_SIZE and $MAX_BIT_SIZE bytes"
puts $INSTRUCTIONS
return -1
} else {
set options [InteractiveMode $bit_size_bytes]
}
} elseif { $argc == 5 } {
set options {}
scan [lindex $argv 0] "%s" flash_type
scan [lindex $argv 1] "%d" data_width
scan [lindex $argv 2] "%d" freq_mhz
scan [lindex $argv 3] "%d" flash_size_mbit
scan [lindex $argv 4] "%d" bit_size_bytes
lappend options $flash_type
lappend options $data_width
lappend options $freq_mhz
lappend options $flash_size_mbit
lappend options $bit_size_bytes
} elseif { $argc == 0 } {
set options [InteractiveMode]
} else {
puts "Unrecognized argument list: $argv"
puts $INSTRUCTIONS
return -1
}
# puts "DEBUG(GetOptions): Options: $options"
return $options
}
# NextBitstreamAddress --
#
# Calculate the address for the next bitstream. There is a minimum buffer
# requirement between bitstreams as certain startup conditions can delay
# configuration. If a following bitstream inserts new configuration commands,
# it could cause a configuration failure of the first bitstream
#
# Arguments:
# bits: size of the bitstream
# start: start address for the bitstream (0 by default)
# width: (optional) Configuration width (defaults to 16)
# freq: (optional) Configuration frequency in MHz (defaults to 134)
# dci_wait: (optional) Is DCI wait needed. Should be set to 1 if any DCI is
# being used in the design. Recommended to leave this at the
# default unless no DCI is used in the design
# family: (optional) 7: 7 series, 8: UltraScale (defaults to 7)
# Safe to leave at 7 for UltraScale
#
# results:
# Returns the next address at which it is safe to place a new bitstream (such
# as the timer images)
proc NextBitstreamAddress {bits start {width 16} {freq_mhz 134} {dci_wait 1} \
{family 7}} {
# Constants
# Always assume at least PLL lock waitup is needed. This is quite small
set pll_tlockmax_us 200
# Use 256 kB sectors, smaller sectors may save a little bit of buffer
# space, but will likely cause problems if used on 256 kB sector devices
set sector_size [expr 256 * 2**10]
if {$family == 8} {
set dcu_wait_ms 4
} else {
set dcu_wait_ms 10
}
set dcu_wait_us [expr $dcu_wait_ms * 1000]
# DCI Wait is always larger then pll_tlockmax_us, use it if enabled
if {$dci_wait} {
set wait_time [expr $dcu_wait_us * pow(10, -6)]
} else {
set wait_time [expr $pll_tlockmax_us * pow(10, -6)]
}
set frequency [expr $freq_mhz * 10**6]
# Find the number CCLK cycles needed for the max wait time
set wait_cycles [expr int(ceil($wait_time * $frequency))]
# puts " -- Wait cycles: $wait_cycles"
# The extra bits needed for the buffer
set extra_bytes [expr ($wait_cycles * $width) / 8]
# int(ceil(($frequency * $width / 8)))]
# puts " -- Extra Bytes: $extra_bytes"
# Add the extra bytes to the bitstream size and get the end address
set bits_end [expr $bits + $start + $extra_bytes]
set end_sector [expr int(ceil((1.0 * $bits_end) / $sector_size))]
set end_address [expr $end_sector * $sector_size]
# puts " -- Next available address: [hexpr $end_address]"
return $end_address
}
# FirstTimerAddress --
#
# Calculate the first timer address based off the multiboot address
#
# Arguments:
# multiboot_address: Address of the multiboot image. This is the next "safe"
# sector after the golden bitstream
# Results:
# returns the address to place the first timer
proc FirstTimerAddress {multiboot_address} {
set timer_size 1024
return [expr $multiboot_address - $timer_size]
}
# WbstarAddress --
#
# Calculate the first timer address
#
# Arguments:
# multiboot_address: Address of the multiboot image. This is the next "safe"
# sector after the golden bitstream
# Results:
# returns the address for WBSTAR (BITSTREAM.CONFIG.NEXT_CONFIG_ADDR)
proc WbstarAddress {multiboot_address} {
set wbstar_offset 512
return [expr $multiboot_address - $wbstar_offset]
}
# CreateNext4Bytes --
#
# Formats 4 bytes for a bitstream SPI or BPIx16
#
# Arguments:
# bitswap (optional) - Swap the bits in the byte
#
# Results:
# return a single byte
proc CreateNext4Bytes {word {bitswap 0} {byteswap 0}} {
set return_string ""
# puts "DEBUG: Next hex string : $word"
switch $byteswap {
0 {
set byte_sequence {0 2 4 6}
}
1 {
set byte_sequence {2 0 6 4}
}
default {
error "Unknown byte swap pattern: $byteswap"
}
}
foreach i $byte_sequence {
set out_data [binary format H2 [string range $word $i [expr $i + 1]]]
binary scan $out_data B8 bin_string
# puts "DEBUG: Next byte : $bin_string"
if {$bitswap} {
append return_string [string reverse $bin_string]
} else {
append return_string $bin_string
}
}
# puts "DEBUG: Next string: $return_string"
return $return_string
}
# CreateTimers --
#
# Create the BIN files for the Timers
#
# Arguments:
# timer - either 1 or 2 for the timer to be built
# bitswap (optional) - Swap the bits in each byte
# byteswap (optional) - Swap the bytes (every other byte)
#
# Results:
# timer1.bin and timer2.bin are created.
#
# timer1.bin will be 1024 bytes with the bus width detect, sync word and timer
# values near the end of the .bin file.
#
# timer2.bin will be just over 256 bytes (includes 256 bytes of dummy words
# before the sync word
proc CreateTimers {timer {bitswap 0} {byteswap 0}} {
# set timer1_size 1024
#
set dummy_word "FFFFFFFF"
set sync_word "AA995566"
set bus_width_detect_word "000000BB"
set bus_width_word "11220044"
set noop_word "20000000"
set timer_word "30022001"
set timer_set_value [expr int(0x40000000)]
# puts "DEBUG(CreateTimers): timer_set_value: $timer_set_value"
if {$timer == "1"} {
set timer_filename timer1.bin
set header_size_words 242
set timer_count 0x4000
} else {
set timer_filename "timer${timer}.bin"
set header_size_words 1
set timer_count 1
}
puts "Writing Timer: $timer_filename"
set timer_list ""
# Add the dummy words
set i 0
while {$i < $header_size_words} {
incr i
lappend timer_list $dummy_word
}
# Here's the main content of the timer image
lappend timer_list $bus_width_detect_word
lappend timer_list $bus_width_word
lappend timer_list $dummy_word
lappend timer_list $dummy_word
lappend timer_list $sync_word
lappend timer_list $noop_word
lappend timer_list $noop_word
lappend timer_list $noop_word
lappend timer_list $timer_word
# Figure out the timer string
set timer_string [format "%08X" [expr $timer_set_value | $timer_count]]
lappend timer_list $timer_string
# Add a few dummy words and no-ops
lappend timer_list $noop_word
lappend timer_list $noop_word
lappend timer_list $dummy_word
lappend timer_list $dummy_word
set fp [open $timer_filename w]
fconfigure $fp -translation binary
foreach i $timer_list {
set next_word [CreateNext4Bytes $i $bitswap $byteswap]
puts -nonewline $fp [binary format B32 $next_word]
}
close $fp
}
# CompareAddress2Size --
#
# Check that given address is within the bounds of the flash device
#
# Arguments:
# address: address in bytes
# size : size of flash device in bits
#
# Results:
# Return the size difference in bytes (rounded up) between the address and
# size of the flash. Negative means address is with the flash density
proc CompareAddress2Size {address size_mbit} {
# convert address to bits
set size_bytes [expr ($size_mbit/8) * 2**20]
return [expr $address - $size_bytes]
}
## ---- Main (script entry) ----
set options [GetOptions $argc $argv]
if {$options == -1} {
exit -1
}
set type [lindex $options 0]
set width [lindex $options 1]
set freq_mhz [lindex $options 2]
set flash_size_mbit [lindex $options 3]
set bitsize_bytes [lindex $options 4]
puts "Flash type : [string toupper $type]"
puts "Flash width (bits) : $width"
puts "CCLK frequency (MHz): $freq_mhz"
puts "Flash density (Mbit): $flash_size_mbit"
puts "Bitstream size (B) : $bitsize_bytes"
# By default, do not swap bits or bytes
set bitswap 0
set byteswap 0
# Select the appropriate configuration mode
switch ${type}_${width} {
"spi_1" {
set interface "SPIx1"
}
"spi_2" {
set interface "SPIx2"
}
"spi_4" {
set interface "SPIx4"
}
"spi_8" {
set interface "SPIx8"
}
"bpi_8" {
set interface "BPIx8"
set bitswap 1
}
"bpi_16" {
set interface "BPIx16"
set bitswap 1
set byteswap 1
}
default {
error "Unknown width and flash type combo: $type/$width"
}
}
# Create the timer images
puts ""
CreateTimers 1 $bitswap $byteswap
CreateTimers 2 $bitswap $byteswap
set multiboot_address [NextBitstreamAddress $bitsize_bytes 0 $width $freq_mhz 0]
set timer1_address [FirstTimerAddress $multiboot_address]
set timer2_address [NextBitstreamAddress $bitsize_bytes $multiboot_address \
$width $freq_mhz 0]
# Check that the sizes make sense
set crit_warn "\nCritical Warning: The"
set beyond_msg "address is beyond the end of the flash device"
set size_check [CompareAddress2Size $timer1_address $flash_size_mbit]
if {$size_check > 0} {
puts "$crit_warn Timer1 $beyond_msg"
}
set size_check [CompareAddress2Size $multiboot_address $flash_size_mbit]
if {$size_check > 0} {
puts "$crit_warn Multiboot start $beyond_msg"
}
set size_check [CompareAddress2Size $timer2_address $flash_size_mbit]
if {$size_check > 0} {
puts "$crit_warn Timer2 $beyond_msg"
}
# Adjust for BPI addressing if required
if {[string match $interface "BPIx16"]} {
set multiboot_address [expr $multiboot_address >> 1]
set timer1_address [expr $timer1_address >> 1]
set timer2_address [expr $timer2_address >> 1]
}
puts ""
puts "Golden bitstream address: [hexpr 0]"
puts "Timer1 image address : [hexpr $timer1_address]"
puts "Multiboot image address : [hexpr $multiboot_address]"
puts "Timer2 image address : [hexpr $timer2_address]"
# Write out the write_cfgmem command line
puts ""
puts "write_cfgmem command:"
puts -nonewline "write_cfgmem -format mcs -size [expr ($flash_size_mbit/8)]"
puts -nonewline " -interface $interface"
puts -nonewline " -loadbit \""
puts -nonewline "up [hexpr 0] <golden>"
puts -nonewline " up [hexpr $multiboot_address] <multiboot>\" "
puts -nonewline " -loaddata \""
puts -nonewline "up [hexpr $timer1_address] timer1.bin"
puts -nonewline " up [hexpr $timer2_address] timer2.bin\""
puts -nonewline " <output_mcs>"
puts ""

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*************************************************************************
____ ____
/ /\/ /
/___/ \ /
\ \ \/ © Copyright 2015 Xilinx, Inc. All rights reserved.
\ \ This file contains confidential and proprietary
/ / information of Xilinx, Inc. and is protected under U.S.
/___/ /\ and international copyright and other intellectual
\ \ / \ property laws.
\___\/\___\
*************************************************************************
Vendor: Xilinx
Current readme.txt Version: 1.0.0
Date Last Modified: 19April2015
Date Created: 19April2015
Associated Filename: xapp1247.zip
Associated Document: XAPP1247, MultiBoot with 7Series FPGAs using SPI Interface
Supported Device(s): 7Series
*************************************************************************
Disclaimer:
This disclaimer is not a license and does not grant any rights to
the materials distributed herewith. Except as otherwise provided in
a valid license issued to you by Xilinx, and to the maximum extent
permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE
"AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of liability) for
any loss or damage of any kind or nature related to, arising under
or in connection with these materials, including for any direct, or
any indirect, special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of loss or
damage suffered as a result of any action brought by a third party)
even if such damage or loss was reasonably foreseeable or Xilinx
had been advised of the possibility of the same.
Critical Applications:
Xilinx products are not designed or intended to be fail-safe, or
for use in any application requiring fail-safe performance, such as
life-support or safety devices or systems, Class III medical
devices, nuclear facilities, applications related to the deployment
of airbags, or any other applications that could lead to death,
personal injury, or severe property or environmental damage
(individually and collectively, "Critical Applications"). Customer
assumes the sole risk and liability of any use of Xilinx products
in Critical Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS
FILE AT ALL TIMES.
*************************************************************************
This readme file contains these sections:
1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. SUPPORT
1. REVISION HISTORY
Readme
Date Version Revision Description
=========================================================================
19April2015 1.0 Initial Xilinx release.
=========================================================================
2. OVERVIEW
This readme describes how to use the files that come with XAPP1247.
multiboot_address_table directory contains tcl script to generate Barrier images along with address map locations of images in flash memory device.
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
* Xilinx Vivado Design Suite 2015.1
4. DESIGN FILE HIERARCHY
\multiboot_address_table
| This folder contains multiboot_address_table.tcl script to generate barrier/timer
| images. For insturcitons how to use this script refer to Advanced section of xapp1247.
5. SUPPORT
To obtain technical support for this reference design, go to
www.xilinx.com/support to locate answers to known issues in the Xilinx
Answers Database or to create a WebCase.

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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "fifo_generator_0",
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
"ip_revision": "9",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "fifo_generator_0", "resolve_type": "user", "usage": "all" } ],
"Fifo_Implementation": [ { "value": "Independent_Clocks_Block_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
"Performance_Options": [ { "value": "First_Word_Fall_Through", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Data_Width": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Input_Depth": [ { "value": "1024", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Data_Width": [ { "value": "128", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Depth": [ { "value": "512", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Flags_Reset_Value": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Use_Dout_Reset": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Valid_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Extra_Logic": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Data_Count_Width": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Data_Count_Width": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Read_Data_Count_Width": [ { "value": "9", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
"Full_Threshold_Assert_Value": [ { "value": "1023", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Full_Threshold_Negate_Value": [ { "value": "1022", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
"Empty_Threshold_Assert_Value": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Negate_Value": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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2020.1:
* Version 13.2 (Rev. 5)
* No changes
2019.2.2:
* Version 13.2 (Rev. 5)
* No changes
2019.2.1:
* Version 13.2 (Rev. 5)
* No changes
2019.2:
* Version 13.2 (Rev. 5)
* General: IP Waivers update in constraint files. No functional changes
* Revision change in one or more subcores
2019.1.3:
* Version 13.2 (Rev. 4)
* No changes
2019.1.2:
* Version 13.2 (Rev. 4)
* No changes
2019.1.1:
* Version 13.2 (Rev. 4)
* No changes
2019.1:
* Version 13.2 (Rev. 4)
* Bug Fix: Destination Clock not connected properly for some XPM_CDC instances when in common clock mode. Conditions added to connect the correct clock
* Other: IP Waivers added in constraint files. No functional changes
* Revision change in one or more subcores
2018.3.1:
* Version 13.2 (Rev. 3)
* No changes
2018.3:
* Version 13.2 (Rev. 3)
* Feature Enhancement: None
* Other: Reduced simulation warnings in Behavioral model. No functional changes
* Revision change in one or more subcores
2018.2:
* Version 13.2 (Rev. 2)
* No changes
2018.1:
* Version 13.2 (Rev. 2)
* Bug Fix: Enable Safety Circuit option was unintentionally made available for user selection when Enable Reset Synchronization is not selected. This unintentional enablement is corrected and Enable Safety Circuit is available for user selection only if Enable Reset Synchronization option is selected
* Bug Fix: REQP-1839 DRC warning removed from example test bench
* Bug Fix: Read Data Count in behavioral model is updated to start with a valid value when Enable Reset Synchronization option is not selected
* Other: As FIFO Generator core uses XPM_CDC module, user must ensure that the wr_rst and rd_rst overlap for at least C_SYNCHRONIZER_STAGE+1 slowest clock cycles if Enable Reset Synchronization option is disabled
2017.4:
* Version 13.2 (Rev. 1)
* Revision change in one or more subcores
2017.3:
* Version 13.2
* Feature Enhancement: Enable Safety Circuit option is made default for BRAM based FIFOs when Asynchronous Reset is selected
* Feature Enhancement: All outputs are made synchronous to respective clock domain when Enable Safety Circuit option is selected
* Feature Enhancement: All outputs are invalid for reset duration + 60 slowest clock cycles when Enable Safety Circuit option is selected
* Feature Enhancement: All outputs are invalid for reset duration + 30 slowest clock cycles when Enable Safety Circuit option is not selected
* Feature Enhancement: The outputs of FIFO Generator may be Xs for initial few clock cycles if the core is configured without reset. It is recommended to wait for 15 slowest clock cycles at the beginning of behavioral simulation (from time 0) before accessing the FIFO
2017.2:
* Version 13.1 (Rev. 4)
* No changes
2017.1:
* Version 13.1 (Rev. 4)
* Bug Fix: FIFO Generator core was constructing the buit-in FIFO sub-optimally for 2K-deep and 36-bit wide configuration. This is corrected to use the optimal FIFO structure
* Bug Fix: In order to enable the tool to perform the recovery check on the reset, set_false_path for reset is kept only from the input port to the first flop where it connects to
* Feature Enhancement: Updated the FIFO Generator's constraints to improve tool performance processing its XDC
* Other: Internal device family change, no functional changes
* Revision change in one or more subcores
2016.4:
* Version 13.1 (Rev. 3)
* Port Change: None
* Bug Fix: Supported features table in the first page of GUI updated to reflect the asymmetry support for common clock BRAM FIFO
* Feature Enhancement: None
* Revision change in one or more subcores
2016.3:
* Version 13.1 (Rev. 2)
* Port Change: wr_rst_busy and rd_rst_busy ports made available if safety circuit is enabled
* Bug Fix: Fixed issue which was causing the m_axis_tvalid to go high after the reset is released and no valid data written to the FIFO
* Feature Enhancement: Safety circuit is made independent of Output Register and Enable Reset Synchronization options
* Other: Added support for future devices
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
* Revision change in one or more subcores
2016.2:
* Version 13.1 (Rev. 1)
* Revision change in one or more subcores
2016.1:
* Version 13.1
* Delivering only Verilog behavioral model.
* Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.
* Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.
* Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.
* Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer the PG(057)
* Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected
* Revision change in one or more subcores
2015.4.2:
* Version 13.0 (Rev. 1)
* No changes
2015.4.1:
* Version 13.0 (Rev. 1)
* No changes
2015.4:
* Version 13.0 (Rev. 1)
* Fixed safety circuit related warnings in Behavioral model
* Revision change in one or more subcores
2015.3:
* Version 13.0
* Additional safety circuit option provided for asynchronous reset configurations.
* Delivering only VHDL behavioral model.
* Added asymmetric port width support for 7-series Common Clock Block RAM FIFO
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
2015.2.1:
* Version 12.0 (Rev. 4)
* No changes
2015.2:
* Version 12.0 (Rev. 4)
* No changes
2015.1:
* Version 12.0 (Rev. 4)
* Delivering non encrypted behavioral models.
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
* Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 12.0 (Rev. 3)
* No changes
2014.4:
* Version 12.0 (Rev. 3)
* Reduced DRC warnings.
* Internal device family change, no functional changes
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
2014.3:
* Version 12.0 (Rev. 2)
* Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
* Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
* Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
* Added support for Low Latency Built-in FIFO for UltraScale devices.
2014.2:
* Version 12.0 (Rev. 1)
* Repackaged to improve internal automation, no functional changes.
2014.1:
* Version 12.0
* Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.
* Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.
* Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices
* Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices
* Internal device family name change, no functional changes
2013.4:
* Version 11.0 (Rev. 1)
* Added support for Ultrascale devices
* Common Clock Builtin FIFO is set as default implementation type only for UltraScale devices
* Embedded Register option is always ON for Block RAM and Builtin FIFOs only for UltraScale devices
* Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices
2013.3:
* Version 11.0
* AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
* AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
* Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
* Enhanced support for IP Integrator
* Reduced warnings in synthesis and simulation
* Added support for Cadence IES and Synopsys VCS simulators
* Improved GUI speed and responsiveness, no functional changes
* Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4
2013.2:
* Version 10.0 (Rev. 1)
* Constraints processing order changed
2013.1:
* Version 10.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
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// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 5
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
fifo_generator_0 your_instance_name (
.rst(rst), // input wire rst
.wr_clk(wr_clk), // input wire wr_clk
.rd_clk(rd_clk), // input wire rd_clk
.din(din), // input wire [63 : 0] din
.wr_en(wr_en), // input wire wr_en
.rd_en(rd_en), // input wire rd_en
.dout(dout), // output wire [127 : 0] dout
.full(full), // output wire full
.empty(empty), // output wire empty
.valid(valid), // output wire valid
.wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy
.rd_rst_busy(rd_rst_busy) // output wire rd_rst_busy
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file fifo_generator_0.v when simulating
// the core, fifo_generator_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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@ -0,0 +1,97 @@
-- (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
-- IP Revision: 5
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT fifo_generator_0
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : fifo_generator_0
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file fifo_generator_0.vhd when simulating
-- the core, fifo_generator_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.

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################################################################################
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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# This file contains confidential and proprietary information
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# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
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# (individually and collectively, "Critical
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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################################################################################
#------------------------------------------------------------------------------#
# Native FIFO Constraints #
#------------------------------------------------------------------------------#
################################################################################

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Firmware/XDMA/xci/100t/fifo_generator_0/fifo_generator_0_clocks.xdc Normal file
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################################################################################
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
#------------------------------------------------------------------------------#
# Native FIFO Constraints #
#------------------------------------------------------------------------------#
#set wr_clock [get_clocks -of_objects [get_ports wr_clk]]
#set rd_clock [get_clocks -of_objects [get_ports rd_clk]]
#set wr_clk_period [get_property PERIOD $wr_clock]
#set rd_clk_period [get_property PERIOD $rd_clock]
#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.sckt_wrst_i_reg}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_inst/Q_reg_reg[0]}]
#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[3].rd_rst_inst/Q_reg_reg[0]}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_wr_inst/Q_reg_reg[0]}]
################################################################################

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Firmware/XDMA/xci/100t/fifo_generator_0/fifo_generator_0_ooc.xdc Normal file
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# (c) Copyright 2012-2024 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 10 -name wr_clk [get_ports wr_clk]
create_clock -period 10 -name rd_clk [get_ports rd_clk]

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Firmware/XDMA/xci/100t/fifo_generator_0/fifo_generator_0_sim_netlist.v Normal file
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Firmware/XDMA/xci/100t/fifo_generator_0/fifo_generator_0_sim_netlist.vhdl Normal file
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