Routing in progress, minor SCH changes

Stiffer I2C Pullups, more 100nF changed to 1uF

Hardware/KiCad/Thunderscope_Rev5/Thunderscope_Rev5.kicad_prl

@@ -1,6 +1,6 @@
 {
   "board": {
-    "active_layer": 0,
+    "active_layer": 2,
     "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_netclasses": [
@@ -14,8 +14,6 @@
       "PWR"
     ],
     "hidden_nets": [
-      "/ADC/+1V8A",
-      "/ADC/+1V8D",
       "/VCM",
       "/FPGA/MGT_TX0_N",
       "/FPGA/MGT_TX0_P",
@@ -25,11 +23,8 @@
       "/FPGA/MGT_TX2_P",
       "/FPGA/MGT_TX3_N",
       "/FPGA/MGT_TX3_P",
-      "/Clock Generator/INTREF",
-      "/Clock Generator/ADC_CLK_R_P",
       "/ADC/ADC_CLK_P",
       "/ADC/ADC_CLK_N",
-      "/Clock Generator/ADC_CLK_R_N",
       "Net-(U18H-VCCADC_0)",
       "/CH1/ATTEN_50X_R",
       "/CH2/ATTEN_50X_R",
@@ -76,7 +71,9 @@
       "/CH4/TERM_50Z_R",
       "/CH4/ATTEN_OUT",
       "/Front End Trim and Bias/TRIM_SCL",
+      "/Front End Trim and Bias/TRIM_SCL_5V",
       "/Front End Trim and Bias/TRIM_SDA",
+      "/Front End Trim and Bias/TRIM_SDA_5V",
       "/ADC/ADC_CSn",
       "/ADC/ADC_RSTn",
       "/ADC/ADC_PD",
@@ -100,12 +97,6 @@
       "/FPGA/FPGA IO Banks/PLL_SCL",
       "/FPGA/FPGA IO Banks/PLL_SDA",
       "+1V8_ACQ",
-      "/Clock Generator/IF1",
-      "/Clock Generator/IF0",
-      "/Clock Generator/AC0",
-      "/Clock Generator/AC1",
-      "/Clock Generator/AC2",
-      "/Clock Generator/TEST",
       "/FPGA/FPGA IO Banks/PUDC",
       "Net-(U18D-INIT_B_0)",
       "Net-(U18D-PROGRAM_B_0)",
@@ -229,16 +220,12 @@
       "/TS-PCIe Components/PCIe_PET3_P",
       "/TS-PCIe Components/PCIe_PET2_P",
       "/TS-PCIe Components/PCIe_PERST#",
-      "/TS-PCIe Components/PRSNT1#",
       "/TS-PCIe Components/PCIe_PET2_N",
-      "/TS-PCIe Components/PRSNT2#_1",
-      "/TS-PCIe Components/PRSNT2#_4",
       "/TS-PCIe Components/PCIe_PET0_P",
       "/TS-PCIe Components/PCIe_PET0_N",
       "/FPGA/FPGA Voltage Regs/PG_1V8",
       "/SYNC",
       "/FPGA/LED_G",
-      "/COMP",
       "/FPGA/PROBE_COMP",
       "/PERST#",
       "/FPGA/FPGA IO Banks/ACQ_PG",
@@ -300,7 +287,7 @@
       "footprints": true,
       "graphics": true,
       "keepouts": true,
-      "lockedItems": true,
+      "lockedItems": false,
       "otherItems": true,
       "pads": true,
       "text": true,