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https://github.com/EEVengers/ThunderScope.git
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137 lines
5.0 KiB
Plaintext
137 lines
5.0 KiB
Plaintext
(version 1)
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(rule FE_100Z_Diff_Inner
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(layer inner)
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(condition "A.hasNetclass('FE_100Z_Diff')")
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(constraint disallow track))
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(rule FE_100Z_Diff_Outer
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(layer outer)
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(condition "A.hasNetclass('FE_100Z_Diff')")
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(constraint diff_pair_gap (opt 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule FE_100Z_Diff_Vias
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(condition "A.hasNetclass('FE_100Z_Diff')")
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(constraint via_count (min 0) (opt 0) (max 0)))
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(rule LVDS_SYNC_Inner
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(layer inner)
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(condition "A.hasNetclass('LVDS_SYNC')")
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(constraint diff_pair_gap (opt 0.23035mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule LVDS_SYNC_Outer
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(layer outer)
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(condition "A.hasNetclass('LVDS_SYNC')")
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(constraint diff_pair_gap (opt 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule LVDS_USRIO_Inner
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(layer inner)
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(condition "A.hasNetclass('LVDS_USRIO')")
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(constraint diff_pair_gap (opt 0.23035mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule LVDS_USRIO_Outer
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(layer outer)
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(condition "A.hasNetclass('LVDS_USRIO')")
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(constraint diff_pair_gap (opt 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule LVDS_ADC_Inner
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(layer inner)
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(condition "A.hasNetclass('LVDS_ADC')")
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(constraint diff_pair_gap (opt 0.23035mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule LVDS_ADC_Outer
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(layer outer)
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(condition "A.hasNetclass('LVDS_ADC')")
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(constraint diff_pair_gap (opt 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule LVDS_ADC_CLK_Inner
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(layer inner)
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(condition "A.hasNetclass('LVDS_ADC_CLK')")
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(constraint diff_pair_gap (opt 0.23035mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule LVDS_ADC_CLK_Outer
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(layer outer)
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(condition "A.hasNetclass('LVDS_ADC_CLK')")
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(constraint diff_pair_gap (opt 0.13022mm))
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(constraint track_width (min 0.127mm)(opt 0.127mm)(max 0.127mm)))
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(rule PCIe_Inner
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(layer inner)
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(condition "A.hasNetclass('PCIe')")
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(constraint diff_pair_gap (opt 0.127mm))
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(constraint track_width (min 0.14789mm)(opt 0.14789mm)(max 0.14789mm)))
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(rule PCIe_Outer
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(layer outer)
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(condition "A.hasNetclass('PCIe')")
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(constraint diff_pair_gap (opt 0.127mm))
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(constraint track_width (min 0.19079mm)(opt 0.19079mm)(max 0.19079mm)))
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(rule FE_50Z_Inner
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(layer inner)
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(condition "A.hasNetclass('FE_50Z')")
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(constraint disallow track))
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(rule FE_50Z_Outer
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(layer outer)
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(condition "A.hasNetclass('FE_50Z')")
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(constraint track_width (min 0.213mm)(opt 0.213mm)(max 0.213mm)))
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(rule FE_50Z_Vias
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(condition "A.hasNetclass('FE_50Z')")
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(constraint via_count (min 0) (opt 0) (max 0)))
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(rule GND_Planes
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(condition "A.Layer == 'In1.Cu' || A.Layer == 'In4.Cu'")
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(constraint disallow track))
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(rule "Allow connector silk to intersect board edge"
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(constraint silk_clearance)
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(severity ignore)
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(condition "A.memberOfFootprint('J*') && B.Layer=='Edge.Cuts'"))
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(rule "Distance between test points"
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(constraint courtyard_clearance (min 0.5mm))
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(condition "A.Reference =='TP*' && B.Reference == 'TP*"))
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(rule "Through Hole Pad to Plane Clearence"
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(condition "A.Pad_Type == 'Through-hole' && B.Type == 'Zone'")
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(constraint clearance (min 0.5mm)))
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(rule "FE_100Z_Diff to GND Plane Clearence"
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(condition "A.hasNetclass('FE_100Z_Diff') && A.Type == 'Track' && B.Type == 'Zone' && B.NetName == 'GND'")
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(constraint clearance (min 0.4mm)))
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(rule "FE_50Z_INPUT to GND Plane Clearence"
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(condition "A.hasNetclass('FE_50Z_INPUT') && A.Type == 'Track' && B.Type == 'Zone' && B.NetName == 'GND'")
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(constraint clearance (min 0.5mm)))
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(rule "LVDS_USRIO to GND Plane Clearence"
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(condition "A.hasNetclass('LVDS_USRIO') && A.Type == 'Track' && B.Type == 'Zone' && B.NetName == 'GND'")
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(constraint clearance (min 0.4mm)))
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(rule "50Z to GND Plane Clearence"
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(condition "A.hasNetclass('50Z') && A.Type == 'Track' && B.Type == 'Zone' && B.NetName == 'GND'")
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(constraint clearance (min 0.4mm)))
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(rule "PCIe to GND Plane Clearence"
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(condition "A.hasNetclass('PCIe') && A.Type == 'Track' && B.Type == 'Zone' && B.NetName == 'GND'")
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(constraint clearance (min 0.4mm)))
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(rule "LVDS_SYNC to GND Plane Clearence"
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(condition "A.hasNetclass('LVDS_SYNC') && A.Type == 'Track' && B.Type == 'Zone' && B.NetName == 'GND'")
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(constraint clearance (min 0.4mm)))
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(rule "/CH1/BNC_IN length"
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(condition "A.NetName == '/CH1/BNC_IN'")
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(constraint length (min 9.011649415608034mm) (opt 9.191457506750472mm) (max 9.371265597892911mm)))
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(rule "/CH2/BNC_IN length"
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(condition "A.NetName == '/CH2/BNC_IN'")
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(constraint length (min 9.011649415608035mm) (opt 9.191457506750474mm) (max 9.371265597892913mm)))
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(rule "/CH3/BNC_IN length"
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(condition "A.NetName == '/CH3/BNC_IN'")
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(constraint length (min 9.011649415608035mm) (opt 9.191457506750474mm) (max 9.371265597892913mm)))
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(rule "/CH4/BNC_IN length"
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(condition "A.NetName == '/CH4/BNC_IN'")
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(constraint length (min 9.011649415608035mm) (opt 9.191457506750474mm) (max 9.371265597892913mm)))
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# DELAY TUNER RULES
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