Tubii_Tk2/Parts/parts/capacitors/tant0805/entity/verilog.v

14 lines
169 B
Coq
Raw Normal View History

2015-02-28 00:09:38 +00:00
// generated by newgenasym Mon Sep 13 13:16:51 2010
module tant0805 (a, b);
input [0:0] a;
output [0:0] b;
initial
begin
end
endmodule