Tubii_Tk2/Parts/parts/ecl/10h125/entity/verilog.v

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2015-02-28 00:09:38 +00:00
// generated by newgenasym Wed Oct 6 10:34:08 2010
module \10h125 (a, \b* , v, y);
parameter section = 3;
parameter size = 1;
input [size-1:0] a;
input [size-1:0] \b* ;
output v;
output [size-1:0] y;
initial
begin
end
endmodule