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Similarly connected large pin of 7815s_l and 7915l to output

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This commit is contained in:
Eric Marzec 2015-05-19 17:08:03 -04:00
parent dfdc87dc52
commit 2f5d188fc6
213 changed files with 178550 additions and 167981 deletions
Parts/parts/regulators
7815s_l
entity
verilog.vvhdl.vhd
metadata
pdv_validation.txtrevHistory.logrevision.log
7915_l
entity
verilog.vvhdl.vhd
metadata
pdv_validation.txtrevHistory.logrevision.log
7915s_l
entity
verilog.vvhdl.vhd
metadata
pdv_validation.txtrevHistory.logrevision.log
temp
csdirect.logsessionlog.txt
tubii_tk2.cpm
worklib
baseline_buffer/sch_1
baseline_buffer.xcon,1baseline_buffer.xcon,2baseline_buffer.xcon,3
caen_analog_coms/sch_1
caen_analog_coms.concaen_analog_coms.xcon,1caen_analog_coms.xcon,2caen_analog_coms.xcon,3
caen_dig_coms/sch_1
caen_dig_coms.xcon,1caen_dig_coms.xcon,2caen_dig_coms.xcon,3
change_clks/sch_1
change_clks.xcon,1change_clks.xcon,2change_clks.xcon,3
clocks/sch_1
clocks.conclocks.dcf,1clocks.dcf,2clocks.dcf,3clocks.xcon,1clocks.xcon,2clocks.xcon,3
cntrl_register/sch_1
cntrl_register.xcon,1cntrl_register.xcon,2cntrl_register.xcon,3
default_clk_sel/sch_1
default_clk_sel.xcon,1default_clk_sel.xcon,2default_clk_sel.xcon,3
ecal_control/sch_1
ecal_control.xcon,1ecal_control.xcon,2ecal_control.xcon,3
ecl_translation/sch_1
ecl_translation.xcon,1ecl_translation.xcon,2ecl_translation.xcon,3
ellie_coms/sch_1
ellie_coms.xcon,1ellie_coms.xcon,2ellie_coms.xcon,3
ext_trigs/sch_1
ext_trigs.xcon,1ext_trigs.xcon,2ext_trigs.xcon,3
fault_detection/sch_1
fault_detection.xcon,1fault_detection.xcon,2fault_detection.xcon,3
generic_delays/sch_1
generic_delays.xcon,1generic_delays.xcon,2generic_delays.xcon,3
gt_delays/sch_1
gt_delays.xcon,1gt_delays.xcon,2gt_delays.xcon,3
lo_gen/sch_1
lo_gen.conlo_gen.xcon,1lo_gen.xcon,2lo_gen.xcon,3
microzed_module/sch_1
microzed_module.xcon,1microzed_module.xcon,2microzed_module.xcon,3
mtca_mimic/sch_1
mtca_mimic.conmtca_mimic.xcon,1mtca_mimic.xcon,2mtca_mimic.xcon,3
power/sch_1
power.conpower.dcf,1power.dcf,2power.dcf,3power.xcon,1power.xcon,2power.xcon,3
pulse_inverter/sch_1
pulse_inverter.xcon,1pulse_inverter.xcon,2pulse_inverter.xcon,3
ribbon_delay/sch_1
ribbon_delay.xcon,1ribbon_delay.xcon,2ribbon_delay.xcon,3
select_lo_src/sch_1
select_lo_src.xcon,1select_lo_src.xcon,2select_lo_src.xcon,3
trigger_logic/sch_1
trigger_logic.xcon,1trigger_logic.xcon,2trigger_logic.xcon,3
tubii
packaged
pstback.dat,1pstback.dat,2pstback.dat,3pstchip.dat,1pstchip.dat,2pstchip.dat,3pstpin.dat,1pstpin.dat,2pstpin.dat,3pstrprt.dat,1pstrprt.dat,2pstrprt.dat,3pstxnet.dat,1pstxnet.dat,2pstxnet.dat,3pstxprt.dat,1pstxprt.dat,2pstxprt.dat,3pstxref.dat,1pstxref.dat,2pstxref.dat,3pxl.chg,1pxl.chg,2pxl.chg,3pxl.dbgpxl.dbg.oldpxl.logpxl.state,1pxl.state,2pxl.state,3
physical
TubiiPCB_V6.brdallegro.jrlallegro.jrl,1eco.txteco.txt,1pstcmdb2.dat
sch_1
tubii.dcf,1tubii.dcf,2tubii.dcf,3
tubii_pcb/sch_1
tubii_pcb.dcf,1tubii_pcb.dcf,2tubii_pcb.dcf,3
tubii_spkr/sch_1
tubii_spkr.xcon,1tubii_spkr.xcon,2tubii_spkr.xcon,3
vref_gen/sch_1
vref_gen.xcon,1vref_gen.xcon,2vref_gen.xcon,3

5
Parts/parts/regulators/7815s_l/entity/verilog.v
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@ -1,10 +1,11 @@
// generated by newgenasym Tue May 18 12:01:37 2010
// generated by newgenasym Tue May 19 16:51:53 2015
module \7815s_l (ground, \input , \output );
module \7815s_l (ground, \input , \output , output_2);
inout ground;
input \input ;
output \output ;
inout output_2;
initial

5
Parts/parts/regulators/7815s_l/entity/vhdl.vhd
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@ -1,4 +1,4 @@
-- generated by newgenasym Tue May 18 12:01:37 2010
-- generated by newgenasym Tue May 19 16:51:53 2015
library ieee;
use ieee.std_logic_1164.all;
@ -7,5 +7,6 @@ entity \7815s_l\ is
port (
GROUND: INOUT STD_LOGIC;
INPUT: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC);
OUTPUT: OUT STD_LOGIC;
OUTPUT_2: INOUT STD_LOGIC);
end \7815s_l\;

1
Parts/parts/regulators/7815s_l/metadata/pdv_validation.txt Normal file
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@ -0,0 +1 @@
SPLBPD-170,Cell '7815s_l':Pin(s) NC is (are) not present in any package or symbol. You can choose Pins - Add from the Package Pin page and delete these pins. If the HAS_FIXED_SIZE value has been reduced, reload the part.,Warning

0
Parts/parts/regulators/7815s_l/metadata/revHistory.log Normal file
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0
Parts/parts/regulators/7815s_l/metadata/revision.log Normal file
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5
Parts/parts/regulators/7915_l/entity/verilog.v
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@ -1,10 +1,11 @@
// generated by newgenasym Tue May 18 12:01:39 2010
// generated by newgenasym Tue May 19 16:55:16 2015
module \7915_l (ground, \input , \output );
module \7915_l (ground, \input , \output , output_2);
inout ground;
input \input ;
output \output ;
inout output_2;
initial

5
Parts/parts/regulators/7915_l/entity/vhdl.vhd
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@ -1,4 +1,4 @@
-- generated by newgenasym Tue May 18 12:01:39 2010
-- generated by newgenasym Tue May 19 16:55:16 2015
library ieee;
use ieee.std_logic_1164.all;
@ -7,5 +7,6 @@ entity \7915_l\ is
port (
GROUND: INOUT STD_LOGIC;
INPUT: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC);
OUTPUT: OUT STD_LOGIC;
OUTPUT_2: INOUT STD_LOGIC);
end \7915_l\;

1
Parts/parts/regulators/7915_l/metadata/pdv_validation.txt Normal file
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@ -0,0 +1 @@
SPLBPD-170,Cell '7915_l':Pin(s) NC is (are) not present in any package or symbol. You can choose Pins - Add from the Package Pin page and delete these pins. If the HAS_FIXED_SIZE value has been reduced, reload the part.,Warning

0
Parts/parts/regulators/7915_l/metadata/revHistory.log Normal file
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0
Parts/parts/regulators/7915_l/metadata/revision.log Normal file
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5
Parts/parts/regulators/7915s_l/entity/verilog.v
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@ -1,10 +1,11 @@
// generated by newgenasym Tue May 18 12:01:40 2010
// generated by newgenasym Tue May 19 16:53:11 2015
module \7915s_l (ground, \input , \output );
module \7915s_l (ground, \input , \output , output_2);
inout ground;
input \input ;
output \output ;
inout output_2;
initial

5
Parts/parts/regulators/7915s_l/entity/vhdl.vhd
View File

@ -1,4 +1,4 @@
-- generated by newgenasym Tue May 18 12:01:40 2010
-- generated by newgenasym Tue May 19 16:53:11 2015
library ieee;
use ieee.std_logic_1164.all;
@ -7,5 +7,6 @@ entity \7915s_l\ is
port (
GROUND: INOUT STD_LOGIC;
INPUT: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC);
OUTPUT: OUT STD_LOGIC;
OUTPUT_2: INOUT STD_LOGIC);
end \7915s_l\;

0
Parts/parts/regulators/7915s_l/metadata/pdv_validation.txt Normal file
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0
Parts/parts/regulators/7915s_l/metadata/revHistory.log Normal file
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14
Parts/parts/regulators/7915s_l/metadata/revision.log Normal file
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@ -0,0 +1,14 @@
(Comment
(Time 05/19/15,16:52:36)
(User QGPWindowsVB)
(MsgId ECO_081)
(Text "Symbol sym_2 added to cell")
(Param1 "sym_2")
)
(Comment
(Time 05/19/15,16:52:49)
(User QGPWindowsVB)
(MsgId ECO_082)
(Text "Symbol sym_2 deleted from cell")
(Param1 "sym_2")
)

2
temp/csdirect.log
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@ -1,4 +1,4 @@
CSDirect 16.6-p007 (v16-6-112F)
Netlisting block power
Netlisting block gt_delays_ports
Processing page 1

88
temp/sessionlog.txt
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@ -1,32 +1,56 @@
05/19/15 16:24:50 Opening project C:/Users/QGPWindowsVB/Documents/ANUSTART/tubii_tk2.cpm
05/19/15 16:24:50 cdslib C:/Users/QGPWindowsVB/Documents/ANUSTART/cds.lib opened
05/19/15 16:24:50 Project C:/Users/QGPWindowsVB/Documents/ANUSTART/tubii_tk2.cpm opened
05/19/15 16:25:06 Loading cell lm1117 from library regulators
05/19/15 16:25:06 Loading view sym_1 of cell lm1117
05/19/15 16:25:06 Loading view chips of cell lm1117
05/19/15 16:25:06 Loading view entity of cell lm1117
05/19/15 16:25:06 Loading cell lm1117 from library regulators
05/19/15 16:25:06 Analyzing view relationships of cell lm1117 in library regulators
05/19/15 16:25:06 Completed loading cell lm1117 from library regulators
05/19/15 16:25:06 Starting validations on cell lm1117 of library regulators
05/19/15 16:25:06 Completed validations on cell lm1117 of library regulators
05/19/15 16:31:10 Pin number(s) entered cannot be saved because they have invalid character(s) ','. Specify physical pin number(s) with valid characters only.
05/19/15 16:31:10 Pin number(s) entered cannot be saved because they have invalid character(s) ','. Specify physical pin number(s) with valid characters only.
05/19/15 16:31:10 Pin number(s) entered cannot be saved because they have invalid character(s) ','. Specify physical pin number(s) with valid characters only.
05/19/15 16:31:14 Pin number(s) entered cannot be saved because they have invalid character(s) ','. Specify physical pin number(s) with valid characters only.
05/19/15 16:31:14 Pin number(s) entered cannot be saved because they have invalid character(s) ','. Specify physical pin number(s) with valid characters only.
05/19/15 16:32:07 Pin number(s) entered cannot be saved because they have invalid character(s) ','. Specify physical pin number(s) with valid characters only.
05/19/15 16:32:14 Pin number(s) entered cannot be saved because they have invalid character(s) ' '. Specify physical pin number(s) with valid characters only.
05/19/15 16:32:14 Pin number(s) entered cannot be saved because they have invalid character(s) ' '. Specify physical pin number(s) with valid characters only.
05/19/15 16:32:20 Pin number(s) entered cannot be saved because they have invalid character(s) ' '. Specify physical pin number(s) with valid characters only.
05/19/15 16:32:21 Pin number(s) entered cannot be saved because they have invalid character(s) ' '. Specify physical pin number(s) with valid characters only.
05/19/15 16:32:22 Pin number(s) entered cannot be saved because they have invalid character(s) ' '. Specify physical pin number(s) with valid characters only.
05/19/15 16:32:33 Pin name OUTPUT already exists. Specify a unique pin name.
05/19/15 16:32:57 Starting validations on cell lm1117 of library regulators
05/19/15 16:32:57 Completed validations on cell lm1117 of library regulators
05/19/15 16:33:37 Starting validations on cell lm1117 of library regulators
05/19/15 16:33:37 Completed validations on cell lm1117 of library regulators
05/19/15 16:33:52 Starting validations on cell lm1117 of library regulators
05/19/15 16:33:52 Completed validations on cell lm1117 of library regulators
05/19/15 16:33:54 Completed saving cell lm1117 in library regulators with errors/warnings
05/19/15 16:33:56 Project C:/Users/QGPWindowsVB/Documents/ANUSTART/tubii_tk2.cpm is closed.
05/19/15 16:49:33 Opening project C:/Users/QGPWindowsVB/Documents/ANUSTART/tubii_tk2.cpm
05/19/15 16:49:33 cdslib C:/Users/QGPWindowsVB/Documents/ANUSTART/cds.lib opened
05/19/15 16:49:33 Project C:/Users/QGPWindowsVB/Documents/ANUSTART/tubii_tk2.cpm opened
05/19/15 16:50:40 Loading cell 7815s_l from library regulators
05/19/15 16:50:40 Loading view sym_1 of cell 7815s_l
05/19/15 16:50:40 Loading view chips of cell 7815s_l
05/19/15 16:50:40 Loading view vlog_map of cell 7815s_l
05/19/15 16:50:40 File verilog.v does not exist. Check the filename and location.
05/19/15 16:50:40 Loading view entity of cell 7815s_l
05/19/15 16:50:40 Loading cell 7815s_l from library regulators
05/19/15 16:50:40 Analyzing view relationships of cell 7815s_l in library regulators
05/19/15 16:50:40 Completed loading cell 7815s_l from library regulators
05/19/15 16:50:40 Starting validations on cell 7815s_l of library regulators
05/19/15 16:50:40 BODY_NAME property does not exist in package 7815S_L. Since backannotation will not work without this property, it will be written automatically when the cell is saved.
05/19/15 16:50:40 Completed validations on cell 7815s_l of library regulators
05/19/15 16:51:21 Starting validations on cell 7815s_l of library regulators
05/19/15 16:51:21 Completed validations on cell 7815s_l of library regulators
05/19/15 16:51:51 Starting validations on cell 7815s_l of library regulators
05/19/15 16:51:51 Completed validations on cell 7815s_l of library regulators
05/19/15 16:51:54 Completed saving cell 7815s_l in library regulators with errors/warnings
05/19/15 16:52:04 Loading cell 7915s_l from library regulators
05/19/15 16:52:04 Loading view sym_1 of cell 7915s_l
05/19/15 16:52:04 Loading view chips of cell 7915s_l
05/19/15 16:52:04 Loading view vlog_map of cell 7915s_l
05/19/15 16:52:04 File verilog.v does not exist. Check the filename and location.
05/19/15 16:52:04 Loading view entity of cell 7915s_l
05/19/15 16:52:04 Loading cell 7915s_l from library regulators
05/19/15 16:52:04 Analyzing view relationships of cell 7915s_l in library regulators
05/19/15 16:52:04 Completed loading cell 7915s_l from library regulators
05/19/15 16:52:04 Starting validations on cell 7915s_l of library regulators
05/19/15 16:52:04 BODY_NAME property does not exist in package 7915S_L. Since backannotation will not work without this property, it will be written automatically when the cell is saved.
05/19/15 16:52:04 Completed validations on cell 7915s_l of library regulators
05/19/15 16:52:24 Starting validations on cell 7915s_l of library regulators
05/19/15 16:52:24 BODY_NAME property does not exist in package 7915S_L. Since backannotation will not work without this property, it will be written automatically when the cell is saved.
05/19/15 16:52:24 Completed validations on cell 7915s_l of library regulators
05/19/15 16:53:11 Starting validations on cell 7915s_l of library regulators
05/19/15 16:53:11 Completed validations on cell 7915s_l of library regulators
05/19/15 16:53:11 Completed saving cell 7915s_l in library regulators
05/19/15 16:54:29 Loading cell 7915_l from library regulators
05/19/15 16:54:29 Loading view sym_1 of cell 7915_l
05/19/15 16:54:29 Loading view chips of cell 7915_l
05/19/15 16:54:29 Loading view vlog_map of cell 7915_l
05/19/15 16:54:29 File verilog.v does not exist. Check the filename and location.
05/19/15 16:54:29 Loading view entity of cell 7915_l
05/19/15 16:54:29 Loading cell 7915_l from library regulators
05/19/15 16:54:29 Analyzing view relationships of cell 7915_l in library regulators
05/19/15 16:54:29 Completed loading cell 7915_l from library regulators
05/19/15 16:54:29 Starting validations on cell 7915_l of library regulators
05/19/15 16:54:29 BODY_NAME property does not exist in package 7915_L. Since backannotation will not work without this property, it will be written automatically when the cell is saved.
05/19/15 16:54:29 Completed validations on cell 7915_l of library regulators
05/19/15 16:54:51 Starting validations on cell 7915_l of library regulators
05/19/15 16:54:51 Completed validations on cell 7915_l of library regulators
05/19/15 16:55:14 Starting validations on cell 7915_l of library regulators
05/19/15 16:55:14 Completed validations on cell 7915_l of library regulators
05/19/15 16:55:17 Completed saving cell 7915_l in library regulators with errors/warnings
05/19/15 16:55:22 Project C:/Users/QGPWindowsVB/Documents/ANUSTART/tubii_tk2.cpm is closed.

tubii_tk2.cpm
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LOADING design file

2
worklib/baseline_buffer/sch_1/baseline_buffer.xcon,1
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@ -5,7 +5,7 @@
<schemaVersion>16.6</schemaVersion>
<creatorTool>conceptHDL</creatorTool>
<modifierTool>conceptHDL</modifierTool>
<modificationTime>2015-05-18T18:44:28</modificationTime>
<modificationTime>2015-05-19T16:43:15</modificationTime>
<savedLibrary>tubii_tk2_lib</savedLibrary>
</header>
<designs>

2
worklib/baseline_buffer/sch_1/baseline_buffer.xcon,2
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@ -5,7 +5,7 @@
<schemaVersion>16.6</schemaVersion>
<creatorTool>conceptHDL</creatorTool>
<modifierTool>conceptHDL</modifierTool>
<modificationTime>2015-05-18T16:17:37</modificationTime>
<modificationTime>2015-05-19T15:06:52</modificationTime>
<savedLibrary>tubii_tk2_lib</savedLibrary>
</header>
<designs>

2
worklib/baseline_buffer/sch_1/baseline_buffer.xcon,3
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@ -5,7 +5,7 @@
<schemaVersion>16.6</schemaVersion>
<creatorTool>conceptHDL</creatorTool>
<modifierTool>conceptHDL</modifierTool>
<modificationTime>2015-05-18T14:55:21</modificationTime>
<modificationTime>2015-05-18T18:44:28</modificationTime>
<savedLibrary>tubii_tk2_lib</savedLibrary>
</header>
<designs>

4
worklib/caen_analog_coms/sch_1/caen_analog_coms.con
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@ -8,8 +8,8 @@
(design "caen_analog_coms"
(lastIds
(lastInstanceId 33)
(lastNetId 240)
(lastInstTermId 2699)
(lastNetId 246)
(lastInstTermId 2785)
)
(cells
("S2" "caen_buffer" "tubii_tk2_lib" "sym_1"

6
worklib/caen_analog_coms/sch_1/caen_analog_coms.xcon,1
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@ -5,15 +5,15 @@
<schemaVersion>16.6</schemaVersion>
<creatorTool>conceptHDL</creatorTool>
<modifierTool>conceptHDL</modifierTool>
<modificationTime>2015-05-18T18:43:54</modificationTime>
<modificationTime>2015-05-19T16:42:46</modificationTime>
<savedLibrary>tubii_tk2_lib</savedLibrary>
</header>
<designs>
<design schemaType="nameBased" name="caen_analog_coms" view="sch_1">
<lastids>
<instanceid>33</instanceid>
<netid>237</netid>
<insttermid>2656</insttermid>
<netid>243</netid>
<insttermid>2742</insttermid>
</lastids>
<cells>
<cell>

6
worklib/caen_analog_coms/sch_1/caen_analog_coms.xcon,2
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@ -5,15 +5,15 @@
<schemaVersion>16.6</schemaVersion>
<creatorTool>conceptHDL</creatorTool>
<modifierTool>conceptHDL</modifierTool>
<modificationTime>2015-05-18T16:17:07</modificationTime>
<modificationTime>2015-05-19T15:06:23</modificationTime>
<savedLibrary>tubii_tk2_lib</savedLibrary>
</header>
<designs>
<design schemaType="nameBased" name="caen_analog_coms" view="sch_1">
<lastids>
<instanceid>33</instanceid>
<netid>234</netid>
<insttermid>2613</insttermid>
<netid>240</netid>
<insttermid>2699</insttermid>
</lastids>
<cells>
<cell>

6
worklib/caen_analog_coms/sch_1/caen_analog_coms.xcon,3
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@ -5,15 +5,15 @@
<schemaVersion>16.6</schemaVersion>
<creatorTool>conceptHDL</creatorTool>
<modifierTool>conceptHDL</modifierTool>
<modificationTime>2015-05-18T14:54:53</modificationTime>
<modificationTime>2015-05-18T18:43:54</modificationTime>
<savedLibrary>tubii_tk2_lib</savedLibrary>
</header>
<designs>
<design schemaType="nameBased" name="caen_analog_coms" view="sch_1">
<lastids>
<instanceid>33</instanceid>
<netid>231</netid>
<insttermid>2570</insttermid>
<netid>237</netid>
<insttermid>2656</insttermid>
</lastids>
<cells>
<cell>

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