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adw
|
Finished layout and such for new regulator (hope it works
|
2015-05-29 18:36:27 -04:00 |
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cdssetup
|
Made some rooms and layed them out
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2015-03-07 23:39:19 -05:00 |
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Documentation
|
Added documentation
|
2016-01-26 18:51:25 -05:00 |
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Parts
|
Went through each part to make BOM better
|
2015-06-04 19:44:13 -04:00 |
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signoise.run
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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temp
|
Bookkeeping update, no real changes
|
2015-09-07 11:41:52 -04:00 |
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worklib
|
Added documentation
|
2016-01-26 18:51:25 -05:00 |
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allegro_P00416.6_AllegroMiniDump.dmp
|
Routed unnused mz ribbons
|
2015-05-28 02:12:18 -04:00 |
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cds.lib
|
Initial Commit. Created Hierchy Blocks
|
2015-02-27 19:09:38 -05:00 |
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extract.log
|
Commiting here b/c synching isn't changing layout...needs to be fixed
|
2015-05-12 19:56:40 -04:00 |
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Finished3D.png
|
Added some screenshots
|
2015-04-23 15:31:38 -04:00 |
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FinishedLayout.png
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Added some screenshots
|
2015-04-23 15:31:38 -04:00 |
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netlist.txt
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Made rooms have 'soft' boundaries
|
2015-05-11 14:15:36 -04:00 |
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pad_designer.jrl
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Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
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PortsList.txt
|
Did layout for Baseline_Buffer and added package to hct123
|
2015-03-07 22:33:10 -05:00 |
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refcds.lib
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Initial Commit. Created Hierchy Blocks
|
2015-02-27 19:09:38 -05:00 |
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tubii_tk2.cpm
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Bookkeeping update, no real changes
|
2015-09-07 11:41:52 -04:00 |
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TubiiPCB_V6.SAV
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Routed unnused mz ribbons
|
2015-05-28 02:12:18 -04:00 |
