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check
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Finished all layout crap. Added Neutrino Atlas
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2015-05-31 17:16:36 -04:00 |
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xxnedtmp
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Working on MTCA_MIMICS
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2015-03-01 00:26:53 -05:00 |
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xxnedtmp1
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Created Fault Detection schem and CAEN anal stuff
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2015-03-02 01:10:23 -05:00 |
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xxnedtmp2
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Created Fault Detection schem and CAEN anal stuff
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2015-03-02 01:10:23 -05:00 |
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xxnedtmp3
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Started translation schems. Did TTL<->ECL already
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2015-03-04 12:05:45 -05:00 |
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xxnedtmp4
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Made Translation Ports
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2015-03-06 14:06:33 -05:00 |
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xxnedtmp5
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Did layout for Powers & ELLIE a bit
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2015-03-23 18:18:56 -04:00 |
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xxnedtmp6
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Book keeping commit before beging CAEN_ANAL module
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2015-03-23 18:36:03 -04:00 |
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xxnedtmp7
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Made VREF5M block in CAEN ANAL
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2015-03-25 11:38:44 -04:00 |
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xxnedtmp8
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Deleted CAEN_ANAL stuff, redid ANAL Trace only
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2015-03-25 19:53:17 -04:00 |
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xxnedtmp9
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Did routing of analog trace for CAEN_BUF
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2015-03-26 15:59:27 -04:00 |
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xxnedtmp10
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Save before start messing with CMGR
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2015-04-02 16:35:48 -04:00 |
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xxnedtmp11
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Save before start messing with CMGR
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2015-04-02 16:35:48 -04:00 |
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xxnedtmp12
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Connected SEL_LO* and GT_DELAYS
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2015-04-03 19:32:21 -04:00 |
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xxnedtmp13
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Moved connections mentioned in previous commit
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2015-04-06 17:45:06 -04:00 |
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xxnedtmp14
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Rearranging things for new smaller parts
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2015-04-06 20:18:40 -04:00 |
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xxnedtmp15
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Placed MTCA_MIMIC and routed much of it.
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2015-04-16 16:00:01 -04:00 |
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xxnedtmp16
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Placed MTCA_MIMIC and routed much of it.
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2015-04-16 16:00:01 -04:00 |
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xxnedtmp17
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Replaced a cap and placed a missed resistor
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2015-04-18 15:48:07 -04:00 |
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xxnedtmp18
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Commit before I fuckup MUXer entierly
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2015-04-22 23:50:39 -04:00 |
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xxnedtmp19
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Finished up nearly all the routing.
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2015-04-23 05:55:57 -04:00 |
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xxnedtmp20
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Made rooms have 'soft' boundaries
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2015-05-11 14:15:36 -04:00 |
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xxnedtmp21
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Changed planes for POWER and added LVDS terminating res
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2015-05-15 14:44:54 -04:00 |
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xxnedtmp22
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Fixed the bug a net named jx1_se_) caused it
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2015-05-13 14:28:21 -04:00 |
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xxnedtmp23
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Changed planes for POWER and added LVDS terminating res
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2015-05-15 14:44:54 -04:00 |
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xxnedtmp24
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Changed planes for POWER and added LVDS terminating res
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2015-05-15 14:44:54 -04:00 |
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xxnedtmp25
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Added Block for fan connections (layout too)
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2015-05-18 13:49:04 -04:00 |
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xxnedtmp26
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Changed mux so enable connects to MZ. Made button corners only
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2015-05-26 19:37:14 -04:00 |
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xxnedtmp27
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Did schem layout & routing for remaining buffers
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2015-05-28 00:01:47 -04:00 |
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xxnedtmp28
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Finished layout and such for new regulator (hope it works
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2015-05-29 18:36:27 -04:00 |
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xxnedtmp29
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Added tp to vccio
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2015-05-31 17:41:36 -04:00 |
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xxnedtmp30
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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xxnedtmp31
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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xxnedtmp32
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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xxnedtmp33
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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xxnedtmp34
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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xxnedtmp35
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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.log
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Initial Commit. Created Hierchy Blocks
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2015-02-27 19:09:38 -05:00 |
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ConCM.log
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Did (most of) Gt Delays. Changed some parts
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2015-02-28 01:58:57 -05:00 |
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back_ports.sym_1.mkr
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Added Unnused MZ ports thing
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2015-05-28 01:20:24 -04:00 |
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backannotate.log
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Routed unnused mz ribbons
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2015-05-28 02:12:18 -04:00 |
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caen_coms.sym_1.mkr
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Added GT_TTL_OUT to schematic
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2015-05-18 16:11:03 -04:00 |
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caen_dig_coms.sym_1.mkr
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Added GT_TTL_OUT to schematic
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2015-05-18 16:11:03 -04:00 |
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cfg_package.log
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Initial Commit. Created Hierchy Blocks
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2015-02-27 19:09:38 -05:00 |
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cfg_pic.log
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Initial Commit. Created Hierchy Blocks
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2015-02-27 19:09:38 -05:00 |
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cfg_verilog.log
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Initial Commit. Created Hierchy Blocks
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2015-02-27 19:09:38 -05:00 |
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cfg_vhdl.log
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Initial Commit. Created Hierchy Blocks
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2015-02-27 19:09:38 -05:00 |
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change_clks.sym_1.mkr
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Finished CLK change over schem
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2015-03-03 16:36:17 -05:00 |
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clock_ports.sch_1.mkr
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Routed the last route
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2015-04-23 11:29:06 -04:00 |
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clocks.sym_1.mkr
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Changed planes for POWER and added LVDS terminating res
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2015-05-15 14:44:54 -04:00 |
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cmdifffeedback.log
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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cmdifflogical.log
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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concept_backannotate.scr
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Layout & Routed Ext Trig
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2015-04-09 16:19:36 -04:00 |
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csdirect.log
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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default_clk_sel.sym_1.mkr
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Changed planes for POWER and added LVDS terminating res
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2015-05-15 14:44:54 -04:00 |
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ecl_translation.sym_1.mkr
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Began connecting wires
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2015-03-05 13:17:52 -05:00 |
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ellie_coms.sym_1.mkr
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More Wiring. Gotta decide on some design stuff
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2015-03-05 19:56:05 -05:00 |
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ext_trigs.sym_1.mkr
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Made ext trig in and Ellie stuff and wiring
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2015-03-05 18:36:20 -05:00 |
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front_ports.sym_1.mkr
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Added GT_TTL_OUT to schematic
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2015-05-18 16:11:03 -04:00 |
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general_utilities_ports.sym_1.mkr
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Routed the last route
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2015-04-23 11:29:06 -04:00 |
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genview.log
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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gt_delays.sym_1.mkr
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Made ext trig in and Ellie stuff and wiring
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2015-03-05 18:36:20 -05:00 |
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hdldir.log
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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lo_gen.sym_1.mkr
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Made ext trig in and Ellie stuff and wiring
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2015-03-05 18:36:20 -05:00 |
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lvds_ecl.sch_1.mkr
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Worked on translation schems and...
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2015-03-04 18:45:16 -05:00 |
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microzed_module.sch_1.mkr
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Finished all layout crap. Added Neutrino Atlas
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2015-05-31 17:16:36 -04:00 |
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microzed_module.sym_1.mkr
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Finshed ports and made a mess out of doing the MZ
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2015-03-07 18:10:30 -05:00 |
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mkdefcfg.log
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Initial Commit. Created Hierchy Blocks
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2015-02-27 19:09:38 -05:00 |
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nconcept.log
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Did (some of the) layout for fixxes and power solution
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2015-05-28 19:20:49 -04:00 |
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newgenasym.log
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Initial Commit. Created Hierchy Blocks
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2015-02-27 19:09:38 -05:00 |
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packagerxl.bat
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Fixed things in schem (I think)
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2015-05-28 17:09:32 -04:00 |
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partmgr.log
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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pm.log
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Improved readability and added mounting holes
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2015-05-03 19:09:48 -04:00 |
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pm.log,1
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Improved readability and added mounting holes
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2015-05-03 19:09:48 -04:00 |
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pm.log,2
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Fixed the bug a net named jx1_se_) caused it
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2015-05-13 14:28:21 -04:00 |
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secErr.out
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Made rooms have 'soft' boundaries
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2015-05-11 14:15:36 -04:00 |
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select_lo_src.sym_1.mkr
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Made ext trig in and Ellie stuff and wiring
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2015-03-05 18:36:20 -05:00 |
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sessionlog.txt
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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translation.sch_1.mkr
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Worked on translation schems and...
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2015-03-04 18:45:16 -05:00 |
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translation.sym_1.mkr
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Changed Translation block to Translation_ECL
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2015-03-04 19:07:57 -05:00 |
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trnslation.sch_1.mkr
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Changed Translation block to Translation_ECL
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2015-03-04 19:07:57 -05:00 |
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ttl_ecl.sch_1.mkr
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Started translation schems. Did TTL<->ECL already
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2015-03-04 12:05:45 -05:00 |
bd255ca0a8