AllSpiceMirrors/Tubii_Tk2
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Tubii_Tk2/temp
History
Eric Marzec bd255ca0a8 Bookkeeping update, no real changes
2015-09-07 11:41:52 -04:00
..
check
Finished all layout crap. Added Neutrino Atlas
2015-05-31 17:16:36 -04:00
xxnedtmp
Working on MTCA_MIMICS
2015-03-01 00:26:53 -05:00
xxnedtmp1
Created Fault Detection schem and CAEN anal stuff
2015-03-02 01:10:23 -05:00
xxnedtmp2
Created Fault Detection schem and CAEN anal stuff
2015-03-02 01:10:23 -05:00
xxnedtmp3
Started translation schems. Did TTL<->ECL already
2015-03-04 12:05:45 -05:00
xxnedtmp4
Made Translation Ports
2015-03-06 14:06:33 -05:00
xxnedtmp5
Did layout for Powers & ELLIE a bit
2015-03-23 18:18:56 -04:00
xxnedtmp6
Book keeping commit before beging CAEN_ANAL module
2015-03-23 18:36:03 -04:00
xxnedtmp7
Made VREF5M block in CAEN ANAL
2015-03-25 11:38:44 -04:00
xxnedtmp8
Deleted CAEN_ANAL stuff, redid ANAL Trace only
2015-03-25 19:53:17 -04:00
xxnedtmp9
Did routing of analog trace for CAEN_BUF
2015-03-26 15:59:27 -04:00
xxnedtmp10
Save before start messing with CMGR
2015-04-02 16:35:48 -04:00
xxnedtmp11
Save before start messing with CMGR
2015-04-02 16:35:48 -04:00
xxnedtmp12
Connected SEL_LO* and GT_DELAYS
2015-04-03 19:32:21 -04:00
xxnedtmp13
Moved connections mentioned in previous commit
2015-04-06 17:45:06 -04:00
xxnedtmp14
Rearranging things for new smaller parts
2015-04-06 20:18:40 -04:00
xxnedtmp15
Placed MTCA_MIMIC and routed much of it.
2015-04-16 16:00:01 -04:00
xxnedtmp16
Placed MTCA_MIMIC and routed much of it.
2015-04-16 16:00:01 -04:00
xxnedtmp17
Replaced a cap and placed a missed resistor
2015-04-18 15:48:07 -04:00
xxnedtmp18
Commit before I fuckup MUXer entierly
2015-04-22 23:50:39 -04:00
xxnedtmp19
Finished up nearly all the routing.
2015-04-23 05:55:57 -04:00
xxnedtmp20
Made rooms have 'soft' boundaries
2015-05-11 14:15:36 -04:00
xxnedtmp21
Changed planes for POWER and added LVDS terminating res
2015-05-15 14:44:54 -04:00
xxnedtmp22
Fixed the bug a net named jx1_se_) caused it
2015-05-13 14:28:21 -04:00
xxnedtmp23
Changed planes for POWER and added LVDS terminating res
2015-05-15 14:44:54 -04:00
xxnedtmp24
Changed planes for POWER and added LVDS terminating res
2015-05-15 14:44:54 -04:00
xxnedtmp25
Added Block for fan connections (layout too)
2015-05-18 13:49:04 -04:00
xxnedtmp26
Changed mux so enable connects to MZ. Made button corners only
2015-05-26 19:37:14 -04:00
xxnedtmp27
Did schem layout & routing for remaining buffers
2015-05-28 00:01:47 -04:00
xxnedtmp28
Finished layout and such for new regulator (hope it works
2015-05-29 18:36:27 -04:00
xxnedtmp29
Added tp to vccio
2015-05-31 17:41:36 -04:00
xxnedtmp30
Added a note for d6r10 push button
2015-06-08 16:53:59 -04:00
xxnedtmp31
Bookkeeping update, no real changes
2015-09-07 11:41:52 -04:00
xxnedtmp32
Bookkeeping update, no real changes
2015-09-07 11:41:52 -04:00
xxnedtmp33
Bookkeeping update, no real changes
2015-09-07 11:41:52 -04:00
xxnedtmp34
Bookkeeping update, no real changes
2015-09-07 11:41:52 -04:00
xxnedtmp35
Bookkeeping update, no real changes
2015-09-07 11:41:52 -04:00
.log
Initial Commit. Created Hierchy Blocks
2015-02-27 19:09:38 -05:00
back_ports.sym_1.mkr
Added Unnused MZ ports thing
2015-05-28 01:20:24 -04:00
backannotate.log
Routed unnused mz ribbons
2015-05-28 02:12:18 -04:00
caen_coms.sym_1.mkr
Added GT_TTL_OUT to schematic
2015-05-18 16:11:03 -04:00
caen_dig_coms.sym_1.mkr
Added GT_TTL_OUT to schematic
2015-05-18 16:11:03 -04:00
cfg_package.log
Initial Commit. Created Hierchy Blocks
2015-02-27 19:09:38 -05:00
cfg_pic.log
Initial Commit. Created Hierchy Blocks
2015-02-27 19:09:38 -05:00
cfg_verilog.log
Initial Commit. Created Hierchy Blocks
2015-02-27 19:09:38 -05:00
cfg_vhdl.log
Initial Commit. Created Hierchy Blocks
2015-02-27 19:09:38 -05:00
change_clks.sym_1.mkr
Finished CLK change over schem
2015-03-03 16:36:17 -05:00
clock_ports.sch_1.mkr
Routed the last route
2015-04-23 11:29:06 -04:00
clocks.sym_1.mkr
Changed planes for POWER and added LVDS terminating res
2015-05-15 14:44:54 -04:00
cmdifffeedback.log
Commiting here b/c synching isn't changing layout...needs to be fixed
2015-05-12 19:56:40 -04:00
cmdifflogical.log
Commiting here b/c synching isn't changing layout...needs to be fixed
2015-05-12 19:56:40 -04:00
concept_backannotate.scr
Layout & Routed Ext Trig
2015-04-09 16:19:36 -04:00
ConCM.log
Did (most of) Gt Delays. Changed some parts
2015-02-28 01:58:57 -05:00
csdirect.log
Added a note for d6r10 push button
2015-06-08 16:53:59 -04:00
default_clk_sel.sym_1.mkr
Changed planes for POWER and added LVDS terminating res
2015-05-15 14:44:54 -04:00
ecl_translation.sym_1.mkr
Began connecting wires
2015-03-05 13:17:52 -05:00
ellie_coms.sym_1.mkr
More Wiring. Gotta decide on some design stuff
2015-03-05 19:56:05 -05:00
ext_trigs.sym_1.mkr
Made ext trig in and Ellie stuff and wiring
2015-03-05 18:36:20 -05:00
front_ports.sym_1.mkr
Added GT_TTL_OUT to schematic
2015-05-18 16:11:03 -04:00
general_utilities_ports.sym_1.mkr
Routed the last route
2015-04-23 11:29:06 -04:00
genview.log
Commiting here b/c synching isn't changing layout...needs to be fixed
2015-05-12 19:56:40 -04:00
gt_delays.sym_1.mkr
Made ext trig in and Ellie stuff and wiring
2015-03-05 18:36:20 -05:00
hdldir.log
Commiting here b/c synching isn't changing layout...needs to be fixed
2015-05-12 19:56:40 -04:00
lo_gen.sym_1.mkr
Made ext trig in and Ellie stuff and wiring
2015-03-05 18:36:20 -05:00
lvds_ecl.sch_1.mkr
Worked on translation schems and...
2015-03-04 18:45:16 -05:00
microzed_module.sch_1.mkr
Finished all layout crap. Added Neutrino Atlas
2015-05-31 17:16:36 -04:00
microzed_module.sym_1.mkr
Finshed ports and made a mess out of doing the MZ
2015-03-07 18:10:30 -05:00
mkdefcfg.log
Initial Commit. Created Hierchy Blocks
2015-02-27 19:09:38 -05:00
nconcept.log
Did (some of the) layout for fixxes and power solution
2015-05-28 19:20:49 -04:00
newgenasym.log
Initial Commit. Created Hierchy Blocks
2015-02-27 19:09:38 -05:00
packagerxl.bat
Fixed things in schem (I think)
2015-05-28 17:09:32 -04:00
partmgr.log
Commiting here b/c synching isn't changing layout...needs to be fixed
2015-05-12 19:56:40 -04:00
pm.log
Improved readability and added mounting holes
2015-05-03 19:09:48 -04:00
pm.log,1
Improved readability and added mounting holes
2015-05-03 19:09:48 -04:00
pm.log,2
Fixed the bug a net named jx1_se_) caused it
2015-05-13 14:28:21 -04:00
secErr.out
Made rooms have 'soft' boundaries
2015-05-11 14:15:36 -04:00
select_lo_src.sym_1.mkr
Made ext trig in and Ellie stuff and wiring
2015-03-05 18:36:20 -05:00
sessionlog.txt
Bookkeeping update, no real changes
2015-09-07 11:41:52 -04:00
translation.sch_1.mkr
Worked on translation schems and...
2015-03-04 18:45:16 -05:00
translation.sym_1.mkr
Changed Translation block to Translation_ECL
2015-03-04 19:07:57 -05:00
trnslation.sch_1.mkr
Changed Translation block to Translation_ECL
2015-03-04 19:07:57 -05:00
ttl_ecl.sch_1.mkr
Started translation schems. Did TTL<->ECL already
2015-03-04 12:05:45 -05:00