18 lines
265 B
Verilog
18 lines
265 B
Verilog
// generated by newgenasym Thu Jun 04 18:01:30 2015
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module \100el05 (in1, \in1* , in2, \in2* , out, \out* );
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input in1;
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input \in1* ;
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input in2;
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input \in2* ;
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output out;
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output \out* ;
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initial
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begin
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end
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endmodule
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